Re: [V5, 1/6] i2c: qup: Change qup_wait_writeready function to use for all timeouts

[Andy Gross]

On Tue, Nov 17, 2015 at 05:15:22PM +0530, Sricharan R wrote:
> qup_wait_writeready waits only on a output fifo empty event.
> Change the same function to accept the event and data length
> to wait as parameters. This way the same function can be used for
> timeouts in other places as well.
> 
> Signed-off-by: Sricharan R <sricha...@codeaurora.org>

Looks good to me.

Reviewed-by: Andy Gross <andy.gr...@linaro.org>
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Re: [PATCH 4/4] dt: binding: Add Qualcomm wcn36xx WiFi binding

[Andy Gross]

On Sun, Dec 27, 2015 at 05:34:27PM -0800, Bjorn Andersson wrote:
> Add binding representing the Qualcomm wcn3620/60/80 WiFi block.
> 
> Signed-off-by: Bjorn Andersson <bjorn.anders...@sonymobile.com>
> ---



> +
> +- qcom,wcnss-mmio:
> + Usage: required
> + Value type: 

nit:  encoded

> + Definition: should specify base address and size of the WiFi related
> + registers of WCNSS
> +
> +- qcom,state:
> + Usage: required
> + Value type: 
> + Definition: should specify the tx-enable and tx-ring-empty state
> + references
> +



Otherwise looks good.

Reviewed-by: Andy Gross <andy.gr...@linaro.org>
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Re: [PATCH v2 3/4] dt-binding: remoteproc: Introduce Qualcomm WCNSS loader binding

[Andy Gross]

On Sun, Dec 27, 2015 at 05:15:45PM -0800, Bjorn Andersson wrote:
> The document defines the binding for a component that loads firmware for
> and boots the Qualcomm WCNSS core.
> 
> Signed-off-by: Bjorn Andersson <bjorn.anders...@sonymobile.com>
> ---

Acked-by: Andy Gross <andy.gr...@linaro.org>
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Re: next-20151222 build: 3 failures 13 warnings (next-20151222)

[Andy Gross]

On Tue, Dec 22, 2015 at 12:22:28PM +, Mark Brown wrote:
> On Tue, Dec 22, 2015 at 08:57:20AM +, Build bot for Mark Brown wrote:
> 
> Today's linux-next fails to link an arm64 allmodconfig due to:
> 
> > ERROR: "of_irq_count" [drivers/pinctrl/qcom/pinctrl-ssbi-mpp.ko] undefined!
> > ERROR: "of_irq_count" [drivers/pinctrl/qcom/pinctrl-ssbi-gpio.ko] undefined!
> > ERROR: "of_irq_count" [drivers/pinctrl/qcom/pinctrl-spmi-mpp.ko] undefined!
> > ERROR: "of_irq_count" [drivers/pinctrl/qcom/pinctrl-spmi-gpio.ko] undefined!
> 
> which are caused by ab4256cfeab91569 (pinctrl: qcom: pmic-gpio/mpp:
> of_irq_count() == npins) which adds uses of irq_of_count() but that is
> not exported so can't be used in modules.  I've just sent a patch adding
> the export.

Thanks for fixing that Mark.  I had seen it in the pinctrl builds but hadn't
gotten the screen time to send in a fix.

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Re: [PATCH v4 2/3] power: qcom_smbb: Add otg regulator for control of vbus

[Andy Gross]

On Tue, Dec 15, 2015 at 11:52:11AM -0800, Tim Bird wrote:
> Add a regulator to control the OTG chargepath switch.  This
> is used by USB code to control VBUS direction - out for host mode
> on the OTG port, and in for charging mode.
> 
> Signed-off-by: Tim Bird <tim.b...@sonymobile.com>
> ---
> Changes since v3:
>  - changed DT node name to otg-vbus
>  - removed fixed-voltage setup from otg regulator rdesc
> Changes since v1:
>  - changed name of supply to remove underscores
> ---

Reviewed-by: Andy Gross <andy.gr...@linaro.org>
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Re: [PATCH v4 1/3] dt-binding: power: Add otg regulator binding

[Andy Gross]

On Tue, Dec 15, 2015 at 11:52:10AM -0800, Tim Bird wrote:
> Add a binding for the regulator which controls the OTG chargepath switch.
> The OTG switch gets its power from pm8941_5vs1, and that should be
> expressed as a usb_otg_in-supply property in the DT node for the
> charger driver.  The regulator name is "otg-vbus".
> 
> Signed-off-by: Tim Bird <tim.b...@sonymobile.com>
> ---
> Changes since v3
>  - switch supply name to have underscores instead of dashes
>- (switched back to match the name used in data sheets)
>  - switch regulator node name to otg-vbus
> Changes since v1
>  - switch supply name to have dashes instead of underscores
>  - remove superfluous DT explanations in the otg node description

Reviewed-by: Andy Gross <andy.gr...@linaro.org>
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Re: [PATCH 4/4] arm: dts: apq8064: add shared memory node

[Andy Gross]

On Fri, Dec 11, 2015 at 06:33:09PM +, Srinivas Kandagatla wrote:
> This patch adds support to qcom,smem device.
> 
> Signed-off-by: Srinivas Kandagatla 
> ---
>  arch/arm/boot/dts/qcom-apq8064.dtsi | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi 
> b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 829028a..40dd6b4 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -682,5 +682,11 @@
>   #hwlock-cells = <1>;
>   };
>  
> + smem {
> + compatible = "qcom,smem";
> + memory-region = <>;
> + hwlocks = <_mutex 3>;
> + };
> +

smem needs to be outside the soc as there is no reg entry.

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Re: [PATCH 3/4] arm: dts: apq8064: add hwspinlock nodes

[Andy Gross]

On Fri, Dec 11, 2015 at 06:32:11PM +, Srinivas Kandagatla wrote:
> This patch adds support hwspinlock devicetree node.
> 
> Signed-off-by: Srinivas Kandagatla 


Looks fine to me.  Thanks for the patch.
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Re: [PATCH 1/4] ARM: dts: qcom: apq8064-ifc6410 Use hardware flow control for GSBI6

[Andy Gross]

On Fri, Dec 11, 2015 at 06:29:58PM +, Srinivas Kandagatla wrote:
> From: "Ivan T. Ivanov" 
> 
> GSBI6 UART module is connected to BT chip, which uses
> hardware flow control lines. Enable them on SoC side.
> 
> Signed-off-by: Ivan T. Ivanov 

Looks fine to me. Thanks for the patch.
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Re: [PATCH 2/4] arm: dts: apq8064: add shared memory into dt reserved-memory

[Andy Gross]

On Fri, Dec 11, 2015 at 06:31:47PM +, Srinivas Kandagatla wrote:
> This patch adds the shared memory in the Device tree reserved memory
> list so that kernel would not map it as normal memory.
> 
> Signed-off-by: Srinivas Kandagatla 

Looks fine to me.
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Re: [v3,1/6] pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support

[Andy Gross]

On Thu, Nov 19, 2015 at 05:19:28PM -0600, Matthew McClintock wrote:
> From: Varadarajan Narayanan <var...@codeaurora.org>
> 
> Add pinctrl driver support for IPQ4019 platform
> 
> Signed-off-by: Sricharan R <sricha...@codeaurora.org>
> Signed-off-by: Mathieu Olivari <math...@codeaurora.org>
> Signed-off-by: Varadarajan Narayanan <var...@codeaurora.org>
> Signed-off-by: Matthew McClintock <mmccl...@codeaurora.org>
> Acked-by: Rob Herring <r...@kernel.org>

Looks good.  Much better than before.

Reviewed-by: Andy Gross <andy.gr...@linaro.org>

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[Patch v4 0/2] Add SMEM nodes for APQ8084 and MSM8916

[Andy Gross]

This patch set adds the SMEM nodes for the APQ8084 and MSM8916 platforms.  These
patches were originally part of:
https://lkml.org/lkml/headers/2015/9/24/561

I split these two patches out because these were the only DTS patches that
required modifications.  The rest have been accepted.  I continued to add the
previous change log for continuity sake.

Changes since v3:
- Moved smem node outside of soc and fixed up the rpm-msg-ram

Changes since v2:
- Fixed some missed review comments
- Corrected the SMD RPM example binding indentation

Changes since v1:
- Fixed various review comments
- Removed MSM8974 patches as there was already an outstanding patch

Andy Gross (2):
  arm64: dts: qcom: Add MSM8916 SMEM nodes
  arm: dts: Add APQ8084 SMEM nodes

 arch/arm/boot/dts/qcom-apq8084.dtsi   | 36 ++
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 41 +++
 2 files changed, 77 insertions(+)

-- 
1.9.1

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[Patch v4 2/2] arm: dts: Add APQ8084 SMEM nodes

[Andy Gross]

From: Andy Gross <agr...@codeaurora.org>

This patch adds all the required nodes to support SMEM on APQ8084

Signed-off-by: Andy Gross <agr...@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.anders...@sonymobile.com>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi | 36 
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi 
b/arch/arm/boot/dts/qcom-apq8084.dtsi
index fcffeca..3d3b394 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -10,6 +10,17 @@
compatible = "qcom,apq8084";
interrupt-parent = <>;
 
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   smem_mem: smem_region@fa0 {
+   reg = <0xfa0 0x20>;
+   no-map;
+   };
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -89,6 +100,15 @@
clock-frequency = <1920>;
};
 
+   smem {
+   compatible = "qcom,smem";
+
+   qcom,rpm-msg-ram = <_msg_ram>;
+   memory-region = <_mem>;
+
+   hwlocks = <_mutex 3>;
+   };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -225,6 +245,22 @@
reg = <0xfc40 0x4000>;
};
 
+   tcsr_mutex_regs: syscon@fd484000 {
+   compatible = "syscon";
+   reg = <0xfd484000 0x2000>;
+   };
+
+   tcsr_mutex: hwlock {
+   compatible = "qcom,tcsr-mutex";
+   syscon = <_mutex_regs 0 0x80>;
+   #hwlock-cells = <1>;
+   };
+
+   rpm_msg_ram: memory@fc428000 {
+   compatible = "qcom,rpm-msg-ram";
+   reg = <0xfc428000 0x4000>;
+   };
+
tlmm: pinctrl@fd51 {
compatible = "qcom,apq8084-pinctrl";
reg = <0xfd51 0x4000>;
-- 
1.9.1

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Re: [PATCH] MAINTAINERS: Add missing platform maintainers for dts files

[Andy Gross]

On Thu, Dec 10, 2015 at 05:38:23PM -0600, Rob Herring wrote:
> Platform dts files need to be reviewed primarily by the platform
> maintainers as dts files typically go in thru their trees. Add the missing
> paths where there are existing maintainers listed.
> 
> Signed-off-by: Rob Herring <r...@kernel.org>
> ---



>  ARM/Marvell Dove/MV78xx0/Orion SOC support
> @@ -1406,7 +1415,9 @@ M:  David Brown <dav...@codeaurora.org>
>  L:   linux-arm-...@vger.kernel.org
>  L:   linux-...@vger.kernel.org
>  S:   Maintained
> +F:   arch/arm/boot/dts/qcom-*
>  F:   arch/arm/mach-qcom/
> +F:   arch/arm64/boot/dts/qcom/*
>  F:   drivers/soc/qcom/
>  F:   drivers/tty/serial/msm_serial.h
>  F:   drivers/tty/serial/msm_serial.c



for QCOM,

Acked-by: Andy Gross <agr...@codeaurora.org>
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[Patch v4 1/2] arm64: dts: qcom: Add MSM8916 SMEM nodes

[Andy Gross]

From: Andy Gross <agr...@codeaurora.org>

This patch adds the nodes necessary to support the SMEM driver on MSM8916
platforms.

Signed-off-by: Andy Gross <agr...@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.anders...@sonymobile.com>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 41 +++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi 
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 8d184ff..fe4541f 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -37,6 +37,22 @@
reg = <0 0 0 0>;
};
 
+   reserved-memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   reserve_aligned@8600 {
+   reg = <0x0 0x8600 0x0 0x030>;
+   no-map;
+   };
+
+   smem_mem: smem_region@8630 {
+   reg = <0x0 0x8630 0x0 0x010>;
+   no-map;
+   };
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -74,6 +90,15 @@
 ;
};
 
+   smem {
+   compatible = "qcom,smem";
+
+   memory-region = <_mem>;
+   qcom,rpm-msg-ram = <_msg_ram>;
+
+   hwlocks = <_mutex 3>;
+   };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -103,6 +128,22 @@
reg = <0x180 0x8>;
};
 
+   tcsr_mutex_regs: syscon@1905000 {
+   compatible = "syscon";
+   reg = <0x1905000 0x2>;
+   };
+
+   tcsr_mutex: hwlock {
+   compatible = "qcom,tcsr-mutex";
+   syscon = <_mutex_regs 0 0x1000>;
+   #hwlock-cells = <1>;
+   };
+
+   rpm_msg_ram: memory@6 {
+   compatible = "qcom,rpm-msg-ram";
+   reg = <0x6 0x8000>;
+   };
+
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
-- 
1.9.1

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Re: [PATCH 3/4] dmaengine: qcom_bam_dma: use correct pipe FIFO size

[Andy Gross]

On Wed, Dec 02, 2015 at 06:44:11PM +0200, Stanimir Varbanov wrote:
> On 12/01/2015 07:23 PM, Andy Gross wrote:
> > On Tue, Dec 01, 2015 at 11:14:58AM +0200, Stanimir Varbanov wrote:
> >> The pipe fifo size register must instruct the bam hw
> >> how many hw descriptors can be pushed to fifo. Currently
> >> we isntruct the hw with 32KBytes but wrap the tail in
> >> bam_start_dma in BAM_P_EVNT_REG on 4095 i.e. 32760. This
> >> leads to stalled transactions when the tail wraps.
> >>
> >> Fix this by use the correct fifo size in BAM_P_FIFO_SIZES
> >> register i.e. 32K - 8.
> >>
> >> Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>
> >> ---
> >>  drivers/dma/qcom_bam_dma.c |2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
> >> index 0f06f3b7a72b..6d290de9ab2b 100644
> >> --- a/drivers/dma/qcom_bam_dma.c
> >> +++ b/drivers/dma/qcom_bam_dma.c
> >> @@ -458,7 +458,7 @@ static void bam_chan_init_hw(struct bam_chan *bchan,
> >> */
> >>writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
> >>bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
> >> -  writel_relaxed(BAM_DESC_FIFO_SIZE,
> >> +  writel_relaxed(BAM_MAX_DATA_SIZE,
> >>bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));
> > 
> > This is just using the #define.  That is ok, but if you use this instead of 
> > the
> > BAM_P_FIFO_SIZES then you need to fix your comment.  Or actually use the
> > register value otherwise looks fine.
> 
> I did not follow your comment, but the intension of the patch is to set
> the proper FIFO size in BAM_P_FIFO_SIZES register, i.e. 32K - 8.

Sorry, I mixed up the usage and was thinking there was something you read out
that told you the size.  That's not how it works, unfortunately.  The
MAX_DATA_SIZE is fine, but the name is a little misleading.  Perhaps just
BAM_FIFO_SIZE?


Regards,

Andy
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Re: [PATCH 3/4] dmaengine: qcom_bam_dma: use correct pipe FIFO size

[Andy Gross]

On Tue, Dec 01, 2015 at 11:14:58AM +0200, Stanimir Varbanov wrote:
> The pipe fifo size register must instruct the bam hw
> how many hw descriptors can be pushed to fifo. Currently
> we isntruct the hw with 32KBytes but wrap the tail in
> bam_start_dma in BAM_P_EVNT_REG on 4095 i.e. 32760. This
> leads to stalled transactions when the tail wraps.
> 
> Fix this by use the correct fifo size in BAM_P_FIFO_SIZES
> register i.e. 32K - 8.
> 
> Signed-off-by: Stanimir Varbanov 
> ---
>  drivers/dma/qcom_bam_dma.c |2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
> index 0f06f3b7a72b..6d290de9ab2b 100644
> --- a/drivers/dma/qcom_bam_dma.c
> +++ b/drivers/dma/qcom_bam_dma.c
> @@ -458,7 +458,7 @@ static void bam_chan_init_hw(struct bam_chan *bchan,
>*/
>   writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
>   bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
> - writel_relaxed(BAM_DESC_FIFO_SIZE,
> + writel_relaxed(BAM_MAX_DATA_SIZE,
>   bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));

This is just using the #define.  That is ok, but if you use this instead of the
BAM_P_FIFO_SIZES then you need to fix your comment.  Or actually use the
register value otherwise looks fine.

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Re: [PATCH 3/4] dmaengine: qcom_bam_dma: use correct pipe FIFO size

[Andy Gross]

On Tue, Dec 01, 2015 at 11:28:32AM +0100, Arnd Bergmann wrote:
> On Tuesday 01 December 2015 11:14:58 Stanimir Varbanov wrote:
> > 
> > diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
> > index 0f06f3b7a72b..6d290de9ab2b 100644
> > --- a/drivers/dma/qcom_bam_dma.c
> > +++ b/drivers/dma/qcom_bam_dma.c
> > @@ -458,7 +458,7 @@ static void bam_chan_init_hw(struct bam_chan *bchan,
> >  */
> > writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
> > bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
> > -   writel_relaxed(BAM_DESC_FIFO_SIZE,
> > +   writel_relaxed(BAM_MAX_DATA_SIZE,
> > bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));
> >  
> > /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */
> 
> I'm looking at that now and fail to see why these have to use 
> writel_relaxed().

At some point I believe I got a comment about using (readl/writel)_relaxed
instead of readl/writel.  So I used these instead.  Has the wind direction
changed?  =)

Using the readl/writel is nice w.r.t. having the implicit barriers, especially
with the funky 1K boundary on reordering of operations that can occur on Kraits.
This can hit you on accesses even within the same IP block.
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Re: [PATCH 2/4] dmaengine: qcom_bam_dma: clear BAM interrupt only if it is rised

[Andy Gross]

On Tue, Dec 01, 2015 at 11:14:57AM +0200, Stanimir Varbanov wrote:
> Currently we write BAM_IRQ_CLR register with zero even when no
> BAM_IRQ occured. This write has some bad side effects when the
> BAM instance is for the crypto engine. In case of crypto engine
> some of the BAM registers are xPU protected and they cannot be
> controlled by the driver.
> 
> Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>
> ---
>  drivers/dma/qcom_bam_dma.c |   12 
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
> index dc9da477eb69..0f06f3b7a72b 100644
> --- a/drivers/dma/qcom_bam_dma.c
> +++ b/drivers/dma/qcom_bam_dma.c
> @@ -800,13 +800,17 @@ static irqreturn_t bam_dma_irq(int irq, void *data)
>   if (srcs & P_IRQ)
>   tasklet_schedule(>task);
>  
> - if (srcs & BAM_IRQ)
> + if (srcs & BAM_IRQ) {
>   clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS));
>  
> - /* don't allow reorder of the various accesses to the BAM registers */
> - mb();
> + /*
> +  * don't allow reorder of the various accesses to the BAM
> +  * registers
> +  */
> + mb();
>  
> - writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR));
> + writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR));
> + }

Looks good.  We shouldn't be accessing this unless there is actually an irq
shown in the srcs.


Thanks for catching this.


Reviewed-by: Andy Gross <agr...@codeaurora.org>
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Re: [PATCH 4/4] dmaengine: qcom_bam_dma: add controlled remotely dt property

[Andy Gross]

On Tue, Dec 01, 2015 at 11:14:59AM +0200, Stanimir Varbanov wrote:
> Some of the peripherals has bam which is controlled by remote
> processor, thus the bam dma driver must avoid register writes
> which initialise bam hw block. Those registers are protected
> from xPU block and any writes to them will lead to secure
> violation and system reboot.
> 
> Adding the contolled_remotely flag in bam driver to avoid
> not permitted register writes in bam_init function.
> 
> Signed-off-by: Stanimir Varbanov <stanimir.varba...@linaro.org>
> ---
>  .../devicetree/bindings/dma/qcom_bam_dma.txt   |2 ++
>  drivers/dma/qcom_bam_dma.c |7 +++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt 
> b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> index 1c9d48ea4914..87b6b2bf5e1e 100644
> --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> @@ -13,6 +13,8 @@ Required properties:
>  - clock-names: must contain "bam_clk" entry
>  - qcom,ee : indicates the active Execution Environment identifier (0-7) used 
> in
>the secure world.
> +- qcom,controlled-remotely : optional, indicates that the bam is controled by
> +  remote proccessor i.e. execution enviroment.

Please fix the spelling.  controlled, environment.  Otherwise looks ok.

>  
>  Example:
>  
> diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
> index 6d290de9ab2b..5dedab77180a 100644
> --- a/drivers/dma/qcom_bam_dma.c
> +++ b/drivers/dma/qcom_bam_dma.c
> @@ -387,6 +387,7 @@ struct bam_device {
>  
>   /* execution environment ID, from DT */
>   u32 ee;
> + bool controlled_remotely;
>  
>   const struct reg_offset_data *layout;
>  
> @@ -1039,6 +1040,9 @@ static int bam_init(struct bam_device *bdev)
>   val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES));
>   bdev->num_channels = val & BAM_NUM_PIPES_MASK;
>  
> + if (bdev->controlled_remotely)
> + return 0;
> +
>   /* s/w reset bam */
>   /* after reset all pipes are disabled and idle */
>   val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL));
> @@ -1126,6 +1130,9 @@ static int bam_dma_probe(struct platform_device *pdev)
>   return ret;
>   }
>  
> + bdev->controlled_remotely = of_property_read_bool(pdev->dev.of_node,
> +     "qcom,controlled-remotely");
> +
>   bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk");
>   if (IS_ERR(bdev->bamclk))
>   return PTR_ERR(bdev->bamclk);


Reviewed-by: Andy Gross <agr...@codeaurora.org>
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Re: [PATCH 1/7] ARM: dts: qcom: msm8974-honami: Define pinctrl state for blsp_uart2

[Andy Gross]

On Mon, Nov 30, 2015 at 12:19:13PM -0800, Bjorn Andersson wrote:
> On Mon, Nov 30, 2015 at 11:23 AM, Kevin Hilman  wrote:
> > On Tue, Oct 20, 2015 at 9:57 PM, Bjorn Andersson
> >  wrote:
> >> Make sure the blsp1_uart2 pins are in the correct state for the uart.
> >>
> >> Signed-off-by: Bjorn Andersson 
> >
> > kernelci.org has been detecting boot failures on my z1 since
> > next-20151120[1] and I finally got around to bisecting, which pointed
> > to this patch which is in next in the for of commit 14cd83b824aa ARM:
> > dts: qcom: msm8974-honami: Define pinctrl state for blsp_uart2
> >
> > That commit doesn't revert cleanly on top of next-20151130, but
> > manually removing the stuff added in this patch, next-20151130 boots
> > fine on the z1.
> >
> > Kevin
> >
> > [1] 
> > http://kernelci.org/boot/qcom-msm8974-sony-xperia-honami/job/next/kernel/next-20151127/defconfig/multi_v7_defconfig/lab/lab-khilman/?_id=5658061359b5140196b5fd2f
> 
> Thanks Kevin,
> 
> I did see these too. But at the same time, as far as I can see, the
> qcom_defconfig boots just fine - indicating that this particular
> commit would not be the cause.
> 
> I'll fire up some builds to figure out what's going on.

I threw the extra config options that qcom_defconfig had on it on top of my next
branch.  I hadn't seen any kernel ci runs on that yet.
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Re: [PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register

[Andy Gross]

On Fri, Nov 20, 2015 at 09:06:33AM -0600, Felipe Balbi wrote:
> 
> Hi,
> 
> Andy Gross <agr...@codeaurora.org> writes:
> > This patch adds automatic configuration of the TCSR phy mux register based 
> > on
> > the syscon-tcsr devicetree entry.  This configuration is optional, as some
> > platforms may not require the mux selection.
> >
> > Signed-off-by: Andy Gross <agr...@codeaurora.org>
> 
> just when I find a way to make a generic dwc3-of-simple.c glue layer :-p
> 
> I can, certainly drop my patches but I need more details on the syscon
> usage below.
> 
> > ---
> >  drivers/usb/dwc3/dwc3-qcom.c | 25 +
> >  1 file changed, 25 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> > index 0880260..fcf264c 100644
> > --- a/drivers/usb/dwc3/dwc3-qcom.c
> > +++ b/drivers/usb/dwc3/dwc3-qcom.c
> > @@ -17,6 +17,8 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> >  
> >  struct dwc3_qcom {
> > struct device   *dev;
> > @@ -30,6 +32,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> >  {
> > struct device_node *node = pdev->dev.of_node;
> > struct dwc3_qcom *qdwc;
> > +   struct regmap *regmap;
> > +   u32 mux_offset;
> > +   u32 mux_bit;
> > int ret;
> >  
> > qdwc = devm_kzalloc(>dev, sizeof(*qdwc), GFP_KERNEL);
> > @@ -58,6 +63,26 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> > qdwc->sleep_clk = NULL;
> > }
> >  
> > +   /* look for tcsr and if present, provision it */
> > +   regmap = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
> > +   if (!IS_ERR(regmap)) {
> > +   if (of_property_read_u32_index(node, "syscon-tcsr", 1,
> > +  _offset)) {
> > +   dev_err(qdwc->dev, "missing USB TCSR mux offset\n");
> > +   return -EINVAL;
> > +   }
> > +   if (of_property_read_u32_index(node, "syscon-tcsr", 2,
> > +  _bit)) {
> > +   dev_err(qdwc->dev, "missing USB TCSR mux bit\n");
> > +   return -EINVAL;
> > +   }
> > +
> > +   regmap_update_bits(regmap, mux_offset, BIT(mux_bit),
> > +  BIT(mux_bit));
> 
> what is tcsr and what does it ? It also seems to be optional, why's that ?
> 
> -- 
> balbi

The syscon is to set the mux selection for the phys.  Our hardware has a
steering mux between hsic and dwc3 and setting this to 1 steers the phys to the
right controller.

It is optional because not all platforms appear to have this stupidity.


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Re: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage

[Andy Gross]

On Fri, Nov 20, 2015 at 09:08:46AM -0600, Felipe Balbi wrote:
> 
> Hi,
> 
> Andy Gross <agr...@codeaurora.org> writes:
> > This patch adds documentation for the optional syscon-tcsr property in the
> > Qualcomm DWC3 node.  The syscon-tcsr specifies the register and bit used to
> > configure the TCSR USB phy mux register.
> >
> > Signed-off-by: Andy Gross <agr...@codeaurora.org>
> > ---
> >  Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt 
> > b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> > index ca164e7..dfa222d 100644
> > --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> > +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> > @@ -8,6 +8,10 @@ Required properties:
> >"core"   Master/Core clock, have to be >= 125 MHz for SS
> > operation and >= 60MHz for HS operation
> >  
> > +Optional properties:
> > +- syscon-tcsr  Specifies TCSR handle, register offset, and bit 
> > position for
> > +   configuring the phy mux setting.
> 
> oh, it's a PHY mux ? I don't think it should be part of any dwc3-* glue
> layer then. By the time we reach dwc3, the mux should be properly
> configured.
> 
> Kishon, any ideas ?
> 
> -- 
> balbi

The only issue with putting it at the phy layer is that i'd have redundant
syscon entries for each pair of phys, unless i group them somehow in dt.  The
only other issue I can think of is that in the downstream kernels, they do this
before messing with the configuration of the dwc3.  So long as the phys do their
thing before the dwc3 (phys latched before config), we're ok.



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[PATCH 3/4] ARM: dts: qcom: Add DWC3 USB support on IPQ8064

[Andy Gross]

This patch adds Qualcomm DWC3 USB nodes to device tree to enable support for the
DWC3 controller found on IPQ8064/AP148 platforms.

Signed-off-by: Andy Gross <agr...@codeaurora.org>
---
 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 24 +
 arch/arm/boot/dts/qcom-ipq8064.dtsi  | 89 
 2 files changed, 113 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts 
b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index d501382..bf1638c 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -97,5 +97,29 @@
sata@2900 {
status = "ok";
};
+
+   phy@100f8800 {
+   status = "ok";
+   };
+
+   phy@100f8830 {
+   status = "ok";
+   };
+
+   usb30@0 {
+   status = "ok";
+   };
+
+   phy@110f8800 {
+   status = "ok";
+   };
+
+   phy@110f8830 {
+   status = "ok";
+   };
+
+   usb30@1 {
+   status = "ok";
+   };
};
 };
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi 
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index fa69863..b2dcd9d 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -329,5 +329,94 @@
#reset-cells = <1>;
};
 
+   hs_phy_0: phy@100f8800 {
+   compatible = "qcom,dwc3-hs-usb-phy";
+   reg = <0x100f8800 0x30>;
+   clocks = < USB30_0_UTMI_CLK>;
+   clock-names = "ref";
+
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
+   ss_phy_0: phy@100f8830 {
+   compatible = "qcom,dwc3-ss-usb-phy";
+   reg = <0x100f8830 0x30>;
+
+   clocks = < USB30_0_MASTER_CLK>;
+   clock-names = "ref";
+
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
+   usb30@0 {
+   compatible = "qcom,dwc3";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < USB30_0_MASTER_CLK>;
+   clock-names = "core";
+
+   syscon-tcsr = < 0xb0 1>;
+
+   ranges;
+
+   status = "disabled";
+
+   dwc3@1000 {
+   compatible = "snps,dwc3";
+   reg = <0x1000 0xcd00>;
+   interrupts = <0 205 0x4>;
+   phys = <_phy_0>, <_phy_0>;
+   phy-names = "usb2-phy", "usb3-phy";
+   tx-fifo-resize;
+   dr_mode = "host";
+   };
+   };
+
+   hs_phy_1: phy@110f8800 {
+   compatible = "qcom,dwc3-hs-usb-phy";
+   reg = <0x110f8800 0x30>;
+   clocks = < USB30_1_UTMI_CLK>;
+   clock-names = "ref";
+
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
+   ss_phy_1: phy@110f8830 {
+   compatible = "qcom,dwc3-ss-usb-phy";
+   reg = <0x110f8830 0x30>;
+
+   clocks = < USB30_1_MASTER_CLK>;
+   clock-names = "ref";
+
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
+   usb30@1 {
+   compatible = "qcom,dwc3";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < USB30_1_MASTER_CLK>;
+   clock-names = "core";
+
+   syscon-tcsr = < 0xb0 0>;
+
+   ranges;
+
+   status = "disabled";
+
+   dwc3@1100 {
+   compatible = "snps,dwc3";
+   reg = <0x1100 0xcd00>;
+   interrupts = <0 110 0x4>;
+   phys

[PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register

[Andy Gross]

This patch adds automatic configuration of the TCSR phy mux register based on
the syscon-tcsr devicetree entry.  This configuration is optional, as some
platforms may not require the mux selection.

Signed-off-by: Andy Gross <agr...@codeaurora.org>
---
 drivers/usb/dwc3/dwc3-qcom.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 0880260..fcf264c 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -17,6 +17,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 struct dwc3_qcom {
struct device   *dev;
@@ -30,6 +32,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
 {
struct device_node *node = pdev->dev.of_node;
struct dwc3_qcom *qdwc;
+   struct regmap *regmap;
+   u32 mux_offset;
+   u32 mux_bit;
int ret;
 
qdwc = devm_kzalloc(>dev, sizeof(*qdwc), GFP_KERNEL);
@@ -58,6 +63,26 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
qdwc->sleep_clk = NULL;
}
 
+   /* look for tcsr and if present, provision it */
+   regmap = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
+   if (!IS_ERR(regmap)) {
+   if (of_property_read_u32_index(node, "syscon-tcsr", 1,
+  _offset)) {
+   dev_err(qdwc->dev, "missing USB TCSR mux offset\n");
+   return -EINVAL;
+   }
+   if (of_property_read_u32_index(node, "syscon-tcsr", 2,
+  _bit)) {
+   dev_err(qdwc->dev, "missing USB TCSR mux bit\n");
+   return -EINVAL;
+   }
+
+   regmap_update_bits(regmap, mux_offset, BIT(mux_bit),
+  BIT(mux_bit));
+   } else {
+   dev_info(qdwc->dev, "missing syscon tcsr entry\n");
+   }
+
ret = clk_prepare_enable(qdwc->core_clk);
if (ret) {
dev_err(qdwc->dev, "failed to enable core clock\n");
-- 
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[PATCH 1/4] phy: Add Qualcomm DWC3 HS/SS PHY driver

[Andy Gross]

This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms.  This driver uses the generic PHY framework and will
interact with the DWC3 controller.

Signed-off-by: Andy Gross <agr...@codeaurora.org>
---
 drivers/phy/Kconfig |  11 +
 drivers/phy/Makefile|   1 +
 drivers/phy/phy-qcom-dwc3.c | 483 
 3 files changed, 495 insertions(+)
 create mode 100644 drivers/phy/phy-qcom-dwc3.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859d..f26bfc9 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -305,6 +305,17 @@ config PHY_QCOM_APQ8064_SATA
depends on OF
select GENERIC_PHY
 
+config PHY_QCOM_DWC3
+   tristate "Qualcomm DWC3 USB PHY support"
+   depends on ARCH_QCOM
+   depends on HAS_IOMEM
+   depends on OF
+   select GENERIC_PHY
+   help
+ This option enables support for the Synopsis PHYs present inside the
+ Qualcomm USB3.0 DWC3 controller.  This driver supports both HS and SS
+ PHY controllers.
+
 config PHY_QCOM_IPQ806X_SATA
tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
depends on ARCH_QCOM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a..0610e0d 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -48,3 +48,4 @@ obj-$(CONFIG_PHY_TUSB1210)+= phy-tusb1210.o
 obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
 obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
 obj-$(CONFIG_PHY_CYGNUS_PCIE)  += phy-bcm-cygnus-pcie.o
+obj-$(CONFIG_PHY_QCOM_DWC3)+= phy-qcom-dwc3.o
diff --git a/drivers/phy/phy-qcom-dwc3.c b/drivers/phy/phy-qcom-dwc3.c
new file mode 100644
index 000..9398f6b
--- /dev/null
+++ b/drivers/phy/phy-qcom-dwc3.c
@@ -0,0 +1,483 @@
+/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ *  USB QSCRATCH Hardware registers
+ */
+#define QSCRATCH_GENERAL_CFG   (0x08)
+#define HSUSB_PHY_CTRL_REG (0x10)
+
+/* PHY_CTRL_REG */
+#define HSUSB_CTRL_DMSEHV_CLAMPBIT(24)
+#define HSUSB_CTRL_USB2_SUSPENDBIT(23)
+#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
+#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
+#define HSUSB_CTRL_USE_CLKCORE BIT(18)
+#define HSUSB_CTRL_DPSEHV_CLAMPBIT(17)
+#define HSUSB_CTRL_COMMONONN   BIT(11)
+#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
+#define HSUSB_CTRL_OTGSESSVLD_CLAMPBIT(8)
+#define HSUSB_CTRL_CLAMP_ENBIT(7)
+#define HSUSB_CTRL_RETENABLEN  BIT(1)
+#define HSUSB_CTRL_POR BIT(0)
+
+/* QSCRATCH_GENERAL_CFG */
+#define HSUSB_GCFG_XHCI_REVBIT(2)
+
+/**
+ *  USB QSCRATCH Hardware registers
+ */
+#define SSUSB_PHY_CTRL_REG (0x00)
+#define SSUSB_PHY_PARAM_CTRL_1 (0x04)
+#define SSUSB_PHY_PARAM_CTRL_2 (0x08)
+#define CR_PROTOCOL_DATA_IN_REG(0x0c)
+#define CR_PROTOCOL_DATA_OUT_REG   (0x10)
+#define CR_PROTOCOL_CAP_ADDR_REG   (0x14)
+#define CR_PROTOCOL_CAP_DATA_REG   (0x18)
+#define CR_PROTOCOL_READ_REG   (0x1c)
+#define CR_PROTOCOL_WRITE_REG  (0x20)
+
+/* PHY_CTRL_REG */
+#define SSUSB_CTRL_REF_USE_PAD BIT(28)
+#define SSUSB_CTRL_TEST_POWERDOWN  BIT(27)
+#define SSUSB_CTRL_LANE0_PWR_PRESENT   BIT(24)
+#define SSUSB_CTRL_SS_PHY_EN   BIT(8)
+#define SSUSB_CTRL_SS_PHY_RESETBIT(7)
+
+/* SSPHY control registers */
+#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane)
+#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane)(0x1002 + 0x100 * lane)
+
+/* RX OVRD IN HI bits */
+#define RX_OVRD_IN_HI_RX_RESET_OVRDBIT(13)
+#define RX_OVRD_IN_HI_RX_RX_RESET  BIT(12)
+#define RX_OVRD_IN_HI_RX_EQ_OVRD   BIT(11)
+#define RX_OVRD_IN_HI_RX_EQ_MASK   0x0700
+#define RX_OVRD_IN_HI_RX_EQ_SHIFT  8
+#define RX_OVRD_IN_HI_RX_EQ_EN_OVRDBIT(7)
+#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
+#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD   BIT(5)
+#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK   0x0018
+#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
+#define RX_OVRD_IN_HI_RX_RATE_MASK   

[PATCH 0/4] Add QCOM DWC3 Phy support

[Andy Gross]

This set of patches adds support for the QCOM DWC3 phys found on various
Qualcomm platforms.  The PHY portion of this set was originally part of:

https://lkml.org/lkml/2014/9/12/597

The applicable review comments were fixed and additional changes were made to
accomodate the TCSR phy mux selection required to get working ports.

Andy Gross (4):
  phy: Add Qualcomm DWC3 HS/SS PHY driver
  usb: dwc3: qcom: Configure TCSR phy mux register
  ARM: dts: qcom: Add DWC3 USB support on IPQ8064
  Documentation: usb: dwc3: qcom: Add TCSR mux usage

 .../devicetree/bindings/usb/qcom,dwc3.txt  |  11 +
 arch/arm/boot/dts/qcom-ipq8064-ap148.dts   |  24 +
 arch/arm/boot/dts/qcom-ipq8064.dtsi|  89 
 drivers/phy/Kconfig|  11 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/phy-qcom-dwc3.c| 483 +
 drivers/usb/dwc3/dwc3-qcom.c   |  25 ++
 7 files changed, 644 insertions(+)
 create mode 100644 drivers/phy/phy-qcom-dwc3.c

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[PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage

[Andy Gross]

This patch adds documentation for the optional syscon-tcsr property in the
Qualcomm DWC3 node.  The syscon-tcsr specifies the register and bit used to
configure the TCSR USB phy mux register.

Signed-off-by: Andy Gross <agr...@codeaurora.org>
---
 Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt 
b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
index ca164e7..dfa222d 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
@@ -8,6 +8,10 @@ Required properties:
   "core"   Master/Core clock, have to be >= 125 MHz for SS
operation and >= 60MHz for HS operation
 
+Optional properties:
+- syscon-tcsr  Specifies TCSR handle, register offset, and bit position for
+   configuring the phy mux setting.
+
 Optional clocks:
   "iface"  System bus AXI clock.  Not present on all platforms
   "sleep"  Sleep clock, used when USB3 core goes into low
@@ -22,6 +26,11 @@ Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
 
 Example device nodes:
 
+   tcsr: syscon@1a40 {
+   compatible = "qcom,tcsr-ipq8064", "syscon";
+   reg = <0x1a40 0x100>;
+   };
+
hs_phy: phy@100f8800 {
compatible = "qcom,dwc3-hs-usb-phy";
reg = <0x100f8800 0x30>;
@@ -51,6 +60,8 @@ Example device nodes:
 
ranges;
 
+   syscon-tcsr = < 0xb0 0x1>;
+
status = "ok";
 
dwc3@1000 {
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Re: [RFC/PATCH] pinctrl: qcom: Add generic ssbi and spmi GPIO/MPP bindings

[Andy Gross]

On Tue, Nov 17, 2015 at 05:00:26PM -0800, Stephen Boyd wrote:
> The drivers don't really need to know which PMIC they're for, so
> make a generic binding for them. This alleviates us from updating
> the drivers every time a new PMIC comes out. It's still
> recommended that we update the binding with new PMIC models and
> always specify the specific model for the MPPs and gpios before
> the generic compatible string in devicetree, but this at least
> cuts down on adding more and more compatible strings to the
> drivers until we actually need them.
> 
> Cc: <devicetree@vger.kernel.org>
> Cc: "Ivan T. Ivanov" <iiva...@mm-sol.com>
> Cc: Bjorn Andersson <bjorn.anders...@sonymobile.com>
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>

Reviewed-by: Andy Gross <agr...@codeaurora.org>

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Re: [PATCH 0/4] Add DTS for MSM8996 SoC and MTP

[Andy Gross]

On Tue, Nov 17, 2015 at 05:12:25PM -0800, Stephen Boyd wrote:
> These patches add the initial dts files for the MSM8996 SoC and
> MTP evaluation board.
> 

These all look fine.

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Re: [PATCH 1/3] devicetree: bindings: Document qcom board compatible format

[Andy Gross]

On Mon, Oct 26, 2015 at 02:25:10PM -0700, Stephen Boyd wrote:
> Some qcom based bootloaders identify the dtb blob based on a set
> of device properties like SoC, platform, PMIC, and revisions of
> those components. In downstream kernels, these values are added
> to the different component dtsi files (i.e. pmic dtsi file, SoC
> dtsi file, board dtsi file, etc.) via qcom specific DT
> properties. The dtb files are parsed by a program called dtbTool
> that picks out these properties and creates a table of contents
> binary blob with the property information and some offsets into
> the concatenation of all the dtbs (termed a QCDT image).
> 
> The suggestion is to do this via the board compatible string
> instead, because these qcom specific properties are never used by
> the kernel. Add a document describing the format of the
> compatible string that encodes all this information that's
> currently encoded in the qcom,{msm-id,board-id,pmic-id}
> properties in downstream devicetrees. Future bootloaders may be
> updated to look at the compatible field instead of looking for
> the table of contents image. For non-updateable bootloaders, a
> new dtbTool program will parse the compatible string and generate
> a QCDT image from it.
> 
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
> ---

Looks workable.

Reviewed-by: Andy Gross <agr...@codeaurora.org>

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[Patch v2] firmware: qcom: scm: Convert to platform driver

[Andy Gross]

This patch creates a platform driver for the SCM so that we can adequately
manage resources.  This removes clients having to carry the necessary
clocks to use the SCM resources.

Signed-off-by: Andy Gross <agr...@codeaurora.org>
---
 .../devicetree/bindings/firmware/qcom,scm.txt  |   25 
 drivers/firmware/qcom_scm.c|  135 ++--
 2 files changed, 152 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/firmware/qcom,scm.txt

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt 
b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
new file mode 100644
index 000..debcd32
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -0,0 +1,25 @@
+QCOM Secure Channel Manager (SCM)
+
+Qualcomm processors include an interface to communicate to the secure firmware.
+This interface allows for clients to request different types of actions.  These
+can include CPU power up/down, HDCP requests, loading of firmware, and other
+assorted actions.
+
+Required properties:
+- compatible: must contain "qcom,scm"
+- clocks: Should contain the core, iface, and bus clocks.
+- clock-names: Must contain "core" for the core clock, "iface" for the 
interface
+  clock and "bus" for the bus clock.
+
+Example:
+
+   firmware {
+   compatible = "simple-bus";
+
+   scm {
+   compatible = "qcom,scm";
+   clocks = < GCC_CE1_CLK> , < GCC_CE1_AXI_CLK>, 
< GCC_CE1_AHB_CLK>;
+   clock-names = "core", "bus", "iface";
+   };
+   };
+
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 45c008d..7c4ec48 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -10,19 +10,57 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
  */
-
+#include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include "qcom_scm.h"
 
+struct qcom_scm {
+   struct clk *core_clk;
+   struct clk *iface_clk;
+   struct clk *bus_clk;
+};
+
+static struct qcom_scm *__scm;
+
+static int qcom_scm_clk_enable(void)
+{
+   int ret;
+
+   ret = clk_prepare_enable(__scm->core_clk);
+   if (ret)
+   goto bail;
+   ret = clk_prepare_enable(__scm->iface_clk);
+   if (ret)
+   goto disable_core;
+   ret = clk_prepare_enable(__scm->bus_clk);
+   if (ret)
+   goto disable_iface;
+
+   return 0;
+
+disable_iface:
+   clk_disable_unprepare(__scm->iface_clk);
+disable_core:
+   clk_disable_unprepare(__scm->core_clk);
+bail:
+   return ret;
+}
+
+static void qcom_scm_clk_disable(void)
+{
+   clk_disable_unprepare(__scm->core_clk);
+   clk_disable_unprepare(__scm->iface_clk);
+   clk_disable_unprepare(__scm->bus_clk);
+}
+
 /**
  * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
  * @entry: Entry point function for the cpus
@@ -72,11 +110,17 @@ EXPORT_SYMBOL(qcom_scm_cpu_power_down);
  */
 bool qcom_scm_hdcp_available(void)
 {
-   int ret;
+   int ret = qcom_scm_clk_enable();
+
+   if (ret)
+   goto clk_err;
 
ret = __qcom_scm_is_call_available(QCOM_SCM_SVC_HDCP,
-   QCOM_SCM_CMD_HDCP);
+   QCOM_SCM_CMD_HDCP);
 
+   qcom_scm_clk_disable();
+
+clk_err:
return (ret > 0) ? true : false;
 }
 EXPORT_SYMBOL(qcom_scm_hdcp_available);
@@ -91,6 +135,81 @@ EXPORT_SYMBOL(qcom_scm_hdcp_available);
  */
 int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
 {
-   return __qcom_scm_hdcp_req(req, req_cnt, resp);
+   int ret = qcom_scm_clk_enable();
+
+   if (ret)
+   return ret;
+
+   ret = __qcom_scm_hdcp_req(req, req_cnt, resp);
+   qcom_scm_clk_disable();
+   return ret;
 }
 EXPORT_SYMBOL(qcom_scm_hdcp_req);
+
+/**
+ * qcom_scm_is_available() - Checks if SCM is available
+ */
+bool qcom_scm_is_available(void)
+{
+   return !!__scm;
+}
+EXPORT_SYMBOL(qcom_scm_is_available);
+
+static int qcom_scm_probe(struct platform_device *pdev)
+{
+   struct qcom_scm *scm;
+   long rate;
+   int ret;
+
+   scm = devm_kzalloc(>dev, sizeof(*scm), GFP_KERNEL);
+   if (!scm)
+   return -ENOMEM;
+
+   scm->core_clk = devm_clk_get(>dev, "core");
+   if (IS_ERR(scm->core_clk)) {
+   if (PTR_ERR(scm->core_clk) != -EPROBE_DEFER)
+   

Re: [PATCH v2 4/6] tty: serial: msm: Add TX DMA support

[Andy Gross]

On Wed, Sep 30, 2015 at 06:32:01PM +0100, Mark Rutland wrote:
> On Wed, Sep 30, 2015 at 02:51:26PM +0100, Ivan T. Ivanov wrote:
> > 
> > On Wed, 2015-09-30 at 14:29 +0100, Mark Rutland wrote:
> > > On Wed, Sep 30, 2015 at 01:08:24PM +0100, Ivan T. Ivanov wrote:
> > > > Add transmit DMA support for UARTDM type of controllers.
> > > > 
> > > > Tested on APQ8064, which have UARTDM v1.3 and ADM DMA engine
> > > > and APQ8016, which have UARTDM v1.4 and BAM DMA engine.
> > > > 
> > > > Signed-off-by: Ivan T. Ivanov iva...@linaro.org>
> > > > ---
> > > >  .../devicetree/bindings/serial/qcom,msm-uartdm.txt |   3 +
> > > >  drivers/tty/serial/msm_serial.c| 312 
> > > > +++--
> > > >  drivers/tty/serial/msm_serial.h|   3 +
> > > >  3 files changed, 294 insertions(+), 24 deletions(-)
> > > > 
> > > > diff --git 
> > > > a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt 
> > > > b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
> > > > index a2114c217376..a600023d9ec1 100644
> > > > --- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
> > > > +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
> > > > @@ -26,6 +26,9 @@ Required properties:
> > > >  Optional properties:
> > > >  - dmas: Should contain dma specifiers for transmit and receive channels
> > > >  - dma-names: Should contain "tx" for transmit and "rx" for receive 
> > > > channels
> > > > +- qcom,tx-crci: Identificator  for Client Rate Control Interface 
> > > > to be
> > > > +   used with TX DMA channel. Required when using DMA for 
> > > > transmission
> > > > +   with UARTDM v1.3 and bellow.
> > > 
> > > This sounds like it belongs in the dma-specifier, and dealt with by the
> > > DMA controller driver.
> > > 
> > > Why does the UART driver need to know about this?
> > 
> > CRCI information was part of the first version of ADM DMA engine driver
> > bindings, but Andy remove it because some client devices are requiring
> > more that one CRCI number. See here[1] and here [2].
> > 
> > Regards,
> > Ivan
> > 
> > [1] 
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314190.html
> > [2] https://lkml.org/lkml/2015/8/19/19
> 
> This leaves me more confused. If different writes from the same agent
> are being distinguished then it sounds like you actually have two
> logical DMA channels.
> 
> Could you elaborate on the qcom,ebi2-nand binding? From a brief read I'd
> expect you to have "txrx" and "cmd" dmas, rather than describing the
> CRCI information on the side.

The ADM does have physical channels, but when you utilize those channels you may
also need to describe the flow control used for specific transactions.  And this
flow control has to be configured for that specific transaction, if you are
interleaving different flow control origination/end points.

In the case of nand, they actually use different flow controls on the same
physical channel.  For UART/I2C/SPI, they use just one flow control identifier.

I see your point at specifying these as logical channels.  That is certainly a
possibility.  Then the ADM driver would just have to handle the logical channel
allocation.  That would remove the need for the slave_config being sent.

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Re: [PATCH v2 0/2] arm64: dts: qcom: 8x16: UARTDM additions

[Andy Gross]

On Fri, Sep 18, 2015 at 04:18:52PM +0300, Ivan T. Ivanov wrote:
> Hi,
> 
> This is second version of the changes previously posted [1].
> I have to rebase them on top of Andy's for-next[2] branch and rework them
> a little bit, because some of the definitions have been already merged.
> 
> Regards,
> Ivan
> 
> [1] https://lkml.org/lkml/2015/9/12/114
> [2] https://www.codeaurora.org/cgit/quic/kernel/agross-msm/

Thanks!  I have these applied.

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Re: [PATCH 00/14] ARM: dts: apq8064 dt cleanups and additions

[Andy Gross]

On Fri, Sep 18, 2015 at 01:29:31PM +0100, Srinivas Kandagatla wrote:
> Hi Andy, 
> 
> Here are few cleanup and additions to the existing APQ8064 device tree.
> 
> Some of the patches are to do with princtrl cleanup which was always not
> in the right place and some of the pinctrls were missing.
> Other set of patches is to do with adding more devices like rtc rng
> and pwr key for pmic 8921.
> Last set of patches are related to pwrseq and SD card detect taking Stephens
> comments into consideration.

These all look fine.  I tested in ifc6410 as well.  I'll test on qs600 to be
sure.

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Re: [PATCH v4] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC

[Andy Gross]

On Thu, Aug 27, 2015 at 11:01:38AM +0530, Varadarajan Narayanan wrote:
> Add initial dts files and SoC support for IPQ4019
> 
> Signed-off-by: Varadarajan Narayanan 
> ---


Aside from the incorrect copyright date (which i will fix), this is fine.

I'll apply this.

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Re: [PATCH] firmware: qcom: scm: Convert to platform driver

[Andy Gross]

On Thu, Sep 03, 2015 at 02:33:22PM -0700, Stephen Boyd wrote:
> On 07/20, Andy Gross wrote:
> > This patch creates a platform driver for the SCM so that we can adequately
> > manage resources.  This removes clients having to carry the necessary
> > clocks to use the SCM resources.
> > 
> > Signed-off-by: Andy Gross <agr...@codeaurora.org>
> > ---
> 
> It would be nice if we could use this platform device for doing
> the DMAish memory allocations that we do in this driver too. I
> guess one complication there is that we would need to allocate
> memory with the DMA APIs before CPUs are brought up
> (early_initcall level).

Yeah that's one thing we could do but we'd have to defer the memory stuff until
it's used the first time (specific calls require it).

> 
> > diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
> > index 45c008d..5dd0514 100644
> > --- a/drivers/firmware/qcom_scm.c
> > +++ b/drivers/firmware/qcom_scm.c
> > @@ -15,14 +15,57 @@
> >   * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
> >   * 02110-1301, USA.
> >   */
> > -
> > +#include 
> > +#include 
> > +#include 
> 
> This include is here twice.
> 
> >  #include 
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> >  
> [...]
> > +
> > +/**
> > + * qcom_scm_is_available() - Checks if SCM is available
> > + */
> > +bool qcom_scm_is_available(void)
> > +{
> > +   return !!__scm;
> > +}
> > +EXPORT_SYMBOL(qcom_scm_is_available);
> > +
> > +static int qcom_scm_remove(struct platform_device *pdev)
> > +{
> > +   __scm = NULL;
> > +
> > +   return 0;
> > +}
> 
> Maybe we just shouldn't allow this? The firmware isn't going
> anywhere at runtime, and this driver is currently marked as
> bool in the Kconfig.

Fair enough.

> 
> > +
> > +static const struct of_device_id qcom_scm_dt_match[] = {
> > +   { .compatible = "qcom,scm",},
> > +   {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, qcom_scm_dt_match);
> > +
> > +static struct platform_driver qcom_scm_driver = {
> > +   .driver = {
> > +   .name   = "scm",
> 
> Maybe 'qcom_scm' ?

yeah i should have used that.

> 
> > +   .of_match_table = qcom_scm_dt_match,
> > +   },
> > +   .probe = qcom_scm_probe,
> > +   .remove = qcom_scm_remove,
> > +};
> > +
> > +module_platform_driver(qcom_scm_driver);
> 
> Isn't there some sort of builtin_platform_driver() macro for
> builtin modules?

I'll take a look and convert.


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Re: [PATCH v2 5/6] ARM: dts: qs600: add alias to serial0

[Andy Gross]

On Tue, Aug 25, 2015 at 04:46:22PM -0500, Andy Gross wrote:
 On Tue, Aug 18, 2015 at 02:10:27PM +0100, Srinivas Kandagatla wrote:
  This patch add alias node with serial0.
  
  Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
  ---
   arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 4 
   1 file changed, 4 insertions(+)
 
 Looks fine.  Applied.

Scratch that.  I dropped it from the patch list due to stephen's set.

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Re: [PATCH] arm64: dts: qcom: Add RNG device tree node

[Andy Gross]

On Tue, Aug 25, 2015 at 06:37:42PM +0300, Stanimir Varbanov wrote:
 Adds rng device tree node for msm8916 SoCs.
 
 Signed-off-by: Stanimir Varbanov stanimir.varba...@linaro.org
 ---
  arch/arm64/boot/dts/qcom/msm8916.dtsi |7 +++
  1 file changed, 7 insertions(+)

Looks good to me.  Applied.

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Re: [PATCH v2 4/6] ARM: dts: qs600: remove unnecessary i2c pinctrl nodes in board file.

[Andy Gross]

On Tue, Aug 18, 2015 at 02:10:19PM +0100, Srinivas Kandagatla wrote:
 This patch removes unnecessary i2c pinctrl nodes in board file, these
 are already defined in the soc specific file qcom-apq8064.dtsi.
 
 Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
 ---
  arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 9 -
  1 file changed, 9 deletions(-)

Applied, thanks!

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Re: [PATCH v2 5/6] ARM: dts: qs600: add alias to serial0

[Andy Gross]

On Tue, Aug 18, 2015 at 02:10:27PM +0100, Srinivas Kandagatla wrote:
 This patch add alias node with serial0.
 
 Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
 ---
  arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 4 
  1 file changed, 4 insertions(+)

Looks fine.  Applied.

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Re: [PATCH RFC 06/10] drivers: qcom: Enable genpd on selecting QCOM_PM

[Andy Gross]

On Wed, Aug 05, 2015 at 10:32:42AM -0600, Lina Iyer wrote:
 Enable PM_CPU_DOMAIN and its PM_GENERIC_DOMAINS dependenciesd to provide
 cpu domain support for QCOM SoCs.

Fix dependencies sic

 
 Signed-off-by: Lina Iyer lina.i...@linaro.org
 ---
  drivers/soc/qcom/Kconfig | 4 
  1 file changed, 4 insertions(+)
 
 diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
 index ba47b70..b6c2e5d 100644
 --- a/drivers/soc/qcom/Kconfig
 +++ b/drivers/soc/qcom/Kconfig
 @@ -14,6 +14,10 @@ config QCOM_PM
   bool Qualcomm Power Management
   depends on ARCH_QCOM  !ARM64
   select QCOM_SCM
 + select ARM_CPU_SUSPEND
 + select PM_GENERIC_DOMAINS
 + select PM_GENERIC_DOMAINS_SLEEP
 + select PM_GENERIC_DOMAINS_OF
   help
 QCOM Platform specific power driver to manage cores and L2 low power
 modes. It interface with various system drivers to put the cores in
 -- 
 2.1.4
 

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Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

[Andy Gross]

On Mon, Aug 03, 2015 at 10:38:18AM +0530, Archit Taneja wrote:
 Enable the NAND controller node on the AP148 platform. Provide pinmux
 information.
 
 Cc: devicetree@vger.kernel.org
 
 Signed-off-by: Archit Taneja arch...@codeaurora.org
 ---
  arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 
 
  1 file changed, 36 insertions(+)
 
 diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts 
 b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 index 7f9ea50..2e88eff 100644
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 @@ -30,6 +30,28 @@
   bias-none;
   };
   };
 + nand_pins: nand_pins {
 + mux {
 + pins = gpio34, gpio35, gpio36,
 +gpio37, gpio38, gpio39,
 +gpio40, gpio41, gpio42,
 +gpio43, gpio44, gpio45,
 +gpio46, gpio47;
 + function = nand;
 + drive-strength = 10;
 + bias-disable;
 + };
 + pullups {
 + pins = gpio39;
 + bias-pull-up;
 + };
 + hold {
 + pins = gpio40, gpio41, gpio42,
 +gpio43, gpio44, gpio45,
 +gpio46, gpio47;
 + bias-bus-hold;

Maybe split out the bias-disable into a separate set and remove that property
from the mux.

 + };
 + };
   };
  
   gsbi@1630 {
 @@ -93,5 +115,19 @@
   sata@2900 {
   status = ok;
   };
 +
 + nand@1ac0 {
 + status = ok;
 +
 + pinctrl-0 = nand_pins;
 + pinctrl-names = default;
 +
 + nand-ecc-strength = 4;
 + nand-bus-width = 8;
 + };
   };
  };
 +
 +adm_dma {
 + status = ok;
 +};
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Re: [PATCH v3 1/5] soc: qcom: Add device tree binding for Shared Memory Device

[Andy Gross]

On Mon, Jul 27, 2015 at 08:20:29PM -0700, Bjorn Andersson wrote:
 Add device tree binding documentation for the Qualcomm Shared Memory
 Device, used for communication between the various CPUs in the Qualcomm
 SoCs.
 
 Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
 ---

Applied, thanks.

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Re: [PATCH v3 3/5] devicetree: soc: Add Qualcomm SMD based RPM DT binding

[Andy Gross]

On Mon, Jul 27, 2015 at 08:20:31PM -0700, Bjorn Andersson wrote:
 Add binding documentation for the Qualcomm Resource Power Manager (RPM)
 using shared memory (Qualcomm SMD) as transport mechanism. This is found
 in 8974 and newer based devices.
 
 The binding currently describes the rpm itself and the regulator
 subnodes.
 
 Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
 ---

Applied, thanks

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Re: [PATCH v1 0/7] DT: APQ8064 for qcom-dt-next

[Andy Gross]

On Tue, Jul 28, 2015 at 01:52:36PM +0100, Srinivas Kandagatla wrote:
 Hi Andy, 
 
 As discussed here are some dt patches which depend on
 pmic header dt-bindings/pinctrl/qcom,pmic-gpio.h which is availble in
 linux-next.

Ok.  I took all of these and put them on top of my 4.3 tags on the
qcom/for-next.  I compiled against the current next master and all was well.

snip


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Re: [PATCH v2 3/3] ARM: dts: qs600: Add real regulators to sdcc

[Andy Gross]

On Tue, Jul 28, 2015 at 09:13:05AM +0100, Srinivas Kandagatla wrote:
 This patch adds real regulators to sdcc nodes.
 
 Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
 ---

Applied.  Thanks

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Re: [PATCH v2 2/3] ARM: dts: ifc6410: add real regulators for sdcc nodes.

[Andy Gross]

On Tue, Jul 28, 2015 at 09:12:58AM +0100, Srinivas Kandagatla wrote:
 This patch adds real regulators for all the three sdcc nodes.
 
 Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
 ---

Applied.  Thanks

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Re: [PATCH v2 1/3] ARM: dts: apq8064: remove temporary fixed regulator for mmc

[Andy Gross]

On Tue, Jul 28, 2015 at 09:12:51AM +0100, Srinivas Kandagatla wrote:
 This patch removes temporary fixed regluator use for mmc.
 Board files should use the regulators which are wiredup appropriately.
 
 Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
 ---

Applied.  Thanks!

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Re: [PATCH v1 0/7] APQ8064 dt patches.

[Andy Gross]

On Mon, Jul 27, 2015 at 02:49:05PM +0100, Srinivas Kandagatla wrote:
 Hi Andy,
 
 Here are some DT patches which are fixes + pmic gpio/mpp nodes for APQ8064.
 I tested these patches on APQ8064 based IFC6410 board. These patches are
 on top of your qcom/dt branch.
 
 I got few more DT patches which depend on the pmic gpio and mpp dt-bindings 
 header file,
 this header file is already available in the linux-next, Should I send those 
 patches too?
 Or wait till it appears on 4.3-rc1?

Send em.  I can at least add them to my next branch.

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Re: [PATCH v1 2/7] ARM: dts: ifc6410: add real regulators for sdcc nodes.

[Andy Gross]

On Mon, Jul 27, 2015 at 02:50:12PM +0100, Srinivas Kandagatla wrote:

snip

   sdcc3: sdcc@1218 {
   status = okay;
 + vmmc-supply = pm8921_l6;
   pinctrl-names   = default;
   pinctrl-0   = card_detect;
   cd-gpios= tlmm_pinmux 26 
 GPIO_ACTIVE_LOW;
 @@ -187,6 +200,8 @@
   /* WLAN */
   sdcc4: sdcc@121c {
   status = okay;
 + vmmc-supply = ext_3p3v;

Where is ext_3p3v defined?

 + vqmmc-supply = pm8921_lvs1;

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Re: [PATCH v1 5/7] ARM: dts: apq8064: add pm8921 mpp support

[Andy Gross]

On Mon, Jul 27, 2015 at 02:52:02PM +0100, Srinivas Kandagatla wrote:
 This patch adds pmic pm8921 mpp gpio controller node.
 
 Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
 ---

Applied.  Thanks!

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Re: [PATCH v1 3/7] ARM: dts: qs600: Add real regulators to sdcc

[Andy Gross]

On Mon, Jul 27, 2015 at 02:50:20PM +0100, Srinivas Kandagatla wrote:

snip

   /* WLAN */
   sdcc4: sdcc@121c {
   status = okay;
 + vmmc-supply = v3p3_fixed;
 + vqmmc-supply = v3p3_fixed;
 + mmc-pwrseq = sdcc4_pwrseq;

Where is sdcc4_pwrseq defined?


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Re: [PATCH v1 6/7] ARM: dts: apq8064: Add DT support for GSBI6 and for UART pin mux

[Andy Gross]

On Mon, Jul 27, 2015 at 02:52:10PM +0100, Srinivas Kandagatla wrote:
 From: Pramod Gurav pramod.gu...@smartplayin.com
 
 This change adds DT support for GSBI6 and muxes the gpio pins
 as UART lines. Also defines a alias for serial port on these lines.
 
 Signed-off-by: Pramod Gurav pramod.gu...@smartplayin.com
 [Srinivas Kandagatla]: fix pinctrl location and rename alias correctly
 Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
 ---

Applied.  Thanks.

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Re: [PATCH v1 4/7] ARM: dts: apq8064: Add pm8921 mfd and its gpio node

[Andy Gross]

On Mon, Jul 27, 2015 at 02:51:52PM +0100, Srinivas Kandagatla wrote:
 This patch adds pmic gpio node to the device tree, this node is
 necessary for devices like wlan to control reset gpio.
 
 Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
 ---

Applied.  thanks!

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Re: [PATCH v1 7/7] ARM: dts: apq8064: fix missing gsbi cell-index

[Andy Gross]

On Mon, Jul 27, 2015 at 02:52:19PM +0100, Srinivas Kandagatla wrote:
 Without this i2c instance for missing cell-index nodes would fail, fix
 it by adding correct cell-index.
 
 Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
 ---

Applied.  Thanks.

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Re: [PATCH v3 2/3] ARM: qcom: Add coincell charger driver

[Andy Gross]

On Thu, Jul 16, 2015 at 04:55:32PM -0700, Tim Bird wrote:
 This driver is used to configure the coincell charger found in
 Qualcomm PMICs.
 
 The driver allows configuring the current-limiting resistor for
 the charger, as well as the voltage to apply to the coincell
 (or capacitor) when charging.
 
 Signed-off-by: Tim Bird tim.b...@sonymobile.com
 ---

Looks fine.

Reviewed-by: Andy Gross agr...@codeaurora.org

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Re: [PATCH v3 3/3] ARM: dts: qcom: Add dts changes for qcom coincell charger

[Andy Gross]

On Thu, Jul 16, 2015 at 04:55:33PM -0700, Tim Bird wrote:
 Add framework for the coincell charger DT block in pm8941 file, and
 actual values for honami battery in the honami dts file.
 
 Signed-off-by: Tim Bird tim.b...@sonymobile.com
 ---

Reviewed-by: Andy Gross agr...@codeaurora.org


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Re: [PATCH v3 1/3] ARM: dts: qcom: Add binding for the qcom coincell charger

[Andy Gross]

On Thu, Jul 16, 2015 at 04:55:31PM -0700, Tim Bird wrote:
 This binding is used to configure the driver for the coincell charger
 found in Qualcomm PMICs.
 
 Signed-off-by: Tim Bird tim.b...@sonymobile.com
 ---

Looks reasonable.

Reviewed-by: Andy Gross agr...@codeaurora.org

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Re: [PATCH v2 3/5] dt/bindings: qcom_nandc: Add DT bindings

[Andy Gross]

On Tue, Jul 21, 2015 at 04:04:44PM +0530, Archit Taneja wrote:
 Add DT bindings document for the Qualcomm NAND controller driver.
 
 Cc: devicetree@vger.kernel.org
 
 Signed-off-by: Archit Taneja arch...@codeaurora.org
 ---

Acked-by: Andy Gross agr...@codeaurora.org

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Re: [PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform

[Andy Gross]

On Tue, Jul 21, 2015 at 04:04:46PM +0530, Archit Taneja wrote:
 Enable the NAND controller node on the AP148 platform. Provide pinmux
 information.
 
 Cc: devicetree@vger.kernel.org
 Signed-off-by: Archit Taneja arch...@codeaurora.org
 ---

Looks fine.

Reviewed-by: Andy Gross agr...@codeaurora.org


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Re: [PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform

[Andy Gross]

On Tue, Jul 21, 2015 at 04:04:46PM +0530, Archit Taneja wrote:
 Enable the NAND controller node on the AP148 platform. Provide pinmux
 information.
 
 Cc: devicetree@vger.kernel.org
 Signed-off-by: Archit Taneja arch...@codeaurora.org
 ---

One nit though.  The subject mispells Enable.

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Re: [PATCH v2 4/5] arm: qcom: dts: Add NAND controller node for ipq806x

[Andy Gross]

On Tue, Jul 21, 2015 at 04:04:45PM +0530, Archit Taneja wrote:
 The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
 compatible string.
 
 Cc: devicetree@vger.kernel.org
 Signed-off-by: Archit Taneja arch...@codeaurora.org
 ---

Reviewed-by: Andy Gross agr...@codeaurora.org

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Re: [PATCH v2 01/11] soc: qcom: Add device tree binding for SMEM

[Andy Gross]

On Fri, Jun 26, 2015 at 02:50:09PM -0700, bj...@kryo.se wrote:
 From: Bjorn Andersson bjorn.anders...@sonymobile.com
 
 Add device tree binding documentation for the Qualcom Shared Memory
 Manager.
 
 Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com

snip

 + smem@fa0 {
 + compatible = qcom,smem;
 +
 + memory-region = smem_region;
 + reg = 0xfc428000 0x4000;

I'll fixup the address here before applying.

Applied, thanks!

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Re: [PATCH v2 08/11] ARM: dts: msm8974: Add tcsr mutex node

[Andy Gross]

On Fri, Jun 26, 2015 at 02:50:16PM -0700, bj...@kryo.se wrote:
 From: Bjorn Andersson bjorn.anders...@sonymobile.com
 
 Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
 ---
  arch/arm/boot/dts/qcom-msm8974.dtsi | 12 
  1 file changed, 12 insertions(+)
 

Applied, thanks!

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Re: [PATCH v2 09/11] ARM: dts: msm8974: Add smem reservation and node

[Andy Gross]

On Fri, Jun 26, 2015 at 02:50:17PM -0700, bj...@kryo.se wrote:
 From: Bjorn Andersson bjorn.anders...@sonymobile.com
 
 Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
 ---

Applied, thanks.

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[PATCH] firmware: qcom: scm: Convert to platform driver

[Andy Gross]

This patch creates a platform driver for the SCM so that we can adequately
manage resources.  This removes clients having to carry the necessary
clocks to use the SCM resources.

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 .../devicetree/bindings/firmware/qcom,scm.txt  |   25 
 drivers/firmware/qcom_scm.c|  138 +++-
 2 files changed, 159 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/firmware/qcom,scm.txt

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt 
b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
new file mode 100644
index 000..debcd32
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -0,0 +1,25 @@
+QCOM Secure Channel Manager (SCM)
+
+Qualcomm processors include an interface to communicate to the secure firmware.
+This interface allows for clients to request different types of actions.  These
+can include CPU power up/down, HDCP requests, loading of firmware, and other
+assorted actions.
+
+Required properties:
+- compatible: must contain qcom,scm
+- clocks: Should contain the core, iface, and bus clocks.
+- clock-names: Must contain core for the core clock, iface for the 
interface
+  clock and bus for the bus clock.
+
+Example:
+
+   firmware {
+   compatible = simple-bus;
+
+   scm {
+   compatible = qcom,scm;
+   clocks = gcc GCC_CE1_CLK , gcc GCC_CE1_AXI_CLK, 
gcc GCC_CE1_AHB_CLK;
+   clock-names = core, bus, iface;
+   };
+   };
+
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 45c008d..5dd0514 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -15,14 +15,57 @@
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  * 02110-1301, USA.
  */
-
+#include linux/platform_device.h
+#include linux/module.h
+#include linux/platform_device.h
 #include linux/cpumask.h
 #include linux/export.h
 #include linux/types.h
 #include linux/qcom_scm.h
+#include linux/of.h
+#include linux/clk.h
 
 #include qcom_scm.h
 
+struct qcom_scm {
+   struct clk *core_clk;
+   struct clk *iface_clk;
+   struct clk *bus_clk;
+};
+
+static struct qcom_scm *__scm;
+
+static int qcom_scm_clk_enable(void)
+{
+   int ret;
+
+   ret = clk_prepare_enable(__scm-core_clk);
+   if (ret)
+   goto bail;
+   ret = clk_prepare_enable(__scm-iface_clk);
+   if (ret)
+   goto disable_core;
+   ret = clk_prepare_enable(__scm-bus_clk);
+   if (ret)
+   goto disable_iface;
+
+   return 0;
+
+disable_iface:
+   clk_disable_unprepare(__scm-iface_clk);
+disable_core:
+   clk_disable_unprepare(__scm-core_clk);
+bail:
+   return ret;
+}
+
+static void qcom_scm_clk_disable(void)
+{
+   clk_disable_unprepare(__scm-core_clk);
+   clk_disable_unprepare(__scm-iface_clk);
+   clk_disable_unprepare(__scm-bus_clk);
+}
+
 /**
  * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
  * @entry: Entry point function for the cpus
@@ -72,11 +115,17 @@ EXPORT_SYMBOL(qcom_scm_cpu_power_down);
  */
 bool qcom_scm_hdcp_available(void)
 {
-   int ret;
+   int ret = qcom_scm_clk_enable();
+
+   if (ret)
+   goto clk_err;
 
ret = __qcom_scm_is_call_available(QCOM_SCM_SVC_HDCP,
-   QCOM_SCM_CMD_HDCP);
+   QCOM_SCM_CMD_HDCP);
+
+   qcom_scm_clk_disable();
 
+clk_err:
return (ret  0) ? true : false;
 }
 EXPORT_SYMBOL(qcom_scm_hdcp_available);
@@ -91,6 +140,87 @@ EXPORT_SYMBOL(qcom_scm_hdcp_available);
  */
 int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
 {
-   return __qcom_scm_hdcp_req(req, req_cnt, resp);
+   int ret = qcom_scm_clk_enable();
+
+   if (ret)
+   return ret;
+
+   ret = __qcom_scm_hdcp_req(req, req_cnt, resp);
+   qcom_scm_clk_disable();
+   return ret;
 }
 EXPORT_SYMBOL(qcom_scm_hdcp_req);
+
+/**
+ * qcom_scm_is_available() - Checks if SCM is available
+ */
+bool qcom_scm_is_available(void)
+{
+   return !!__scm;
+}
+EXPORT_SYMBOL(qcom_scm_is_available);
+
+static int qcom_scm_remove(struct platform_device *pdev)
+{
+   __scm = NULL;
+
+   return 0;
+}
+
+static int qcom_scm_probe(struct platform_device *pdev)
+{
+   struct qcom_scm *scm;
+   int ret;
+
+   scm = devm_kzalloc(pdev-dev, sizeof(*scm), GFP_KERNEL);
+   if (!scm)
+   return -ENOMEM;
+
+   scm-core_clk = devm_clk_get(pdev-dev, core);
+   if (IS_ERR(scm-core_clk)) {
+   if (PTR_ERR(scm-core_clk) != -EPROBE_DEFER)
+   dev_err(pdev-dev, failed to acquire core clk\n);
+   return PTR_ERR(scm-core_clk);
+   }
+
+   scm-iface_clk = devm_clk_get(pdev-dev, iface);
+   if (IS_ERR(scm-iface_clk

Re: [PATCH v2 01/11] soc: qcom: Add device tree binding for SMEM

[Andy Gross]

On Wed, Jul 08, 2015 at 04:56:34PM -0700, Stephen Boyd wrote:
 On 06/26/2015 02:50 PM, bj...@kryo.se wrote:
  += EXAMPLE
  +The following example shows the SMEM setup for MSM8974, with a main SMEM 
  region
  +at 0xfa0 and an auxiliary region at 0xfc428000:
  +
  +   reserved-memory {
  +   #address-cells = 1;
  +   #size-cells = 1;
  +   ranges;
  +
  +   smem_region: smem@fa0 {
  +   reg = 0xfa0 0x20;
  +   no-map;
  +   };
  +   };
  +
  +   smem@fa0 {
 
 This should be smem@fc428000 matching the first reg property. It's weird
 though, because if smem is using a secondary region it will be under the
 SoC node and have a reg property. Otherwise it would be directly under
 the root node and only have a memory-region. It would be nice if we
 could somehow move the rpm message ram (0xfc428000) into the
 reserved-memory node so that we could use memory-region for both regions.

The memory-region is just used to describe 'real' memory.  The RPM message is IO
memory and part of the SOC.  Thats my take at least.

 
  +   compatible = qcom,smem;
  +
  +   memory-region = smem_region;
  +   reg = 0xfc428000 0x4000;
  +
  +   hwlocks = tcsr_mutex 3;
  +   };

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Re: [PATCH v2 1/2] soc: qcom: Add device tree binding for SMEM

[Andy Gross]

On Thu, Apr 23, 2015 at 02:01:28PM -0600, Jeffrey Hugo wrote:
 On 4/11/2015 5:32 PM, Bjorn Andersson wrote:
 Add device tree binding documentation for the Qualcom Shared Memory
 manager.
 
 Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
 ---
 
 Changes since v1:
 - None
 
   .../devicetree/bindings/soc/qcom/qcom,smem.txt | 49 
  ++
   1 file changed, 49 insertions(+)
   create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt
 
 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt 
 b/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt
 new file mode 100644
 index 000..d90f839
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt
 @@ -0,0 +1,49 @@
 +Qualcomm Shared Memory binding
 +
 +This binding describes the Qualcomm Shared Memory, used to share data 
 between
 +various subsystems and OSes in Qualcomm platforms.
 +
 +- compatible:
 +Usage: required
 +Value type: stringlist
 +Definition: must be:
 +qcom,smem
 +
 +- memory-region:
 +Usage: required
 +Value type: prop-encoded-array
 +Definition: handle to memory reservation for main smem memory region.
 +
 +- reg:
 +Usage: optional
 +Value type: prop-encoded-array
 +Definition: base address and size pair for any additional memory areas
 +of the shared memory.
 +
 +- hwspinlocks:
 +Usage: required
 +Value type: prop-encoded-array
 +Definition: reference to a hwspinlock used to protect allocations from
 +the shared memory
 +
 += EXAMPLE
 +
 +reserved-memory {
 +#address-cells = 1;
 +#size-cells = 1;
 +ranges;
 +
 +smem_region: smem@fa0 {
 +reg = 0xfa0 0x20;
 +no-map;
 +};
 +};
 +
 +smem@fa0 {
 +compatible = qcom,smem;
 +
 +memory-region = smem_region;
 +reg = 0xfc428000 0x4000;
 +
 +hwlocks = tcsr_mutex 3;
 +};
 
 
 For my information, is there any intention to support the
 relocatable smem_region by looking it up at init time?  It does not
 seem like it would be possible to support that with this binding.

The APPS processor really doesn't need anything except the memory region in the
DT.  If it was truly going to be dynamic, we could modify the DT in the
bootloader to set the correct address.  We can let the other processors get the
information through the WONCE TCSR registers.

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Re: [PATCH V2 2/6] i2c: qup: Add V2 tags support

[Andy Gross]

On Tue, Apr 07, 2015 at 12:01:03AM +0530, Sricharan R wrote:

snip

 +static u32 qup_i2c_send_data(struct qup_i2c_dev *qup, int tlen, u8 *tbuf,
 +  int dlen, u8 *dbuf)
 +{
 + u32 val = 0, idx = 0, pos = 0, i = 0, t;
 + int  len = tlen + dlen;
 + u8 *buf = tbuf;
 +
 + while (len  0) {
 + if (qup_i2c_wait_ready(qup, QUP_OUT_FULL, 0, 4)) {

Instead of 0 and 4 can we use some #defines?  This applies for all of the
i2c_wait_ready calls

snip


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Re: [PATCH v7 1/2] DT: hwspinlock: Add binding documentation for Qualcomm hwmutex

[Andy Gross]

On Thu, Mar 19, 2015 at 06:48:10PM -0700, Bjorn Andersson wrote:

snip

 +Example:
 +
 + tcsr: syscon@1a40 {

typo here, syscon@fd484000.  And this syscon is specifically for the tcsr mutex
reg area.

 + compatible = qcom,tcsr-msm8974, syscon;
 + reg = 0xfd484000 0x2000;

snip

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Re: [PATCH v7 1/2] DT: hwspinlock: Add binding documentation for Qualcomm hwmutex

[Andy Gross]

On Fri, Mar 20, 2015 at 01:49:12PM -0700, Bjorn Andersson wrote:
 On Fri 20 Mar 13:29 PDT 2015, Andy Gross wrote:
 
  On Thu, Mar 19, 2015 at 06:48:10PM -0700, Bjorn Andersson wrote:
  
  snip
  
   +Example:
   +
   + tcsr: syscon@1a40 {
  
  typo here, syscon@fd484000.  And this syscon is specifically for the tcsr 
  mutex
  reg area.
  
 
 You're right, I didn't read the documentation good enough; let's name it
 tcsr-mutex and as this is not the main tcsr region we should fall back
 to just having syscon as compatible.

Agreed.  A generic syscon will work until we need to support the other registers
in that block.

 But there's still a bunch of other registers in the tcsr-mutex range -
 that probably will be consumed by various drivers, so it still makes
 sense to have a syscon there.

Agreed.

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Re: [PATCH v16 00/11] ARM: qcom: cpuidle support for 8064, 8074, 8084

[Andy Gross]

On Tue, Mar 17, 2015 at 04:33:40PM -0600, Lina Iyer wrote:

snip

 
 Tested on: 8074, 8084.
 

These worked fine for me on IPQ8064 (ap148), however I did have to add my own DT
entries for the idle states and saw changes.

Also tested on APQ8064 (ifc6410).

Tested-by: Andy Gross agr...@codeaurora.org

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[PATCH 1/4] ARM: DT: ipq8064: Add ADM device node

[Andy Gross]

This patch adds support for the ADM DMA on the IPQ8064 SOC

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 arch/arm/boot/dts/qcom-ipq8064-ap148.dts |4 
 arch/arm/boot/dts/qcom-ipq8064.dtsi  |   23 +++
 2 files changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts 
b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 55b2910..7f9ea50 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -62,6 +62,10 @@
 
cs-gpios = qcom_pinmux 20 0;
 
+   dmas = adm_dma 6,
+   adm_dma 5;
+   dma-names = rx, tx;
+
flash: m25p80@0 {
compatible = s25fl256s1;
#address-cells = 1;
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi 
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index cb225da..4108ac4 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,7 +2,10 @@
 
 #include skeleton.dtsi
 #include dt-bindings/clock/qcom,gcc-ipq806x.h
+#include dt-bindings/reset/qcom,gcc-ipq806x.h
 #include dt-bindings/soc/qcom,gsbi.h
+#include dt-bindings/interrupt-controller/arm-gic.h
+
 
 / {
model = Qualcomm IPQ8064;
@@ -279,5 +282,25 @@
#clock-cells = 1;
#reset-cells = 1;
};
+
+   adm_dma: dma@1830 {
+   compatible = qcom,adm;
+   reg = 0x1830 0x10;
+   interrupts = GIC_SPI 170 IRQ_TYPE_NONE;
+   #dma-cells = 1;
+
+   clocks = gcc ADM0_CLK, gcc ADM0_PBUS_CLK;
+   clock-names = core, iface;
+
+   resets = gcc ADM0_RESET,
+gcc ADM0_PBUS_RESET,
+gcc ADM0_C0_RESET,
+gcc ADM0_C1_RESET,
+gcc ADM0_C2_RESET;
+   reset-names = clk, pbus, c0, c1, c2;
+   qcom,ee = 0;
+
+   status = disabled;
+   };
};
 };
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[PATCH 4/4] ARM: DT: msm8960: Add ADM device node

[Andy Gross]

This patch adds support for the ADM DMA on the MSM8960 SOC

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 arch/arm/boot/dts/qcom-msm8960.dtsi |   21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi 
b/arch/arm/boot/dts/qcom-msm8960.dtsi
index e1b0d5c..1b7c4c4 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -4,6 +4,7 @@
 
 #include dt-bindings/interrupt-controller/arm-gic.h
 #include dt-bindings/clock/qcom,gcc-msm8960.h
+#include dt-bindings/reset/qcom,gcc-msm8960.h
 #include dt-bindings/soc/qcom,gsbi.h
 
 / {
@@ -238,5 +239,25 @@
vmmc-supply = vsdcc_fixed;
};
};
+
+   adm_dma: dma@1832 {
+   compatible = qcom,adm;
+   reg = 0x1832 0xE;
+   interrupts = GIC_SPI 171 IRQ_TYPE_NONE;
+   #dma-cells = 1;
+
+   clocks = gcc ADM0_CLK, gcc ADM0_PBUS_CLK;
+   clock-names = core, iface;
+
+   resets = gcc ADM0_RESET,
+gcc ADM0_PBUS_RESET,
+gcc ADM0_C0_RESET,
+gcc ADM0_C1_RESET,
+gcc ADM0_C2_RESET;
+   reset-names = clk, pbus, c0, c1, c2;
+   qcom,ee = 1;
+
+   status = disabled;
+   };
};
 };
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[PATCH 2/4] ARM: DT: apq8064: Add ADM device node

[Andy Gross]

This patch adds support for the ADM DMA on the APQ8064 SOC.

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 arch/arm/boot/dts/qcom-apq8064.dtsi |   21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi 
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index b3154c0..0f24334 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -2,6 +2,7 @@
 
 #include skeleton.dtsi
 #include dt-bindings/clock/qcom,gcc-msm8960.h
+#include dt-bindings/reset/qcom,gcc-msm8960.h
 #include dt-bindings/clock/qcom,mmcc-msm8960.h
 #include dt-bindings/soc/qcom,gsbi.h
 #include dt-bindings/interrupt-controller/arm-gic.h
@@ -349,5 +350,25 @@
pinctrl-0 = sdc4_gpios;
};
};
+
+   adm_dma: dma@1832 {
+   compatible = qcom,adm;
+   reg = 0x1832 0xE;
+   interrupts = GIC_SPI 171 IRQ_TYPE_NONE;
+   #dma-cells = 1;
+
+   clocks = gcc ADM0_CLK, gcc ADM0_PBUS_CLK;
+   clock-names = core, iface;
+
+   resets = gcc ADM0_RESET,
+gcc ADM0_PBUS_RESET,
+gcc ADM0_C0_RESET,
+gcc ADM0_C1_RESET,
+gcc ADM0_C2_RESET;
+   reset-names = clk, pbus, c0, c1, c2;
+   qcom,ee = 1;
+
+   status = disabled;
+   };
};
 };
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[PATCH 3/4] ARM: DT: msm8660: Add ADM device nodes

[Andy Gross]

This patch adds support for the ADM DMA on the MSM8660 SOC

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 arch/arm/boot/dts/qcom-msm8660.dtsi |   42 +++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi 
b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 0affd61..8043c12 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -4,7 +4,9 @@
 
 #include dt-bindings/interrupt-controller/arm-gic.h
 #include dt-bindings/clock/qcom,gcc-msm8660.h
+#include dt-bindings/reset/qcom,gcc-msm8660.h
 #include dt-bindings/soc/qcom,gsbi.h
+#include dt-bindings/interrupt-controller/arm-gic.h
 
 / {
model = Qualcomm MSM8660;
@@ -196,6 +198,46 @@
vmmc-supply = vsdcc_fixed;
};
};
+
+   adm_dma0: dma@1832 {
+   compatible = qcom,adm;
+   reg = 0x1832 0x10;
+   interrupts = GIC_SPI 171 IRQ_TYPE_NONE;
+   #dma-cells = 1;
+
+   clocks = gcc ADM0_CLK, gcc ADM0_PBUS_CLK;
+   clock-names = core, iface;
+
+   resets = gcc ADM0_RESET,
+gcc ADM0_PBUS_RESET,
+gcc ADM0_C0_RESET,
+gcc ADM0_C1_RESET,
+gcc ADM0_C2_RESET;
+   reset-names = clk, pbus, c0, c1, c2;
+   qcom,ee = 1;
+
+   status = disabled;
+   };
+
+   adm_dma1: dma@1842 {
+   compatible = qcom,adm;
+   reg = 0x1842 0xE;
+   interrupts = GIC_SPI 167 IRQ_TYPE_NONE;
+   #dma-cells = 1;
+
+   clocks = gcc ADM1_CLK, gcc ADM1_PBUS_CLK;
+   clock-names = core, iface;
+
+   resets = gcc ADM1_RESET,
+gcc ADM1_PBUS_RESET,
+gcc ADM1_C0_RESET,
+gcc ADM1_C1_RESET,
+gcc ADM1_C2_RESET;
+   reset-names = clk, pbus, c0, c1, c2;
+   qcom,ee = 1;
+
+   status = disabled;
+   };
};
 
 };
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[PATCH 0/4] Add Qualcomm ADM DMA support

[Andy Gross]

This patch set adds support for the Qualcomm ADM DMA controller that is present
in the APQ8064, IPQ8064, MSM8660, and MSM8960.

Andy Gross (4):
  ARM: DT: ipq8064: Add ADM device node
  ARM: DT: apq8064: Add ADM device node
  ARM: DT: msm8660: Add ADM device nodes
  ARM: DT: msm8960: Add ADM device node

 arch/arm/boot/dts/qcom-apq8064.dtsi  |   21 +++
 arch/arm/boot/dts/qcom-ipq8064-ap148.dts |4 +++
 arch/arm/boot/dts/qcom-ipq8064.dtsi  |   23 
 arch/arm/boot/dts/qcom-msm8660.dtsi  |   42 ++
 arch/arm/boot/dts/qcom-msm8960.dtsi  |   21 +++
 5 files changed, 111 insertions(+)

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Re: [Patch v4 2/2] dmaengine: Add ADM driver

[Andy Gross]

On Mon, Mar 16, 2015 at 08:15:26AM -, sricha...@codeaurora.org wrote:
 Hi,
 
 snip
 
 
   +static int adm_get_blksize(unsigned int burst)
   +{
   +int ret;
   +
   +switch (burst) {
   +case 16:
   +ret = 0;
   +break;
   +case 32:
   +ret = 1;
   +break;
   +case 64:
   +ret = 2;
   +break;
   +case 128:
   +ret = 3;
   +break;
   +case 192:
   +ret = 4;
   +break;
   +case 256:
   +ret = 5;
   +break;
  ffs(burst4) ?
 
  that should work nicely.  thanks.
 
   Will not work for 192, 256 ?

you are right.  I'll have to separate those out into 2 more cases.  Good catch!

-- 
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a Linux Foundation Collaborative Project

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[Patch v6 2/2] dmaengine: Add ADM driver

[Andy Gross]

Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
controller found in the MSM8x60 and IPQ/APQ8064 platforms.

The ADM supports both memory to memory transactions and memory
to/from peripheral device transactions.  The controller also provides flow
control capabilities for transactions to/from peripheral devices.

The initial release of this driver supports slave transfers to/from peripherals
and also incorporates CRCI (client rate control interface) flow control.

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 drivers/dma/Kconfig|   10 +
 drivers/dma/Makefile   |1 +
 drivers/dma/qcom_adm.c |  900 
 3 files changed, 911 insertions(+)
 create mode 100644 drivers/dma/qcom_adm.c

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index a874b6e..6919013 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -473,4 +473,14 @@ config QCOM_BAM_DMA
  Enable support for the QCOM BAM DMA controller.  This controller
  provides DMA capabilities for a variety of on-chip devices.
 
+config QCOM_ADM
+   tristate Qualcomm ADM support
+   depends on ARCH_QCOM || (COMPILE_TEST  OF  ARM)
+   select DMA_ENGINE
+   select DMA_VIRTUAL_CHANNELS
+   ---help---
+ Enable support for the Qualcomm ADM DMA controller.  This controller
+ provides DMA capabilities for both general purpose and on-chip
+ peripheral devices.
+
 endif
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index f915f61..7f0fbe6 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
 obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o
 obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
 obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
+obj-$(CONFIG_QCOM_ADM) += qcom_adm.o
diff --git a/drivers/dma/qcom_adm.c b/drivers/dma/qcom_adm.c
new file mode 100644
index 000..7f8c119
--- /dev/null
+++ b/drivers/dma/qcom_adm.c
@@ -0,0 +1,900 @@
+/*
+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/kernel.h
+#include linux/io.h
+#include linux/init.h
+#include linux/slab.h
+#include linux/module.h
+#include linux/interrupt.h
+#include linux/dma-mapping.h
+#include linux/scatterlist.h
+#include linux/device.h
+#include linux/platform_device.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_irq.h
+#include linux/of_dma.h
+#include linux/reset.h
+#include linux/clk.h
+#include linux/dmaengine.h
+
+#include dmaengine.h
+#include virt-dma.h
+
+/* ADM registers - calculated from channel number and security domain */
+#define ADM_CHAN_MULTI 0x4
+#define ADM_CI_MULTI   0x4
+#define ADM_CRCI_MULTI 0x4
+#define ADM_EE_MULTI   0x800
+#define ADM_CHAN_OFFS(chan)(ADM_CHAN_MULTI * chan)
+#define ADM_EE_OFFS(ee)(ADM_EE_MULTI * ee)
+#define ADM_CHAN_EE_OFFS(chan, ee) (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee))
+#define ADM_CHAN_OFFS(chan)(ADM_CHAN_MULTI * chan)
+#define ADM_CI_OFFS(ci)(ADM_CHAN_OFF(ci))
+#define ADM_CH_CMD_PTR(chan, ee)   (ADM_CHAN_EE_OFFS(chan, ee))
+#define ADM_CH_RSLT(chan, ee)  (0x40 + ADM_CHAN_EE_OFFS(chan, ee))
+#define ADM_CH_FLUSH_STATE0(chan, ee)  (0x80 + ADM_CHAN_EE_OFFS(chan, ee))
+#define ADM_CH_STATUS_SD(chan, ee) (0x200 + ADM_CHAN_EE_OFFS(chan, ee))
+#define ADM_CH_CONF(chan)  (0x240 + ADM_CHAN_OFFS(chan))
+#define ADM_CH_RSLT_CONF(chan, ee) (0x300 + ADM_CHAN_EE_OFFS(chan, ee))
+#define ADM_SEC_DOMAIN_IRQ_STATUS(ee)  (0x380 + ADM_EE_OFFS(ee))
+#define ADM_CI_CONF(ci)(0x390 + ci * ADM_CI_MULTI)
+#define ADM_GP_CTL 0x3d8
+#define ADM_CRCI_CTL(crci, ee) (0x400 + crci * ADM_CRCI_MULTI + \
+   ADM_EE_OFFS(ee))
+
+/* channel status */
+#define ADM_CH_STATUS_VALIDBIT(1)
+
+/* channel result */
+#define ADM_CH_RSLT_VALID  BIT(31)
+#define ADM_CH_RSLT_ERRBIT(3)
+#define ADM_CH_RSLT_FLUSH  BIT(2)
+#define ADM_CH_RSLT_TPDBIT(1)
+
+/* channel conf */
+#define ADM_CH_CONF_SHADOW_EN  BIT(12)
+#define ADM_CH_CONF_MPU_DISABLEBIT(11)
+#define ADM_CH_CONF_PERM_MPU_CONF  BIT(9)
+#define ADM_CH_CONF_FORCE_RSLT_EN  BIT(7)
+#define ADM_CH_CONF_SEC_DOMAIN(ee) (((ee  0x3)  4) | ((ee  0x4)  11))
+
+/* channel result

[Patch v6 0/2] Add Qualcomm ADM dmaengine driver

[Andy Gross]

This patch set introduces the dmaengine driver for the Qualcomm Application
Data Mover (ADM) DMA controller present on MSM8x60, APQ8064, and IPQ8064
devices.

The initial version of this driver will only support slave DMA operations
between system memory and peripherals.  Flow control via the CRCI (client rate
control interface) is supported and can be configured via device tree
configuration.  Flow control usage is required for some peripheral devices.

Changes from v5:
  - Fix erroneous adm_get_blksize for values of 192 and 256.

Changes from v4:
  - Fixed copyright date
  - Fixed error in EE offsets and usage
  - Changed namespace for registers and fields to ADM specific naming
  - Removed alloc_chan function
  - Removed control function and fixed up terminate_all and slave_config
  - Reworked descriptor processing code to make it more clean
  - Moved to use of_dma_xlate_by_chan_id
  - Fixed other small review comments

Changes from v3:
  - Remove .owner field

Changes from v2:
  - Removed extraneous achan variable from xlate function
  - Reworked crci check in slave_sg function
  - Added mux field to async_desc structure.
  - Reworked dma start function to use crci and mux values directly from
structure.
  - Added disable of clocks in probe error paths.
  - Changed to use #define for fixed number of channels.

Changes since v1:
  - Fixed various review comments
  - Fixed some descriptor programming issues.
  - Added single descriptors to support sub burst length transactions.
Selection of single or box descriptors depends on the sg length and burst
size.
  - Removed use of crci in the dmas property.  CRCI is now designated via the
slave_config structure and will be stored in slave_id.

Andy Gross (2):
  dt/bindings: qcom_adm: Fix channel specifiers
  dmaengine: Add ADM driver

 Documentation/devicetree/bindings/dma/qcom_adm.txt |   16 +-
 drivers/dma/Kconfig|   10 +
 drivers/dma/Makefile   |1 +
 drivers/dma/qcom_adm.c |  900 
 4 files changed, 917 insertions(+), 10 deletions(-)
 create mode 100644 drivers/dma/qcom_adm.c

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[Patch v6 1/2] dt/bindings: qcom_adm: Fix channel specifiers

[Andy Gross]

This patch removes the crci information from the dma channel property.  At least
one client device requires using more than one CRCI value for a channel.  This
does not match the current binding and the crci information needs to be removed.

Instead, the client device will provide this information via other means.

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 Documentation/devicetree/bindings/dma/qcom_adm.txt |   16 ++--
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt 
b/Documentation/devicetree/bindings/dma/qcom_adm.txt
index 9bcab91..38d45f8 100644
--- a/Documentation/devicetree/bindings/dma/qcom_adm.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt
@@ -4,8 +4,7 @@ Required properties:
 - compatible: must contain qcom,adm for IPQ/APQ8064 and MSM8960
 - reg: Address range for DMA registers
 - interrupts: Should contain one interrupt shared by all channels
-- #dma-cells: must be 2.  First cell denotes the channel number.  Second cell
-  denotes CRCI (client rate control interface) flow control assignment.
+- #dma-cells: must be 1.  First cell denotes the channel number.
 - clocks: Should contain the core clock and interface clock.
 - clock-names: Must contain core for the core clock and iface for the
   interface clock.
@@ -22,7 +21,7 @@ Example:
compatible = qcom,adm;
reg = 0x1830 0x10;
interrupts = 0 170 0;
-   #dma-cells = 2;
+   #dma-cells = 1;
 
clocks = gcc ADM0_CLK, gcc ADM0_PBUS_CLK;
clock-names = core, iface;
@@ -35,15 +34,12 @@ Example:
qcom,ee = 0;
};
 
-DMA clients must use the format descripted in the dma.txt file, using a three
+DMA clients must use the format descripted in the dma.txt file, using a two
 cell specifier for each channel.
 
-Each dmas request consists of 3 cells:
+Each dmas request consists of two cells:
  1. phandle pointing to the DMA controller
  2. channel number
- 3. CRCI assignment, if applicable.  If no CRCI flow control is required, use 
0.
-The CRCI is used for flow control.  It identifies the peripheral device 
that
-is the source/destination for the transferred data.
 
 Example:
 
@@ -56,7 +52,7 @@ Example:
 
cs-gpios = qcom_pinmux 20 0;
 
-   dmas = adm_dma 6 9,
-   adm_dma 5 10;
+   dmas = adm_dma 6,
+   adm_dma 5;
dma-names = rx, tx;
};
-- 
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[Patch v5 2/2] dmaengine: Add ADM driver

[Andy Gross]

Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
controller found in the MSM8x60 and IPQ/APQ8064 platforms.

The ADM supports both memory to memory transactions and memory
to/from peripheral device transactions.  The controller also provides flow
control capabilities for transactions to/from peripheral devices.

The initial release of this driver supports slave transfers to/from peripherals
and also incorporates CRCI (client rate control interface) flow control.

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 drivers/dma/Kconfig|   10 +
 drivers/dma/Makefile   |1 +
 drivers/dma/qcom_adm.c |  896 
 3 files changed, 907 insertions(+)
 create mode 100644 drivers/dma/qcom_adm.c

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index a874b6e..6919013 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -473,4 +473,14 @@ config QCOM_BAM_DMA
  Enable support for the QCOM BAM DMA controller.  This controller
  provides DMA capabilities for a variety of on-chip devices.
 
+config QCOM_ADM
+   tristate Qualcomm ADM support
+   depends on ARCH_QCOM || (COMPILE_TEST  OF  ARM)
+   select DMA_ENGINE
+   select DMA_VIRTUAL_CHANNELS
+   ---help---
+ Enable support for the Qualcomm ADM DMA controller.  This controller
+ provides DMA capabilities for both general purpose and on-chip
+ peripheral devices.
+
 endif
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index f915f61..7f0fbe6 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
 obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o
 obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
 obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
+obj-$(CONFIG_QCOM_ADM) += qcom_adm.o
diff --git a/drivers/dma/qcom_adm.c b/drivers/dma/qcom_adm.c
new file mode 100644
index 000..f7cfb4e
--- /dev/null
+++ b/drivers/dma/qcom_adm.c
@@ -0,0 +1,896 @@
+/*
+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/kernel.h
+#include linux/io.h
+#include linux/init.h
+#include linux/slab.h
+#include linux/module.h
+#include linux/interrupt.h
+#include linux/dma-mapping.h
+#include linux/scatterlist.h
+#include linux/device.h
+#include linux/platform_device.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_irq.h
+#include linux/of_dma.h
+#include linux/reset.h
+#include linux/clk.h
+#include linux/dmaengine.h
+
+#include dmaengine.h
+#include virt-dma.h
+
+/* ADM registers - calculated from channel number and security domain */
+#define ADM_CHAN_MULTI 0x4
+#define ADM_CI_MULTI   0x4
+#define ADM_CRCI_MULTI 0x4
+#define ADM_EE_MULTI   0x800
+#define ADM_CHAN_OFFS(chan)(ADM_CHAN_MULTI * chan)
+#define ADM_EE_OFFS(ee)(ADM_EE_MULTI * ee)
+#define ADM_CHAN_EE_OFFS(chan, ee) (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee))
+#define ADM_CHAN_OFFS(chan)(ADM_CHAN_MULTI * chan)
+#define ADM_CI_OFFS(ci)(ADM_CHAN_OFF(ci))
+#define ADM_CH_CMD_PTR(chan, ee)   (ADM_CHAN_EE_OFFS(chan, ee))
+#define ADM_CH_RSLT(chan, ee)  (0x40 + ADM_CHAN_EE_OFFS(chan, ee))
+#define ADM_CH_FLUSH_STATE0(chan, ee)  (0x80 + ADM_CHAN_EE_OFFS(chan, ee))
+#define ADM_CH_STATUS_SD(chan, ee) (0x200 + ADM_CHAN_EE_OFFS(chan, ee))
+#define ADM_CH_CONF(chan)  (0x240 + ADM_CHAN_OFFS(chan))
+#define ADM_CH_RSLT_CONF(chan, ee) (0x300 + ADM_CHAN_EE_OFFS(chan, ee))
+#define ADM_SEC_DOMAIN_IRQ_STATUS(ee)  (0x380 + ADM_EE_OFFS(ee))
+#define ADM_CI_CONF(ci)(0x390 + ci * ADM_CI_MULTI)
+#define ADM_GP_CTL 0x3d8
+#define ADM_CRCI_CTL(crci, ee) (0x400 + crci * ADM_CRCI_MULTI + \
+   ADM_EE_OFFS(ee))
+
+/* channel status */
+#define ADM_CH_STATUS_VALIDBIT(1)
+
+/* channel result */
+#define ADM_CH_RSLT_VALID  BIT(31)
+#define ADM_CH_RSLT_ERRBIT(3)
+#define ADM_CH_RSLT_FLUSH  BIT(2)
+#define ADM_CH_RSLT_TPDBIT(1)
+
+/* channel conf */
+#define ADM_CH_CONF_SHADOW_EN  BIT(12)
+#define ADM_CH_CONF_MPU_DISABLEBIT(11)
+#define ADM_CH_CONF_PERM_MPU_CONF  BIT(9)
+#define ADM_CH_CONF_FORCE_RSLT_EN  BIT(7)
+#define ADM_CH_CONF_SEC_DOMAIN(ee) (((ee  0x3)  4) | ((ee  0x4)  11))
+
+/* channel result

[Patch v5 0/2] Add Qualcomm ADM dmaengine driver

[Andy Gross]

This patch set introduces the dmaengine driver for the Qualcomm Application
Data Mover (ADM) DMA controller present on MSM8x60, APQ8064, and IPQ8064
devices.

The initial version of this driver will only support slave DMA operations
between system memory and peripherals.  Flow control via the CRCI (client rate
control interface) is supported and can be configured via device tree
configuration.  Flow control usage is required for some peripheral devices.

Changes from v4:
  - Fixed copyright date
  - Fixed error in EE offsets and usage
  - Changed namespace for registers and fields to ADM specific naming
  - Removed alloc_chan function
  - Removed control function and fixed up terminate_all and slave_config
  - Reworked descriptor processing code to make it more clean
  - Moved to use of_dma_xlate_by_chan_id
  - Fixed other small review comments

Changes from v3:
  - Remove .owner field

Changes from v2:
  - Removed extraneous achan variable from xlate function
  - Reworked crci check in slave_sg function
  - Added mux field to async_desc structure.
  - Reworked dma start function to use crci and mux values directly from
structure.
  - Added disable of clocks in probe error paths.
  - Changed to use #define for fixed number of channels.

Changes since v1:
  - Fixed various review comments
  - Fixed some descriptor programming issues.
  - Added single descriptors to support sub burst length transactions.
Selection of single or box descriptors depends on the sg length and burst
size.
  - Removed use of crci in the dmas property.  CRCI is now designated via the
slave_config structure and will be stored in slave_id.

Andy Gross (2):
  dt/bindings: qcom_adm: Fix channel specifiers
  dmaengine: Add ADM driver

 Documentation/devicetree/bindings/dma/qcom_adm.txt |   16 +-
 drivers/dma/Kconfig|   10 +
 drivers/dma/Makefile   |1 +
 drivers/dma/qcom_adm.c |  896 
 4 files changed, 913 insertions(+), 10 deletions(-)
 create mode 100644 drivers/dma/qcom_adm.c

-- 
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[Patch v5 1/2] dt/bindings: qcom_adm: Fix channel specifiers

[Andy Gross]

This patch removes the crci information from the dma channel property.  At least
one client device requires using more than one CRCI value for a channel.  This
does not match the current binding and the crci information needs to be removed.

Instead, the client device will provide this information via other means.

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 Documentation/devicetree/bindings/dma/qcom_adm.txt |   16 ++--
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt 
b/Documentation/devicetree/bindings/dma/qcom_adm.txt
index 9bcab91..38d45f8 100644
--- a/Documentation/devicetree/bindings/dma/qcom_adm.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt
@@ -4,8 +4,7 @@ Required properties:
 - compatible: must contain qcom,adm for IPQ/APQ8064 and MSM8960
 - reg: Address range for DMA registers
 - interrupts: Should contain one interrupt shared by all channels
-- #dma-cells: must be 2.  First cell denotes the channel number.  Second cell
-  denotes CRCI (client rate control interface) flow control assignment.
+- #dma-cells: must be 1.  First cell denotes the channel number.
 - clocks: Should contain the core clock and interface clock.
 - clock-names: Must contain core for the core clock and iface for the
   interface clock.
@@ -22,7 +21,7 @@ Example:
compatible = qcom,adm;
reg = 0x1830 0x10;
interrupts = 0 170 0;
-   #dma-cells = 2;
+   #dma-cells = 1;
 
clocks = gcc ADM0_CLK, gcc ADM0_PBUS_CLK;
clock-names = core, iface;
@@ -35,15 +34,12 @@ Example:
qcom,ee = 0;
};
 
-DMA clients must use the format descripted in the dma.txt file, using a three
+DMA clients must use the format descripted in the dma.txt file, using a two
 cell specifier for each channel.
 
-Each dmas request consists of 3 cells:
+Each dmas request consists of two cells:
  1. phandle pointing to the DMA controller
  2. channel number
- 3. CRCI assignment, if applicable.  If no CRCI flow control is required, use 
0.
-The CRCI is used for flow control.  It identifies the peripheral device 
that
-is the source/destination for the transferred data.
 
 Example:
 
@@ -56,7 +52,7 @@ Example:
 
cs-gpios = qcom_pinmux 20 0;
 
-   dmas = adm_dma 6 9,
-   adm_dma 5 10;
+   dmas = adm_dma 6,
+   adm_dma 5;
dma-names = rx, tx;
};
-- 
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hosted by The Linux Foundation

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Re: [PATCH 6/6] dts: msm8974: Add dma channels for blsp2_i2c1 node

[Andy Gross]

On Fri, Mar 13, 2015 at 11:19:52PM +0530, Sricharan R wrote:
 Signed-off-by: Sricharan R sricha...@codeaurora.org
 ---

Reviewed-by: Andy Gross agr...@codeaurora.org

  arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++
  1 file changed, 2 insertions(+)
 
 diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi 
 b/arch/arm/boot/dts/qcom-msm8974.dtsi
 index 3f648ae..1ec7ec5 100644
 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
 +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
 @@ -246,6 +246,8 @@
   clock-names = core, iface;
   #address-cells = 1;
   #size-cells = 0;
 + dmas = blsp2_dma 20, blsp2_dma 21;
 + dma-names = bam-tx, bam-rx;

more of a nit, but the bam- is unnecessary.  it's just rx/tx.
   };
  
   blsp2_dma: dma@f9944000 {
 -- 
 1.8.2.1
 

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Re: [Patch v4 2/2] dmaengine: Add ADM driver

[Andy Gross]

On Fri, Mar 13, 2015 at 02:27:45PM +0530, Vinod Koul wrote:
 On Wed, Feb 11, 2015 at 11:46:05PM -0600, Andy Gross wrote:
  +++ b/drivers/dma/qcom_adm.c
  @@ -0,0 +1,901 @@
  +/*
  + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 shouldn't this be 15 :)

yeah, need to update.

 
  +/* ADM registers - calculated from channel number and security domain */
  +#define HI_CH_CMD_PTR(chan, ee)(4*chan + 0x20800*ee)
  +#define HI_CH_RSLT(chan, ee)   (0x40 + 4*chan + 0x20800*ee)
  +#define HI_CH_FLUSH_STATE0(chan, ee)   (0x80 + 4*chan + 0x20800*ee)
  +#define HI_CH_FLUSH_STATE1(chan, ee)   (0xc0 + 4*chan + 0x20800*ee)
  +#define HI_CH_FLUSH_STATE2(chan, ee)   (0x100 + 4*chan + 0x20800*ee)
  +#define HI_CH_FLUSH_STATE3(chan, ee)   (0x140 + 4*chan + 0x20800*ee)
  +#define HI_CH_FLUSH_STATE4(chan, ee)   (0x180 + 4*chan + 0x20800*ee)
  +#define HI_CH_FLUSH_STATE5(chan, ee)   (0x1c0 + 4*chan + 0x20800*ee)
  +#define HI_CH_STATUS_SD(chan, ee)  (0x200 + 4*chan + 0x20800*ee)
  +#define HI_CH_CONF(chan)   (0x240 + 4*chan)
  +#define HI_CH_RSLT_CONF(chan, ee)  (0x300 + 4*chan + 0x20800*ee)
  +#define HI_SEC_DOMAIN_IRQ_STATUS(ee)   (0x380 + 0x20800*ee)
  +#define HI_CI_CONF(ci) (0x390 + 4*ci)
  +#define HI_CRCI_CONF0  0x3d0
  +#define HI_CRCI_CONF1  0x3d4
  +#define HI_GP_CTL  0x3d8
  +#define HI_CRCI_CTL(crci, ee)  (0x400 + 0x4*crci + 0x20800*ee)
 two things, one the names are quite generic and may cause conflicts so pls
 fix that. Second the values, what is the deal with 4*chan, should that be a
 define as well. Also rather than copy pasting a macros would be better for
 this expansion

Yeah there are sets of registers that have both channel and execution
environment offsets.  It is messy.  I'll try to make it more sane.

 
  +
  +/* channel status */
  +#define CH_STATUS_VALIDBIT(1)
  +
  +/* channel result */
  +#define CH_RSLT_VALID  BIT(31)
  +#define CH_RSLT_ERRBIT(3)
  +#define CH_RSLT_FLUSH  BIT(2)
  +#define CH_RSLT_TPDBIT(1)
  +
  +/* channel conf */
  +#define CH_CONF_MPU_DISABLEBIT(11)
  +#define CH_CONF_PERM_MPU_CONF  BIT(9)
  +#define CH_CONF_FLUSH_RSLT_EN  BIT(8)
  +#define CH_CONF_FORCE_RSLT_EN  BIT(7)
  +#define CH_CONF_IRQ_EN BIT(6)
  +
  +/* channel result conf */
  +#define CH_RSLT_CONF_FLUSH_EN  BIT(1)
  +#define CH_RSLT_CONF_IRQ_ENBIT(0)
  +
  +/* CRCI CTL */
  +#define CRCI_CTL_MUX_SEL   BIT(18)
  +#define CRCI_CTL_RST   BIT(17)
  +
  +/* CI configuration */
  +#define CI_RANGE_END(x)(x  24)
  +#define CI_RANGE_START(x)  (x  16)
  +#define CI_BURST_4_WORDS   0x4
  +#define CI_BURST_8_WORDS   0x8
 shouldn't you be consistent is usage of BIT()

good catch

  +
  +/* GP CTL */
  +#define GP_CTL_LP_EN   BIT(12)
  +#define GP_CTL_LP_CNT(x)   (x  8)
  +
  +/* Command pointer list entry */
  +#define CPLE_LPBIT(31)
  +#define CPLE_CMD_PTR_LIST  BIT(29)
  +
  +/* Command list entry */
  +#define CMD_LC BIT(31)
  +#define CMD_DST_CRCI(n)(((n)  0xf)  7)
  +#define CMD_SRC_CRCI(n)(((n)  0xf)  3)
  +
  +#define CMD_TYPE_SINGLE0x0
  +#define CMD_TYPE_BOX   0x3a
 naming issues...

ok. will try to come up with something better

  +static int adm_alloc_chan(struct dma_chan *chan)
  +{
  +   return 0;
  +}
 This is no longer mandatory, so can be dropped

will remove

 
  +static int adm_get_blksize(unsigned int burst)
  +{
  +   int ret;
  +
  +   switch (burst) {
  +   case 16:
  +   ret = 0;
  +   break;
  +   case 32:
  +   ret = 1;
  +   break;
  +   case 64:
  +   ret = 2;
  +   break;
  +   case 128:
  +   ret = 3;
  +   break;
  +   case 192:
  +   ret = 4;
  +   break;
  +   case 256:
  +   ret = 5;
  +   break;
 ffs(burst4) ?

that should work nicely.  thanks.

  +static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan 
  *chan,
  +   struct scatterlist *sgl, unsigned int sg_len,
  +   enum dma_transfer_direction direction, unsigned long flags,
  +   void *context)
  +{
  +   struct adm_chan *achan = to_adm_chan(chan);
  +   struct adm_device *adev = achan-adev;
  +   struct adm_async_desc *async_desc;
  +   struct scatterlist *sg;
  +   u32 i;
  +   u32 single_count = 0, box_count = 0, desc_offset = 0, crci = 0;
  +   struct adm_desc_hw_box *box_desc;
  +   struct adm_desc_hw_single *single_desc;
  +   void *desc;
  +   u32 *cple, *last_cmd;
  +   u32 burst;
  +   int blk_size = 0;
  +
  +
  +   if (!is_slave_direction(direction)) {
  +   dev_err(adev-dev, invalid dma direction\n);
  +   return NULL;
  +   }
  +
  +   /*
  +* get burst value from slave configuration
  +* If zero, default to maximum burst size

Re: [RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Andy Gross]

On Mon, Mar 09, 2015 at 03:40:06PM -0600, Lina Iyer wrote:
snip

 for_each_possible_cpu(cpu) {
 +
 ret = arm_cpuidle_init(cpu);
 +   /*
 +* This cpu does not support any idle states
 +*/
 +   if (ret == -ENOSYS)
 +   continue;
 +
 if (ret) {
 pr_err(CPU %d failed to init idle CPU ops\n, cpu);
 return ret;
 }
 +
 +   dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 
 devm_kzalloc?  Otherwise, failures could lead to lost memory.
 
 I dont have a local device to work with for allocation. May be I can get
 the cpu device node and the device therefore for allocation. Thoughts?

Ah, well the cpu device node could be used.  My only concern is that dev cannot
be referenced after the cpu is removed.

 +   if (!dev)
 +   return -ENOMEM;
 +
 +   dev-cpu = cpu;
 +   ret = cpuidle_register_device(dev);
 +   if (ret) {
 +   pr_err(Failed to register cpuidle device for CPU %d\n,
 +  cpu);

snip

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Re: [RFC PATCH v15 01/11] ARM: cpuidle: Register per cpuidle device

[Andy Gross]

On Mon, Mar 09, 2015 at 09:16:36AM -0600, Lina Iyer wrote:
 From: Daniel Lezcano daniel.lezc...@linaro.org
 
 Some architectures have some cpus which does not support idle states.
 
 Let the underlying low level code to return -ENOSYS when it is not
 possible to set an idle state.
 
 Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
 Signed-off-by: Lina Iyer lina.i...@linaro.org
 [Minor clean ups and fixes of the per-cpu variable]
 ---
  drivers/cpuidle/cpuidle-arm.c | 34 +-
  1 file changed, 33 insertions(+), 1 deletion(-)
 
 diff --git a/drivers/cpuidle/cpuidle-arm.c b/drivers/cpuidle/cpuidle-arm.c
 index 1c94b88..f7cdb73 100644
 --- a/drivers/cpuidle/cpuidle-arm.c
 +++ b/drivers/cpuidle/cpuidle-arm.c
 @@ -17,11 +17,14 @@
  #include linux/kernel.h
  #include linux/module.h
  #include linux/of.h
 +#include linux/slab.h
  
  #include asm/cpuidle.h
  
  #include dt_idle_states.h
  
 +static DEFINE_PER_CPU(struct cpuidle_device, *cpuidle_arm_dev);
 +
  /*
   * arm_enter_idle_state - Programs CPU to enter the specified state
   *
 @@ -93,6 +96,7 @@ static const struct of_device_id arm_idle_state_match[] 
 __initconst = {
  static int __init arm_idle_init(void)
  {
   int cpu, ret;
 + struct cpuidle_device *dev;
   struct cpuidle_driver *drv = arm_idle_driver;
  
   /*
 @@ -105,18 +109,46 @@ static int __init arm_idle_init(void)
   if (ret = 0)
   return ret ? : -ENODEV;
  
 +
 + ret = cpuidle_register_driver(drv);
 + if (ret) {
 + pr_err(Failed to register cpuidle driver\n);
 + return ret;
 + }
 +
   /*
* Call arch CPU operations in order to initialize
* idle states suspend back-end specific data
*/
   for_each_possible_cpu(cpu) {
 +
   ret = arm_cpuidle_init(cpu);
 + /*
 +  * This cpu does not support any idle states
 +  */
 + if (ret == -ENOSYS)
 + continue;
 +
   if (ret) {
   pr_err(CPU %d failed to init idle CPU ops\n, cpu);
   return ret;
   }
 +
 + dev = kzalloc(sizeof(*dev), GFP_KERNEL);

devm_kzalloc?  Otherwise, failures could lead to lost memory.

 + if (!dev)
 + return -ENOMEM;
 +
 + dev-cpu = cpu;
 + ret = cpuidle_register_device(dev);
 + if (ret) {
 + pr_err(Failed to register cpuidle device for CPU %d\n,
 +cpu);
 + return ret;
 + }
 +
 + per_cpu(cpuidle_arm_dev, cpu) = dev;
   }
  
 - return cpuidle_register(drv, NULL);
 + return 0;
  }
  device_initcall(arm_idle_init);
 -- 
 2.1.0
 
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Re: [PATCH v6 1/2] DT: hwspinlock: Add binding documentation for Qualcomm hwmutex

[Andy Gross]

On Fri, Feb 27, 2015 at 02:30:16PM -0800, Bjorn Andersson wrote:
 Add binding documentation for the Qualcomm Hardware Mutex.
 
 Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
 ---

Looks fine.

Reviewed-by: Andy Gross agr...@codeaurora.org

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Re: [PATCH v2] spi: qup: Add DMA capabilities

[Andy Gross]

On Tue, Feb 24, 2015 at 06:08:54PM +0200, Stanimir Varbanov wrote:

snip

 
 yes, there is a potential race between atomic_inc and dma callback. I
 reordered these calls to save few checks, and now it returns to me.
 
 I imagine few options here:
 
  - reorder the dmaengine calls and atomic operations, i.e.
 call atomic_inc for rx and tx channels before corresponding
 dmaengine_submit and dmaengine_issue_pending.
 
  - have two different dma callbacks and two completions and waiting for
 the two.

This is probably the better solution.  The only thing you'll have to take into
consideration is that you may not have a RX DMA transactions.

 
  - manage to receive only one dma callback, i.e. the last transfer in
 case of presence of the rx_buf and tx_buf at the same time.

You use separate channels for the RX and TX, so as long as you have separate
callbacks, it shouldnt be a problem.


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Re: [PATCH] mfd: devicetree: bindings: Add Qualcomm RPM regulator subnodes

[Andy Gross]

On Thu, Jan 29, 2015 at 05:51:06PM -0800, Bjorn Andersson wrote:
 Add the regulator subnodes to the Qualcomm RPM MFD device tree bindings.
 
 Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
 ---

   #include dt-bindings/mfd/qcom-rpm.h
 @@ -66,5 +237,18 @@ frequencies.
  
   #address-cells = 1;
   #size-cells = 0;
 +
 + pm8921_smps1: pm8921-smps1 {
 + compatible = qcom,rpm-pm8921-smps;
 + reg = QCOM_RPM_PM8921_SMPS1;
 +
 + regulator-min-microvolt = 1225000;
 + regulator-max-microvolt = 1225000;
 + regulator-always-on;
 +
 + bias-pull-down;
 +
 + qcom,switch-mode-frequency = 320;
 + };
   };

My only comment here is that most (all but one) of the other mfd regulator
devices use regulators {}.  Still wonder if that's what we should do.

Otherwise,

Reviewed-by: Andy Gross agr...@codeaurora.org


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[Patch v4 0/2] Add Qualcomm ADM dmaengine driver

[Andy Gross]

This patch set introduces the dmaengine driver for the Qualcomm Application
Data Mover (ADM) DMA controller present on MSM8x60, APQ8064, and IPQ8064
devices.

The initial version of this driver will only support slave DMA operations
between system memory and peripherals.  Flow control via the CRCI (client rate
control interface) is supported and can be configured via device tree
configuration.  Flow control usage is required for some peripheral devices.

Changes from v3:
  - Remove .owner field

Changes from v2:
  - Removed extraneous achan variable from xlate function
  - Reworked crci check in slave_sg function
  - Added mux field to async_desc structure.
  - Reworked dma start function to use crci and mux values directly from
structure.
  - Added disable of clocks in probe error paths.
  - Changed to use #define for fixed number of channels.

Changes since v1:
  - Fixed various review comments
  - Fixed some descriptor programming issues.
  - Added single descriptors to support sub burst length transactions.
Selection of single or box descriptors depends on the sg length and burst
size.
  - Removed use of crci in the dmas property.  CRCI is now designated via the
slave_config structure and will be stored in slave_id.


Andy Gross (2):
  dt/bindings: qcom_adm: Fix channel specifiers
  dmaengine: Add ADM driver

 Documentation/devicetree/bindings/dma/qcom_adm.txt |   16 +-
 drivers/dma/Kconfig|   10 +
 drivers/dma/Makefile   |1 +
 drivers/dma/qcom_adm.c |  901 
 4 files changed, 918 insertions(+), 10 deletions(-)
 create mode 100644 drivers/dma/qcom_adm.c

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[Patch v4 2/2] dmaengine: Add ADM driver

[Andy Gross]

Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
controller found in the MSM8x60 and IPQ/APQ8064 platforms.

The ADM supports both memory to memory transactions and memory
to/from peripheral device transactions.  The controller also provides flow
control capabilities for transactions to/from peripheral devices.

The initial release of this driver supports slave transfers to/from peripherals
and also incorporates CRCI (client rate control interface) flow control.

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 drivers/dma/Kconfig|   10 +
 drivers/dma/Makefile   |1 +
 drivers/dma/qcom_adm.c |  901 
 3 files changed, 912 insertions(+)
 create mode 100644 drivers/dma/qcom_adm.c

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f2b2c4e..69bc15e 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -464,4 +464,14 @@ config QCOM_BAM_DMA
  Enable support for the QCOM BAM DMA controller.  This controller
  provides DMA capabilities for a variety of on-chip devices.
 
+config QCOM_ADM
+   tristate Qualcomm ADM support
+   depends on ARCH_QCOM || (COMPILE_TEST  OF  ARM)
+   select DMA_ENGINE
+   select DMA_VIRTUAL_CHANNELS
+   ---help---
+ Enable support for the Qualcomm ADM DMA controller.  This controller
+ provides DMA capabilities for both general purpose and on-chip
+ peripheral devices.
+
 endif
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 2022b54..3b7ead6 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -50,3 +50,4 @@ obj-y += xilinx/
 obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
 obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o
 obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
+obj-$(CONFIG_QCOM_ADM) += qcom_adm.o
diff --git a/drivers/dma/qcom_adm.c b/drivers/dma/qcom_adm.c
new file mode 100644
index 000..baea945
--- /dev/null
+++ b/drivers/dma/qcom_adm.c
@@ -0,0 +1,901 @@
+/*
+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include linux/kernel.h
+#include linux/io.h
+#include linux/init.h
+#include linux/slab.h
+#include linux/module.h
+#include linux/interrupt.h
+#include linux/dma-mapping.h
+#include linux/scatterlist.h
+#include linux/device.h
+#include linux/platform_device.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_irq.h
+#include linux/of_dma.h
+#include linux/reset.h
+#include linux/clk.h
+#include linux/dmaengine.h
+
+#include dmaengine.h
+#include virt-dma.h
+
+/* ADM registers - calculated from channel number and security domain */
+#define HI_CH_CMD_PTR(chan, ee)(4*chan + 0x20800*ee)
+#define HI_CH_RSLT(chan, ee)   (0x40 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE0(chan, ee)   (0x80 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE1(chan, ee)   (0xc0 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE2(chan, ee)   (0x100 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE3(chan, ee)   (0x140 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE4(chan, ee)   (0x180 + 4*chan + 0x20800*ee)
+#define HI_CH_FLUSH_STATE5(chan, ee)   (0x1c0 + 4*chan + 0x20800*ee)
+#define HI_CH_STATUS_SD(chan, ee)  (0x200 + 4*chan + 0x20800*ee)
+#define HI_CH_CONF(chan)   (0x240 + 4*chan)
+#define HI_CH_RSLT_CONF(chan, ee)  (0x300 + 4*chan + 0x20800*ee)
+#define HI_SEC_DOMAIN_IRQ_STATUS(ee)   (0x380 + 0x20800*ee)
+#define HI_CI_CONF(ci) (0x390 + 4*ci)
+#define HI_CRCI_CONF0  0x3d0
+#define HI_CRCI_CONF1  0x3d4
+#define HI_GP_CTL  0x3d8
+#define HI_CRCI_CTL(crci, ee)  (0x400 + 0x4*crci + 0x20800*ee)
+
+/* channel status */
+#define CH_STATUS_VALIDBIT(1)
+
+/* channel result */
+#define CH_RSLT_VALID  BIT(31)
+#define CH_RSLT_ERRBIT(3)
+#define CH_RSLT_FLUSH  BIT(2)
+#define CH_RSLT_TPDBIT(1)
+
+/* channel conf */
+#define CH_CONF_MPU_DISABLEBIT(11)
+#define CH_CONF_PERM_MPU_CONF  BIT(9)
+#define CH_CONF_FLUSH_RSLT_EN  BIT(8)
+#define CH_CONF_FORCE_RSLT_EN  BIT(7)
+#define CH_CONF_IRQ_EN BIT(6)
+
+/* channel result conf */
+#define CH_RSLT_CONF_FLUSH_EN  BIT(1)
+#define CH_RSLT_CONF_IRQ_ENBIT(0)
+
+/* CRCI CTL */
+#define CRCI_CTL_MUX_SEL   BIT(18)
+#define CRCI_CTL_RST   BIT(17)
+
+/* CI configuration */
+#define CI_RANGE_END(x)(x  24)
+#define CI_RANGE_START(x)  (x  16)
+#define CI_BURST_4_WORDS   0x4
+#define CI_BURST_8_WORDS

[Patch v4 1/2] dt/bindings: qcom_adm: Fix channel specifiers

[Andy Gross]

This patch removes the crci information from the dma channel property.  At least
one client device requires using more than one CRCI value for a channel.  This
does not match the current binding and the crci information needs to be removed.

Instead, the client device will provide this information via other means.

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 Documentation/devicetree/bindings/dma/qcom_adm.txt |   16 ++--
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt 
b/Documentation/devicetree/bindings/dma/qcom_adm.txt
index 9bcab91..38d45f8 100644
--- a/Documentation/devicetree/bindings/dma/qcom_adm.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt
@@ -4,8 +4,7 @@ Required properties:
 - compatible: must contain qcom,adm for IPQ/APQ8064 and MSM8960
 - reg: Address range for DMA registers
 - interrupts: Should contain one interrupt shared by all channels
-- #dma-cells: must be 2.  First cell denotes the channel number.  Second cell
-  denotes CRCI (client rate control interface) flow control assignment.
+- #dma-cells: must be 1.  First cell denotes the channel number.
 - clocks: Should contain the core clock and interface clock.
 - clock-names: Must contain core for the core clock and iface for the
   interface clock.
@@ -22,7 +21,7 @@ Example:
compatible = qcom,adm;
reg = 0x1830 0x10;
interrupts = 0 170 0;
-   #dma-cells = 2;
+   #dma-cells = 1;
 
clocks = gcc ADM0_CLK, gcc ADM0_PBUS_CLK;
clock-names = core, iface;
@@ -35,15 +34,12 @@ Example:
qcom,ee = 0;
};
 
-DMA clients must use the format descripted in the dma.txt file, using a three
+DMA clients must use the format descripted in the dma.txt file, using a two
 cell specifier for each channel.
 
-Each dmas request consists of 3 cells:
+Each dmas request consists of two cells:
  1. phandle pointing to the DMA controller
  2. channel number
- 3. CRCI assignment, if applicable.  If no CRCI flow control is required, use 
0.
-The CRCI is used for flow control.  It identifies the peripheral device 
that
-is the source/destination for the transferred data.
 
 Example:
 
@@ -56,7 +52,7 @@ Example:
 
cs-gpios = qcom_pinmux 20 0;
 
-   dmas = adm_dma 6 9,
-   adm_dma 5 10;
+   dmas = adm_dma 6,
+   adm_dma 5;
dma-names = rx, tx;
};
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Re: [Patch v3 2/2] dmaengine: Add ADM driver

[Andy Gross]

On Wed, Feb 11, 2015 at 05:28:14PM -0800, Stephen Boyd wrote:
 On 02/11, Andy Gross wrote:
  +static struct platform_driver adm_dma_driver = {
  +   .probe = adm_dma_probe,
  +   .remove = adm_dma_remove,
  +   .driver = {
  +   .name = adm-dma-engine,
  +   .owner = THIS_MODULE,
  +   .of_match_table = adm_of_match,
  +   },
  +};
 
 The THIS_MODULE script will find you. Am I a script?

darn it.  I skimmed right over that.  I'll resend.

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Re: [Patch v3 0/6] GSBI CRCI Autoconfiguration Support

[Andy Gross]

On Tue, Feb 10, 2015 at 11:57:27AM -0600, Kumar Gala wrote:
 
 On Feb 9, 2015, at 4:01 PM, Andy Gross agr...@codeaurora.org wrote:
 
  This patch set adds support for automatic configuration of GSBI DMA CRCI 
  values.
  
  DMA operations require that the ADM CRCI mux values be properly configured 
  in
  the TCSR (Top Control and Status Register) block.  During probing of a GSBI
  device, the client mode must be declared and this can be used to lookup the
  correct TCSR ADM CRCI MUX settings and then program them so that they are
  correct before any clients are populated.
  
  These patches add the TCSR as a syscon device and that allows the GSBI to
  access and manipulate the ADM CRCI MUX registers to correctly configure the
  values based on the GSBI port configuration.
  
  Changes since v2:
   - Use cell-index instead of alias to denote GSBI instance
  
  Changes since v1:
   - Fixed various review comments
  
  Andy Gross (6):
   soc: qcom: gsbi: Add support for ADM CRCI muxing
   mfd: qcom,tcsr: Add device tree binding for TCSR
   ARM: DT: apq8064: Add TCSR support
   ARM: DT: ipq8064: Add TCSR support
   ARM: DT: msm8660: Add TCSR support
   ARM: DT: msm8960: Add TCSR support
  
  .../devicetree/bindings/mfd/qcom,tcsr.txt  |   22 +++
  .../devicetree/bindings/soc/qcom/qcom,gsbi.txt |   14 +-
  arch/arm/boot/dts/qcom-apq8064.dtsi|   14 ++
  arch/arm/boot/dts/qcom-ipq8064.dtsi|   14 ++
  arch/arm/boot/dts/qcom-msm8660.dtsi|8 ++
  arch/arm/boot/dts/qcom-msm8960.dtsi|8 ++
  drivers/soc/qcom/Kconfig   |1 +
  drivers/soc/qcom/qcom_gsbi.c   |  152 
  
  8 files changed, 232 insertions(+), 1 deletion(-)
  create mode 100644 Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
 
 Series looks good, do we need a qcom_defconfig update to enable anything new 
 for this?
 
 - k

I'll send a followup to enable qcom_defconfig.

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Re: [Patch v3 0/6] GSBI CRCI Autoconfiguration Support

[Andy Gross]

snip

  
  Series looks good, do we need a qcom_defconfig update to enable anything 
  new for this?
  
  - k
 
 I'll send a followup to enable qcom_defconfig.
 

Correction:
Since I use a 'selects MFD_SYSCON' in the Kconfig we shouldn't need anything.

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[Patch v3 0/2] Add Qualcomm ADM dmaengine driver

[Andy Gross]

This patch set introduces the dmaengine driver for the Qualcomm Application
Data Mover (ADM) DMA controller present on MSM8x60, APQ8064, and IPQ8064
devices.

The initial version of this driver will only support slave DMA operations
between system memory and peripherals.  Flow control via the CRCI (client rate
control interface) is supported and can be configured via device tree
configuration.  Flow control usage is required for some peripheral devices.

Changes from v2:
  - Removed extraneous achan variable from xlate function
  - Reworked crci check in slave_sg function
  - Added mux field to async_desc structure.
  - Reworked dma start function to use crci and mux values directly from
structure.
  - Added disable of clocks in probe error paths.
  - Changed to use #define for fixed number of channels.

Changes since v1:
  - Fixed various review comments
  - Fixed some descriptor programming issues.
  - Added single descriptors to support sub burst length transactions.
Selection of single or box descriptors depends on the sg length and burst
size.
  - Removed use of crci in the dmas property.  CRCI is now designated via the
slave_config structure and will be stored in slave_id.

Andy Gross (2):
  dt/bindings: qcom_adm: Fix channel specifiers
  dmaengine: Add ADM driver

 Documentation/devicetree/bindings/dma/qcom_adm.txt |   16 +-
 drivers/dma/Kconfig|   10 +
 drivers/dma/Makefile   |1 +
 drivers/dma/qcom_adm.c |  902 
 4 files changed, 919 insertions(+), 10 deletions(-)
 create mode 100644 drivers/dma/qcom_adm.c

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[Patch v3 1/2] dt/bindings: qcom_adm: Fix channel specifiers

[Andy Gross]

This patch removes the crci information from the dma channel property.  At least
one client device requires using more than one CRCI value for a channel.  This
does not match the current binding and the crci information needs to be removed.

Instead, the client device will provide this information via other means.

Signed-off-by: Andy Gross agr...@codeaurora.org
---
 Documentation/devicetree/bindings/dma/qcom_adm.txt |   16 ++--
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt 
b/Documentation/devicetree/bindings/dma/qcom_adm.txt
index 9bcab91..38d45f8 100644
--- a/Documentation/devicetree/bindings/dma/qcom_adm.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt
@@ -4,8 +4,7 @@ Required properties:
 - compatible: must contain qcom,adm for IPQ/APQ8064 and MSM8960
 - reg: Address range for DMA registers
 - interrupts: Should contain one interrupt shared by all channels
-- #dma-cells: must be 2.  First cell denotes the channel number.  Second cell
-  denotes CRCI (client rate control interface) flow control assignment.
+- #dma-cells: must be 1.  First cell denotes the channel number.
 - clocks: Should contain the core clock and interface clock.
 - clock-names: Must contain core for the core clock and iface for the
   interface clock.
@@ -22,7 +21,7 @@ Example:
compatible = qcom,adm;
reg = 0x1830 0x10;
interrupts = 0 170 0;
-   #dma-cells = 2;
+   #dma-cells = 1;
 
clocks = gcc ADM0_CLK, gcc ADM0_PBUS_CLK;
clock-names = core, iface;
@@ -35,15 +34,12 @@ Example:
qcom,ee = 0;
};
 
-DMA clients must use the format descripted in the dma.txt file, using a three
+DMA clients must use the format descripted in the dma.txt file, using a two
 cell specifier for each channel.
 
-Each dmas request consists of 3 cells:
+Each dmas request consists of two cells:
  1. phandle pointing to the DMA controller
  2. channel number
- 3. CRCI assignment, if applicable.  If no CRCI flow control is required, use 
0.
-The CRCI is used for flow control.  It identifies the peripheral device 
that
-is the source/destination for the transferred data.
 
 Example:
 
@@ -56,7 +52,7 @@ Example:
 
cs-gpios = qcom_pinmux 20 0;
 
-   dmas = adm_dma 6 9,
-   adm_dma 5 10;
+   dmas = adm_dma 6,
+   adm_dma 5;
dma-names = rx, tx;
};
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