Re: [PATCH 3/3] arm: dts: bcm5301x: Add syscon based reboot in DT
On Fri, Dec 18, 2015 at 10:44:28PM +0100, Arnd Bergmann wrote:
> On Friday 18 December 2015 16:37:56 Jon Mason wrote:
> > + cru: cru@1800c184 {
> > + compatible = "syscon";
> > + reg = <0x1800c184 0xc>;
> > + };
>
> It's unusual for a device to start at such an odd address. Are you sure
> it's not a larger device starting at 0x1800c000 or 0x1800?
The CRU (Clock and Reset Unit) starts at 0x1800c100, with the
following layout:
CRU Clock Management at 0x1800c100-0x1800c180
CRU Reset at 0x1800c184
CRU Period Sample Clock at 0x1800c188
CRU Interrupt register at 0x1800c18c
CRU MDIO Control at 0x1800c190
CRU GPIO at 0x1800c1c0-0x1800c1e0
CRU SDIO 0x1800c200-0x1800c214
CRU RoboSW Interrupt at 0x1800c280
CRU Straps Control at 0x1800c2a0
The clock driver is already referencing the registers between
0x1800c100-0x1800c180, and the GPIO driver is referencing registers
between 0x1800c1c0-0x1800c1e0.
The reset part of the syscon seems to be the only useful thing in this
block. Am I approaching this incorrectly?
> Also, please provide a more specific compatible string based on the
> name of the device in the data sheet. The node name in contrast should
> be more generic, e.g.
>
> cru: system-controller@1800c000 {
> compatible = "brcm,bcm53010-cru", "syscon";
This is very similar between the NS and NSP (and NS2) platforms. I'll
verify the layout and see if this can't be "brcm,iproc-cru" or
something similar.
Thanks,
Jon
> reg = <0x1800c000 0x400>; /* whatever the data sheet says */
> };
>
>
> Arnd
>
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[PATCH 1/3] ARM: dts: bcm5301x: Add TWD WD Support to DT
Add support for the ARM TWD Watchdog to the bcm5301x device tree. The
ARM TWD timer allocated the register space for the WDT, so this patch
necessitated shrinking that. Also, the GIC masks were added for these.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm5301x.dtsi | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 65a1309..c31fafe 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -66,10 +66,19 @@
clocks = <&periph_clk>;
};
- local-timer@20600 {
+ twd-timer@20600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x20600 0x100>;
- interrupts = ;
+ reg = <0x20600 0x20>;
+ interrupts = ;
+ clocks = <&periph_clk>;
+ };
+
+ twd-watchdog@20620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0x20620 0x20>;
+ interrupts = ;
clocks = <&periph_clk>;
};
--
1.9.1
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[PATCH 3/3] arm: dts: bcm5301x: Add syscon based reboot in DT
Add the ability to reboot via a reset of the processor. This is
achieved via a write of 0x39 to the CRU Reset Register. Unfortunately,
this only resets the core and not the other IP blocks. So if possible,
other methods should be used on the individual boards.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm5301x.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 553b2ec..2a482ec 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -246,6 +246,18 @@
"sata2";
};
+ cru: cru@1800c184 {
+ compatible = "syscon";
+ reg = <0x1800c184 0xc>;
+ };
+
+ reboot@1800c184 {
+ compatible ="syscon-reboot";
+ regmap = <&cru>;
+ offset = <0>;
+ mask = <0x39>;
+ };
+
nand: nand@18028000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1",
"brcm,brcmnand";
reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
--
1.9.1
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[PATCH 2/3] ARM: dts: bcm5301x: Add I2C support to the DT
Add I2C support to the bcm5301x Device Tree. Since no driver changes
are needed to enable this hardware, only the device tree changes are
required to make this functional.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm5301x.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index c31fafe..553b2ec 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -218,6 +218,15 @@
};
};
+ i2c0: i2c@18009000 {
+ compatible = "brcm,iproc-i2c";
+ reg = <0x18009000 0x50>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <10>;
+ };
+
lcpll0: lcpll0@1800c100 {
#clock-cells = <1>;
compatible = "brcm,nsp-lcpll0";
--
1.9.1
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Re: [PATCH v4 5/5] ARM: BCM: Add SMP support for Broadcom 4708
On Thu, Dec 03, 2015 at 04:08:36PM -0500, Jon Mason wrote:
> On Wed, Dec 02, 2015 at 04:03:03PM +0100, Hauke Mehrtens wrote:
> > On 12/01/2015 05:24 PM, Kapil Hali wrote:
> > > From: Jon Mason
> > >
> > > Add SMP support for Broadcom's 4708 SoCs.
> > >
> > > Signed-off-by: Jon Mason
> > > Acked-by: Hauke Mehrtens
> > > Tested-by: Hauke Mehrtens
> > > Signed-off-by: Kapil Hali
> > > ---
> > > arch/arm/boot/dts/bcm4708.dtsi | 2 ++
> > > arch/arm/mach-bcm/Kconfig | 1 +
> > > arch/arm/mach-bcm/Makefile | 3 +++
> > > 3 files changed, 6 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/bcm4708.dtsi
> > > b/arch/arm/boot/dts/bcm4708.dtsi
> > > index 31141e8..eed4dd1 100644
> > > --- a/arch/arm/boot/dts/bcm4708.dtsi
> > > +++ b/arch/arm/boot/dts/bcm4708.dtsi
> > > @@ -15,6 +15,7 @@
> > > cpus {
> > > #address-cells = <1>;
> > > #size-cells = <0>;
> > > + enable-method = "brcm,bcm-nsp-smp";
> > >
> > > cpu@0 {
> > > device_type = "cpu";
> > > @@ -27,6 +28,7 @@
> > > device_type = "cpu";
> > > compatible = "arm,cortex-a9";
> > > next-level-cache = <&L2>;
> > > + secondary-boot-reg = <0x0400>;
> > > reg = <0x1>;
> > > };
> > > };
> > > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> > > index 83765a0..e85246f 100644
> > > --- a/arch/arm/mach-bcm/Kconfig
> > > +++ b/arch/arm/mach-bcm/Kconfig
> > > @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
> > > config ARCH_BCM_5301X
> > > bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
> > > select ARCH_BCM_IPROC
> > > + select HAVE_SMP
> > > help
> > > Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
> > >
> >
> > When applying this patch please make sure it is correctly applied this
> > patch causes some problems here:
> >
> > http://www.spinics.net/lists/arm-kernel/msg462137.html
> >
> > > diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
> > > index 5193a25..7d66515 100644
> > > --- a/arch/arm/mach-bcm/Makefile
> > > +++ b/arch/arm/mach-bcm/Makefile
> > > @@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
> > >
> > > # BCM5301X
> > > obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
> > > +ifeq ($(CONFIG_ARCH_BCM_5301X),y)
> > > +obj-$(CONFIG_SMP)+= platsmp.o
> > > +endif
> > >
> > > # BCM63XXx
> > > ifeq ($(CONFIG_ARCH_BCM_63XX),y)
> > >
> >
> > I am getting this on a Northstar 1 / BCM4708:
> >
> > [ 0.137634] CPU0: thread -1, cpu 0, socket 0, mpidr 8000
> > [ 0.143643] Setting up static identity map for 0x82a0 - 0x82d4
> > [ 0.189772] CPU1: thread -1, cpu 1, socket 0, mpidr 8001
> > [ 0.189861] Brought up 2 CPUs
> > [ 0.198845] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
> > [ 0.205446] CPU: WARNING: CPU(s) started in wrong/inconsistent modes
> > (primary CPU mode 0x13)
> > [ 0.214167] CPU: This may indicate a broken bootloader or firmware.
> >
> > I assume that this is correct and the bootloader is just broken, it uses
> > this bootloader: "CFE for Foxconn Router version: v1.0.14", I haven't
> > noticed any problems, so it is ok for me.
>
> On my 4708 SVK, I see the same issue
>
> [0.090877] CPU: Testing write buffer coherency: ok
> [0.091231] CPU0: thread -1, cpu 0, socket 0, mpidr 8000
> [0.091377] Setting up static identity map for 0x82a0 - 0x82f8
> [0.130146] CPU1: thread -1, cpu 1, socket 0, mpidr 8001
> [0.130251] Brought up 2 CPUs
> [0.130323] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
> [0.130345] CPU: WARNING: CPU(s) started in wrong/inconsistent modes
> (primary CPU mode 0x13)
> [0.130374] CPU: This may indicate a broken bootloader or firmware.
>
> I'll investigate it more and see if I can bottom out on the cause.
I looked at previous versions of this patch, and the issue appears to
be present there as well. I'm not sure why I didn't notice it before.
I don't think "fixing" CFE is an option. Should we investigate the
possibility of setting the CPU mode of CPU1 in the early_boot of
Linux?
Thanks,
Jon
>
> Thanks,
> Jon
>
>
> >
> > Hauke
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Re: [PATCH v4 5/5] ARM: BCM: Add SMP support for Broadcom 4708
On Wed, Dec 02, 2015 at 04:03:03PM +0100, Hauke Mehrtens wrote:
> On 12/01/2015 05:24 PM, Kapil Hali wrote:
> > From: Jon Mason
> >
> > Add SMP support for Broadcom's 4708 SoCs.
> >
> > Signed-off-by: Jon Mason
> > Acked-by: Hauke Mehrtens
> > Tested-by: Hauke Mehrtens
> > Signed-off-by: Kapil Hali
> > ---
> > arch/arm/boot/dts/bcm4708.dtsi | 2 ++
> > arch/arm/mach-bcm/Kconfig | 1 +
> > arch/arm/mach-bcm/Makefile | 3 +++
> > 3 files changed, 6 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
> > index 31141e8..eed4dd1 100644
> > --- a/arch/arm/boot/dts/bcm4708.dtsi
> > +++ b/arch/arm/boot/dts/bcm4708.dtsi
> > @@ -15,6 +15,7 @@
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > + enable-method = "brcm,bcm-nsp-smp";
> >
> > cpu@0 {
> > device_type = "cpu";
> > @@ -27,6 +28,7 @@
> > device_type = "cpu";
> > compatible = "arm,cortex-a9";
> > next-level-cache = <&L2>;
> > + secondary-boot-reg = <0x0400>;
> > reg = <0x1>;
> > };
> > };
> > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> > index 83765a0..e85246f 100644
> > --- a/arch/arm/mach-bcm/Kconfig
> > +++ b/arch/arm/mach-bcm/Kconfig
> > @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
> > config ARCH_BCM_5301X
> > bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
> > select ARCH_BCM_IPROC
> > + select HAVE_SMP
> > help
> > Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
> >
>
> When applying this patch please make sure it is correctly applied this
> patch causes some problems here:
>
> http://www.spinics.net/lists/arm-kernel/msg462137.html
>
> > diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
> > index 5193a25..7d66515 100644
> > --- a/arch/arm/mach-bcm/Makefile
> > +++ b/arch/arm/mach-bcm/Makefile
> > @@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835)+= board_bcm2835.o
> >
> > # BCM5301X
> > obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
> > +ifeq ($(CONFIG_ARCH_BCM_5301X),y)
> > +obj-$(CONFIG_SMP) += platsmp.o
> > +endif
> >
> > # BCM63XXx
> > ifeq ($(CONFIG_ARCH_BCM_63XX),y)
> >
>
> I am getting this on a Northstar 1 / BCM4708:
>
> [ 0.137634] CPU0: thread -1, cpu 0, socket 0, mpidr 8000
> [ 0.143643] Setting up static identity map for 0x82a0 - 0x82d4
> [ 0.189772] CPU1: thread -1, cpu 1, socket 0, mpidr 8001
> [ 0.189861] Brought up 2 CPUs
> [ 0.198845] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
> [ 0.205446] CPU: WARNING: CPU(s) started in wrong/inconsistent modes
> (primary CPU mode 0x13)
> [ 0.214167] CPU: This may indicate a broken bootloader or firmware.
>
> I assume that this is correct and the bootloader is just broken, it uses
> this bootloader: "CFE for Foxconn Router version: v1.0.14", I haven't
> noticed any problems, so it is ok for me.
On my 4708 SVK, I see the same issue
[0.090877] CPU: Testing write buffer coherency: ok
[0.091231] CPU0: thread -1, cpu 0, socket 0, mpidr 8000
[0.091377] Setting up static identity map for 0x82a0 - 0x82f8
[0.130146] CPU1: thread -1, cpu 1, socket 0, mpidr 8001
[0.130251] Brought up 2 CPUs
[0.130323] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
[0.130345] CPU: WARNING: CPU(s) started in wrong/inconsistent modes
(primary CPU mode 0x13)
[0.130374] CPU: This may indicate a broken bootloader or firmware.
I'll investigate it more and see if I can bottom out on the cause.
Thanks,
Jon
>
> Hauke
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Re: Preprocessor arithmetic in dtsi files (base + offset)
On 26/11/2015 17:23, Geert Uytterhoeven wrote:
> I guess this would work, too?
>
> scu_container@2000 {
> compatible = "simple-bus";
>
> ranges = <0x0 0x2000 0x1>;
> #address-cells = <1>;
> #size-cells = <1>;
>
> scu: scu@0 {
> compatible = "arm,cortex-a9-scu";
> reg = <0x 0x100>;
>
> gic: interrupt-controller@1000 {
> compatible = "arm,cortex-a9-gic";
> reg = <0x1000 0x1000>, <0x0100 0x0100>;
>
> twd-timer@0600 {
> compatible = "arm,cortex-a9-twd-timer";
> reg = <0x0600 0x10>;
> };
>
> No more explicit arithmetic needed, just substitute "2000".
I like it! Only one address to change in the next chip.
Minimizes the risk of missing something.
(I see that armada did something similar, but they also grouped
unrelated stuff. And bcm5301x did exactly what you suggested.)
Wondering if there are macro definitions for the intra-SCU offsets?
So I could have symbolic names, such as
twd-timer@0600 {
reg =
Didn't see anything appropriate in include and arch/arm.
Should I include my own definitions at the top of the dtsi?
Regards.
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Re: Preprocessor arithmetic in dtsi files (base + offset)
On 26/11/2015 14:59, Russell King - ARM Linux wrote:
> On Thu, Nov 26, 2015 at 02:16:16PM +0100, Mason wrote:
>> #define SCU_BASE 0x2000
>>
>> scu: scu@XXX {
>> compatible = "arm,cortex-a9-scu";
>> reg = ;
>>
>> gic: interrupt-controller@XXX {
>> compatible = "arm,cortex-a9-gic";
>> reg = , ;
>
> You don't get preprocessor arithmetic here. What you get is this passed
> to DTC:
>
> reg = <0x2000+0x1000 0x1000>...
>
> The only time the preprocessor does arithmetic is when it needs to
> evaluate an expression, eg, in an #if statement.
Doh! Brain malfunction. No arithmetic indeed.
Working with the preprocessor would have to involve token-pasting.
#define SCU_BASE(OFFSET)2000##OFFSET
#define SCU_BASEX(OFFSET) 0x2000##OFFSET
gic: interrupt-controller@SCU_BASE(1000) {
reg = , ;
};
My very own abomination!
Regards.
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Preprocessor arithmetic in dtsi files (base + offset)
Hello,
In the device tree for my ARM platform, I have several nodes with
addresses within the SCU block:
scu: scu@2000 {
compatible = "arm,cortex-a9-scu";
reg = <0x2000 0x100>;
gic: interrupt-controller@20001000 {
compatible = "arm,cortex-a9-gic";
reg = <0x20001000 0x1000>, <0x2100 0x0100>;
twd-timer@2600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x2600 0x10>;
Can I use preprocessor arithmetic to abstract the base address,
as would be done in C?
#define SCU_BASE 0x2000
scu: scu@XXX {
compatible = "arm,cortex-a9-scu";
reg = ;
gic: interrupt-controller@XXX {
compatible = "arm,cortex-a9-gic";
reg = , ;
twd-timer@XXX {
compatible = "arm,cortex-a9-twd-timer";
reg = ;
Are the @XXX important? Can they be removed altogether?
Regards.
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[PATCH v3 0/3] ARM: dts: add support for NS, NSP, and NS2 clocks
Changes in v3: Tweaked the NSP entry names, per Ray Jui Changes in v2: Rebased off of outstanding NSP DT patches and tweaked the entry names per Ray Jui This patch series adds device tree support for the Broadcom Northstar, Northstar Plus, and Northstar 2 clocks. Last sent as an RFC (see https://lkml.org/lkml/2015/10/13/882) due to the inability to merge because of the driver dependencies. Those necessary driver changes were merged into 4.4. All comments have been addressed and it is ready to be pulled in. Jon Mason (3): ARM: dts: enable clock support for BCM5301X ARM: dts: enable clock support for Broadcom NSP ARM64: dts: enable clock support for Broadcom NS2 arch/arm/boot/dts/bcm-nsp.dtsi| 81 -- arch/arm/boot/dts/bcm5301x.dtsi | 92 +++ arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 +- 3 files changed, 216 insertions(+), 37 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/3] ARM: dts: enable clock support for BCM5301X
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar SoCs.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm5301x.dtsi | 92 +++--
1 file changed, 71 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 6f50f67..65a1309 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -8,6 +8,7 @@
* Licensed under the GNU/GPL. See COPYING for details.
*/
+#include
#include
#include
#include
@@ -27,7 +28,7 @@
compatible = "ns16550";
reg = <0x0300 0x100>;
interrupts = ;
- clock-frequency = <1>;
+ clocks = <&iprocslow>;
status = "disabled";
};
@@ -35,48 +36,55 @@
compatible = "ns16550";
reg = <0x0400 0x100>;
interrupts = ;
- clock-frequency = <1>;
+ clocks = <&iprocslow>;
status = "disabled";
};
};
mpcore {
compatible = "simple-bus";
- ranges = <0x 0x1902 0x3000>;
+ ranges = <0x 0x1900 0x00023000>;
#address-cells = <1>;
#size-cells = <1>;
- scu@ {
+ a9pll: arm_clk@0 {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x0 0x1000>;
+ };
+
+ scu@2 {
compatible = "arm,cortex-a9-scu";
- reg = <0x 0x100>;
+ reg = <0x2 0x100>;
};
- timer@0200 {
+ timer@20200 {
compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
+ reg = <0x20200 0x100>;
interrupts = ;
- clocks = <&clk_periph>;
+ clocks = <&periph_clk>;
};
- local-timer@0600 {
+ local-timer@20600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x0600 0x100>;
+ reg = <0x20600 0x100>;
interrupts = ;
- clocks = <&clk_periph>;
+ clocks = <&periph_clk>;
};
- gic: interrupt-controller@1000 {
+ gic: interrupt-controller@21000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
};
- L2: cache-controller@2000 {
+ L2: cache-controller@22000 {
compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
+ reg = <0x22000 0x1000>;
cache-unified;
arm,shared-override;
prefetch-data = <1>;
@@ -94,14 +102,37 @@
clocks {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ ranges;
- /* As long as we do not have a real clock driver us this
-* fixed clock */
- clk_periph: periph {
+ osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock
[PATCH v3 2/3] ARM: dts: enable clock support for Broadcom NSP
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar Plus SoC
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 81 ++
1 file changed, 66 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index b74438c..d9bfc56 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -32,6 +32,7 @@
#include
#include
+#include
#include "skeleton.dtsi"
@@ -42,7 +43,7 @@
mpcore {
compatible = "simple-bus";
- ranges = <0x 0x1902 0x3000>;
+ ranges = <0x 0x1900 0x00023000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -58,41 +59,48 @@
};
};
- timer@0200 {
+ a9pll: arm_clk@0 {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x0 0x1000>;
+ };
+
+ timer@20200 {
compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
+ reg = <0x20200 0x100>;
interrupts = ;
clocks = <&periph_clk>;
};
- twd-timer@0600 {
+ twd-timer@20600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x0600 0x20>;
+ reg = <0x20600 0x20>;
interrupts = ;
clocks = <&periph_clk>;
};
- twd-watchdog@0620 {
+ twd-watchdog@20620 {
compatible = "arm,cortex-a9-twd-wdt";
- reg = <0x0620 0x20>;
+ reg = <0x20620 0x20>;
interrupts = ;
clocks = <&periph_clk>;
};
- gic: interrupt-controller@1000 {
+ gic: interrupt-controller@21000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
};
L2: l2-cache {
compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
+ reg = <0x22000 0x1000>;
cache-unified;
cache-level = <2>;
};
@@ -103,10 +111,34 @@
#size-cells = <1>;
ranges;
- periph_clk: periph_clk {
+ osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ periph_clk: periph_clk {
#clock-cells = <0>;
- clock-frequency = <5>;
+ compatible = "fixed-factor-clock";
+ clocks = <&a9pll>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
};
@@ -120,7 +152,7 @@
compatible = "ns16550a";
reg = <0x0300 0x100>;
interrupts = ;
- clock-frequency = <62499840>;
+ clocks = <&osc>;
status = "disabled";
[PATCH v3 3/3] ARM64: dts: enable clock support for Broadcom NS2
Add device tree entries for clock support for Broadcom Northstar 2 SoC
Signed-off-by: Jon Mason
---
arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 ++-
1 file changed, 79 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 9610822..a510d3a 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -31,6 +31,7 @@
*/
#include
+#include
/memreserve/ 0x84b0 0x0008;
@@ -109,6 +110,33 @@
<&A57_3>;
};
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -156,6 +184,56 @@
mmu-masters;
};
+ lcpll_ddr: lcpll_ddr@6501d058 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ddr";
+ reg = <0x6501d058 0x20>,
+ <0x6501c020 0x4>,
+ <0x6501d04c 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ddr", "pcie_sata_usb",
+"ddr", "ddr_ch2_unused",
+"ddr_ch3_unused", "ddr_ch4_unused",
+"ddr_ch5_unused";
+ };
+
+ lcpll_ports: lcpll_ports@6501d078 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ports";
+ reg = <0x6501d078 0x20>,
+ <0x6501c020 0x4>,
+ <0x6501d054 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ports", "wan", "rgmii",
+"ports_ch2_unused",
+"ports_ch3_unused",
+"ports_ch4_unused",
+"ports_ch5_unused";
+ };
+
+ genpll_scr: genpll_scr@6501d098 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-scr";
+ reg = <0x6501d098 0x32>,
+ <0x6501c020 0x4>,
+ <0x6501d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_scr", "scr", "fs",
+"audio_ref", "scr_ch3_unused",
+"scr_ch4_unused", "scr_ch5_unused";
+ };
+
+ genpll_sw: genpll_sw@6501d0c4 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-sw";
+ reg = <0x6501d0c4 0x32>,
+ <0x6501c020 0x4>,
+ <0x6501d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_sw", "rpe", "250", "nic",
+"chimp", "port", "sdio";
+ };
+
crmu: crmu@65024000 {
compatible = "syscon";
reg = <0x65024000 0x100>;
@@ -204,7 +282,7 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <23961600>;
+ clocks = <&osc>;
status = "disabled";
};
--
1.9.1
--
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Re: [PATCH v2 2/3] ARM: dts: enable clock support for Broadcom NSP
On Thu, Nov 19, 2015 at 03:40:04PM -0800, Ray Jui wrote:
>
>
> On 11/19/2015 3:05 PM, Jon Mason wrote:
> >Replace current device tree dummy clocks with real clock support for
> >Broadcom Northstar Plus SoC
> >
> >Signed-off-by: Jon Mason
> >---
> > arch/arm/boot/dts/bcm-nsp.dtsi | 77
> > +++---
> > 1 file changed, 64 insertions(+), 13 deletions(-)
> >
> >diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> >index b74438c..361c2a6 100644
> >--- a/arch/arm/boot/dts/bcm-nsp.dtsi
> >+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> >@@ -32,6 +32,7 @@
> >
> > #include
> > #include
> >+#include
> >
> > #include "skeleton.dtsi"
> >
> >@@ -42,7 +43,7 @@
> >
> > mpcore {
> > compatible = "simple-bus";
> >-ranges = <0x 0x1902 0x3000>;
> >+ranges = <0x 0x1900 0x00023000>;
> > #address-cells = <1>;
> > #size-cells = <1>;
> >
> >@@ -58,16 +59,23 @@
> > };
> > };
> >
> >+a9pll: arm_clk@ {
> >+#clock-cells = <0>;
> >+compatible = "brcm,nsp-armpll";
> >+clocks = <&osc>;
> >+reg = <0x 0x1000>;
> >+};
> >+
> > timer@0200 {
>
> timer@20200. Or is this addressed in another patch? I completely
> lose track of these
No, you are correct. The names need to be updated as well with the
new offsets. New series to follow.
Thanks,
Jon
>
> > compatible = "arm,cortex-a9-global-timer";
> >-reg = <0x0200 0x100>;
> >+reg = <0x20200 0x100>;
> > interrupts = ;
> > clocks = <&periph_clk>;
> > };
> >
> > twd-timer@0600 {
>
> twd-timer@20600
>
> > compatible = "arm,cortex-a9-twd-timer";
> >-reg = <0x0600 0x20>;
> >+reg = <0x20600 0x20>;
> > interrupts = > IRQ_TYPE_LEVEL_HIGH)>;
> > clocks = <&periph_clk>;
> >@@ -75,7 +83,7 @@
> >
> > twd-watchdog@0620 {
>
> same here
>
> > compatible = "arm,cortex-a9-twd-wdt";
> >-reg = <0x0620 0x20>;
> >+reg = <0x20620 0x20>;
> > interrupts = > IRQ_TYPE_LEVEL_HIGH)>;
> > clocks = <&periph_clk>;
> >@@ -86,13 +94,13 @@
> > #interrupt-cells = <3>;
> > #address-cells = <0>;
> > interrupt-controller;
> >-reg = <0x1000 0x1000>,
> >- <0x0100 0x100>;
> >+reg = <0x21000 0x1000>,
> >+ <0x20100 0x100>;
> > };
> >
> > L2: l2-cache {
> > compatible = "arm,pl310-cache";
> >-reg = <0x2000 0x1000>;
> >+reg = <0x22000 0x1000>;
> > cache-unified;
> > cache-level = <2>;
> > };
> >@@ -103,10 +111,34 @@
> > #size-cells = <1>;
> > ranges;
> >
> >-periph_clk: periph_clk {
> >+osc: oscillator {
> >+#clock-cells = <0>;
> > compatible = "fixed-clock";
> >+clock-frequency = <2500>;
> >+};
> >+
> >+iprocmed: iprocmed {
> >+#clock-cells = <0>;
> >+compatible = "fixed-factor-clock";
> >+clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
> >+clock-div = <2>;
> >+clock-mult = <1>;
> >+};
> >+
> >+iprocslow: iprocslow {
> >+#clock-cells = <0>;
> >+
Re: [PATCH 2/2] irqchip: add support for Sigma Designs SMP86xx interrupt controller
On 19/11/2015 19:33, Mans Rullgard wrote: > This adds support for the secondary interrupt controller used in Sigma > Designs SMP86xx and SMP87xx chips. > > Signed-off-by: Mans Rullgard > --- > drivers/irqchip/Kconfig | 5 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-tangox.c | 232 > +++ > 3 files changed, 238 insertions(+) > create mode 100644 drivers/irqchip/irq-tangox.c > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > index 4d7294e..baf3345 100644 > --- a/drivers/irqchip/Kconfig > +++ b/drivers/irqchip/Kconfig > @@ -193,3 +193,8 @@ config IRQ_MXS > def_bool y if MACH_ASM9260 || ARCH_MXS > select IRQ_DOMAIN > select STMP_DEVICE > + > +config TANGOX_IRQ Question: Kevin Hilman said I should use tango instead of tangox for the arch directory. Does that advice extend to Kconfig names? Regards. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/3] ARM: dts: enable clock support for Broadcom NSP
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar Plus SoC
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 77 +++---
1 file changed, 64 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index b74438c..361c2a6 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -32,6 +32,7 @@
#include
#include
+#include
#include "skeleton.dtsi"
@@ -42,7 +43,7 @@
mpcore {
compatible = "simple-bus";
- ranges = <0x 0x1902 0x3000>;
+ ranges = <0x 0x1900 0x00023000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -58,16 +59,23 @@
};
};
+ a9pll: arm_clk@ {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x 0x1000>;
+ };
+
timer@0200 {
compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
+ reg = <0x20200 0x100>;
interrupts = ;
clocks = <&periph_clk>;
};
twd-timer@0600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x0600 0x20>;
+ reg = <0x20600 0x20>;
interrupts = ;
clocks = <&periph_clk>;
@@ -75,7 +83,7 @@
twd-watchdog@0620 {
compatible = "arm,cortex-a9-twd-wdt";
- reg = <0x0620 0x20>;
+ reg = <0x20620 0x20>;
interrupts = ;
clocks = <&periph_clk>;
@@ -86,13 +94,13 @@
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
};
L2: l2-cache {
compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
+ reg = <0x22000 0x1000>;
cache-unified;
cache-level = <2>;
};
@@ -103,10 +111,34 @@
#size-cells = <1>;
ranges;
- periph_clk: periph_clk {
+ osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ periph_clk: periph_clk {
#clock-cells = <0>;
- clock-frequency = <5>;
+ compatible = "fixed-factor-clock";
+ clocks = <&a9pll>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
};
@@ -118,17 +150,17 @@
uart0: serial@0300 {
compatible = "ns16550a";
- reg = <0x0300 0x100>;
+ reg = <0x000300 0x100>;
interrupts = ;
- clock-frequency = <62499840>;
+ clocks = <&osc>;
status = "disabled";
};
uart1: serial@0400 {
compatible = "ns16550a";
- reg = <0x0400 0x100>;
+ reg = <0x000400 0x100&g
[PATCH v2 1/3] ARM: dts: enable clock support for BCM5301X
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar SoCs.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm5301x.dtsi | 92 +++--
1 file changed, 71 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 6f50f67..65a1309 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -8,6 +8,7 @@
* Licensed under the GNU/GPL. See COPYING for details.
*/
+#include
#include
#include
#include
@@ -27,7 +28,7 @@
compatible = "ns16550";
reg = <0x0300 0x100>;
interrupts = ;
- clock-frequency = <1>;
+ clocks = <&iprocslow>;
status = "disabled";
};
@@ -35,48 +36,55 @@
compatible = "ns16550";
reg = <0x0400 0x100>;
interrupts = ;
- clock-frequency = <1>;
+ clocks = <&iprocslow>;
status = "disabled";
};
};
mpcore {
compatible = "simple-bus";
- ranges = <0x 0x1902 0x3000>;
+ ranges = <0x 0x1900 0x00023000>;
#address-cells = <1>;
#size-cells = <1>;
- scu@ {
+ a9pll: arm_clk@0 {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x0 0x1000>;
+ };
+
+ scu@2 {
compatible = "arm,cortex-a9-scu";
- reg = <0x 0x100>;
+ reg = <0x2 0x100>;
};
- timer@0200 {
+ timer@20200 {
compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
+ reg = <0x20200 0x100>;
interrupts = ;
- clocks = <&clk_periph>;
+ clocks = <&periph_clk>;
};
- local-timer@0600 {
+ local-timer@20600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x0600 0x100>;
+ reg = <0x20600 0x100>;
interrupts = ;
- clocks = <&clk_periph>;
+ clocks = <&periph_clk>;
};
- gic: interrupt-controller@1000 {
+ gic: interrupt-controller@21000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
};
- L2: cache-controller@2000 {
+ L2: cache-controller@22000 {
compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
+ reg = <0x22000 0x1000>;
cache-unified;
arm,shared-override;
prefetch-data = <1>;
@@ -94,14 +102,37 @@
clocks {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ ranges;
- /* As long as we do not have a real clock driver us this
-* fixed clock */
- clk_periph: periph {
+ osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock
[PATCH v2 3/3] ARM64: dts: enable clock support for Broadcom NS2
Add device tree entries for clock support for Broadcom Northstar 2 SoC
Signed-off-by: Jon Mason
---
arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 ++-
1 file changed, 79 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 9610822..a510d3a 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -31,6 +31,7 @@
*/
#include
+#include
/memreserve/ 0x84b0 0x0008;
@@ -109,6 +110,33 @@
<&A57_3>;
};
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -156,6 +184,56 @@
mmu-masters;
};
+ lcpll_ddr: lcpll_ddr@6501d058 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ddr";
+ reg = <0x6501d058 0x20>,
+ <0x6501c020 0x4>,
+ <0x6501d04c 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ddr", "pcie_sata_usb",
+"ddr", "ddr_ch2_unused",
+"ddr_ch3_unused", "ddr_ch4_unused",
+"ddr_ch5_unused";
+ };
+
+ lcpll_ports: lcpll_ports@6501d078 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ports";
+ reg = <0x6501d078 0x20>,
+ <0x6501c020 0x4>,
+ <0x6501d054 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ports", "wan", "rgmii",
+"ports_ch2_unused",
+"ports_ch3_unused",
+"ports_ch4_unused",
+"ports_ch5_unused";
+ };
+
+ genpll_scr: genpll_scr@6501d098 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-scr";
+ reg = <0x6501d098 0x32>,
+ <0x6501c020 0x4>,
+ <0x6501d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_scr", "scr", "fs",
+"audio_ref", "scr_ch3_unused",
+"scr_ch4_unused", "scr_ch5_unused";
+ };
+
+ genpll_sw: genpll_sw@6501d0c4 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-sw";
+ reg = <0x6501d0c4 0x32>,
+ <0x6501c020 0x4>,
+ <0x6501d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_sw", "rpe", "250", "nic",
+"chimp", "port", "sdio";
+ };
+
crmu: crmu@65024000 {
compatible = "syscon";
reg = <0x65024000 0x100>;
@@ -204,7 +282,7 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <23961600>;
+ clocks = <&osc>;
status = "disabled";
};
--
1.9.1
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[PATCH v2 0/3] ARM: dts: add support for NS, NSP, and NS2 clocks
Changes in v2: Rebased off of outstanding NSP DT patches and tweaked the entry names per Ray Jui This patch series adds device tree support for the Broadcom Northstar, Northstar Plus, and Northstar 2 clocks. Last sent as an RFC (see https://lkml.org/lkml/2015/10/13/882) due to the inability to merge because of the driver dependencies. Those necessary driver changes were merged into 4.4. All comments have been addressed and it is ready to be pulled in. Jon Mason (3): ARM: dts: enable clock support for BCM5301X ARM: dts: enable clock support for Broadcom NSP ARM64: dts: enable clock support for Broadcom NS2 arch/arm/boot/dts/bcm-nsp.dtsi| 77 - arch/arm/boot/dts/bcm5301x.dtsi | 92 +++ arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 +- 3 files changed, 214 insertions(+), 35 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] ARM: dts: enable clock support for Broadcom NSP
On Wed, Nov 18, 2015 at 03:57:36PM -0800, Ray Jui wrote:
> Would this patch merge properly with the other NSP DT clean up patch
> + I2C DT patch that you worked out internally but have not sent out?
>
> I thought it's going to make the maintainers' life easier if you can
> group DT changes per platform and send them out in the same series.
>
> I also have some inline comments below.
>
> On 11/18/2015 3:13 PM, Jon Mason wrote:
> >Replace current device tree dummy clocks with real clock support for
> >Broadcom Northstar Plus SoC
> >
> >Signed-off-by: Jon Mason
> >---
> > arch/arm/boot/dts/bcm-nsp.dtsi | 99
> > --
> > 1 file changed, 75 insertions(+), 24 deletions(-)
> >
> >diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> >index 4bcdd28..f85a4f1 100644
> >--- a/arch/arm/boot/dts/bcm-nsp.dtsi
> >+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> >@@ -32,6 +32,7 @@
> >
> > #include
> > #include
> >+#include
> >
> > #include "skeleton.dtsi"
> >
> >@@ -42,7 +43,7 @@
> >
> > mpcore {
> > compatible = "simple-bus";
> >-ranges = <0x 0x1902 0x3000>;
> >+ranges = <0x 0x1900 0x00023000>;
>
> Why does this have anything to do with clocks? Shouldn't it be a
> separate patch?
No, this is correct (though the patch is a little odd to look at).
The a9pll starts at 0x1900 instead of 0x1902. So, everything
needs to be adjusted.
>
> > #address-cells = <1>;
> > #size-cells = <1>;
> >
> >@@ -58,32 +59,23 @@
> > };
> > };
> >
> >-L2: l2-cache {
> >-compatible = "arm,pl310-cache";
> >-reg = <0x2000 0x1000>;
> >-cache-unified;
> >-cache-level = <2>;
> >-};
> >-
> >-gic: interrupt-controller@19021000 {
> >-compatible = "arm,cortex-a9-gic";
> >-#interrupt-cells = <3>;
> >-#address-cells = <0>;
> >-interrupt-controller;
> >-reg = <0x1000 0x1000>,
> >- <0x0100 0x100>;
> >+a9pll: arm_clk@1900 {
> >+#clock-cells = <0>;
> >+compatible = "brcm,nsp-armpll";
> >+clocks = <&osc>;
> >+reg = <0x0 0x1000>;
> > };
> >
> > timer@19020200 {
> > compatible = "arm,cortex-a9-global-timer";
> >-reg = <0x0200 0x100>;
> >+reg = <0x20200 0x100>;
> > interrupts = ;
> > clocks = <&periph_clk>;
> > };
> >
> > twd-timer@19020600 {
> > compatible = "arm,cortex-a9-twd-timer";
> >-reg = <0x0600 0x20>;
> >+reg = <0x20600 0x20>;
> > interrupts = > IRQ_TYPE_LEVEL_HIGH)>;
> > clocks = <&periph_clk>;
> >@@ -91,11 +83,27 @@
> >
> > twd-watchdog@19020620 {
> > compatible = "arm,cortex-a9-twd-wdt";
> >-reg = <0x0620 0x20>;
> >+reg = <0x20620 0x20>;
> > interrupts = > IRQ_TYPE_LEVEL_HIGH)>;
> > clocks = <&periph_clk>;
> > };
> >+
> >+gic: interrupt-controller@19021000 {
> >+compatible = "arm,cortex-a9-gic";
> >+#interrupt-cells = <3>;
> >+#address-cells = <0>;
> >+interrupt-controller;
> >+reg = <0x21000 0x1000>,
> >+ <0x20100 0x100>;
> >+};
> >+
> >+L2: l2-cache {
> >+compatible = "arm,pl310-cache";
> >+reg = <0x22000 0x1000>;
> >+cache-unified;
> >+
[PATCH 1/3] ARM: dts: enable clock support for BCM5301X
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar SoCs.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm5301x.dtsi | 92 +++--
1 file changed, 71 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 6f50f67..65a1309 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -8,6 +8,7 @@
* Licensed under the GNU/GPL. See COPYING for details.
*/
+#include
#include
#include
#include
@@ -27,7 +28,7 @@
compatible = "ns16550";
reg = <0x0300 0x100>;
interrupts = ;
- clock-frequency = <1>;
+ clocks = <&iprocslow>;
status = "disabled";
};
@@ -35,48 +36,55 @@
compatible = "ns16550";
reg = <0x0400 0x100>;
interrupts = ;
- clock-frequency = <1>;
+ clocks = <&iprocslow>;
status = "disabled";
};
};
mpcore {
compatible = "simple-bus";
- ranges = <0x 0x1902 0x3000>;
+ ranges = <0x 0x1900 0x00023000>;
#address-cells = <1>;
#size-cells = <1>;
- scu@ {
+ a9pll: arm_clk@0 {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x0 0x1000>;
+ };
+
+ scu@2 {
compatible = "arm,cortex-a9-scu";
- reg = <0x 0x100>;
+ reg = <0x2 0x100>;
};
- timer@0200 {
+ timer@20200 {
compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
+ reg = <0x20200 0x100>;
interrupts = ;
- clocks = <&clk_periph>;
+ clocks = <&periph_clk>;
};
- local-timer@0600 {
+ local-timer@20600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x0600 0x100>;
+ reg = <0x20600 0x100>;
interrupts = ;
- clocks = <&clk_periph>;
+ clocks = <&periph_clk>;
};
- gic: interrupt-controller@1000 {
+ gic: interrupt-controller@21000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
};
- L2: cache-controller@2000 {
+ L2: cache-controller@22000 {
compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
+ reg = <0x22000 0x1000>;
cache-unified;
arm,shared-override;
prefetch-data = <1>;
@@ -94,14 +102,37 @@
clocks {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ ranges;
- /* As long as we do not have a real clock driver us this
-* fixed clock */
- clk_periph: periph {
+ osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock
[PATCH 2/3] ARM: dts: enable clock support for Broadcom NSP
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar Plus SoC
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 99 --
1 file changed, 75 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 4bcdd28..f85a4f1 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -32,6 +32,7 @@
#include
#include
+#include
#include "skeleton.dtsi"
@@ -42,7 +43,7 @@
mpcore {
compatible = "simple-bus";
- ranges = <0x 0x1902 0x3000>;
+ ranges = <0x 0x1900 0x00023000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -58,32 +59,23 @@
};
};
- L2: l2-cache {
- compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
- cache-unified;
- cache-level = <2>;
- };
-
- gic: interrupt-controller@19021000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ a9pll: arm_clk@1900 {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x0 0x1000>;
};
timer@19020200 {
compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
+ reg = <0x20200 0x100>;
interrupts = ;
clocks = <&periph_clk>;
};
twd-timer@19020600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x0600 0x20>;
+ reg = <0x20600 0x20>;
interrupts = ;
clocks = <&periph_clk>;
@@ -91,11 +83,27 @@
twd-watchdog@19020620 {
compatible = "arm,cortex-a9-twd-wdt";
- reg = <0x0620 0x20>;
+ reg = <0x20620 0x20>;
interrupts = ;
clocks = <&periph_clk>;
};
+
+ gic: interrupt-controller@19021000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
+ };
+
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0x22000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
};
clocks {
@@ -103,10 +111,34 @@
#size-cells = <1>;
ranges;
- periph_clk: periph_clk {
+ osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ periph_clk: periph_clk {
#clock-cells = <0>;
- clock-frequency = <5>;
+ compatible = "fixed-factor-clock";
+ clocks = <&a9pll>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
};
@@ -1
[PATCH 0/3] ARM: dts: add support for NS, NSP, and NS2 clocks
This patch series adds device tree support for the Broadcom Northstar, Northstar Plus, and Northstar 2 clocks. Last sent as an RFC (see https://lkml.org/lkml/2015/10/13/882) due to the inability to merge because of the driver dependencies. Those necessary driver changes were merged into 4.4. All comments have been addressed and it is ready to be pulled in. Jon Mason (3): ARM: dts: enable clock support for BCM5301X ARM: dts: enable clock support for Broadcom NSP ARM64: dts: enable clock support for Broadcom NS2 arch/arm/boot/dts/bcm-nsp.dtsi| 99 ++- arch/arm/boot/dts/bcm5301x.dtsi | 92 arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 +++- 3 files changed, 225 insertions(+), 46 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] ARM64: dts: enable clock support for Broadcom NS2
Add device tree entries for clock support for Broadcom Northstar 2 SoC
Signed-off-by: Jon Mason
---
arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 ++-
1 file changed, 79 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 9610822..a510d3a 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -31,6 +31,7 @@
*/
#include
+#include
/memreserve/ 0x84b0 0x0008;
@@ -109,6 +110,33 @@
<&A57_3>;
};
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -156,6 +184,56 @@
mmu-masters;
};
+ lcpll_ddr: lcpll_ddr@6501d058 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ddr";
+ reg = <0x6501d058 0x20>,
+ <0x6501c020 0x4>,
+ <0x6501d04c 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ddr", "pcie_sata_usb",
+"ddr", "ddr_ch2_unused",
+"ddr_ch3_unused", "ddr_ch4_unused",
+"ddr_ch5_unused";
+ };
+
+ lcpll_ports: lcpll_ports@6501d078 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ports";
+ reg = <0x6501d078 0x20>,
+ <0x6501c020 0x4>,
+ <0x6501d054 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ports", "wan", "rgmii",
+"ports_ch2_unused",
+"ports_ch3_unused",
+"ports_ch4_unused",
+"ports_ch5_unused";
+ };
+
+ genpll_scr: genpll_scr@6501d098 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-scr";
+ reg = <0x6501d098 0x32>,
+ <0x6501c020 0x4>,
+ <0x6501d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_scr", "scr", "fs",
+"audio_ref", "scr_ch3_unused",
+"scr_ch4_unused", "scr_ch5_unused";
+ };
+
+ genpll_sw: genpll_sw@6501d0c4 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-sw";
+ reg = <0x6501d0c4 0x32>,
+ <0x6501c020 0x4>,
+ <0x6501d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_sw", "rpe", "250", "nic",
+"chimp", "port", "sdio";
+ };
+
crmu: crmu@65024000 {
compatible = "syscon";
reg = <0x65024000 0x100>;
@@ -204,7 +282,7 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <23961600>;
+ clocks = <&osc>;
status = "disabled";
};
--
1.9.1
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[PATCH 1/2] ARM: dts: NSP: Device Tree clean-ups
Minor changes to the Broadcom Northstar Plus device tree to make it more
organized and clean. Firstly, move the GIC and L2 cache entries to be
sequential with respect to the memory addresses. Secondly, modify the
address portion of the entry names to reflect the difference from the
range modification.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 50 +-
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 4bcdd28..7335a74 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -58,30 +58,14 @@
};
};
- L2: l2-cache {
- compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
- cache-unified;
- cache-level = <2>;
- };
-
- gic: interrupt-controller@19021000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
- };
-
- timer@19020200 {
+ timer@0200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x0200 0x100>;
interrupts = ;
clocks = <&periph_clk>;
};
- twd-timer@19020600 {
+ twd-timer@0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x0600 0x20>;
interrupts = ;
};
- twd-watchdog@19020620 {
+ twd-watchdog@0620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0x0620 0x20>;
interrupts = ;
clocks = <&periph_clk>;
};
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x0100 0x100>;
+ };
+
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0x2000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
};
clocks {
@@ -116,7 +116,7 @@
#address-cells = <1>;
#size-cells = <1>;
- uart0: serial@18000300 {
+ uart0: serial@0300 {
compatible = "ns16550a";
reg = <0x0300 0x100>;
interrupts = ;
@@ -124,7 +124,7 @@
status = "disabled";
};
- uart1: serial@18000400 {
+ uart1: serial@0400 {
compatible = "ns16550a";
reg = <0x0400 0x100>;
interrupts = ;
@@ -132,7 +132,7 @@
status = "disabled";
};
- pcie0: pcie@18012000 {
+ pcie0: pcie@12000 {
compatible = "brcm,iproc-pcie";
reg = <0x12000 0x1000>;
@@ -156,7 +156,7 @@
status = "disabled";
};
- pcie1: pcie@18013000 {
+ pcie1: pcie@13000 {
compatible = "brcm,iproc-pcie";
reg = <0x13000 0x1000>;
@@ -180,7 +180,7 @@
status = "disabled";
};
- pcie2: pcie@18014000 {
+ pcie2: pcie@14000 {
compatible = "brcm,iproc-pcie";
reg = <0x14000 0x1000>;
@@ -204,7 +204,7 @@
status = "disabled";
};
- nand: nand@18026000 {
+ nand: nand@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x026000 0x600>,
<0x11b408 0x600>,
--
1.9.1
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[PATCH 2/2] ARM: dts: NSP: Add I2C support to the DT
Add I2C support to the Broadcom Northstar Plus Device Tree. Since no
driver changes are needed to enable this hardware, only the device tree
changes are required to make this functional.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 7335a74..b74438c 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -217,5 +217,14 @@
brcm,nand-has-wp;
};
+
+ i2c0: i2c@38000 {
+ compatible = "brcm,iproc-i2c";
+ reg = <0x38000 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+ clock-frequency = <10>;
+ };
};
};
--
1.9.1
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[PATCH 0/2] ARM: dts: NSP: clean-ups and I2C support
Minor changes to the Broadcom Northstar Plus device tree to make it more organized and clean, and adding I2C support (device tree only change needed for support). Jon Mason (2): ARM: dts: NSP: Device Tree clean-ups ARM: dts: NSP: Add I2C support to the DT arch/arm/boot/dts/bcm-nsp.dtsi | 59 -- 1 file changed, 34 insertions(+), 25 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Conditionals in dtsi files
Hello,
I'm wondering how much C preprocessor syntax one can use in DT files.
Suppose I have 2 board DTS (both including common.dtsi)
board_A.dts (1-core), board_B.dts (2-core)
Can I have in common.dtsi something along these lines:
cpus {
enable-method = "foo,bar";
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
};
#if CORE_COUNT > 1
cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
};
#endif
};
board_A.dts would have
#define CORE_COUNT 1
#include "common.dtsi"
board_B.dts would have
#define CORE_COUNT 2
#include "common.dtsi"
Regards.
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Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708
On Sat, Nov 07, 2015 at 12:41:21AM +0100, Hauke Mehrtens wrote: > On 11/07/2015 12:27 AM, Hauke Mehrtens wrote: > > On 11/06/2015 11:54 PM, Jon Mason wrote: > >> On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote: > >>> On 11/06/2015 10:11 PM, Kapil Hali wrote: > >>>> From: Jon Mason > >>>> > >>>> Add SMP support for Broadcom's 4708 SoCs. > >>>> > >>>> Signed-off-by: Jon Mason > >>>> Acked-by: Hauke Mehrtens > >>>> Tested-by: Hauke Mehrtens > >>>> Signed-off-by: Kapil Hali > >>> > >>> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked. > >>> > >>>> --- > >>>> arch/arm/boot/dts/bcm4708.dtsi | 2 ++ > >>>> arch/arm/mach-bcm/Kconfig | 1 + > >>>> arch/arm/mach-bcm/Makefile | 3 +++ > >>>> 3 files changed, 6 insertions(+) > >>>> > >>> > >>> ... > >>> > >>>> --- a/arch/arm/mach-bcm/Kconfig > >>>> +++ b/arch/arm/mach-bcm/Kconfig > >>>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP > >>>> config ARCH_BCM_5301X > >>>> bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7 > >>>> select ARCH_BCM_IPROC > >>> > >>> You activated ARM_ERRATA_764369 for NSP is this not needed for NS? > >> > >> I'm not certain the CPU version, and without that it is difficult to > >> know what errata's are present in the underlying hardware. My guess > >> is that all present in NSP are present in NS (for UP and SMP). This > >> would put it as: > >> select ARM_ERRATA_754322 > >> select ARM_ERRATA_775420 > >> select ARM_ERRATA_764369 if SMP > >> > >> Would you like me to have them added? > >> > > > > I will send a separate patch adding all the workarounds for erratas in > > the CPU core and the cache controller. > > > > Hauke > > > > > Hi, > > BCM4708 uses a Cortex-A9 rev r3p0 and a L2C-310 rev r3p2. For this CPU > and cache controller the same workaround are needed as for NSP, if you > will resend this patch, please add all of them. Agreed. Kapil or I will mod the patch. Thanks, Jon > > Hauke -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708
On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote: > On 11/06/2015 10:11 PM, Kapil Hali wrote: > > From: Jon Mason > > > > Add SMP support for Broadcom's 4708 SoCs. > > > > Signed-off-by: Jon Mason > > Acked-by: Hauke Mehrtens > > Tested-by: Hauke Mehrtens > > Signed-off-by: Kapil Hali > > I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked. > > > --- > > arch/arm/boot/dts/bcm4708.dtsi | 2 ++ > > arch/arm/mach-bcm/Kconfig | 1 + > > arch/arm/mach-bcm/Makefile | 3 +++ > > 3 files changed, 6 insertions(+) > > > > ... > > > --- a/arch/arm/mach-bcm/Kconfig > > +++ b/arch/arm/mach-bcm/Kconfig > > @@ -54,6 +54,7 @@ config ARCH_BCM_NSP > > config ARCH_BCM_5301X > > bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7 > > select ARCH_BCM_IPROC > > You activated ARM_ERRATA_764369 for NSP is this not needed for NS? I'm not certain the CPU version, and without that it is difficult to know what errata's are present in the underlying hardware. My guess is that all present in NSP are present in NS (for UP and SMP). This would put it as: select ARM_ERRATA_754322 select ARM_ERRATA_775420 select ARM_ERRATA_764369 if SMP Would you like me to have them added? Thanks, Jon > > > > + select HAVE_SMP > > help > > Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores. > > > > ... -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RESEND 3/3] ARM: dts: NSP: Add TWD Support to DT
Add support for the ARM TWD Timer and Watchdog to the Northstar Plus
device tree.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 62bc86f..4bcdd28 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -80,6 +80,22 @@
interrupts = ;
clocks = <&periph_clk>;
};
+
+ twd-timer@19020600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x0600 0x20>;
+ interrupts = ;
+ clocks = <&periph_clk>;
+ };
+
+ twd-watchdog@19020620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0x0620 0x20>;
+ interrupts = ;
+ clocks = <&periph_clk>;
+ };
};
clocks {
--
1.9.1
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[PATCH RESEND 1/3] ARM: dts: NSP: Add PCI support
Add PCI support to the Northstar Plus SoC. This uses the existing
pcie-iproc driver. So, all that is needed is device tree entries in the
DTS.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 74 +++-
arch/arm/boot/dts/bcm958625k.dts | 12 +++
2 files changed, 85 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..85fb1c8 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -96,7 +96,7 @@
axi {
compatible = "simple-bus";
- ranges = <0x 0x1800 0x1000>;
+ ranges = <0x 0x1800 0x00015000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -115,5 +115,77 @@
clock-frequency = <62499840>;
status = "disabled";
};
+
+ pcie0: pcie@18012000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x12000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 131
IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <0>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+
+ /* Note: The HW does not support I/O resources. So,
+* only the memory resource range is being specified.
+*/
+ ranges = <0x8200 0 0x0800 0x0800 0
0x800>;
+
+ status = "disabled";
+ };
+
+ pcie1: pcie@18013000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x13000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 137
IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <1>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+
+ /* Note: The HW does not support I/O resources. So,
+* only the memory resource range is being specified.
+*/
+ ranges = <0x8200 0 0x4000 0x4000 0
0x800>;
+
+ status = "disabled";
+ };
+
+ pcie2: pcie@18014000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x14000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 143
IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+
+ /* Note: The HW does not support I/O resources. So,
+* only the memory resource range is being specified.
+*/
+ ranges = <0x8200 0 0x4800 0x4800 0
0x800>;
+
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 16303db..4859268 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -55,3 +55,15 @@
&uart1 {
status = "okay";
};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
--
1.9.1
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[PATCH RESEND 2/3] ARM: dts: NSP: Add NAND Support to DT
Add NAND support to the device tree for the Broadcom Northstar Plus SoC.
Since no driver changes are needed to enable this hardware, only the
device tree changes are required to make this functional.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 16 +++-
arch/arm/boot/dts/bcm958625k.dts | 38 ++
2 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 85fb1c8..62bc86f 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -96,7 +96,7 @@
axi {
compatible = "simple-bus";
- ranges = <0x 0x1800 0x00015000>;
+ ranges = <0x 0x1800 0x0011ba08>;
#address-cells = <1>;
#size-cells = <1>;
@@ -187,5 +187,19 @@
status = "disabled";
};
+
+ nand: nand@18026000 {
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
+ reg = <0x026000 0x600>,
+ <0x11b408 0x600>,
+ <0x026f00 0x20>;
+ reg-names = "nand", "iproc-idm", "iproc-ext";
+ interrupts = ;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcm,nand-has-wp;
+ };
};
};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 4859268..b966955 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -67,3 +67,41 @@
&pcie2 {
status = "okay";
};
+
+&nand {
+ nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+
+ partition@0 {
+ label = "nboot";
+ reg = <0x 0x0020>;
+ read-only;
+ };
+ partition@1 {
+ label = "nenv";
+ reg = <0x0020 0x0040>;
+ };
+ partition@2 {
+ label = "nsystem";
+ reg = <0x0060 0x00a0>;
+ };
+ partition@3 {
+ label = "nrootfs";
+ reg = <0x0100 0x0300>;
+ };
+ partition@4 {
+ label = "ncustfs";
+ reg = <0x0400 0x3c00>;
+ };
+ };
+};
--
1.9.1
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[PATCH RESEND 0/3] ARM: dts: NSP: Add PCI, NAND, and TWD Support to DT
Resending due to lack of any response to the original series Add PCI, NAND, and TWD Support to the Broadcom Northstar Plus SoC device tree file. Since no driver changes are needed to enable these pieces of hardware, only the device tree changes are required to make them functional. Jon Mason (3): ARM: dts: NSP: Add PCI support ARM: dts: NSP: Add NAND Support to DT ARM: dts: NSP: Add TWD Support to DT arch/arm/boot/dts/bcm-nsp.dtsi | 104 ++- arch/arm/boot/dts/bcm958625k.dts | 50 +++ 2 files changed, 153 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RESEND v4 2/2] ARM: dts: bcm5301x: Add BCM SVK DT files
Add device tree files for Broadcom Northstar based SVKs. Since the
bcm5301x.dtsi already exists, all that is necessary is the dts files to
enable the UARTs. With these files, the SVKs are able to boot to shell.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/Makefile | 5 +++-
arch/arm/boot/dts/bcm94708.dts | 56 +++
arch/arm/boot/dts/bcm94709.dts | 56 +++
arch/arm/boot/dts/bcm953012k.dts | 63
4 files changed, 179 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/bcm94708.dts
create mode 100644 arch/arm/boot/dts/bcm94709.dts
create mode 100644 arch/arm/boot/dts/bcm953012k.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 233159d..96a1b58 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -72,7 +72,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm47081-buffalo-wzr-900dhp.dtb \
bcm4709-asus-rt-ac87u.dtb \
bcm4709-buffalo-wxr-1900dhp.dtb \
- bcm4709-netgear-r8000.dtb
+ bcm4709-netgear-r8000.dtb \
+ bcm94708.dtb \
+ bcm94709.dtb \
+ bcm953012k.dtb
dtb-$(CONFIG_ARCH_BCM_63XX) += \
bcm963138dvt.dtb
dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts
new file mode 100644
index 000..251a486
--- /dev/null
+++ b/arch/arm/boot/dts/bcm94708.dts
@@ -0,0 +1,56 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ ** Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ ** Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ ** Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+
+/ {
+ model = "NorthStar SVK (BCM94708)";
+ compatible = "brcm,bcm94708", "brcm,bcm4708";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x 0x0800>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/bcm94709.dts
new file mode 100644
index 000..b16cac9
--- /dev/null
+++ b/arch/arm/boot/dts/bcm94709.dts
@@ -0,0 +1,56 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ ** Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ ** Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ ** Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
[PATCH RESEND v4 0/2] ARM: dts: bcm5301x: Add SVK DT files and docs
Resending due to lack of any response to the original v4 series Changes in v4: * Changed bootargs to stdout-path, per Sudeep Holla Changes in v3: * Updated the DT documentation compat strings * Modified the include files and compat strings for the SVK DT files, per Hauke Mehrtens Changes in v2: * Reorder the patches to add the DT binding documentation prior to the new DT files * Removed the DT documentation compat strings to only the SoCs, not the individual boards * Fixed the compat strings in the individual device tree files * Added the memory node and removed the "mem=" from the bootargs Add device tree files and update the documentation for Broadcom Northstar based SVKs. Since the bcm5301x.dtsi already exists, all that is necessary is the dts files to enable the UARTs. With these files, the SVKs are able to boot to shell Jon Mason (2): dt-bindings: Add new SoCs to bcm4708 DT bindings ARM: dts: bcm5301x: Add BCM SVK DT files .../devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++ arch/arm/boot/dts/Makefile | 5 +- arch/arm/boot/dts/bcm94708.dts | 56 +++ arch/arm/boot/dts/bcm94709.dts | 56 +++ arch/arm/boot/dts/bcm953012k.dts | 63 ++ 5 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/bcm94708.dts create mode 100644 arch/arm/boot/dts/bcm94709.dts create mode 100644 arch/arm/boot/dts/bcm953012k.dts -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH RESEND v4 1/2] dt-bindings: Add new SoCs to bcm4708 DT bindings
Add the 4708, 4709, and 53012 SoCs to the the documentation for the Broadcom Northstar device tree bindings. Signed-off-by: Jon Mason Acked-by: Hauke Mehrtens Acked-by: Scott Branden Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt index 6b0f49f..8608a77 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt @@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following properties: Required root node property: +bcm4708 compatible = "brcm,bcm4708"; + +bcm4709 +compatible = "brcm,bcm4709"; + +bcm53012 +compatible = "brcm,bcm53012"; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] devicetree: add Sigma Designs vendor prefix
On 02/10/2015 19:21, Mans Rullgard wrote: > Add the "sigma" vendor prefix for Sigma Designs, Inc. > > Signed-off-by: Mans Rullgard > --- > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt > b/Documentation/devicetree/bindings/vendor-prefixes.txt > index 82d2ac9..ea77ee5 100644 > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt > @@ -192,6 +192,7 @@ schindler Schindler > seagate Seagate Technology PLC > semtech Semtech Corporation > sharpSharp Corporation > +sigmaSigma Designs, Inc. > sil Silicon Image > silabs Silicon Laboratories > siliconmitus Silicon Mitus, Inc. Hello, How can I determine whether this patch has been applied? (I examined a few branches in Rob's tree.) Regards. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
On Wed, Oct 21, 2015 at 05:22:47PM -0700, Stephen Boyd wrote: > On 10/15, Scott Branden wrote: > > On 15-10-15 02:15 PM, Ray Jui wrote: > > >On 10/15/2015 2:10 PM, Jon Mason wrote: > > >>On Thu, Oct 15, 2015 at 02:04:09PM -0700, Scott Branden wrote: > > >>>On 15-10-15 01:55 PM, Ray Jui wrote: > > >>>>On 10/15/2015 1:40 PM, Scott Branden wrote: > > >>>> > > >>>>If using CONFIG_CLK_NS2, how is it going to be enabled/selected? > > >>> > > >>>Since CONFIG_ARCH_BCM_NS2 isn't "allowed" to be introduced we will > > >>>need to create and select a CONFIG_CLK_BCM_NS2 in the defconfig > > >>>instead. > > >> > > >>Is this better than the binary becoming slightly bigger? I thought > > >>the extra complexity was worse than having an unused chunk of clk code > > >>(and Kona is already doing the same thing above). I believe Ray was > > >>in agreement with me during the internal review of this code. > > >> > > >>Thanks, > > >>Jon > > >> > > > > > >Yes, I'm okay with leaving it as it is. I even prefer changing the > > >current Makefile to make all iProc based core clock drivers and SoC > > >specific clock tables under CONFIG_COMMON_CLK_IPROC, which is what some > > >of the other vendors do. > > > > > I'd leave it exactly as is then rather than pulling in more dead > > code when not needed. This ns2 clock code is very minor compared to > > other code bloat in the kernel and drivers. > > We should really make these visible options that can be selected > by anyone. Having selects in the ARCH config area is simple, but > also has some downsides: > > 1) select is a reverse dependency and is hard for people to > understand and can sometimes be a pain to track down > > 2) build coverage goes down because configs are hidden > > 3) we get code bloat like is being discussed here > > So I'd really like to see someone take a good look at this whole > Makefile situation that's going on and clean it up so that > they're user visible options and then throw the config options > into the defconfig. It isn't going to block this series, but it > would be nice to do at some later point. I'll do a pass at this today and send it out for review. Thanks, Jon > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 0/10] clk: iproc: add support for BCM NS, NSP, and NS2
On Wed, Oct 21, 2015 at 04:51:44PM -0700, Stephen Boyd wrote: > On 10/15, Jon Mason wrote: > > > > v3 - Added a patch to fix cygnus clk link failures, and added back the > > DT documentation patches that were removed from v2. > > > > v2 - Added a patch to change the Cygnus clk macros to uppercase, > > removed the device tree changes from the series (will send out those as > > an RFC), and other minor changes that Stephen Boyd requested. > > > > This patch series adds support for the Broadcom Northstar, Northstar > > Plus, and Northstar 2 clocks. Some slight modifications were necessary > > to clk-iproc-pll to get Northstar and Northstar Plus working, due to > > differences in register layout. This is the reason why the first patch > > is necessary. Some more modifications were necessary to clk-iproc-pll > > to get Northstar 2 working, due to differences in register layout (and > > resulting fallout in Cygnus and NSP). This is the reason why the sixth > > and seventh patches are necessary. The fifth patch is clean-up to > > prevent accidentally forgetting to adjust for the base write errata > > (which happened a few times, but was caught in internal review). > > > > Can you please use git cover-letter format where the diffstat for > the series is shown? Without that information here I started > applying patches until I realized this added dt-bindings headers, > thus probably needing some stable clk branch to pull into arm-soc. My apologies. I will do so in the future. Thanks, Jon > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] ARM: dts: NSP: Add PCI support
Add PCI support to the Northstar Plus SoC. This uses the existing
pcie-iproc driver. So, all that is needed is device tree entries in the
DTS.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 74 +++-
arch/arm/boot/dts/bcm958625k.dts | 12 +++
2 files changed, 85 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..85fb1c8 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -96,7 +96,7 @@
axi {
compatible = "simple-bus";
- ranges = <0x 0x1800 0x1000>;
+ ranges = <0x 0x1800 0x00015000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -115,5 +115,77 @@
clock-frequency = <62499840>;
status = "disabled";
};
+
+ pcie0: pcie@18012000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x12000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 131
IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <0>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+
+ /* Note: The HW does not support I/O resources. So,
+* only the memory resource range is being specified.
+*/
+ ranges = <0x8200 0 0x0800 0x0800 0
0x800>;
+
+ status = "disabled";
+ };
+
+ pcie1: pcie@18013000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x13000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 137
IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <1>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+
+ /* Note: The HW does not support I/O resources. So,
+* only the memory resource range is being specified.
+*/
+ ranges = <0x8200 0 0x4000 0x4000 0
0x800>;
+
+ status = "disabled";
+ };
+
+ pcie2: pcie@18014000 {
+ compatible = "brcm,iproc-pcie";
+ reg = <0x14000 0x1000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 143
IRQ_TYPE_NONE>;
+
+ linux,pci-domain = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+
+ /* Note: The HW does not support I/O resources. So,
+* only the memory resource range is being specified.
+*/
+ ranges = <0x8200 0 0x4800 0x4800 0
0x800>;
+
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 16303db..4859268 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -55,3 +55,15 @@
&uart1 {
status = "okay";
};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
--
1.9.1
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[PATCH 2/3] ARM: dts: NSP: Add NAND Support to DT
Add NAND support to the device tree for the Broadcom Northstar Plus SoC.
Since no driver changes are needed to enable this hardware, only the
device tree changes are required to make this functional.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 16 +++-
arch/arm/boot/dts/bcm958625k.dts | 38 ++
2 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 85fb1c8..62bc86f 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -96,7 +96,7 @@
axi {
compatible = "simple-bus";
- ranges = <0x 0x1800 0x00015000>;
+ ranges = <0x 0x1800 0x0011ba08>;
#address-cells = <1>;
#size-cells = <1>;
@@ -187,5 +187,19 @@
status = "disabled";
};
+
+ nand: nand@18026000 {
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
+ reg = <0x026000 0x600>,
+ <0x11b408 0x600>,
+ <0x026f00 0x20>;
+ reg-names = "nand", "iproc-idm", "iproc-ext";
+ interrupts = ;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcm,nand-has-wp;
+ };
};
};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 4859268..b966955 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -67,3 +67,41 @@
&pcie2 {
status = "okay";
};
+
+&nand {
+ nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+
+ partition@0 {
+ label = "nboot";
+ reg = <0x 0x0020>;
+ read-only;
+ };
+ partition@1 {
+ label = "nenv";
+ reg = <0x0020 0x0040>;
+ };
+ partition@2 {
+ label = "nsystem";
+ reg = <0x0060 0x00a0>;
+ };
+ partition@3 {
+ label = "nrootfs";
+ reg = <0x0100 0x0300>;
+ };
+ partition@4 {
+ label = "ncustfs";
+ reg = <0x0400 0x3c00>;
+ };
+ };
+};
--
1.9.1
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[PATCH 3/3] ARM: dts: NSP: Add TWD Support to DT
Add support for the ARM TWD Timer and Watchdog to the Northstar Plus
device tree.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 62bc86f..4bcdd28 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -80,6 +80,22 @@
interrupts = ;
clocks = <&periph_clk>;
};
+
+ twd-timer@19020600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x0600 0x20>;
+ interrupts = ;
+ clocks = <&periph_clk>;
+ };
+
+ twd-watchdog@19020620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0x0620 0x20>;
+ interrupts = ;
+ clocks = <&periph_clk>;
+ };
};
clocks {
--
1.9.1
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[PATCH 0/3] ARM: dts: NSP: Add PCI, NAND, and TWD Support to DT
Add PCI, NAND, and TWD Support to the Broadcom Northstar Plus SoC device tree file. Since no driver changes are needed to enable these pieces of hardware, only the device tree changes are required to make them functional. Jon Mason (3): ARM: dts: NSP: Add PCI support ARM: dts: NSP: Add NAND Support to DT ARM: dts: NSP: Add TWD Support to DT arch/arm/boot/dts/bcm-nsp.dtsi | 104 ++- arch/arm/boot/dts/bcm958625k.dts | 50 +++ 2 files changed, 153 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/2] dt-bindings: Add new SoCs to bcm4708 DT bindings
Add the 4708, 4709, and 53012 SoCs to the the documentation for the Broadcom Northstar device tree bindings. Signed-off-by: Jon Mason Acked-by: Hauke Mehrtens Acked-by: Scott Branden Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt index 6b0f49f..8608a77 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt @@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following properties: Required root node property: +bcm4708 compatible = "brcm,bcm4708"; + +bcm4709 +compatible = "brcm,bcm4709"; + +bcm53012 +compatible = "brcm,bcm53012"; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 2/2] ARM: dts: bcm5301x: Add BCM SVK DT files
Add device tree files for Broadcom Northstar based SVKs. Since the
bcm5301x.dtsi already exists, all that is necessary is the dts files to
enable the UARTs. With these files, the SVKs are able to boot to shell.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/Makefile | 5 +++-
arch/arm/boot/dts/bcm94708.dts | 56 +++
arch/arm/boot/dts/bcm94709.dts | 56 +++
arch/arm/boot/dts/bcm953012k.dts | 63
4 files changed, 179 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/bcm94708.dts
create mode 100644 arch/arm/boot/dts/bcm94709.dts
create mode 100644 arch/arm/boot/dts/bcm953012k.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 233159d..96a1b58 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -72,7 +72,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm47081-buffalo-wzr-900dhp.dtb \
bcm4709-asus-rt-ac87u.dtb \
bcm4709-buffalo-wxr-1900dhp.dtb \
- bcm4709-netgear-r8000.dtb
+ bcm4709-netgear-r8000.dtb \
+ bcm94708.dtb \
+ bcm94709.dtb \
+ bcm953012k.dtb
dtb-$(CONFIG_ARCH_BCM_63XX) += \
bcm963138dvt.dtb
dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts
new file mode 100644
index 000..251a486
--- /dev/null
+++ b/arch/arm/boot/dts/bcm94708.dts
@@ -0,0 +1,56 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ ** Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ ** Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ ** Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+
+/ {
+ model = "NorthStar SVK (BCM94708)";
+ compatible = "brcm,bcm94708", "brcm,bcm4708";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x 0x0800>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/bcm94709.dts
new file mode 100644
index 000..b16cac9
--- /dev/null
+++ b/arch/arm/boot/dts/bcm94709.dts
@@ -0,0 +1,56 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ ** Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ ** Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ ** Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
[PATCH v4 0/2] ARM: dts: bcm5301x: Add SVK DT files and docs
Changes in v4: * Changed bootargs to stdout-path, per Sudeep Holla Changes in v3: * Updated the DT documentation compat strings * Modified the include files and compat strings for the SVK DT files, per Hauke Mehrtens Changes in v2: * Reorder the patches to add the DT binding documentation prior to the new DT files * Removed the DT documentation compat strings to only the SoCs, not the individual boards * Fixed the compat strings in the individual device tree files * Added the memory node and removed the "mem=" from the bootargs Add device tree files and update the documentation for Broadcom Northstar based SVKs. Since the bcm5301x.dtsi already exists, all that is necessary is the dts files to enable the UARTs. With these files, the SVKs are able to boot to shell Jon Mason (2): dt-bindings: Add new SoCs to bcm4708 DT bindings ARM: dts: bcm5301x: Add BCM SVK DT files .../devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++ arch/arm/boot/dts/Makefile | 5 +- arch/arm/boot/dts/bcm94708.dts | 56 +++ arch/arm/boot/dts/bcm94709.dts | 56 +++ arch/arm/boot/dts/bcm953012k.dts | 63 ++ 5 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/bcm94708.dts create mode 100644 arch/arm/boot/dts/bcm94709.dts create mode 100644 arch/arm/boot/dts/bcm953012k.dts -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/2] dt-bindings: Add new SoCs to bcm4708 DT bindings
Add the 4708, 4709, and 53012 SoCs to the the documentation for the Broadcom Northstar device tree bindings. Signed-off-by: Jon Mason --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt index 6b0f49f..8608a77 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt @@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following properties: Required root node property: +bcm4708 compatible = "brcm,bcm4708"; + +bcm4709 +compatible = "brcm,bcm4709"; + +bcm53012 +compatible = "brcm,bcm53012"; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/2] ARM: dts: bcm5301x: Add BCM SVK DT files
Add device tree files for Broadcom Northstar based SVKs. Since the
bcm5301x.dtsi already exists, all that is necessary is the dts files to
enable the UARTs. With these files, the SVKs are able to boot to shell.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/Makefile | 5 +++-
arch/arm/boot/dts/bcm94708.dts | 56 +++
arch/arm/boot/dts/bcm94709.dts | 56 +++
arch/arm/boot/dts/bcm953012k.dts | 63
4 files changed, 179 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/bcm94708.dts
create mode 100644 arch/arm/boot/dts/bcm94709.dts
create mode 100644 arch/arm/boot/dts/bcm953012k.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 233159d..96a1b58 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -72,7 +72,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm47081-buffalo-wzr-900dhp.dtb \
bcm4709-asus-rt-ac87u.dtb \
bcm4709-buffalo-wxr-1900dhp.dtb \
- bcm4709-netgear-r8000.dtb
+ bcm4709-netgear-r8000.dtb \
+ bcm94708.dtb \
+ bcm94709.dtb \
+ bcm953012k.dtb
dtb-$(CONFIG_ARCH_BCM_63XX) += \
bcm963138dvt.dtb
dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts
new file mode 100644
index 000..49682d6
--- /dev/null
+++ b/arch/arm/boot/dts/bcm94708.dts
@@ -0,0 +1,56 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ ** Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ ** Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ ** Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+
+/ {
+ model = "NorthStar SVK (BCM94708)";
+ compatible = "brcm,bcm94708", "brcm,bcm4708";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ reg = <0x 0x0800>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/bcm94709.dts
new file mode 100644
index 000..4ab19c0
--- /dev/null
+++ b/arch/arm/boot/dts/bcm94709.dts
@@ -0,0 +1,56 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ ** Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ ** Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ ** Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
Re: [PATCH v2 2/2] ARM: dts: bcm5301x: Add BCM SVK DT files
On Thu, Oct 15, 2015 at 11:32:27PM +0200, Hauke Mehrtens wrote: > On 10/15/2015 11:25 PM, Jon Mason wrote: > > On Thu, Oct 15, 2015 at 10:55:16PM +0200, Hauke Mehrtens wrote: > >> On 10/15/2015 10:40 PM, Hauke Mehrtens wrote: > >>> On 10/15/2015 12:14 AM, Jon Mason wrote: > >>>> Add device tree files for Broadcom Northstar based SVKs. Since the > >>>> bcm5301x.dtsi already exists, all that is necessary is the dts files to > >>>> enable the UARTs (and specify the RAM size for the 4708/9). With these > >>>> files, the SVKs are able to boot to shell. > >> > >> One additional question. What flash are you using on these boards? For > >> some common NAND flash properties you only have to include > >> bcm5301x-nand-cs0-bch8.dtsi or do these boards use serial or parallel > >> flash? > > > > To be honest, I haven't gotten far enough to investigate that. I am > > assuming that it is "brcm,nand-iproc" like NSP (which is different > > than the file you reference). > > It uses brcm,nand-iproc, but this driver also needs some information > about the nand chip connected to that controller, most board vendors are > using NAND chips with the same settings and we put these settings to > bcm5301x-nand-cs0-bch8.dtsi. If it is alright with you, I'll investigate, add, and test this after these initial changes get it. Thanks, Jon > > Hauke > > > > > Thanks, > > Jon > > > >> > >> Hauke > >> > >>>> > >>>> Signed-off-by: Jon Mason > >>>> --- > >>>> arch/arm/boot/dts/Makefile | 5 +++- > >>>> arch/arm/boot/dts/bcm94708.dts | 56 > >>>> +++ > >>>> arch/arm/boot/dts/bcm94709.dts | 56 > >>>> +++ > >>>> arch/arm/boot/dts/bcm953012k.dts | 63 > >>>> > >>>> 4 files changed, 179 insertions(+), 1 deletion(-) > >>>> create mode 100644 arch/arm/boot/dts/bcm94708.dts > >>>> create mode 100644 arch/arm/boot/dts/bcm94709.dts > >>>> create mode 100644 arch/arm/boot/dts/bcm953012k.dts > >>>> > >>>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > >>>> index 233159d..96a1b58 100644 > >>>> --- a/arch/arm/boot/dts/Makefile > >>>> +++ b/arch/arm/boot/dts/Makefile > >>>> @@ -72,7 +72,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ > >>>> bcm47081-buffalo-wzr-900dhp.dtb \ > >>>> bcm4709-asus-rt-ac87u.dtb \ > >>>> bcm4709-buffalo-wxr-1900dhp.dtb \ > >>>> -bcm4709-netgear-r8000.dtb > >>>> +bcm4709-netgear-r8000.dtb \ > >>>> +bcm94708.dtb \ > >>>> +bcm94709.dtb \ > >>>> +bcm953012k.dtb > >>>> dtb-$(CONFIG_ARCH_BCM_63XX) += \ > >>>> bcm963138dvt.dtb > >>>> dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ > >>>> diff --git a/arch/arm/boot/dts/bcm94708.dts > >>>> b/arch/arm/boot/dts/bcm94708.dts > >>>> new file mode 100644 > >>>> index 000..f60bb1d > >>>> --- /dev/null > >>>> +++ b/arch/arm/boot/dts/bcm94708.dts > >>>> @@ -0,0 +1,56 @@ > >>>> +/* > >>>> + * BSD LICENSE > >>>> + * > >>>> + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. > >>>> + * > >>>> + * Redistribution and use in source and binary forms, with or without > >>>> + * modification, are permitted provided that the following conditions > >>>> + * are met: > >>>> + * > >>>> + ** Redistributions of source code must retain the above copyright > >>>> + * notice, this list of conditions and the following disclaimer. > >>>> + ** Redistributions in binary form must reproduce the above > >>>> copyright > >>>> + * notice, this list of conditions and the following disclaimer in > >>>> + * the documentation and/or other materials provided with the > >>>> + * distribution. > >>>> + ** Neither the name of Broadcom Corporation nor the names of its > >>>> + * contributors may be used to endorse or promote products derived > >>>> + * from t
Re: [PATCH v2 2/2] ARM: dts: bcm5301x: Add BCM SVK DT files
On Thu, Oct 15, 2015 at 10:40:47PM +0200, Hauke Mehrtens wrote:
> On 10/15/2015 12:14 AM, Jon Mason wrote:
> > Add device tree files for Broadcom Northstar based SVKs. Since the
> > bcm5301x.dtsi already exists, all that is necessary is the dts files to
> > enable the UARTs (and specify the RAM size for the 4708/9). With these
> > files, the SVKs are able to boot to shell.
> >
> > Signed-off-by: Jon Mason
> > ---
> > arch/arm/boot/dts/Makefile | 5 +++-
> > arch/arm/boot/dts/bcm94708.dts | 56 +++
> > arch/arm/boot/dts/bcm94709.dts | 56 +++
> > arch/arm/boot/dts/bcm953012k.dts | 63
> >
> > 4 files changed, 179 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/boot/dts/bcm94708.dts
> > create mode 100644 arch/arm/boot/dts/bcm94709.dts
> > create mode 100644 arch/arm/boot/dts/bcm953012k.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 233159d..96a1b58 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -72,7 +72,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
> > bcm47081-buffalo-wzr-900dhp.dtb \
> > bcm4709-asus-rt-ac87u.dtb \
> > bcm4709-buffalo-wxr-1900dhp.dtb \
> > - bcm4709-netgear-r8000.dtb
> > + bcm4709-netgear-r8000.dtb \
> > + bcm94708.dtb \
> > + bcm94709.dtb \
> > + bcm953012k.dtb
> > dtb-$(CONFIG_ARCH_BCM_63XX) += \
> > bcm963138dvt.dtb
> > dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
> > diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts
> > new file mode 100644
> > index 000..f60bb1d
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/bcm94708.dts
> > @@ -0,0 +1,56 @@
> > +/*
> > + * BSD LICENSE
> > + *
> > + * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
> > + *
> > + * Redistribution and use in source and binary forms, with or without
> > + * modification, are permitted provided that the following conditions
> > + * are met:
> > + *
> > + ** Redistributions of source code must retain the above copyright
> > + * notice, this list of conditions and the following disclaimer.
> > + ** Redistributions in binary form must reproduce the above copyright
> > + * notice, this list of conditions and the following disclaimer in
> > + * the documentation and/or other materials provided with the
> > + * distribution.
> > + ** Neither the name of Broadcom Corporation nor the names of its
> > + * contributors may be used to endorse or promote products derived
> > + * from this software without specific prior written permission.
> > + *
> > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> > + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> > + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> > + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> > + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> > + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> > + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> > + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> > + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "bcm5301x.dtsi"
>
> Please include bcm4708.dtsi instead here.
>
> > +
> > +/ {
> > + model = "NorthStar SVK (BCM94708)";
> > + compatible = "brcm,bcm94708", "brcm,bcm4708";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + bootargs = "console=ttyS0,115200";
> > + };
> > +
> > + memory {
> > + reg = <0x 0x0800>;
> > + };
> > +};
> > +
> > +&uart0 {
> > + status = "okay";
> > +};
> > diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/bcm94709.dts
> > new file mode 100644
> > index 000..88de313
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/bcm94709.dts
> > @@ -0,0 +1,56
Re: [PATCH v2 2/2] ARM: dts: bcm5301x: Add BCM SVK DT files
On Thu, Oct 15, 2015 at 10:55:16PM +0200, Hauke Mehrtens wrote:
> On 10/15/2015 10:40 PM, Hauke Mehrtens wrote:
> > On 10/15/2015 12:14 AM, Jon Mason wrote:
> >> Add device tree files for Broadcom Northstar based SVKs. Since the
> >> bcm5301x.dtsi already exists, all that is necessary is the dts files to
> >> enable the UARTs (and specify the RAM size for the 4708/9). With these
> >> files, the SVKs are able to boot to shell.
>
> One additional question. What flash are you using on these boards? For
> some common NAND flash properties you only have to include
> bcm5301x-nand-cs0-bch8.dtsi or do these boards use serial or parallel flash?
To be honest, I haven't gotten far enough to investigate that. I am
assuming that it is "brcm,nand-iproc" like NSP (which is different
than the file you reference).
Thanks,
Jon
>
> Hauke
>
> >>
> >> Signed-off-by: Jon Mason
> >> ---
> >> arch/arm/boot/dts/Makefile | 5 +++-
> >> arch/arm/boot/dts/bcm94708.dts | 56 +++
> >> arch/arm/boot/dts/bcm94709.dts | 56 +++
> >> arch/arm/boot/dts/bcm953012k.dts | 63
> >>
> >> 4 files changed, 179 insertions(+), 1 deletion(-)
> >> create mode 100644 arch/arm/boot/dts/bcm94708.dts
> >> create mode 100644 arch/arm/boot/dts/bcm94709.dts
> >> create mode 100644 arch/arm/boot/dts/bcm953012k.dts
> >>
> >> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> >> index 233159d..96a1b58 100644
> >> --- a/arch/arm/boot/dts/Makefile
> >> +++ b/arch/arm/boot/dts/Makefile
> >> @@ -72,7 +72,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
> >>bcm47081-buffalo-wzr-900dhp.dtb \
> >>bcm4709-asus-rt-ac87u.dtb \
> >>bcm4709-buffalo-wxr-1900dhp.dtb \
> >> - bcm4709-netgear-r8000.dtb
> >> + bcm4709-netgear-r8000.dtb \
> >> + bcm94708.dtb \
> >> + bcm94709.dtb \
> >> + bcm953012k.dtb
> >> dtb-$(CONFIG_ARCH_BCM_63XX) += \
> >>bcm963138dvt.dtb
> >> dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
> >> diff --git a/arch/arm/boot/dts/bcm94708.dts
> >> b/arch/arm/boot/dts/bcm94708.dts
> >> new file mode 100644
> >> index 000..f60bb1d
> >> --- /dev/null
> >> +++ b/arch/arm/boot/dts/bcm94708.dts
> >> @@ -0,0 +1,56 @@
> >> +/*
> >> + * BSD LICENSE
> >> + *
> >> + * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
> >> + *
> >> + * Redistribution and use in source and binary forms, with or without
> >> + * modification, are permitted provided that the following conditions
> >> + * are met:
> >> + *
> >> + ** Redistributions of source code must retain the above copyright
> >> + * notice, this list of conditions and the following disclaimer.
> >> + ** Redistributions in binary form must reproduce the above copyright
> >> + * notice, this list of conditions and the following disclaimer in
> >> + * the documentation and/or other materials provided with the
> >> + * distribution.
> >> + ** Neither the name of Broadcom Corporation nor the names of its
> >> + * contributors may be used to endorse or promote products derived
> >> + * from this software without specific prior written permission.
> >> + *
> >> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> >> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> >> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> >> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> >> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> >> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> >> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> >> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> >> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> >> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> >> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> >> + */
> >> +
> >> +/dts-v1/;
> >> +
> >> +#include "bcm5301x.dtsi"
> >
> > Please include bcm4708.dtsi instead here.
> >
> >> +
> >> +/ {
> &
Re: [PATCH 3/3] ARM: BCM: Add SMP support for Broadcom NSP
On Thu, Oct 15, 2015 at 11:12:09PM +0200, Hauke Mehrtens wrote:
> On 10/15/2015 06:10 PM, Kapil Hali wrote:
> >
> >
> > On 10/15/2015 3:56 AM, Hauke Mehrtens wrote:
> >> On 10/14/2015 07:47 PM, Kapil Hali wrote:
> >>> Add SMP support for Broadcom's Northstar Plus SoC,
> >>> cpu enable method and pen_release procedures. This
> >>> changes also consolidates iProc family's - BCM NSP
> >>> and BCM Kona, SMP handling in a common file.
> >>
> >> This will probably also work on normal Northstar CPUs without changes.
> >>
> > I think, it should work for most of the variants of Northstar family,
> > except for those which have a BOOTROM bug.
>
> Which SoC are affected by this BOOTROM bug?
53012 is the one I am seeing. Not seeing it on 4708 (and assuming it is
not present on 4709). Internally, we do the ugly bug workaround on
all Northstar SoCs. The workaround is not acceptable upstream, so I
am not pushing it. :)
Thanks,
Jon
>
> >>> Northstar Plus SoC is based on ARM Cortex-A9
> >>> revision r3p0 which requires configuration for ARM
> >>> Errata 764369 for SMP. This change adds the needed
> >>> configuration option.
> >>>
> >>> Signed-off-by: Kapil Hali
> >>> ---
> >>> arch/arm/mach-bcm/Kconfig | 2 +
> >>> arch/arm/mach-bcm/Makefile | 8 +-
> >>> arch/arm/mach-bcm/bcm_nsp.h | 19
> >>> arch/arm/mach-bcm/headsmp.S | 37
> >>> arch/arm/mach-bcm/{kona_smp.c => platsmp.c} | 142
> >>> ++--
> >>> 5 files changed, 197 insertions(+), 11 deletions(-)
> >>> create mode 100644 arch/arm/mach-bcm/bcm_nsp.h
> >>> create mode 100644 arch/arm/mach-bcm/headsmp.S
> >>> rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (63%)
> >>>
> >>> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> >>> index 1679fa4..2e9dbb5 100644
> >>> --- a/arch/arm/mach-bcm/Kconfig
> >>> +++ b/arch/arm/mach-bcm/Kconfig
> >>> @@ -40,6 +40,8 @@ config ARCH_BCM_NSP
> >>> select ARCH_BCM_IPROC
> >>> select ARM_ERRATA_754322
> >>> select ARM_ERRATA_775420
> >>> + select ARM_ERRATA_764369 if SMP
> >>> + select HAVE_SMP
> >>> help
> >>> Support for Broadcom Northstar Plus SoC.
> >>> Broadcom Northstar Plus family of SoCs are used for switching control
> >>> diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
> >>> index 892261f..36a4ca30 100644
> >>> --- a/arch/arm/mach-bcm/Makefile
> >>> +++ b/arch/arm/mach-bcm/Makefile
> >>> @@ -14,7 +14,11 @@
> >>> obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
> >>>
> >>> # Northstar Plus
> >>> -obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
> >>> +obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
> >>> +
> >>> +ifeq ($(CONFIG_ARCH_BCM_NSP),y)
> >>> +obj-$(CONFIG_SMP)+= headsmp.o platsmp.o
> >>> +endif
> >>>
> >>> # BCM281XX
> >>> obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
> >>> @@ -23,7 +27,7 @@ obj-$(CONFIG_ARCH_BCM_281XX)+= board_bcm281xx.o
> >>> obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
> >>>
> >>> # BCM281XX and BCM21664 SMP support
> >>> -obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
> >>> +obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
> >>>
> >>> # BCM281XX and BCM21664 L2 cache control
> >>> obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
> >>> diff --git a/arch/arm/mach-bcm/bcm_nsp.h b/arch/arm/mach-bcm/bcm_nsp.h
> >>> new file mode 100644
> >>> index 000..58e1e80
> >>> --- /dev/null
> >>> +++ b/arch/arm/mach-bcm/bcm_nsp.h
> >>> @@ -0,0 +1,19 @@
> >>> +/*
> >>> + * Copyright (C) 2015 Broadcom Corporation
> >>> + *
> >>> + * This program is free software; you can redistribute it and/or
> >>> + * modify it under the terms of the GNU General Public License as
> >>> + * published by the Free Software Foundation version 2.
> >>> + *
> >>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> >>> + * kind, whether express or implied; without even the implied warranty
> >>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >>> + * GNU General Public License for more details.
> >>> + */
> >>> +
> >>> +#ifndef __BCM_NSP_H
> >>> +#define __BCM_NSP_H
> >>> +
> >>> +extern void nsp_secondary_startup(void);
> >>> +
> >>> +#endif /* __BCM_NSP_H */
> >>> diff --git a/arch/arm/mach-bcm/headsmp.S b/arch/arm/mach-bcm/headsmp.S
> >>> new file mode 100644
> >>> index 000..0da13b2
> >>> --- /dev/null
> >>> +++ b/arch/arm/mach-bcm/headsmp.S
> >>> @@ -0,0 +1,37 @@
> >>> +/*
> >>> + * Copyright (C) 2015 Broadcom Corporation
> >>> + *
> >>> + * This program is free software; you can redistribute it and/or
> >>> + * modify it under the terms of the GNU General Public License as
> >>> + * published by the Free Software Foundation version 2.
> >>> + *
> >>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> >>> + * kind, whether express or implied; without even the implied warranty
> >>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Re: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
On Thu, Oct 15, 2015 at 02:04:09PM -0700, Scott Branden wrote: > Hi Ray, > > Comment at near end. > > On 15-10-15 01:55 PM, Ray Jui wrote: > > > > > >On 10/15/2015 1:40 PM, Scott Branden wrote: > >>We need some sort of kconfig option to differentiate NS2 clock driver > >>from being pulled in all the time. > >> > >>On 15-10-15 12:48 PM, Jon Mason wrote: > >>>The Broadcom Northstar 2 SoC is architected under the iProc > >>>architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, > >>>LCPLL DDR, LCPLL Ports, all derived from an onboard crystal. > >>> > >>>Signed-off-by: Jon Mason > >>>--- > >>> drivers/clk/Makefile| 2 +- > >>> drivers/clk/bcm/Makefile| 1 + > >>> drivers/clk/bcm/clk-ns2.c | 288 > >>> > >>> include/dt-bindings/clock/bcm-ns2.h | 72 + > >>> 4 files changed, 362 insertions(+), 1 deletion(-) > >>> create mode 100644 drivers/clk/bcm/clk-ns2.c > >>> create mode 100644 include/dt-bindings/clock/bcm-ns2.h > >>> > >>>diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > >>>index d08b3e5..6124bd3 100644 > >>>--- a/drivers/clk/Makefile > >>>+++ b/drivers/clk/Makefile > >>>@@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X)+= clk-wm831x.o > >>> obj-$(CONFIG_COMMON_CLK_XGENE)+= clk-xgene.o > >>> obj-$(CONFIG_COMMON_CLK_PWM)+= clk-pwm.o > >>> obj-$(CONFIG_COMMON_CLK_AT91)+= at91/ > >>>-obj-$(CONFIG_ARCH_BCM)+= bcm/ > >>>+obj-y+= bcm/ > >>> obj-$(CONFIG_ARCH_BERLIN)+= berlin/ > >>> obj-$(CONFIG_ARCH_HISI)+= hisilicon/ > >>> obj-$(CONFIG_ARCH_MXC)+= imx/ > >>>diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile > >>>index e258b28..2d1cbc5 100644 > >>>--- a/drivers/clk/bcm/Makefile > >>>+++ b/drivers/clk/bcm/Makefile > >>>@@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA)+= clk-kona-setup.o > >>> obj-$(CONFIG_CLK_BCM_KONA)+= clk-bcm281xx.o > >>> obj-$(CONFIG_CLK_BCM_KONA)+= clk-bcm21664.o > >>> obj-$(CONFIG_COMMON_CLK_IPROC)+= clk-iproc-armpll.o > >>>clk-iproc-pll.o clk-iproc-asiu.o > >>>+obj-$(CONFIG_COMMON_CLK_IPROC)+= clk-ns2.o > >> > >>NS2 code is dragged in for all IPROC SoCs. We need a config option for > >>NS2 (CONFIG_ARCH_BCM_NS2) to avoid this (if Arnd allows this for ARMv8 > >>processors... ?). > >> > >>You can see below ARMv7 processors don't have this problem. > >> > > > >The arm64 maintainers (Catalin, Mark, and etc.) stated they only want > >one ARCH options per chip family. > > > >>If not we need to add CONFIG_CLK_NS2. > > > >If using CONFIG_CLK_NS2, how is it going to be enabled/selected? > > Since CONFIG_ARCH_BCM_NS2 isn't "allowed" to be introduced we will > need to create and select a CONFIG_CLK_BCM_NS2 in the defconfig > instead. Is this better than the binary becoming slightly bigger? I thought the extra complexity was worse than having an unused chunk of clk code (and Kona is already doing the same thing above). I believe Ray was in agreement with me during the internal review of this code. Thanks, Jon > > > >Ray > > > > Regards, > Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 01/10] ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
On Thu, Oct 15, 2015 at 01:28:50PM -0700, Scott Branden wrote: > Jon, > > One question below for others to comment on. > > On 15-10-15 12:48 PM, Jon Mason wrote: > >From: Arnd Bergmann > > > >When CONFIG_CYGNUS is set but CONFIG_COMMON_CLK_IPROC is disabled, the > >following link failures are caused: > > > >drivers/built-in.o: In function `cygnus_armpll_init': > >:(.init.text+0x1d290): undefined reference to `iproc_armpll_setup' > >drivers/built-in.o: In function `cygnus_genpll_clk_init': > >:(.init.text+0x1d2c4): undefined reference to `iproc_pll_clk_setup' > >drivers/built-in.o: In function `cygnus_lcpll0_clk_init': > >:(.init.text+0x1d304): undefined reference to `iproc_pll_clk_setup' > >drivers/built-in.o: In function `cygnus_mipipll_clk_init': > >:(.init.text+0x1d344): undefined reference to `iproc_pll_clk_setup' > >drivers/built-in.o: In function `cygnus_asiu_init': > >:(.init.text+0x1d370): undefined reference to `iproc_asiu_setup' > > > >It is fixed it by always selecting COMMON_CLK_IPROC from > >ARCH_BCM_IPROC, and making COMMON_CLK_IPROC a silent option (thus > >preventing it from being erroneously disabled by a user). > > > >Signed-off-by: Arnd Bergmann > >Signed-off-by: Jon Mason > >--- > > arch/arm/mach-bcm/Kconfig | 2 +- > > drivers/clk/bcm/Kconfig | 4 +--- > > 2 files changed, 2 insertions(+), 4 deletions(-) > > > >diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig > >index 1319c3c..84bd265 100644 > >--- a/arch/arm/mach-bcm/Kconfig > >+++ b/arch/arm/mach-bcm/Kconfig > >@@ -14,7 +14,7 @@ config ARCH_BCM_IPROC > > select HAVE_ARM_SCU if SMP > > select HAVE_ARM_TWD if SMP > > select ARM_GLOBAL_TIMER > >- > >+select COMMON_CLK_IPROC > > select CLKSRC_MMIO > > select ARCH_REQUIRE_GPIOLIB > > select ARM_AMBA > >diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig > >index 88febf5..46ee475 100644 > >--- a/drivers/clk/bcm/Kconfig > >+++ b/drivers/clk/bcm/Kconfig > >@@ -9,10 +9,8 @@ config CLK_BCM_KONA > > in the BCM281xx and BCM21664 families. > > > > config COMMON_CLK_IPROC > >-bool "Broadcom iProc clock support" > >-depends on ARCH_BCM_IPROC > >+bool > > depends on COMMON_CLK > Should these depends on remain? I think COMMON_CLK_IPROC won't work > without them. The ones that were removed were not necessary (as ARCH_BCM_IPROC now selects it). I left the "depends on COMMON_CLK" in the off chance that the dependency chain gets broken some how (as ARCH_BCM_IPROC is not selecting COMMON_CLK directly, but it is being selected by ARCH_MULTIPLATFORM). Thanks, Jon > >-default ARCH_BCM_IPROC > > help > > Enable common clock framework support for Broadcom SoCs > > based on the iProc architecture > > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 04/10] clk: nsp: add clock support for Broadcom Northstar Plus SoC
On Thu, Oct 15, 2015 at 01:41:57PM -0700, Scott Branden wrote: > Jon, > > Review below. > > On 15-10-15 12:48 PM, Jon Mason wrote: > >The Broadcom Northstar Plus SoC is architected under the iProc > > Based on changes in Makefile below - should this be for Northstar > and Northstar Plus? Yes, that would be more accurate (or the 5301x/4708 verbage we are using now in Linux for that SoC family). If there is the need for another version of this patch, I'll fix it up. Thanks, Jon > > >architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all > >derived from an onboard crystal. > > > >Signed-off-by: Jon Mason > >--- > > drivers/clk/bcm/Makefile| 2 + > > drivers/clk/bcm/clk-nsp.c | 135 > > > > include/dt-bindings/clock/bcm-nsp.h | 51 ++ > > 3 files changed, 188 insertions(+) > > create mode 100644 drivers/clk/bcm/clk-nsp.c > > create mode 100644 include/dt-bindings/clock/bcm-nsp.h > > > >diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile > >index 8a7a477..e258b28 100644 > >--- a/drivers/clk/bcm/Makefile > >+++ b/drivers/clk/bcm/Makefile > >@@ -4,3 +4,5 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o > > obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o > > obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o > > clk-iproc-asiu.o > > obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o > >+obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o > >+obj-$(CONFIG_ARCH_BCM_5301X)+= clk-nsp.o > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 03/10] clk: iproc: Add PWRCTRL support
Some iProc SoC clocks use a different way to control clock power, via
the PWRDWN bit in the PLL control register. Since the PLL control
register is used to access the PWRDWN bit, there is no need for the
pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL,
has been added to identify this usage. We can use the AON interface to
write the values to enable/disable PWRDOWN.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/clk-iproc-pll.c | 55 -
drivers/clk/bcm/clk-iproc.h | 6 +
2 files changed, 44 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index 2dda4e8..e029ab3 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -148,14 +148,25 @@ static void __pll_disable(struct iproc_pll *pll)
writel(val, pll->asiu_base + ctrl->asiu.offset);
}
- /* latch input value so core power can be shut down */
- val = readl(pll->pwr_base + ctrl->aon.offset);
- val |= (1 << ctrl->aon.iso_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
-
- /* power down the core */
- val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
+ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
+ val = readl(pll->pll_base + ctrl->aon.offset);
+ val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
+ writel(val, pll->pll_base + ctrl->aon.offset);
+
+ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
+ readl(pll->pll_base + ctrl->aon.offset);
+ }
+
+ if (pll->pwr_base) {
+ /* latch input value so core power can be shut down */
+ val = readl(pll->pwr_base + ctrl->aon.offset);
+ val |= (1 << ctrl->aon.iso_shift);
+ writel(val, pll->pwr_base + ctrl->aon.offset);
+
+ /* power down the core */
+ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
+ writel(val, pll->pwr_base + ctrl->aon.offset);
+ }
}
static int __pll_enable(struct iproc_pll *pll)
@@ -163,11 +174,22 @@ static int __pll_enable(struct iproc_pll *pll)
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
u32 val;
- /* power up the PLL and make sure it's not latched */
- val = readl(pll->pwr_base + ctrl->aon.offset);
- val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
- val &= ~(1 << ctrl->aon.iso_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
+ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
+ val = readl(pll->pll_base + ctrl->aon.offset);
+ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
+ writel(val, pll->pll_base + ctrl->aon.offset);
+
+ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
+ readl(pll->pll_base + ctrl->aon.offset);
+ }
+
+ if (pll->pwr_base) {
+ /* power up the PLL and make sure it's not latched */
+ val = readl(pll->pwr_base + ctrl->aon.offset);
+ val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
+ val &= ~(1 << ctrl->aon.iso_shift);
+ writel(val, pll->pwr_base + ctrl->aon.offset);
+ }
/* certain PLLs also need to be ungated from the ASIU top level */
if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
@@ -610,9 +632,8 @@ void __init iproc_pll_clk_setup(struct device_node *node,
if (WARN_ON(!pll->pll_base))
goto err_pll_iomap;
+ /* Some SoCs do not require the pwr_base, thus failing is not fatal */
pll->pwr_base = of_iomap(node, 1);
- if (WARN_ON(!pll->pwr_base))
- goto err_pwr_iomap;
/* some PLLs require gating control at the top ASIU level */
if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) {
@@ -695,9 +716,9 @@ err_pll_register:
iounmap(pll->asiu_base);
err_asiu_iomap:
- iounmap(pll->pwr_base);
+ if (pll->pwr_base)
+ iounmap(pll->pwr_base);
-err_pwr_iomap:
iounmap(pll->pll_base);
err_pll_iomap:
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
index d834b7a..ff7bfad 100644
--- a/drivers/clk/bcm/clk-iproc.h
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -49,6 +49,12 @@
#define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
/*
+ * Some PLLs use a different way to control clock power, via the PWRDWN bit in
+ * the PLL control register
+ */
+#define IPROC_CLK_EMBED_PWRCTRL BIT(5)
+
+/*
* Parameters for VCO frequency configuration
*
* VCO frequency =
--
1.9.1
--
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[PATCH v3 04/10] clk: nsp: add clock support for Broadcom Northstar Plus SoC
The Broadcom Northstar Plus SoC is architected under the iProc
architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all
derived from an onboard crystal.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/Makefile| 2 +
drivers/clk/bcm/clk-nsp.c | 135
include/dt-bindings/clock/bcm-nsp.h | 51 ++
3 files changed, 188 insertions(+)
create mode 100644 drivers/clk/bcm/clk-nsp.c
create mode 100644 include/dt-bindings/clock/bcm-nsp.h
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 8a7a477..e258b28 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -4,3 +4,5 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o
clk-iproc-asiu.o
obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
+obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o
+obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
diff --git a/drivers/clk/bcm/clk-nsp.c b/drivers/clk/bcm/clk-nsp.c
new file mode 100644
index 000..bc8ebdcd
--- /dev/null
+++ b/drivers/clk/bcm/clk-nsp.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include "clk-iproc.h"
+
+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
+
+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
+ .pwr_shift = ps, .iso_shift = is }
+
+#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
+ .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
+ .ka_width = kaw }
+
+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
+ .hold_shift = hs, .bypass_shift = bs }
+
+static void __init nsp_armpll_init(struct device_node *node)
+{
+ iproc_armpll_setup(node);
+}
+CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
+
+static const struct iproc_pll_ctrl genpll = {
+ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
+ .aon = AON_VAL(0x0, 1, 12, 0),
+ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
+ .ndiv_int = REG_VAL(0x14, 20, 10),
+ .ndiv_frac = REG_VAL(0x14, 0, 20),
+ .pdiv = REG_VAL(0x18, 24, 3),
+ .status = REG_VAL(0x20, 12, 1),
+};
+
+static const struct iproc_clk_ctrl genpll_clk[] = {
+ [BCM_NSP_GENPLL_PHY_CLK] = {
+ .channel = BCM_NSP_GENPLL_PHY_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 12, 6, 18),
+ .mdiv = REG_VAL(0x18, 16, 8),
+ },
+ [BCM_NSP_GENPLL_ENET_SW_CLK] = {
+ .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 13, 7, 19),
+ .mdiv = REG_VAL(0x18, 8, 8),
+ },
+ [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = {
+ .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 14, 8, 20),
+ .mdiv = REG_VAL(0x18, 0, 8),
+ },
+ [BCM_NSP_GENPLL_IPROCFAST_CLK] = {
+ .channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 15, 9, 21),
+ .mdiv = REG_VAL(0x1c, 16, 8),
+ },
+ [BCM_NSP_GENPLL_SATA1_CLK] = {
+ .channel = BCM_NSP_GENPLL_SATA1_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 16, 10, 22),
+ .mdiv = REG_VAL(0x1c, 8, 8),
+ },
+ [BCM_NSP_GENPLL_SATA2_CLK] = {
+ .channel = BCM_NSP_GENPLL_SATA2_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 17, 11, 23),
+ .mdiv = REG_VAL(0x1c, 0, 8),
+ },
+};
+
+static void __init nsp_genpll_clk_init(struct device_node *node)
+{
+ iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
+ ARRAY_SIZE(genpll_clk));
+}
+CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);
+
+static const struct iproc_pll_ctrl lcpll0 = {
+ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
+ .aon = AON_VAL(0x0, 1, 24, 0),
+ .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4),
+ .ndiv_i
[PATCH v3 01/10] ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
From: Arnd Bergmann When CONFIG_CYGNUS is set but CONFIG_COMMON_CLK_IPROC is disabled, the following link failures are caused: drivers/built-in.o: In function `cygnus_armpll_init': :(.init.text+0x1d290): undefined reference to `iproc_armpll_setup' drivers/built-in.o: In function `cygnus_genpll_clk_init': :(.init.text+0x1d2c4): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_lcpll0_clk_init': :(.init.text+0x1d304): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_mipipll_clk_init': :(.init.text+0x1d344): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_asiu_init': :(.init.text+0x1d370): undefined reference to `iproc_asiu_setup' It is fixed it by always selecting COMMON_CLK_IPROC from ARCH_BCM_IPROC, and making COMMON_CLK_IPROC a silent option (thus preventing it from being erroneously disabled by a user). Signed-off-by: Arnd Bergmann Signed-off-by: Jon Mason --- arch/arm/mach-bcm/Kconfig | 2 +- drivers/clk/bcm/Kconfig | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 1319c3c..84bd265 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -14,7 +14,7 @@ config ARCH_BCM_IPROC select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ARM_GLOBAL_TIMER - + select COMMON_CLK_IPROC select CLKSRC_MMIO select ARCH_REQUIRE_GPIOLIB select ARM_AMBA diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig index 88febf5..46ee475 100644 --- a/drivers/clk/bcm/Kconfig +++ b/drivers/clk/bcm/Kconfig @@ -9,10 +9,8 @@ config CLK_BCM_KONA in the BCM281xx and BCM21664 families. config COMMON_CLK_IPROC - bool "Broadcom iProc clock support" - depends on ARCH_BCM_IPROC + bool depends on COMMON_CLK - default ARCH_BCM_IPROC help Enable common clock framework support for Broadcom SoCs based on the iProc architecture -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 05/10] clk: iproc: Add PLL base write function
All writes to the PLL base address must be flushed if the
IPROC_CLK_NEEDS_READ_BACK flag is set. If we add a function to make the
necessary write and reads, we can make sure that any future code which
makes PLL base writes will do the correct thing.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/clk-iproc-pll.c | 80 +
1 file changed, 33 insertions(+), 47 deletions(-)
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index e029ab3..74cdd66 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -137,6 +137,18 @@ static int pll_wait_for_lock(struct iproc_pll *pll)
return -EIO;
}
+static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base,
+ const u32 offset, u32 val)
+{
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+
+ writel(val, base + offset);
+
+ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK &&
+base == pll->pll_base))
+ val = readl(base + offset);
+}
+
static void __pll_disable(struct iproc_pll *pll)
{
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
@@ -145,27 +157,24 @@ static void __pll_disable(struct iproc_pll *pll)
if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
val = readl(pll->asiu_base + ctrl->asiu.offset);
val &= ~(1 << ctrl->asiu.en_shift);
- writel(val, pll->asiu_base + ctrl->asiu.offset);
+ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val);
}
if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
val = readl(pll->pll_base + ctrl->aon.offset);
val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- writel(val, pll->pll_base + ctrl->aon.offset);
-
- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
- readl(pll->pll_base + ctrl->aon.offset);
+ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val);
}
if (pll->pwr_base) {
/* latch input value so core power can be shut down */
val = readl(pll->pwr_base + ctrl->aon.offset);
val |= (1 << ctrl->aon.iso_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
+ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
/* power down the core */
val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
+ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
}
}
@@ -177,10 +186,7 @@ static int __pll_enable(struct iproc_pll *pll)
if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
val = readl(pll->pll_base + ctrl->aon.offset);
val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- writel(val, pll->pll_base + ctrl->aon.offset);
-
- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
- readl(pll->pll_base + ctrl->aon.offset);
+ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val);
}
if (pll->pwr_base) {
@@ -188,14 +194,14 @@ static int __pll_enable(struct iproc_pll *pll)
val = readl(pll->pwr_base + ctrl->aon.offset);
val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
val &= ~(1 << ctrl->aon.iso_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
+ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
}
/* certain PLLs also need to be ungated from the ASIU top level */
if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
val = readl(pll->asiu_base + ctrl->asiu.offset);
val |= (1 << ctrl->asiu.en_shift);
- writel(val, pll->asiu_base + ctrl->asiu.offset);
+ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val);
}
return 0;
@@ -209,9 +215,7 @@ static void __pll_put_in_reset(struct iproc_pll *pll)
val = readl(pll->pll_base + reset->offset);
val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift);
- writel(val, pll->pll_base + reset->offset);
- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
- readl(pll->pll_base + reset->offset);
+ iproc_pll_write(pll, pll->pll_base, reset->offset, val);
}
static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
@@ -228,9 +232,7 @@ s
[PATCH v3 02/10] clk: cygnus: Convert all macros to all caps
The macros that are being used to initialize the values of the clk
structures should be all caps. Find and replace all of them with their
relevant counterparts.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/clk-cygnus.c | 146 +--
1 file changed, 73 insertions(+), 73 deletions(-)
diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
index 316c603..aac82c6 100644
--- a/drivers/clk/bcm/clk-cygnus.c
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -23,28 +23,28 @@
#include
#include "clk-iproc.h"
-#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, }
+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
-#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
.pwr_shift = ps, .iso_shift = is }
-#define sw_ctrl_val(o, s) { .offset = o, .shift = s, }
+#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
-#define asiu_div_val(o, es, hs, hw, ls, lw) \
+#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \
{ .offset = o, .en_shift = es, .high_shift = hs, \
.high_width = hw, .low_shift = ls, .low_width = lw }
-#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
+#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
.reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
.ka_width = kaw }
-#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo }
+#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
-#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \
+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
.hold_shift = hs, .bypass_shift = bs }
-#define asiu_gate_val(o, es) { .offset = o, .en_shift = es }
+#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }
static void __init cygnus_armpll_init(struct device_node *node)
{
@@ -55,52 +55,52 @@ CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll",
cygnus_armpll_init);
static const struct iproc_pll_ctrl genpll = {
.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
IPROC_CLK_PLL_NEEDS_SW_CFG,
- .aon = aon_val(0x0, 2, 1, 0),
- .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
- .sw_ctrl = sw_ctrl_val(0x10, 31),
- .ndiv_int = reg_val(0x10, 20, 10),
- .ndiv_frac = reg_val(0x10, 0, 20),
- .pdiv = reg_val(0x14, 0, 4),
- .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
- .status = reg_val(0x28, 12, 1),
+ .aon = AON_VAL(0x0, 2, 1, 0),
+ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
+ .sw_ctrl = SW_CTRL_VAL(0x10, 31),
+ .ndiv_int = REG_VAL(0x10, 20, 10),
+ .ndiv_frac = REG_VAL(0x10, 0, 20),
+ .pdiv = REG_VAL(0x14, 0, 4),
+ .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
+ .status = REG_VAL(0x28, 12, 1),
};
static const struct iproc_clk_ctrl genpll_clk[] = {
[BCM_CYGNUS_GENPLL_AXI21_CLK] = {
.channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
.flags = IPROC_CLK_AON,
- .enable = enable_val(0x4, 6, 0, 12),
- .mdiv = reg_val(0x20, 0, 8),
+ .enable = ENABLE_VAL(0x4, 6, 0, 12),
+ .mdiv = REG_VAL(0x20, 0, 8),
},
[BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
.channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
.flags = IPROC_CLK_AON,
- .enable = enable_val(0x4, 7, 1, 13),
- .mdiv = reg_val(0x20, 10, 8),
+ .enable = ENABLE_VAL(0x4, 7, 1, 13),
+ .mdiv = REG_VAL(0x20, 10, 8),
},
[BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
.channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
.flags = IPROC_CLK_AON,
- .enable = enable_val(0x4, 8, 2, 14),
- .mdiv = reg_val(0x20, 20, 8),
+ .enable = ENABLE_VAL(0x4, 8, 2, 14),
+ .mdiv = REG_VAL(0x20, 20, 8),
},
[BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
.channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
.flags = IPROC_CLK_AON,
- .enable = enable_val(0x4, 9, 3, 15),
- .mdiv = reg_val(0x24, 0, 8),
+ .enable = ENABLE_VAL(0x4, 9, 3, 15),
+ .mdiv = REG_VAL(0x24, 0, 8),
},
[BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
.channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
.flags = IPROC_CLK_AON,
- .enable = enable_val(0x4, 10, 4, 16),
- .mdiv = reg_val(0x24, 10, 8),
+ .enable = ENABLE_VAL(0x4, 10, 4, 16),
+ .mdiv = REG_VAL(0x24, 10, 8),
},
[BCM_CYGNUS_GENPLL_CAN_CLK] = {
.channel = BCM_CYGNUS_GENPLL_CAN_CLK,
.flags = IPROC_CLK_AON,
- .ena
[PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
The Broadcom Northstar 2 SoC is architected under the iProc
architecture. It has the following PLLs: GENPLL SCR, GENPLL SW,
LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
Signed-off-by: Jon Mason
---
drivers/clk/Makefile| 2 +-
drivers/clk/bcm/Makefile| 1 +
drivers/clk/bcm/clk-ns2.c | 288
include/dt-bindings/clock/bcm-ns2.h | 72 +
4 files changed, 362 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/bcm/clk-ns2.c
create mode 100644 include/dt-bindings/clock/bcm-ns2.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d08b3e5..6124bd3 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
-obj-$(CONFIG_ARCH_BCM) += bcm/
+obj-y += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_ARCH_MXC) += imx/
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index e258b28..2d1cbc5 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o
clk-iproc-asiu.o
+obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o
obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o
obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
diff --git a/drivers/clk/bcm/clk-ns2.c b/drivers/clk/bcm/clk-ns2.c
new file mode 100644
index 000..a564e92
--- /dev/null
+++ b/drivers/clk/bcm/clk-ns2.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include "clk-iproc.h"
+
+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
+
+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
+ .pwr_shift = ps, .iso_shift = is }
+
+#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
+ .p_reset_shift = prs }
+
+#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift =
kis,\
+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas,\
+ .ka_width = kaw }
+
+#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
+
+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
+ .hold_shift = hs, .bypass_shift = bs }
+
+static const struct iproc_pll_ctrl genpll_scr = {
+ .flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
+ .aon = AON_VAL(0x0, 1, 15, 12),
+ .reset = RESET_VAL(0x4, 2, 1),
+ .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
+ .ndiv_int = REG_VAL(0x8, 4, 10),
+ .pdiv = REG_VAL(0x8, 0, 4),
+ .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
+ .status = REG_VAL(0x0, 27, 1),
+};
+
+
+static const struct iproc_clk_ctrl genpll_scr_clk[] = {
+ /* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
+* in NS2. However, it doesn't appear to be used anywhere, so setting
+* it to 0.
+*/
+ [BCM_NS2_GENPLL_SCR_SCR_CLK] = {
+ .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 18, 12, 0),
+ .mdiv = REG_VAL(0x18, 0, 8),
+ },
+ [BCM_NS2_GENPLL_SCR_FS_CLK] = {
+ .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 19, 13, 0),
+ .mdiv = REG_VAL(0x18, 8, 8),
+ },
+ [BCM_NS2_GENPLL_SCR_AUDIO_CLK] = {
+ .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 20, 14, 0),
+ .mdiv = REG_VAL(0x14, 0, 8),
+ },
+ [BCM_NS2_GENPLL_SCR_CH3_UNUSED] = {
+ .channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 21, 15, 0),
+ .mdiv = REG_VAL(0x14, 8, 8),
+ },
+ [BCM_
[PATCH v3 07/10] clk: iproc: Separate status and control variables
Some PLLs have separate registers for Status and Control. The means the
pll_base needs to be split into 2 new variables, so that those PLLs can
specify device tree registers for those independently. Also, add a new
driver flag to identify this presence of the split, and let the driver
know that additional registers need to be used.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/clk-iproc-pll.c | 96 -
drivers/clk/bcm/clk-iproc.h | 6 +++
2 files changed, 62 insertions(+), 40 deletions(-)
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index d4aab4e..f128a9d 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -74,7 +74,8 @@ struct iproc_clk {
};
struct iproc_pll {
- void __iomem *pll_base;
+ void __iomem *status_base;
+ void __iomem *control_base;
void __iomem *pwr_base;
void __iomem *asiu_base;
@@ -127,7 +128,7 @@ static int pll_wait_for_lock(struct iproc_pll *pll)
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
for (i = 0; i < LOCK_DELAY; i++) {
- u32 val = readl(pll->pll_base + ctrl->status.offset);
+ u32 val = readl(pll->status_base + ctrl->status.offset);
if (val & (1 << ctrl->status.shift))
return 0;
@@ -145,7 +146,7 @@ static void iproc_pll_write(const struct iproc_pll *pll,
void __iomem *base,
writel(val, base + offset);
if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK &&
-base == pll->pll_base))
+(base == pll->status_base || base == pll->control_base)))
val = readl(base + offset);
}
@@ -161,9 +162,9 @@ static void __pll_disable(struct iproc_pll *pll)
}
if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
- val = readl(pll->pll_base + ctrl->aon.offset);
+ val = readl(pll->control_base + ctrl->aon.offset);
val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val);
+ iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val);
}
if (pll->pwr_base) {
@@ -184,9 +185,9 @@ static int __pll_enable(struct iproc_pll *pll)
u32 val;
if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
- val = readl(pll->pll_base + ctrl->aon.offset);
+ val = readl(pll->control_base + ctrl->aon.offset);
val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val);
+ iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val);
}
if (pll->pwr_base) {
@@ -213,9 +214,9 @@ static void __pll_put_in_reset(struct iproc_pll *pll)
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
- val = readl(pll->pll_base + reset->offset);
+ val = readl(pll->control_base + reset->offset);
val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift);
- iproc_pll_write(pll, pll->pll_base, reset->offset, val);
+ iproc_pll_write(pll, pll->control_base, reset->offset, val);
}
static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
@@ -226,17 +227,17 @@ static void __pll_bring_out_reset(struct iproc_pll *pll,
unsigned int kp,
const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter;
- val = readl(pll->pll_base + dig_filter->offset);
+ val = readl(pll->control_base + dig_filter->offset);
val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift |
bit_mask(dig_filter->kp_width) << dig_filter->kp_shift |
bit_mask(dig_filter->ka_width) << dig_filter->ka_shift);
val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift |
ka << dig_filter->ka_shift;
- iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val);
+ iproc_pll_write(pll, pll->control_base, dig_filter->offset, val);
- val = readl(pll->pll_base + reset->offset);
+ val = readl(pll->control_base + reset->offset);
val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift;
- iproc_pll_write(pll, pll->pll_base, reset->offset, val);
+ iproc_pll_write(pll, pll->control_base, reset->offset, val);
}
static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_inde
[PATCH v3 06/10] clk: iproc: Split off dig_filter
The PLL loop filter/gain can be located in a separate register on some
SoCs. Split these off into a separate variable, so that an offset can
be added if necessary. Also, make the necessary modifications to the
Cygnus and NSP drivers for this change.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/clk-cygnus.c| 17 +++--
drivers/clk/bcm/clk-iproc-pll.c | 14 +-
drivers/clk/bcm/clk-iproc.h | 10 +-
drivers/clk/bcm/clk-nsp.c | 14 +-
4 files changed, 38 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
index aac82c6..3a228b6 100644
--- a/drivers/clk/bcm/clk-cygnus.c
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -34,9 +34,11 @@
{ .offset = o, .en_shift = es, .high_shift = hs, \
.high_width = hw, .low_shift = ls, .low_width = lw }
-#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
- .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
- .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
+#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
+ .p_reset_shift = prs }
+
+#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift =
kis,\
+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas,\
.ka_width = kaw }
#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
@@ -56,7 +58,8 @@ static const struct iproc_pll_ctrl genpll = {
.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
IPROC_CLK_PLL_NEEDS_SW_CFG,
.aon = AON_VAL(0x0, 2, 1, 0),
- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
+ .reset = RESET_VAL(0x0, 11, 10),
+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
.sw_ctrl = SW_CTRL_VAL(0x10, 31),
.ndiv_int = REG_VAL(0x10, 20, 10),
.ndiv_frac = REG_VAL(0x10, 0, 20),
@@ -114,7 +117,8 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll",
cygnus_genpll_clk_init);
static const struct iproc_pll_ctrl lcpll0 = {
.flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
.aon = AON_VAL(0x0, 2, 5, 4),
- .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
+ .reset = RESET_VAL(0x0, 31, 30),
+ .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4),
.sw_ctrl = SW_CTRL_VAL(0x4, 31),
.ndiv_int = REG_VAL(0x4, 16, 10),
.pdiv = REG_VAL(0x4, 26, 4),
@@ -191,7 +195,8 @@ static const struct iproc_pll_ctrl mipipll = {
IPROC_CLK_NEEDS_READ_BACK,
.aon = AON_VAL(0x0, 4, 17, 16),
.asiu = ASIU_GATE_VAL(0x0, 3),
- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
+ .reset = RESET_VAL(0x0, 11, 10),
+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4),
.ndiv_int = REG_VAL(0x10, 20, 10),
.ndiv_frac = REG_VAL(0x10, 0, 20),
.pdiv = REG_VAL(0x14, 0, 4),
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index 74cdd66..d4aab4e 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -224,13 +224,17 @@ static void __pll_bring_out_reset(struct iproc_pll *pll,
unsigned int kp,
u32 val;
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
+ const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter;
+
+ val = readl(pll->pll_base + dig_filter->offset);
+ val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift |
+ bit_mask(dig_filter->kp_width) << dig_filter->kp_shift |
+ bit_mask(dig_filter->ka_width) << dig_filter->ka_shift);
+ val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift |
+ ka << dig_filter->ka_shift;
+ iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val);
val = readl(pll->pll_base + reset->offset);
- val &= ~(bit_mask(reset->ki_width) << reset->ki_shift |
-bit_mask(reset->kp_width) << reset->kp_shift |
-bit_mask(reset->ka_width) << reset->ka_shift);
- val |= ki << reset->ki_shift | kp << reset->kp_shift |
- ka << reset->ka_shift;
val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift;
iproc_pll_write(pll, pll->pll_base, reset->offset, val);
}
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
index ff7bfad..b71c197 100644
--- a/drivers/clk/bcm/clk-iproc.h
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -94,12 +94,19 @@ struct iproc_pll_aon_pwr_ctrl {
};
/*
- * Control of the PLL reset, with Ki, Kp, and Ka parameters
+ * Control of the PLL reset
*/
struct iproc_pll_reset_ctrl {
unsigned int offset;
unsigned int
[PATCH v3 10/10] clk: iproc: define Broadcom NS2 iProc clock binding
Document the device tree bindings for Broadcom Northstar 2 architecture based clock controller Signed-off-by: Jon Mason --- .../bindings/clock/brcm,iproc-clocks.txt | 48 ++ 1 file changed, 48 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index b3c3e9d..ede65a5 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -160,3 +160,51 @@ Northstar Plus. These clock IDs are defined in: pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK ddr_phylcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK + +Northstar 2 +--- +PLL and leaf clock compatible strings for Northstar 2 are: +"brcm,ns2-genpll-scr" +"brcm,ns2-genpll-sw" +"brcm,ns2-lcpll-ddr" +"brcm,ns2-lcpll-ports" + +The following table defines the set of PLL/clock index and ID for Northstar 2. +These clock IDs are defined in: +"include/dt-bindings/clock/bcm-ns2.h" + +Clock Source Index ID +---- - - +crystalN/A N/A N/A + +genpll_scr crystal 0 BCM_NS2_GENPLL_SCR +scrgenpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK +fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK +audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK +ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED +ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED +ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED + +genpll_sw crystal 0 BCM_NS2_GENPLL_SW +rpegenpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK +250genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK +nicgenpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK +chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK +port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK +sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK + +lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR +pcie_sata_usb lcpll_ddr1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK +ddrlcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK +ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED +ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED +ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED +ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED + +lcpll_portscrystal 0 BCM_NS2_LCPLL_PORTS +wanlcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK +rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK +ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED +ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED +ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED +ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 09/10] clk: iproc: define Broadcom NSP iProc clock binding
Document the device tree bindings for Broadcom Northstar Plus architecture based clock controller Signed-off-by: Jon Mason --- .../bindings/clock/brcm,iproc-clocks.txt | 30 ++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index da8d9bb..b3c3e9d 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -130,3 +130,33 @@ These clock IDs are defined in: ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED + +Northstar and Northstar Plus +-- +PLL and leaf clock compatible strings for Northstar and Northstar Plus are: + "brcm,nsp-armpll" + "brcm,nsp-genpll" + "brcm,nsp-lcpll0" + +The following table defines the set of PLL/clock index and ID for Northstar and +Northstar Plus. These clock IDs are defined in: +"include/dt-bindings/clock/bcm-nsp.h" + +Clock Source Index ID +---- - - +crystalN/A N/A N/A + +armpll crystal N/A N/A + +genpll crystal 0 BCM_NSP_GENPLL +phygenpll 1 BCM_NSP_GENPLL_PHY_CLK +ethernetclkgenpll 2 BCM_NSP_GENPLL_ENET_SW_CLK +usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK +iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK +sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK +sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK + +lcpll0 crystal 0 BCM_NSP_LCPLL0 +pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK +sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK +ddr_phylcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/10] clk: iproc: add support for BCM NS, NSP, and NS2
v3 - Added a patch to fix cygnus clk link failures, and added back the DT documentation patches that were removed from v2. v2 - Added a patch to change the Cygnus clk macros to uppercase, removed the device tree changes from the series (will send out those as an RFC), and other minor changes that Stephen Boyd requested. This patch series adds support for the Broadcom Northstar, Northstar Plus, and Northstar 2 clocks. Some slight modifications were necessary to clk-iproc-pll to get Northstar and Northstar Plus working, due to differences in register layout. This is the reason why the first patch is necessary. Some more modifications were necessary to clk-iproc-pll to get Northstar 2 working, due to differences in register layout (and resulting fallout in Cygnus and NSP). This is the reason why the sixth and seventh patches are necessary. The fifth patch is clean-up to prevent accidentally forgetting to adjust for the base write errata (which happened a few times, but was caught in internal review). Thanks, Jon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 7/7] clk: ns2: add clock support for Broadcom Northstar 2 SoC
On Thu, Oct 15, 2015 at 08:54:34PM +0200, Arnd Bergmann wrote: > On Thursday 15 October 2015 14:43:45 Jon Mason wrote: > > On Thu, Oct 15, 2015 at 11:36:19AM -0700, Scott Branden wrote: > > > Jon, > > > > > > Can you add this to your patchset and change COMMON_CLK_IPROC to a > > > silent option? > > > > Sure, I'll add this (and make it silent), as well as adding the > > documentation patches back to this series (per Ray's suggestion), and > > will resend. > > > > Thanks! > > Arnd I'm tweaking the patch slightly. So, I'll remove Scott's ack and let him re-ack if he still likes it. I moved the selection of the COMMON_CLK_IPROC to ARCH_BCM_IPROC, as all iProc SoCs will soon have clk drivers (and enabling it without a SoC driver won't hurt anything). Also, the slient enable option is added. Thanks, Jon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 7/7] clk: ns2: add clock support for Broadcom Northstar 2 SoC
On Thu, Oct 15, 2015 at 11:36:19AM -0700, Scott Branden wrote: > Jon, > > Can you add this to your patchset and change COMMON_CLK_IPROC to a > silent option? Sure, I'll add this (and make it silent), as well as adding the documentation patches back to this series (per Ray's suggestion), and will resend. Thanks, Jon > > On 15-10-14 01:16 PM, Arnd Bergmann wrote: > >On Wednesday 14 October 2015 12:46:19 Scott Branden wrote: > >>> > >>>My patch fixes it by always selecting COMMON_CLK_IPROC from > >>>ARCH_BCM_CYGNUS. I wasn't sure whether you want COMMON_CLK_IPROC > >>>to still be user-selectable, so I left that in place. Normally > >>>I'd expect it to be a silent option though, that just gets > >>>implicitly enabled whenever a platform that needs it is built > >>>into the kernel. > >>COMMON_CLK_IPROC can be a silent option and selected as Arnd has done below. > > > >Ok, please do that then. If you want to apply my patch directly, > >you can remove that last paragraph from the description. > > > >>>Signed-off-by: Arnd Bergmann > >>Acked-by: Scott Branden > > > >Thanks for taking a look! > > > > Arnd > > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC] ARM: BCM: Add SMP support for Broadcom 4708
ARM: BCM: Add SMP support for Broadcom 4708
Add SMP support for Broadcom's 4708 SoCs.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm4708.dtsi | 2 ++
arch/arm/boot/dts/bcm94708.dts | 2 +-
arch/arm/mach-bcm/Kconfig | 1 +
arch/arm/mach-bcm/Makefile | 3 +++
4 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
index 31141e8..22a41df 100644
--- a/arch/arm/boot/dts/bcm4708.dtsi
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -15,6 +15,8 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "brcm,bcm-nsp-smp";
+ secondary-boot-reg = <0x0400>;
cpu@0 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts
index f60bb1d..49682d6 100644
--- a/arch/arm/boot/dts/bcm94708.dts
+++ b/arch/arm/boot/dts/bcm94708.dts
@@ -32,7 +32,7 @@
/dts-v1/;
-#include "bcm5301x.dtsi"
+#include "bcm4708.dtsi"
/ {
model = "NorthStar SVK (BCM94708)";
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 2e9dbb5..4fc8fa3 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
config ARCH_BCM_5301X
bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
select ARCH_BCM_IPROC
+ select HAVE_SMP
help
Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 36a4ca30..3ca1cf1 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835)+= board_bcm2835.o
# BCM5301X
obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
+ifeq ($(CONFIG_ARCH_BCM_5301X),y)
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
+endif
# BCM63XXx
ifeq ($(CONFIG_ARCH_BCM_63XX),y)
--
1.9.1
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Re: [PATCH 3/3] ARM: BCM: Add SMP support for Broadcom NSP
On Wed, Oct 14, 2015 at 06:40:04PM -0400, Jon Mason wrote:
> On Thu, Oct 15, 2015 at 12:26:25AM +0200, Hauke Mehrtens wrote:
> > On 10/14/2015 07:47 PM, Kapil Hali wrote:
> > > Add SMP support for Broadcom's Northstar Plus SoC,
> > > cpu enable method and pen_release procedures. This
> > > changes also consolidates iProc family's - BCM NSP
> > > and BCM Kona, SMP handling in a common file.
> >
> > This will probably also work on normal Northstar CPUs without changes.
>
> I think all that needs to be changed is adding to
> arch/arm/boot/dts/bcm4708.dts
>
> + enable-method = "brcm,bcm-nsp-smp";
> + secondary-boot-reg = <0x0400>;
>
> But I have not been able to confirm that yet.
I was able to confirm it on my BCM94708 SVK. I'll send out the patch
which enables it shortly.
Thanks,
Jon
>
> Thanks,
> Jon
>
> >
> > > Northstar Plus SoC is based on ARM Cortex-A9
> > > revision r3p0 which requires configuration for ARM
> > > Errata 764369 for SMP. This change adds the needed
> > > configuration option.
> > >
> > > Signed-off-by: Kapil Hali
> > > ---
> > > arch/arm/mach-bcm/Kconfig | 2 +
> > > arch/arm/mach-bcm/Makefile | 8 +-
> > > arch/arm/mach-bcm/bcm_nsp.h | 19
> > > arch/arm/mach-bcm/headsmp.S | 37
> > > arch/arm/mach-bcm/{kona_smp.c => platsmp.c} | 142
> > > ++--
> > > 5 files changed, 197 insertions(+), 11 deletions(-)
> > > create mode 100644 arch/arm/mach-bcm/bcm_nsp.h
> > > create mode 100644 arch/arm/mach-bcm/headsmp.S
> > > rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (63%)
> > >
> > > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> > > index 1679fa4..2e9dbb5 100644
> > > --- a/arch/arm/mach-bcm/Kconfig
> > > +++ b/arch/arm/mach-bcm/Kconfig
> > > @@ -40,6 +40,8 @@ config ARCH_BCM_NSP
> > > select ARCH_BCM_IPROC
> > > select ARM_ERRATA_754322
> > > select ARM_ERRATA_775420
> > > + select ARM_ERRATA_764369 if SMP
> > > + select HAVE_SMP
> > > help
> > > Support for Broadcom Northstar Plus SoC.
> > > Broadcom Northstar Plus family of SoCs are used for switching control
> > > diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
> > > index 892261f..36a4ca30 100644
> > > --- a/arch/arm/mach-bcm/Makefile
> > > +++ b/arch/arm/mach-bcm/Makefile
> > > @@ -14,7 +14,11 @@
> > > obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
> > >
> > > # Northstar Plus
> > > -obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
> > > +obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
> > > +
> > > +ifeq ($(CONFIG_ARCH_BCM_NSP),y)
> > > +obj-$(CONFIG_SMP)+= headsmp.o platsmp.o
> > > +endif
> > >
> > > # BCM281XX
> > > obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
> > > @@ -23,7 +27,7 @@ obj-$(CONFIG_ARCH_BCM_281XX)+= board_bcm281xx.o
> > > obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
> > >
> > > # BCM281XX and BCM21664 SMP support
> > > -obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
> > > +obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
> > >
> > > # BCM281XX and BCM21664 L2 cache control
> > > obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
> > > diff --git a/arch/arm/mach-bcm/bcm_nsp.h b/arch/arm/mach-bcm/bcm_nsp.h
> > > new file mode 100644
> > > index 000..58e1e80
> > > --- /dev/null
> > > +++ b/arch/arm/mach-bcm/bcm_nsp.h
> > > @@ -0,0 +1,19 @@
> > > +/*
> > > + * Copyright (C) 2015 Broadcom Corporation
> > > + *
> > > + * This program is free software; you can redistribute it and/or
> > > + * modify it under the terms of the GNU General Public License as
> > > + * published by the Free Software Foundation version 2.
> > > + *
> > > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > > + * kind, whether express or implied; without even the implied warranty
> > > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > > + * GNU General Public License for more details.
> > > + */
> > > +
> > > +#ifndef __BCM_NSP_H
> > > +#define __BCM_NSP_H
> > > +
> > >
Re: [PATCH 3/3] ARM: BCM: Add SMP support for Broadcom NSP
On Thu, Oct 15, 2015 at 12:26:25AM +0200, Hauke Mehrtens wrote:
> On 10/14/2015 07:47 PM, Kapil Hali wrote:
> > Add SMP support for Broadcom's Northstar Plus SoC,
> > cpu enable method and pen_release procedures. This
> > changes also consolidates iProc family's - BCM NSP
> > and BCM Kona, SMP handling in a common file.
>
> This will probably also work on normal Northstar CPUs without changes.
I think all that needs to be changed is adding to
arch/arm/boot/dts/bcm4708.dts
+ enable-method = "brcm,bcm-nsp-smp";
+ secondary-boot-reg = <0x0400>;
But I have not been able to confirm that yet.
Thanks,
Jon
>
> > Northstar Plus SoC is based on ARM Cortex-A9
> > revision r3p0 which requires configuration for ARM
> > Errata 764369 for SMP. This change adds the needed
> > configuration option.
> >
> > Signed-off-by: Kapil Hali
> > ---
> > arch/arm/mach-bcm/Kconfig | 2 +
> > arch/arm/mach-bcm/Makefile | 8 +-
> > arch/arm/mach-bcm/bcm_nsp.h | 19
> > arch/arm/mach-bcm/headsmp.S | 37
> > arch/arm/mach-bcm/{kona_smp.c => platsmp.c} | 142
> > ++--
> > 5 files changed, 197 insertions(+), 11 deletions(-)
> > create mode 100644 arch/arm/mach-bcm/bcm_nsp.h
> > create mode 100644 arch/arm/mach-bcm/headsmp.S
> > rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (63%)
> >
> > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> > index 1679fa4..2e9dbb5 100644
> > --- a/arch/arm/mach-bcm/Kconfig
> > +++ b/arch/arm/mach-bcm/Kconfig
> > @@ -40,6 +40,8 @@ config ARCH_BCM_NSP
> > select ARCH_BCM_IPROC
> > select ARM_ERRATA_754322
> > select ARM_ERRATA_775420
> > + select ARM_ERRATA_764369 if SMP
> > + select HAVE_SMP
> > help
> > Support for Broadcom Northstar Plus SoC.
> > Broadcom Northstar Plus family of SoCs are used for switching control
> > diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
> > index 892261f..36a4ca30 100644
> > --- a/arch/arm/mach-bcm/Makefile
> > +++ b/arch/arm/mach-bcm/Makefile
> > @@ -14,7 +14,11 @@
> > obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
> >
> > # Northstar Plus
> > -obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
> > +obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
> > +
> > +ifeq ($(CONFIG_ARCH_BCM_NSP),y)
> > +obj-$(CONFIG_SMP) += headsmp.o platsmp.o
> > +endif
> >
> > # BCM281XX
> > obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
> > @@ -23,7 +27,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
> > obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
> >
> > # BCM281XX and BCM21664 SMP support
> > -obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
> > +obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
> >
> > # BCM281XX and BCM21664 L2 cache control
> > obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
> > diff --git a/arch/arm/mach-bcm/bcm_nsp.h b/arch/arm/mach-bcm/bcm_nsp.h
> > new file mode 100644
> > index 000..58e1e80
> > --- /dev/null
> > +++ b/arch/arm/mach-bcm/bcm_nsp.h
> > @@ -0,0 +1,19 @@
> > +/*
> > + * Copyright (C) 2015 Broadcom Corporation
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation version 2.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __BCM_NSP_H
> > +#define __BCM_NSP_H
> > +
> > +extern void nsp_secondary_startup(void);
> > +
> > +#endif /* __BCM_NSP_H */
> > diff --git a/arch/arm/mach-bcm/headsmp.S b/arch/arm/mach-bcm/headsmp.S
> > new file mode 100644
> > index 000..0da13b2
> > --- /dev/null
> > +++ b/arch/arm/mach-bcm/headsmp.S
> > @@ -0,0 +1,37 @@
> > +/*
> > + * Copyright (C) 2015 Broadcom Corporation
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation version 2.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include
> > +
> > +/*
> > + * iProc specific entry point for secondary CPUs. This provides
> > + * a "holding pen" into which all secondary cores are held until
> > + * we are ready for them to initialise.
> > + */
> > +ENTRY(nsp_secondary_startup)
> > + mrc p15, 0, r0, c0, c0, 5
> > + and r0, r0, #15
> > + adr r4, 1f
> > + ldmia r4, {r5, r6}
> > + sub r4, r4, r5
>
[PATCH v2 2/2] ARM: dts: bcm5301x: Add BCM SVK DT files
Add device tree files for Broadcom Northstar based SVKs. Since the
bcm5301x.dtsi already exists, all that is necessary is the dts files to
enable the UARTs (and specify the RAM size for the 4708/9). With these
files, the SVKs are able to boot to shell.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/Makefile | 5 +++-
arch/arm/boot/dts/bcm94708.dts | 56 +++
arch/arm/boot/dts/bcm94709.dts | 56 +++
arch/arm/boot/dts/bcm953012k.dts | 63
4 files changed, 179 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/bcm94708.dts
create mode 100644 arch/arm/boot/dts/bcm94709.dts
create mode 100644 arch/arm/boot/dts/bcm953012k.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 233159d..96a1b58 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -72,7 +72,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm47081-buffalo-wzr-900dhp.dtb \
bcm4709-asus-rt-ac87u.dtb \
bcm4709-buffalo-wxr-1900dhp.dtb \
- bcm4709-netgear-r8000.dtb
+ bcm4709-netgear-r8000.dtb \
+ bcm94708.dtb \
+ bcm94709.dtb \
+ bcm953012k.dtb
dtb-$(CONFIG_ARCH_BCM_63XX) += \
bcm963138dvt.dtb
dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts
new file mode 100644
index 000..f60bb1d
--- /dev/null
+++ b/arch/arm/boot/dts/bcm94708.dts
@@ -0,0 +1,56 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ ** Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ ** Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ ** Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm5301x.dtsi"
+
+/ {
+ model = "NorthStar SVK (BCM94708)";
+ compatible = "brcm,bcm94708", "brcm,bcm4708";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ reg = <0x 0x0800>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/bcm94709.dts
new file mode 100644
index 000..88de313
--- /dev/null
+++ b/arch/arm/boot/dts/bcm94709.dts
@@ -0,0 +1,56 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ ** Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ ** Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ ** Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PU
[PATCH v2 1/2] dt-bindings: Add new boards to bcm4708 DT bindings
Add the 4708, 4709, and 953012k SVKs to the the documentation for the Broadcom Northstar device tree bindings. Signed-off-by: Jon Mason --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt index 6b0f49f..b9cc308 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt @@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following properties: Required root node property: +bcm94708 compatible = "brcm,bcm4708"; + +bcm94709 +compatible = "brcm,bcm4709"; + +bcm953012 +compatible = "brcm,bcm53012"; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/2] ARM: dts: bcm5301x: Add BCM SVK DT files
This patch series adds the device tree files for the Broadcom Northstar based SVKs. Changes in v2: * Reorder the patches to add the DT binding documentation prior to the new DT files * Removed the DT documentation compat strings to only the SoCs, not the individual boards * Fixed the compat strings in the individual device tree files * Added the memory node and removed the "mem=" from the bootargs Thanks, Jon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding
On Tue, Oct 13, 2015 at 03:24:52PM -0700, Ray Jui wrote: > Same as this patch. I thought device tree binding document should go > with the clock driver changes. > > Strictly speaking, device tree binding document should always go before > the driver changes. In the binding document the DT interface is defined, > then changes are implemented in the driver. I split them off this way due to the clk maintainer not wanting to pull in any device tree changes. Since the documentation is for the device tree enties, it makes logical sense to me that they be in the same device tree series. If Stephen will pull these in with the clk changes, I am more than happy to have it done by him :) Thanks, Jon > > Ray > > On 10/13/2015 2:22 PM, Jon Mason wrote: > > Document the device tree bindings for Broadcom Northstar 2 architecture > > based clock controller > > > > Signed-off-by: Jon Mason > > --- > > .../bindings/clock/brcm,iproc-clocks.txt | 48 > > ++ > > 1 file changed, 48 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > > b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > > index b3c3e9d..ede65a5 100644 > > --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > > +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > > @@ -160,3 +160,51 @@ Northstar Plus. These clock IDs are defined in: > > pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK > > sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK > > ddr_phylcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK > > + > > +Northstar 2 > > +--- > > +PLL and leaf clock compatible strings for Northstar 2 are: > > +"brcm,ns2-genpll-scr" > > +"brcm,ns2-genpll-sw" > > +"brcm,ns2-lcpll-ddr" > > +"brcm,ns2-lcpll-ports" > > + > > +The following table defines the set of PLL/clock index and ID for > > Northstar 2. > > +These clock IDs are defined in: > > +"include/dt-bindings/clock/bcm-ns2.h" > > + > > +Clock Source Index ID > > +---- - - > > +crystalN/A N/A N/A > > + > > +genpll_scr crystal 0 BCM_NS2_GENPLL_SCR > > +scrgenpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK > > +fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK > > +audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK > > +ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED > > +ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED > > +ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED > > + > > +genpll_sw crystal 0 BCM_NS2_GENPLL_SW > > +rpegenpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK > > +250genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK > > +nicgenpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK > > +chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK > > +port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK > > +sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK > > + > > +lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR > > +pcie_sata_usb lcpll_ddr1 > > BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK > > +ddrlcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK > > +ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED > > +ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED > > +ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED > > +ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED > > + > > +lcpll_portscrystal 0 BCM_NS2_LCPLL_PORTS > > +wanlcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK > > +rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK > > +ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED > > +ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED > > +ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED > > +ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] ARM: dts: bcm5301x: Add BCM SVK DT files
On Tue, Oct 13, 2015 at 03:43:20PM -0700, Ray Jui wrote:
>
>
> On 10/13/2015 2:38 PM, Jon Mason wrote:
> > On Sat, Oct 10, 2015 at 04:39:00PM +0200, Hauke Mehrtens wrote:
> >> On 10/03/2015 12:22 AM, Jon Mason wrote:
> >>> Add device tree files for Broadcom Northstar based SVKs. Since the
> >>> bcm5301x.dtsi already exists, all that is necessary is the dts files to
> >>> enable the UARTs (and specify the RAM size for the 4708/9). With these
> >>> files, the SVKs are able to boot to shell.
> >>>
> >>> Signed-off-by: Jon Mason
> >>> ---
> >>> arch/arm/boot/dts/Makefile | 5 +++-
> >>> arch/arm/boot/dts/bcm94708.dts | 52 +++
> >>> arch/arm/boot/dts/bcm94709.dts | 52 +++
> >>> arch/arm/boot/dts/bcm953012k.dts | 59
> >>>
> >>> 4 files changed, 167 insertions(+), 1 deletion(-)
> >>> create mode 100644 arch/arm/boot/dts/bcm94708.dts
> >>> create mode 100644 arch/arm/boot/dts/bcm94709.dts
> >>> create mode 100644 arch/arm/boot/dts/bcm953012k.dts
> >>>
>
> >>> +&uart0 {
> >>> + clock-frequency = <62499840>;
> >>
> >> Just out of curiosity on what does this clock frequency depend? I saw
> >> your patch adding a real clock driver which should make this obsolete.
> >
> > Better to add this now, as the device tree part might be out of sync
> > for a time.
>
> Sure, this can potentially be a reason to not using the real clock node
> and just use a hardcoded clock frequency for now, until the other clock
> change is merged, then you can submit another patch to use it.
>
> Also, is it not better to make the UARTs a static clock
> > and not dependent on the clk driver?
> >
>
> I disagree. You should always use the real clock driver for querying the
> clock frequency, in the case when the clock driver is available.
>
> Today one can change the core clock for UART in the bootloader for
> various reasons (and we saw that happening a lot in the past), which in
> this case will make your kernel not seeing any console output.
>
> By always querying the clock rate based on real registers instead of a
> hardcoded value, you don't have that issue and your kernel is less
> dependent on any changes in the bootloader.
Fair enough. This is moot until the clk driver changes get pulled in.
This file can be changed at that time :)
Thanks,
Jon
>
> > Thanks,
> > Jon
> >
--
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Re: [RFC 1/5] clk: iproc: define Broadcom NSP iProc clock binding
On Tue, Oct 13, 2015 at 03:17:36PM -0700, Ray Jui wrote: > Shouldn't the device tree binding document go with the other patch > series since both the binding document and drivers are merged by Michael > or Stephen? > > On 10/13/2015 2:22 PM, Jon Mason wrote: > > Document the device tree bindings for Broadcom Northstar Plus > > architecture based clock controller > > > > Signed-off-by: Jon Mason > > --- > > .../bindings/clock/brcm,iproc-clocks.txt | 30 > > ++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > > b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > > index da8d9bb..b3c3e9d 100644 > > --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > > +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt > > @@ -130,3 +130,33 @@ These clock IDs are defined in: > > ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED > > ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED > > ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED > > + > > +Northstar and Northstar Plus > > +-- > > +PLL and leaf clock compatible strings for Northstar and Northstar Plus are: > > + "brcm,nsp-armpll" > > + "brcm,nsp-genpll" > > + "brcm,nsp-lcpll0" > > So the current clock driver also supports NS? That will be nice and that > indicates all the clock related registers/offsets are exactly the same > between NS and NSP? Yes. The register offsets are different, but everything else is identical. > > > + > > +The following table defines the set of PLL/clock index and ID for > > Northstar and > > +Northstar Plus. These clock IDs are defined in: > > +"include/dt-bindings/clock/bcm-nsp.h" > > + > > +Clock Source Index ID > > +---- - - > > +crystalN/A N/A N/A > > + > > +armpll crystal N/A N/A > > + > > +genpll crystal 0 BCM_NSP_GENPLL > > +phygenpll 1 BCM_NSP_GENPLL_PHY_CLK > > +ethernetclkgenpll 2 BCM_NSP_GENPLL_ENET_SW_CLK > > +usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK > > +iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK > > +sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK > > +sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK > > + > > +lcpll0 crystal 0 BCM_NSP_LCPLL0 > > +pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK > > +sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK > > +ddr_phylcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] dt-bindings: Add new boards to bcm4708 DT bindings
On Tue, Oct 13, 2015 at 03:37:49PM -0700, Florian Fainelli wrote: > On 13/10/15 14:40, Jon Mason wrote: > > On Sat, Oct 10, 2015 at 04:42:04PM +0200, Hauke Mehrtens wrote: > >> On 10/03/2015 12:22 AM, Jon Mason wrote: > >>> Add the 4708, 4709, and 953012k SVKs to the the documentation for the > >>> Broadcom Northstar device tree bindings. > >>> > >>> Signed-off-by: Jon Mason > >>> --- > >>> Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++ > >>> 1 file changed, 7 insertions(+) > >>> > >>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt > >>> b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt > >>> index 6b0f49f..bdf4c06 100644 > >>> --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt > >>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt > >> > >> What should be documented in this file? This is more a question to the > >> guys more familiar with arm in Linux. Currently the Linux kernel only > >> supports brcm,bcm4708 and all goes back to that one. > > > > I was under the impression that all boards should be added to these > > files. We have been doing so for Cygnus and NSP. > > Tracking exactly which boards are supported by the brcm,bcm4708 > compatible string might be tedious, I tend to agree with just listing > the supported SoCs, and leaving the specific board compatibles to the > individual DTS files instead. Ok, I'll simply add entries for NS and 4709 to this. Thanks, Jon > > > > > Thanks, > > Jon > > > >> > >>> @@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following > >>> properties: > >>> > >>> Required root node property: > >>> > >>> +bcm94709 > >>> compatible = "brcm,bcm4708"; > >>> + > >>> +bcm94709 > >>> +compatible = "brcm,bcm4709", "brcm,bcm4708"; > >>> + > >>> +bcm953012k > >>> +compatible = "brcm,bcm5301k", "brcm,bcm4708"; > >>> > >> > > > -- > Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 7/7] clk: ns2: add clock support for Broadcom Northstar 2 SoC
On Tue, Oct 13, 2015 at 11:18:53PM +0200, Arnd Bergmann wrote: > On Tuesday 13 October 2015 17:08:05 Jon Mason wrote: > > @@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o > > obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o > > obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o > > obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o > > clk-iproc-asiu.o > > +obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o > > obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o > > obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o > > obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o > > If I understand this right, both CYGNUS and NS2 are IPROC based, but it > looks like you now require building the clk-ns2 file for both? There is no need for the NS2 clk code to be used by anything other than NS2. There is no unique CONFIG_ identifier for NS2 in the code that was accepted upstream. If I can add one for NS2, then I can split this off similar to Cygnus or NSP. If not, then it has to be lumped in with all of iProc. :( > On a related note, I'm seeing problems when CONFIG_CYGNUS is set but > CONFIG_COMMON_CLK_IPROC is disabled, as that currently leads to a link > failure. I can double check, but it should be on by default when Cygnus is enabled. If you send me the error, I'll be happy to fix it. Thanks, Jon > > Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] dt-bindings: Add new boards to bcm4708 DT bindings
On Sat, Oct 10, 2015 at 04:42:04PM +0200, Hauke Mehrtens wrote: > On 10/03/2015 12:22 AM, Jon Mason wrote: > > Add the 4708, 4709, and 953012k SVKs to the the documentation for the > > Broadcom Northstar device tree bindings. > > > > Signed-off-by: Jon Mason > > --- > > Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt > > b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt > > index 6b0f49f..bdf4c06 100644 > > --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt > > +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt > > What should be documented in this file? This is more a question to the > guys more familiar with arm in Linux. Currently the Linux kernel only > supports brcm,bcm4708 and all goes back to that one. I was under the impression that all boards should be added to these files. We have been doing so for Cygnus and NSP. Thanks, Jon > > > @@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following > > properties: > > > > Required root node property: > > > > +bcm94709 > > compatible = "brcm,bcm4708"; > > + > > +bcm94709 > > +compatible = "brcm,bcm4709", "brcm,bcm4708"; > > + > > +bcm953012k > > +compatible = "brcm,bcm5301k", "brcm,bcm4708"; > > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] ARM: dts: bcm5301x: Add BCM SVK DT files
On Sat, Oct 10, 2015 at 04:39:00PM +0200, Hauke Mehrtens wrote:
> On 10/03/2015 12:22 AM, Jon Mason wrote:
> > Add device tree files for Broadcom Northstar based SVKs. Since the
> > bcm5301x.dtsi already exists, all that is necessary is the dts files to
> > enable the UARTs (and specify the RAM size for the 4708/9). With these
> > files, the SVKs are able to boot to shell.
> >
> > Signed-off-by: Jon Mason
> > ---
> > arch/arm/boot/dts/Makefile | 5 +++-
> > arch/arm/boot/dts/bcm94708.dts | 52 +++
> > arch/arm/boot/dts/bcm94709.dts | 52 +++
> > arch/arm/boot/dts/bcm953012k.dts | 59
> >
> > 4 files changed, 167 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/boot/dts/bcm94708.dts
> > create mode 100644 arch/arm/boot/dts/bcm94709.dts
> > create mode 100644 arch/arm/boot/dts/bcm953012k.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 233159d..96a1b58 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -72,7 +72,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
> > bcm47081-buffalo-wzr-900dhp.dtb \
> > bcm4709-asus-rt-ac87u.dtb \
> > bcm4709-buffalo-wxr-1900dhp.dtb \
> > - bcm4709-netgear-r8000.dtb
> > + bcm4709-netgear-r8000.dtb \
> > + bcm94708.dtb \
> > + bcm94709.dtb \
> > + bcm953012k.dtb
> > dtb-$(CONFIG_ARCH_BCM_63XX) += \
> > bcm963138dvt.dtb
> > dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
> > diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts
> > new file mode 100644
> > index 000..57a74c6
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/bcm94708.dts
>
> Currently the files are named beginning with the chip name something
> like this should fit better the other naming schema:
> arch/arm/boot/dts/bcm4708-brcm-bcm94708.dts
Sorry, I was following the namign schema that we've been using on
other Broadcom SVKs in the Linux device tree directory. For example,
arch/arm/boot/dts/bcm911360_entphn.dts
arch/arm/boot/dts/bcm911360k.dts
arch/arm/boot/dts/bcm958300k.dts
arch/arm/boot/dts/bcm958305k.dts
arch/arm/boot/dts/bcm958625k.dts
arch/arm/boot/dts/bcm963138dvt.dts
Also, this is the name we have been using internally. So, it will
making migrating to newer kernels much easier.
>
> > @@ -0,0 +1,52 @@
> > +/*
> > + * BSD LICENSE
> > + *
> > + * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
> > + *
> > + * Redistribution and use in source and binary forms, with or without
> > + * modification, are permitted provided that the following conditions
> > + * are met:
> > + *
> > + ** Redistributions of source code must retain the above copyright
> > + * notice, this list of conditions and the following disclaimer.
> > + ** Redistributions in binary form must reproduce the above copyright
> > + * notice, this list of conditions and the following disclaimer in
> > + * the documentation and/or other materials provided with the
> > + * distribution.
> > + ** Neither the name of Broadcom Corporation nor the names of its
> > + * contributors may be used to endorse or promote products derived
> > + * from this software without specific prior written permission.
> > + *
> > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> > + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> > + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> > + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> > + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> > + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> > + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> > + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> > + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "bcm5301x.dtsi"
> > +
> > +/ {
> > + model = "NorthStar SVK (BCM94708)";
> > + compatible = "brcm,bcm4708";
>
> The compatible string should also contain this exactly board like this:
> compatible = "br
[RFC 1/5] clk: iproc: define Broadcom NSP iProc clock binding
Document the device tree bindings for Broadcom Northstar Plus architecture based clock controller Signed-off-by: Jon Mason --- .../bindings/clock/brcm,iproc-clocks.txt | 30 ++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index da8d9bb..b3c3e9d 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -130,3 +130,33 @@ These clock IDs are defined in: ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED + +Northstar and Northstar Plus +-- +PLL and leaf clock compatible strings for Northstar and Northstar Plus are: + "brcm,nsp-armpll" + "brcm,nsp-genpll" + "brcm,nsp-lcpll0" + +The following table defines the set of PLL/clock index and ID for Northstar and +Northstar Plus. These clock IDs are defined in: +"include/dt-bindings/clock/bcm-nsp.h" + +Clock Source Index ID +---- - - +crystalN/A N/A N/A + +armpll crystal N/A N/A + +genpll crystal 0 BCM_NSP_GENPLL +phygenpll 1 BCM_NSP_GENPLL_PHY_CLK +ethernetclkgenpll 2 BCM_NSP_GENPLL_ENET_SW_CLK +usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK +iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK +sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK +sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK + +lcpll0 crystal 0 BCM_NSP_LCPLL0 +pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK +sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK +ddr_phylcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 3/5] ARM: dts: enable clock support for BCM5301X
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar SoCs.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm5301x.dtsi | 88 -
1 file changed, 69 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 6f50f67..1eca551 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -8,6 +8,7 @@
* Licensed under the GNU/GPL. See COPYING for details.
*/
+#include
#include
#include
#include
@@ -42,41 +43,48 @@
mpcore {
compatible = "simple-bus";
- ranges = <0x 0x1902 0x3000>;
+ ranges = <0x 0x1900 0x00023000>;
#address-cells = <1>;
#size-cells = <1>;
- scu@ {
+ a9pll: arm_clk@0 {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x0 0x1000>;
+ };
+
+ scu@2 {
compatible = "arm,cortex-a9-scu";
- reg = <0x 0x100>;
+ reg = <0x2 0x100>;
};
- timer@0200 {
+ timer@20200 {
compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
+ reg = <0x20200 0x100>;
interrupts = ;
- clocks = <&clk_periph>;
+ clocks = <&periph_clk>;
};
- local-timer@0600 {
+ local-timer@20600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x0600 0x100>;
+ reg = <0x20600 0x100>;
interrupts = ;
- clocks = <&clk_periph>;
+ clocks = <&periph_clk>;
};
- gic: interrupt-controller@1000 {
+ gic: interrupt-controller@21000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
};
- L2: cache-controller@2000 {
+ L2: cache-controller@22000 {
compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
+ reg = <0x22000 0x1000>;
cache-unified;
arm,shared-override;
prefetch-data = <1>;
@@ -94,14 +102,37 @@
clocks {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ ranges;
- /* As long as we do not have a real clock driver us this
-* fixed clock */
- clk_periph: periph {
+ osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ periph_clk: periph_clk {
#clock-cells = <0>;
- clock-frequency = <4>;
+ compatible = "fixed-factor-clock";
+ clocks = <&a9pll>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
};
@@ -178,6 +209,25 @@
};
};
+ lcpll0: lcpll0@1800c100 {
+ #clock-cells =
[RFC 2/5] ARM: dts: enable clock support for Broadcom NSP
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar Plus SoC
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm-nsp.dtsi | 93 --
1 file changed, 72 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..768ee24 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -32,6 +32,7 @@
#include
#include
+#include
#include "skeleton.dtsi"
@@ -42,7 +43,7 @@
mpcore {
compatible = "simple-bus";
- ranges = <0x 0x1902 0x3000>;
+ ranges = <0x 0x1900 0x00023000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -58,27 +59,34 @@
};
};
- L2: l2-cache {
- compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
- cache-unified;
- cache-level = <2>;
+ a9pll: arm_clk@ {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x 0x1000>;
+ };
+
+ timer@20200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x20200 0x100>;
+ interrupts = ;
+ clocks = <&periph_clk>;
};
- gic: interrupt-controller@19021000 {
+ gic: interrupt-controller@21000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
};
- timer@19020200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
- interrupts = ;
- clocks = <&periph_clk>;
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0x22000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
};
};
@@ -87,33 +95,76 @@
#size-cells = <1>;
ranges;
- periph_clk: periph_clk {
+ osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
#clock-cells = <0>;
- clock-frequency = <5>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ periph_clk: periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&a9pll>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
};
axi {
compatible = "simple-bus";
- ranges = <0x 0x1800 0x1000>;
+ ranges = <0x 0x1800 0x0003f164>;
#address-cells = <1>;
#size-cells = <1>;
- uart0: serial@18000300 {
+ uart0: serial@00300 {
compatible = "ns16550a";
- reg = <0x0300 0x100>;
+ reg = <0x00300 0x100>;
interrupts = ;
clock-frequency = <62499840>;
status = "disabled";
};
- uart1:
[RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding
Document the device tree bindings for Broadcom Northstar 2 architecture based clock controller Signed-off-by: Jon Mason --- .../bindings/clock/brcm,iproc-clocks.txt | 48 ++ 1 file changed, 48 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index b3c3e9d..ede65a5 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -160,3 +160,51 @@ Northstar Plus. These clock IDs are defined in: pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK ddr_phylcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK + +Northstar 2 +--- +PLL and leaf clock compatible strings for Northstar 2 are: +"brcm,ns2-genpll-scr" +"brcm,ns2-genpll-sw" +"brcm,ns2-lcpll-ddr" +"brcm,ns2-lcpll-ports" + +The following table defines the set of PLL/clock index and ID for Northstar 2. +These clock IDs are defined in: +"include/dt-bindings/clock/bcm-ns2.h" + +Clock Source Index ID +---- - - +crystalN/A N/A N/A + +genpll_scr crystal 0 BCM_NS2_GENPLL_SCR +scrgenpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK +fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK +audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK +ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED +ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED +ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED + +genpll_sw crystal 0 BCM_NS2_GENPLL_SW +rpegenpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK +250genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK +nicgenpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK +chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK +port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK +sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK + +lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR +pcie_sata_usb lcpll_ddr1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK +ddrlcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK +ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED +ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED +ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED +ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED + +lcpll_portscrystal 0 BCM_NS2_LCPLL_PORTS +wanlcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK +rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK +ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED +ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED +ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED +ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/5] ARM: dts: add device tree support for NS, NSP, and NS2 clocks
This patch series adds device tree support for the Broadcom Northstar, Northstar Plus, and Northstar 2 clocks. This is being sent as a separate patch series due to the the clk maintainer(s) not wanting to pull in device tree changes into the clk repo. This series is an RFC due to a potential merge "race" between the device tree changes and the clk changes. If the device tree changes go in before the clk changes, there is a window where there are non-working clk entries in the device tree. So, these patches will be officially pushed once the clk changes are merged. Thanks, Jon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 5/5] ARM: dts: enable clock support for Broadcom NS2
Add device tree entries for clock support for Broadcom Northstar 2 SoC
Signed-off-by: Jon Mason
---
arch/arm64/boot/dts/broadcom/ns2.dtsi | 93 ---
1 file changed, 86 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 3c92d92..c632f3b 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -31,6 +31,7 @@
*/
#include
+#include
/memreserve/ 0x84b0 0x0008;
@@ -89,25 +90,103 @@
IRQ_TYPE_EDGE_RISING)>;
};
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x>;
+ ranges = <0 0 0x6500 0x01130100>;
+
+ lcpll_ddr: lcpll_ddr@001d058 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ddr";
+ reg = <0x001d058 0x20>,
+ <0x001c020 0x4>,
+ <0x001d04c 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ddr", "pcie_sata_usb",
+"ddr", "ddr_ch2_unused",
+"ddr_ch3_unused", "ddr_ch4_unused",
+"ddr_ch5_unused";
+ };
+
+ lcpll_ports: lcpll_ports@1d078 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ports";
+ reg = <0x001d078 0x20>,
+ <0x001c020 0x4>,
+ <0x001d054 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ports", "wan", "rgmii",
+"ports_ch2_unused",
+"ports_ch3_unused",
+"ports_ch4_unused",
+"ports_ch5_unused";
+ };
+
+ genpll_scr: genpll_scr@001d098 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-scr";
+ reg = <0x001d098 0x32>,
+ <0x001c020 0x4>,
+ <0x001d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_scr", "scr", "fs",
+"audio_ref", "scr_ch3_unused",
+"scr_ch4_unused", "scr_ch5_unused";
+ };
+
+ genpll_sw: genpll_sw@001d0c4 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-sw";
+ reg = <0x001d0c4 0x32>,
+ <0x001c020 0x4>,
+ <0x001d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_sw", "rpe", "250", "nic",
+"chimp", "port", "sdio";
+ };
- gic: interrupt-controller@6521 {
+ gic: interrupt-controller@021 {
compatible = "arm
Re: [PATCH v2 0/10] clk: iproc: add support for BCM NS, NSP, and NS2
Oops, this should be 0/7 not 0/10 On Tue, Oct 13, 2015 at 05:07:58PM -0400, Jon Mason wrote: > > v2 - Added a patch to change the Cygnus clk macros to uppercase, > removed the device tree changes from the series (will send out those as > an RFC), and other minor changes that Stephen Boyd requested. > > This patch series adds support for the Broadcom Northstar, Northstar > Plus, and Northstar 2 clocks. Some slight modifications were necessary > to clk-iproc-pll to get Northstar and Northstar Plus working, due to > differences in register layout. This is the reason why the first patch > is necessary. Some more modifications were necessary to clk-iproc-pll > to get Northstar 2 working, due to differences in register layout (and > resulting fallout in Cygnus and NSP). This is the reason why the sixth > and seventh patches are necessary. The fifth patch is clean-up to > prevent accidentally forgetting to adjust for the base write errata > (which happened a few times, but was caught in internal review). > > Thanks, > Jon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 4/7] clk: iproc: Add PLL base write function
All writes to the PLL base address must be flushed if the
IPROC_CLK_NEEDS_READ_BACK flag is set. If we add a function to make the
necessary write and reads, we can make sure that any future code which
makes PLL base writes will do the correct thing.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/clk-iproc-pll.c | 80 +
1 file changed, 33 insertions(+), 47 deletions(-)
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index e029ab3..74cdd66 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -137,6 +137,18 @@ static int pll_wait_for_lock(struct iproc_pll *pll)
return -EIO;
}
+static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base,
+ const u32 offset, u32 val)
+{
+ const struct iproc_pll_ctrl *ctrl = pll->ctrl;
+
+ writel(val, base + offset);
+
+ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK &&
+base == pll->pll_base))
+ val = readl(base + offset);
+}
+
static void __pll_disable(struct iproc_pll *pll)
{
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
@@ -145,27 +157,24 @@ static void __pll_disable(struct iproc_pll *pll)
if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
val = readl(pll->asiu_base + ctrl->asiu.offset);
val &= ~(1 << ctrl->asiu.en_shift);
- writel(val, pll->asiu_base + ctrl->asiu.offset);
+ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val);
}
if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
val = readl(pll->pll_base + ctrl->aon.offset);
val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- writel(val, pll->pll_base + ctrl->aon.offset);
-
- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
- readl(pll->pll_base + ctrl->aon.offset);
+ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val);
}
if (pll->pwr_base) {
/* latch input value so core power can be shut down */
val = readl(pll->pwr_base + ctrl->aon.offset);
val |= (1 << ctrl->aon.iso_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
+ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
/* power down the core */
val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
+ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
}
}
@@ -177,10 +186,7 @@ static int __pll_enable(struct iproc_pll *pll)
if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
val = readl(pll->pll_base + ctrl->aon.offset);
val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- writel(val, pll->pll_base + ctrl->aon.offset);
-
- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
- readl(pll->pll_base + ctrl->aon.offset);
+ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val);
}
if (pll->pwr_base) {
@@ -188,14 +194,14 @@ static int __pll_enable(struct iproc_pll *pll)
val = readl(pll->pwr_base + ctrl->aon.offset);
val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
val &= ~(1 << ctrl->aon.iso_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
+ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val);
}
/* certain PLLs also need to be ungated from the ASIU top level */
if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
val = readl(pll->asiu_base + ctrl->asiu.offset);
val |= (1 << ctrl->asiu.en_shift);
- writel(val, pll->asiu_base + ctrl->asiu.offset);
+ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val);
}
return 0;
@@ -209,9 +215,7 @@ static void __pll_put_in_reset(struct iproc_pll *pll)
val = readl(pll->pll_base + reset->offset);
val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift);
- writel(val, pll->pll_base + reset->offset);
- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
- readl(pll->pll_base + reset->offset);
+ iproc_pll_write(pll, pll->pll_base, reset->offset, val);
}
static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
@@ -228,9 +232,7 @@ s
[PATCH v2 5/7] clk: iproc: Split off dig_filter
The PLL loop filter/gain can be located in a separate register on some
SoCs. Split these off into a separate variable, so that an offset can
be added if necessary. Also, make the necessary modifications to the
Cygnus and NSP drivers for this change.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/clk-cygnus.c| 17 +++--
drivers/clk/bcm/clk-iproc-pll.c | 14 +-
drivers/clk/bcm/clk-iproc.h | 10 +-
drivers/clk/bcm/clk-nsp.c | 14 +-
4 files changed, 38 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
index aac82c6..3a228b6 100644
--- a/drivers/clk/bcm/clk-cygnus.c
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -34,9 +34,11 @@
{ .offset = o, .en_shift = es, .high_shift = hs, \
.high_width = hw, .low_shift = ls, .low_width = lw }
-#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
- .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
- .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
+#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
+ .p_reset_shift = prs }
+
+#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift =
kis,\
+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas,\
.ka_width = kaw }
#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
@@ -56,7 +58,8 @@ static const struct iproc_pll_ctrl genpll = {
.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
IPROC_CLK_PLL_NEEDS_SW_CFG,
.aon = AON_VAL(0x0, 2, 1, 0),
- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
+ .reset = RESET_VAL(0x0, 11, 10),
+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
.sw_ctrl = SW_CTRL_VAL(0x10, 31),
.ndiv_int = REG_VAL(0x10, 20, 10),
.ndiv_frac = REG_VAL(0x10, 0, 20),
@@ -114,7 +117,8 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll",
cygnus_genpll_clk_init);
static const struct iproc_pll_ctrl lcpll0 = {
.flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
.aon = AON_VAL(0x0, 2, 5, 4),
- .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
+ .reset = RESET_VAL(0x0, 31, 30),
+ .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4),
.sw_ctrl = SW_CTRL_VAL(0x4, 31),
.ndiv_int = REG_VAL(0x4, 16, 10),
.pdiv = REG_VAL(0x4, 26, 4),
@@ -191,7 +195,8 @@ static const struct iproc_pll_ctrl mipipll = {
IPROC_CLK_NEEDS_READ_BACK,
.aon = AON_VAL(0x0, 4, 17, 16),
.asiu = ASIU_GATE_VAL(0x0, 3),
- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
+ .reset = RESET_VAL(0x0, 11, 10),
+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4),
.ndiv_int = REG_VAL(0x10, 20, 10),
.ndiv_frac = REG_VAL(0x10, 0, 20),
.pdiv = REG_VAL(0x14, 0, 4),
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index 74cdd66..d4aab4e 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -224,13 +224,17 @@ static void __pll_bring_out_reset(struct iproc_pll *pll,
unsigned int kp,
u32 val;
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
+ const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter;
+
+ val = readl(pll->pll_base + dig_filter->offset);
+ val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift |
+ bit_mask(dig_filter->kp_width) << dig_filter->kp_shift |
+ bit_mask(dig_filter->ka_width) << dig_filter->ka_shift);
+ val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift |
+ ka << dig_filter->ka_shift;
+ iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val);
val = readl(pll->pll_base + reset->offset);
- val &= ~(bit_mask(reset->ki_width) << reset->ki_shift |
-bit_mask(reset->kp_width) << reset->kp_shift |
-bit_mask(reset->ka_width) << reset->ka_shift);
- val |= ki << reset->ki_shift | kp << reset->kp_shift |
- ka << reset->ka_shift;
val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift;
iproc_pll_write(pll, pll->pll_base, reset->offset, val);
}
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
index ff7bfad..b71c197 100644
--- a/drivers/clk/bcm/clk-iproc.h
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -94,12 +94,19 @@ struct iproc_pll_aon_pwr_ctrl {
};
/*
- * Control of the PLL reset, with Ki, Kp, and Ka parameters
+ * Control of the PLL reset
*/
struct iproc_pll_reset_ctrl {
unsigned int offset;
unsigned int
[PATCH v2 6/7] clk: iproc: Separate status and control variables
Some PLLs have separate registers for Status and Control. The means the
pll_base needs to be split into 2 new variables, so that those PLLs can
specify device tree registers for those independently. Also, add a new
driver flag to identify this presence of the split, and let the driver
know that additional registers need to be used.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/clk-iproc-pll.c | 96 -
drivers/clk/bcm/clk-iproc.h | 6 +++
2 files changed, 62 insertions(+), 40 deletions(-)
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index d4aab4e..f128a9d 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -74,7 +74,8 @@ struct iproc_clk {
};
struct iproc_pll {
- void __iomem *pll_base;
+ void __iomem *status_base;
+ void __iomem *control_base;
void __iomem *pwr_base;
void __iomem *asiu_base;
@@ -127,7 +128,7 @@ static int pll_wait_for_lock(struct iproc_pll *pll)
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
for (i = 0; i < LOCK_DELAY; i++) {
- u32 val = readl(pll->pll_base + ctrl->status.offset);
+ u32 val = readl(pll->status_base + ctrl->status.offset);
if (val & (1 << ctrl->status.shift))
return 0;
@@ -145,7 +146,7 @@ static void iproc_pll_write(const struct iproc_pll *pll,
void __iomem *base,
writel(val, base + offset);
if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK &&
-base == pll->pll_base))
+(base == pll->status_base || base == pll->control_base)))
val = readl(base + offset);
}
@@ -161,9 +162,9 @@ static void __pll_disable(struct iproc_pll *pll)
}
if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
- val = readl(pll->pll_base + ctrl->aon.offset);
+ val = readl(pll->control_base + ctrl->aon.offset);
val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val);
+ iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val);
}
if (pll->pwr_base) {
@@ -184,9 +185,9 @@ static int __pll_enable(struct iproc_pll *pll)
u32 val;
if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
- val = readl(pll->pll_base + ctrl->aon.offset);
+ val = readl(pll->control_base + ctrl->aon.offset);
val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val);
+ iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val);
}
if (pll->pwr_base) {
@@ -213,9 +214,9 @@ static void __pll_put_in_reset(struct iproc_pll *pll)
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
- val = readl(pll->pll_base + reset->offset);
+ val = readl(pll->control_base + reset->offset);
val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift);
- iproc_pll_write(pll, pll->pll_base, reset->offset, val);
+ iproc_pll_write(pll, pll->control_base, reset->offset, val);
}
static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
@@ -226,17 +227,17 @@ static void __pll_bring_out_reset(struct iproc_pll *pll,
unsigned int kp,
const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter;
- val = readl(pll->pll_base + dig_filter->offset);
+ val = readl(pll->control_base + dig_filter->offset);
val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift |
bit_mask(dig_filter->kp_width) << dig_filter->kp_shift |
bit_mask(dig_filter->ka_width) << dig_filter->ka_shift);
val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift |
ka << dig_filter->ka_shift;
- iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val);
+ iproc_pll_write(pll, pll->control_base, dig_filter->offset, val);
- val = readl(pll->pll_base + reset->offset);
+ val = readl(pll->control_base + reset->offset);
val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift;
- iproc_pll_write(pll, pll->pll_base, reset->offset, val);
+ iproc_pll_write(pll, pll->control_base, reset->offset, val);
}
static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_inde
[PATCH v2 0/10] clk: iproc: add support for BCM NS, NSP, and NS2
v2 - Added a patch to change the Cygnus clk macros to uppercase, removed the device tree changes from the series (will send out those as an RFC), and other minor changes that Stephen Boyd requested. This patch series adds support for the Broadcom Northstar, Northstar Plus, and Northstar 2 clocks. Some slight modifications were necessary to clk-iproc-pll to get Northstar and Northstar Plus working, due to differences in register layout. This is the reason why the first patch is necessary. Some more modifications were necessary to clk-iproc-pll to get Northstar 2 working, due to differences in register layout (and resulting fallout in Cygnus and NSP). This is the reason why the sixth and seventh patches are necessary. The fifth patch is clean-up to prevent accidentally forgetting to adjust for the base write errata (which happened a few times, but was caught in internal review). Thanks, Jon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 3/7] clk: nsp: add clock support for Broadcom Northstar Plus SoC
The Broadcom Northstar Plus SoC is architected under the iProc
architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all
derived from an onboard crystal.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/Makefile| 2 +
drivers/clk/bcm/clk-nsp.c | 135
include/dt-bindings/clock/bcm-nsp.h | 51 ++
3 files changed, 188 insertions(+)
create mode 100644 drivers/clk/bcm/clk-nsp.c
create mode 100644 include/dt-bindings/clock/bcm-nsp.h
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 8a7a477..e258b28 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -4,3 +4,5 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o
clk-iproc-asiu.o
obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
+obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o
+obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
diff --git a/drivers/clk/bcm/clk-nsp.c b/drivers/clk/bcm/clk-nsp.c
new file mode 100644
index 000..bc8ebdcd
--- /dev/null
+++ b/drivers/clk/bcm/clk-nsp.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include "clk-iproc.h"
+
+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
+
+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
+ .pwr_shift = ps, .iso_shift = is }
+
+#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
+ .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
+ .ka_width = kaw }
+
+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
+ .hold_shift = hs, .bypass_shift = bs }
+
+static void __init nsp_armpll_init(struct device_node *node)
+{
+ iproc_armpll_setup(node);
+}
+CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
+
+static const struct iproc_pll_ctrl genpll = {
+ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
+ .aon = AON_VAL(0x0, 1, 12, 0),
+ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
+ .ndiv_int = REG_VAL(0x14, 20, 10),
+ .ndiv_frac = REG_VAL(0x14, 0, 20),
+ .pdiv = REG_VAL(0x18, 24, 3),
+ .status = REG_VAL(0x20, 12, 1),
+};
+
+static const struct iproc_clk_ctrl genpll_clk[] = {
+ [BCM_NSP_GENPLL_PHY_CLK] = {
+ .channel = BCM_NSP_GENPLL_PHY_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 12, 6, 18),
+ .mdiv = REG_VAL(0x18, 16, 8),
+ },
+ [BCM_NSP_GENPLL_ENET_SW_CLK] = {
+ .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 13, 7, 19),
+ .mdiv = REG_VAL(0x18, 8, 8),
+ },
+ [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = {
+ .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 14, 8, 20),
+ .mdiv = REG_VAL(0x18, 0, 8),
+ },
+ [BCM_NSP_GENPLL_IPROCFAST_CLK] = {
+ .channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 15, 9, 21),
+ .mdiv = REG_VAL(0x1c, 16, 8),
+ },
+ [BCM_NSP_GENPLL_SATA1_CLK] = {
+ .channel = BCM_NSP_GENPLL_SATA1_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 16, 10, 22),
+ .mdiv = REG_VAL(0x1c, 8, 8),
+ },
+ [BCM_NSP_GENPLL_SATA2_CLK] = {
+ .channel = BCM_NSP_GENPLL_SATA2_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 17, 11, 23),
+ .mdiv = REG_VAL(0x1c, 0, 8),
+ },
+};
+
+static void __init nsp_genpll_clk_init(struct device_node *node)
+{
+ iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
+ ARRAY_SIZE(genpll_clk));
+}
+CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);
+
+static const struct iproc_pll_ctrl lcpll0 = {
+ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
+ .aon = AON_VAL(0x0, 1, 24, 0),
+ .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4),
+ .ndiv_i
[PATCH v2 7/7] clk: ns2: add clock support for Broadcom Northstar 2 SoC
The Broadcom Northstar 2 SoC is architected under the iProc
architecture. It has the following PLLs: GENPLL SCR, GENPLL SW,
LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
Signed-off-by: Jon Mason
---
drivers/clk/Makefile| 2 +-
drivers/clk/bcm/Makefile| 1 +
drivers/clk/bcm/clk-ns2.c | 288
include/dt-bindings/clock/bcm-ns2.h | 72 +
4 files changed, 362 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/bcm/clk-ns2.c
create mode 100644 include/dt-bindings/clock/bcm-ns2.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d08b3e5..6124bd3 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
-obj-$(CONFIG_ARCH_BCM) += bcm/
+obj-y += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_ARCH_MXC) += imx/
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index e258b28..2d1cbc5 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o
clk-iproc-asiu.o
+obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o
obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o
obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
diff --git a/drivers/clk/bcm/clk-ns2.c b/drivers/clk/bcm/clk-ns2.c
new file mode 100644
index 000..a564e92
--- /dev/null
+++ b/drivers/clk/bcm/clk-ns2.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include "clk-iproc.h"
+
+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
+
+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
+ .pwr_shift = ps, .iso_shift = is }
+
+#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
+ .p_reset_shift = prs }
+
+#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift =
kis,\
+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas,\
+ .ka_width = kaw }
+
+#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
+
+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
+ .hold_shift = hs, .bypass_shift = bs }
+
+static const struct iproc_pll_ctrl genpll_scr = {
+ .flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
+ .aon = AON_VAL(0x0, 1, 15, 12),
+ .reset = RESET_VAL(0x4, 2, 1),
+ .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
+ .ndiv_int = REG_VAL(0x8, 4, 10),
+ .pdiv = REG_VAL(0x8, 0, 4),
+ .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
+ .status = REG_VAL(0x0, 27, 1),
+};
+
+
+static const struct iproc_clk_ctrl genpll_scr_clk[] = {
+ /* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
+* in NS2. However, it doesn't appear to be used anywhere, so setting
+* it to 0.
+*/
+ [BCM_NS2_GENPLL_SCR_SCR_CLK] = {
+ .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 18, 12, 0),
+ .mdiv = REG_VAL(0x18, 0, 8),
+ },
+ [BCM_NS2_GENPLL_SCR_FS_CLK] = {
+ .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 19, 13, 0),
+ .mdiv = REG_VAL(0x18, 8, 8),
+ },
+ [BCM_NS2_GENPLL_SCR_AUDIO_CLK] = {
+ .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 20, 14, 0),
+ .mdiv = REG_VAL(0x14, 0, 8),
+ },
+ [BCM_NS2_GENPLL_SCR_CH3_UNUSED] = {
+ .channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 21, 15, 0),
+ .mdiv = REG_VAL(0x14, 8, 8),
+ },
+ [BCM_
[PATCH v2 1/7] clk: cygnus: Convert all macros to all caps
The macros that are being used to initialize the values of the clk
structures should be all caps. Find and replace all of them with their
relevant counterparts.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/clk-cygnus.c | 146 +--
1 file changed, 73 insertions(+), 73 deletions(-)
diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
index 316c603..aac82c6 100644
--- a/drivers/clk/bcm/clk-cygnus.c
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -23,28 +23,28 @@
#include
#include "clk-iproc.h"
-#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, }
+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
-#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
.pwr_shift = ps, .iso_shift = is }
-#define sw_ctrl_val(o, s) { .offset = o, .shift = s, }
+#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
-#define asiu_div_val(o, es, hs, hw, ls, lw) \
+#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \
{ .offset = o, .en_shift = es, .high_shift = hs, \
.high_width = hw, .low_shift = ls, .low_width = lw }
-#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
+#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
.reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
.ka_width = kaw }
-#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo }
+#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
-#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \
+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
.hold_shift = hs, .bypass_shift = bs }
-#define asiu_gate_val(o, es) { .offset = o, .en_shift = es }
+#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }
static void __init cygnus_armpll_init(struct device_node *node)
{
@@ -55,52 +55,52 @@ CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll",
cygnus_armpll_init);
static const struct iproc_pll_ctrl genpll = {
.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
IPROC_CLK_PLL_NEEDS_SW_CFG,
- .aon = aon_val(0x0, 2, 1, 0),
- .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
- .sw_ctrl = sw_ctrl_val(0x10, 31),
- .ndiv_int = reg_val(0x10, 20, 10),
- .ndiv_frac = reg_val(0x10, 0, 20),
- .pdiv = reg_val(0x14, 0, 4),
- .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
- .status = reg_val(0x28, 12, 1),
+ .aon = AON_VAL(0x0, 2, 1, 0),
+ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
+ .sw_ctrl = SW_CTRL_VAL(0x10, 31),
+ .ndiv_int = REG_VAL(0x10, 20, 10),
+ .ndiv_frac = REG_VAL(0x10, 0, 20),
+ .pdiv = REG_VAL(0x14, 0, 4),
+ .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
+ .status = REG_VAL(0x28, 12, 1),
};
static const struct iproc_clk_ctrl genpll_clk[] = {
[BCM_CYGNUS_GENPLL_AXI21_CLK] = {
.channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
.flags = IPROC_CLK_AON,
- .enable = enable_val(0x4, 6, 0, 12),
- .mdiv = reg_val(0x20, 0, 8),
+ .enable = ENABLE_VAL(0x4, 6, 0, 12),
+ .mdiv = REG_VAL(0x20, 0, 8),
},
[BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
.channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
.flags = IPROC_CLK_AON,
- .enable = enable_val(0x4, 7, 1, 13),
- .mdiv = reg_val(0x20, 10, 8),
+ .enable = ENABLE_VAL(0x4, 7, 1, 13),
+ .mdiv = REG_VAL(0x20, 10, 8),
},
[BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
.channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
.flags = IPROC_CLK_AON,
- .enable = enable_val(0x4, 8, 2, 14),
- .mdiv = reg_val(0x20, 20, 8),
+ .enable = ENABLE_VAL(0x4, 8, 2, 14),
+ .mdiv = REG_VAL(0x20, 20, 8),
},
[BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
.channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
.flags = IPROC_CLK_AON,
- .enable = enable_val(0x4, 9, 3, 15),
- .mdiv = reg_val(0x24, 0, 8),
+ .enable = ENABLE_VAL(0x4, 9, 3, 15),
+ .mdiv = REG_VAL(0x24, 0, 8),
},
[BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
.channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
.flags = IPROC_CLK_AON,
- .enable = enable_val(0x4, 10, 4, 16),
- .mdiv = reg_val(0x24, 10, 8),
+ .enable = ENABLE_VAL(0x4, 10, 4, 16),
+ .mdiv = REG_VAL(0x24, 10, 8),
},
[BCM_CYGNUS_GENPLL_CAN_CLK] = {
.channel = BCM_CYGNUS_GENPLL_CAN_CLK,
.flags = IPROC_CLK_AON,
- .ena
[PATCH v2 2/7] clk: iproc: Add PWRCTRL support
Some iProc SoC clocks use a different way to control clock power, via
the PWRDWN bit in the PLL control register. Since the PLL control
register is used to access the PWRDWN bit, there is no need for the
pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL,
has been added to identify this usage. We can use the AON interface to
write the values to enable/disable PWRDOWN.
Signed-off-by: Jon Mason
---
drivers/clk/bcm/clk-iproc-pll.c | 55 -
drivers/clk/bcm/clk-iproc.h | 6 +
2 files changed, 44 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index 2dda4e8..e029ab3 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -148,14 +148,25 @@ static void __pll_disable(struct iproc_pll *pll)
writel(val, pll->asiu_base + ctrl->asiu.offset);
}
- /* latch input value so core power can be shut down */
- val = readl(pll->pwr_base + ctrl->aon.offset);
- val |= (1 << ctrl->aon.iso_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
-
- /* power down the core */
- val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
+ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
+ val = readl(pll->pll_base + ctrl->aon.offset);
+ val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
+ writel(val, pll->pll_base + ctrl->aon.offset);
+
+ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
+ readl(pll->pll_base + ctrl->aon.offset);
+ }
+
+ if (pll->pwr_base) {
+ /* latch input value so core power can be shut down */
+ val = readl(pll->pwr_base + ctrl->aon.offset);
+ val |= (1 << ctrl->aon.iso_shift);
+ writel(val, pll->pwr_base + ctrl->aon.offset);
+
+ /* power down the core */
+ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
+ writel(val, pll->pwr_base + ctrl->aon.offset);
+ }
}
static int __pll_enable(struct iproc_pll *pll)
@@ -163,11 +174,22 @@ static int __pll_enable(struct iproc_pll *pll)
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
u32 val;
- /* power up the PLL and make sure it's not latched */
- val = readl(pll->pwr_base + ctrl->aon.offset);
- val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
- val &= ~(1 << ctrl->aon.iso_shift);
- writel(val, pll->pwr_base + ctrl->aon.offset);
+ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
+ val = readl(pll->pll_base + ctrl->aon.offset);
+ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
+ writel(val, pll->pll_base + ctrl->aon.offset);
+
+ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
+ readl(pll->pll_base + ctrl->aon.offset);
+ }
+
+ if (pll->pwr_base) {
+ /* power up the PLL and make sure it's not latched */
+ val = readl(pll->pwr_base + ctrl->aon.offset);
+ val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
+ val &= ~(1 << ctrl->aon.iso_shift);
+ writel(val, pll->pwr_base + ctrl->aon.offset);
+ }
/* certain PLLs also need to be ungated from the ASIU top level */
if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
@@ -610,9 +632,8 @@ void __init iproc_pll_clk_setup(struct device_node *node,
if (WARN_ON(!pll->pll_base))
goto err_pll_iomap;
+ /* Some SoCs do not require the pwr_base, thus failing is not fatal */
pll->pwr_base = of_iomap(node, 1);
- if (WARN_ON(!pll->pwr_base))
- goto err_pwr_iomap;
/* some PLLs require gating control at the top ASIU level */
if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) {
@@ -695,9 +716,9 @@ err_pll_register:
iounmap(pll->asiu_base);
err_asiu_iomap:
- iounmap(pll->pwr_base);
+ if (pll->pwr_base)
+ iounmap(pll->pwr_base);
-err_pwr_iomap:
iounmap(pll->pll_base);
err_pll_iomap:
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
index d834b7a..ff7bfad 100644
--- a/drivers/clk/bcm/clk-iproc.h
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -49,6 +49,12 @@
#define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
/*
+ * Some PLLs use a different way to control clock power, via the PWRDWN bit in
+ * the PLL control register
+ */
+#define IPROC_CLK_EMBED_PWRCTRL BIT(5)
+
+/*
* Parameters for VCO frequency configuration
*
* VCO frequency =
--
1.9.1
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Re: [PATCH 09/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
On Fri, Oct 09, 2015 at 05:33:52PM -0700, Stephen Boyd wrote: > On 10/02, Jon Mason wrote: > > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms > > index 23800a1..2790f21 100644 > > --- a/arch/arm64/Kconfig.platforms > > +++ b/arch/arm64/Kconfig.platforms > > @@ -2,6 +2,7 @@ menu "Platform selection" > > > > config ARCH_BCM_IPROC > > bool "Broadcom iProc SoC Family" > > + select COMMON_CLK_IPROC > > Given that this is a visible option, I'd expect the defconfig to > enable this. After looking at this again, it is completely unnecessary. Removed. > > > help > > This enables support for Broadcom iProc based SoCs > > > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > > index d08b3e5..ea81eaa 100644 > > --- a/drivers/clk/Makefile > > +++ b/drivers/clk/Makefile > > @@ -47,7 +47,8 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o > > obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o > > obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o > > obj-$(CONFIG_COMMON_CLK_AT91) += at91/ > > -obj-$(CONFIG_ARCH_BCM) += bcm/ > > +obj-$(CONFIG_CLK_BCM_KONA) += bcm/ > > +obj-$(CONFIG_COMMON_CLK_IPROC) += bcm/ > > Also, perhaps we need some sort of Kconfig thing for overall bcm > clock drivers, so that we don't have duplicate Makefile rules. > > config COMMON_CLK_BCM > bool "Support for Broadcom clocks" Will do. Thanks, Jon > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 04/10] ARM: dts: enable clock support for BCM5301X
On Fri, Oct 09, 2015 at 05:14:08PM -0700, Stephen Boyd wrote:
> On 10/09, Jon Mason wrote:
> > On Fri, Oct 09, 2015 at 12:35:40AM -0700, Stephen Boyd wrote:
> > > On 10/02, Jon Mason wrote:
> > >
> > > > arch/arm/boot/dts/bcm5301x.dtsi | 67
> > > > -
> > > > 1 file changed, 60 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/arch/arm/boot/dts/bcm5301x.dtsi
> > > > b/arch/arm/boot/dts/bcm5301x.dtsi
> > > > index 6f50f67..f717859 100644
> > > > --- a/arch/arm/boot/dts/bcm5301x.dtsi
> > > > +++ b/arch/arm/boot/dts/bcm5301x.dtsi
> > > > @@ -55,14 +56,14 @@
> > > > compatible = "arm,cortex-a9-global-timer";
> > > > reg = <0x0200 0x100>;
> > > > interrupts = ;
> > > > - clocks = <&clk_periph>;
> > > > + clocks = <&periph_clk>;
> > > > };
> > > >
> > > > local-timer@0600 {
> > > > compatible = "arm,cortex-a9-twd-timer";
> > > > reg = <0x0600 0x100>;
> > > > interrupts = ;
> > > > - clocks = <&clk_periph>;
> > > > + clocks = <&periph_clk>;
> > > > };
> > > >
> > > > gic: interrupt-controller@1000 {
> > > > @@ -94,14 +95,66 @@
> > > >
> > > > clocks {
> > >
> > > I'd expect this to only contain nodes that don't have a reg
> > > property. Clock providers that have a reg property would go into
> > > some soc node or bus. Perhaps that's the chipcommonA node, or
> > > axi?
> >
> > This might get a little ugly, as some of the clocks are in the
> > 0x1800 and others are in 0x1900. I would think it better to
> > have them all in one place (as that is more readable). Do you preferr
> > I split the pieces up into their respective DT nodes?
>
> Are there two clock controllers? Sorry I don't understand the
> architecture here very well. Nodes with reg properties in the
> same range should be near each other. We don't group all i2c
> controllers into the same node because they're logically i2c
> controllers. We express the hierarchy of devices with container
> nodes. The clocks node is only useful for board-level clocks, not
> things that are inside the SoC.
3 clock sources: a9pll, lcpll, and genpll. The first one resides in
the IP block living at the 0x1900 address range, while the latter
two live in the 0x1800 address range.
I'll split up the clocks amongst the respective entries, per your
suggestion.
Thanks,
Jon
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
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Re: [PATCH 09/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
On Fri, Oct 09, 2015 at 05:19:15PM -0700, Stephen Boyd wrote:
> On 10/02, Jon Mason wrote:
> > diff --git a/drivers/clk/bcm/clk-ns2.c b/drivers/clk/bcm/clk-ns2.c
> > new file mode 100644
> > index 000..1d08281
> > --- /dev/null
> > +++ b/drivers/clk/bcm/clk-ns2.c
> > @@ -0,0 +1,290 @@
> > +/*
> > + * Copyright (C) 2015 Broadcom Corporation
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation version 2.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
>
> clkdev looks unused here too?
>
> > +#include
> > +#include
>
> And this one?
Yes, already caught this when you mentioned the other file :)
>
> > +
> > +#include
> > +#include "clk-iproc.h"
> > +
> > +#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, }
>
> I guess we missed this one already, but this isn't a macro
> resembling a function. Kernel style is to capitalize this sort of
> macro.
I agree, but I was following prior example in
drivers/clk/bcm/clk-cygnus.c. I can make the changes here and do a
patch for that file making the necessary changes as well. Just let me
know your preference.
Thanks,
Jon
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
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