[PATCH v3 6/9] ARM: dts: Add pinctrl node to STM32F429

[Maxime Coquelin]

The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32f429.dtsi | 97 
 1 file changed, 97 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 5e1e234..62d2b3d 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -46,6 +46,7 @@
  */
 
 #include "armv7-m.dtsi"
+#include 
 
 / {
clocks {
@@ -168,6 +169,102 @@
status = "disabled";
};
 
+   pin-controller {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,stm32f429-pinctrl";
+   ranges = <0 0x4002 0x3000>;
+   pins-are-numbered;
+
+   gpioa: gpio@4002 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x0 0x400>;
+   clocks = < 0 256>;
+   st,bank-name = "GPIOA";
+   };
+
+   gpiob: gpio@40020400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x400 0x400>;
+   clocks = < 0 257>;
+   st,bank-name = "GPIOB";
+   };
+
+   gpioc: gpio@40020800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x800 0x400>;
+   clocks = < 0 258>;
+   st,bank-name = "GPIOC";
+   };
+
+   gpiod: gpio@40020c00 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0xc00 0x400>;
+   clocks = < 0 259>;
+   st,bank-name = "GPIOD";
+   };
+
+   gpioe: gpio@40021000 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1000 0x400>;
+   clocks = < 0 260>;
+   st,bank-name = "GPIOE";
+   };
+
+   gpiof: gpio@40021400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1400 0x400>;
+   clocks = < 0 261>;
+   st,bank-name = "GPIOF";
+   };
+
+   gpiog: gpio@40021800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1800 0x400>;
+   clocks = < 0 262>;
+   st,bank-name = "GPIOG";
+   };
+
+   gpioh: gpio@40021c00 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1c00 0x400>;
+   clocks = < 0 263>;
+   st,bank-name = "GPIOH";
+   };
+
+   gpioi: gpio@40022000 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2000 0x400>;
+   clocks = < 0 264>;
+   st,bank-name = "GPIOI";
+   };
+
+   gpioj: gpio@40022400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2400 0x400>;
+   clocks = < 0 265>;
+   st,bank-name = "GPIOJ";
+   };
+
+   gpiok: gpio@40022800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2800 0x400>;
+   clocks = < 0 266>;
+   st,bank-name = "GPIOK";
+   };
+   };
+
rcc: rcc@40023810 {
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
-- 
1.9.1

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[PATCH v3 7/9] ARM: dts: Add USART1 pin config to STM32F429 boards

[Maxime Coquelin]

This patch selects USART1 pin configuration on PA9/PA10 pins
for both Eval and Disco boards.

Acked-by: Linus Walleij <linus.wall...@linaro.org>
Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32429i-eval.dts  |  2 ++
 arch/arm/boot/dts/stm32f429-disco.dts |  2 ++
 arch/arm/boot/dts/stm32f429.dtsi  | 13 +
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts 
b/arch/arm/boot/dts/stm32429i-eval.dts
index 6964fc9..71fe17a 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -71,5 +71,7 @@
 };
 
  {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
status = "okay";
 };
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts 
b/arch/arm/boot/dts/stm32f429-disco.dts
index f0b731d..e3ce796 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -71,5 +71,7 @@
 };
 
  {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
status = "okay";
 };
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 62d2b3d..1cf713e 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -263,6 +263,19 @@
clocks = < 0 266>;
st,bank-name = "GPIOK";
};
+
+   usart1_pins_a: usart1@0 {
+   pins1 {
+   pinmux = ;
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins2 {
+   pinmux = 
;
+   bias-disable;
+   };
+   };
};
 
rcc: rcc@40023810 {
-- 
1.9.1

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Re: [PATCH v2 4/9] pinctrl: Add support STM32 MCUs

[Maxime Coquelin]

2015-12-11 9:20 GMT+01:00 Patrice Chotard :
> Hi Linus
>
> I will try to review it before end of next week

Thanks Patrice, I resent the series.

Regards,
Maxime
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[PATCH v3 4/9] pinctrl: Add STM32 MCUs support

[Maxime Coquelin]

This patch adds pinctrl and GPIO support to STMicroelectronic's STM32
family of MCUs.

While it only supports STM32F429 for now, it has been designed to enable
support of other MCUs of the family (e.g. STM32F746).

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 drivers/pinctrl/Kconfig   |1 +
 drivers/pinctrl/Makefile  |1 +
 drivers/pinctrl/stm32/Kconfig |   16 +
 drivers/pinctrl/stm32/Makefile|5 +
 drivers/pinctrl/stm32/pinctrl-stm32.c |  856 +++
 drivers/pinctrl/stm32/pinctrl-stm32.h |   43 +
 drivers/pinctrl/stm32/pinctrl-stm32f429.c | 1598 +
 7 files changed, 2520 insertions(+)
 create mode 100644 drivers/pinctrl/stm32/Kconfig
 create mode 100644 drivers/pinctrl/stm32/Makefile
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b422e4e..9cdb7df 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -258,6 +258,7 @@ source "drivers/pinctrl/qcom/Kconfig"
 source "drivers/pinctrl/samsung/Kconfig"
 source "drivers/pinctrl/sh-pfc/Kconfig"
 source "drivers/pinctrl/spear/Kconfig"
+source "drivers/pinctrl/stm32/Kconfig"
 source "drivers/pinctrl/sunxi/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
 source "drivers/pinctrl/vt8500/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 738cb49..640079c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_ARCH_QCOM)   += qcom/
 obj-$(CONFIG_PINCTRL_SAMSUNG)  += samsung/
 obj-$(CONFIG_PINCTRL_SH_PFC)   += sh-pfc/
 obj-$(CONFIG_PLAT_SPEAR)   += spear/
+obj-$(CONFIG_ARCH_STM32)   += stm32/
 obj-$(CONFIG_ARCH_SUNXI)   += sunxi/
 obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
 obj-$(CONFIG_ARCH_VT8500)  += vt8500/
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
new file mode 100644
index 000..0f28841
--- /dev/null
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -0,0 +1,16 @@
+if ARCH_STM32 || COMPILE_TEST
+
+config PINCTRL_STM32
+   bool
+   depends on OF
+   select PINMUX
+   select GENERIC_PINCONF
+   select GPIOLIB
+
+config PINCTRL_STM32F429
+   bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && 
!MACH_STM32F429
+   depends on OF
+   default MACH_STM32F429
+   select PINCTRL_STM32
+
+endif
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
new file mode 100644
index 000..fc17d42
--- /dev/null
+++ b/drivers/pinctrl/stm32/Makefile
@@ -0,0 +1,5 @@
+# Core
+obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_STM32F429)+= pinctrl-stm32f429.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c 
b/drivers/pinctrl/stm32/pinctrl-stm32.c
new file mode 100644
index 000..4ebceaa
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -0,0 +1,856 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.st...@gmail.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ *
+ * Heavily based on Mediatek's pinctrl driver
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-stm32.h"
+
+#define STM32_GPIO_MODER   0x00
+#define STM32_GPIO_TYPER   0x04
+#define STM32_GPIO_SPEEDR  0x08
+#define STM32_GPIO_PUPDR   0x0c
+#define STM32_GPIO_IDR 0x10
+#define STM32_GPIO_ODR 0x14
+#define STM32_GPIO_BSRR0x18
+#define STM32_GPIO_LCKR0x1c
+#define STM32_GPIO_AFRL0x20
+#define STM32_GPIO_AFRH0x24
+
+#define STM32_GPIO_PINS_PER_BANK 16
+
+#define gpio_range_to_bank(chip) \
+   container_of(chip, struct stm32_gpio_bank, range)
+
+#define gpio_chip_to_bank(chip) \
+   container_of(chip, struct stm32_gpio_bank, gpio_chip)
+
+static const char * const stm32_gpio_functions[] = {
+   "gpio", "af0", "af1",
+   "af2", "af3", "af4",
+   "af5", "af6", "af7",
+   "af8", "af9", "af10",
+   "af11", "af12", "af13",
+   "af14", "af15", "analog",
+};
+
+struct stm32_pinctrl_group {
+   const char *name;
+   unsigned long config;
+   unsigned pin;
+};
+

[PATCH RESEND v3 0/9] Add STM32 pinctrl/GPIO driver

[Maxime Coquelin]

Hi Linus, Patrice,

I resend the series for Patrice to review it.

Thanks,
Maxime



This is the third round of STM32 pinctrl series, which improves DT
bindings declaration and documentation, and also fixes some commit fixup
issues. The series also contains two more patches, adding GPIO LEDs
support as a user of this driver.

The STM32 family has 16 pins per GPIO bank, and the number of bank varies
depending on the model.

Pins can be multiplexed either in GPIO mode, alternate function (up to 15
functions per pin) or analog (for ADC/DAC).

Changes since v2:
-
 - Rebase on v4.4-rc1
 - Declare leds also for Eval board
 - Set green led as heartbeat
 - Collect some acks

Changes since v1:
-
 - Add GPIO LEDs support in DT and defconfig
 - Changes pinmux DT bindings from macros to raw values (Daniel)
 - Improve DT bindings documentation (Daniel)
 - Fix some commit fixup and rebase issues.

Kind regards,
Maxime

Maxime Coquelin (9):
  ARM: Kconfig: Introduce MACH_STM32F429 flag
  Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings
  includes: dt-bindings: Add STM32F429 pinctrl DT bindings
  pinctrl: Add STM32 MCUs support
  ARM: mach-stm32: Select pinctrl
  ARM: dts: Add pinctrl node to STM32F429
  ARM: dts: Add USART1 pin config to STM32F429 boards
  ARM: dts: Add leds support to STM32F429 boards
  ARM: config: Enable GPIO Led driver in stm32_defconfig

 .../bindings/pinctrl/st,stm32-pinctrl.txt  |  126 ++
 arch/arm/Kconfig   |6 +
 arch/arm/boot/dts/stm32429i-eval.dts   |   19 +
 arch/arm/boot/dts/stm32f429-disco.dts  |   13 +
 arch/arm/boot/dts/stm32f429.dtsi   |  110 ++
 arch/arm/configs/stm32_defconfig   |1 +
 drivers/pinctrl/Kconfig|1 +
 drivers/pinctrl/Makefile   |1 +
 drivers/pinctrl/stm32/Kconfig  |   16 +
 drivers/pinctrl/stm32/Makefile |5 +
 drivers/pinctrl/stm32/pinctrl-stm32.c  |  856 +++
 drivers/pinctrl/stm32/pinctrl-stm32.h  |   43 +
 drivers/pinctrl/stm32/pinctrl-stm32f429.c  | 1598 
 include/dt-bindings/pinctrl/pinctrl-stm32.h|   12 +
 include/dt-bindings/pinctrl/stm32f429-pinfunc.h| 1241 +++
 15 files changed, 4048 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
 create mode 100644 drivers/pinctrl/stm32/Kconfig
 create mode 100644 drivers/pinctrl/stm32/Makefile
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h
 create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h

-- 
1.9.1

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[PATCH v3 9/9] ARM: config: Enable GPIO Led driver in stm32_defconfig

[Maxime Coquelin]

Acked-by: Linus Walleij <linus.wall...@linaro.org>
Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/configs/stm32_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 4725fab..92ade2e 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -52,6 +52,7 @@ CONFIG_SERIAL_STM32_CONSOLE=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 # CONFIG_FILE_LOCKING is not set
-- 
1.9.1

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[PATCH v3 8/9] ARM: dts: Add leds support to STM32F429 boards

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32429i-eval.dts  | 17 +
 arch/arm/boot/dts/stm32f429-disco.dts | 11 +++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts 
b/arch/arm/boot/dts/stm32429i-eval.dts
index 71fe17a..e3921d9 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -64,6 +64,23 @@
aliases {
serial0 = 
};
+
+   leds {
+   compatible = "gpio-leds";
+   green {
+   gpios = < 6 1>;
+   linux,default-trigger = "heartbeat";
+   };
+   orange {
+   gpios = < 7 1>;
+   };
+   red {
+   gpios = < 10 1>;
+   };
+   blue {
+   gpios = < 12 1>;
+   };
+   };
 };
 
 _hse {
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts 
b/arch/arm/boot/dts/stm32f429-disco.dts
index e3ce796..0140807 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -64,6 +64,17 @@
aliases {
serial0 = 
};
+
+   leds {
+   compatible = "gpio-leds";
+   red {
+   gpios = < 14 0>;
+   };
+   green {
+   gpios = < 13 0>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
 };
 
 _hse {
-- 
1.9.1

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[PATCH v3 5/9] ARM: mach-stm32: Select pinctrl

[Maxime Coquelin]

Acked-by: Linus Walleij <linus.wall...@linaro.org>
Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4d2fcba..365714b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -963,6 +963,7 @@ config ARCH_STM32
select ARCH_HAS_RESET_CONTROLLER
select ARMV7M_SYSTICK
select CLKSRC_STM32
+   select PINCTRL
select RESET_CONTROLLER
help
  Support for STMicroelectronics STM32 processors.
-- 
1.9.1

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[PATCH v3 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 .../bindings/pinctrl/st,stm32-pinctrl.txt  | 126 +
 1 file changed, 126 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
new file mode 100644
index 000..7b4800c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -0,0 +1,126 @@
+* STM32 GPIO and Pin Mux/Config controller
+
+STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
+controller. It controls the input/output settings on the available pins and
+also provides ability to multiplex and configure the output of various on-chip
+controllers onto these pads.
+
+Pin controller node:
+Required properies:
+ - compatible: value should be one of the following:
+   (a) "st,stm32f429-pinctrl"
+ - #address-cells: The value of this property must be 1
+ - #size-cells : The value of this property must be 1
+ - ranges  : defines mapping between pin controller node (parent) to
+   gpio-bank node (children).
+ - pins-are-numbered: Specify the subnodes are using numbered pinmux to
+   specify pins.
+
+GPIO controller/bank node:
+Required properties:
+ - gpio-controller : Indicates this device is a GPIO controller
+ - #gpio-cells   : Should be two.
+   The first cell is the pin number
+   The second one is the polarity:
+   - 0 for active high
+   - 1 for active low
+ - reg   : The gpio address range, relative to the pinctrl range
+ - clocks: clock that drives this bank
+ - st,bank-name  : Should be a name string for this bank as specified 
in
+   the datasheet
+
+Optional properties:
+ - reset:: Reference to the reset controller
+
+Example:
+#include 
+...
+
+   pin-controller {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,stm32f429-pinctrl";
+   ranges = <0 0x4002 0x3000>;
+   pins-are-numbered;
+
+   gpioa: gpio@4002 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x0 0x400>;
+   resets = <_ahb1 0>;
+   st,bank-name = "GPIOA";
+   };
+   ...
+   pin-functions nodes follow...
+   };
+
+Contents of function subnode node:
+--
+Subnode format
+A pinctrl node should contain at least one subnode representing the
+pinctrl group available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, pullups, drive, output high/low and output speed.
+
+node {
+   pinmux = ;
+   GENERIC_PINCONFIG;
+};
+
+Required properties:
+- pinmux: integer array, represents gpio pin number and mux setting.
+  Supported pin number and mux varies for different SoCs, and are defined in
+  dt-bindings/pinctrl/-pinfunc.h directly.
+  These defines are calculated as:
+((port * 16 + line) << 8) | function
+  With:
+- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
+- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
+- function: The function number, can be:
+  * 0 : GPIO
+  * 1 : Alternate Function 0
+  * 2 : Alternate Function 1
+  * 3 : Alternate Function 2
+  * ...
+  * 16 : Alternate Function 15
+  * 17 : Analog
+
+Optional properties:
+- GENERIC_PINCONFIG: is the generic pinconfig options to use.
+  Available options are:
+   - bias-disable,
+   - bias-pull-down,
+   - bias-pull-up,
+   - drive-push-pull,
+   - drive-open-drain,
+   - output-low
+   - output-high
+   - slew-rate = , with x being:
+   < 0 > : Low speed
+   < 1 > : Medium speed
+   < 2 > : Fast speed
+   < 3 > : High speed
+
+Example:
+
+pin-controller {
+...
+   usart1_pins_a: usart1@0 {
+   pins1 {
+   pinmux = ;
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins2 {
+   pinmux = ;
+   bias-disable;
+   };
+   };
+};
+
+ {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
+   status = "okay";
+};
-- 
1.9.1

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[PATCH v3 3/9] includes: dt-bindings: Add STM32F429 pinctrl DT bindings

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 include/dt-bindings/pinctrl/pinctrl-stm32.h |   12 +
 include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1241 +++
 2 files changed, 1253 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h
 create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h

diff --git a/include/dt-bindings/pinctrl/pinctrl-stm32.h 
b/include/dt-bindings/pinctrl/pinctrl-stm32.h
new file mode 100644
index 000..a2e7222
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-stm32.h
@@ -0,0 +1,12 @@
+#ifndef _DT_BINDINGS_PINCTRL_STM32_H
+#define _DT_BINDINGS_PINCTRL_STM32_H
+
+#define STM32_PIN_NO(x) ((x) << 8)
+#define STM32_GET_PIN_NO(x) ((x) >> 8)
+#define STM32_GET_PIN_FUNC(x) ((x) & 0xff)
+
+#define STM32_PIN_GPIO 0
+#define STM32_PIN_AF(x)((x) + 1)
+#define STM32_PIN_ANALOG   (STM32_PIN_AF(15) + 1)
+
+#endif /* _DT_BINDINGS_PINCTRL_STM32_H */
diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h 
b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
new file mode 100644
index 000..9dd5fd0
--- /dev/null
+++ b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
@@ -0,0 +1,1241 @@
+#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H
+#define _DT_BINDINGS_STM32F429_PINFUNC_H
+
+#include 
+
+#define STM32F429_PA0_FUNC_GPIO 0x0
+#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
+#define STM32F429_PA0_FUNC_TIM5_CH1 0x3
+#define STM32F429_PA0_FUNC_TIM8_ETR 0x4
+#define STM32F429_PA0_FUNC_USART2_CTS 0x8
+#define STM32F429_PA0_FUNC_UART4_TX 0x9
+#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc
+#define STM32F429_PA0_FUNC_EVENTOUT 0x10
+#define STM32F429_PA0_FUNC_ANALOG 0x11
+
+#define STM32F429_PA1_FUNC_GPIO 0x100
+#define STM32F429_PA1_FUNC_TIM2_CH2 0x102
+#define STM32F429_PA1_FUNC_TIM5_CH2 0x103
+#define STM32F429_PA1_FUNC_USART2_RTS 0x108
+#define STM32F429_PA1_FUNC_UART4_RX 0x109
+#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c
+#define STM32F429_PA1_FUNC_EVENTOUT 0x110
+#define STM32F429_PA1_FUNC_ANALOG 0x111
+
+#define STM32F429_PA2_FUNC_GPIO 0x200
+#define STM32F429_PA2_FUNC_TIM2_CH3 0x202
+#define STM32F429_PA2_FUNC_TIM5_CH3 0x203
+#define STM32F429_PA2_FUNC_TIM9_CH1 0x204
+#define STM32F429_PA2_FUNC_USART2_TX 0x208
+#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c
+#define STM32F429_PA2_FUNC_EVENTOUT 0x210
+#define STM32F429_PA2_FUNC_ANALOG 0x211
+
+#define STM32F429_PA3_FUNC_GPIO 0x300
+#define STM32F429_PA3_FUNC_TIM2_CH4 0x302
+#define STM32F429_PA3_FUNC_TIM5_CH4 0x303
+#define STM32F429_PA3_FUNC_TIM9_CH2 0x304
+#define STM32F429_PA3_FUNC_USART2_RX 0x308
+#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b
+#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c
+#define STM32F429_PA3_FUNC_LCD_B5 0x30f
+#define STM32F429_PA3_FUNC_EVENTOUT 0x310
+#define STM32F429_PA3_FUNC_ANALOG 0x311
+
+#define STM32F429_PA4_FUNC_GPIO 0x400
+#define STM32F429_PA4_FUNC_SPI1_NSS 0x406
+#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407
+#define STM32F429_PA4_FUNC_USART2_CK 0x408
+#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d
+#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e
+#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f
+#define STM32F429_PA4_FUNC_EVENTOUT 0x410
+#define STM32F429_PA4_FUNC_ANALOG 0x411
+
+#define STM32F429_PA5_FUNC_GPIO 0x500
+#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502
+#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504
+#define STM32F429_PA5_FUNC_SPI1_SCK 0x506
+#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b
+#define STM32F429_PA5_FUNC_EVENTOUT 0x510
+#define STM32F429_PA5_FUNC_ANALOG 0x511
+
+#define STM32F429_PA6_FUNC_GPIO 0x600
+#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602
+#define STM32F429_PA6_FUNC_TIM3_CH1 0x603
+#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604
+#define STM32F429_PA6_FUNC_SPI1_MISO 0x606
+#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a
+#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e
+#define STM32F429_PA6_FUNC_LCD_G2 0x60f
+#define STM32F429_PA6_FUNC_EVENTOUT 0x610
+#define STM32F429_PA6_FUNC_ANALOG 0x611
+
+#define STM32F429_PA7_FUNC_GPIO 0x700
+#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702
+#define STM32F429_PA7_FUNC_TIM3_CH2 0x703
+#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704
+#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706
+#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a
+#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c
+#define STM32F429_PA7_FUNC_EVENTOUT 0x710
+#define STM32F429_PA7_FUNC_ANALOG 0x711
+
+#define STM32F429_PA8_FUNC_GPIO 0x800
+#define STM32F429_PA8_FUNC_MCO1 0x801
+#define STM32F429_PA8_FUNC_TIM1_CH1 0x802
+#define STM32F429_PA8_FUNC_I2C3_SCL 0x805
+#define STM32F429_PA8_FUNC_USART1_CK 0x808
+#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b
+#define STM32F429_PA8_FUNC_LCD_R6 0x80f
+#define STM32F429_PA8_FUNC_EVENTOUT 0x810
+#define STM32F429_PA8_FUNC_ANALOG 0x811
+
+#define STM32F429_PA9_FUNC_GPIO 0x900
+#define STM32F429_PA9_FUNC_TIM1_CH2 0x902
+#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905
+#define STM32F429_PA9_FUNC_USART1_TX 0x908
+#define STM32F429_PA9_FUNC_

[PATCH v3 1/9] ARM: Kconfig: Introduce MACH_STM32F429 flag

[Maxime Coquelin]

This patch introduces the MACH_STM32F429 to make possible to only select
STM32F429 pinctrl driver.

By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0365cbb..4d2fcba 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -967,6 +967,11 @@ config ARCH_STM32
help
  Support for STMicroelectronics STM32 processors.
 
+config MACH_STM32F429
+   bool "STMicrolectronics STM32F429"
+   depends on ARCH_STM32
+   default y
+
 # Definitions to make life easier
 config ARCH_ACORN
bool
-- 
1.9.1

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Re: [PATCH v3 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings

[Maxime Coquelin]

Hi Rob,

2015-12-09 4:41 GMT+01:00 Rob Herring <r...@kernel.org>:
> On Tue, Dec 08, 2015 at 01:45:04PM +0100, Maxime Coquelin wrote:
>> Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
>> ---
>>  .../bindings/pinctrl/st,stm32-pinctrl.txt  | 126 
>> +
>>  1 file changed, 126 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt 
>> b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>> new file mode 100644
>> index 000..7b4800c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
>> @@ -0,0 +1,126 @@
>> +* STM32 GPIO and Pin Mux/Config controller
>> +
>> +STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config 
>> hardware
>> +controller. It controls the input/output settings on the available pins and
>> +also provides ability to multiplex and configure the output of various 
>> on-chip
>> +controllers onto these pads.
>> +
>> +Pin controller node:
>> +Required properies:
>> + - compatible: value should be one of the following:
>> +   (a) "st,stm32f429-pinctrl"
>> + - #address-cells: The value of this property must be 1
>> + - #size-cells   : The value of this property must be 1
>> + - ranges: defines mapping between pin controller node (parent) to
>> +   gpio-bank node (children).
>> + - pins-are-numbered: Specify the subnodes are using numbered pinmux to
>> +   specify pins.
>> +
>> +GPIO controller/bank node:
>> +Required properties:
>> + - gpio-controller : Indicates this device is a GPIO controller
>> + - #gpio-cells : Should be two.
>> + The first cell is the pin number
>> + The second one is the polarity:
>> + - 0 for active high
>> + - 1 for active low
>> + - reg : The gpio address range, relative to the pinctrl 
>> range
>> + - clocks  : clock that drives this bank
>> + - st,bank-name: Should be a name string for this bank as specified 
>> in
>> +   the datasheet
>
> How do you intend to use this? We should come up with something generic
> or drop it.
Good point.
It is used to have a meaningful name set in gpio_chip's label.
I see two alternatives:
 1. replace "st,bank-name" with label
 2. use aliases, and construct label in driver with something like:
 kasprintf(GFP_KERNEL, "GPIO%c", 'A' + of_alias_get_id(np, "gpio"));

What do you prefer?
Do you have other ideas?

Thanks,
Maxime
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[PATCH v3 5/9] ARM: mach-stm32: Select pinctrl

[Maxime Coquelin]

Acked-by: Linus Walleij <linus.wall...@linaro.org>
Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4d2fcba..365714b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -963,6 +963,7 @@ config ARCH_STM32
select ARCH_HAS_RESET_CONTROLLER
select ARMV7M_SYSTICK
select CLKSRC_STM32
+   select PINCTRL
select RESET_CONTROLLER
help
  Support for STMicroelectronics STM32 processors.
-- 
1.9.1

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[PATCH v3 4/9] pinctrl: Add STM32 MCUs support

[Maxime Coquelin]

This patch adds pinctrl and GPIO support to STMicroelectronic's STM32
family of MCUs.

While it only supports STM32F429 for now, it has been designed to enable
support of other MCUs of the family (e.g. STM32F746).

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 drivers/pinctrl/Kconfig   |1 +
 drivers/pinctrl/Makefile  |1 +
 drivers/pinctrl/stm32/Kconfig |   16 +
 drivers/pinctrl/stm32/Makefile|5 +
 drivers/pinctrl/stm32/pinctrl-stm32.c |  856 +++
 drivers/pinctrl/stm32/pinctrl-stm32.h |   43 +
 drivers/pinctrl/stm32/pinctrl-stm32f429.c | 1598 +
 7 files changed, 2520 insertions(+)
 create mode 100644 drivers/pinctrl/stm32/Kconfig
 create mode 100644 drivers/pinctrl/stm32/Makefile
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b422e4e..9cdb7df 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -258,6 +258,7 @@ source "drivers/pinctrl/qcom/Kconfig"
 source "drivers/pinctrl/samsung/Kconfig"
 source "drivers/pinctrl/sh-pfc/Kconfig"
 source "drivers/pinctrl/spear/Kconfig"
+source "drivers/pinctrl/stm32/Kconfig"
 source "drivers/pinctrl/sunxi/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
 source "drivers/pinctrl/vt8500/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 738cb49..640079c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_ARCH_QCOM)   += qcom/
 obj-$(CONFIG_PINCTRL_SAMSUNG)  += samsung/
 obj-$(CONFIG_PINCTRL_SH_PFC)   += sh-pfc/
 obj-$(CONFIG_PLAT_SPEAR)   += spear/
+obj-$(CONFIG_ARCH_STM32)   += stm32/
 obj-$(CONFIG_ARCH_SUNXI)   += sunxi/
 obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
 obj-$(CONFIG_ARCH_VT8500)  += vt8500/
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
new file mode 100644
index 000..0f28841
--- /dev/null
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -0,0 +1,16 @@
+if ARCH_STM32 || COMPILE_TEST
+
+config PINCTRL_STM32
+   bool
+   depends on OF
+   select PINMUX
+   select GENERIC_PINCONF
+   select GPIOLIB
+
+config PINCTRL_STM32F429
+   bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && 
!MACH_STM32F429
+   depends on OF
+   default MACH_STM32F429
+   select PINCTRL_STM32
+
+endif
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
new file mode 100644
index 000..fc17d42
--- /dev/null
+++ b/drivers/pinctrl/stm32/Makefile
@@ -0,0 +1,5 @@
+# Core
+obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_STM32F429)+= pinctrl-stm32f429.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c 
b/drivers/pinctrl/stm32/pinctrl-stm32.c
new file mode 100644
index 000..4ebceaa
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -0,0 +1,856 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.st...@gmail.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ *
+ * Heavily based on Mediatek's pinctrl driver
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-stm32.h"
+
+#define STM32_GPIO_MODER   0x00
+#define STM32_GPIO_TYPER   0x04
+#define STM32_GPIO_SPEEDR  0x08
+#define STM32_GPIO_PUPDR   0x0c
+#define STM32_GPIO_IDR 0x10
+#define STM32_GPIO_ODR 0x14
+#define STM32_GPIO_BSRR0x18
+#define STM32_GPIO_LCKR0x1c
+#define STM32_GPIO_AFRL0x20
+#define STM32_GPIO_AFRH0x24
+
+#define STM32_GPIO_PINS_PER_BANK 16
+
+#define gpio_range_to_bank(chip) \
+   container_of(chip, struct stm32_gpio_bank, range)
+
+#define gpio_chip_to_bank(chip) \
+   container_of(chip, struct stm32_gpio_bank, gpio_chip)
+
+static const char * const stm32_gpio_functions[] = {
+   "gpio", "af0", "af1",
+   "af2", "af3", "af4",
+   "af5", "af6", "af7",
+   "af8", "af9", "af10",
+   "af11", "af12", "af13",
+   "af14", "af15", "analog",
+};
+
+struct stm32_pinctrl_group {
+   const char *name;
+   unsigned long config;
+   unsigned pin;
+};
+

[PATCH v3 7/9] ARM: dts: Add USART1 pin config to STM32F429 boards

[Maxime Coquelin]

This patch selects USART1 pin configuration on PA9/PA10 pins
for both Eval and Disco boards.

Acked-by: Linus Walleij <linus.wall...@linaro.org>
Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32429i-eval.dts  |  2 ++
 arch/arm/boot/dts/stm32f429-disco.dts |  2 ++
 arch/arm/boot/dts/stm32f429.dtsi  | 13 +
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts 
b/arch/arm/boot/dts/stm32429i-eval.dts
index 6964fc9..71fe17a 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -71,5 +71,7 @@
 };
 
  {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
status = "okay";
 };
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts 
b/arch/arm/boot/dts/stm32f429-disco.dts
index f0b731d..e3ce796 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -71,5 +71,7 @@
 };
 
  {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
status = "okay";
 };
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 62d2b3d..1cf713e 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -263,6 +263,19 @@
clocks = < 0 266>;
st,bank-name = "GPIOK";
};
+
+   usart1_pins_a: usart1@0 {
+   pins1 {
+   pinmux = ;
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins2 {
+   pinmux = 
;
+   bias-disable;
+   };
+   };
};
 
rcc: rcc@40023810 {
-- 
1.9.1

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[PATCH v3 9/9] ARM: config: Enable GPIO Led driver in stm32_defconfig

[Maxime Coquelin]

Acked-by: Linus Walleij <linus.wall...@linaro.org>
Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/configs/stm32_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 4725fab..92ade2e 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -52,6 +52,7 @@ CONFIG_SERIAL_STM32_CONSOLE=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 # CONFIG_FILE_LOCKING is not set
-- 
1.9.1

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[PATCH v3 6/9] ARM: dts: Add pinctrl node to STM32F429

[Maxime Coquelin]

The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32f429.dtsi | 97 
 1 file changed, 97 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 5e1e234..62d2b3d 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -46,6 +46,7 @@
  */
 
 #include "armv7-m.dtsi"
+#include 
 
 / {
clocks {
@@ -168,6 +169,102 @@
status = "disabled";
};
 
+   pin-controller {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,stm32f429-pinctrl";
+   ranges = <0 0x4002 0x3000>;
+   pins-are-numbered;
+
+   gpioa: gpio@4002 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x0 0x400>;
+   clocks = < 0 256>;
+   st,bank-name = "GPIOA";
+   };
+
+   gpiob: gpio@40020400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x400 0x400>;
+   clocks = < 0 257>;
+   st,bank-name = "GPIOB";
+   };
+
+   gpioc: gpio@40020800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x800 0x400>;
+   clocks = < 0 258>;
+   st,bank-name = "GPIOC";
+   };
+
+   gpiod: gpio@40020c00 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0xc00 0x400>;
+   clocks = < 0 259>;
+   st,bank-name = "GPIOD";
+   };
+
+   gpioe: gpio@40021000 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1000 0x400>;
+   clocks = < 0 260>;
+   st,bank-name = "GPIOE";
+   };
+
+   gpiof: gpio@40021400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1400 0x400>;
+   clocks = < 0 261>;
+   st,bank-name = "GPIOF";
+   };
+
+   gpiog: gpio@40021800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1800 0x400>;
+   clocks = < 0 262>;
+   st,bank-name = "GPIOG";
+   };
+
+   gpioh: gpio@40021c00 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1c00 0x400>;
+   clocks = < 0 263>;
+   st,bank-name = "GPIOH";
+   };
+
+   gpioi: gpio@40022000 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2000 0x400>;
+   clocks = < 0 264>;
+   st,bank-name = "GPIOI";
+   };
+
+   gpioj: gpio@40022400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2400 0x400>;
+   clocks = < 0 265>;
+   st,bank-name = "GPIOJ";
+   };
+
+   gpiok: gpio@40022800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2800 0x400>;
+   clocks = < 0 266>;
+   st,bank-name = "GPIOK";
+   };
+   };
+
rcc: rcc@40023810 {
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
-- 
1.9.1

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[PATCH v3 8/9] ARM: dts: Add leds support to STM32F429 boards

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32429i-eval.dts  | 17 +
 arch/arm/boot/dts/stm32f429-disco.dts | 11 +++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts 
b/arch/arm/boot/dts/stm32429i-eval.dts
index 71fe17a..e3921d9 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -64,6 +64,23 @@
aliases {
serial0 = 
};
+
+   leds {
+   compatible = "gpio-leds";
+   green {
+   gpios = < 6 1>;
+   linux,default-trigger = "heartbeat";
+   };
+   orange {
+   gpios = < 7 1>;
+   };
+   red {
+   gpios = < 10 1>;
+   };
+   blue {
+   gpios = < 12 1>;
+   };
+   };
 };
 
 _hse {
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts 
b/arch/arm/boot/dts/stm32f429-disco.dts
index e3ce796..0140807 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -64,6 +64,17 @@
aliases {
serial0 = 
};
+
+   leds {
+   compatible = "gpio-leds";
+   red {
+   gpios = < 14 0>;
+   };
+   green {
+   gpios = < 13 0>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
 };
 
 _hse {
-- 
1.9.1

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[PATCH v3 0/9] Add STM32 pinctrl/GPIO driver

[Maxime Coquelin]

Hi Linus, all,

This is the second round of STM32 pinctrl series, which improves DT
bindings declaration and documentation, and also fixes some commit fixup
issues. The series also contains two more patches, adding GPIO LEDs
support as a user of this driver.

The STM32 family has 16 pins per GPIO bank, and the number of bank varies
depending on the model.

Pins can be multiplexed either in GPIO mode, alternate function (up to 15
functions per pin) or analog (for ADC/DAC).

Changes since v2:
-
 - Rebase on v4.4-rc1
 - Declare leds also for Eval board
 - Set green led as heartbeat
 - Collect some acks

Changes since v1:
-
 - Add GPIO LEDs support in DT and defconfig
 - Changes pinmux DT bindings from macros to raw values (Daniel)
 - Improve DT bindings documentation (Daniel)
 - Fix some commit fixup and rebase issues.

Kind regards,
Maxime

Maxime Coquelin (9):
  ARM: Kconfig: Introduce MACH_STM32F429 flag
  Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings
  includes: dt-bindings: Add STM32F429 pinctrl DT bindings
  pinctrl: Add STM32 MCUs support
  ARM: mach-stm32: Select pinctrl
  ARM: dts: Add pinctrl node to STM32F429
  ARM: dts: Add USART1 pin config to STM32F429 boards
  ARM: dts: Add leds support to STM32F429 boards
  ARM: config: Enable GPIO Led driver in stm32_defconfig

 .../bindings/pinctrl/st,stm32-pinctrl.txt  |  126 ++
 arch/arm/Kconfig   |6 +
 arch/arm/boot/dts/stm32429i-eval.dts   |   19 +
 arch/arm/boot/dts/stm32f429-disco.dts  |   13 +
 arch/arm/boot/dts/stm32f429.dtsi   |  110 ++
 arch/arm/configs/stm32_defconfig   |1 +
 drivers/pinctrl/Kconfig|1 +
 drivers/pinctrl/Makefile   |1 +
 drivers/pinctrl/stm32/Kconfig  |   16 +
 drivers/pinctrl/stm32/Makefile |5 +
 drivers/pinctrl/stm32/pinctrl-stm32.c  |  856 +++
 drivers/pinctrl/stm32/pinctrl-stm32.h  |   43 +
 drivers/pinctrl/stm32/pinctrl-stm32f429.c  | 1598 
 include/dt-bindings/pinctrl/pinctrl-stm32.h|   12 +
 include/dt-bindings/pinctrl/stm32f429-pinfunc.h| 1241 +++
 15 files changed, 4048 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
 create mode 100644 drivers/pinctrl/stm32/Kconfig
 create mode 100644 drivers/pinctrl/stm32/Makefile
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h
 create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h

-- 
1.9.1

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[PATCH v3 3/9] includes: dt-bindings: Add STM32F429 pinctrl DT bindings

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 include/dt-bindings/pinctrl/pinctrl-stm32.h |   12 +
 include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1241 +++
 2 files changed, 1253 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h
 create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h

diff --git a/include/dt-bindings/pinctrl/pinctrl-stm32.h 
b/include/dt-bindings/pinctrl/pinctrl-stm32.h
new file mode 100644
index 000..a2e7222
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-stm32.h
@@ -0,0 +1,12 @@
+#ifndef _DT_BINDINGS_PINCTRL_STM32_H
+#define _DT_BINDINGS_PINCTRL_STM32_H
+
+#define STM32_PIN_NO(x) ((x) << 8)
+#define STM32_GET_PIN_NO(x) ((x) >> 8)
+#define STM32_GET_PIN_FUNC(x) ((x) & 0xff)
+
+#define STM32_PIN_GPIO 0
+#define STM32_PIN_AF(x)((x) + 1)
+#define STM32_PIN_ANALOG   (STM32_PIN_AF(15) + 1)
+
+#endif /* _DT_BINDINGS_PINCTRL_STM32_H */
diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h 
b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
new file mode 100644
index 000..9dd5fd0
--- /dev/null
+++ b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
@@ -0,0 +1,1241 @@
+#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H
+#define _DT_BINDINGS_STM32F429_PINFUNC_H
+
+#include 
+
+#define STM32F429_PA0_FUNC_GPIO 0x0
+#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
+#define STM32F429_PA0_FUNC_TIM5_CH1 0x3
+#define STM32F429_PA0_FUNC_TIM8_ETR 0x4
+#define STM32F429_PA0_FUNC_USART2_CTS 0x8
+#define STM32F429_PA0_FUNC_UART4_TX 0x9
+#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc
+#define STM32F429_PA0_FUNC_EVENTOUT 0x10
+#define STM32F429_PA0_FUNC_ANALOG 0x11
+
+#define STM32F429_PA1_FUNC_GPIO 0x100
+#define STM32F429_PA1_FUNC_TIM2_CH2 0x102
+#define STM32F429_PA1_FUNC_TIM5_CH2 0x103
+#define STM32F429_PA1_FUNC_USART2_RTS 0x108
+#define STM32F429_PA1_FUNC_UART4_RX 0x109
+#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c
+#define STM32F429_PA1_FUNC_EVENTOUT 0x110
+#define STM32F429_PA1_FUNC_ANALOG 0x111
+
+#define STM32F429_PA2_FUNC_GPIO 0x200
+#define STM32F429_PA2_FUNC_TIM2_CH3 0x202
+#define STM32F429_PA2_FUNC_TIM5_CH3 0x203
+#define STM32F429_PA2_FUNC_TIM9_CH1 0x204
+#define STM32F429_PA2_FUNC_USART2_TX 0x208
+#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c
+#define STM32F429_PA2_FUNC_EVENTOUT 0x210
+#define STM32F429_PA2_FUNC_ANALOG 0x211
+
+#define STM32F429_PA3_FUNC_GPIO 0x300
+#define STM32F429_PA3_FUNC_TIM2_CH4 0x302
+#define STM32F429_PA3_FUNC_TIM5_CH4 0x303
+#define STM32F429_PA3_FUNC_TIM9_CH2 0x304
+#define STM32F429_PA3_FUNC_USART2_RX 0x308
+#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b
+#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c
+#define STM32F429_PA3_FUNC_LCD_B5 0x30f
+#define STM32F429_PA3_FUNC_EVENTOUT 0x310
+#define STM32F429_PA3_FUNC_ANALOG 0x311
+
+#define STM32F429_PA4_FUNC_GPIO 0x400
+#define STM32F429_PA4_FUNC_SPI1_NSS 0x406
+#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407
+#define STM32F429_PA4_FUNC_USART2_CK 0x408
+#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d
+#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e
+#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f
+#define STM32F429_PA4_FUNC_EVENTOUT 0x410
+#define STM32F429_PA4_FUNC_ANALOG 0x411
+
+#define STM32F429_PA5_FUNC_GPIO 0x500
+#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502
+#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504
+#define STM32F429_PA5_FUNC_SPI1_SCK 0x506
+#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b
+#define STM32F429_PA5_FUNC_EVENTOUT 0x510
+#define STM32F429_PA5_FUNC_ANALOG 0x511
+
+#define STM32F429_PA6_FUNC_GPIO 0x600
+#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602
+#define STM32F429_PA6_FUNC_TIM3_CH1 0x603
+#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604
+#define STM32F429_PA6_FUNC_SPI1_MISO 0x606
+#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a
+#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e
+#define STM32F429_PA6_FUNC_LCD_G2 0x60f
+#define STM32F429_PA6_FUNC_EVENTOUT 0x610
+#define STM32F429_PA6_FUNC_ANALOG 0x611
+
+#define STM32F429_PA7_FUNC_GPIO 0x700
+#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702
+#define STM32F429_PA7_FUNC_TIM3_CH2 0x703
+#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704
+#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706
+#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a
+#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c
+#define STM32F429_PA7_FUNC_EVENTOUT 0x710
+#define STM32F429_PA7_FUNC_ANALOG 0x711
+
+#define STM32F429_PA8_FUNC_GPIO 0x800
+#define STM32F429_PA8_FUNC_MCO1 0x801
+#define STM32F429_PA8_FUNC_TIM1_CH1 0x802
+#define STM32F429_PA8_FUNC_I2C3_SCL 0x805
+#define STM32F429_PA8_FUNC_USART1_CK 0x808
+#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b
+#define STM32F429_PA8_FUNC_LCD_R6 0x80f
+#define STM32F429_PA8_FUNC_EVENTOUT 0x810
+#define STM32F429_PA8_FUNC_ANALOG 0x811
+
+#define STM32F429_PA9_FUNC_GPIO 0x900
+#define STM32F429_PA9_FUNC_TIM1_CH2 0x902
+#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905
+#define STM32F429_PA9_FUNC_USART1_TX 0x908
+#define STM32F429_PA9_FUNC_

[PATCH v3 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 .../bindings/pinctrl/st,stm32-pinctrl.txt  | 126 +
 1 file changed, 126 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
new file mode 100644
index 000..7b4800c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -0,0 +1,126 @@
+* STM32 GPIO and Pin Mux/Config controller
+
+STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
+controller. It controls the input/output settings on the available pins and
+also provides ability to multiplex and configure the output of various on-chip
+controllers onto these pads.
+
+Pin controller node:
+Required properies:
+ - compatible: value should be one of the following:
+   (a) "st,stm32f429-pinctrl"
+ - #address-cells: The value of this property must be 1
+ - #size-cells : The value of this property must be 1
+ - ranges  : defines mapping between pin controller node (parent) to
+   gpio-bank node (children).
+ - pins-are-numbered: Specify the subnodes are using numbered pinmux to
+   specify pins.
+
+GPIO controller/bank node:
+Required properties:
+ - gpio-controller : Indicates this device is a GPIO controller
+ - #gpio-cells   : Should be two.
+   The first cell is the pin number
+   The second one is the polarity:
+   - 0 for active high
+   - 1 for active low
+ - reg   : The gpio address range, relative to the pinctrl range
+ - clocks: clock that drives this bank
+ - st,bank-name  : Should be a name string for this bank as specified 
in
+   the datasheet
+
+Optional properties:
+ - reset:: Reference to the reset controller
+
+Example:
+#include 
+...
+
+   pin-controller {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,stm32f429-pinctrl";
+   ranges = <0 0x4002 0x3000>;
+   pins-are-numbered;
+
+   gpioa: gpio@4002 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x0 0x400>;
+   resets = <_ahb1 0>;
+   st,bank-name = "GPIOA";
+   };
+   ...
+   pin-functions nodes follow...
+   };
+
+Contents of function subnode node:
+--
+Subnode format
+A pinctrl node should contain at least one subnode representing the
+pinctrl group available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, pullups, drive, output high/low and output speed.
+
+node {
+   pinmux = ;
+   GENERIC_PINCONFIG;
+};
+
+Required properties:
+- pinmux: integer array, represents gpio pin number and mux setting.
+  Supported pin number and mux varies for different SoCs, and are defined in
+  dt-bindings/pinctrl/-pinfunc.h directly.
+  These defines are calculated as:
+((port * 16 + line) << 8) | function
+  With:
+- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
+- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
+- function: The function number, can be:
+  * 0 : GPIO
+  * 1 : Alternate Function 0
+  * 2 : Alternate Function 1
+  * 3 : Alternate Function 2
+  * ...
+  * 16 : Alternate Function 15
+  * 17 : Analog
+
+Optional properties:
+- GENERIC_PINCONFIG: is the generic pinconfig options to use.
+  Available options are:
+   - bias-disable,
+   - bias-pull-down,
+   - bias-pull-up,
+   - drive-push-pull,
+   - drive-open-drain,
+   - output-low
+   - output-high
+   - slew-rate = , with x being:
+   < 0 > : Low speed
+   < 1 > : Medium speed
+   < 2 > : Fast speed
+   < 3 > : High speed
+
+Example:
+
+pin-controller {
+...
+   usart1_pins_a: usart1@0 {
+   pins1 {
+   pinmux = ;
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins2 {
+   pinmux = ;
+   bias-disable;
+   };
+   };
+};
+
+ {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
+   status = "okay";
+};
-- 
1.9.1

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[PATCH v3 1/9] ARM: Kconfig: Introduce MACH_STM32F429 flag

[Maxime Coquelin]

This patch introduces the MACH_STM32F429 to make possible to only select
STM32F429 pinctrl driver.

By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0365cbb..4d2fcba 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -967,6 +967,11 @@ config ARCH_STM32
help
  Support for STMicroelectronics STM32 processors.
 
+config MACH_STM32F429
+   bool "STMicrolectronics STM32F429"
+   depends on ARCH_STM32
+   default y
+
 # Definitions to make life easier
 config ARCH_ACORN
bool
-- 
1.9.1

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[PATCH] ARM: dts: stm32f429: Boost perfs by remapping SDRAM Bank 1 to 0x0

[Maxime Coquelin]

STM32F429 allows to remap FMC SDRAM Bank 1 from 0xc000 to 0x0,
by writing 0x4 to SYSCFG_MEMRMP register.

As mentionned in the reference manual (see chapter 9.3.1), the performance
gain is really interresting:
"In remap mode at address 0x , the CPU can access the external
memory via ICode bus instead of System bus which boosts up the
performance."

These are the dhrystone results with and without the remap enabled:
Default (SDRAM in 0xc000):
-
Microseconds for one run through Dhrystone:   31.8
Dhrystones per Second:  31416.9

Remap (SDRAM in 0x000):
-
Microseconds for one run through Dhrystone:   20.6
Dhrystones per Second:  48520.1

This patch first change the SDRAM start address to 0x0 for STM32429i-EVAL
board, and also set the dma-range property as the other masters than the M4
CPU still see SDRAM in 0xc000.

Note that the Discovery board cannot benefit from this feature, since the
SDRAM is connected to Bank 2.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32429i-eval.dts | 2 +-
 arch/arm/boot/dts/stm32f429.dtsi | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts 
b/arch/arm/boot/dts/stm32429i-eval.dts
index 6964fc9..a717acb 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -58,7 +58,7 @@
};
 
memory {
-   reg = <0xc000 0x200>;
+   reg = <0x 0x200>;
};
 
aliases {
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index eaf7a72..84e5fb3 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -57,6 +57,8 @@
};
 
soc {
+   dma-ranges = <0xc000 0x0 0x1000>;
+
timer2: timer@4000 {
compatible = "st,stm32-timer";
reg = <0x4000 0x400>;
-- 
1.9.1

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Re: [PATCH v2 4/9] pinctrl: Add support STM32 MCUs

[Maxime Coquelin]

Hi Linus,

2015-10-17 19:23 GMT+02:00 Maxime Coquelin <mcoquelin.st...@gmail.com>:
> This patch adds pinctrl and GPIO support to STMicroelectronic's STM32
> family of MCUs.
>
> While it only supports STM32F429 for now, it has been designed to enable
> support of other MCUs of the family (e.g. STM32F746).
>
> Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
> ---
>  drivers/pinctrl/Kconfig   |1 +
>  drivers/pinctrl/Makefile  |1 +
>  drivers/pinctrl/stm32/Kconfig |   16 +
>  drivers/pinctrl/stm32/Makefile|5 +
>  drivers/pinctrl/stm32/pinctrl-stm32.c |  856 +++
>  drivers/pinctrl/stm32/pinctrl-stm32.h |   43 +
>  drivers/pinctrl/stm32/pinctrl-stm32f429.c | 1598 
> +
>  7 files changed, 2520 insertions(+)
>  create mode 100644 drivers/pinctrl/stm32/Kconfig
>  create mode 100644 drivers/pinctrl/stm32/Makefile
>  create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c
>  create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h
>  create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c
>

Gentle reminder, do you know when you will be able to review this driver?

Thanks in advance,
Maxime
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Re: [PATCH v4 3/4] ARM: dts: Add STM32 DMA support for STM32F429 MCU

[Maxime Coquelin]

2015-10-16 15:59 GMT+02:00 M'boumba Cedric Madianga :
> This patch adds STM32 DMA bindings for STM32F429.
>
> Signed-off-by: M'boumba Cedric Madianga 
> ---
>  arch/arm/boot/dts/stm32f429.dtsi | 31 +++
>  1 file changed, 31 insertions(+)

Applied to STM32 DT branch for v4.5.

Thanks!
Maxime
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Re: [PATCH v2 3/9] includes: dt-bindings: Add STM32F429 pinctrl DT bindings

[Maxime Coquelin]

2015-11-17 12:00 GMT+01:00 Linus Walleij <linus.wall...@linaro.org>:
> On Fri, Nov 6, 2015 at 1:57 PM, Maxime Coquelin
> <mcoquelin.st...@gmail.com> wrote:
>
>> Thinking again at it, I persist to believe have the defines makes it
>> easier to use.
>> With auto-completion, it makes it faster and less error prone to
>> select the right
>> alternate function without parsing the datasheet.
>
> Auto-completion ... should we design our source code to
> fit certain editors?
No, you are right.
But even without auto-completion, it is easier to have the values pre-computed.
And Mediatek has the defines, so it is better to do the same for STM32
for consistency.

>> But as these defines are not actually used on driver side, maybe I
>> could just move
>> them to the dts directory?
>
> No strong opinion there. include/dt-bindings is part of the bindings
> documentation actually so I guess it goes there.
Ok.

Thanks,
Maxime
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Re: [PATCH v2 3/9] includes: dt-bindings: Add STM32F429 pinctrl DT bindings

[Maxime Coquelin]

2015-10-22 14:35 GMT+02:00 Linus Walleij <linus.wall...@linaro.org>:
> On Tue, Oct 20, 2015 at 6:32 PM, Maxime Coquelin
> <mcoquelin.st...@gmail.com> wrote:
>> 2015-10-20 12:06 GMT+02:00 Daniel Thompson <daniel.thomp...@linaro.org>:
>>> On 17/10/15 18:23, Maxime Coquelin wrote:
>
>>> I suggesting that, like with the clock driver, there is no need to the
>>> STM32F429_PAXX_FUNC_YYY macros at all.
>>>
>>> Given the way you can enumerate pin config options in stm32f429.dtsi then I
>>> think stm32f429.dtsi is the only file that will ever include this header? If
>>> so then why not just plug the values directly into the pinmux fields. Its
>>> not duplicative and is easier to map back to data sheets.
>>>
>>> ~~~
>>> #define PIN_NO(x) ...
>>> #define PIN_AF(x) ...
>>>
>>> usart1_pins_a: usart1@0 {
>>> pins1 {
>>> pinmux = PIN_NO(9) | PIN_AF(7);
>>> bias-disable;
>>> drive-push-pull;
>>> slew-rate = <0>;
>>> };
>>> ...
>>> };
>>> ~~~
>>
>> The advantage with the defines is that you can see easily which pin we
>> are talking about.
>> Moreover, the defines are generated from the datasheet, so it is
>> painless to generate them.
>> And it will be consistent with Mediatek implementation, on which I
>> heavily inspired.
>>
>> Linus, what is your view?
>
> I have no strong view of this at all.
>
> I would ask the opinion of other people doing numbered muxes
> to see what is generally best for everyone to use,
> Sascha Hauer specifically, or the Mediatek people.

Thinking again at it, I persist to believe have the defines makes it
easier to use.
With auto-completion, it makes it faster and less error prone to
select the right
alternate function without parsing the datasheet.

But as these defines are not actually used on driver side, maybe I
could just move
them to the dts directory?

Regards,
Maxime
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Re: [PATCH v2 8/9] ARM: dts: Add leds support to STM32F429 Discovery board

[Maxime Coquelin]

2015-10-28 9:09 GMT+01:00 Daniel Thompson :
> On 27/10/15 21:52, Andreas Färber wrote:
>>
>> Am 27.10.2015 um 22:46 schrieb Linus Walleij:
>>>
>>> Heartbeat is awesome.
>>
>>
>> Yes, it's awesome for testing, but not for a .dts file that ends up in a
>> distro (not the case here, of course) and keeps blinking on the desk.
>>
>> If someone wants LEDs to blink, they can set that via sysfs or by
>> modifying their .dts locally.
>>
>> sunxi chose to keep LEDs off my default. For qcom we had a similar
>> discussion some weeks ago. I don't regularly read Linux patches, so feel
>> free to skim the archives yourself.
>
>
> Among the existing DTS files there is pretty significant use of heartbeat
> although its not absolute.
>
> There are 119 files that set a default-trigger, of these 91 (~75%) include a
> line to configure a heartbeat.
>
> Personally I'd be very happy with heartbeat by default on STM32... I've
> seldom worked on a board without a default-enabled heartbeat so they make me
> feel comfortable. ;-)

I will add heartbeat in next version, which will arrive when the
pinctrl driver first review is done.

Thanks,
Maxime
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Re: [PATCH v2 8/9] ARM: dts: Add leds support to STM32F429 Discovery board

[Maxime Coquelin]

2015-10-26 14:41 GMT+01:00 Linus Walleij <linus.wall...@linaro.org>:
> On Sat, Oct 17, 2015 at 7:23 PM, Maxime Coquelin
> <mcoquelin.st...@gmail.com> wrote:
>
>> Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
> (...)
>> +   leds {
>> +   compatible = "gpio-leds";
>> +   red {
>> +   gpios = < 14 0>;
>> +   };
>> +   green {
>> +   gpios = < 13 0>;
>> +   };
>
> I suggest you add labels to these LEDs.
>
> label = "red-LED"
> label = "green-LED"
>
> This make things so much easier in sysfs.

I'm not sure to understand where it makes things easier in sysfs.
This is the sysfs path for the red led:
/sys/class/leds/red/

Indeed, if label is not present, it gets the node name.

>
> Usually people also want to add a default linux,trigger to these,
> like linux,default-trigger = "heartbeat"; but whatever you prefer.

Makes sense, I will add default trigger in next version.

> Acked-by: Linus Walleij <linus.wall...@linaro.org>

Thanks!
Maxime
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Re: [PATCH v2 3/9] includes: dt-bindings: Add STM32F429 pinctrl DT bindings

[Maxime Coquelin]

2015-10-20 12:06 GMT+02:00 Daniel Thompson <daniel.thomp...@linaro.org>:
> On 17/10/15 18:23, Maxime Coquelin wrote:
>>
>> Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
>> ---
>>   include/dt-bindings/pinctrl/pinctrl-stm32.h |   12 +
>>   include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1241
>> +++
>>   2 files changed, 1253 insertions(+)
>>   create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h
>>   create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h
>>
>> diff --git a/include/dt-bindings/pinctrl/pinctrl-stm32.h
>> b/include/dt-bindings/pinctrl/pinctrl-stm32.h
>> new file mode 100644
>> index 000..a2e7222
>> --- /dev/null
>> +++ b/include/dt-bindings/pinctrl/pinctrl-stm32.h
>> @@ -0,0 +1,12 @@
>> +#ifndef _DT_BINDINGS_PINCTRL_STM32_H
>> +#define _DT_BINDINGS_PINCTRL_STM32_H
>> +
>> +#define STM32_PIN_NO(x) ((x) << 8)
>> +#define STM32_GET_PIN_NO(x) ((x) >> 8)
>> +#define STM32_GET_PIN_FUNC(x) ((x) & 0xff)
>> +
>> +#define STM32_PIN_GPIO 0
>> +#define STM32_PIN_AF(x)((x) + 1)
>> +#define STM32_PIN_ANALOG   (STM32_PIN_AF(15) + 1)
>> +
>> +#endif /* _DT_BINDINGS_PINCTRL_STM32_H */
>> diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
>> b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
>> new file mode 100644
>> index 000..9dd5fd0
>> --- /dev/null
>> +++ b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
>> @@ -0,0 +1,1241 @@
>> +#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H
>> +#define _DT_BINDINGS_STM32F429_PINFUNC_H
>> +
>> +#include 
>> +
>> +#define STM32F429_PA0_FUNC_GPIO 0x0
>> +#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
>
>
> Did you expand these out after my feedback (instead of things like:
> STM32_PIN_NO(0) | STM32_PIN_AF(1) )?
Yes.

>
> If so I must have been somewhat unclear.
Most likely I didn't understood what you meant!

>
> I suggesting that, like with the clock driver, there is no need to the
> STM32F429_PAXX_FUNC_YYY macros at all.
>
> Given the way you can enumerate pin config options in stm32f429.dtsi then I
> think stm32f429.dtsi is the only file that will ever include this header? If
> so then why not just plug the values directly into the pinmux fields. Its
> not duplicative and is easier to map back to data sheets.
>
> ~~~
> #define PIN_NO(x) ...
> #define PIN_AF(x) ...
>
> usart1_pins_a: usart1@0 {
> pins1 {
> pinmux = PIN_NO(9) | PIN_AF(7);
> bias-disable;
> drive-push-pull;
> slew-rate = <0>;
> };
> ...
> };
> ~~~

The advantage with the defines is that you can see easily which pin we
are talking about.
Moreover, the defines are generated from the datasheet, so it is
painless to generate them.
And it will be consistent with Mediatek implementation, on which I
heavily inspired.

Linus, what is your view?

Thanks,
Maxime
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[PATCH v2 0/9] Add STM32 pinctrl/GPIO driver

[Maxime Coquelin]

Hi Linus, all,

This is the second round of STM32 pinctrl series, which improves DT
bindings declaration and documentation, and also fixes some commit fixup
issues. The series also contains two more patches, adding GPIO LEDs
support as a user of this driver.

The STM32 family has 16 pins per GPIO bank, and the number of bank varies
depending on the model.

Pins can be multiplexed either in GPIO mode, alternate function (up to 15
functions per pin) or analog (for ADC/DAC).

Changes since v1:
-
 - Add GPIO LEDs support in DT and defconfig
 - Changes pinmux DT bindings from macros to raw values (Daniel)
 - Improve DT bindings documentation (Daniel)
 - Fix some commit fixup and rebase issues.

Kind regards,
Maxime

Maxime Coquelin (9):
  ARM: Kconfig: Introduce MACH_STM32F429 flag
  Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings
  includes: dt-bindings: Add STM32F429 pinctrl DT bindings
  pinctrl: Add support STM32 MCUs
  ARM: mach-stm32: Select pinctrl
  ARM: dts: Add pinctrl node to STM32F429
  ARM: dts: Add USART1 pin config to STM32F429 boards
  ARM: dts: Add leds support to STM32F429 Discovery board
  ARM: config: Enable GPIO Led driver in stm32_defconfig

 .../bindings/pinctrl/st,stm32-pinctrl.txt  |  126 ++
 arch/arm/Kconfig   |6 +
 arch/arm/boot/dts/stm32429i-eval.dts   |2 +
 arch/arm/boot/dts/stm32f429-disco.dts  |   12 +
 arch/arm/boot/dts/stm32f429.dtsi   |  110 ++
 arch/arm/configs/stm32_defconfig   |1 +
 drivers/pinctrl/Kconfig|1 +
 drivers/pinctrl/Makefile   |1 +
 drivers/pinctrl/stm32/Kconfig  |   16 +
 drivers/pinctrl/stm32/Makefile |5 +
 drivers/pinctrl/stm32/pinctrl-stm32.c  |  856 +++
 drivers/pinctrl/stm32/pinctrl-stm32.h  |   43 +
 drivers/pinctrl/stm32/pinctrl-stm32f429.c  | 1598 
 include/dt-bindings/pinctrl/pinctrl-stm32.h|   12 +
 include/dt-bindings/pinctrl/stm32f429-pinfunc.h| 1241 +++
 15 files changed, 4030 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
 create mode 100644 drivers/pinctrl/stm32/Kconfig
 create mode 100644 drivers/pinctrl/stm32/Makefile
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h
 create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h

-- 
1.9.1

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[PATCH 2/9] drivers: irqchip: Add STM32 external interrupts support

[Maxime Coquelin]

The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, fallin or both edges. Each line can also
be masked independently.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 drivers/irqchip/Kconfig  |   4 +
 drivers/irqchip/Makefile |   1 +
 drivers/irqchip/irq-stm32-exti.c | 169 +++
 3 files changed, 174 insertions(+)
 create mode 100644 drivers/irqchip/irq-stm32-exti.c

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 27b52c8..5bd8df5 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -187,3 +187,7 @@ config IMX_GPCV2
select IRQ_DOMAIN
help
  Enables the wakeup IRQs for IMX platforms with GPCv2 block
+
+config STM32_EXTI
+   bool
+   select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index bb3048f..cabe2f4 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC)+= 
irq-renesas-h8s.o
 obj-$(CONFIG_ARCH_SA1100)  += irq-sa11x0.o
 obj-$(CONFIG_INGENIC_IRQ)  += irq-ingenic.o
 obj-$(CONFIG_IMX_GPCV2)+= irq-imx-gpcv2.o
+obj-$(CONFIG_STM32_EXTI)   += irq-stm32-exti.o
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
new file mode 100644
index 000..02bfa80
--- /dev/null
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.st...@gmail.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define EXTI_IMR   0x0
+#define EXTI_EMR   0x4
+#define EXTI_RTSR  0x8
+#define EXTI_FTSR  0xc
+#define EXTI_SWIER 0x10
+#define EXTI_PR0x14
+
+static void stm32_irq_handler(struct irq_desc *desc)
+{
+   struct irq_domain *domain = irq_desc_get_handler_data(desc);
+   struct irq_chip_generic *gc = domain->gc->gc[0];
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   unsigned long pending;
+   int n;
+
+   chained_irq_enter(chip, desc);
+
+   pending = irq_reg_readl(gc, EXTI_PR);
+   for_each_set_bit(n, , BITS_PER_LONG) {
+   generic_handle_irq(irq_find_mapping(domain, n));
+   }
+
+   chained_irq_exit(chip, desc);
+}
+
+static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
+{
+   struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+   u32 rtsr, ftsr;
+   int pin = data->hwirq;
+
+   irq_gc_lock(gc);
+
+   rtsr = irq_reg_readl(gc, EXTI_RTSR);
+   ftsr = irq_reg_readl(gc, EXTI_FTSR);
+
+   switch (type) {
+   case IRQ_TYPE_EDGE_RISING:
+   rtsr |= BIT(pin);
+   ftsr &= ~BIT(pin);
+   break;
+   case IRQ_TYPE_EDGE_FALLING:
+   rtsr &= ~BIT(pin);
+   ftsr |= BIT(pin);
+   break;
+   case IRQ_TYPE_EDGE_BOTH:
+   rtsr |= BIT(pin);
+   ftsr |= BIT(pin);
+   break;
+   default:
+   irq_gc_unlock(gc);
+   return -EINVAL;
+   }
+
+   irq_reg_writel(gc, rtsr, EXTI_RTSR);
+   irq_reg_writel(gc, ftsr, EXTI_FTSR);
+
+   irq_gc_unlock(gc);
+
+   return 0;
+}
+
+static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+   struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+   int pin = data->hwirq;
+   u32 emr;
+
+   irq_gc_lock(gc);
+
+   emr = irq_reg_readl(gc, EXTI_EMR);
+   if (on)
+   emr |= BIT(pin);
+   else
+   emr &= ~BIT(pin);
+   irq_reg_writel(gc, emr, EXTI_EMR);
+
+   irq_gc_unlock(gc);
+
+   return 0;
+}
+
+static int __init stm32_exti_init(struct device_node *node,
+ struct device_node *parent)
+{
+   int nr_irqs, nr_exti, ret, i;
+   unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+   struct irq_domain *domain;
+   struct irq_chip_generic *gc;
+   void *base;
+
+   base = of_iomap(node, 0);
+   if (!base) {
+   pr_err("%s: Unable to map registers\n", node->full_name);
+   return -ENOMEM;
+   }
+
+   /* Determine number of irqs supported */
+   writel_relaxed(~0UL, base + EXTI_RTSR);
+   nr_exti = fls(readl_relaxed(base + EXTI_RTSR));
+   writel_relaxed(0, base + EXTI_RTSR);
+
+   pr_info("%s: %d External IRQs detected\n", node->full_name, nr_exti);
+
+   domain = irq_domain_add_linear(node, nr_exti,
+ 

[PATCH 9/9] ARM: config: Enable GPIO Key driver in stm32_defconfig

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/configs/stm32_defconfig | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 92ade2e..31894ef 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -38,7 +38,11 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_BLK_DEV is not set
 CONFIG_EEPROM_93CX6=y
-# CONFIG_INPUT is not set
+# CONFIG_INPUT_LEDS is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
 # CONFIG_UNIX98_PTYS is not set
-- 
1.9.1

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[PATCH 7/9] ARM: dts: Add GPIO irq support to STM2F429

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32f429.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index a2c3aaa..bc84e8b 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -169,6 +169,11 @@
status = "disabled";
};
 
+   syscfg: system-config@40013800 {
+   compatible = "syscon";
+   reg = <0x40013800 0x400>;
+   };
+
exti: interrupt-controller@40013c00 {
compatible = "st,stm32-exti";
interrupt-controller;
@@ -182,6 +187,8 @@
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
ranges = <0 0x4002 0x3000>;
+   interrupt-parent = <>;
+   st,syscfg = < 0x8>;
pins-are-numbered;
 
gpioa: gpio@4002 {
-- 
1.9.1

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[PATCH 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index 7b4800c..dd95bec 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -13,6 +13,9 @@ Required properies:
  - #size-cells : The value of this property must be 1
  - ranges  : defines mapping between pin controller node (parent) to
gpio-bank node (children).
+ - interrupt-parent: phandle of the interrupt parent to which the external
+   GPIO interrupts are forwarded to.
+ - st,syscfg: phandle of the syscfg node used for IRQ mux selection.
  - pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
 
-- 
1.9.1

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[PATCH 0/9] Add STM32 EXTI interrupt controller support

[Maxime Coquelin]

This series adds support to EXTI interrupt controller and GPIO IRQ support in
STM32 pinctrl driver.

The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, fallin or both edges. Each line can also
be masked independently.

This series applies on top of STM32 pinctrl v2 series.

Regards,
Maxime

Maxime Coquelin (9):
  Documentation: dt-bindings: Document STM32 EXTI controller bindings
  drivers: irqchip: Add STM32 external interrupts support
  ARM: STM32: Select external interrupts controller
  ARM: dts: Add EXTI controller node to stm32f429
  Documentation: dt-bindings: Add IRQ related properties of STM32
pinctrl
  pinctrl: Add IRQ support to STM32 gpios
  ARM: dts: Add GPIO irq support to STM2F429
  ARM: dts: Declare push button as GPIO key on stm32f429 Disco board
  ARM: config: Enable GPIO Key driver in stm32_defconfig

 .../interrupt-controller/st,stm32-exti.txt |  20 +++
 .../bindings/pinctrl/st,stm32-pinctrl.txt  |   3 +
 arch/arm/Kconfig   |   1 +
 arch/arm/boot/dts/stm32429i-eval.dts   |  19 +++
 arch/arm/boot/dts/stm32f429-disco.dts  |  13 ++
 arch/arm/boot/dts/stm32f429.dtsi   |  15 ++
 arch/arm/configs/stm32_defconfig   |   6 +-
 drivers/irqchip/Kconfig|   4 +
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/irq-stm32-exti.c   | 169 +
 drivers/pinctrl/stm32/Kconfig  |   1 +
 drivers/pinctrl/stm32/pinctrl-stm32.c  |  68 +
 12 files changed, 319 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
 create mode 100644 drivers/irqchip/irq-stm32-exti.c

-- 
1.9.1

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[PATCH 3/9] ARM: STM32: Select external interrupts controller

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8a764ba..8ca5b2b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -986,6 +986,7 @@ config ARCH_STM32
select CLKSRC_STM32
select PINCTRL
select RESET_CONTROLLER
+   select STM32_EXTI
help
  Support for STMicroelectronics STM32 processors.
 
-- 
1.9.1

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[PATCH 6/9] pinctrl: Add IRQ support to STM32 gpios

[Maxime Coquelin]

This patch adds IRQ support to STM32 gpios.

The EXTI controller has 16 lines dedicated to GPIOs.
EXTI line n can be connected to only line n of one of the GPIO ports, for
example EXTI0 can be connected to either PA0, or PB0, or PC0...
This port selection is done by specifying the port number into System
Config registers.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 drivers/pinctrl/stm32/Kconfig |  1 +
 drivers/pinctrl/stm32/pinctrl-stm32.c | 68 +++
 2 files changed, 69 insertions(+)

diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 0f28841..b5cac5b 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -6,6 +6,7 @@ config PINCTRL_STM32
select PINMUX
select GENERIC_PINCONF
select GPIOLIB
+   select MFD_SYSCON
 
 config PINCTRL_STM32F429
bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && 
!MACH_STM32F429
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c 
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 4ebceaa..954b596 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -8,6 +8,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -20,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -82,6 +85,9 @@ struct stm32_pinctrl {
struct stm32_gpio_bank *banks;
unsigned nbanks;
const struct stm32_pinctrl_match_data *match_data;
+   struct irq_domain   *domain;
+   struct regmap   *regmap;
+   struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
 };
 
 static inline int stm32_gpio_pin(int gpio)
@@ -179,6 +185,22 @@ static int stm32_gpio_direction_output(struct gpio_chip 
*chip,
return 0;
 }
 
+
+static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+   struct stm32_pinctrl *pctl = dev_get_drvdata(chip->dev);
+   struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);
+   unsigned int virq;
+
+   regmap_field_write(pctl->irqmux[offset], bank->range.id);
+
+   virq = irq_create_mapping(pctl->domain, offset);
+   if (!virq)
+   return -ENXIO;
+
+   return virq;
+}
+
 static struct gpio_chip stm32_gpio_template = {
.request= stm32_gpio_request,
.free   = stm32_gpio_free,
@@ -186,6 +208,7 @@ static struct gpio_chip stm32_gpio_template = {
.set= stm32_gpio_set,
.direction_input= stm32_gpio_direction_input,
.direction_output   = stm32_gpio_direction_output,
+   .to_irq = stm32_gpio_to_irq,
 };
 
 /* Pinctrl functions */
@@ -731,6 +754,47 @@ static int stm32_gpiolib_register_bank(struct 
stm32_pinctrl *pctl,
return 0;
 }
 
+static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
+  struct stm32_pinctrl *pctl)
+{
+   struct device_node *np = pdev->dev.of_node, *parent;
+   struct device *dev = >dev;
+   struct regmap *rm;
+   int offset, ret, i;
+
+   parent = of_irq_find_parent(np);
+   if (!parent)
+   return -ENXIO;
+
+   pctl->domain = irq_find_host(parent);
+   if (!pctl->domain)
+   return -ENXIO;
+
+   pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
+   if (IS_ERR(pctl->regmap))
+   return PTR_ERR(pctl->regmap);
+
+   rm = pctl->regmap;
+
+   ret = of_property_read_u32_index(np, "st,syscfg", 1, );
+   if (ret)
+   return ret;
+
+   for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
+   struct reg_field mux;
+
+   mux.reg = offset + (i / 4) * 4;
+   mux.lsb = (i % 4) * 4;
+   mux.msb = mux.lsb + 3;
+
+   pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
+   if (IS_ERR(pctl->irqmux[i]))
+   return PTR_ERR(pctl->irqmux[i]);
+   }
+
+   return 0;
+}
+
 static int stm32_pctrl_build_state(struct platform_device *pdev)
 {
struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
@@ -823,6 +887,10 @@ int stm32_pctl_probe(struct platform_device *pdev)
}
}
 
+   ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
+   if (ret)
+   return ret;
+
pins = devm_kcalloc(>dev, pctl->match_data->npins, sizeof(*pins),
GFP_KERNEL);
if (!pins)
-- 
1.9.1

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[PATCH 4/9] ARM: dts: Add EXTI controller node to stm32f429

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32f429.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index eb3580e..a2c3aaa 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -169,6 +169,14 @@
status = "disabled";
};
 
+   exti: interrupt-controller@40013c00 {
+   compatible = "st,stm32-exti";
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   reg = <0x40013C00 0x400>;
+   interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, 
<23>, <40>, <41>, <42>, <62>, <76>;
+   };
+
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
-- 
1.9.1

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[PATCH 8/9] ARM: dts: Declare push button as GPIO key on stm32f429 Disco board

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32429i-eval.dts  | 19 +++
 arch/arm/boot/dts/stm32f429-disco.dts | 13 +
 2 files changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts 
b/arch/arm/boot/dts/stm32429i-eval.dts
index 71fe17a..be21931 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -47,6 +47,7 @@
 
 /dts-v1/;
 #include "stm32f429.dtsi"
+#include 
 
 / {
model = "STMicroelectronics STM32429i-EVAL board";
@@ -64,6 +65,24 @@
aliases {
serial0 = 
};
+
+   gpio_keys {
+   compatible = "gpio-keys";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   autorepeat;
+   button@0 {
+   label = "Wake up";
+   linux,code = ;
+   gpios = < 0 0>;
+   };
+   button@1 {
+   label = "Tamper";
+   linux,code = ;
+   gpios = < 13 0>;
+   };
+
+   };
 };
 
 _hse {
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts 
b/arch/arm/boot/dts/stm32f429-disco.dts
index 532c499..2cb4c9e 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -47,6 +47,7 @@
 
 /dts-v1/;
 #include "stm32f429.dtsi"
+#include 
 
 / {
model = "STMicroelectronics STM32F429i-DISCO board";
@@ -74,6 +75,18 @@
gpios = < 13 0>;
};
};
+
+   gpio_keys {
+   compatible = "gpio-keys";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   autorepeat;
+   button@0 {
+   label = "User";
+   linux,code = ;
+   gpios = < 0 0>;
+   };
+   };
 };
 
 _hse {
-- 
1.9.1

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[PATCH v2 3/9] includes: dt-bindings: Add STM32F429 pinctrl DT bindings

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 include/dt-bindings/pinctrl/pinctrl-stm32.h |   12 +
 include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1241 +++
 2 files changed, 1253 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h
 create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h

diff --git a/include/dt-bindings/pinctrl/pinctrl-stm32.h 
b/include/dt-bindings/pinctrl/pinctrl-stm32.h
new file mode 100644
index 000..a2e7222
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-stm32.h
@@ -0,0 +1,12 @@
+#ifndef _DT_BINDINGS_PINCTRL_STM32_H
+#define _DT_BINDINGS_PINCTRL_STM32_H
+
+#define STM32_PIN_NO(x) ((x) << 8)
+#define STM32_GET_PIN_NO(x) ((x) >> 8)
+#define STM32_GET_PIN_FUNC(x) ((x) & 0xff)
+
+#define STM32_PIN_GPIO 0
+#define STM32_PIN_AF(x)((x) + 1)
+#define STM32_PIN_ANALOG   (STM32_PIN_AF(15) + 1)
+
+#endif /* _DT_BINDINGS_PINCTRL_STM32_H */
diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h 
b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
new file mode 100644
index 000..9dd5fd0
--- /dev/null
+++ b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
@@ -0,0 +1,1241 @@
+#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H
+#define _DT_BINDINGS_STM32F429_PINFUNC_H
+
+#include 
+
+#define STM32F429_PA0_FUNC_GPIO 0x0
+#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
+#define STM32F429_PA0_FUNC_TIM5_CH1 0x3
+#define STM32F429_PA0_FUNC_TIM8_ETR 0x4
+#define STM32F429_PA0_FUNC_USART2_CTS 0x8
+#define STM32F429_PA0_FUNC_UART4_TX 0x9
+#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc
+#define STM32F429_PA0_FUNC_EVENTOUT 0x10
+#define STM32F429_PA0_FUNC_ANALOG 0x11
+
+#define STM32F429_PA1_FUNC_GPIO 0x100
+#define STM32F429_PA1_FUNC_TIM2_CH2 0x102
+#define STM32F429_PA1_FUNC_TIM5_CH2 0x103
+#define STM32F429_PA1_FUNC_USART2_RTS 0x108
+#define STM32F429_PA1_FUNC_UART4_RX 0x109
+#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c
+#define STM32F429_PA1_FUNC_EVENTOUT 0x110
+#define STM32F429_PA1_FUNC_ANALOG 0x111
+
+#define STM32F429_PA2_FUNC_GPIO 0x200
+#define STM32F429_PA2_FUNC_TIM2_CH3 0x202
+#define STM32F429_PA2_FUNC_TIM5_CH3 0x203
+#define STM32F429_PA2_FUNC_TIM9_CH1 0x204
+#define STM32F429_PA2_FUNC_USART2_TX 0x208
+#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c
+#define STM32F429_PA2_FUNC_EVENTOUT 0x210
+#define STM32F429_PA2_FUNC_ANALOG 0x211
+
+#define STM32F429_PA3_FUNC_GPIO 0x300
+#define STM32F429_PA3_FUNC_TIM2_CH4 0x302
+#define STM32F429_PA3_FUNC_TIM5_CH4 0x303
+#define STM32F429_PA3_FUNC_TIM9_CH2 0x304
+#define STM32F429_PA3_FUNC_USART2_RX 0x308
+#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b
+#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c
+#define STM32F429_PA3_FUNC_LCD_B5 0x30f
+#define STM32F429_PA3_FUNC_EVENTOUT 0x310
+#define STM32F429_PA3_FUNC_ANALOG 0x311
+
+#define STM32F429_PA4_FUNC_GPIO 0x400
+#define STM32F429_PA4_FUNC_SPI1_NSS 0x406
+#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407
+#define STM32F429_PA4_FUNC_USART2_CK 0x408
+#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d
+#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e
+#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f
+#define STM32F429_PA4_FUNC_EVENTOUT 0x410
+#define STM32F429_PA4_FUNC_ANALOG 0x411
+
+#define STM32F429_PA5_FUNC_GPIO 0x500
+#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502
+#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504
+#define STM32F429_PA5_FUNC_SPI1_SCK 0x506
+#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b
+#define STM32F429_PA5_FUNC_EVENTOUT 0x510
+#define STM32F429_PA5_FUNC_ANALOG 0x511
+
+#define STM32F429_PA6_FUNC_GPIO 0x600
+#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602
+#define STM32F429_PA6_FUNC_TIM3_CH1 0x603
+#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604
+#define STM32F429_PA6_FUNC_SPI1_MISO 0x606
+#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a
+#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e
+#define STM32F429_PA6_FUNC_LCD_G2 0x60f
+#define STM32F429_PA6_FUNC_EVENTOUT 0x610
+#define STM32F429_PA6_FUNC_ANALOG 0x611
+
+#define STM32F429_PA7_FUNC_GPIO 0x700
+#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702
+#define STM32F429_PA7_FUNC_TIM3_CH2 0x703
+#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704
+#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706
+#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a
+#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c
+#define STM32F429_PA7_FUNC_EVENTOUT 0x710
+#define STM32F429_PA7_FUNC_ANALOG 0x711
+
+#define STM32F429_PA8_FUNC_GPIO 0x800
+#define STM32F429_PA8_FUNC_MCO1 0x801
+#define STM32F429_PA8_FUNC_TIM1_CH1 0x802
+#define STM32F429_PA8_FUNC_I2C3_SCL 0x805
+#define STM32F429_PA8_FUNC_USART1_CK 0x808
+#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b
+#define STM32F429_PA8_FUNC_LCD_R6 0x80f
+#define STM32F429_PA8_FUNC_EVENTOUT 0x810
+#define STM32F429_PA8_FUNC_ANALOG 0x811
+
+#define STM32F429_PA9_FUNC_GPIO 0x900
+#define STM32F429_PA9_FUNC_TIM1_CH2 0x902
+#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905
+#define STM32F429_PA9_FUNC_USART1_TX 0x908
+#define STM32F429_PA9_FUNC_

[PATCH 1/9] Documentation: dt-bindings: Document STM32 EXTI controller bindings

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 .../bindings/interrupt-controller/st,stm32-exti.txt  | 20 
 1 file changed, 20 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt 
b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
new file mode 100644
index 000..6e7703d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
@@ -0,0 +1,20 @@
+STM32 External Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "st,stm32-exti"
+- reg: Specifies base physical address and size of the registers
+- interrupt-controller: Indentifies the node as an interrupt controller
+- #interrupt-cells: Specifies the number of cells to encode an interrupt
+  specifier, shall be 2
+- interrupts: interrupts references to primary interrupt controller
+
+Example:
+
+exti: interrupt-controller@40013c00 {
+   compatible = "st,stm32-exti";
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   reg = <0x40013C00 0x400>;
+   interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, 
<42>, <62>, <76>;
+};
-- 
1.9.1

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[PATCH v2 8/9] ARM: dts: Add leds support to STM32F429 Discovery board

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32f429-disco.dts | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429-disco.dts 
b/arch/arm/boot/dts/stm32f429-disco.dts
index e3ce796..532c499 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -64,6 +64,16 @@
aliases {
serial0 = 
};
+
+   leds {
+   compatible = "gpio-leds";
+   red {
+   gpios = < 14 0>;
+   };
+   green {
+   gpios = < 13 0>;
+   };
+   };
 };
 
 _hse {
-- 
1.9.1

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[PATCH v2 9/9] ARM: config: Enable GPIO Led driver in stm32_defconfig

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/configs/stm32_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 4725fab..92ade2e 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -52,6 +52,7 @@ CONFIG_SERIAL_STM32_CONSOLE=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 # CONFIG_FILE_LOCKING is not set
-- 
1.9.1

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[PATCH v2 1/9] ARM: Kconfig: Introduce MACH_STM32F429 flag

[Maxime Coquelin]

This patch introduces the MACH_STM32F429 to make possible to only select
STM32F429 pinctrl driver.

By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 72ad724..bf94e54 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -988,6 +988,11 @@ config ARCH_STM32
help
  Support for STMicroelectronics STM32 processors.
 
+config MACH_STM32F429
+   bool "STMicrolectronics STM32F429"
+   depends on ARCH_STM32
+   default y
+
 # Definitions to make life easier
 config ARCH_ACORN
bool
-- 
1.9.1

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[PATCH v2 7/9] ARM: dts: Add USART1 pin config to STM32F429 boards

[Maxime Coquelin]

This patch selects USART1 pin configuration on PA9/PA10 pins
for both Eval and Disco boards.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32429i-eval.dts  |  2 ++
 arch/arm/boot/dts/stm32f429-disco.dts |  2 ++
 arch/arm/boot/dts/stm32f429.dtsi  | 13 +
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts 
b/arch/arm/boot/dts/stm32429i-eval.dts
index 6964fc9..71fe17a 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -71,5 +71,7 @@
 };
 
  {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
status = "okay";
 };
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts 
b/arch/arm/boot/dts/stm32f429-disco.dts
index f0b731d..e3ce796 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -71,5 +71,7 @@
 };
 
  {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
status = "okay";
 };
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 9e6e75c..eb3580e 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -263,6 +263,19 @@
clocks = < 0 266>;
st,bank-name = "GPIOK";
};
+
+   usart1_pins_a: usart1@0 {
+   pins1 {
+   pinmux = ;
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins2 {
+   pinmux = 
;
+   bias-disable;
+   };
+   };
};
 
rcc: rcc@40023810 {
-- 
1.9.1

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[PATCH v2 5/9] ARM: mach-stm32: Select pinctrl

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bf94e54..8a764ba 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -984,6 +984,7 @@ config ARCH_STM32
select ARCH_HAS_RESET_CONTROLLER
select ARMV7M_SYSTICK
select CLKSRC_STM32
+   select PINCTRL
select RESET_CONTROLLER
help
  Support for STMicroelectronics STM32 processors.
-- 
1.9.1

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[PATCH v2 6/9] ARM: dts: Add pinctrl node to STM32F429

[Maxime Coquelin]

The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32f429.dtsi | 97 
 1 file changed, 97 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index d78a481..9e6e75c 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -46,6 +46,7 @@
  */
 
 #include "armv7-m.dtsi"
+#include 
 
 / {
clocks {
@@ -168,6 +169,102 @@
status = "disabled";
};
 
+   pin-controller {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,stm32f429-pinctrl";
+   ranges = <0 0x4002 0x3000>;
+   pins-are-numbered;
+
+   gpioa: gpio@4002 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x0 0x400>;
+   clocks = < 0 256>;
+   st,bank-name = "GPIOA";
+   };
+
+   gpiob: gpio@40020400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x400 0x400>;
+   clocks = < 0 257>;
+   st,bank-name = "GPIOB";
+   };
+
+   gpioc: gpio@40020800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x800 0x400>;
+   clocks = < 0 258>;
+   st,bank-name = "GPIOC";
+   };
+
+   gpiod: gpio@40020c00 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0xc00 0x400>;
+   clocks = < 0 259>;
+   st,bank-name = "GPIOD";
+   };
+
+   gpioe: gpio@40021000 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1000 0x400>;
+   clocks = < 0 260>;
+   st,bank-name = "GPIOE";
+   };
+
+   gpiof: gpio@40021400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1400 0x400>;
+   clocks = < 0 261>;
+   st,bank-name = "GPIOF";
+   };
+
+   gpiog: gpio@40021800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1800 0x400>;
+   clocks = < 0 262>;
+   st,bank-name = "GPIOG";
+   };
+
+   gpioh: gpio@40021c00 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1c00 0x400>;
+   clocks = < 0 263>;
+   st,bank-name = "GPIOH";
+   };
+
+   gpioi: gpio@40022000 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2000 0x400>;
+   clocks = < 0 264>;
+   st,bank-name = "GPIOI";
+   };
+
+   gpioj: gpio@40022400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2400 0x400>;
+   clocks = < 0 265>;
+   st,bank-name = "GPIOJ";
+   };
+
+   gpiok: gpio@40022800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2800 0x400>;
+   clocks = < 0 266>;
+   st,bank-name = "GPIOK";
+   };
+   };
+
rcc: rcc@40023810 {
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
-- 
1.9.1

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[PATCH v2 4/9] pinctrl: Add support STM32 MCUs

[Maxime Coquelin]

This patch adds pinctrl and GPIO support to STMicroelectronic's STM32
family of MCUs.

While it only supports STM32F429 for now, it has been designed to enable
support of other MCUs of the family (e.g. STM32F746).

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 drivers/pinctrl/Kconfig   |1 +
 drivers/pinctrl/Makefile  |1 +
 drivers/pinctrl/stm32/Kconfig |   16 +
 drivers/pinctrl/stm32/Makefile|5 +
 drivers/pinctrl/stm32/pinctrl-stm32.c |  856 +++
 drivers/pinctrl/stm32/pinctrl-stm32.h |   43 +
 drivers/pinctrl/stm32/pinctrl-stm32f429.c | 1598 +
 7 files changed, 2520 insertions(+)
 create mode 100644 drivers/pinctrl/stm32/Kconfig
 create mode 100644 drivers/pinctrl/stm32/Makefile
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 84dd2ed..5749cc4 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -249,6 +249,7 @@ source "drivers/pinctrl/sunxi/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
 source "drivers/pinctrl/vt8500/Kconfig"
 source "drivers/pinctrl/mediatek/Kconfig"
+source "drivers/pinctrl/stm32/Kconfig"
 
 config PINCTRL_XWAY
bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index cad077c..1fffcda 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_ARCH_SUNXI)  += sunxi/
 obj-$(CONFIG_ARCH_UNIPHIER)+= uniphier/
 obj-$(CONFIG_ARCH_VT8500)  += vt8500/
 obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
+obj-$(CONFIG_ARCH_STM32)   += stm32/
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
new file mode 100644
index 000..0f28841
--- /dev/null
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -0,0 +1,16 @@
+if ARCH_STM32 || COMPILE_TEST
+
+config PINCTRL_STM32
+   bool
+   depends on OF
+   select PINMUX
+   select GENERIC_PINCONF
+   select GPIOLIB
+
+config PINCTRL_STM32F429
+   bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && 
!MACH_STM32F429
+   depends on OF
+   default MACH_STM32F429
+   select PINCTRL_STM32
+
+endif
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
new file mode 100644
index 000..fc17d42
--- /dev/null
+++ b/drivers/pinctrl/stm32/Makefile
@@ -0,0 +1,5 @@
+# Core
+obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_STM32F429)+= pinctrl-stm32f429.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c 
b/drivers/pinctrl/stm32/pinctrl-stm32.c
new file mode 100644
index 000..4ebceaa
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -0,0 +1,856 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.st...@gmail.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ *
+ * Heavily based on Mediatek's pinctrl driver
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-stm32.h"
+
+#define STM32_GPIO_MODER   0x00
+#define STM32_GPIO_TYPER   0x04
+#define STM32_GPIO_SPEEDR  0x08
+#define STM32_GPIO_PUPDR   0x0c
+#define STM32_GPIO_IDR 0x10
+#define STM32_GPIO_ODR 0x14
+#define STM32_GPIO_BSRR0x18
+#define STM32_GPIO_LCKR0x1c
+#define STM32_GPIO_AFRL0x20
+#define STM32_GPIO_AFRH0x24
+
+#define STM32_GPIO_PINS_PER_BANK 16
+
+#define gpio_range_to_bank(chip) \
+   container_of(chip, struct stm32_gpio_bank, range)
+
+#define gpio_chip_to_bank(chip) \
+   container_of(chip, struct stm32_gpio_bank, gpio_chip)
+
+static const char * const stm32_gpio_functions[] = {
+   "gpio", "af0", "af1",
+   "af2", "af3", "af4",
+   "af5", "af6", "af7",
+   "af8", "af9", "af10",
+   "af11", "af12", "af13",
+   "af14", "af15", "analog",
+};
+
+struct stm32_pinctrl_group {
+   const char *name;
+   unsigned long config;
+   unsigned pin;
+};
+
+struct stm32_gpio_bank {
+   void __iomem *base;
+   struct clk *clk;
+   spinlock_t lock;
+   struct gpio_chip gpio_chip;
+   struct pinctrl_gpio_range range;
+};
+
+struct stm32_pinctrl {
+   struct device *dev;

[PATCH v2 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 .../bindings/pinctrl/st,stm32-pinctrl.txt  | 126 +
 1 file changed, 126 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
new file mode 100644
index 000..7b4800c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -0,0 +1,126 @@
+* STM32 GPIO and Pin Mux/Config controller
+
+STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
+controller. It controls the input/output settings on the available pins and
+also provides ability to multiplex and configure the output of various on-chip
+controllers onto these pads.
+
+Pin controller node:
+Required properies:
+ - compatible: value should be one of the following:
+   (a) "st,stm32f429-pinctrl"
+ - #address-cells: The value of this property must be 1
+ - #size-cells : The value of this property must be 1
+ - ranges  : defines mapping between pin controller node (parent) to
+   gpio-bank node (children).
+ - pins-are-numbered: Specify the subnodes are using numbered pinmux to
+   specify pins.
+
+GPIO controller/bank node:
+Required properties:
+ - gpio-controller : Indicates this device is a GPIO controller
+ - #gpio-cells   : Should be two.
+   The first cell is the pin number
+   The second one is the polarity:
+   - 0 for active high
+   - 1 for active low
+ - reg   : The gpio address range, relative to the pinctrl range
+ - clocks: clock that drives this bank
+ - st,bank-name  : Should be a name string for this bank as specified 
in
+   the datasheet
+
+Optional properties:
+ - reset:: Reference to the reset controller
+
+Example:
+#include 
+...
+
+   pin-controller {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,stm32f429-pinctrl";
+   ranges = <0 0x4002 0x3000>;
+   pins-are-numbered;
+
+   gpioa: gpio@4002 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x0 0x400>;
+   resets = <_ahb1 0>;
+   st,bank-name = "GPIOA";
+   };
+   ...
+   pin-functions nodes follow...
+   };
+
+Contents of function subnode node:
+--
+Subnode format
+A pinctrl node should contain at least one subnode representing the
+pinctrl group available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, pullups, drive, output high/low and output speed.
+
+node {
+   pinmux = ;
+   GENERIC_PINCONFIG;
+};
+
+Required properties:
+- pinmux: integer array, represents gpio pin number and mux setting.
+  Supported pin number and mux varies for different SoCs, and are defined in
+  dt-bindings/pinctrl/-pinfunc.h directly.
+  These defines are calculated as:
+((port * 16 + line) << 8) | function
+  With:
+- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
+- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
+- function: The function number, can be:
+  * 0 : GPIO
+  * 1 : Alternate Function 0
+  * 2 : Alternate Function 1
+  * 3 : Alternate Function 2
+  * ...
+  * 16 : Alternate Function 15
+  * 17 : Analog
+
+Optional properties:
+- GENERIC_PINCONFIG: is the generic pinconfig options to use.
+  Available options are:
+   - bias-disable,
+   - bias-pull-down,
+   - bias-pull-up,
+   - drive-push-pull,
+   - drive-open-drain,
+   - output-low
+   - output-high
+   - slew-rate = , with x being:
+   < 0 > : Low speed
+   < 1 > : Medium speed
+   < 2 > : Fast speed
+   < 3 > : High speed
+
+Example:
+
+pin-controller {
+...
+   usart1_pins_a: usart1@0 {
+   pins1 {
+   pinmux = ;
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins2 {
+   pinmux = ;
+   bias-disable;
+   };
+   };
+};
+
+ {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
+   status = "okay";
+};
-- 
1.9.1

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Re: [PATCH 2/7] includes: dt-bindings: Add STM32F429 pinctrl DT bindings

[Maxime Coquelin]

2015-10-15 13:14 GMT+02:00 Daniel Thompson <daniel.thomp...@linaro.org>:
> On 14/10/15 21:07, Maxime Coquelin wrote:
>>
>> Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
>> ---
>>   include/dt-bindings/pinctrl/pinctrl-stm32.h |   12 +
>>   include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1241
>> +++
>>   2 files changed, 1253 insertions(+)
>>   create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h
>>   create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h
>>
>> diff --git a/include/dt-bindings/pinctrl/pinctrl-stm32.h
>> b/include/dt-bindings/pinctrl/pinctrl-stm32.h
>> new file mode 100644
>> index 000..a2e7222
>> --- /dev/null
>> +++ b/include/dt-bindings/pinctrl/pinctrl-stm32.h
>> @@ -0,0 +1,12 @@
>> +#ifndef _DT_BINDINGS_PINCTRL_STM32_H
>> +#define _DT_BINDINGS_PINCTRL_STM32_H
>> +
>> +#define STM32_PIN_NO(x) ((x) << 8)
>> +#define STM32_GET_PIN_NO(x) ((x) >> 8)
>> +#define STM32_GET_PIN_FUNC(x) ((x) & 0xff)
>> +
>> +#define STM32_PIN_GPIO 0
>> +#define STM32_PIN_AF(x)((x) + 1)
>> +#define STM32_PIN_ANALOG   (STM32_PIN_AF(15) + 1)
>> +
>> +#endif /* _DT_BINDINGS_PINCTRL_STM32_H */
>> diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
>> b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
>> new file mode 100644
>> index 000..979e4eb
>> --- /dev/null
>> +++ b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
>> @@ -0,0 +1,1241 @@
>> +#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H
>> +#define _DT_BINDINGS_STM32F429_PINFUNC_H
>> +
>> +#include 
>> +
>> +#define STM32F429_PA0_FUNC_GPIO (STM32_PIN_NO(0) | STM32_PIN_GPIO)
>> +#define STM32F429_PA0_FUNC_TIM2_CH1 TIM2_ETR (STM32_PIN_NO(0) |
>> STM32_PIN_AF(1))
>
>
> For the clock driver I was advised to get rid of this sort of "heroics" and
> expose raw numbers from the datasheet directly to DT bindings users.
>
> Should the same logic apply to this *huge* collection of macros?

I'm open to change, I just took example on the Mediatek implementation.
Advantage is that checkpatch will be more silent, drawback is that it
will be a little harder to understand how these values are generated.
If we decide to change to raw values, then the DT Bindings
documentation will need to be more verbose on the way these values are
generated.

Note that it will not be painful, as I can generate them from a script.

Regards,
Maxime
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Re: [PATCH 0/4] Enable Ethernet on StiH407 family boards

[Maxime Coquelin]

On 10/01/2015 05:56 PM, Maxime Coquelin wrote:

This series enables Ethernet support on STiH407 family reference design
boards.

These boards use the RTL8367 Switch as PHY.
As it is previously configured by the bootloader, we declare it as a fixed
link.

Maxime Coquelin (4):
   ARM: dts: Fix RGMII pinctrl timings
   ARM: dts: Add Ethernet node to STiH407 family
   ARM: dts: Enable Ethernet on STi's B2120 boards
   ARM: dts: Enable Ethernet on STi's B2199 board

  arch/arm/boot/dts/stih407-b2120.dts|  1 +
  arch/arm/boot/dts/stih407-family.dtsi  | 27 +++
  arch/arm/boot/dts/stih407-pinctrl.dtsi |  4 ++--
  arch/arm/boot/dts/stih410-b2120.dts|  1 +
  arch/arm/boot/dts/stih418-b2199.dts|  8 
  arch/arm/boot/dts/stihxxx-b2120.dtsi   |  6 ++
  6 files changed, 45 insertions(+), 2 deletions(-)


Series applied.

Maxime
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Re: [PATCH v2] ARM: DT: STi: STiH418: Fix mmc0 clock configuration

[Maxime Coquelin]

On 08/24/2015 04:23 PM, Gabriel Fernandez wrote:

This patch configure correctly the MMC-0 clock for STiH418 platform.

Signed-off-by: Gabriel Fernandez <gabriel.fernan...@linaro.org>
Acked-by: Maxime Coquelin <maxime.coque...@st.com>
---
  arch/arm/boot/dts/stih418.dtsi | 6 ++
  1 file changed, 6 insertions(+)



Applied, thanks.

Maxime
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Re: [PATCH 5/7] ARM: mach-stm32: Select pinctrl

[Maxime Coquelin]

Hi,

Commenting myself before someone else does...

On 10/14/2015 10:07 PM, Maxime Coquelin wrote:

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
  arch/arm/Kconfig  | 1 +
  drivers/pinctrl/stm32/pinctrl-stm32f429.c | 2 +-
  2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bf94e54..8b1afd4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -985,6 +985,7 @@ config ARCH_STM32
select ARMV7M_SYSTICK
select CLKSRC_STM32
select RESET_CONTROLLER
+   select PINCTRL

This is not in alphabetical order...


help
  Support for STMicroelectronics STM32 processors.

diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f429.c 
b/drivers/pinctrl/stm32/pinctrl-stm32f429.c
index 3535037..f34016b 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32f429.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f429.c
@@ -1564,7 +1564,7 @@ static const struct stm32_desc_pin stm32f429_pins[] = {
),
  };

-struct stm32_pinctrl_match_data stm32f429_match_data = {
+static struct stm32_pinctrl_match_data stm32f429_match_data = {
.pins = stm32f429_pins,
.npins = ARRAY_SIZE(stm32f429_pins),
  };



And I didn't fixed-up in the good patch... Should go in the driver one.

Will be fixed in the v2.

Maxime
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Re: [PATCH 0/3] hwrng: stm32 - add support for STM32 HW RNG

[Maxime Coquelin]

Herbert,

2015-10-14 16:28 GMT+02:00 Herbert Xu <herb...@gondor.apana.org.au>:
> On Mon, Oct 12, 2015 at 09:21:27AM +0100, Daniel Thompson wrote:
>> This patchset introduces a driver for the STM32 hardware random number
>> generator.
>>
>> v2:
>>
>>  * Moved binding docs from .../hwrng/ to .../rng/ and renamed to match
>>convention in new directory (Rob Herring).
>>  * Adopted runtime PM and auto-suspend instead of managing the clocks
>>from the read function (Linus Walleij). Increased bandwidth by ~30%.
>>  * Simplified error detection in main read loop (Linus Walleij, Maxime
>>Coquelin).
>>  * Only WARN_ONCE() when hardware failure mechanisms trigger (Maxime
>>Coquelin).
>>  * Simplify end of probe function after cocci warning (Fengguang Wu).
>>  * Switch to devm_hwrng_register.
>
> All applied.  Thanks!

I see you again have applied the DT patch like for STi three weeks ago.
The DT patch should go through the arm_soc tree to avoid Linus having
to handle conflicts resolution.

Can you please remove these two patches from your tree?
ba25d8b ARM: STi: STiH407: Enable the 2 HW Random Number Generators
for STiH4{07, 10}
b47c9fa ARM: dts: stm32f429: Adopt STM32 RNG driver

Thanks,
Maxime
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[PATCH 0/7] Add STM32 pinctrl/GPIO driver

[Maxime Coquelin]

Hi Linus, all,

As you suggested during the submission of the STM32 machine support,
I reworked the STM32 pinctrl driver to use the standardized pin config
bindings.

The STM32 family has 16 pins per GPIO bank, and the number of bank varies
depending on the model.

Pins can be multiplexed either in GPIO mode, alternate function (up to 15
functions per pin) or analog (for ADC/DAC).

Kind regards,
Maxime

Maxime Coquelin (7):
  ARM: Kconfig: Introduce MACH_STM32F429 flag
  includes: dt-bindings: Add STM32F429 pinctrl DT bindings
  Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings
  pinctrl: Add support STM32 MCUs
  ARM: mach-stm32: Select pinctrl
  ARM: dts: Add pinctrl node to STM32F429
  ARM: dts: Add USART1 pin config to STM32F429 boards

 .../bindings/pinctrl/st,stm32-pinctrl.txt  |  113 ++
 arch/arm/Kconfig   |6 +
 arch/arm/boot/dts/stm32429i-eval.dts   |2 +
 arch/arm/boot/dts/stm32f429-disco.dts  |2 +
 arch/arm/boot/dts/stm32f429.dtsi   |  110 ++
 drivers/pinctrl/Kconfig|1 +
 drivers/pinctrl/Makefile   |4 +-
 drivers/pinctrl/stm32/Kconfig  |   16 +
 drivers/pinctrl/stm32/Makefile |5 +
 drivers/pinctrl/stm32/pinctrl-stm32.c  |  856 +++
 drivers/pinctrl/stm32/pinctrl-stm32.h  |   43 +
 drivers/pinctrl/stm32/pinctrl-stm32f429.c  | 1598 
 include/dt-bindings/pinctrl/pinctrl-stm32.h|   12 +
 include/dt-bindings/pinctrl/stm32f429-pinfunc.h| 1241 +++
 14 files changed, 4008 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
 create mode 100644 drivers/pinctrl/stm32/Kconfig
 create mode 100644 drivers/pinctrl/stm32/Makefile
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h
 create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h

-- 
1.9.1

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[PATCH 1/7] ARM: Kconfig: Introduce MACH_STM32F429 flag

[Maxime Coquelin]

This patch introduces the MACH_STM32F429 to make possible to only select
STM32F429 pinctrl driver.

By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 72ad724..bf94e54 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -988,6 +988,11 @@ config ARCH_STM32
help
  Support for STMicroelectronics STM32 processors.
 
+config MACH_STM32F429
+   bool "STMicrolectronics STM32F429"
+   depends on ARCH_STM32
+   default y
+
 # Definitions to make life easier
 config ARCH_ACORN
bool
-- 
1.9.1

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[PATCH 4/7] pinctrl: Add support STM32 MCUs

[Maxime Coquelin]

This patch adds pinctrl and GPIO support to STMicroelectronic's STM32
family of MCUs.

While it only supports STM32F429 for now, it has been designed to enable
support of other MCUs of the family (e.g. STM32F746).

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 drivers/pinctrl/Kconfig   |1 +
 drivers/pinctrl/Makefile  |4 +-
 drivers/pinctrl/stm32/Kconfig |   16 +
 drivers/pinctrl/stm32/Makefile|5 +
 drivers/pinctrl/stm32/pinctrl-stm32.c |  856 +++
 drivers/pinctrl/stm32/pinctrl-stm32.h |   43 +
 drivers/pinctrl/stm32/pinctrl-stm32f429.c | 1598 +
 7 files changed, 2522 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pinctrl/stm32/Kconfig
 create mode 100644 drivers/pinctrl/stm32/Makefile
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.c
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32.h
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32f429.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 84dd2ed..5749cc4 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -249,6 +249,7 @@ source "drivers/pinctrl/sunxi/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
 source "drivers/pinctrl/vt8500/Kconfig"
 source "drivers/pinctrl/mediatek/Kconfig"
+source "drivers/pinctrl/stm32/Kconfig"
 
 config PINCTRL_XWAY
bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index cad077c..6112e91 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -51,5 +51,7 @@ obj-$(CONFIG_PINCTRL_SH_PFC)  += sh-pfc/
 obj-$(CONFIG_PLAT_SPEAR)   += spear/
 obj-$(CONFIG_ARCH_SUNXI)   += sunxi/
 obj-$(CONFIG_ARCH_UNIPHIER)+= uniphier/
-obj-$(CONFIG_ARCH_VT8500)  += vt8500/
 obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
+obj-$(CONFIG_ARCH_VT8500)  += vt8500/
+obj-$(CONFIG_ARCH_STM32)   += stm32/
+
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
new file mode 100644
index 000..0f28841
--- /dev/null
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -0,0 +1,16 @@
+if ARCH_STM32 || COMPILE_TEST
+
+config PINCTRL_STM32
+   bool
+   depends on OF
+   select PINMUX
+   select GENERIC_PINCONF
+   select GPIOLIB
+
+config PINCTRL_STM32F429
+   bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && 
!MACH_STM32F429
+   depends on OF
+   default MACH_STM32F429
+   select PINCTRL_STM32
+
+endif
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
new file mode 100644
index 000..fc17d42
--- /dev/null
+++ b/drivers/pinctrl/stm32/Makefile
@@ -0,0 +1,5 @@
+# Core
+obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_STM32F429)+= pinctrl-stm32f429.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c 
b/drivers/pinctrl/stm32/pinctrl-stm32.c
new file mode 100644
index 000..4ebceaa
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -0,0 +1,856 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.st...@gmail.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ *
+ * Heavily based on Mediatek's pinctrl driver
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-stm32.h"
+
+#define STM32_GPIO_MODER   0x00
+#define STM32_GPIO_TYPER   0x04
+#define STM32_GPIO_SPEEDR  0x08
+#define STM32_GPIO_PUPDR   0x0c
+#define STM32_GPIO_IDR 0x10
+#define STM32_GPIO_ODR 0x14
+#define STM32_GPIO_BSRR0x18
+#define STM32_GPIO_LCKR0x1c
+#define STM32_GPIO_AFRL0x20
+#define STM32_GPIO_AFRH0x24
+
+#define STM32_GPIO_PINS_PER_BANK 16
+
+#define gpio_range_to_bank(chip) \
+   container_of(chip, struct stm32_gpio_bank, range)
+
+#define gpio_chip_to_bank(chip) \
+   container_of(chip, struct stm32_gpio_bank, gpio_chip)
+
+static const char * const stm32_gpio_functions[] = {
+   "gpio", "af0", "af1",
+   "af2", "af3", "af4",
+   "af5", "af6", "af7",
+   "af8", "af9", "af10",
+   "af11", "af12", "af13",
+   "af14", "af15", "analog",
+};
+
+struct stm32_pinctrl_group {
+   const char *name;
+   unsigned long config;
+   unsigned pin;
+};
+
+struct stm32_gpio_bank {
+   void __iomem *base;
+   struct clk *clk;
+   spinlock_t lock;

[PATCH 5/7] ARM: mach-stm32: Select pinctrl

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/Kconfig  | 1 +
 drivers/pinctrl/stm32/pinctrl-stm32f429.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bf94e54..8b1afd4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -985,6 +985,7 @@ config ARCH_STM32
select ARMV7M_SYSTICK
select CLKSRC_STM32
select RESET_CONTROLLER
+   select PINCTRL
help
  Support for STMicroelectronics STM32 processors.
 
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f429.c 
b/drivers/pinctrl/stm32/pinctrl-stm32f429.c
index 3535037..f34016b 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32f429.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f429.c
@@ -1564,7 +1564,7 @@ static const struct stm32_desc_pin stm32f429_pins[] = {
),
 };
 
-struct stm32_pinctrl_match_data stm32f429_match_data = {
+static struct stm32_pinctrl_match_data stm32f429_match_data = {
.pins = stm32f429_pins,
.npins = ARRAY_SIZE(stm32f429_pins),
 };
-- 
1.9.1

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[PATCH 2/7] includes: dt-bindings: Add STM32F429 pinctrl DT bindings

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 include/dt-bindings/pinctrl/pinctrl-stm32.h |   12 +
 include/dt-bindings/pinctrl/stm32f429-pinfunc.h | 1241 +++
 2 files changed, 1253 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-stm32.h
 create mode 100644 include/dt-bindings/pinctrl/stm32f429-pinfunc.h

diff --git a/include/dt-bindings/pinctrl/pinctrl-stm32.h 
b/include/dt-bindings/pinctrl/pinctrl-stm32.h
new file mode 100644
index 000..a2e7222
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-stm32.h
@@ -0,0 +1,12 @@
+#ifndef _DT_BINDINGS_PINCTRL_STM32_H
+#define _DT_BINDINGS_PINCTRL_STM32_H
+
+#define STM32_PIN_NO(x) ((x) << 8)
+#define STM32_GET_PIN_NO(x) ((x) >> 8)
+#define STM32_GET_PIN_FUNC(x) ((x) & 0xff)
+
+#define STM32_PIN_GPIO 0
+#define STM32_PIN_AF(x)((x) + 1)
+#define STM32_PIN_ANALOG   (STM32_PIN_AF(15) + 1)
+
+#endif /* _DT_BINDINGS_PINCTRL_STM32_H */
diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h 
b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
new file mode 100644
index 000..979e4eb
--- /dev/null
+++ b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
@@ -0,0 +1,1241 @@
+#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H
+#define _DT_BINDINGS_STM32F429_PINFUNC_H
+
+#include 
+
+#define STM32F429_PA0_FUNC_GPIO (STM32_PIN_NO(0) | STM32_PIN_GPIO)
+#define STM32F429_PA0_FUNC_TIM2_CH1 TIM2_ETR (STM32_PIN_NO(0) | 
STM32_PIN_AF(1))
+#define STM32F429_PA0_FUNC_TIM5_CH1 (STM32_PIN_NO(0) | STM32_PIN_AF(2))
+#define STM32F429_PA0_FUNC_TIM8_ETR (STM32_PIN_NO(0) | STM32_PIN_AF(3))
+#define STM32F429_PA0_FUNC_USART2_CTS (STM32_PIN_NO(0) | STM32_PIN_AF(7))
+#define STM32F429_PA0_FUNC_UART4_TX (STM32_PIN_NO(0) | STM32_PIN_AF(8))
+#define STM32F429_PA0_FUNC_ETH_MII_CRS (STM32_PIN_NO(0) | STM32_PIN_AF(11))
+#define STM32F429_PA0_FUNC_EVENTOUT (STM32_PIN_NO(0) | STM32_PIN_AF(15))
+#define STM32F429_PA0_FUNC_ANALOG (STM32_PIN_NO(0) | STM32_PIN_ANALOG)
+
+#define STM32F429_PA1_FUNC_GPIO (STM32_PIN_NO(1) | STM32_PIN_GPIO)
+#define STM32F429_PA1_FUNC_TIM2_CH2 (STM32_PIN_NO(1) | STM32_PIN_AF(1))
+#define STM32F429_PA1_FUNC_TIM5_CH2 (STM32_PIN_NO(1) | STM32_PIN_AF(2))
+#define STM32F429_PA1_FUNC_USART2_RTS (STM32_PIN_NO(1) | STM32_PIN_AF(7))
+#define STM32F429_PA1_FUNC_UART4_RX (STM32_PIN_NO(1) | STM32_PIN_AF(8))
+#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK ETH_RMII_REF_CLK (STM32_PIN_NO(1) | 
STM32_PIN_AF(11))
+#define STM32F429_PA1_FUNC_EVENTOUT (STM32_PIN_NO(1) | STM32_PIN_AF(15))
+#define STM32F429_PA1_FUNC_ANALOG (STM32_PIN_NO(1) | STM32_PIN_ANALOG)
+
+#define STM32F429_PA2_FUNC_GPIO (STM32_PIN_NO(2) | STM32_PIN_GPIO)
+#define STM32F429_PA2_FUNC_TIM2_CH3 (STM32_PIN_NO(2) | STM32_PIN_AF(1))
+#define STM32F429_PA2_FUNC_TIM5_CH3 (STM32_PIN_NO(2) | STM32_PIN_AF(2))
+#define STM32F429_PA2_FUNC_TIM9_CH1 (STM32_PIN_NO(2) | STM32_PIN_AF(3))
+#define STM32F429_PA2_FUNC_USART2_TX (STM32_PIN_NO(2) | STM32_PIN_AF(7))
+#define STM32F429_PA2_FUNC_ETH_MDIO (STM32_PIN_NO(2) | STM32_PIN_AF(11))
+#define STM32F429_PA2_FUNC_EVENTOUT (STM32_PIN_NO(2) | STM32_PIN_AF(15))
+#define STM32F429_PA2_FUNC_ANALOG (STM32_PIN_NO(2) | STM32_PIN_ANALOG)
+
+#define STM32F429_PA3_FUNC_GPIO (STM32_PIN_NO(3) | STM32_PIN_GPIO)
+#define STM32F429_PA3_FUNC_TIM2_CH4 (STM32_PIN_NO(3) | STM32_PIN_AF(1))
+#define STM32F429_PA3_FUNC_TIM5_CH4 (STM32_PIN_NO(3) | STM32_PIN_AF(2))
+#define STM32F429_PA3_FUNC_TIM9_CH2 (STM32_PIN_NO(3) | STM32_PIN_AF(3))
+#define STM32F429_PA3_FUNC_USART2_RX (STM32_PIN_NO(3) | STM32_PIN_AF(7))
+#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 (STM32_PIN_NO(3) | STM32_PIN_AF(10))
+#define STM32F429_PA3_FUNC_ETH_MII_COL (STM32_PIN_NO(3) | STM32_PIN_AF(11))
+#define STM32F429_PA3_FUNC_LCD_B5 (STM32_PIN_NO(3) | STM32_PIN_AF(14))
+#define STM32F429_PA3_FUNC_EVENTOUT (STM32_PIN_NO(3) | STM32_PIN_AF(15))
+#define STM32F429_PA3_FUNC_ANALOG (STM32_PIN_NO(3) | STM32_PIN_ANALOG)
+
+#define STM32F429_PA4_FUNC_GPIO (STM32_PIN_NO(4) | STM32_PIN_GPIO)
+#define STM32F429_PA4_FUNC_SPI1_NSS (STM32_PIN_NO(4) | STM32_PIN_AF(5))
+#define STM32F429_PA4_FUNC_SPI3_NSS I2S3_WS (STM32_PIN_NO(4) | STM32_PIN_AF(6))
+#define STM32F429_PA4_FUNC_USART2_CK (STM32_PIN_NO(4) | STM32_PIN_AF(7))
+#define STM32F429_PA4_FUNC_OTG_HS_SOF (STM32_PIN_NO(4) | STM32_PIN_AF(12))
+#define STM32F429_PA4_FUNC_DCMI_HSYNC (STM32_PIN_NO(4) | STM32_PIN_AF(13))
+#define STM32F429_PA4_FUNC_LCD_VSYNC (STM32_PIN_NO(4) | STM32_PIN_AF(14))
+#define STM32F429_PA4_FUNC_EVENTOUT (STM32_PIN_NO(4) | STM32_PIN_AF(15))
+#define STM32F429_PA4_FUNC_ANALOG (STM32_PIN_NO(4) | STM32_PIN_ANALOG)
+
+#define STM32F429_PA5_FUNC_GPIO (STM32_PIN_NO(5) | STM32_PIN_GPIO)
+#define STM32F429_PA5_FUNC_TIM2_CH1 TIM2_ETR (STM32_PIN_NO(5) | 
STM32_PIN_AF(1))
+#define STM32F429_PA5_FUNC_TIM8_CH1N (STM32_PIN_NO(5) | STM32_PIN_AF(3))
+#define STM32F429_PA5_FUNC_SPI1_SCK (STM32_PIN_NO(5) | STM32_PIN_AF(5))
+#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK (STM32_PIN_NO(5) | STM3

[PATCH 7/7] ARM: dts: Add USART1 pin config to STM32F429 boards

[Maxime Coquelin]

This patch selects USART1 pin configuration on PA9/PA10 pins
for both Eval and Disco boards.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32429i-eval.dts  |  2 ++
 arch/arm/boot/dts/stm32f429-disco.dts |  2 ++
 arch/arm/boot/dts/stm32f429.dtsi  | 13 +
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/stm32429i-eval.dts 
b/arch/arm/boot/dts/stm32429i-eval.dts
index 6964fc9..71fe17a 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -71,5 +71,7 @@
 };
 
  {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
status = "okay";
 };
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts 
b/arch/arm/boot/dts/stm32f429-disco.dts
index f0b731d..e3ce796 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -71,5 +71,7 @@
 };
 
  {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
status = "okay";
 };
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 9e6e75c..eb3580e 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -263,6 +263,19 @@
clocks = < 0 266>;
st,bank-name = "GPIOK";
};
+
+   usart1_pins_a: usart1@0 {
+   pins1 {
+   pinmux = ;
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins2 {
+   pinmux = 
;
+   bias-disable;
+   };
+   };
};
 
rcc: rcc@40023810 {
-- 
1.9.1

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[PATCH 3/7] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings

[Maxime Coquelin]

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 .../bindings/pinctrl/st,stm32-pinctrl.txt  | 113 +
 1 file changed, 113 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
new file mode 100644
index 000..fe6df6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -0,0 +1,113 @@
+* STM32 GPIO and Pin Mux/Config controller
+
+STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
+controller. It controls the input/output settings on the available pins and
+also provides ability to multiplex and configure the output of various on-chip
+controllers onto these pads.
+
+Pin controller node:
+Required properies:
+ - compatible: value should be one of the following:
+   (a) "st,stm32f429-pinctrl"
+ - #address-cells: The value of this property must be 1
+ - #size-cells : The value of this property must be 1
+ - ranges  : defines mapping between pin controller node (parent) to
+   gpio-bank node (children).
+ - pins-are-numbered: Specify the subnodes are using numbered pinmux to
+   specify pins.
+
+GPIO controller/bank node:
+Required properties:
+ - gpio-controller : Indicates this device is a GPIO controller
+ - #gpio-cells   : Should be two.
+   The first cell is the pin number
+   The second one is the polarity:
+   - 0 for active high
+   - 1 for active low
+ - reg   : The gpio address range, relative to the pinctrl range
+ - clocks: clock that drives this bank
+ - st,bank-name  : Should be a name string for this bank as specified 
in
+   the datasheet
+
+Optional properties:
+ - reset:: Reference to the reset controller
+
+Example:
+#include 
+...
+
+   pin-controller {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,stm32f429-pinctrl";
+   ranges = <0 0x4002 0x3000>;
+   pins-are-numbered;
+
+   gpioa: gpio@4002 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x0 0x400>;
+   resets = <_ahb1 0>;
+   st,bank-name = "GPIOA";
+   };
+   ...
+   pin-functions nodes follow...
+   };
+
+Contents of function subnode node:
+--
+Subnode format
+A pinctrl node should contain at least one subnode representing the
+pinctrl group available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, pullups, drive, output high/low and output speed.
+
+node {
+   pinmux = ;
+   GENERIC_PINCONFIG;
+};
+
+Required properties:
+- pinmux: integer array, represents gpio pin number and mux setting.
+Supported pin number and mux varies for different SoCs, and are defined
+as macros in dt-bindings/pinctrl/-pinfunc.h directly.
+
+Optional properties:
+- GENERIC_PINCONFIG: is the generic pinconfig options to use.
+  Available options are:
+   - bias-disable,
+   - bias-pull-down,
+   - bias-pull-up,
+   - drive-push-pull,
+   - drive-open-drain,
+   - output-low
+   - output-high
+   - slew-rate = , with x being:
+   < 0 > : Low speed
+   < 1 > : Medium speed
+   < 2 > : Fast speed
+   < 3 > : High speed
+
+Example:
+
+pin-controller {
+...
+   usart1_pins_a: usart1@0 {
+   pins1 {
+   pinmux = ;
+   bias-disable;
+   drive-push-pull;
+   slew-rate = <0>;
+   };
+   pins2 {
+   pinmux = ;
+   bias-disable;
+   };
+   };
+};
+
+ {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
+   status = "okay";
+};
-- 
1.9.1

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[PATCH 6/7] ARM: dts: Add pinctrl node to STM32F429

[Maxime Coquelin]

The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank.

Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
---
 arch/arm/boot/dts/stm32f429.dtsi | 97 
 1 file changed, 97 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index d78a481..9e6e75c 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -46,6 +46,7 @@
  */
 
 #include "armv7-m.dtsi"
+#include 
 
 / {
clocks {
@@ -168,6 +169,102 @@
status = "disabled";
};
 
+   pin-controller {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "st,stm32f429-pinctrl";
+   ranges = <0 0x4002 0x3000>;
+   pins-are-numbered;
+
+   gpioa: gpio@4002 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x0 0x400>;
+   clocks = < 0 256>;
+   st,bank-name = "GPIOA";
+   };
+
+   gpiob: gpio@40020400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x400 0x400>;
+   clocks = < 0 257>;
+   st,bank-name = "GPIOB";
+   };
+
+   gpioc: gpio@40020800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x800 0x400>;
+   clocks = < 0 258>;
+   st,bank-name = "GPIOC";
+   };
+
+   gpiod: gpio@40020c00 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0xc00 0x400>;
+   clocks = < 0 259>;
+   st,bank-name = "GPIOD";
+   };
+
+   gpioe: gpio@40021000 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1000 0x400>;
+   clocks = < 0 260>;
+   st,bank-name = "GPIOE";
+   };
+
+   gpiof: gpio@40021400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1400 0x400>;
+   clocks = < 0 261>;
+   st,bank-name = "GPIOF";
+   };
+
+   gpiog: gpio@40021800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1800 0x400>;
+   clocks = < 0 262>;
+   st,bank-name = "GPIOG";
+   };
+
+   gpioh: gpio@40021c00 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x1c00 0x400>;
+   clocks = < 0 263>;
+   st,bank-name = "GPIOH";
+   };
+
+   gpioi: gpio@40022000 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2000 0x400>;
+   clocks = < 0 264>;
+   st,bank-name = "GPIOI";
+   };
+
+   gpioj: gpio@40022400 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2400 0x400>;
+   clocks = < 0 265>;
+   st,bank-name = "GPIOJ";
+   };
+
+   gpiok: gpio@40022800 {
+   gpio-controller;
+   #gpio-cells = <2>;
+   reg = <0x2800 0x400>;
+   clocks = < 0 266>;
+   st,bank-name = "GPIOK";
+   };
+   };
+
rcc: rcc@40023810 {
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
-- 
1.9.1

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Re: [PATCH 1/4] dt-bindings: Document the STM32 DMA bindings

[Maxime Coquelin]

Hi Cedric,

On 10/08/2015 05:20 PM, M'boumba Cedric Madianga wrote:

This patch adds documentation of device tree bindings for the STM32 dma
controller.

Signed-off-by: M'boumba Cedric Madianga <cedric.madia...@gmail.com>
---
  .../devicetree/bindings/dma/stm32-dma.txt  | 98 ++
  1 file changed, 98 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/dma/stm32-dma.txt



Acked-by: Maxime Coquelin <maxime.coque...@st.com>

Thanks!
Maxime
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Re: [PATCH 2/4] dmaengine: Add STM32 DMA driver

[Maxime Coquelin]

Hi Cedric,

On 10/08/2015 05:20 PM, M'boumba Cedric Madianga wrote:

This patch adds support for the STM32 DMA controller.

Signed-off-by: M'boumba Cedric Madianga 
---
  drivers/dma/Kconfig |   12 +
  drivers/dma/Makefile|1 +
  drivers/dma/stm32-dma.c | 1193 +++
  3 files changed, 1206 insertions(+)
  create mode 100644 drivers/dma/stm32-dma.c

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 5c931d4..4c6b37b 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -431,6 +431,18 @@ config STE_DMA40
help
  Support for ST-Ericsson DMA40 controller

+config STM32_DMA
+   tristate "STMicroelectronics STM32 dma support"

s/dma/DMA/ ?


diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
new file mode 100644
index 000..9814ca5
--- /dev/null
+++ b/drivers/dma/stm32-dma.c
@@ -0,0 +1,1193 @@



+#define STM32_DMA_LISR 0x /* DMA Low Int Status Reg */
+#define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */
+#define STM32_DMA_LIFCR0x0008 /* DMA Low Int Flag 
Clear Reg */
+#define STM32_DMA_HIFCR0x000C /* DMA High Int Flag 
Clear Reg */

We usually use lower case for numerical values.


+static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
+   enum dma_transfer_direction direction,
+   enum dma_slave_buswidth *buswidth)
+{
+   enum dma_slave_buswidth src_addr_width, dst_addr_width;
+   u32 src_bus_width, dst_bus_width, src_burst_size, dst_burst_size;
+   u32 src_maxburst, dst_maxburst;
+   dma_addr_t src_addr, dst_addr;
+
+   src_addr_width = chan->dma_sconfig.src_addr_width;
+   dst_addr_width = chan->dma_sconfig.dst_addr_width;
+   src_maxburst = chan->dma_sconfig.src_maxburst;
+   dst_maxburst = chan->dma_sconfig.dst_maxburst;
+   src_addr = chan->dma_sconfig.src_addr;
+   dst_addr = chan->dma_sconfig.dst_addr;
+
+   switch (direction) {
+   case DMA_MEM_TO_DEV:
+   dst_bus_width = stm32_get_dma_width(chan, dst_addr_width);
+   if (dst_bus_width < 0)
+   return -EINVAL;

dst_bus_width is a u32, so cannot be negative.
Also, you should propagate de error returned by stm32_get_dma_width().

The comment also applies below:

+   dst_burst_size = stm32_get_dma_burst(chan, dst_maxburst);
+   if (dst_burst_size < 0)
+   return -EINVAL;
+   if (!src_addr_width)
+   src_addr_width = dst_addr_width;
+   src_bus_width = stm32_get_dma_width(chan, src_addr_width);
+   if (src_bus_width < 0)
+   return -EINVAL;
+   src_burst_size = stm32_get_dma_burst(chan, src_maxburst);
+   if (src_burst_size < 0)
+   return -EINVAL;
+
+   chan->chan_reg.dma_scr |= (chan->chan_reg.dma_scr &
+   ~(STM32_DMA_SCR_DIR_MASK | STM32_DMA_SCR_PSIZE_MASK |
+   STM32_DMA_SCR_MSIZE_MASK | STM32_DMA_SCR_PBURST_MASK |
+   STM32_DMA_SCR_MBURST_MASK)) |
+   STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) |
+   STM32_DMA_SCR_PSIZE(dst_bus_width) |
+   STM32_DMA_SCR_MSIZE(src_bus_width) |
+   STM32_DMA_SCR_PBURST(dst_burst_size) |
+   STM32_DMA_SCR_MBURST(src_burst_size);
+
+   chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
+   *buswidth = dst_addr_width;
+   return 0;
+
+   case DMA_DEV_TO_MEM:
+   src_bus_width = stm32_get_dma_width(chan, src_addr_width);
+   if (src_bus_width < 0)
+   return -EINVAL;
+   src_burst_size = stm32_get_dma_burst(chan, src_maxburst);
+   if (src_burst_size < 0)
+   return -EINVAL;
+   if (!dst_addr_width)
+   dst_addr_width = src_addr_width;
+   dst_bus_width = stm32_get_dma_width(chan, dst_addr_width);
+   if (dst_bus_width < 0)
+   return -EINVAL;
+   dst_burst_size = stm32_get_dma_burst(chan, dst_maxburst);
+   if (dst_burst_size < 0)
+   return -EINVAL;
+
+   chan->chan_reg.dma_scr |= (chan->chan_reg.dma_scr &
+   ~(STM32_DMA_SCR_DIR_MASK | STM32_DMA_SCR_PSIZE_MASK |
+   STM32_DMA_SCR_MSIZE_MASK | STM32_DMA_SCR_PBURST_MASK |
+   STM32_DMA_SCR_MBURST_MASK)) |
+   STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) |
+   STM32_DMA_SCR_PSIZE(src_bus_width) |
+   STM32_DMA_SCR_MSIZE(dst_bus_width) |
+   

Re: [PATCH 4/4] ARM: configs: Add STM32 DMA support in STM32 defconfig

[Maxime Coquelin]

On 10/08/2015 05:20 PM, M'boumba Cedric Madianga wrote:

This patch adds STM32 DMA support in stm32_defconfig file

Signed-off-by: M'boumba Cedric Madianga <cedric.madia...@gmail.com>
---
  arch/arm/configs/stm32_defconfig | 2 ++
  1 file changed, 2 insertions(+)



Acked-by: Maxime Coquelin <mcoquelin.st...@gmail.com>

I will apply it to my tree as soon as the driver is accepted.

Thanks,
Maxime
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Re: [PATCH 1/3] dt-bindings: Document the STM32 HW RNG bindings

[Maxime Coquelin]

Hi Daniel,

On 10/03/2015 10:35 PM, Daniel Thompson wrote:

This adds documenttaion of device tree binds for the STM32 hardware

s/documenttaion/documentation/

random number generator.

Signed-off-by: Daniel Thompson <daniel.thomp...@linaro.org>
---
  .../devicetree/bindings/hwrng/stm32-rng.txt | 21 +
  1 file changed, 21 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/hwrng/stm32-rng.txt


Except the typo, the patch looks good to me.
When fixed, you can add my:
Acked-by: Maxime Coquelin <mcoquelin.st...@gmail.com>

Thanks!
Maxime
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Re: [PATCH 2/3] hwrng: stm32 - add support for STM32 HW RNG

[Maxime Coquelin]

Hi Daniel,

On 10/03/2015 10:35 PM, Daniel Thompson wrote:

Add support for STMicroelectronics STM32 random number generator.

The config value defaults to N, reflecting the fact that STM32 is a
very low resource microcontroller platform and unlikely to be targeted
by any "grown up" defconfigs.

Signed-off-by: Daniel Thompson 
---
  drivers/char/hw_random/Kconfig |  12 +++
  drivers/char/hw_random/Makefile|   1 +
  drivers/char/hw_random/stm32-rng.c | 192 +
  3 files changed, 205 insertions(+)
  create mode 100644 drivers/char/hw_random/stm32-rng.c



diff --git a/drivers/char/hw_random/stm32-rng.c 
b/drivers/char/hw_random/stm32-rng.c
new file mode 100644
index ..37dfa5fca105
--- /dev/null
+++ b/drivers/char/hw_random/stm32-rng.c
@@ -0,0 +1,192 @@



+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define RNG_CR 0x00
+#define RNG_CR_RNGEN BIT(2)
+
+#define RNG_SR 0x04
+#define RNG_SR_SEIS BIT(6)
+#define RNG_SR_CEIS BIT(5)
+#define RNG_SR_DRDY BIT(0)
+
+#define RNG_DR 0x08
+
+/*
+ * It takes 40 cycles @ 48MHz to generate each random number (e.g. <1us).
+ * At the time of writing STM32 parts max out at ~200MHz meaning a timeout
+ * of 500 leaves us a very comfortable margin for error. The loop to which
+ * the timeout applies takes at least 4 instructions per cycle so the
+ * timeout is enough to take us up to multi-GHz parts!
+ */
+#define RNG_TIMEOUT 500
+
+struct stm32_rng_private {
+   struct hwrng rng;
+   void __iomem *base;
+   struct clk *clk;
+};
+
+static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
+{
+   struct stm32_rng_private *priv =
+   container_of(rng, struct stm32_rng_private, rng);
+   u32 cr, sr;
+   int retval = 0;
+
+   /* enable random number generation */
+   clk_enable(priv->clk);
+   cr = readl(priv->base + RNG_CR);
+   writel(cr | RNG_CR_RNGEN, priv->base + RNG_CR);
+
+   while (max > sizeof(u32)) {
+   sr = readl(priv->base + RNG_SR);
+   if (!sr && wait) {
+   unsigned int timeout = RNG_TIMEOUT;
+
+   do {
+   cpu_relax();
+   sr = readl(priv->base + RNG_SR);
+   } while (!sr && --timeout);
+   }
+
+   /* Has h/ware error dection been triggered? */
+   if (WARN_ON(sr & (RNG_SR_SEIS | RNG_SR_CEIS)))

Maybe you should instead use WARN_ONCE?
Because from what I understand in the datasheet, CEIS bit indicates and 
error with clock configuration.
If that happens, it is likely the same error will occur each time this 
function will be called.



+   break;
+
+   /* No data ready... */
+   if (!sr)
+   break;
Maybe you could perform this check before the error detection, as if 
!sr, the HW error condition will be always false.

+
+   *(u32 *)data = readl(priv->base + RNG_DR);
+
+   retval += sizeof(u32);
+   data += sizeof(u32);
+   max -= sizeof(u32);
+   }
+
+   /* disable the generator */
+   writel(cr, priv->base + RNG_CR);
+   clk_disable(priv->clk);
+
+   return retval || !wait ? retval : -EIO;
+}


Couldn't we use "_relaxed" versions of readl/writel?
I might save some not needed barriers.


+static int stm32_rng_probe(struct platform_device *ofdev)
+{
+   struct device *dev = >dev;
+   struct device_node *np = ofdev->dev.of_node;
+   struct stm32_rng_private *priv;
+   struct resource res;
+   int err;
+
+   priv = devm_kzalloc(dev, sizeof(struct stm32_rng_private), GFP_KERNEL);
+   if (!priv)
+   return -ENOMEM;
+
+   err = of_address_to_resource(np, 0, );
+   if (err)
+   return err;
+
+   priv->base = devm_ioremap_resource(dev, );
+   if (IS_ERR(priv->base))
+   return PTR_ERR(priv->base);
+
+   priv->clk = devm_clk_get(>dev, NULL);
+   if (IS_ERR(priv->clk))
+   return PTR_ERR(priv->clk);
+
+   dev_set_drvdata(dev, priv);
+
+   priv->rng.name = dev_driver_string(dev),
+   priv->rng.init = stm32_rng_init,
+   priv->rng.cleanup = stm32_rng_cleanup,
+   priv->rng.read = stm32_rng_read,
+   priv->rng.priv = (unsigned long) dev;
+
+   err = hwrng_register(>rng);
+   if (err)
+   return err;
+
+   return 0;

As detected with Coccinelle by Fengguang build system, you could simplify:
return hwrng_register(>rng);

Regards,
Maxime
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Re: [PATCH 3/3] ARM: dts: stm32f429: Adopt STM32 RNG driver

[Maxime Coquelin]

Hi Daniel,

On 10/03/2015 10:35 PM, Daniel Thompson wrote:

New bindings and driver have been created for STM32 series parts. This
patch integrates this changes.

Signed-off-by: Daniel Thompson <daniel.thomp...@linaro.org>
---
  arch/arm/boot/dts/stm32f429.dtsi | 7 +++
  1 file changed, 7 insertions(+)



Acked-by: Maxime Coquelin <mcoquelin.st...@gmail.com>

I will queue it to STM32 tree as soon as the DT bindings are accepted.

Thanks,
Maxime
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Re: [PATCH v2 4/4] ARM: STi: DT: Add support for stih418 A9 pll

[Maxime Coquelin]

On 10/02/2015 09:32 PM, Stephen Boyd wrote:

On 08/24, Gabriel Fernandez wrote:

Add support for new PLL-type for stih418 A9-PLL.

Signed-off-by: Gabriel Fernandez 
---

I assume this will go through arm-soc?


Yes, I will take it through STi tree.

Thanks,
Maxime
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Re: [STLinux Kernel] [PATCH v2 6/7] ARM: STi: STiH407: Enable the 2 HW Random Number Generators for STiH4{07, 10}

[Maxime Coquelin]

Hi Lee, Herbert,

On 09/17/2015 03:45 PM, Lee Jones wrote:

Signed-off-by: Lee Jones 
---
  arch/arm/boot/dts/stih407-family.dtsi | 14 ++
  1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi 
b/arch/arm/boot/dts/stih407-family.dtsi
index 838b812..9452b42 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -565,5 +565,19 @@
  <_port2 PHY_TYPE_USB3>;
};
};
+
+   rng10: rng@08a89000 {
+   compatible  = "st,rng";
+   reg = <0x08a89000 0x1000>;
+   clocks  = <_sysin>;
+   status  = "okay";
+   };
+
+   rng11: rng@08a8a000 {
+   compatible  = "st,rng";
+   reg = <0x08a8a000 0x1000>;
+   clocks  = <_sysin>;
+   status  = "okay";
+   };
};
  };


Patch applied to STi tree (sti-dt-for-v4.4).

Thanks,
Maxime
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[PATCH 2/4] ARM: dts: Add Ethernet node to STiH407 family

[Maxime Coquelin]

STiH407 family uses the Synopsys IP.

Signed-off-by: Maxime Coquelin <maxime.coque...@st.com>
---
 arch/arm/boot/dts/stih407-family.dtsi | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi 
b/arch/arm/boot/dts/stih407-family.dtsi
index 582154b..c944d3a 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -653,5 +653,32 @@
clocks  = <_sysin>;
status  = "okay";
};
+
+   ethernet0: dwmac@963 {
+   device_type = "network";
+   status = "disabled";
+   compatible = "st,stih407-dwmac", "snps,dwmac", 
"snps,dwmac-3.710";
+   reg = <0x963 0x8000>, <0x80 0x4>;
+   reg-names = "stmmaceth", "sti-ethconf";
+
+   st,syscon = <_sbc_reg 0x80>;
+   st,gmac_en;
+   resets = < STIH407_ETH1_SOFTRESET>;
+   reset-names = "stmmaceth";
+
+   interrupts = ,
+;
+   interrupt-names = "macirq", "eth_wake_irq";
+
+   /* DMA Bus Mode */
+   snps,pbl = <8>;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <_rgmii1>;
+
+   clock-names = "stmmaceth", "sti-ethclk";
+   clocks = <_s_c0_flexgen CLK_EXT2F_A9>,
+<_s_c0_flexgen CLK_ETH_PHY>;
+   };
};
 };
-- 
1.9.1

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[PATCH 0/4] Enable Ethernet on StiH407 family boards

[Maxime Coquelin]

This series enables Ethernet support on STiH407 family reference design
boards.

These boards use the RTL8367 Switch as PHY.
As it is previously configured by the bootloader, we declare it as a fixed
link.

Maxime Coquelin (4):
  ARM: dts: Fix RGMII pinctrl timings
  ARM: dts: Add Ethernet node to STiH407 family
  ARM: dts: Enable Ethernet on STi's B2120 boards
  ARM: dts: Enable Ethernet on STi's B2199 board

 arch/arm/boot/dts/stih407-b2120.dts|  1 +
 arch/arm/boot/dts/stih407-family.dtsi  | 27 +++
 arch/arm/boot/dts/stih407-pinctrl.dtsi |  4 ++--
 arch/arm/boot/dts/stih410-b2120.dts|  1 +
 arch/arm/boot/dts/stih418-b2199.dts|  8 
 arch/arm/boot/dts/stihxxx-b2120.dtsi   |  6 ++
 6 files changed, 45 insertions(+), 2 deletions(-)

-- 
1.9.1

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[PATCH 4/4] ARM: dts: Enable Ethernet on STi's B2199 board

[Maxime Coquelin]

The B2199 board is mounted with Realtek RTL8367 switch.
We consider the bootloader will have intiliazed the switch before jumping into
the kernel, so we declare it as a fixed link.

Signed-off-by: Maxime Coquelin <maxime.coque...@st.com>
---
 arch/arm/boot/dts/stih418-b2199.dts | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/stih418-b2199.dts 
b/arch/arm/boot/dts/stih418-b2199.dts
index 82eee39..772d2bb 100644
--- a/arch/arm/boot/dts/stih418-b2199.dts
+++ b/arch/arm/boot/dts/stih418-b2199.dts
@@ -24,6 +24,7 @@
 
aliases {
ttyAS0 = _serial0;
+   ethernet0 = 
};
 
soc {
@@ -101,5 +102,12 @@
st_dwc3: dwc3@8f94000 {
status = "okay";
};
+
+   ethernet0: dwmac@963 {
+   st,tx-retime-src = "clkgen";
+   status = "okay";
+   phy-mode = "rgmii";
+   fixed-link = <0 1 1000 0 0>;
+   };
};
 };
-- 
1.9.1

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[PATCH 3/4] ARM: dts: Enable Ethernet on STi's B2120 boards

[Maxime Coquelin]

These boards are mounted with Realtek RTL8367 switch.
We consider the bootloader will have intiliazed the switch before jumping into
the kernel, so we declare it as a fixed link.

Signed-off-by: Maxime Coquelin <maxime.coque...@st.com>
---
 arch/arm/boot/dts/stih407-b2120.dts  | 1 +
 arch/arm/boot/dts/stih410-b2120.dts  | 1 +
 arch/arm/boot/dts/stihxxx-b2120.dtsi | 6 ++
 3 files changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-b2120.dts 
b/arch/arm/boot/dts/stih407-b2120.dts
index 6d93475..c8ad905 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -25,6 +25,7 @@
 
aliases {
ttyAS0 = _serial0;
+   ethernet0 = 
};
 
 };
diff --git a/arch/arm/boot/dts/stih410-b2120.dts 
b/arch/arm/boot/dts/stih410-b2120.dts
index 8af1e73..118ac28 100644
--- a/arch/arm/boot/dts/stih410-b2120.dts
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -25,6 +25,7 @@
 
aliases {
ttyAS0 = _serial0;
+   ethernet0 = 
};
 
soc {
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi 
b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index ab029f7..ad21a42 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -87,5 +87,11 @@
status = "okay";
};
 
+   ethernet0: dwmac@963 {
+   st,tx-retime-src = "clkgen";
+   status = "okay";
+   phy-mode = "rgmii";
+   fixed-link = <0 1 1000 0 0>;
+   };
};
 };
-- 
1.9.1

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[PATCH 1/4] ARM: dts: Fix RGMII pinctrl timings

[Maxime Coquelin]

These new re-timing values provides a better stability on Ethernet link.

Signed-off-by: Maxime Coquelin <maxime.coque...@st.com>
---
 arch/arm/boot/dts/stih407-pinctrl.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi 
b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 8fe542a..a538ae5 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -216,9 +216,9 @@
rxd2 = < 6 ALT1 IN DE_IO 0 
CLK_A>;
rxd3 = < 7 ALT1 IN DE_IO 0 
CLK_A>;
rxdv = < 0 ALT1 IN DE_IO 0 
CLK_A>;
-   rxclk = < 2 ALT1 IN NICLK 
500 CLK_A>;
+   rxclk = < 2 ALT1 IN NICLK 
0 CLK_A>;
clk125 = < 7 ALT4 IN NICLK 
0 CLK_A>;
-   phyclk = < 3 ALT4 OUT 
NICLK 1750 CLK_B>;
+   phyclk = < 3 ALT4 OUT 
NICLK 1250 CLK_B>;
};
};
 
-- 
1.9.1

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Re: [PATCH v2 00/11] Hi Maxime / Patrice / Srini,

[Maxime Coquelin]

Hi Peter,

On 09/28/2015 02:37 PM, Peter Griffin wrote:

This series makes a series of updates to the stih407 pinctrl groups
and makes the upstream kernel more closely aligned in terms of pin
configuration to the vendor kernel.

A number of new periphs are added such as spi fsm, nand, cec0, and
for others such as SPI the various alternate function pin muxings have
been added. Finally for SPI the controller nodes have been updated
to have the default pin assignment in the controller node.

Changes since v1:
  - Rebase on v4.3-rc3
  - Remove some SoBs (Lee)
  - Collect up Acks

kind regards,

Peter.

Peter Griffin (11):
   ARM: STi: DT: STiH407: Add a cec0 pin definition
   ARM: STi: DT: STiH407: Add i2c3 alternate pin configs
   ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs
   ARM: DT: STiH407: Add serial3 pinctrl configuration
   ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin config
   ARM: DT: STiH407: Add NAND flash controller pin configuration
   ARM: DT: STiH407: Add systrace pin configuration
   ARM: DT: STiH407: Add SD pinctrl config for mmc0 controller
   ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX
   ARM: DT: STiH407: Add RMII pinctrl support
   ARM: STi: STiH407: Add spi default pinctrl groups.

  arch/arm/boot/dts/stih407-family.dtsi  |  14 ++
  arch/arm/boot/dts/stih407-pinctrl.dtsi | 378 -
  2 files changed, 387 insertions(+), 5 deletions(-)



Series applied to sti-dt-for-v4.4.
Thanks!
Maxime
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Re: [PATCH 0/3] ARM: dts: Various STi DT clean-ups

[Maxime Coquelin]

On 09/23/2015 09:37 PM, Maxime Coquelin wrote:

This series cleans the STi407 family DTs, by factorizing common nodes between
STiH407 and STiH410, and also by only enabling PWM and USB nodes at board
level, as they could not be exposed on some boards.

Maxime Coquelin (3):
   ARM: dts: stih407: Enable PWM nodes only board level
   ARM: dts: stih407/410: Tidy up display nodes
   ARM: dts: stih410: Enable USB2.0 and related PHY nodes at board level

  arch/arm/boot/dts/stih407-family.dtsi | 19 +--
  arch/arm/boot/dts/stih407.dtsi| 13 -
  arch/arm/boot/dts/stih410-b2120.dts   | 24 
  arch/arm/boot/dts/stih410.dtsi| 23 +++
  arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 
  5 files changed, 60 insertions(+), 27 deletions(-)


Thanks for the reviews.
Series applied to sti-dt-for-v4.4

Regards,
Maxime
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Re: [PATCH] ARM: STi: DT: STiH407: Rename incorrect interrupt related binding

[Maxime Coquelin]

Hi Lee,

On 09/29/2015 10:52 AM, Lee Jones wrote:

interrupts-names => interrupt-names

Signed-off-by: Lee Jones 
---
  arch/arm/boot/dts/stih407-pinctrl.dtsi | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)




Good spot!
Applied to sti-dt-for-v4.4.

thanks,
Maxime
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Re: [STLinux Kernel] [PATCH v2 0/7] hwrng: Add support for STMicroelectronics' RNG IP

[Maxime Coquelin]

On 09/30/2015 04:28 PM, Herbert Xu wrote:

On Wed, Sep 30, 2015 at 03:15:39PM +0100, Lee Jones wrote:

I prefer not to merge patches that cannot be tested.  Without
the DT bits in patch 6 the other five patches are useless.  So
I think patch 6 should be applied together with the other five
which add the driver.

That's crazy talk.  If all subsystem maintainers abide by this rule
there would be chaos.  We'd either need to send pull-requests to each
other for every set which crossed a subsystems boundary, or 1000's of
merge conflicts would ensue at merge time.

The (sensible) rule we normally stick to is; as long as there isn't
a _build_ dependency, then the patches should filter though their
respective trees; _functional_ dependencies have nothing to do with
us as maintainers.  Another chaos preventing rule we abide by is; thou
shalt not apply patches belonging to other maintainer's subsystems
without the appropriate Ack-by and a subsequent "you may take this
though your tree" and/or "please send me an immutable pull-request".

So you want the series to be merged in two parts via two different
trees where neither can be tested? That sounds crazy to me.



Yes, that's what we want, and that's how people work usually.
I will repeat what Lee was saying, what we have to ensure as maintainer 
is that our tree is building.

We will be able to test it with linux-next.

Regards,
Maxime


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Re: [STLinux Kernel] [PATCH 3/3] ARM: dts: stih410: Enable USB2.0 and related PHY nodes at board level

[Maxime Coquelin]

On 09/24/2015 08:58 AM, Patrice Chotard wrote:

Hi Max

On 09/23/2015 09:37 PM, Maxime Coquelin wrote:
A borad might not expose the USB2.0 ports, so disable them by default 
in SoC


typo borad

Otherwise, for the series

Acked-by: Patrice Chotard <patrice.chot...@st.com>



Thanks Patrice, I will fix the typo before sending the pull request.

Regards,
Maxime
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[PATCH 0/3] ARM: dts: Various STi DT clean-ups

[Maxime Coquelin]

This series cleans the STi407 family DTs, by factorizing common nodes between
STiH407 and STiH410, and also by only enabling PWM and USB nodes at board
level, as they could not be exposed on some boards.

Maxime Coquelin (3):
  ARM: dts: stih407: Enable PWM nodes only board level
  ARM: dts: stih407/410: Tidy up display nodes
  ARM: dts: stih410: Enable USB2.0 and related PHY nodes at board level

 arch/arm/boot/dts/stih407-family.dtsi | 19 +--
 arch/arm/boot/dts/stih407.dtsi| 13 -
 arch/arm/boot/dts/stih410-b2120.dts   | 24 
 arch/arm/boot/dts/stih410.dtsi| 23 +++
 arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 
 5 files changed, 60 insertions(+), 27 deletions(-)

-- 
1.9.1

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[PATCH 3/3] ARM: dts: stih410: Enable USB2.0 and related PHY nodes at board level

[Maxime Coquelin]

A borad might not expose the USB2.0 ports, so disable them by default in SoC
file, and enable them in b2120 board.

Signed-off-by: Maxime Coquelin <maxime.coque...@st.com>
---
 arch/arm/boot/dts/stih410-b2120.dts | 24 
 arch/arm/boot/dts/stih410.dtsi  | 12 
 2 files changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/stih410-b2120.dts 
b/arch/arm/boot/dts/stih410-b2120.dts
index 16f02c5..8af1e73 100644
--- a/arch/arm/boot/dts/stih410-b2120.dts
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -35,5 +35,29 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+   usb2_picophy1: phy2 {
+   status = "okay";
+   };
+
+   usb2_picophy2: phy3 {
+   status = "okay";
+   };
+
+   ohci0: usb@9a03c00 {
+   status = "okay";
+   };
+
+   ehci0: usb@9a03e00 {
+   status = "okay";
+   };
+
+   ohci1: usb@9a83c00 {
+   status = "okay";
+   };
+
+   ehci1: usb@9a83e00 {
+   status = "okay";
+   };
};
 };
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 23f4a48..e3150e3 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -22,6 +22,8 @@
resets = < STIH407_PICOPHY_SOFTRESET>,
 < STIH407_PICOPHY0_RESET>;
reset-names = "global", "port";
+
+   status = "disabled";
};
 
usb2_picophy2: phy3 {
@@ -31,6 +33,8 @@
resets = < STIH407_PICOPHY_SOFTRESET>,
 < STIH407_PICOPHY1_RESET>;
reset-names = "global", "port";
+
+   status = "disabled";
};
 
ohci0: usb@9a03c00 {
@@ -43,6 +47,8 @@
reset-names = "power", "softreset";
phys = <_picophy1>;
phy-names = "usb";
+
+   status = "disabled";
};
 
ehci0: usb@9a03e00 {
@@ -57,6 +63,8 @@
reset-names = "power", "softreset";
phys = <_picophy1>;
phy-names = "usb";
+
+   status = "disabled";
};
 
ohci1: usb@9a83c00 {
@@ -69,6 +77,8 @@
reset-names = "power", "softreset";
phys = <_picophy2>;
phy-names = "usb";
+
+   status = "disabled";
};
 
ehci1: usb@9a83e00 {
@@ -83,6 +93,8 @@
reset-names = "power", "softreset";
phys = <_picophy2>;
phy-names = "usb";
+
+   status = "disabled";
};
 
sti-display-subsystem {
-- 
1.9.1

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[PATCH 1/3] ARM: dts: stih407: Enable PWM nodes only board level

[Maxime Coquelin]

The PWM may not be used on some boards, so enable them only the board file.

Signed-off-by: Maxime Coquelin <maxime.coque...@st.com>
---
 arch/arm/boot/dts/stih407-family.dtsi | 6 --
 arch/arm/boot/dts/stihxxx-b2120.dtsi  | 8 
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi 
b/arch/arm/boot/dts/stih407-family.dtsi
index ae05277..9975e8f 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -585,7 +585,6 @@
/* COMMS PWM Module */
pwm0: pwm@981 {
compatible  = "st,sti-pwm";
-   status  = "okay";
#pwm-cells  = <2>;
reg = <0x981 0x68>;
pinctrl-names   = "default";
@@ -593,12 +592,13 @@
clock-names = "pwm";
clocks  = <_sysin>;
st,pwm-num-chan = <1>;
+
+   status  = "disabled";
};
 
/* SBC PWM Module */
pwm1: pwm@951 {
compatible  = "st,sti-pwm";
-   status  = "okay";
#pwm-cells  = <2>;
reg = <0x951 0x68>;
pinctrl-names   = "default";
@@ -609,6 +609,8 @@
clock-names = "pwm";
clocks  = <_sysin>;
st,pwm-num-chan = <4>;
+
+   status  = "disabled";
};
};
 };
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi 
b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index f589fe4..ab029f7 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -27,6 +27,14 @@
};
};
 
+   pwm0: pwm@981 {
+   status = "okay";
+   };
+
+   pwm1: pwm@951 {
+   status = "okay";
+   };
+
i2c@9842000 {
status = "okay";
};
-- 
1.9.1

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[PATCH 2/3] ARM: dts: stih407/410: Tidy up display nodes

[Maxime Coquelin]

The display nodes are common to both STiH407 and STiH410, move them to the
family file.

Signed-off-by: Maxime Coquelin <maxime.coque...@st.com>
---
 arch/arm/boot/dts/stih407-family.dtsi | 13 +
 arch/arm/boot/dts/stih407.dtsi| 13 -
 arch/arm/boot/dts/stih410.dtsi| 13 -
 3 files changed, 13 insertions(+), 26 deletions(-)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi 
b/arch/arm/boot/dts/stih407-family.dtsi
index 9975e8f..5b454d9 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -152,6 +152,19 @@
;
};
 
+   /* Display */
+   vtg_main: sti-vtg-main@8d02800 {
+   compatible = "st,vtg";
+   reg = <0x8d02800 0x200>;
+   interrupts = ;
+   };
+
+   vtg_aux: sti-vtg-aux@8d00200 {
+   compatible = "st,vtg";
+   reg = <0x8d00200 0x100>;
+   interrupts = ;
+   };
+
serial@983 {
compatible = "st,asc";
reg = <0x983 0x2c>;
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index 3efa3b2..98c3468 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -10,19 +10,6 @@
 #include "stih407-family.dtsi"
 / {
soc {
-   /* Display */
-   vtg_main: sti-vtg-main@8d02800 {
-   compatible = "st,vtg";
-   reg = <0x8d02800 0x200>;
-   interrupts = ;
-   };
-
-   vtg_aux: sti-vtg-aux@8d00200 {
-   compatible = "st,vtg";
-   reg = <0x8d00200 0x100>;
-   interrupts = ;
-   };
-
sti-display-subsystem {
compatible = "st,sti-display-subsystem";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 6f40bc9..23f4a48 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -85,19 +85,6 @@
phy-names = "usb";
};
 
-   /* Display */
-   vtg_main: sti-vtg-main@8d02800 {
-   compatible = "st,vtg";
-   reg = <0x8d02800 0x200>;
-   interrupts = ;
-   };
-
-   vtg_aux: sti-vtg-aux@8d00200 {
-   compatible = "st,vtg";
-   reg = <0x8d00200 0x100>;
-   interrupts = ;
-   };
-
sti-display-subsystem {
compatible = "st,sti-display-subsystem";
#address-cells = <1>;
-- 
1.9.1

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Re: [RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2

[Maxime Coquelin]

On 09/17/2015 08:14 PM, Stephen Boyd wrote:

On 09/17, Maxime Coquelin wrote:


On 09/17/2015 12:30 AM, Stephen Boyd wrote:

On 09/16, Gabriel Fernandez wrote:

This patch set fixes a kernel crash :

[..]

This kernel crash is due to a broken compatibility with this commit:
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into 
st_pll3200c32_cx_x")

It isn't clear who's supposed to apply this because the To: list
is huge. Did you want to take this through arm-soc? If so, feel
free to take my acked-by on the second patch. The first patch
doesn't even apply to clk tree because the patch introducing the
typo didn't go through our tree.

Indeed Stephen, I see it went through my tree (STi DT).
So the first patch should be taken through arm-soc.
The second patch, should be taken through yours I think.


Ok. That probably breaks bisectability, but if you're not
worried, I'm not worried.
I'm not worried about bisectability indeed, as the first patch is just 
typo fixes in DT Bindings documentation.


Regards,
Maxime
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Re: [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x

[Maxime Coquelin]

On 09/17/2015 08:51 PM, Stephen Boyd wrote:

On 09/16, Gabriel Fernandez wrote:

Use a generic name for this kind of PLL

Correction in dts files are already done here:
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into 
st_pll3200c32_cx_x")

Signed-off-by: Gabriel Fernandez 
---

Applied to clk-fixes


Thanks Stephen
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Re: [RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2

[Maxime Coquelin]

On 09/17/2015 12:30 AM, Stephen Boyd wrote:

On 09/16, Gabriel Fernandez wrote:

This patch set fixes a kernel crash :

[..]

This kernel crash is due to a broken compatibility with this commit:
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into 
st_pll3200c32_cx_x")

It isn't clear who's supposed to apply this because the To: list
is huge. Did you want to take this through arm-soc? If so, feel
free to take my acked-by on the second patch. The first patch
doesn't even apply to clk tree because the patch introducing the
typo didn't go through our tree.

Indeed Stephen, I see it went through my tree (STi DT).
So the first patch should be taken through arm-soc.
The second patch, should be taken through yours I think.

Regards,
Maxime
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Re: [PATCH 3/7] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support

[Maxime Coquelin]

On 08/31/2015 10:08 AM, Paul Bolle wrote:

Hi Maxime,

On ma, 2015-08-31 at 09:49 +0200, Maxime Coquelin wrote:

On 07/09/2015 10:17 AM, Paul Bolle wrote:

+static int __exit st_fdma_remove(struct platform_device *pdev)
+{
+   struct st_fdma_dev *fdev = platform_get_drvdata(pdev);
+
+   wait_for_completion(>fw_ack);
+
+   st_fdma_clk_disable(fdev);
+
+   return 0;
+}

Since this driver is built-in only this means st_fdma_remove() can
never be used, right?

It's not because a driver is built-in only that it does not need a
remove callback.
An instance can be probed/removed any time via driver's bind/unbind
SysFS entries.
Am I missing something?

(This discussion is moot because Peter already stated that a new version
will be modular.)

It follows from the __exit tag that st_fdma_remove() should never be
part of the kernel image (in this version of the patch), doesn't it?

Yes, you are right.
The remove callback is relevant, but without the __exit tag.


(I don't know what happens in this situation if an unbind sysfs entry is
used to remove a driver. I've never tried that.)


Not checked whether the function is omitted when built-in, but in any 
case, I thnk remove callbacks should not be tagged with __exit.


Regards,
Maxime


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Re: [PATCH 3/7] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support

[Maxime Coquelin]

Hi Paul,

On 07/09/2015 10:17 AM, Paul Bolle wrote:

>+static int __exit st_fdma_remove(struct platform_device *pdev)
>+{
>+   struct st_fdma_dev *fdev = platform_get_drvdata(pdev);
>+
>+   wait_for_completion(>fw_ack);
>+
>+   st_fdma_clk_disable(fdev);
>+
>+   return 0;
>+}

Since this driver is built-in only this means st_fdma_remove() can never
be used, right?



It's not because a driver is built-in only that it does not need a 
remove callback.
An instance can be probed/removed any time via driver's bind/unbind 
SysFS entries.

Am I missing something?

Kind regards,
Maxime
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Re: [PATCH 1/1] ARM: DT: STi: STiH418: Fix mmc0 clock configuration

[Maxime Coquelin]

Hi Gabriel,

On 08/24/2015 11:40 AM, Gabriel Fernandez wrote:

This patch configure correctly the MMC-0 clock for STiH418 platform.

Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
---
  arch/arm/boot/dts/stih418-b2199.dts | 4 
  1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/stih418-b2199.dts 
b/arch/arm/boot/dts/stih418-b2199.dts
index 82eee39..7a03ca6 100644
--- a/arch/arm/boot/dts/stih418-b2199.dts
+++ b/arch/arm/boot/dts/stih418-b2199.dts
@@ -85,6 +85,10 @@
sd-uhs-sdr50;
sd-uhs-sdr104;
sd-uhs-ddr50;
+
+   assigned-clocks = clk_s_c0_flexgen CLK_MMC_0;
+   assigned-clock-parents = clk_s_c0_pll1 0;
+   assigned-clock-rates = 2;


Thanks for the fix, but I would rather define the parent and rate in the 
SoC dtsi file, i.e. stih418.dtsi.

If you agree to change, you can add:
Acked-by: Maxime Coquelin maxime.coque...@st.com

Thanks!
Maxime
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Re: [PATCH] enable HQVDP for stih410 platform

[Maxime Coquelin]

Hi Benjamin,

The title needs to be appended with ARM: dts:.

If you agree, I can fix this when applying it.


On 08/11/2015 05:12 PM, Benjamin Gaignard wrote:

From: Vincent Abriou vincent.abr...@st.com

Add HQVDP in stih410 devicetree to enable it.
HQVDP bindings have been describe in
Documentation/devicetree/bindings/gpu/st,stih4xx.txt file.

Signed-off-by: Vincent Abriou vincent.abr...@st.com

You need also your sign-off here. I will add it too.

---
  arch/arm/boot/dts/stih410.dtsi | 10 ++
  1 file changed, 10 insertions(+)




Regards,
Maxime
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Re: [PATCH 2/2] drm: sti: adapt DT to fix probe/bind issues in DRM driver

[Maxime Coquelin]

Hi Olof,

On 07/17/2015 01:51 PM, Maxime Coquelin wrote:

Dear ARM SoC Maintainers,

On 07/17/2015 01:45 PM, Benjamin Gaignard wrote:

STI drm drivers probe and bind using component framework was incorrect.
In addition to drivers fix DT update is needed to make all 
sub-components

become childs of sti-display-subsystem.

Signed-off-by: Benjamin Gaignard benjamin.gaign...@linaro.org
---
  arch/arm/boot/dts/stih407.dtsi | 82 
+-
  arch/arm/boot/dts/stih410.dtsi | 82 
+-

  2 files changed, 80 insertions(+), 84 deletions(-)




This patch solves an issue preventing DRM driver probing, but it 
breaks the DT ABI.
For now, this driver and its DT node are only used by a few identified 
people.


Since these people only use aligned version of Kernel and DT, do you 
accept we break the ABI for this time?




Just a gentle reminder.
Can we derogate for this patch?

Thanks in advance,
Maxime
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Re: [PATCH] ARM: dts: Add STM32429i-EVAL board support

[Maxime Coquelin]

On 07/12/2015 11:39 AM, Maxime Coquelin wrote:

Main features of STM32429i-EVAL evaluation kit are:
  - STM32F429 Cortex-M4 MCU @180MHz
* 2MB internal Flash
* 256KB internal RAM
  - 32MB SDRAM
  - 16MB NOR Flash
  - 2MB SRAM
  - 4.3 TFT LCD with resistive touchscreen
  - SDCard connector (SDIO compatible)
  - 1x USB 2.0 OTG + 1x USB 1.1 OTG
  - Ethernet

Signed-off-by: Maxime Coquelin mcoquelin.st...@gmail.com
---
  arch/arm/boot/dts/Makefile   |  4 +-
  arch/arm/boot/dts/stm32429i-eval.dts | 75 
  2 files changed, 78 insertions(+), 1 deletion(-)
  create mode 100644 arch/arm/boot/dts/stm32429i-eval.dts



Applied to next/dt-for-v4.3.

Best regards,
Maxime
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Re: [PATCH v2 3/3] ARM: STi: DT: STiH418: Add cpu-release-addr dt property.

[Maxime Coquelin]

HI Peter,

On 06/09/2015 03:33 PM, Peter Griffin wrote:

To enable SMP when booting via u-boot we need to specify the
newly implemented cpu-release-addr DT property for cores 2  3.
Cores 0  1 are inherited from stih407-family.dtsi.

Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
  arch/arm/boot/dts/stih418.dtsi | 4 
  1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
index 354d90f..8160a75 100644
--- a/arch/arm/boot/dts/stih418.dtsi
+++ b/arch/arm/boot/dts/stih418.dtsi
@@ -17,11 +17,15 @@
device_type = cpu;
compatible = arm,cortex-a9;
reg = 2;
+   /* u-boot puts hpen in SBC dmem at 0xa4 offset */
+   cpu-release-addr = 0x94100A4;
};
cpu@3 {
device_type = cpu;
compatible = arm,cortex-a9;
reg = 3;
+   /* u-boot puts hpen in SBC dmem at 0xa4 offset */
+   cpu-release-addr = 0x94100A4;
};
};
  


Patch applied for v4.3.

Thanks,
Maxime
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Re: [PATCH 9/9] ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x

[Maxime Coquelin]

Hi Gabriel,

On 06/23/2015 04:09 PM, Gabriel Fernandez wrote:

Use a generic name for this kind of PLL

Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
---
  Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
  arch/arm/boot/dts/stih407-clock.dtsi | 4 ++--
  arch/arm/boot/dts/stih410-clock.dtsi | 4 ++--
  arch/arm/boot/dts/stih418-clock.dtsi | 4 ++--
  4 files changed, 8 insertions(+), 8 deletions(-)




Patch applied to sti-dt-for-v4.3.

Thanks!
Maxime
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Re: [PATCH v2 2/3] ARM: STi: DT: STiH407: Add cpu-release-addr dt property.

[Maxime Coquelin]

HI Peter,

On 06/09/2015 03:33 PM, Peter Griffin wrote:

To enable SMP when booting via u-boot we need to specify the
newly implemented cpu-release-addr DT property.

Signed-off-by: Peter Griffin peter.grif...@linaro.org
Acked-by: Maxime Coquelin maxime.coque...@st.com
---
  arch/arm/boot/dts/stih407-family.dtsi | 4 
  1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi 
b/arch/arm/boot/dts/stih407-family.dtsi
index c06a546..3c90227 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -19,11 +19,15 @@
device_type = cpu;
compatible = arm,cortex-a9;
reg = 0;
+   /* u-boot puts hpen in SBC dmem at 0xa4 offset */
+   cpu-release-addr = 0x94100A4;
};
cpu@1 {
device_type = cpu;
compatible = arm,cortex-a9;
reg = 1;
+   /* u-boot puts hpen in SBC dmem at 0xa4 offset */
+   cpu-release-addr = 0x94100A4;
};
};
  


Patch applied for v4.3.

Thanks,
Maxime
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Re: [PATCH v2 1/3] ARM: STi: Add code to release secondary cores from holding pen.

[Maxime Coquelin]

Hi Peter,

On 06/09/2015 03:33 PM, Peter Griffin wrote:

Most upstream devs boot STi platform via JTAG which abuses the
boot process by setting the PC of secondary cores directly. As
a consquence, booting STi platforms via u-boot results in only
the primary core being brought up as the code to manage the
holding pen is not upstream.

This patch adds the necessary code to bring the secondary cores
out of the holding pen. It uses the cpu-release-addr DT property
to get the address of the holding pen from the bootloader.

With this patch booting upstream kernels via u-boot works
correctly:

[0.045456] CPU: Testing write buffer coherency: ok
[0.045597] CPU0: thread -1, cpu 0, socket 0, mpidr 8000
[0.045734] Setting up static identity map for 0x40209000 - 0x40209098
[0.065047] CPU1: thread -1, cpu 1, socket 0, mpidr 8001
[0.065081] Brought up 2 CPUs
[0.065089] SMP: Total of 2 processors activated (5983.43 BogoMIPS).
[0.065092] CPU: All CPU(s) started in SVC mode.

Signed-off-by: Peter Griffin peter.grif...@linaro.org
Acked-by: Maxime Coquelin maxime.coque...@st.com
---
  arch/arm/mach-sti/headsmp.S |  1 +
  arch/arm/mach-sti/platsmp.c | 55 ++---
  arch/arm/mach-sti/smp.h |  2 ++
  3 files changed, 55 insertions(+), 3 deletions(-)




Applied to sti-soc-for-v4.3.

Thanks!
Maxime
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Re: [PATCH] ARM: DT: STiH410: Add bdisp dt nodes

[Maxime Coquelin]

Hi Fabien,

On 06/16/2015 03:30 PM, Fabien Dessenne wrote:

Add the bdisp (2D blitter for STMicroelectronics SoC) dt nodes for the
first of the two bdisp devices, defining register address, interrupt and
clock.

Signed-off-by: Fabien Dessenne fabien.desse...@st.com
---
  arch/arm/boot/dts/stih410.dtsi | 12 
  1 file changed, 12 insertions(+)




Patch applied to sti-dt-for-v4.3.

Thanks!
Maxime
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Re: [PATCH 0/9] Add STiH407 fanmily pinctrl DT for tsin, tsout and mtsin channels

[Maxime Coquelin]

Hi Peter,

On 06/10/2015 04:03 PM, Peter Griffin wrote:

Hi folks,

This set adds in the necessary DT pinctrl configuration for the transport stream
input channels, transport stream output channels and merged transport stream 
input
channels for STiH407 family silicon.

Some of these channels have alternate pinctrl configurations depending on the 
board
design. These pinctrl groups will be used by the LinuxDVB c8sectpfe driver which
will be upstreamed in due course, which allows LDVB tuners and demodulators to 
be
used with an upstream kernel to get transport stream data into the SoC.

regards,

Peter.

Peter Griffin (9):
   ARM: STi: DT: Add STiH407 family tsin0 pinctrl configuration
   ARM: STi: DT: Add STiH407 family tsin1 pinctrl configuration
   ARM: STi: DT: Add STiH407 family tsin2 pinctrl configuration
   ARM: STi: DT: Add STiH407 family tsin3 pinctrl configuration
   ARM: STi: DT: Add STiH407 family tsin4 pinctrl configuration
   ARM: STi: DT: Add STiH407 family tsin5 pinctrl configuration
   ARM: STi: DT: Add STiH407 family tsout0 pinctrl configuration
   ARM: STi: DT: Add STiH407 family tsout1 pinctrl configuration
   ARM: STi: DT: Add STiH407 family mtsin0 pinctrl configuration

  arch/arm/boot/dts/stih407-pinctrl.dtsi | 200 +
  1 file changed, 200 insertions(+)


Series applied for v4.3.

Thanks,
Maxime
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