[PATCH v2 5/5] clk: rockchip: rk3036: add HCLK_MAC id for emac

[Xing Zheng]

We need to add HCLK_MAC id explicitly because that it is referred
by hclk in the emac driver.

Signed-off-by: Xing Zheng 
---

 drivers/clk/rockchip/clk-rk3036.c  |2 +-
 include/dt-bindings/clock/rk3036-cru.h |1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3036.c 
b/drivers/clk/rockchip/clk-rk3036.c
index bc7fbac..15cd29a 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -404,7 +404,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] 
__initdata = {
GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, 
GFLAGS),
GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(3), 14, GFLAGS),
-   GATE(0, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(3), 15, GFLAGS),
+   GATE(HCLK_MAC, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(3), 15, GFLAGS),
 
/* pclk_peri gates */
GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 1, GFLAGS),
diff --git a/include/dt-bindings/clock/rk3036-cru.h 
b/include/dt-bindings/clock/rk3036-cru.h
index ebc7a7b..3396591 100644
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -92,6 +92,7 @@
 #define HCLK_SDMMC 456
 #define HCLK_SDIO  457
 #define HCLK_EMMC  459
+#define HCLK_MAC   460
 #define HCLK_I2S   462
 #define HCLK_LCDC  465
 #define HCLK_ROM   467
-- 
1.7.9.5


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[PATCH v2 0/5] fix some clock configuration for the RK3036 platform

[Xing Zheng]

Hi:
  In the development work, we found that some of the previous
incorrect clock configuration on the RK3036 platform, we should
fix them.



Xing Zheng (5):
  clk: rockchip: rk3036: fix the FLAGs for clock mux
  clk: rockchip: rk3036: fix uarts clock error
  clk: rockchip: rk3036: fix the div offset for emac clock
  clk: rockchip: rk3036: rename emac ext source clock
  clk: rockchip: rk3036: add HCLK_MAC id for emac

 drivers/clk/rockchip/clk-rk3036.c  |   28 ++--
 include/dt-bindings/clock/rk3036-cru.h |1 +
 2 files changed, 15 insertions(+), 14 deletions(-)

-- 
1.7.9.5


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Re: [RESEND PATCH v1 4/4] clk: rockchip: rk3036: fix and add node id for emac clock

[Xing Zheng]

Hi Heiko,

On 2016年01月02日 10:34, Xing Zheng wrote:
> Hi Heiko,
> Thank you for your patch, I will apply and test it later.
>
> Thanks.
>
>> 在 2016年1月2日，06:10，Heiko Stübner  写道：
>>
>> Hi Xing,
>>
>> Am Dienstag, 29. Dezember 2015, 10:34:09 schrieb Xing Zheng:
>>> On 2015年12月29日 09:59, Yakir Yang wrote:
>>>> On 12/28/2015 08:41 PM, Heiko Stübner wrote:
>>>>> Am Montag, 28. Dezember 2015, 17:03:53 schrieb Xing Zheng:
>>>>>> Due to referred old version TRM, there is incorrect emac clock node,
>>>>>> we should fix it. The SEL_21_9 is the parent of SEL_21_4.
>>>>>>
>>>>>> In the emac driver, we need to refer HCLK_MAC, and because There are
>>>>>> only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clock are under the
>>>>>> GPLL, and it is unable to provide the accurate rate for mac_ref which
>>>>>> need to 50MHz probability, we should let it under the APLL and are
>>>>>> able to set the freq which integer multiples of 50MHz, so we add these
>>>>>> emac node for reference.
>>>>> I don't really follow here. While I do understand that the emac needs
>>>>> 50MHz, I
>>>>> don't think using the APLL as source is helpful.
>>>>>
>>>>> The APLL is the main clocksource for the cpu-cores, including frequency
>>>>> scaling, and while it currently only lists 816MHz as sole frequency,
>>>>> you're
>>>>> pretty much guaranteed to not get your correct multiple of 50MHz from
>>>>> there
>>>>> either. And limiting the cpu to just do 600MHz to get the mac working
>>>>> sounds
>>>>> pretty bad ;-) .
>>>>>
>>>>>
>>>>> In the rk3036 cru-node the gpll gets set to 594MHz. Is there a
>>>>> special reason
>>>>> why it needs to be 594MHz and cannot be a round 600MHz? Because that
>>>>> would
>>>>> also provide your 50MHz-multiple nicely.
>>>> Yes, this magic 594MHz would help to support the standard HDMI
>>>> resolutions, here are the math:
>>>>
>>>> 1920x1080-60Hz DCLK = 148.5MHz = 594MHz / 4
>>>> 1280x720-60Hz DCLK = 74.25MHz = 594MHz / 8
>>>> 720x480-60Hz DCLK = 27MHz = 594MHz / 22
>>>>
>>>> Thanks,
>>>> - Yakir
>>> Thanks Yakir.
>>>
>>> Hi Heiko,
>>> From the above, do you have better idea for the RK3036's emac without
>>> ext-oscillator?
>> During the last days I did play a bit with the clock framework. As I don't 
>> have a Kylin (or any rk3036) board, I did build a test-case with pclk_cpu on 
>> the rk3188 (which can be affected by the armclk if not reparented to the 
>> gpll), which got sucessfully adapted to get back to (or near) the originally 
>> requested frequency.
>>
>> So ideally you could roll back your mux/div split here and try the attached 
>> diff. In theory it should help :-) .
>> As can be seen by the FIXMEs, not fully finished, but I'd like to determine 
>> if 
>> it fixes the issue at least.
>>
>>
>> Heiko
>> 

I tested your patch just now, it seems to work well. I will do more tests.

Thank you. :-)

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Re: [RESEND PATCH v1 4/4] clk: rockchip: rk3036: fix and add node id for emac clock

[Xing Zheng]

Hi Heiko,
Thank you for your patch, I will apply and test it later.

Thanks.

> 在 2016年1月2日，06:10，Heiko Stübner  写道：
> 
> Hi Xing,
> 
> Am Dienstag, 29. Dezember 2015, 10:34:09 schrieb Xing Zheng:
>> On 2015年12月29日 09:59, Yakir Yang wrote:
>>> On 12/28/2015 08:41 PM, Heiko Stübner wrote:
>>>> Am Montag, 28. Dezember 2015, 17:03:53 schrieb Xing Zheng:
>>>>> Due to referred old version TRM, there is incorrect emac clock node,
>>>>> we should fix it. The SEL_21_9 is the parent of SEL_21_4.
>>>>> 
>>>>> In the emac driver, we need to refer HCLK_MAC, and because There are
>>>>> only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clock are under the
>>>>> GPLL, and it is unable to provide the accurate rate for mac_ref which
>>>>> need to 50MHz probability, we should let it under the APLL and are
>>>>> able to set the freq which integer multiples of 50MHz, so we add these
>>>>> emac node for reference.
>>>> 
>>>> I don't really follow here. While I do understand that the emac needs
>>>> 50MHz, I
>>>> don't think using the APLL as source is helpful.
>>>> 
>>>> The APLL is the main clocksource for the cpu-cores, including frequency
>>>> scaling, and while it currently only lists 816MHz as sole frequency,
>>>> you're
>>>> pretty much guaranteed to not get your correct multiple of 50MHz from
>>>> there
>>>> either. And limiting the cpu to just do 600MHz to get the mac working
>>>> sounds
>>>> pretty bad ;-) .
>>>> 
>>>> 
>>>> In the rk3036 cru-node the gpll gets set to 594MHz. Is there a
>>>> special reason
>>>> why it needs to be 594MHz and cannot be a round 600MHz? Because that
>>>> would
>>>> also provide your 50MHz-multiple nicely.
>>> 
>>> Yes, this magic 594MHz would help to support the standard HDMI
>>> resolutions, here are the math:
>>> 
>>> 1920x1080-60Hz DCLK = 148.5MHz = 594MHz / 4
>>> 1280x720-60Hz DCLK = 74.25MHz = 594MHz / 8
>>> 720x480-60Hz DCLK = 27MHz = 594MHz / 22
>>> 
>>> Thanks,
>>> - Yakir
>> 
>> Thanks Yakir.
>> 
>> Hi Heiko,
>> From the above, do you have better idea for the RK3036's emac without
>> ext-oscillator?
> 
> During the last days I did play a bit with the clock framework. As I don't 
> have a Kylin (or any rk3036) board, I did build a test-case with pclk_cpu on 
> the rk3188 (which can be affected by the armclk if not reparented to the 
> gpll), which got sucessfully adapted to get back to (or near) the originally 
> requested frequency.
> 
> So ideally you could roll back your mux/div split here and try the attached 
> diff. In theory it should help :-) .
> As can be seen by the FIXMEs, not fully finished, but I'd like to determine 
> if 
> it fixes the issue at least.
> 
> 
> Heiko
> 

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Re: [RESEND PATCH v1 4/4] clk: rockchip: rk3036: fix and add node id for emac clock

[Xing Zheng]

On 2015年12月29日 09:59, Yakir Yang wrote:

Hi Heiko,

On 12/28/2015 08:41 PM, Heiko Stübner wrote:

Hi,

Am Montag, 28. Dezember 2015, 17:03:53 schrieb Xing Zheng:

Due to referred old version TRM, there is incorrect emac clock node,
we should fix it. The SEL_21_9 is the parent of SEL_21_4.

In the emac driver, we need to refer HCLK_MAC, and because There are
only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clock are under the
GPLL, and it is unable to provide the accurate rate for mac_ref which
need to 50MHz probability, we should let it under the APLL and are
able to set the freq which integer multiples of 50MHz, so we add these
emac node for reference.
I don't really follow here. While I do understand that the emac needs 
50MHz, I

don't think using the APLL as source is helpful.

The APLL is the main clocksource for the cpu-cores, including frequency
scaling, and while it currently only lists 816MHz as sole frequency, 
you're
pretty much guaranteed to not get your correct multiple of 50MHz from 
there
either. And limiting the cpu to just do 600MHz to get the mac working 
sounds

pretty bad ;-) .


In the rk3036 cru-node the gpll gets set to 594MHz. Is there a 
special reason
why it needs to be 594MHz and cannot be a round 600MHz? Because that 
would

also provide your 50MHz-multiple nicely.


Yes, this magic 594MHz would help to support the standard HDMI 
resolutions, here are the math:


1920x1080-60Hz DCLK = 148.5MHz = 594MHz / 4
1280x720-60Hz DCLK = 74.25MHz = 594MHz / 8
720x480-60Hz DCLK = 27MHz = 594MHz / 22

Thanks,
- Yakir

Thanks Yakir.

Hi Heiko,
From the above, do you have better idea for the RK3036's emac without 
ext-oscillator?


Thanks. :-)



Signed-off-by: Xing Zheng 
---

drivers/clk/rockchip/clk-rk3036.c | 11 ++-
include/dt-bindings/clock/rk3036-cru.h | 2 ++
2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3036.c
b/drivers/clk/rockchip/clk-rk3036.c index 7420cbe..7863c4d 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -328,13 +328,14 @@ static struct rockchip_clk_branch
rk3036_clk_branches[] __initdata = { RK2928_CLKSEL_CON(16), 0, 2, 
MFLAGS,

2, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 5, GFLAGS),

- COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
- RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
+ MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0,
+ RK2928_CLKSEL_CON(21), 0, 2, MFLAGS),
+ DIV(0, "mac_pll_src", "mac_pll_pre", 0,
+ RK2928_CLKSEL_CON(21), 9, 5, DFLAGS),
MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
-
COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
- RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,
+ RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 6, GFLAGS),

MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
@@ -389,7 +390,7 @@ static struct rockchip_clk_branch 
rk3036_clk_branches[]
__initdata = { GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", 
CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(7), 3, GFLAGS), GATE(HCLK_I2S, "hclk_i2s", 
"hclk_peri",

0, RK2928_CLKGATE_CON(7), 2, GFLAGS), GATE(0, "hclk_sfc", "hclk_peri",
CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), - GATE(0,
"hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15,
GFLAGS), + GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0,
RK2928_CLKGATE_CON(3), 5, GFLAGS),

/* pclk_peri gates */
GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(4), 1, GFLAGS), diff --git
a/include/dt-bindings/clock/rk3036-cru.h
b/include/dt-bindings/clock/rk3036-cru.h index ebc7a7b..de44109 100644
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -54,6 +54,7 @@
#define SCLK_PVTM_VIDEO 125
#define SCLK_MAC 151
#define SCLK_MACREF 152
+#define SCLK_MACPLL 153
#define SCLK_SFC 160

/* aclk gates */
@@ -92,6 +93,7 @@

please separate the hclk addition into two separate patches:
patch1: add the clock-id to the dt-binding header
patch2: use the clock in the clock-driver

Done.



#define HCLK_SDMMC 456
#define HCLK_SDIO 457
#define HCLK_EMMC 459
+#define HCLK_MAC 460
#define HCLK_I2S 462
#define HCLK_LCDC 465
#define HCLK_ROM 467


Thanks
Heiko

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[RESEND PATCH v1 4/4] clk: rockchip: rk3036: fix and add node id for emac clock

[Xing Zheng]

Due to referred old version TRM, there is incorrect emac clock node,
we should fix it. The SEL_21_9 is the parent of SEL_21_4.

In the emac driver, we need to refer HCLK_MAC, and  because There are
only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clock are under the
GPLL, and it is unable to provide the accurate rate for mac_ref which
need to 50MHz probability, we should let it under the APLL and are
able to set the freq which integer multiples of 50MHz, so we add these
emac node for reference.

Signed-off-by: Xing Zheng 
---

 drivers/clk/rockchip/clk-rk3036.c  |   11 ++-
 include/dt-bindings/clock/rk3036-cru.h |2 ++
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3036.c 
b/drivers/clk/rockchip/clk-rk3036.c
index 7420cbe..7863c4d 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -328,13 +328,14 @@ static struct rockchip_clk_branch rk3036_clk_branches[] 
__initdata = {
RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 5, GFLAGS),
 
-   COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
-   RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
+   MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0,
+   RK2928_CLKSEL_CON(21), 0, 2, MFLAGS),
+   DIV(0, "mac_pll_src", "mac_pll_pre", 0,
+   RK2928_CLKSEL_CON(21), 9, 5, DFLAGS),
MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
-
COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
-   RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,
+   RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 6, GFLAGS),
 
MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
@@ -389,7 +390,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] 
__initdata = {
GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, 
GFLAGS),
GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(3), 14, GFLAGS),
-   GATE(0, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(3), 15, GFLAGS),
+   GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, 
GFLAGS),
 
/* pclk_peri gates */
GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 1, GFLAGS),
diff --git a/include/dt-bindings/clock/rk3036-cru.h 
b/include/dt-bindings/clock/rk3036-cru.h
index ebc7a7b..de44109 100644
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -54,6 +54,7 @@
 #define SCLK_PVTM_VIDEO125
 #define SCLK_MAC   151
 #define SCLK_MACREF152
+#define SCLK_MACPLL153
 #define SCLK_SFC   160
 
 /* aclk gates */
@@ -92,6 +93,7 @@
 #define HCLK_SDMMC 456
 #define HCLK_SDIO  457
 #define HCLK_EMMC  459
+#define HCLK_MAC   460
 #define HCLK_I2S   462
 #define HCLK_LCDC  465
 #define HCLK_ROM   467
-- 
1.7.9.5


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[RESEND PATCH v1 0/4] fix some clock configuration for the RK3036 platform

[Xing Zheng]

Hi:
  In the development work, we found that some of the previous incorrect
clock configuration on the RK3036 platform, we should fix them.



Xing Zheng (4):
  clk: rockchip: rk3036: fix the FLAGs for clock mux
  clk: rockchip: rk3036: fix uarts clock error
  clk: rockchip: rk3036: rename emac ext source clock
  clk: rockchip: rk3036: fix and add node id for emac clock

 drivers/clk/rockchip/clk-rk3036.c  |   33 
 include/dt-bindings/clock/rk3036-cru.h |2 ++
 2 files changed, 19 insertions(+), 16 deletions(-)

-- 
1.7.9.5


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[RESEND PATCH v1 0/4] Add support emac for the RK3036 SoC platform

[Xing Zheng]

Hi,
  We have supported the emac for RK3066/RK3188, but the RK3036 have some
configuration different with them. We should let the driver of emac_rockchip
compatible with other Rockchip SoCs.



Xing Zheng (4):
  net: ethernet: arc: Probe emac after set RMII clock
  net: ethernet: arc: Keep emac compatibility for more Rockchip SoCs
  net: ethernet: arc: Add support emac for RK3036
  ARM: dts: rockchip: Add support emac for RK3036

 arch/arm/boot/dts/rk3036-evb.dts |   25 +
 arch/arm/boot/dts/rk3036-kylin.dts   |   23 
 arch/arm/boot/dts/rk3036.dtsi|   32 +++
 drivers/net/ethernet/arc/Kconfig |4 +-
 drivers/net/ethernet/arc/emac_rockchip.c |   86 --
 5 files changed, 140 insertions(+), 30 deletions(-)

-- 
1.7.9.5


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[RESEND PATCH v1 4/4] ARM: dts: rockchip: Add support emac for RK3036

[Xing Zheng]

This patch describe the emac, and we need to let mac clock under
the APLL which is able to provide the accurate 50MHz what mac_ref
need.

Signed-off-by: Xing Zheng 
---

 arch/arm/boot/dts/rk3036-evb.dts   |   25 +
 arch/arm/boot/dts/rk3036-kylin.dts |   23 +++
 arch/arm/boot/dts/rk3036.dtsi  |   32 
 3 files changed, 80 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
index 28a0336..69b96e6 100644
--- a/arch/arm/boot/dts/rk3036-evb.dts
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -62,3 +62,28 @@
 &uart2 {
status = "okay";
 };
+
+&emac {
+   assigned-clocks = <&cru SCLK_MACPLL>;
+   assigned-clock-parents = <&cru PLL_APLL>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
+   phy = <&phy0>;
+   status = "okay";
+
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+};
+
+&pinctrl {
+   pcfg_output_high: pcfg-output-high {
+   output-high;
+   };
+
+   emac {
+   rmii_rst: rmii-rst {
+   rockchip,pins = <2 22 RK_FUNC_GPIO &pcfg_output_high>;
+   };
+   };
+};
diff --git a/arch/arm/boot/dts/rk3036-kylin.dts 
b/arch/arm/boot/dts/rk3036-kylin.dts
index 992f9ca..3fb1cfe 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -285,7 +285,24 @@
status = "okay";
 };
 
+&emac {
+   assigned-clocks = <&cru SCLK_MACPLL>;
+   assigned-clock-parents = <&cru PLL_APLL>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
+   phy = <&phy0>;
+   status = "okay";
+
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+};
+
 &pinctrl {
+   pcfg_output_high: pcfg-output-high {
+   output-high;
+   };
+
pmic {
pmic_int: pmic-int {
rockchip,pins = <2 2 RK_FUNC_GPIO &pcfg_pull_default>;
@@ -297,4 +314,10 @@
rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>;
};
};
+
+   emac {
+   rmii_rst: rmii-rst {
+   rockchip,pins = <2 22 RK_FUNC_GPIO &pcfg_output_high>;
+   };
+   };
 };
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index b9567c1..0c09fb3 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -186,6 +186,20 @@
status = "disabled";
};
 
+   emac: ethernet@1020 {
+   compatible = "rockchip,rk3036-emac", "snps,arc-emac";
+   reg = <0x1020 0x4000>;
+   interrupts = ;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   rockchip,grf = <&grf>;
+   clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
+   clock-names = "hclk", "macref", "macclk";
+   max-speed = <100>;
+   phy-mode = "rmii";
+   status = "disabled";
+   };
+
sdmmc: dwmmc@10214000 {
compatible = "rockchip,rk3036-dw-mshc", 
"rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
@@ -556,6 +570,24 @@
};
};
 
+   emac {
+   emac_xfer: emac-xfer {
+   rockchip,pins = <2 10 RK_FUNC_1 
&pcfg_pull_none>, /* crs_dvalid */
+   <2 13 RK_FUNC_1 
&pcfg_pull_none>, /* tx_en */
+   <2 14 RK_FUNC_1 
&pcfg_pull_none>, /* mac_clk */
+   <2 15 RK_FUNC_1 
&pcfg_pull_none>, /* rx_err */
+   <2 16 RK_FUNC_1 
&pcfg_pull_none>, /* rxd1 */
+   <2 17 RK_FUNC_1 
&pcfg_pull_none>, /* rxd0 */
+   <2 18 RK_FUNC_1 
&pcfg_pull_none>, /* txd1 */
+   <2 19 RK_FUNC_1 
&pcfg_pull_none>; /* txd0 */
+   };
+
+   emac_mdio: emac-mdio {
+   rockchip,pins = <2 12 RK_FUNC_1 
&pcfg_pull_none>, /* mac_md */
+   <2 25 RK_FUNC_1 
&pcfg_pull_none>; /* mac_mdclk */
+   };
+   };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
-- 
1.7.9.5


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[PATCH 4/4] ARM: dts: rockchip: Add support emac for RK3036

[Xing Zheng]

This patch describe the emac, and we need to let mac clock under
the APLL which is able to provide the accurate 50MHz what mac_ref
need.

Signed-off-by: Xing Zheng 
---

 arch/arm/boot/dts/rk3036-evb.dts   |   25 +
 arch/arm/boot/dts/rk3036-kylin.dts |   23 +++
 arch/arm/boot/dts/rk3036.dtsi  |   32 
 3 files changed, 80 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
index 28a0336..69b96e6 100644
--- a/arch/arm/boot/dts/rk3036-evb.dts
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -62,3 +62,28 @@
 &uart2 {
status = "okay";
 };
+
+&emac {
+   assigned-clocks = <&cru SCLK_MACPLL>;
+   assigned-clock-parents = <&cru PLL_APLL>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
+   phy = <&phy0>;
+   status = "okay";
+
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+};
+
+&pinctrl {
+   pcfg_output_high: pcfg-output-high {
+   output-high;
+   };
+
+   emac {
+   rmii_rst: rmii-rst {
+   rockchip,pins = <2 22 RK_FUNC_GPIO &pcfg_output_high>;
+   };
+   };
+};
diff --git a/arch/arm/boot/dts/rk3036-kylin.dts 
b/arch/arm/boot/dts/rk3036-kylin.dts
index 992f9ca..3fb1cfe 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -285,7 +285,24 @@
status = "okay";
 };
 
+&emac {
+   assigned-clocks = <&cru SCLK_MACPLL>;
+   assigned-clock-parents = <&cru PLL_APLL>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
+   phy = <&phy0>;
+   status = "okay";
+
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+};
+
 &pinctrl {
+   pcfg_output_high: pcfg-output-high {
+   output-high;
+   };
+
pmic {
pmic_int: pmic-int {
rockchip,pins = <2 2 RK_FUNC_GPIO &pcfg_pull_default>;
@@ -297,4 +314,10 @@
rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>;
};
};
+
+   emac {
+   rmii_rst: rmii-rst {
+   rockchip,pins = <2 22 RK_FUNC_GPIO &pcfg_output_high>;
+   };
+   };
 };
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index b9567c1..0c09fb3 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -186,6 +186,20 @@
status = "disabled";
};
 
+   emac: ethernet@1020 {
+   compatible = "rockchip,rk3036-emac", "snps,arc-emac";
+   reg = <0x1020 0x4000>;
+   interrupts = ;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   rockchip,grf = <&grf>;
+   clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
+   clock-names = "hclk", "macref", "macclk";
+   max-speed = <100>;
+   phy-mode = "rmii";
+   status = "disabled";
+   };
+
sdmmc: dwmmc@10214000 {
compatible = "rockchip,rk3036-dw-mshc", 
"rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
@@ -556,6 +570,24 @@
};
};
 
+   emac {
+   emac_xfer: emac-xfer {
+   rockchip,pins = <2 10 RK_FUNC_1 
&pcfg_pull_none>, /* crs_dvalid */
+   <2 13 RK_FUNC_1 
&pcfg_pull_none>, /* tx_en */
+   <2 14 RK_FUNC_1 
&pcfg_pull_none>, /* mac_clk */
+   <2 15 RK_FUNC_1 
&pcfg_pull_none>, /* rx_err */
+   <2 16 RK_FUNC_1 
&pcfg_pull_none>, /* rxd1 */
+   <2 17 RK_FUNC_1 
&pcfg_pull_none>, /* rxd0 */
+   <2 18 RK_FUNC_1 
&pcfg_pull_none>, /* txd1 */
+   <2 19 RK_FUNC_1 
&pcfg_pull_none>; /* txd0 */
+   };
+
+   emac_mdio: emac-mdio {
+   rockchip,pins = <2 12 RK_FUNC_1 
&pcfg_pull_none>, /* mac_md */
+   <2 25 RK_FUNC_1 
&pcfg_pull_none>; /* mac_mdclk */
+   };
+   };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
-- 
1.7.9.5


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[PATCH 2/2] clk: rockchip: rk3036: fix and add node id for emac clock

[Xing Zheng]

Due to referred old version TRM, there is incorrect emac clock node,
we should fix it. The SEL_21_9 is the parent of SEL_21_4.

In the emac driver, we need to refer HCLK_MAC, and because There are
only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clock are under the
GPLL, and it is unable to provide the accurate rate for mac_ref which
need to 50MHz probability, we should let it under the APLL and are
able to set the freq which integer multiples of 50MHz, so we add these
emac node for reference.

Signed-off-by: Xing Zheng 
---

 drivers/clk/rockchip/clk-rk3036.c  |   11 ++-
 include/dt-bindings/clock/rk3036-cru.h |2 ++
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3036.c 
b/drivers/clk/rockchip/clk-rk3036.c
index 1016836..92426b0 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -328,13 +328,14 @@ static struct rockchip_clk_branch rk3036_clk_branches[] 
__initdata = {
RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 5, GFLAGS),
 
-   COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
-   RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
+   MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0,
+   RK2928_CLKSEL_CON(21), 0, 2, MFLAGS),
+   DIV(0, "mac_pll_src", "mac_pll_pre", 0,
+   RK2928_CLKSEL_CON(21), 9, 5, DFLAGS),
MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
-
COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
-   RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,
+   RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 6, GFLAGS),
 
MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
@@ -389,7 +390,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] 
__initdata = {
GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, 
GFLAGS),
GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(3), 14, GFLAGS),
-   GATE(0, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(3), 15, GFLAGS),
+   GATE(HCLK_MAC, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(3), 15, GFLAGS),
 
/* pclk_peri gates */
GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 1, GFLAGS),
diff --git a/include/dt-bindings/clock/rk3036-cru.h 
b/include/dt-bindings/clock/rk3036-cru.h
index ebc7a7b..de44109 100644
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -54,6 +54,7 @@
 #define SCLK_PVTM_VIDEO125
 #define SCLK_MAC   151
 #define SCLK_MACREF152
+#define SCLK_MACPLL153
 #define SCLK_SFC   160
 
 /* aclk gates */
@@ -92,6 +93,7 @@
 #define HCLK_SDMMC 456
 #define HCLK_SDIO  457
 #define HCLK_EMMC  459
+#define HCLK_MAC   460
 #define HCLK_I2S   462
 #define HCLK_LCDC  465
 #define HCLK_ROM   467
-- 
1.7.9.5


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Re: [PATCH v7 0/6] Build and support rk3036 SoC platform

[Xing Zheng]

OK, Thanks Heiko. :-)

On 2015年11月24日 08:03, Heiko Stübner wrote:

Hi Xing Zheng,

Am Donnerstag, 5. November 2015, 15:33:54 schrieb Xing Zheng:

Hi,
   We need to support rk3036 soc platform via upstream, there are
some primary parts for the initial release of minimum system: dts,
clk-pll, smp, and clock tree for rk3036, and additional, we can use
these startup and run to init processs.

[...]

after talking with Mike and agreeing that I'm again taking the regular
clock patches to them, I've applied all of this to appropriate branches.
I did some cosmetics, as explained below.



Xing Zheng (6):
   dt-bindings: add documentation of rk3036 clock controller
   clk: rockchip: add dt-binding header for rk3036
   clk: rockchip: add new pll-type for rk3036 and similar socs

- wrapped some overly long lines, otherwise this is similar to what
   Stephen already took for the rk3066-pll-type.



   clk: rockchip: add clock controller for rk3036
   ARM: dts: rockchip: add core rk3036 dts

- split off the evb into a separate patch
- reordered some nodes (please order by the address (the @)
- reordered some properties
- fixed the gic cpu masks



   ARM: dts: enable smp for rk3036

folded into the core dtsi addition


Please take a final look at [0] to make sure I didn't mess up anything.


Thanks
Heiko


[0]
https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/log/?h=v4.5-clk/next
https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/log/?h=v4.5-armsoc/dts32






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[PATCH v7 6/6] ARM: dts: enable smp for rk3036

[Xing Zheng]

Enable smp for rk3036, and add the smp sram name for adapting.

---

Changes in v7:
Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 

 arch/arm/boot/dts/rk3036.dtsi |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 380fe10..61b40dd 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -75,6 +75,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "rockchip,rk3036-smp";
 
cpu0: cpu@f00 {
device_type = "cpu";
@@ -157,6 +158,10 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1008 0x2000>;
+   smp-sram@0 {
+   compatible = "rockchip,rk3066-smp-sram";
+   reg = <0x00 0x10>;
+   };
};
 
cru: clock-controller@2000 {
-- 
1.7.9.5


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[PATCH v7 5/6] ARM: dts: rockchip: add core rk3036 dts

[Xing Zheng]

Initial release for rk3036, node definitions rk3036 sdk board.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v7: None

 arch/arm/boot/dts/Makefile   |1 +
 arch/arm/boot/dts/rk3036-evb.dts |   64 +
 arch/arm/boot/dts/rk3036.dtsi|  547 ++
 3 files changed, 612 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..87c8752 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -512,6 +512,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
 dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+   rk3036-evb.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
new file mode 100644
index 000..28a0336
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -0,0 +1,64 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+   model = "Rockchip RK3036 Evaluation board";
+   compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
+};
+
+&i2c1 {
+   status = "okay";
+
+   hym8563: hym8563@51 {
+   compatible = "haoyu,hym8563";
+   reg = <0x51>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   clock-output-names = "xin32k";
+   };
+};
+
+&uart2 {
+   status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
new file mode 100644
index 000..380fe10
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -0,0 +1,547 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicen

[PATCH v7 2/6] clk: rockchip: add dt-binding header for rk3036

[Xing Zheng]

Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.


Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v7: None

 include/dt-bindings/clock/rk3036-cru.h |  193 
 1 file changed, 193 insertions(+)
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/include/dt-bindings/clock/rk3036-cru.h 
b/include/dt-bindings/clock/rk3036-cru.h
new file mode 100644
index 000..a2763a6
--- /dev/null
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+
+/* core clocks */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_GPLL   3
+#define ARMCLK 4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU   64
+#define SCLK_SPI   65
+#define SCLK_SDMMC 68
+#define SCLK_SDIO  69
+#define SCLK_EMMC  71
+#define SCLK_NANDC 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S   82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER085
+#define SCLK_TIMER186
+#define SCLK_TIMER287
+#define SCLK_TIMER388
+#define SCLK_OTGPHY0   93
+#define SCLK_LCDC  100
+#define SCLK_HDMI  109
+#define SCLK_HEVC  111
+#define SCLK_I2S_OUT   113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV  115
+#define SCLK_EMMC_DRV  117
+#define SCLK_SDMMC_SAMPLE  118
+#define SCLK_SDIO_SAMPLE   119
+#define SCLK_EMMC_SAMPLE   121
+#define SCLK_PVTM_CORE  123
+#define SCLK_PVTM_GPU   124
+#define SCLK_PVTM_VIDEO 125
+#define SCLK_MAC   151
+#define SCLK_MACREF152
+#define SCLK_SFC   160
+
+/* aclk gates */
+#define ACLK_DMAC2 194
+#define ACLK_LCDC  197
+#define ACLK_VIO   203
+#define ACLK_VCODEC208
+#define ACLK_CPU   209
+#define ACLK_PERI  210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GRF   329
+#define PCLK_I2C0  332
+#define PCLK_I2C1  333
+#define PCLK_I2C2  334
+#define PCLK_SPI   338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_PWM   350
+#define PCLK_TIMER 353
+#define PCLK_HDMI  360
+#define PCLK_CPU   362
+#define PCLK_PERI  363
+#define PCLK_DDRUPCTL  364
+#define PCLK_WDT   368
+#define PCLK_ACODEC369
+
+/* hclk gates */
+#define HCLK_OTG0  449
+#define HCLK_OTG1  450
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO  457
+#define HCLK_EMMC  459
+#define HCLK_I2S   462
+#define HCLK_LCDC  465
+#define HCLK_ROM   467
+#define HCLK_VIO_BUS   472
+#define HCLK_VCODEC476
+#define HCLK_CPU   477
+#define HCLK_PERI  478
+
+#define CLK_NR_CLKS(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE0_DBG 4
+#define SRST_CORE1_DBG 5
+#define SRST_CORE0_POR 8
+#define SRST_CORE1_POR 9
+#define SRST_L2C   12
+#define SRST_TOPDBG13
+#define SRST_STRC_SYS_A14
+#define SRST_PD_CORE_NIU   15
+
+#define SRST_TIMER216
+#define SRST_CPUSYS_H  17
+#define SRST_AHB2APB_H 19
+#define SRST_TIMER320
+#define SRST_INTMEM21
+#define SRST_ROM   22
+#define SRST_PERI_NIU  23
+#define SRST_I2S   24
+#define SRST_DDR_PLL   25
+#define SRST_GPU_DLL   26
+#define SRST_TIMER027
+#define SRST_TIMER128
+#define SRST_CORE_DLL  29
+#define SRST_EFUSE_P   30
+#define SRST_ACODEC_P

[PATCH v7 1/6] dt-bindings: add documentation of rk3036 clock controller

[Xing Zheng]

Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.


Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
Acked-by: Rob Herring 
---

Changes in v7: None

 .../bindings/clock/rockchip,rk3036-cru.txt |   56 
 1 file changed, 56 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
new file mode 100644
index 000..ace0599
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,56 @@
+* Rockchip RK3036 Clock and Reset Unit
+
+The RK3036 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3036-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+
+Example: Clock controller node:
+
+   cru: cru@2000 {
+   compatible = "rockchip,rk3036-cru";
+   reg = <0x2000 0x1000>;
+   rockchip,grf = <&grf>;
+
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+   uart0: serial@2006 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2006 0x100>;
+   interrupts = ;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clocks = <&cru SCLK_UART0>;
+   };
-- 
1.7.9.5


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[PATCH v7 0/6] Build and support rk3036 SoC platform

[Xing Zheng]

Hi,
  We need to support rk3036 soc platform via upstream, there are
some primary parts for the initial release of minimum system: dts,
clk-pll, smp, and clock tree for rk3036, and additional, we can use
these startup and run to init processs.

Thanks.

Changed in v7:
- removed the patch "make sure timer5 is enabled on rk3036 platforms" (applied)
- removed the patch "add support smp for rk3036" (applied)

Changed in v6:
- add hardware timer in dtsi and some the aliases of basic modules

Changed in v5:
- don't use clk_ APIs in the pll init-callback

Changed in v4:
- add some basic IP modules on rk3036.dtsi
- optimized supporting smp codes

Changed in v3:
- optimized some codes based on v2
- removed the patch "initial set time for rtc-hym8563" (useless)
- removed the patch "pinctrl" (approved)

Changed in v2:
- based on v1, add clock controller documentation
- enable timer5 startup
- add smp for cpu1
- initial set time for rtc-hym8563

Changes in v1:
- add dts, pinctrl and clock tree for rk3036 soc platform

The patchset (6):
6) ARM: dts: enable smp for rk3036
5) ARM: dts: rockchip: add core rk3036 dts
4) clk: rockchip: add clock controller for rk3036
3) clk: rockchip: add new pll-type for rk3036 and similar socs
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller


Changes in v7:
Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 

Xing Zheng (6):
  dt-bindings: add documentation of rk3036 clock controller
  clk: rockchip: add dt-binding header for rk3036
  clk: rockchip: add new pll-type for rk3036 and similar socs
  clk: rockchip: add clock controller for rk3036
  ARM: dts: rockchip: add core rk3036 dts
  ARM: dts: enable smp for rk3036

 .../bindings/clock/rockchip,rk3036-cru.txt |   56 ++
 arch/arm/boot/dts/Makefile |1 +
 arch/arm/boot/dts/rk3036-evb.dts   |   64 +++
 arch/arm/boot/dts/rk3036.dtsi  |  552 
 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk-pll.c |  249 -
 drivers/clk/rockchip/clk-rk3036.c  |  478 +
 drivers/clk/rockchip/clk.h |   32 +-
 include/dt-bindings/clock/rk3036-cru.h |  193 +++
 9 files changed, 1624 insertions(+), 2 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
 create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

-- 
1.7.9.5


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Re: [PATCH v6 1/8] dt-bindings: add documentation of rk3036 clock controller

[Xing Zheng]

On 2015年11月05日 07:39, Heiko Stuebner wrote:

Hi,

Am Mittwoch, 4. November 2015, 20:18:16 schrieb Xing Zheng:

Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.

Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---

your recipient-list is missing the clock maintainers+lists - sorry for
not noticing this earlier.

While the devicetree-maintainers may Review it, we expect the clock-
maintainers to actually apply all 4 clock-related patches.

Same comment is true for
[PATCH v6 2/8] clk: rockchip: add dt-binding header for rk3036


Heiko


Sorry, and I will loop them in the next versioin.
Thanks.


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Re: [PATCH v6 6/8] ARM: rockchip: add support smp for rk3036

[Xing Zheng]

On 2015年11月05日 07:33, Heiko Stuebner wrote:

Am Mittwoch, 4. November 2015, 20:25:16 schrieb Xing Zheng:

From: Heiko Stuebner

The dual-core Cortex A7 rk3036 is a bit special in that it does not allow
to control the actual powerdomain of the cpu cores, while the rest of the
smp-bringup like reset control and entry address handling stays the same.
Its bigger sibling, the quad-core rk3128 again allows powerdomain control.

So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.

Signed-off-by: Heiko Stuebner
Tested-by: Xing Zheng
Signed-off-by: Xing Zheng

This patch can work standalone, so I took the liberty of applying it to my soc
branch for 4.5 already, so you don't need to resend it in future versions.




OK， thanks Heiko. :)

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[PATCH v6 7/8] ARM: dts: enable smp for rk3036

[Xing Zheng]

Enable smp for rk3036, and add the smp sram name for adapting.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v6: None

 arch/arm/boot/dts/rk3036.dtsi |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 380fe10..61b40dd 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -75,6 +75,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "rockchip,rk3036-smp";
 
cpu0: cpu@f00 {
device_type = "cpu";
@@ -157,6 +158,10 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1008 0x2000>;
+   smp-sram@0 {
+   compatible = "rockchip,rk3066-smp-sram";
+   reg = <0x00 0x10>;
+   };
};
 
cru: clock-controller@2000 {
-- 
1.7.9.5


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[PATCH v6 6/8] ARM: rockchip: add support smp for rk3036

[Xing Zheng]

From: Heiko Stuebner 

The dual-core Cortex A7 rk3036 is a bit special in that it does not allow
to control the actual powerdomain of the cpu cores, while the rest of the
smp-bringup like reset control and entry address handling stays the same.
Its bigger sibling, the quad-core rk3128 again allows powerdomain control.

So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.

Signed-off-by: Heiko Stuebner 
Tested-by: Xing Zheng 
Signed-off-by: Xing Zheng 
---

Changes in v6: None

 Documentation/devicetree/bindings/arm/cpus.txt |1 +
 arch/arm/mach-rockchip/platsmp.c   |   45 +---
 2 files changed, 34 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt 
b/Documentation/devicetree/bindings/arm/cpus.txt
index 3a07a87..8fb0749 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -200,6 +200,7 @@ nodes to be present and contain the properties described 
below.
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
+   "rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
 
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 3e7a4b7..5c138f9 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -42,6 +42,7 @@ static int ncores;
 #define PMU_PWRDN_SCU  4
 
 static struct regmap *pmu;
+static int has_pmu = true;
 
 static int pmu_power_domain_is_on(int pd)
 {
@@ -89,20 +90,23 @@ static int pmu_set_power_domain(int pd, bool on)
if (!IS_ERR(rstc) && !on)
reset_control_assert(rstc);
 
-   ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
-   if (ret < 0) {
-   pr_err("%s: could not update power domain\n", __func__);
-   return ret;
-   }
-
-   ret = -1;
-   while (ret != on) {
-   ret = pmu_power_domain_is_on(pd);
+   if (has_pmu) {
+   ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
if (ret < 0) {
-   pr_err("%s: could not read power domain state\n",
+   pr_err("%s: could not update power domain\n",
   __func__);
return ret;
}
+
+   ret = -1;
+   while (ret != on) {
+   ret = pmu_power_domain_is_on(pd);
+   if (ret < 0) {
+   pr_err("%s: could not read power domain 
state\n",
+  __func__);
+   return ret;
+   }
+   }
}
 
if (!IS_ERR(rstc)) {
@@ -122,7 +126,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 {
int ret;
 
-   if (!sram_base_addr || !pmu) {
+   if (!sram_base_addr || (has_pmu && !pmu)) {
pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
return -ENXIO;
}
@@ -275,7 +279,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int 
max_cpus)
return;
}
 
-   if (rockchip_smp_prepare_pmu())
+   if (has_pmu && rockchip_smp_prepare_pmu())
return;
 
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
@@ -318,6 +322,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int 
max_cpus)
pmu_set_power_domain(0 + i, false);
 }
 
+static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
+{
+   has_pmu = false;
+
+   rockchip_smp_prepare_cpus(max_cpus);
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 static int rockchip_cpu_kill(unsigned int cpu)
 {
@@ -340,6 +351,15 @@ static void rockchip_cpu_die(unsigned int cpu)
 }
 #endif
 
+static struct smp_operations rk3036_smp_ops __initdata = {
+   .smp_prepare_cpus   = rk3036_smp_prepare_cpus,
+   .smp_boot_secondary = rockchip_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+   .cpu_kill   = rockchip_cpu_kill,
+   .cpu_die= rockchip_cpu_die,
+#endif
+};
+
 static struct smp_operations rockchip_smp_ops __initdata = {
.smp_prepare_cpus   = rockchip_smp_prepare_cpus,
.smp_boot_secondary = rockchip_boot_secondary,
@@ -349,4 +369,5 @@ static struct smp_operations rockchip_smp_ops __initdata = {
 #endif
 };
 
+CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
 CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
-- 
1.7.9.5


--

[PATCH v6 5/8] ARM: dts: rockchip: add core rk3036 dts

[Xing Zheng]

Initial release for rk3036, node definitions rk3036 sdk board.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v6: None

 arch/arm/boot/dts/Makefile   |1 +
 arch/arm/boot/dts/rk3036-evb.dts |   64 +
 arch/arm/boot/dts/rk3036.dtsi|  547 ++
 3 files changed, 612 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..87c8752 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -512,6 +512,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
 dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+   rk3036-evb.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
new file mode 100644
index 000..28a0336
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -0,0 +1,64 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+   model = "Rockchip RK3036 Evaluation board";
+   compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
+};
+
+&i2c1 {
+   status = "okay";
+
+   hym8563: hym8563@51 {
+   compatible = "haoyu,hym8563";
+   reg = <0x51>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   clock-output-names = "xin32k";
+   };
+};
+
+&uart2 {
+   status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
new file mode 100644
index 000..380fe10
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -0,0 +1,547 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicen

[PATCH v6 2/8] clk: rockchip: add dt-binding header for rk3036

[Xing Zheng]

Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v6: None

 include/dt-bindings/clock/rk3036-cru.h |  193 
 1 file changed, 193 insertions(+)
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/include/dt-bindings/clock/rk3036-cru.h 
b/include/dt-bindings/clock/rk3036-cru.h
new file mode 100644
index 000..a2763a6
--- /dev/null
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+
+/* core clocks */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_GPLL   3
+#define ARMCLK 4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU   64
+#define SCLK_SPI   65
+#define SCLK_SDMMC 68
+#define SCLK_SDIO  69
+#define SCLK_EMMC  71
+#define SCLK_NANDC 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S   82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER085
+#define SCLK_TIMER186
+#define SCLK_TIMER287
+#define SCLK_TIMER388
+#define SCLK_OTGPHY0   93
+#define SCLK_LCDC  100
+#define SCLK_HDMI  109
+#define SCLK_HEVC  111
+#define SCLK_I2S_OUT   113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV  115
+#define SCLK_EMMC_DRV  117
+#define SCLK_SDMMC_SAMPLE  118
+#define SCLK_SDIO_SAMPLE   119
+#define SCLK_EMMC_SAMPLE   121
+#define SCLK_PVTM_CORE  123
+#define SCLK_PVTM_GPU   124
+#define SCLK_PVTM_VIDEO 125
+#define SCLK_MAC   151
+#define SCLK_MACREF152
+#define SCLK_SFC   160
+
+/* aclk gates */
+#define ACLK_DMAC2 194
+#define ACLK_LCDC  197
+#define ACLK_VIO   203
+#define ACLK_VCODEC208
+#define ACLK_CPU   209
+#define ACLK_PERI  210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GRF   329
+#define PCLK_I2C0  332
+#define PCLK_I2C1  333
+#define PCLK_I2C2  334
+#define PCLK_SPI   338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_PWM   350
+#define PCLK_TIMER 353
+#define PCLK_HDMI  360
+#define PCLK_CPU   362
+#define PCLK_PERI  363
+#define PCLK_DDRUPCTL  364
+#define PCLK_WDT   368
+#define PCLK_ACODEC369
+
+/* hclk gates */
+#define HCLK_OTG0  449
+#define HCLK_OTG1  450
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO  457
+#define HCLK_EMMC  459
+#define HCLK_I2S   462
+#define HCLK_LCDC  465
+#define HCLK_ROM   467
+#define HCLK_VIO_BUS   472
+#define HCLK_VCODEC476
+#define HCLK_CPU   477
+#define HCLK_PERI  478
+
+#define CLK_NR_CLKS(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE0_DBG 4
+#define SRST_CORE1_DBG 5
+#define SRST_CORE0_POR 8
+#define SRST_CORE1_POR 9
+#define SRST_L2C   12
+#define SRST_TOPDBG13
+#define SRST_STRC_SYS_A14
+#define SRST_PD_CORE_NIU   15
+
+#define SRST_TIMER216
+#define SRST_CPUSYS_H  17
+#define SRST_AHB2APB_H 19
+#define SRST_TIMER320
+#define SRST_INTMEM21
+#define SRST_ROM   22
+#define SRST_PERI_NIU  23
+#define SRST_I2S   24
+#define SRST_DDR_PLL   25
+#define SRST_GPU_DLL   26
+#define SRST_TIMER027
+#define SRST_TIMER128
+#define SRST_CORE_DLL  29
+#define SRST_EFUSE_P   30
+#define SRST_ACODEC_P

[PATCH v6 1/8] dt-bindings: add documentation of rk3036 clock controller

[Xing Zheng]

Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v6: None

 .../bindings/clock/rockchip,rk3036-cru.txt |   56 
 1 file changed, 56 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
new file mode 100644
index 000..ace0599
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,56 @@
+* Rockchip RK3036 Clock and Reset Unit
+
+The RK3036 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3036-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+
+Example: Clock controller node:
+
+   cru: cru@2000 {
+   compatible = "rockchip,rk3036-cru";
+   reg = <0x2000 0x1000>;
+   rockchip,grf = <&grf>;
+
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+   uart0: serial@2006 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2006 0x100>;
+   interrupts = ;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clocks = <&cru SCLK_UART0>;
+   };
-- 
1.7.9.5


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[PATCH v6 0/8] Build and support rk3036 SoC platform

[Xing Zheng]

Hi,
  We need to support rk3036 soc platform via upstream, there are
some primary parts for the initial release of minimum system: dts,
clk-pll, smp, and clock tree for rk3036, and additional, we can use
these startup and run to init processs.

Thanks.

Changed in v6:
- add hardware timer in dtsi and some the aliases of basic modules

Changed in v5:
- don't use clk_ APIs in the pll init-callback

Changed in v4:
- add some basic IP modules on rk3036.dtsi
- optimized supporting smp codes

Changed in v3:
- optimized some codes based on v2
- removed the patch "initial set time for rtc-hym8563" (useless)
- removed the patch "pinctrl" (approved)

Changed in v2:
- based on v1, add clock controller documentation
- enable timer5 startup
- add smp for cpu1
- initial set time for rtc-hym8563

Changes in v1:
- add dts, pinctrl and clock tree for rk3036 soc platform

The patchset (8):
8) rockchip: make sure timer5 is enabled on rk3036 platforms
7) ARM: dts: enable smp for rk3036
6) ARM: rockchip: add support smp for rk3036
5) ARM: dts: rockchip: add core rk3036 dts
4) clk: rockchip: add clock controller for rk3036
3) clk: rockchip: add new pll-type for rk3036 and similar socs
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller


Changes in v6:
Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 

Heiko Stuebner (1):
  ARM: rockchip: add support smp for rk3036

Xing Zheng (7):
  dt-bindings: add documentation of rk3036 clock controller
  clk: rockchip: add dt-binding header for rk3036
  clk: rockchip: add new pll-type for rk3036 and similar socs
  clk: rockchip: add clock controller for rk3036
  ARM: dts: rockchip: add core rk3036 dts
  ARM: dts: enable smp for rk3036
  rockchip: make sure timer5 is enabled on rk3036 platforms

 Documentation/devicetree/bindings/arm/cpus.txt |1 +
 .../bindings/clock/rockchip,rk3036-cru.txt |   56 ++
 arch/arm/boot/dts/Makefile |1 +
 arch/arm/boot/dts/rk3036-evb.dts   |   64 +++
 arch/arm/boot/dts/rk3036.dtsi  |  552 
 arch/arm/mach-rockchip/platsmp.c   |   45 +-
 arch/arm/mach-rockchip/rockchip.c  |   44 +-
 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk-pll.c |  249 -
 drivers/clk/rockchip/clk-rk3036.c  |  478 +
 drivers/clk/rockchip/clk.h |   32 +-
 include/dt-bindings/clock/rk3036-cru.h |  193 +++
 12 files changed, 1685 insertions(+), 31 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
 create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

-- 
1.7.9.5


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[PATCH v5 7/8] ARM: dts: enable smp for rk3036

[Xing Zheng]

Enable smp for rk3036, and add the smp sram name for adapting.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v5: None

 arch/arm/boot/dts/rk3036.dtsi |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 8f3a069..61352be 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -72,6 +72,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "rockchip,rk3036-smp";
 
cpu0: cpu@f00 {
device_type = "cpu";
@@ -146,6 +147,10 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1008 0x2000>;
+   smp-sram@0 {
+   compatible = "rockchip,rk3066-smp-sram";
+   reg = <0x00 0x10>;
+   };
};
 
cru: clock-controller@2000 {
-- 
1.7.9.5


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[PATCH v5 6/8] ARM: rockchip: add support smp for rk3036

[Xing Zheng]

From: Heiko Stuebner 

The dual-core Cortex A7 rk3036 is a bit special in that it does not allow
to control the actual powerdomain of the cpu cores, while the rest of the
smp-bringup like reset control and entry address handling stays the same.
Its bigger sibling, the quad-core rk3128 again allows powerdomain control.

So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.

Signed-off-by: Heiko Stuebner 
Tested-by: Xing Zheng 
Signed-off-by: Xing Zheng 
---

Changes in v5: None

 Documentation/devicetree/bindings/arm/cpus.txt |1 +
 arch/arm/mach-rockchip/platsmp.c   |   45 +---
 2 files changed, 34 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt 
b/Documentation/devicetree/bindings/arm/cpus.txt
index 91e6e5c..261cc27 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -198,6 +198,7 @@ nodes to be present and contain the properties described 
below.
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
+   "rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
 
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 3e7a4b7..5c138f9 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -42,6 +42,7 @@ static int ncores;
 #define PMU_PWRDN_SCU  4
 
 static struct regmap *pmu;
+static int has_pmu = true;
 
 static int pmu_power_domain_is_on(int pd)
 {
@@ -89,20 +90,23 @@ static int pmu_set_power_domain(int pd, bool on)
if (!IS_ERR(rstc) && !on)
reset_control_assert(rstc);
 
-   ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
-   if (ret < 0) {
-   pr_err("%s: could not update power domain\n", __func__);
-   return ret;
-   }
-
-   ret = -1;
-   while (ret != on) {
-   ret = pmu_power_domain_is_on(pd);
+   if (has_pmu) {
+   ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
if (ret < 0) {
-   pr_err("%s: could not read power domain state\n",
+   pr_err("%s: could not update power domain\n",
   __func__);
return ret;
}
+
+   ret = -1;
+   while (ret != on) {
+   ret = pmu_power_domain_is_on(pd);
+   if (ret < 0) {
+   pr_err("%s: could not read power domain 
state\n",
+  __func__);
+   return ret;
+   }
+   }
}
 
if (!IS_ERR(rstc)) {
@@ -122,7 +126,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 {
int ret;
 
-   if (!sram_base_addr || !pmu) {
+   if (!sram_base_addr || (has_pmu && !pmu)) {
pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
return -ENXIO;
}
@@ -275,7 +279,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int 
max_cpus)
return;
}
 
-   if (rockchip_smp_prepare_pmu())
+   if (has_pmu && rockchip_smp_prepare_pmu())
return;
 
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
@@ -318,6 +322,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int 
max_cpus)
pmu_set_power_domain(0 + i, false);
 }
 
+static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
+{
+   has_pmu = false;
+
+   rockchip_smp_prepare_cpus(max_cpus);
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 static int rockchip_cpu_kill(unsigned int cpu)
 {
@@ -340,6 +351,15 @@ static void rockchip_cpu_die(unsigned int cpu)
 }
 #endif
 
+static struct smp_operations rk3036_smp_ops __initdata = {
+   .smp_prepare_cpus   = rk3036_smp_prepare_cpus,
+   .smp_boot_secondary = rockchip_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+   .cpu_kill   = rockchip_cpu_kill,
+   .cpu_die= rockchip_cpu_die,
+#endif
+};
+
 static struct smp_operations rockchip_smp_ops __initdata = {
.smp_prepare_cpus   = rockchip_smp_prepare_cpus,
.smp_boot_secondary = rockchip_boot_secondary,
@@ -349,4 +369,5 @@ static struct smp_operations rockchip_smp_ops __initdata = {
 #endif
 };
 
+CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
 CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
-- 
1.7.9.5


--

[PATCH v5 5/8] ARM: dts: rockchip: add core rk3036 dts

[Xing Zheng]

Initial release for rk3036, node definitions rk3036 sdk board.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v5: None

 arch/arm/boot/dts/Makefile   |1 +
 arch/arm/boot/dts/rk3036-evb.dts |   64 +
 arch/arm/boot/dts/rk3036.dtsi|  536 ++
 3 files changed, 601 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7d3e495..3e4e089 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -510,6 +510,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
 dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+   rk3036-evb.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
new file mode 100644
index 000..28a0336
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -0,0 +1,64 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+   model = "Rockchip RK3036 Evaluation board";
+   compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
+};
+
+&i2c1 {
+   status = "okay";
+
+   hym8563: hym8563@51 {
+   compatible = "haoyu,hym8563";
+   reg = <0x51>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   clock-output-names = "xin32k";
+   };
+};
+
+&uart2 {
+   status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
new file mode 100644
index 000..8f3a069
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -0,0 +1,536 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicen

[PATCH v5 0/8] Build and support rk3036 SoC platform

[Xing Zheng]

Hi,
  We need to support rk3036 soc platform via upstream, there are
3 primary parts for the initial release of minimum system: dts,
pinctrl, and clock tree for rk3036, and additional, we can use
these startup and run to init processs.

Thanks.

Changed in v5:
- don't use clk_ APIs in the pll init-callback

Changed in v4:
- add some basic IP modules on rk3036.dtsi
- optimized supporting smp codes

Changed in v3:
- optimized some codes based on v2
- removed the patch "initial set time for rtc-hym8563" (useless)
- removed the patch "pinctrl" (approved)

Changed in v2:
- based on v1, add clock controller documentation
- enable timer5 startup
- add smp for cpu1
- initial set time for rtc-hym8563

Changes in v1:
- add dts, pinctrl and clock tree for rk3036 soc platform

The patchset (8):
8) rockchip: make sure timer5 is enabled on rk3036 platforms
7) ARM: dts: enable smp for rk3036
6) ARM: rockchip: add support smp for rk3036
5) ARM: dts: rockchip: add core rk3036 dts
4) clk: rockchip: add new pll-type for rk3036 and similar socs
3) clk: rockchip: add clock controller for rk3036
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller


Changes in v5:
Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 

Heiko Stuebner (1):
  ARM: rockchip: add support smp for rk3036

Xing Zheng (7):
  dt-bindings: add documentation of rk3036 clock controller
  clk: rockchip: add dt-binding header for rk3036
  clk: rockchip: add clock controller for rk3036
  clk: rockchip: add new pll-type for rk3036 and similar socs
  ARM: dts: rockchip: add core rk3036 dts
  ARM: dts: enable smp for rk3036
  rockchip: make sure timer5 is enabled on rk3036 platforms

 Documentation/devicetree/bindings/arm/cpus.txt |1 +
 .../bindings/clock/rockchip,rk3036-cru.txt |   56 ++
 arch/arm/boot/dts/Makefile |1 +
 arch/arm/boot/dts/rk3036-evb.dts   |   64 +++
 arch/arm/boot/dts/rk3036.dtsi  |  541 
 arch/arm/mach-rockchip/platsmp.c   |   45 +-
 arch/arm/mach-rockchip/rockchip.c  |   44 +-
 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk-pll.c |  249 -
 drivers/clk/rockchip/clk-rk3036.c  |  500 ++
 drivers/clk/rockchip/clk.h |   30 ++
 include/dt-bindings/clock/rk3036-cru.h |  195 +++
 12 files changed, 1697 insertions(+), 30 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
 create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

-- 
1.7.9.5


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[PATCH v5 2/8] clk: rockchip: add dt-binding header for rk3036

[Xing Zheng]

Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v5: None

 include/dt-bindings/clock/rk3036-cru.h |  195 
 1 file changed, 195 insertions(+)
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/include/dt-bindings/clock/rk3036-cru.h 
b/include/dt-bindings/clock/rk3036-cru.h
new file mode 100644
index 000..b0da216
--- /dev/null
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+
+/* core clocks */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_GPLL   3
+#define ARMCLK 4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU   64
+#define SCLK_SPI   65
+#define SCLK_SDMMC 68
+#define SCLK_SDIO  69
+#define SCLK_EMMC  71
+#define SCLK_NANDC 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S   82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER085
+#define SCLK_TIMER186
+#define SCLK_TIMER287
+#define SCLK_TIMER388
+#define SCLK_OTGPHY0   93
+#define SCLK_LCDC  100
+#define SCLK_HDMI  109
+#define SCLK_HEVC  111
+#define SCLK_I2S_OUT   113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV  115
+#define SCLK_EMMC_DRV  117
+#define SCLK_SDMMC_SAMPLE  118
+#define SCLK_SDIO_SAMPLE   119
+#define SCLK_EMMC_SAMPLE   121
+#define SCLK_PVTM_CORE  123
+#define SCLK_PVTM_GPU   124
+#define SCLK_PVTM_VIDEO 125
+#define SCLK_MAC   151
+#define SCLK_MACREF152
+#define SCLK_SFC   160
+
+#define DCLK_LCDC  190
+
+/* aclk gates */
+#define ACLK_DMAC2 194
+#define ACLK_LCDC  197
+#define ACLK_VIO   203
+#define ACLK_VCODEC208
+#define ACLK_CPU   209
+#define ACLK_PERI  210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GRF   329
+#define PCLK_I2C0  332
+#define PCLK_I2C1  333
+#define PCLK_I2C2  334
+#define PCLK_SPI   338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_PWM   350
+#define PCLK_TIMER 353
+#define PCLK_HDMI  360
+#define PCLK_CPU   362
+#define PCLK_PERI  363
+#define PCLK_DDRUPCTL  364
+#define PCLK_WDT   368
+#define PCLK_ACODEC369
+
+/* hclk gates */
+#define HCLK_OTG0  449
+#define HCLK_OTG1  450
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO  457
+#define HCLK_EMMC  459
+#define HCLK_I2S   462
+#define HCLK_LCDC  465
+#define HCLK_ROM   467
+#define HCLK_VIO_BUS   472
+#define HCLK_VCODEC476
+#define HCLK_CPU   477
+#define HCLK_PERI  478
+
+#define CLK_NR_CLKS(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE0_DBG 4
+#define SRST_CORE1_DBG 5
+#define SRST_CORE0_POR 8
+#define SRST_CORE1_POR 9
+#define SRST_L2C   12
+#define SRST_TOPDBG13
+#define SRST_STRC_SYS_A14
+#define SRST_PD_CORE_NIU   15
+
+#define SRST_TIMER216
+#define SRST_CPUSYS_H  17
+#define SRST_AHB2APB_H 19
+#define SRST_TIMER320
+#define SRST_INTMEM21
+#define SRST_ROM   22
+#define SRST_PERI_NIU  23
+#define SRST_I2S   24
+#define SRST_DDR_PLL   25
+#define SRST_GPU_DLL   26
+#define SRST_TIMER027
+#define SRST_TIMER128
+#define SRST_CORE_DLL  29
+#define SRST_EFUSE_P

[PATCH v5 1/8] dt-bindings: add documentation of rk3036 clock controller

[Xing Zheng]

Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v5: None

 .../bindings/clock/rockchip,rk3036-cru.txt |   56 
 1 file changed, 56 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
new file mode 100644
index 000..ace0599
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,56 @@
+* Rockchip RK3036 Clock and Reset Unit
+
+The RK3036 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3036-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+
+Example: Clock controller node:
+
+   cru: cru@2000 {
+   compatible = "rockchip,rk3036-cru";
+   reg = <0x2000 0x1000>;
+   rockchip,grf = <&grf>;
+
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+   uart0: serial@2006 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2006 0x100>;
+   interrupts = ;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clocks = <&cru SCLK_UART0>;
+   };
-- 
1.7.9.5


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[PATCH v4 7/8] ARM: dts: enable smp for rk3036

[Xing Zheng]

Enable smp for rk3036, and add the smp sram name for adapting.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v4: None

 arch/arm/boot/dts/rk3036.dtsi |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 8f3a069..61352be 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -72,6 +72,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "rockchip,rk3036-smp";
 
cpu0: cpu@f00 {
device_type = "cpu";
@@ -146,6 +147,10 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1008 0x2000>;
+   smp-sram@0 {
+   compatible = "rockchip,rk3066-smp-sram";
+   reg = <0x00 0x10>;
+   };
};
 
cru: clock-controller@2000 {
-- 
1.7.9.5


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[PATCH v4 6/8] ARM: rockchip: add support smp for rk3036

[Xing Zheng]

From: Heiko Stuebner 

The dual-core Cortex A7 rk3036 is a bit special in that it does not allow
to control the actual powerdomain of the cpu cores, while the rest of the
smp-bringup like reset control and entry address handling stays the same.
Its bigger sibling, the quad-core rk3128 again allows powerdomain control.

So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.

Signed-off-by: Heiko Stuebner 
Tested-by: Xing Zheng 
Signed-off-by: Xing Zheng 
---

Changes in v4: None

 Documentation/devicetree/bindings/arm/cpus.txt |1 +
 arch/arm/mach-rockchip/platsmp.c   |   45 +---
 2 files changed, 34 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt 
b/Documentation/devicetree/bindings/arm/cpus.txt
index 91e6e5c..261cc27 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -198,6 +198,7 @@ nodes to be present and contain the properties described 
below.
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
+   "rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
 
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 3e7a4b7..5c138f9 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -42,6 +42,7 @@ static int ncores;
 #define PMU_PWRDN_SCU  4
 
 static struct regmap *pmu;
+static int has_pmu = true;
 
 static int pmu_power_domain_is_on(int pd)
 {
@@ -89,20 +90,23 @@ static int pmu_set_power_domain(int pd, bool on)
if (!IS_ERR(rstc) && !on)
reset_control_assert(rstc);
 
-   ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
-   if (ret < 0) {
-   pr_err("%s: could not update power domain\n", __func__);
-   return ret;
-   }
-
-   ret = -1;
-   while (ret != on) {
-   ret = pmu_power_domain_is_on(pd);
+   if (has_pmu) {
+   ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
if (ret < 0) {
-   pr_err("%s: could not read power domain state\n",
+   pr_err("%s: could not update power domain\n",
   __func__);
return ret;
}
+
+   ret = -1;
+   while (ret != on) {
+   ret = pmu_power_domain_is_on(pd);
+   if (ret < 0) {
+   pr_err("%s: could not read power domain 
state\n",
+  __func__);
+   return ret;
+   }
+   }
}
 
if (!IS_ERR(rstc)) {
@@ -122,7 +126,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 {
int ret;
 
-   if (!sram_base_addr || !pmu) {
+   if (!sram_base_addr || (has_pmu && !pmu)) {
pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
return -ENXIO;
}
@@ -275,7 +279,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int 
max_cpus)
return;
}
 
-   if (rockchip_smp_prepare_pmu())
+   if (has_pmu && rockchip_smp_prepare_pmu())
return;
 
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
@@ -318,6 +322,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int 
max_cpus)
pmu_set_power_domain(0 + i, false);
 }
 
+static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
+{
+   has_pmu = false;
+
+   rockchip_smp_prepare_cpus(max_cpus);
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 static int rockchip_cpu_kill(unsigned int cpu)
 {
@@ -340,6 +351,15 @@ static void rockchip_cpu_die(unsigned int cpu)
 }
 #endif
 
+static struct smp_operations rk3036_smp_ops __initdata = {
+   .smp_prepare_cpus   = rk3036_smp_prepare_cpus,
+   .smp_boot_secondary = rockchip_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+   .cpu_kill   = rockchip_cpu_kill,
+   .cpu_die= rockchip_cpu_die,
+#endif
+};
+
 static struct smp_operations rockchip_smp_ops __initdata = {
.smp_prepare_cpus   = rockchip_smp_prepare_cpus,
.smp_boot_secondary = rockchip_boot_secondary,
@@ -349,4 +369,5 @@ static struct smp_operations rockchip_smp_ops __initdata = {
 #endif
 };
 
+CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
 CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
-- 
1.7.9.5


--

[PATCH v4 5/8] ARM: dts: rockchip: add core rk3036 dts

[Xing Zheng]

Initial release for rk3036, node definitions rk3036 sdk board.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v4: None

 arch/arm/boot/dts/Makefile   |1 +
 arch/arm/boot/dts/rk3036-evb.dts |   64 +
 arch/arm/boot/dts/rk3036.dtsi|  536 ++
 3 files changed, 601 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7d3e495..3e4e089 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -510,6 +510,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
 dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+   rk3036-evb.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
new file mode 100644
index 000..28a0336
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -0,0 +1,64 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+   model = "Rockchip RK3036 Evaluation board";
+   compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
+};
+
+&i2c1 {
+   status = "okay";
+
+   hym8563: hym8563@51 {
+   compatible = "haoyu,hym8563";
+   reg = <0x51>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   clock-output-names = "xin32k";
+   };
+};
+
+&uart2 {
+   status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
new file mode 100644
index 000..8f3a069
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -0,0 +1,536 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicen

[PATCH v4 1/8] dt-bindings: add documentation of rk3036 clock controller

[Xing Zheng]

Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v4: None

 .../bindings/clock/rockchip,rk3036-cru.txt |   56 
 1 file changed, 56 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
new file mode 100644
index 000..ace0599
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,56 @@
+* Rockchip RK3036 Clock and Reset Unit
+
+The RK3036 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3036-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+
+Example: Clock controller node:
+
+   cru: cru@2000 {
+   compatible = "rockchip,rk3036-cru";
+   reg = <0x2000 0x1000>;
+   rockchip,grf = <&grf>;
+
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+   uart0: serial@2006 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2006 0x100>;
+   interrupts = ;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clocks = <&cru SCLK_UART0>;
+   };
-- 
1.7.9.5


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[PATCH v4 0/8] Build and support rk3036 SoC platform

[Xing Zheng]

Hi,
  We need to support rk3036 soc platform via upstream, there are
3 primary parts for the initial release of minimum system: dts,
pinctrl, and clock tree for rk3036, and additional, we can use
these startup and run to init processs.

Thanks.

Changed in v4:
- add some basic IP modules on rk3036.dtsi
- optimized supporting smp codes

Changed in v3:
- optimized some codes based on v2
- removed the patch "initial set time for rtc-hym8563" (useless)
- removed the patch "pinctrl" (approved)

Changed in v2:
- based on v1, add clock controller documentation
- enable timer5 startup
- add smp for cpu1
- initial set time for rtc-hym8563

Changes in v1:
- add dts, pinctrl and clock tree for rk3036 soc platform

The patchset (8):
8) rockchip: make sure timer5 is enabled on rk3036 platforms
7) ARM: dts: enable smp for rk3036
6) ARM: rockchip: add support smp for rk3036
5) ARM: dts: rockchip: add core rk3036 dts
4) clk: rockchip: add new pll-type for rk3036 and similar socs
3) clk: rockchip: add clock controller for rk3036
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller


Changes in v4:
Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 

Heiko Stuebner (1):
  ARM: rockchip: add support smp for rk3036

Xing Zheng (7):
  dt-bindings: add documentation of rk3036 clock controller
  clk: rockchip: add dt-binding header for rk3036
  clk: rockchip: add clock controller for rk3036
  clk: rockchip: add new pll-type for rk3036 and similar socs
  ARM: dts: rockchip: add core rk3036 dts
  ARM: dts: enable smp for rk3036
  rockchip: make sure timer5 is enabled on rk3036 platforms

 Documentation/devicetree/bindings/arm/cpus.txt |1 +
 .../bindings/clock/rockchip,rk3036-cru.txt |   56 ++
 arch/arm/boot/dts/Makefile |1 +
 arch/arm/boot/dts/rk3036-evb.dts   |   64 +++
 arch/arm/boot/dts/rk3036.dtsi  |  541 
 arch/arm/mach-rockchip/platsmp.c   |   45 +-
 arch/arm/mach-rockchip/rockchip.c  |   44 +-
 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk-pll.c |  243 -
 drivers/clk/rockchip/clk-rk3036.c  |  500 ++
 drivers/clk/rockchip/clk.h |   30 ++
 include/dt-bindings/clock/rk3036-cru.h |  195 +++
 12 files changed, 1691 insertions(+), 30 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
 create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

-- 
1.7.9.5


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[PATCH v4 2/8] clk: rockchip: add dt-binding header for rk3036

[Xing Zheng]

Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v4: None

 include/dt-bindings/clock/rk3036-cru.h |  195 
 1 file changed, 195 insertions(+)
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/include/dt-bindings/clock/rk3036-cru.h 
b/include/dt-bindings/clock/rk3036-cru.h
new file mode 100644
index 000..b0da216
--- /dev/null
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+
+/* core clocks */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_GPLL   3
+#define ARMCLK 4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU   64
+#define SCLK_SPI   65
+#define SCLK_SDMMC 68
+#define SCLK_SDIO  69
+#define SCLK_EMMC  71
+#define SCLK_NANDC 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S   82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER085
+#define SCLK_TIMER186
+#define SCLK_TIMER287
+#define SCLK_TIMER388
+#define SCLK_OTGPHY0   93
+#define SCLK_LCDC  100
+#define SCLK_HDMI  109
+#define SCLK_HEVC  111
+#define SCLK_I2S_OUT   113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV  115
+#define SCLK_EMMC_DRV  117
+#define SCLK_SDMMC_SAMPLE  118
+#define SCLK_SDIO_SAMPLE   119
+#define SCLK_EMMC_SAMPLE   121
+#define SCLK_PVTM_CORE  123
+#define SCLK_PVTM_GPU   124
+#define SCLK_PVTM_VIDEO 125
+#define SCLK_MAC   151
+#define SCLK_MACREF152
+#define SCLK_SFC   160
+
+#define DCLK_LCDC  190
+
+/* aclk gates */
+#define ACLK_DMAC2 194
+#define ACLK_LCDC  197
+#define ACLK_VIO   203
+#define ACLK_VCODEC208
+#define ACLK_CPU   209
+#define ACLK_PERI  210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GRF   329
+#define PCLK_I2C0  332
+#define PCLK_I2C1  333
+#define PCLK_I2C2  334
+#define PCLK_SPI   338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_PWM   350
+#define PCLK_TIMER 353
+#define PCLK_HDMI  360
+#define PCLK_CPU   362
+#define PCLK_PERI  363
+#define PCLK_DDRUPCTL  364
+#define PCLK_WDT   368
+#define PCLK_ACODEC369
+
+/* hclk gates */
+#define HCLK_OTG0  449
+#define HCLK_OTG1  450
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO  457
+#define HCLK_EMMC  459
+#define HCLK_I2S   462
+#define HCLK_LCDC  465
+#define HCLK_ROM   467
+#define HCLK_VIO_BUS   472
+#define HCLK_VCODEC476
+#define HCLK_CPU   477
+#define HCLK_PERI  478
+
+#define CLK_NR_CLKS(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE0_DBG 4
+#define SRST_CORE1_DBG 5
+#define SRST_CORE0_POR 8
+#define SRST_CORE1_POR 9
+#define SRST_L2C   12
+#define SRST_TOPDBG13
+#define SRST_STRC_SYS_A14
+#define SRST_PD_CORE_NIU   15
+
+#define SRST_TIMER216
+#define SRST_CPUSYS_H  17
+#define SRST_AHB2APB_H 19
+#define SRST_TIMER320
+#define SRST_INTMEM21
+#define SRST_ROM   22
+#define SRST_PERI_NIU  23
+#define SRST_I2S   24
+#define SRST_DDR_PLL   25
+#define SRST_GPU_DLL   26
+#define SRST_TIMER027
+#define SRST_TIMER128
+#define SRST_CORE_DLL  29
+#define SRST_EFUSE_P

[PATCH v3 7/8] ARM: dts: enable smp for rk3036

[Xing Zheng]

Enable the rk3036's cpu1 and smp.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v3: None

 arch/arm/boot/dts/rk3036.dtsi |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index fea51de..ecd053d 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -72,6 +72,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "rockchip,rk3036-smp";
 
cpu0: cpu@f00 {
device_type = "cpu";
-- 
1.7.9.5


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[PATCH v3 4/8] dt-bindings: add documentation of rk3036 clock controller

[Xing Zheng]

Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v3: None

 .../bindings/clock/rockchip,rk3036-cru.txt |   56 
 1 file changed, 56 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
new file mode 100644
index 000..ace0599
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,56 @@
+* Rockchip RK3036 Clock and Reset Unit
+
+The RK3036 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3036-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+
+Example: Clock controller node:
+
+   cru: cru@2000 {
+   compatible = "rockchip,rk3036-cru";
+   reg = <0x2000 0x1000>;
+   rockchip,grf = <&grf>;
+
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+   uart0: serial@2006 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2006 0x100>;
+   interrupts = ;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clocks = <&cru SCLK_UART0>;
+   };
-- 
1.7.9.5


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[PATCH v3 1/8] ARM: dts: rockchip: add core rk3036 dts

[Xing Zheng]

Initial release for rk3036, node definitions rk3036 sdk board.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v3: None

 arch/arm/boot/dts/Makefile   |1 +
 arch/arm/boot/dts/rk3036-evb.dts |   64 +++
 arch/arm/boot/dts/rk3036.dtsi|  382 ++
 3 files changed, 447 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1c5f225..82e4caf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -499,6 +499,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
 dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+   rk3036-evb.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
new file mode 100644
index 000..645d144
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -0,0 +1,64 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+   model = "Rockchip RK3036 Evaluation board";
+   compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
+};
+
+&i2c1 {
+   status = "okay";
+
+hym8563: hym8563@51 {
+   compatible = "haoyu,hym8563";
+   reg = <0x51>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   clock-output-names = "xin32k";
+   };
+};
+
+&uart2 {
+   status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
new file mode 100644
index 000..fea51de
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -0,0 +1,382 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicen

[PATCH v3 3/8] clk: rockchip: add clock controller for rk3036

[Xing Zheng]

Add the clock tree definition for the new rk3036 SoC.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v3: None

 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk-rk3036.c  |  500 
 drivers/clk/rockchip/clk.h |   30 ++
 include/dt-bindings/clock/rk3036-cru.h |2 +-
 4 files changed, 532 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6..d599829 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
 obj-y  += clk-mmc-phase.o
 obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
 
+obj-y  += clk-rk3036.o
 obj-y  += clk-rk3188.o
 obj-y  += clk-rk3288.o
 obj-y  += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-rk3036.c 
b/drivers/clk/rockchip/clk-rk3036.c
new file mode 100644
index 000..6f49df3
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -0,0 +1,500 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner 
+ *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "clk.h"
+
+#define RK3036_GRF_SOC_STATUS0 0x14c
+
+enum rk3036_plls {
+   apll, dpll, gpll,
+};
+
+static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+   RK3036_PLL_RATE(158400, 1, 66, 1, 1, 1, 0),
+   RK3036_PLL_RATE(156000, 1, 65, 1, 1, 1, 0),
+   RK3036_PLL_RATE(153600, 1, 64, 1, 1, 1, 0),
+   RK3036_PLL_RATE(151200, 1, 63, 1, 1, 1, 0),
+   RK3036_PLL_RATE(148800, 1, 62, 1, 1, 1, 0),
+   RK3036_PLL_RATE(146400, 1, 61, 1, 1, 1, 0),
+   RK3036_PLL_RATE(144000, 1, 60, 1, 1, 1, 0),
+   RK3036_PLL_RATE(141600, 1, 59, 1, 1, 1, 0),
+   RK3036_PLL_RATE(139200, 1, 58, 1, 1, 1, 0),
+   RK3036_PLL_RATE(136800, 1, 57, 1, 1, 1, 0),
+   RK3036_PLL_RATE(134400, 1, 56, 1, 1, 1, 0),
+   RK3036_PLL_RATE(132000, 1, 55, 1, 1, 1, 0),
+   RK3036_PLL_RATE(129600, 1, 54, 1, 1, 1, 0),
+   RK3036_PLL_RATE(127200, 1, 53, 1, 1, 1, 0),
+   RK3036_PLL_RATE(124800, 1, 52, 1, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+   RK3036_PLL_RATE(118800, 2, 99, 1, 1, 1, 0),
+   RK3036_PLL_RATE(110400, 1, 46, 1, 1, 1, 0),
+   RK3036_PLL_RATE(11, 12, 550, 1, 1, 1, 0),
+   RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+   RK3036_PLL_RATE(10, 6, 500, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 98400, 1, 82, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 96000, 1, 80, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 93600, 1, 78, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 91200, 1, 76, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 9, 4, 300, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 88800, 1, 74, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 86400, 1, 72, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 84000, 1, 70, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 8, 6, 400, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 7, 6, 350, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 69600, 1, 58, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 6, 1, 75, 3, 1, 1, 0),
+   RK3036_PLL_RATE( 59400, 2, 99, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 50400, 1, 63, 3, 1, 1, 0),
+   RK3036_PLL_RATE( 5, 6, 250, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 40800, 1, 68, 2, 2, 1, 0),
+   RK3036_PLL_RATE( 31200, 1, 52, 2, 2, 1, 0),
+   RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
+   RK3036_PLL_RATE(  9600, 1, 64, 4, 4, 1, 0),
+   { /* sentinel */ },
+};
+
+#define RK3036_DIV_CPU_MASK0x1f
+#define RK3036_DIV_CPU_SHIFT   8
+
+#define RK3036_DIV_PERI_MASK   0xf
+#define RK3036_DIV_PERI_SHIFT  0
+#define RK3036_DIV_ACLK_MASK   0x7
+#define RK3036_DIV_ACLK_SHIFT  4
+#define RK3036_DIV_HCLK_MASK   0x3
+#define RK3036_DIV_HCLK_SHIFT  8
+#define RK3036_DIV_PCLK_MASK   0x7
+#define RK3036_DIV_PCLK_SHIFT  12
+
+#define RK3036_CLKSEL1(_core_

[PATCH v3 0/8] Build and support rk3036 SoC platform

[Xing Zheng]

Hi,
  We need to support rk3036 soc platform via upstream, there are
3 primary parts for the initial release of minimum system: dts,
pinctrl, and clock tree for rk3036, and additional, we can use
these startup and run to init processs.

Thanks.

Changed in v3:
- optimized some codes based on v2
- removed the patch "initial set time for rtc-hym8563" (useless)
- removed the patch "pinctrl" (approved)

Changed in v2:
- based on v1, add clock controller documentation
- enable timer5 startup
- add smp for cpu1
- initial set time for rtc-hym8563

Changes in v1:
- add dts, pinctrl and clock tree for rk3036 soc platform

The patchset (8):
8) rockchip: make sure timer5 is enabled on rk3036 platforms
7) ARM: dts: enable smp for rk3036
6) ARM: rockchip: add support smp for rk3036
5) clk: rockchip: add new clock type and controller for rk3036
4) dt-bindings: add documentation of rk3036 clock controller
3) clk: rockchip: add clock controller for rk3036
2) clk: rockchip: add dt-binding header for rk3036
1) ARM: dts: rockchip: add core rk3036 dts


Changes in v3:
Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 

Xing Zheng (8):
  ARM: dts: rockchip: add core rk3036 dts
  clk: rockchip: add dt-binding header for rk3036
  clk: rockchip: add clock controller for rk3036
  dt-bindings: add documentation of rk3036 clock controller
  clk: rockchip: add new clock type and controller for rk3036
  ARM: rockchip: add support smp for rk3036
  ARM: dts: enable smp for rk3036
  rockchip: make sure timer5 is enabled on rk3036 platforms

 .../bindings/clock/rockchip,rk3036-cru.txt |   56 +++
 arch/arm/boot/dts/Makefile |1 +
 arch/arm/boot/dts/rk3036-evb.dts   |   64 +++
 arch/arm/boot/dts/rk3036.dtsi  |  383 +++
 arch/arm/mach-rockchip/platsmp.c   |  142 ++
 arch/arm/mach-rockchip/rockchip.c  |   44 +-
 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk-pll.c |  243 +-
 drivers/clk/rockchip/clk-rk3036.c  |  500 
 drivers/clk/rockchip/clk.h |   30 ++
 include/dt-bindings/clock/rk3036-cru.h |  195 
 11 files changed, 1641 insertions(+), 18 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
 create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

-- 
1.7.9.5


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[PATCH v3 2/8] clk: rockchip: add dt-binding header for rk3036

[Xing Zheng]

Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.

Signed-off-by: Xing Zheng 
Reviewed-by: Heiko Stuebner 
---

Changes in v3: None

 include/dt-bindings/clock/rk3036-cru.h |  195 
 1 file changed, 195 insertions(+)
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/include/dt-bindings/clock/rk3036-cru.h 
b/include/dt-bindings/clock/rk3036-cru.h
new file mode 100644
index 000..6e30af4
--- /dev/null
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+
+/* core clocks */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_GPLL   3
+#define ARMCLK 4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU   64
+#define SCLK_SPI   65
+#define SCLK_SDMMC 68
+#define SCLK_SDIO  69
+#define SCLK_EMMC  71
+#define SCLK_NANDC 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S   82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER085
+#define SCLK_TIMER186
+#define SCLK_TIMER287
+#define SCLK_TIMER388
+#define SCLK_OTGPHY0   93
+#define SCLK_OTGPHY1   94
+#define SCLK_LCDC  100
+#define SCLK_HDMI  109
+#define SCLK_HEVC  111
+#define SCLK_I2S_OUT   113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV  115
+#define SCLK_EMMC_DRV  117
+#define SCLK_SDMMC_SAMPLE  118
+#define SCLK_SDIO_SAMPLE   119
+#define SCLK_EMMC_SAMPLE   121
+#define SCLK_PVTM_CORE  123
+#define SCLK_PVTM_GPU   124
+#define SCLK_PVTM_VIDEO 125
+#define SCLK_MAC   151
+#define SCLK_MACREF152
+#define SCLK_SFC   160
+
+#define DCLK_LCDC  190
+
+/* aclk gates */
+#define ACLK_DMAC2 194
+#define ACLK_LCDC  197
+#define ACLK_VIO   203
+#define ACLK_VCODEC208
+#define ACLK_CPU   209
+#define ACLK_PERI  210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GRF   329
+#define PCLK_I2C0  332
+#define PCLK_I2C1  333
+#define PCLK_I2C2  334
+#define PCLK_SPI   338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_PWM   350
+#define PCLK_TIMER 353
+#define PCLK_HDMI  360
+#define PCLK_CPU   362
+#define PCLK_PERI  363
+#define PCLK_DDRUPCTL  364
+#define PCLK_WDT   368
+
+/* hclk gates */
+#define HCLK_OTG0  449
+#define HCLK_OTG1  450
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO  457
+#define HCLK_EMMC  459
+#define HCLK_I2S   462
+#define HCLK_LCDC  465
+#define HCLK_ROM   467
+#define HCLK_VIO_BUS   472
+#define HCLK_VCODEC476
+#define HCLK_CPU   477
+#define HCLK_PERI  478
+
+#define CLK_NR_CLKS(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE0_DBG 4
+#define SRST_CORE1_DBG 5
+#define SRST_CORE0_POR 8
+#define SRST_CORE1_POR 9
+#define SRST_L2C   12
+#define SRST_TOPDBG13
+#define SRST_STRC_SYS_A14
+#define SRST_PD_CORE_NIU   15
+
+#define SRST_TIMER216
+#define SRST_CPUSYS_H  17
+#define SRST_AHB2APB_H 19
+#define SRST_TIMER320
+#define SRST_INTMEM21
+#define SRST_ROM   22
+#define SRST_PERI_NIU  23
+#define SRST_I2S   24
+#define SRST_DDR_PLL   25
+#define SRST_GPU_DLL   26
+#define SRST_TIMER027
+#define SRST_TIMER128
+#define SRST_CORE_DLL  29
+#define SRST_EFUSE_P

Re: [PATCH v2 5/9] dt-bindings: add documentation of rk3036 clock controller

[Xing Zheng]

On 2015年09月17日 23:09, Heiko Stübner wrote:

Am Donnerstag, 17. September 2015, 18:32:49 schrieb Xing Zheng:

Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.

Signed-off-by: Xing Zheng
---

Changes in v2: None

  .../bindings/clock/rockchip,rk3036-cru.txt |   60
 1 file changed, 60 insertions(+)
  create mode 100644
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt new file
mode 100644
index 000..ac3037a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,60 @@
+* Rockchip RK3036 Clock and Reset Unit
+
+The RK3036 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3036-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changable, due to the missing pll lock
status. +
+Each clock is assigned an identifier and client nodes can use this
identifier +to specify the clock which they consume. All available clocks
are defined as +preprocessor macros in the dt-bindings/clock/rk3036-cru.h
headers and can be +used in device tree sources. Similar macros exist for
the reset sources in +these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,

The rk3036 does not seem to use a rtc clock, so this should probably go away

Done.

+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_vip" - external VIP clock - optional,
+ - "ext_isp" - external ISP clock - optional,
+ - "ext_jtag" - external JTAG clock - optional

There do not seem to exist external clock sources for hsadc, vip, isp and jtag
in your clock tree?

missing here:
- ext_gmac

Yes, done.

+
+Example: Clock controller node:
+
+   cru: cru@2000 {
+   compatible = "rockchip,rk3036-cru";
+   reg =<0x2000 0x1000>;
+   rockchip,grf =<&grf>;
+
+   #clock-cells =<1>;
+   #reset-cells =<1>;
+   };
+
+Example: UART controller node that consumes the clock generated by the
clock +  controller:
+
+   uart0: serial@2006 {
+   compatible = "snps,dw-apb-uart";
+   reg =<0x2006 0x100>;
+   interrupts =;
+   reg-shift =<2>;
+   reg-io-width =<4>;
+   clocks =<&cru SCLK_UART0>;
+   };

Thanks.

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Re: [PATCH v2 2/9] clk: rockchip: add dt-binding header for rk3036

[Xing Zheng]

On 2015年09月17日 17:25, Heiko Stübner wrote:

Am Donnerstag, 17. September 2015, 16:28:53 schrieb Xing Zheng:

Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.

Signed-off-by: Xing Zheng
---

Changes in v2: None

  include/dt-bindings/clock/rk3036-cru.h |  198
 1 file changed, 198 insertions(+)
  create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/include/dt-bindings/clock/rk3036-cru.h
b/include/dt-bindings/clock/rk3036-cru.h new file mode 100644
index 000..b0033ef
--- /dev/null
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner

you can probably drop that copyright line ... I didn't do anything here ;-)

OK, done. :)



+ *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+
+/* core clocks */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_GPLL   3
+#define ARMCLK 4
+
+/* sclk gates (special clocks) */

you have a lot of gaps in the numbering ... intentional?
Oh, I think I referenced to "rk3288-cru.h" and cut some useless 
numbering from it for rk3036


otherwise
Reviewed-by: Heiko Stuebner

Done.

+#define SCLK_GPU   64
+#define SCLK_SPI   65
+#define SCLK_SDMMC 68
+#define SCLK_SDIO  69
+#define SCLK_EMMC  71
+#define SCLK_NANDC 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S   82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER085
+#define SCLK_TIMER186
+#define SCLK_TIMER287
+#define SCLK_TIMER388
+#define SCLK_OTGPHY0   93
+#define SCLK_OTGPHY1   94
+#define SCLK_LCDC  100
+#define SCLK_HDMI  109
+#define SCLK_HEVC  111
+#define SCLK_I2S_OUT   113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV  115
+#define SCLK_EMMC_DRV  117
+#define SCLK_SDMMC_SAMPLE  118
+#define SCLK_SDIO_SAMPLE   119
+#define SCLK_EMMC_SAMPLE   121
+#define SCLK_PVTM_CORE  123
+#define SCLK_PVTM_GPU   124
+#define SCLK_PVTM_VIDEO 125
+#define SCLK_MAC   151
+#define SCLK_MACREF152
+#define SCLK_SFC   160
+
+#define DCLK_LCDC  190
+
+/* aclk gates */
+#define ACLK_DMAC2 194
+#define ACLK_LCDC  197
+#define ACLK_VIO   203
+#define ACLK_VCODEC208
+#define ACLK_CPU   209
+#define ACLK_PERI  210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GRF   329
+#define PCLK_I2C0  332
+#define PCLK_I2C1  333
+#define PCLK_I2C2  334
+#define PCLK_SPI   338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_PWM   350
+#define PCLK_TIMER 353
+#define PCLK_HDMI  360
+#define PCLK_CPU   362
+#define PCLK_PERI  363
+#define PCLK_DDRUPCTL  364
+#define PCLK_WDT   368
+
+/* hclk gates */
+#define HCLK_OTG0  449
+#define HCLK_OTG1  450
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO  457
+#define HCLK_EMMC  459
+#define HCLK_I2S   462
+#define HCLK_LCDC  465
+#define HCLK_ROM   467
+#define HCLK_VIO_BUS   472
+#define HCLK_VCODEC476
+#define HCLK_CPU   477
+#define HCLK_PERI  478
+
+#define CLK_NR_CLKS(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE0_DBG 4
+#define SRST_CORE1_DBG 5
+#define SRST_CORE0_POR 8
+#define SRST_CORE1_POR 9
+#define SRST_L2C   12
+#define SRST_TOPDBG13
+#define SRST_STRC_SYS_A14
+#define SRST_PD_CORE_NIU   15
+
+#define SRST_TIMER

Re: [PATCH v2 1/9] ARM: dts: rockchip: add core rk3036 dts

[Xing Zheng]

On 2015年09月17日 17:18, Heiko Stübner wrote:

Am Donnerstag, 17. September 2015, 16:28:52 schrieb Xing Zheng:

Initial release for rk3036, node definitions rk3036 sdk board.

Signed-off-by: Xing Zheng
---

Changes in v2: None

  arch/arm/boot/dts/Makefile   |1 +
  arch/arm/boot/dts/rk3036-sdk.dts |   62 +++
  arch/arm/boot/dts/rk3036.dtsi|  381
++ 3 files changed, 444 insertions(+)
  create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts
  create mode 100644 arch/arm/boot/dts/rk3036.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d39ce4b..48260c4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -502,6 +502,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
+   rk3036-sdk.dtb \

ordering ... please put the rk3036 above rk3066 boards

Done.



rk3188-radxarock.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
diff --git a/arch/arm/boot/dts/rk3036-sdk.dts
b/arch/arm/boot/dts/rk3036-sdk.dts new file mode 100644
index 000..9187f93
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-sdk.dts

or "rk3036-evb.dts"? What is the actual board named?

Done, use rk3036-evb.dts

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c)  2015 Xing Zheng

this probably wants a Rockchip copyright notice?

Yes, remove this notice.

+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+   model = "SDK-RK3036";
+   compatible = "sdk,sdk-rk3036", "rockchip,rk3036";

model = "Rockchip RK3036-SDK";
compatible = "rockchip,rk3036-sdk", "rockchip,rk3036";

or

model = "Rockchip RK3036 Evaluation board";
compatible = "rockchip,rk3036-evb", "rockchip,rk3036";

depending on what the real board is labeled

Done.

+};
+
+&i2c1 {
+   status = "okay";
+
+hym8563: hym8563@51 {
+   compatible = "haoyu,hym8563";
+   reg =<0x51>;
+   #clock-cells =<0>;
+   clock-frequency =<32768>;
+   clock-output-names = "xin32k";
+   };
+};
\ No newline at end of file

missing newline as stated above

Done.

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
new file mode 100644
index 000..b7459c0
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -0,0 +1,381 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, 

[PATCH v2 6/9] pinctrl: rockchip: add support for the rk3036

[Xing Zheng]

Add new type for rk3036 and many parts of pinctrl rk3036 are similar
with rk2928's.

Signed-off-by: Xing Zheng 
---

Changes in v2: None

 .../bindings/pinctrl/rockchip,pinctrl.txt  |1 +
 drivers/pinctrl/pinctrl-rockchip.c |   17 +
 2 files changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 391ef4b..c73f2bb 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -22,6 +22,7 @@ Required properties for iomux controller:
   - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
   "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
   "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
+  "rockchip,rk3036-pinctrl"
   - rockchip,grf: phandle referencing a syscon providing the
 "general register files"
 
diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index c5246c0..9c49510 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2089,6 +2089,21 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
.pull_calc_reg  = rk2928_calc_pull_reg_and_bit,
 };
 
+static struct rockchip_pin_bank rk3036_pin_banks[] = {
+   PIN_BANK(0, 32, "gpio0"),
+   PIN_BANK(1, 32, "gpio1"),
+   PIN_BANK(2, 32, "gpio2"),
+};
+
+static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
+   .pin_banks  = rk3036_pin_banks,
+   .nr_banks   = ARRAY_SIZE(rk3036_pin_banks),
+   .label  = "RK3036-GPIO",
+   .type   = RK2928,
+   .grf_mux_offset = 0xa8,
+   .pull_calc_reg  = rk2928_calc_pull_reg_and_bit,
+};
+
 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@@ -2207,6 +,8 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,rk2928-pinctrl",
.data = (void *)&rk2928_pin_ctrl },
+   { .compatible = "rockchip,rk3036-pinctrl",
+   .data = (void *)&rk3036_pin_ctrl },
{ .compatible = "rockchip,rk3066a-pinctrl",
.data = (void *)&rk3066a_pin_ctrl },
{ .compatible = "rockchip,rk3066b-pinctrl",
-- 
1.7.9.5


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[PATCH v2 5/9] dt-bindings: add documentation of rk3036 clock controller

[Xing Zheng]

Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.

Signed-off-by: Xing Zheng 
---

Changes in v2: None

 .../bindings/clock/rockchip,rk3036-cru.txt |   60 
 1 file changed, 60 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
new file mode 100644
index 000..ac3037a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,60 @@
+* Rockchip RK3036 Clock and Reset Unit
+
+The RK3036 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3036-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_vip" - external VIP clock - optional,
+ - "ext_isp" - external ISP clock - optional,
+ - "ext_jtag" - external JTAG clock - optional
+
+Example: Clock controller node:
+
+   cru: cru@2000 {
+   compatible = "rockchip,rk3036-cru";
+   reg = <0x2000 0x1000>;
+   rockchip,grf = <&grf>;
+
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+   uart0: serial@2006 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2006 0x100>;
+   interrupts = ;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clocks = <&cru SCLK_UART0>;
+   };
-- 
1.7.9.5


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Re: [PATCH v1 1/3] ARM: dts: rockchip: add core rk3036 dts

[Xing Zheng]

On 2015年08月28日 16:59, Heiko Stuebner wrote:

Hi,

Am Freitag, 28. August 2015, 13:46:46 schrieb Xing Zheng:

Initial release for rk3036, node definitions rk3036 sdk board.

Signed-off-by: Xing Zheng
---

Changes in v1: None

  arch/arm/boot/dts/Makefile   |1 +
  arch/arm/boot/dts/rk3036-sdk.dts |  362
++ 2 files changed, 363 insertions(+)

as Eddie already said, please split into two files ... just look at the other
Rockchip socs for inspiration :-)

Done.

  create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6d7cec1..7014a3b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -501,6 +501,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
+   rk3036-sdk.dtb \
rk3188-radxarock.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
diff --git a/arch/arm/boot/dts/rk3036-sdk.dts
b/arch/arm/boot/dts/rk3036-sdk.dts new file mode 100644
index 000..0149c9a
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-sdk.dts
@@ -0,0 +1,362 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+   compatible = "rockchip,rk3036";
+
+   interrupt-parent =<&gic>;
+
+   aliases {
+   serial0 =&uart0;
+   serial1 =&uart1;
+   serial2 =&uart2;
+   };
+
+   memory {
+   reg =<0x6000 0x4000>;

missing
device_type = "memory";

Done.



+   };
+
+arm-pmu {
+compatible = "arm,cortex-a7-pmu";
+interrupts =,
+;

missing interrupt-affinity to map irq->cpu_core ?

Done.

+};
+
+   cpus {
+   #address-cells =<1>;
+   #size-cells =<0>;
+   //enable-method = "rockchip,rk3066-smp";

please don't leave commented code around


Done.

+
+   cpu@f00 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg =<0xf00>;
+   operating-points =<
+   /* KHzuV */
+816000 100
+   >;
+   #cooling-cells =<2>; /* min followed by max */
+   clock-latency =<4>;
+   clocks =<&cru ARMCLK>;
+   resets =<&cru SRST_CORE0>;
+   };
+   cpu@f01 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg =<0xf01>;
+   resets =<&cru SRST_CORE1>;
+  

Re: [PATCH v1 3/3] clk: rockchip: add clock controller for rk3036

[Xing Zheng]

On 2015年08月28日 17:54, Heiko Stuebner wrote:

Hi,

Am Freitag, 28. August 2015, 13:46:48 schrieb Xing Zheng:

Add the clock tree definition for the new rk3036 SoC,
but there are some issues to be fixed:
1. soc will crash if gpll run rate_change_remuxed
2. rk3036_clk_suspend and rk3036_clk_resume should be done
in clk-rk3036.c

---

Changes in v1:
Signed-off-by: Xing Zheng

  drivers/clk/rockchip/Makefile  |1 +
  drivers/clk/rockchip/clk-pll.c |  247 ++-

please split this into separate patches.
- addition of the new pll type
- three patches for binding-document, dt-binding header and clock controller
   like in "clk: rockchip: add support for the clock-tree of the rk3368"
   patches 4, 5 and 7:
   "dt-bindings: add documentation of rk3036 clock controller"
   "clk: rockchip: add dt-binding header for rk3036"
   "clk: rockchip: add rk3036 clock controller"

   so you should get in sum 4 clock patches.

[0]http://lists.infradead.org/pipermail/linux-rockchip/2015-July/003394.html

OK.

  drivers/clk/rockchip/clk-rk3036.c  |  539
 drivers/clk/rockchip/clk.h |
30 ++
  include/dt-bindings/clock/rk3036-cru.h |  247 +++
  5 files changed, 1063 insertions(+), 1 deletion(-)
  create mode 100644 drivers/clk/rockchip/clk-rk3036.c
  create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6..d599829 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
  obj-y += clk-mmc-phase.o
  obj-$(CONFIG_RESET_CONTROLLER)+= softrst.o

+obj-y  += clk-rk3036.o
  obj-y += clk-rk3188.o
  obj-y += clk-rk3288.o
  obj-y += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 96903ae..cf56826 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -2,6 +2,9 @@
   * Copyright (c) 2014 MundoReader S.L.
   * Author: Heiko Stuebner
   *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng
+ *
   * This program is free software; you can redistribute it and/or modify
   * it under the terms of the GNU General Public License as published by
   * the Free Software Foundation; either version 2 of the License, or
@@ -48,6 +51,8 @@ struct rockchip_clk_pll {
  #define to_rockchip_clk_pll_nb(nb) \
container_of(nb, struct rockchip_clk_pll, clk_nb)

+static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll);
+
  static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
struct rockchip_clk_pll *pll, unsigned long rate)
  {
@@ -90,6 +95,11 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll
*pll) unsigned int val;
int delay = 2400, ret;

+   /* the plls of rk3036 wait lock */
+   if (pll->type == pll_rk3036 || pll->lock_offset == -1) {
+   return rockchip_rk3036_pll_wait_lock(pll);
+   }
+

according to the rk3036 trm I have the GRF_SOC_STATUS0 [6:4] also contains the
pll lock status like on the other socs. So you could just use the default
mechanism of asking the GRF lock status like the other socs do, without
needing to override the wait_lock .

Oh, sorry, I missed this advice. I will check and test on next version.



while (delay>  0) {
ret = regmap_read(grf, pll->lock_offset,&val);
if (ret) {
@@ -305,6 +315,235 @@ static void rockchip_rk3066_pll_init(struct clk_hw
*hw) rockchip_rk3066_pll_set_rate(hw, drate, prate);
}
  }
+/**
+ * PLL used in RK3036
+ */
+
+#define RK3036_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1)
+
+#define RK3036_PLLCON(i)   (i * 0x4)
+#define RK3036_PLLCON0_FBDIV_MASK  0xfff
+#define RK3036_PLLCON0_FBDIV_SHIFT 0
+#define RK3036_PLLCON0_POSTDIV1_MASK   0x7
+#define RK3036_PLLCON0_POSTDIV1_SHIFT  12
+#define RK3036_PLLCON1_REFDIV_MASK 0x3f
+#define RK3036_PLLCON1_REFDIV_SHIFT0
+#define RK3036_PLLCON1_POSTDIV2_MASK   0x7
+#define RK3036_PLLCON1_POSTDIV2_SHIFT  6
+#define RK3036_PLLCON1_DSMPD_MASK  0x1
+#define RK3036_PLLCON1_DSMPD_SHIFT 12
+#define RK3036_PLLCON2_FRAC_MASK   0xff
+#define RK3036_PLLCON2_FRAC_SHIFT  0
+
+#define RK3036_MODECON 0x40
+#define RK3036_MODECON_AWM (1<<  0)  /* apll work mode */
+
+#define RK3036_PLLCON0_BYPASS  (1<<  15)
+#define RK3036_PLLCON1_LOCK_STATUS (1<<  10)
+#define RK3036_PLLCON1_RESET   (1<<  14)
+
+static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
+{
+   u32 pllcon;
+   int delay = 2400;
+
+   /* poll check the lock

[PATCH v2 1/9] ARM: dts: rockchip: add core rk3036 dts

[Xing Zheng]

Initial release for rk3036, node definitions rk3036 sdk board.

Signed-off-by: Xing Zheng 
---

Changes in v2: None

 arch/arm/boot/dts/Makefile   |1 +
 arch/arm/boot/dts/rk3036-sdk.dts |   62 +++
 arch/arm/boot/dts/rk3036.dtsi|  381 ++
 3 files changed, 444 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d39ce4b..48260c4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -502,6 +502,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
+   rk3036-sdk.dtb \
rk3188-radxarock.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
diff --git a/arch/arm/boot/dts/rk3036-sdk.dts b/arch/arm/boot/dts/rk3036-sdk.dts
new file mode 100644
index 000..9187f93
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-sdk.dts
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c)  2015 Xing Zheng 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+   model = "SDK-RK3036";
+   compatible = "sdk,sdk-rk3036", "rockchip,rk3036";
+};
+
+&i2c1 {
+   status = "okay";
+
+hym8563: hym8563@51 {
+   compatible = "haoyu,hym8563";
+   reg = <0x51>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   clock-output-names = "xin32k";
+   };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
new file mode 100644
index 000..b7459c0
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -0,0 +1,381 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Softw

[PATCH v2 0/9] Build and support rk3036 SoC platform

[Xing Zheng]

Hi,
we need to support rk3036 soc platform via upstream, there are
3 primary parts for the initial release of minimum system: dts,
pinctrl, and clock tree for rk3036, and additional, add a rtc
hym8563 patch to fix initial invaild, we can use these startup
and run to init processs.

Thanks.

changed in v2:
- based on v1, add clock controller documentation
- enable timer5 startup
- add smp for cpu1
- initial set time for rtc-hym8563

changes since v1:
- add dts, pinctrl and clock tree for rk3036 soc platform

The patchset (9):
9) rtc: hym8563: make sure hym8563 can be normal work
8) ARM: rockchip: add support smp for rk3036
7) rockchip: make sure timer5 is enabled on rk3036 platforms
6) pinctrl: rockchip: add support for the rk3036
5) dt-bindings: add documentation of rk3036 clock controller
4) clk: rockchip: add new clock type and controller for rk3036
3) clk: rockchip: add clock controller for rk3036
2) clk: rockchip: add dt-binding header for rk3036
1) ARM: dts: rockchip: add core rk3036 dts


Changes in v2:
Signed-off-by: Xing Zheng 

Xing Zheng (9):
  ARM: dts: rockchip: add core rk3036 dts
  clk: rockchip: add dt-binding header for rk3036
  clk: rockchip: add clock controller for rk3036
  clk: rockchip: add new clock type and controller for rk3036
  dt-bindings: add documentation of rk3036 clock controller
  pinctrl: rockchip: add support for the rk3036
  rockchip: make sure timer5 is enabled on rk3036 platforms
  ARM: rockchip: add support smp for rk3036
  rtc: hym8563: make sure hym8563 can be normal work

 .../bindings/clock/rockchip,rk3036-cru.txt |   60 +++
 .../bindings/pinctrl/rockchip,pinctrl.txt  |1 +
 arch/arm/boot/dts/Makefile |1 +
 arch/arm/boot/dts/rk3036-sdk.dts   |   62 +++
 arch/arm/boot/dts/rk3036.dtsi  |  381 +++
 arch/arm/mach-rockchip/platsmp.c   |  121 +
 arch/arm/mach-rockchip/rockchip.c  |   22 +
 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk-pll.c |  262 +-
 drivers/clk/rockchip/clk-rk3036.c  |  504 
 drivers/clk/rockchip/clk.h |   30 ++
 drivers/pinctrl/pinctrl-rockchip.c |   17 +
 drivers/rtc/rtc-hym8563.c  |   93 
 include/dt-bindings/clock/rk3036-cru.h |  198 
 14 files changed, 1752 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
 create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

-- 
1.7.9.5


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[PATCH v2 2/9] clk: rockchip: add dt-binding header for rk3036

[Xing Zheng]

Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.

Signed-off-by: Xing Zheng 
---

Changes in v2: None

 include/dt-bindings/clock/rk3036-cru.h |  198 
 1 file changed, 198 insertions(+)
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/include/dt-bindings/clock/rk3036-cru.h 
b/include/dt-bindings/clock/rk3036-cru.h
new file mode 100644
index 000..b0033ef
--- /dev/null
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner 
+ *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+
+/* core clocks */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_GPLL   3
+#define ARMCLK 4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU   64
+#define SCLK_SPI   65
+#define SCLK_SDMMC 68
+#define SCLK_SDIO  69
+#define SCLK_EMMC  71
+#define SCLK_NANDC 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S   82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER085
+#define SCLK_TIMER186
+#define SCLK_TIMER287
+#define SCLK_TIMER388
+#define SCLK_OTGPHY0   93
+#define SCLK_OTGPHY1   94
+#define SCLK_LCDC  100
+#define SCLK_HDMI  109
+#define SCLK_HEVC  111
+#define SCLK_I2S_OUT   113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV  115
+#define SCLK_EMMC_DRV  117
+#define SCLK_SDMMC_SAMPLE  118
+#define SCLK_SDIO_SAMPLE   119
+#define SCLK_EMMC_SAMPLE   121
+#define SCLK_PVTM_CORE  123
+#define SCLK_PVTM_GPU   124
+#define SCLK_PVTM_VIDEO 125
+#define SCLK_MAC   151
+#define SCLK_MACREF152
+#define SCLK_SFC   160
+
+#define DCLK_LCDC  190
+
+/* aclk gates */
+#define ACLK_DMAC2 194
+#define ACLK_LCDC  197
+#define ACLK_VIO   203
+#define ACLK_VCODEC208
+#define ACLK_CPU   209
+#define ACLK_PERI  210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GRF   329
+#define PCLK_I2C0  332
+#define PCLK_I2C1  333
+#define PCLK_I2C2  334
+#define PCLK_SPI   338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_PWM   350
+#define PCLK_TIMER 353
+#define PCLK_HDMI  360
+#define PCLK_CPU   362
+#define PCLK_PERI  363
+#define PCLK_DDRUPCTL  364
+#define PCLK_WDT   368
+
+/* hclk gates */
+#define HCLK_OTG0  449
+#define HCLK_OTG1  450
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO  457
+#define HCLK_EMMC  459
+#define HCLK_I2S   462
+#define HCLK_LCDC  465
+#define HCLK_ROM   467
+#define HCLK_VIO_BUS   472
+#define HCLK_VCODEC476
+#define HCLK_CPU   477
+#define HCLK_PERI  478
+
+#define CLK_NR_CLKS(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE0_DBG 4
+#define SRST_CORE1_DBG 5
+#define SRST_CORE0_POR 8
+#define SRST_CORE1_POR 9
+#define SRST_L2C   12
+#define SRST_TOPDBG13
+#define SRST_STRC_SYS_A14
+#define SRST_PD_CORE_NIU   15
+
+#define SRST_TIMER216
+#define SRST_CPUSYS_H  17
+#define SRST_AHB2APB_H 19
+#define SRST_TIMER320
+#define SRST_INTMEM21
+#define SRST_ROM   22
+#define SRST_PERI_NIU  23
+#define SRST_I2S   24
+#define SRST_DDR_PLL   25
+#define SRST_GPU_DLL   26
+#define SRST_TIMER027
+#define SRST_TIMER128
+#define

Re: [PATCH v1 0/3] Port and support rk3036 SoC platform

[Xing Zheng]

HI Heiko,
Thank you for your reply. I will improve them as quickly as possible.

Thanks. :)

On 2015年08月28日 17:59, Heiko Stuebner wrote:

Hi,

Am Freitag, 28. August 2015, 13:46:45 schrieb Xing Zheng:

We need to support rk3036 soc platform via upstream, there are
3 parts for the initial release of minimum system: dts, pinctrl,
and clock tree for rk3036, startup and run to init processs.

this is really cool that you're working on supporting the rk3036.
I had some comments to the individual patches, but overall it looks quite nice
already.


So, thanks for working on this
Heiko







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[PATCH v1 3/3] clk: rockchip: add clock controller for rk3036

[Xing Zheng]

Add the clock tree definition for the new rk3036 SoC,
but there are some issues to be fixed:
1. soc will crash if gpll run rate_change_remuxed
2. rk3036_clk_suspend and rk3036_clk_resume should be done
   in clk-rk3036.c

---

Changes in v1:
Signed-off-by: Xing Zheng 

 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk-pll.c |  247 ++-
 drivers/clk/rockchip/clk-rk3036.c  |  539 
 drivers/clk/rockchip/clk.h |   30 ++
 include/dt-bindings/clock/rk3036-cru.h |  247 +++
 5 files changed, 1063 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6..d599829 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
 obj-y  += clk-mmc-phase.o
 obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
 
+obj-y  += clk-rk3036.o
 obj-y  += clk-rk3188.o
 obj-y  += clk-rk3288.o
 obj-y  += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 96903ae..cf56826 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -2,6 +2,9 @@
  * Copyright (c) 2014 MundoReader S.L.
  * Author: Heiko Stuebner 
  *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -48,6 +51,8 @@ struct rockchip_clk_pll {
 #define to_rockchip_clk_pll_nb(nb) \
container_of(nb, struct rockchip_clk_pll, clk_nb)
 
+static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll);
+
 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
struct rockchip_clk_pll *pll, unsigned long rate)
 {
@@ -90,6 +95,11 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll 
*pll)
unsigned int val;
int delay = 2400, ret;
 
+   /* the plls of rk3036 wait lock */
+   if (pll->type == pll_rk3036 || pll->lock_offset == -1) {
+   return rockchip_rk3036_pll_wait_lock(pll);
+   }
+
while (delay > 0) {
ret = regmap_read(grf, pll->lock_offset, &val);
if (ret) {
@@ -305,6 +315,235 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw)
rockchip_rk3066_pll_set_rate(hw, drate, prate);
}
 }
+/**
+ * PLL used in RK3036
+ */
+
+#define RK3036_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1)
+
+#define RK3036_PLLCON(i)   (i * 0x4)
+#define RK3036_PLLCON0_FBDIV_MASK  0xfff
+#define RK3036_PLLCON0_FBDIV_SHIFT 0
+#define RK3036_PLLCON0_POSTDIV1_MASK   0x7
+#define RK3036_PLLCON0_POSTDIV1_SHIFT  12
+#define RK3036_PLLCON1_REFDIV_MASK 0x3f
+#define RK3036_PLLCON1_REFDIV_SHIFT0
+#define RK3036_PLLCON1_POSTDIV2_MASK   0x7
+#define RK3036_PLLCON1_POSTDIV2_SHIFT  6
+#define RK3036_PLLCON1_DSMPD_MASK  0x1
+#define RK3036_PLLCON1_DSMPD_SHIFT 12
+#define RK3036_PLLCON2_FRAC_MASK   0xff
+#define RK3036_PLLCON2_FRAC_SHIFT  0
+
+#define RK3036_MODECON 0x40
+#define RK3036_MODECON_AWM (1 << 0)  /* apll work mode */
+
+#define RK3036_PLLCON0_BYPASS  (1 << 15)
+#define RK3036_PLLCON1_LOCK_STATUS (1 << 10)
+#define RK3036_PLLCON1_RESET   (1 << 14)
+
+static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
+{
+   u32 pllcon;
+   int delay = 2400;
+
+   /* poll check the lock status in rk3036 xPLLCON1 */
+   while (delay > 0) {
+   pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
+   if (pllcon & RK3036_PLLCON1_LOCK_STATUS)
+   return 0;
+
+   delay--;
+   }
+
+   pr_err("%s: timeout waiting for pll to lock\n", __func__);
+   return -ETIMEDOUT;
+}
+
+static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
+unsigned long prate)
+{
+   struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+   unsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac;
+   u64 rate64 = prate;
+   u32 pllcon;
+
+   pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
+   fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) & 
RK3036_PLLCON0_FBDIV_MASK);
+   postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) & 
RK3036_PLLCON0_POSTDIV1_MASK);
+
+   pllcon = readl_relaxed(pll->

[PATCH v1 1/3] ARM: dts: rockchip: add core rk3036 dts

[Xing Zheng]

Initial release for rk3036, node definitions rk3036 sdk board.

Signed-off-by: Xing Zheng 
---

Changes in v1: None

 arch/arm/boot/dts/Makefile   |1 +
 arch/arm/boot/dts/rk3036-sdk.dts |  362 ++
 2 files changed, 363 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6d7cec1..7014a3b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -501,6 +501,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
+   rk3036-sdk.dtb \
rk3188-radxarock.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
diff --git a/arch/arm/boot/dts/rk3036-sdk.dts b/arch/arm/boot/dts/rk3036-sdk.dts
new file mode 100644
index 000..0149c9a
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-sdk.dts
@@ -0,0 +1,362 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "skeleton.dtsi"
+
+/ {
+   compatible = "rockchip,rk3036";
+
+   interrupt-parent = <&gic>;
+
+   aliases {
+   serial0 = &uart0;
+   serial1 = &uart1;
+   serial2 = &uart2;
+   };
+
+   memory {
+   reg = <0x6000 0x4000>;
+   };
+
+arm-pmu {
+compatible = "arm,cortex-a7-pmu";
+interrupts = ,
+ ;
+};
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   //enable-method = "rockchip,rk3066-smp";
+
+   cpu@f00 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0xf00>;
+   operating-points = <
+   /* KHzuV */
+816000 100
+   >;
+   #cooling-cells = <2>; /* min followed by max */
+   clock-latency = <4>;
+   clocks = <&cru ARMCLK>;
+   resets = <&cru SRST_CORE0>;
+   };
+   cpu@f01 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0xf01>;
+   resets = <&cru SRST_CORE1>;
+   };
+   };
+
+   amba {
+   compatible = "arm,amba-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+pdma: pdma@20078000 {
+compatible = "arm,pl330", "arm,primecell";
+reg = <

[PATCH v1 0/3] Port and support rk3036 SoC platform

[Xing Zheng]

Hi,
We need to support rk3036 soc platform via upstream, there are
3 parts for the initial release of minimum system: dts, pinctrl,
and clock tree for rk3036, startup and run to init processs.

Thanks.


Changes in v1:
Signed-off-by: Xing Zheng 

Xing Zheng (3):
  ARM: dts: rockchip: add core rk3036 dts
  pinctrl: rockchip: add support for the rk3036
  clk: rockchip: add clock controller for rk3036

 arch/arm/boot/dts/Makefile |1 +
 arch/arm/boot/dts/rk3036-sdk.dts   |  362 +
 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk-pll.c |  247 ++-
 drivers/clk/rockchip/clk-rk3036.c  |  539 
 drivers/clk/rockchip/clk.h |   30 ++
 drivers/pinctrl/pinctrl-rockchip.c |   17 +
 include/dt-bindings/clock/rk3036-cru.h |  247 +++
 8 files changed, 1443 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

-- 
1.7.9.5


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[PATCH v3 1/2] ASoC: rockchip: Add machine driver for max98090 codec

[Xing Zheng]

From: zhengxing 

The driver is used for rockchip board using a max98090.

Reviewed-by: Dylan Reid 
Signed-off-by: zhengxing 
---

Changes in v3: None

 .../bindings/sound/rockchip-max98090.txt   |   19 ++
 sound/soc/rockchip/Kconfig |   10 +
 sound/soc/rockchip/Makefile|4 +
 sound/soc/rockchip/rockchip_max98090.c |  236 
 4 files changed, 269 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/sound/rockchip-max98090.txt
 create mode 100644 sound/soc/rockchip/rockchip_max98090.c

diff --git a/Documentation/devicetree/bindings/sound/rockchip-max98090.txt 
b/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
new file mode 100644
index 000..a805aa9
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
@@ -0,0 +1,19 @@
+ROCKCHIP with MAX98090 CODEC
+
+Required properties:
+- compatible: "rockchip,rockchip-audio-max98090"
+- rockchip,model: The user-visible name of this sound complex
+- rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
+  connected to the CODEC
+- rockchip,audio-codec: The phandle of the MAX98090 audio codec
+- rockchip,headset-codec: The phandle of Ext chip for jack detection
+
+Example:
+
+sound {
+   compatible = "rockchip,rockchip-audio-max98090";
+   rockchip,model = "ROCKCHIP-I2S";
+   rockchip,i2s-controller = <&i2s>;
+   rockchip,audio-codec = <&max98090>;
+   rockchip,headset-codec = <&headsetcodec>;
+};
diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index e181826..d123566 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -14,3 +14,13 @@ config SND_SOC_ROCKCHIP_I2S
  Say Y or M if you want to add support for I2S driver for
  Rockchip I2S device. The device supports upto maximum of
  8 channels each for play and record.
+
+config SND_SOC_ROCKCHIP_MAX98090
+   tristate "ASoC support for Rockchip boards using a MAX98090 codec"
+   depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB
+   select SND_SOC_ROCKCHIP_I2S
+   select SND_SOC_MAX98090
+   select SND_SOC_TS3A227E
+   help
+ Say Y or M here if you want to add support for SoC audio on Rockchip
+ boards using the MAX98090 codec, such as Veyron.
diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile
index b921909..df3445b 100644
--- a/sound/soc/rockchip/Makefile
+++ b/sound/soc/rockchip/Makefile
@@ -2,3 +2,7 @@
 snd-soc-i2s-objs := rockchip_i2s.o
 
 obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S) += snd-soc-i2s.o
+
+snd-soc-rockchip-max98090-objs := rockchip_max98090.o
+
+obj-$(CONFIG_SND_SOC_ROCKCHIP_MAX98090) += snd-soc-rockchip-max98090.o
diff --git a/sound/soc/rockchip/rockchip_max98090.c 
b/sound/soc/rockchip/rockchip_max98090.c
new file mode 100644
index 000..acace20
--- /dev/null
+++ b/sound/soc/rockchip/rockchip_max98090.c
@@ -0,0 +1,236 @@
+/*
+ * Rockchip machine ASoC driver for boards using a MAX90809 CODEC.
+ *
+ * Copyright (c) 2014, ROCKCHIP CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rockchip_i2s.h"
+#include "../codecs/ts3a227e.h"
+
+#define DRV_NAME "rockchip-snd-max98090"
+
+static struct snd_soc_jack headset_jack;
+static struct snd_soc_jack_pin headset_jack_pins[] = {
+   {
+   .pin = "Headset Jack",
+   .mask = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
+   SND_JACK_BTN_0 | SND_JACK_BTN_1 |
+   SND_JACK_BTN_2 | SND_JACK_BTN_3,
+   },
+};
+
+static const struct snd_soc_dapm_widget rk_dapm_widgets[] = {
+   SND_SOC_DAPM_HP("Headphone", NULL),
+   SND_SOC_DAPM_MIC("Headset Mic", NULL),
+   SND_SOC_DAPM_MIC("Int Mic", NULL),
+   SND_SOC_DAPM_SPK("Speaker", NULL),
+};
+
+static const struct snd_soc_dapm_route rk_audio_map[] = {
+   {"IN34", NULL, "Headset Mic"},
+   {"IN34", NULL, "MICBIAS"},
+   {"MICBIAS", NULL, "Headset Mic"},
+   {"DMICL", NULL, "Int Mic"},
+   {"Headphone", NULL, "HPL"},
+   {"Headphone", NULL, "HPR"},
+   {"Speaker", NULL, "SPKL"},
+   {"Speaker", NULL, "SPKR"},
+};
+
+static const struct snd_kcontrol_new rk_mc_controls[] = {
+   SOC_DAPM_PIN_SWITCH("Hea

[PATCH v3 2/2] ASoC: rockchip: Add machine driver for rt5645/rt5650 codec

[Xing Zheng]

{"Headphones", NULL, "HPOL"},
+   {"Speakers", NULL, "SPOL"},
+   {"Speakers", NULL, "SPOR"},
+};
+
+static const struct snd_kcontrol_new rk_mc_controls[] = {
+   SOC_DAPM_PIN_SWITCH("Headphones"),
+   SOC_DAPM_PIN_SWITCH("Speakers"),
+   SOC_DAPM_PIN_SWITCH("Headset Mic"),
+   SOC_DAPM_PIN_SWITCH("Int Mic"),
+};
+
+static int rk_aif1_hw_params(struct snd_pcm_substream *substream,
+struct snd_pcm_hw_params *params)
+{
+   int ret = 0;
+   struct snd_soc_pcm_runtime *rtd = substream->private_data;
+   struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+   struct snd_soc_dai *codec_dai = rtd->codec_dai;
+   int mclk;
+
+   switch (params_rate(params)) {
+   case 8000:
+   case 16000:
+   case 48000:
+   case 96000:
+   mclk = 12288000;
+   break;
+   case 44100:
+   mclk = 11289600;
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
+SND_SOC_CLOCK_OUT);
+   if (ret < 0) {
+   dev_err(codec_dai->dev, "Can't set codec clock %d\n", ret);
+   return ret;
+   }
+
+   ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
+SND_SOC_CLOCK_IN);
+   if (ret < 0) {
+   dev_err(codec_dai->dev, "Can't set codec clock %d\n", ret);
+   return ret;
+   }
+
+   return ret;
+}
+
+static int rk_init(struct snd_soc_pcm_runtime *runtime)
+{
+   struct snd_soc_card *card = runtime->card;
+   int ret;
+
+   /* Enable Headset and 4 Buttons Jack detection */
+   ret = snd_soc_card_jack_new(card, "Headset Jack",
+   SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
+   SND_JACK_BTN_0 | SND_JACK_BTN_1 |
+   SND_JACK_BTN_2 | SND_JACK_BTN_3,
+   &headset_jack, NULL, 0);
+   if (!ret) {
+   dev_err(card->dev, "New Headset Jack failed! (%d)\n", ret);
+   return ret;
+   }
+
+   return rt5645_set_jack_detect(runtime->codec,
+&headset_jack,
+&headset_jack,
+&headset_jack);
+}
+
+static struct snd_soc_ops rk_aif1_ops = {
+   .hw_params = rk_aif1_hw_params,
+};
+
+static struct snd_soc_dai_link rk_dailink = {
+   .name = "rt5645",
+   .stream_name = "rt5645 PCM",
+   .codec_dai_name = "rt5645-aif1",
+   .init = rk_init,
+   .ops = &rk_aif1_ops,
+   /* set rt5645 as slave */
+   .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+   SND_SOC_DAIFMT_CBS_CFS,
+};
+
+static struct snd_soc_card snd_soc_card_rk = {
+   .name = "I2S-RT5650",
+   .dai_link = &rk_dailink,
+   .num_links = 1,
+   .dapm_widgets = rk_dapm_widgets,
+   .num_dapm_widgets = ARRAY_SIZE(rk_dapm_widgets),
+   .dapm_routes = rk_audio_map,
+   .num_dapm_routes = ARRAY_SIZE(rk_audio_map),
+   .controls = rk_mc_controls,
+   .num_controls = ARRAY_SIZE(rk_mc_controls),
+};
+
+static int snd_rk_mc_probe(struct platform_device *pdev)
+{
+   int ret = 0;
+   struct snd_soc_card *card = &snd_soc_card_rk;
+   struct device_node *np = pdev->dev.of_node;
+
+   /* register the soc card */
+   card->dev = &pdev->dev;
+
+   rk_dailink.codec_of_node = of_parse_phandle(np,
+   "rockchip,audio-codec", 0);
+   if (!rk_dailink.codec_of_node) {
+   dev_err(&pdev->dev,
+   "Property 'rockchip,audio-codec' missing or invalid\n");
+   return -EINVAL;
+   }
+
+   rk_dailink.cpu_of_node = of_parse_phandle(np,
+   "rockchip,i2s-controller", 0);
+   if (!rk_dailink.cpu_of_node) {
+   dev_err(&pdev->dev,
+   "Property 'rockchip,i2s-controller' missing or 
invalid\n");
+   return -EINVAL;
+   }
+
+   rk_dailink.platform_of_node = rk_dailink.cpu_of_node;
+
+   ret = snd_soc_of_parse_card_name(card, "rockchip,model");
+   if (ret) {
+   dev_err(&pdev->dev,
+   "Soc parse card name failed %d\n", ret);
+   return ret;
+   }
+
+   ret = devm_snd_soc_register_card(&pdev->dev, card);
+   if (ret) {
+   dev_err(&pdev->dev,
+   "Soc register card failed %d\n", ret);
+   return ret;
+

[PATCH v3 0/2] Add codec machine driver for rockchip platform

[Xing Zheng]

From: zhengxing 


Hi,
  The simple-card is not common at present, soc maybe need own machine
driver for jack detection.
  Add drivers for two families of rockchip-bases chromebooks. These
machine drives don't use simplecard because we need custom jack
detection plumbing.

- use ts3a227e for ext jack detection with max98090
- call rt5645_set_jack_detect function via rt5645 codec driver

Thanks.


Changes in v3:
Signed-off-by: zhengxing 

zhengxing (2):
  ASoC: rockchip: Add machine driver for max98090 codec
  ASoC: rockchip: Add machine driver for rt5645/rt5650 codec

 .../bindings/sound/rockchip-max98090.txt   |   19 ++
 .../devicetree/bindings/sound/rockchip-rt5645.txt  |   17 ++
 sound/soc/rockchip/Kconfig |   19 ++
 sound/soc/rockchip/Makefile|6 +
 sound/soc/rockchip/rockchip_max98090.c |  236 
 sound/soc/rockchip/rockchip_rt5645.c   |  225 +++
 6 files changed, 522 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/sound/rockchip-max98090.txt
 create mode 100644 Documentation/devicetree/bindings/sound/rockchip-rt5645.txt
 create mode 100644 sound/soc/rockchip/rockchip_max98090.c
 create mode 100644 sound/soc/rockchip/rockchip_rt5645.c

-- 
1.7.9.5


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[PATCH v3 1/2] ASoC: rockchip: Add machine driver for max98090 codec

[Xing Zheng]

From: zhengxing 

The driver is used for rockchip board using a max98090.

Reviewed-by: Dylan Reid 
Signed-off-by: zhengxing 
---

Changes in v3: None

 .../bindings/sound/rockchip-max98090.txt   |   19 ++
 sound/soc/rockchip/Kconfig |   10 +
 sound/soc/rockchip/Makefile|4 +
 sound/soc/rockchip/rockchip_max98090.c |  236 
 4 files changed, 269 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/sound/rockchip-max98090.txt
 create mode 100644 sound/soc/rockchip/rockchip_max98090.c

diff --git a/Documentation/devicetree/bindings/sound/rockchip-max98090.txt 
b/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
new file mode 100644
index 000..a805aa9
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
@@ -0,0 +1,19 @@
+ROCKCHIP with MAX98090 CODEC
+
+Required properties:
+- compatible: "rockchip,rockchip-audio-max98090"
+- rockchip,model: The user-visible name of this sound complex
+- rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
+  connected to the CODEC
+- rockchip,audio-codec: The phandle of the MAX98090 audio codec
+- rockchip,headset-codec: The phandle of Ext chip for jack detection
+
+Example:
+
+sound {
+   compatible = "rockchip,rockchip-audio-max98090";
+   rockchip,model = "ROCKCHIP-I2S";
+   rockchip,i2s-controller = <&i2s>;
+   rockchip,audio-codec = <&max98090>;
+   rockchip,headset-codec = <&headsetcodec>;
+};
diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index e181826..d123566 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -14,3 +14,13 @@ config SND_SOC_ROCKCHIP_I2S
  Say Y or M if you want to add support for I2S driver for
  Rockchip I2S device. The device supports upto maximum of
  8 channels each for play and record.
+
+config SND_SOC_ROCKCHIP_MAX98090
+   tristate "ASoC support for Rockchip boards using a MAX98090 codec"
+   depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB
+   select SND_SOC_ROCKCHIP_I2S
+   select SND_SOC_MAX98090
+   select SND_SOC_TS3A227E
+   help
+ Say Y or M here if you want to add support for SoC audio on Rockchip
+ boards using the MAX98090 codec, such as Veyron.
diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile
index b921909..df3445b 100644
--- a/sound/soc/rockchip/Makefile
+++ b/sound/soc/rockchip/Makefile
@@ -2,3 +2,7 @@
 snd-soc-i2s-objs := rockchip_i2s.o
 
 obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S) += snd-soc-i2s.o
+
+snd-soc-rockchip-max98090-objs := rockchip_max98090.o
+
+obj-$(CONFIG_SND_SOC_ROCKCHIP_MAX98090) += snd-soc-rockchip-max98090.o
diff --git a/sound/soc/rockchip/rockchip_max98090.c 
b/sound/soc/rockchip/rockchip_max98090.c
new file mode 100644
index 000..acace20
--- /dev/null
+++ b/sound/soc/rockchip/rockchip_max98090.c
@@ -0,0 +1,236 @@
+/*
+ * Rockchip machine ASoC driver for boards using a MAX90809 CODEC.
+ *
+ * Copyright (c) 2014, ROCKCHIP CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rockchip_i2s.h"
+#include "../codecs/ts3a227e.h"
+
+#define DRV_NAME "rockchip-snd-max98090"
+
+static struct snd_soc_jack headset_jack;
+static struct snd_soc_jack_pin headset_jack_pins[] = {
+   {
+   .pin = "Headset Jack",
+   .mask = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
+   SND_JACK_BTN_0 | SND_JACK_BTN_1 |
+   SND_JACK_BTN_2 | SND_JACK_BTN_3,
+   },
+};
+
+static const struct snd_soc_dapm_widget rk_dapm_widgets[] = {
+   SND_SOC_DAPM_HP("Headphone", NULL),
+   SND_SOC_DAPM_MIC("Headset Mic", NULL),
+   SND_SOC_DAPM_MIC("Int Mic", NULL),
+   SND_SOC_DAPM_SPK("Speaker", NULL),
+};
+
+static const struct snd_soc_dapm_route rk_audio_map[] = {
+   {"IN34", NULL, "Headset Mic"},
+   {"IN34", NULL, "MICBIAS"},
+   {"MICBIAS", NULL, "Headset Mic"},
+   {"DMICL", NULL, "Int Mic"},
+   {"Headphone", NULL, "HPL"},
+   {"Headphone", NULL, "HPR"},
+   {"Speaker", NULL, "SPKL"},
+   {"Speaker", NULL, "SPKR"},
+};
+
+static const struct snd_kcontrol_new rk_mc_controls[] = {
+   SOC_DAPM_PIN_SWITCH("Hea

[PATCH v3 2/2] ASoC: rockchip: Add machine driver for rt5645/rt5650 codec

[Xing Zheng]

{"Headphones", NULL, "HPOL"},
+   {"Speakers", NULL, "SPOL"},
+   {"Speakers", NULL, "SPOR"},
+};
+
+static const struct snd_kcontrol_new rk_mc_controls[] = {
+   SOC_DAPM_PIN_SWITCH("Headphones"),
+   SOC_DAPM_PIN_SWITCH("Speakers"),
+   SOC_DAPM_PIN_SWITCH("Headset Mic"),
+   SOC_DAPM_PIN_SWITCH("Int Mic"),
+};
+
+static int rk_aif1_hw_params(struct snd_pcm_substream *substream,
+struct snd_pcm_hw_params *params)
+{
+   int ret = 0;
+   struct snd_soc_pcm_runtime *rtd = substream->private_data;
+   struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+   struct snd_soc_dai *codec_dai = rtd->codec_dai;
+   int mclk;
+
+   switch (params_rate(params)) {
+   case 8000:
+   case 16000:
+   case 48000:
+   case 96000:
+   mclk = 12288000;
+   break;
+   case 44100:
+   mclk = 11289600;
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
+SND_SOC_CLOCK_OUT);
+   if (ret < 0) {
+   dev_err(codec_dai->dev, "Can't set codec clock %d\n", ret);
+   return ret;
+   }
+
+   ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
+SND_SOC_CLOCK_IN);
+   if (ret < 0) {
+   dev_err(codec_dai->dev, "Can't set codec clock %d\n", ret);
+   return ret;
+   }
+
+   return ret;
+}
+
+static int rk_init(struct snd_soc_pcm_runtime *runtime)
+{
+   struct snd_soc_card *card = runtime->card;
+   int ret;
+
+   /* Enable Headset and 4 Buttons Jack detection */
+   ret = snd_soc_card_jack_new(card, "Headset Jack",
+   SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
+   SND_JACK_BTN_0 | SND_JACK_BTN_1 |
+   SND_JACK_BTN_2 | SND_JACK_BTN_3,
+   &headset_jack, NULL, 0);
+   if (!ret) {
+   dev_err(card->dev, "New Headset Jack failed! (%d)\n", ret);
+   return ret;
+   }
+
+   return rt5645_set_jack_detect(runtime->codec,
+&headset_jack,
+&headset_jack,
+&headset_jack);
+}
+
+static struct snd_soc_ops rk_aif1_ops = {
+   .hw_params = rk_aif1_hw_params,
+};
+
+static struct snd_soc_dai_link rk_dailink = {
+   .name = "rt5645",
+   .stream_name = "rt5645 PCM",
+   .codec_dai_name = "rt5645-aif1",
+   .init = rk_init,
+   .ops = &rk_aif1_ops,
+   /* set rt5645 as slave */
+   .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+   SND_SOC_DAIFMT_CBS_CFS,
+};
+
+static struct snd_soc_card snd_soc_card_rk = {
+   .name = "I2S-RT5650",
+   .dai_link = &rk_dailink,
+   .num_links = 1,
+   .dapm_widgets = rk_dapm_widgets,
+   .num_dapm_widgets = ARRAY_SIZE(rk_dapm_widgets),
+   .dapm_routes = rk_audio_map,
+   .num_dapm_routes = ARRAY_SIZE(rk_audio_map),
+   .controls = rk_mc_controls,
+   .num_controls = ARRAY_SIZE(rk_mc_controls),
+};
+
+static int snd_rk_mc_probe(struct platform_device *pdev)
+{
+   int ret = 0;
+   struct snd_soc_card *card = &snd_soc_card_rk;
+   struct device_node *np = pdev->dev.of_node;
+
+   /* register the soc card */
+   card->dev = &pdev->dev;
+
+   rk_dailink.codec_of_node = of_parse_phandle(np,
+   "rockchip,audio-codec", 0);
+   if (!rk_dailink.codec_of_node) {
+   dev_err(&pdev->dev,
+   "Property 'rockchip,audio-codec' missing or invalid\n");
+   return -EINVAL;
+   }
+
+   rk_dailink.cpu_of_node = of_parse_phandle(np,
+   "rockchip,i2s-controller", 0);
+   if (!rk_dailink.cpu_of_node) {
+   dev_err(&pdev->dev,
+   "Property 'rockchip,i2s-controller' missing or 
invalid\n");
+   return -EINVAL;
+   }
+
+   rk_dailink.platform_of_node = rk_dailink.cpu_of_node;
+
+   ret = snd_soc_of_parse_card_name(card, "rockchip,model");
+   if (ret) {
+   dev_err(&pdev->dev,
+   "Soc parse card name failed %d\n", ret);
+   return ret;
+   }
+
+   ret = devm_snd_soc_register_card(&pdev->dev, card);
+   if (ret) {
+   dev_err(&pdev->dev,
+   "Soc register card failed %d\n", ret);
+   return ret;
+

[PATCH v3 0/2] Add codec machine driver for rockchip platform

[Xing Zheng]

From: zhengxing 


Hi,
  The simple-card is not common at present, soc maybe need own machine
driver for jack detection.
  Add drivers for two families of rockchip-bases chromebooks. These
machine drives don't use simplecard because we need custom jack
detection plumbing.

- use ts3a227e for ext jack detection with max98090
- call rt5645_set_jack_detect function via rt5645 codec driver

Thanks.


Changes in v3:
Signed-off-by: zhengxing 

zhengxing (2):
  ASoC: rockchip: Add machine driver for max98090 codec
  ASoC: rockchip: Add machine driver for rt5645/rt5650 codec

 .../bindings/sound/rockchip-max98090.txt   |   19 ++
 .../devicetree/bindings/sound/rockchip-rt5645.txt  |   17 ++
 sound/soc/rockchip/Kconfig |   19 ++
 sound/soc/rockchip/Makefile|6 +
 sound/soc/rockchip/rockchip_max98090.c |  236 
 sound/soc/rockchip/rockchip_rt5645.c   |  225 +++
 6 files changed, 522 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/sound/rockchip-max98090.txt
 create mode 100644 Documentation/devicetree/bindings/sound/rockchip-rt5645.txt
 create mode 100644 sound/soc/rockchip/rockchip_max98090.c
 create mode 100644 sound/soc/rockchip/rockchip_rt5645.c

-- 
1.7.9.5


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Re: [PATCH v2 1/2] ASoC: rockchip: Add machine driver for max98090 codec

[Xing Zheng]

On 2015年07月18日 17:16, Mark Brown wrote:

On Sat, Jul 18, 2015 at 01:08:43PM +0800, Xing Zheng wrote:


+   ret = devm_snd_soc_register_card(&pdev->dev, card);
+   if (ret) {
+   dev_err(&pdev->dev,
+   "Soc register card failed %d\n", ret);
+   return ret;
+   }
+
+   return ret;
+}
+
+static int snd_rk_mc_remove(struct platform_device *pdev)
+{
+   struct snd_soc_card *soc_card = platform_get_drvdata(pdev);
+
+   snd_soc_unregister_card(soc_card);

The point with using devm_snd_soc_register_card() is that you don't need
to manually unregister the card - devm_ ensures that the card is freed.

Got it. Thank you.

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[PATCH v2 1/2] ASoC: rockchip: Add machine driver for max98090 codec

[Xing Zheng]

From: zhengxing 

The driver is used for rockchip board using a max98090.

Reviewed-by: Dylan Reid 
Signed-off-by: zhengxing 
---

Changes in v2: None

 .../bindings/sound/rockchip-max98090.txt   |   19 ++
 sound/soc/rockchip/Kconfig |   10 +
 sound/soc/rockchip/Makefile|4 +
 sound/soc/rockchip/rockchip_max98090.c |  247 
 4 files changed, 280 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/sound/rockchip-max98090.txt
 create mode 100644 sound/soc/rockchip/rockchip_max98090.c

diff --git a/Documentation/devicetree/bindings/sound/rockchip-max98090.txt 
b/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
new file mode 100644
index 000..a805aa9
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
@@ -0,0 +1,19 @@
+ROCKCHIP with MAX98090 CODEC
+
+Required properties:
+- compatible: "rockchip,rockchip-audio-max98090"
+- rockchip,model: The user-visible name of this sound complex
+- rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
+  connected to the CODEC
+- rockchip,audio-codec: The phandle of the MAX98090 audio codec
+- rockchip,headset-codec: The phandle of Ext chip for jack detection
+
+Example:
+
+sound {
+   compatible = "rockchip,rockchip-audio-max98090";
+   rockchip,model = "ROCKCHIP-I2S";
+   rockchip,i2s-controller = <&i2s>;
+   rockchip,audio-codec = <&max98090>;
+   rockchip,headset-codec = <&headsetcodec>;
+};
diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index e181826..d123566 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -14,3 +14,13 @@ config SND_SOC_ROCKCHIP_I2S
  Say Y or M if you want to add support for I2S driver for
  Rockchip I2S device. The device supports upto maximum of
  8 channels each for play and record.
+
+config SND_SOC_ROCKCHIP_MAX98090
+   tristate "ASoC support for Rockchip boards using a MAX98090 codec"
+   depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB
+   select SND_SOC_ROCKCHIP_I2S
+   select SND_SOC_MAX98090
+   select SND_SOC_TS3A227E
+   help
+ Say Y or M here if you want to add support for SoC audio on Rockchip
+ boards using the MAX98090 codec, such as Veyron.
diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile
index b921909..df3445b 100644
--- a/sound/soc/rockchip/Makefile
+++ b/sound/soc/rockchip/Makefile
@@ -2,3 +2,7 @@
 snd-soc-i2s-objs := rockchip_i2s.o
 
 obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S) += snd-soc-i2s.o
+
+snd-soc-rockchip-max98090-objs := rockchip_max98090.o
+
+obj-$(CONFIG_SND_SOC_ROCKCHIP_MAX98090) += snd-soc-rockchip-max98090.o
diff --git a/sound/soc/rockchip/rockchip_max98090.c 
b/sound/soc/rockchip/rockchip_max98090.c
new file mode 100644
index 000..f6644b3
--- /dev/null
+++ b/sound/soc/rockchip/rockchip_max98090.c
@@ -0,0 +1,247 @@
+/*
+ * Rockchip machine ASoC driver for boards using a MAX90809 CODEC.
+ *
+ * Copyright (c) 2014, ROCKCHIP CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rockchip_i2s.h"
+#include "../codecs/ts3a227e.h"
+
+#define DRV_NAME "rockchip-snd-max98090"
+
+static struct snd_soc_jack headset_jack;
+static struct snd_soc_jack_pin headset_jack_pins[] = {
+   {
+   .pin = "Headset Jack",
+   .mask = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
+   SND_JACK_BTN_0 | SND_JACK_BTN_1 |
+   SND_JACK_BTN_2 | SND_JACK_BTN_3,
+   },
+};
+
+static const struct snd_soc_dapm_widget rk_dapm_widgets[] = {
+   SND_SOC_DAPM_HP("Headphone", NULL),
+   SND_SOC_DAPM_MIC("Headset Mic", NULL),
+   SND_SOC_DAPM_MIC("Int Mic", NULL),
+   SND_SOC_DAPM_SPK("Speaker", NULL),
+};
+
+static const struct snd_soc_dapm_route rk_audio_map[] = {
+   {"IN34", NULL, "Headset Mic"},
+   {"IN34", NULL, "MICBIAS"},
+   {"MICBIAS", NULL, "Headset Mic"},
+   {"DMICL", NULL, "Int Mic"},
+   {"Headphone", NULL, "HPL"},
+   {"Headphone", NULL, "HPR"},
+   {"Speaker", NULL, "SPKL"},
+   {"Speaker", NULL, "SPKR"},
+};
+
+static const struct snd_kcontrol_new rk_mc_controls[] = {
+   SOC_DAPM_PIN_SWITCH("Hea

[PATCH v2 0/2] Add codec machine driver for rockchip platform

[Xing Zheng]

From: zhengxing 


Hi,
  The simple-card is not common at present, soc maybe need own machine
driver for jack detection.
  Add drivers for two families of rockchip-bases chromebooks. These
machine drives don't use simplecard because we need custom jack
detection plumbing.

- use ts3a227e for ext jack detection with max98090
- call rt5645_set_jack_detect function via rt5645 codec driver

Thanks.


Changes in v2:
Signed-off-by: zhengxing 

zhengxing (2):
  ASoC: rockchip: Add machine driver for max98090 codec
  ASoC: rockchip: Add machine driver for rt5645/rt5650 codec

 .../bindings/sound/rockchip-max98090.txt   |   19 ++
 .../devicetree/bindings/sound/rockchip-rt5645.txt  |   17 ++
 sound/soc/rockchip/Kconfig |   19 ++
 sound/soc/rockchip/Makefile|6 +
 sound/soc/rockchip/rockchip_max98090.c |  247 
 sound/soc/rockchip/rockchip_rt5645.c   |  236 +++
 6 files changed, 544 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/sound/rockchip-max98090.txt
 create mode 100644 Documentation/devicetree/bindings/sound/rockchip-rt5645.txt
 create mode 100644 sound/soc/rockchip/rockchip_max98090.c
 create mode 100644 sound/soc/rockchip/rockchip_rt5645.c

-- 
1.7.9.5


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[PATCH v2 2/2] ASoC: rockchip: Add machine driver for rt5645/rt5650 codec

[Xing Zheng]

er card failed %d\n", ret);
+   return ret;
+   }
+
+   return ret;
+}
+
+static int snd_rk_mc_remove(struct platform_device *pdev)
+{
+   struct snd_soc_card *soc_card = platform_get_drvdata(pdev);
+
+   snd_soc_unregister_card(soc_card);
+
+   return 0;
+}
+
+static const struct of_device_id rockchip_rt5645_of_match[] = {
+   { .compatible = "rockchip,rockchip-audio-rt5645", },
+   {},
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_rt5645_of_match);
+
+static struct platform_driver snd_rk_mc_driver = {
+   .probe = snd_rk_mc_probe,
+   .remove = snd_rk_mc_remove,
+   .driver = {
+   .name = DRV_NAME,
+   .owner = THIS_MODULE,
+   .pm = &snd_soc_pm_ops,
+   .of_match_table = rockchip_rt5645_of_match,
+   },
+};
+
+module_platform_driver(snd_rk_mc_driver);
+
+MODULE_AUTHOR("Xing Zheng ");
+MODULE_DESCRIPTION("Rockchip rt5645 machine ASoC driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRV_NAME);
-- 
1.7.9.5


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