Re: [PATCH v4 0/4] mtd:nand:omap2: clean-up of supported ECC schemes
On 7/3/2013 11:34 PM, Gupta, Pekon wrote:
On Wednesday 03 July 2013, Artem Bityutskiy wrote:
On Wed, 2013-07-03 at 13:16 +, Gupta, Pekon wrote:
[Pekon]: Yes, I'm not seeing these build issues, as I'm cleanly
returning from probe with pr_err(), if the required libraries (/lib/bch.c)
are not build-in the system.
---
[Patch v4 1/4]: mtd:nand:omap2: clean-up BCHx_HW and BCHx_SW ECC..
@@static int omap_nand_probe(struct platform_device *pdev)
+ default:
+ pr_err("selected ECC scheme not supported or not
enabled\n");
+ err = -EINVAL;
+ goto out_release_mem_region;
+ }
---
However, if you are still seeing this, could you please send me your
config?
I compile tested your patches too, and did not see any issues with my
omap2_defconfig.
To clarify: I'm getting this error with randconfig on today's linux-next.
I think it only happens with MTD_NAND_ECC_BCH enabled, which is not
the default in omap2_defconfig.
Arnd
Hi Arnd, Artem, Stephen,
I see the issue in linux-next/master tree..
linux-next/master has only the first [Patch v4 1/4] from the series.
Other patches [Patch v4 2/4.. 4/4] of this series were dropped,
as 'Olof Johansson' had some apprehensions about DT bindings.
http://permalink.gmane.org/gmane.linux.ports.arm.kernel/249662
As these patches are inter-dependent, so please drop the whole series
including the commit below.
fb1585b [Patch v4 1/4] mtd: nand: omap2: clean-up BCHx_HW and BCHx_SW
I'm awaiting feedbacks from 'Olof Johansson' or other DT maintainers,
once approved, I'll resend the whole series.
"[PATCH v4 2/4] ARM: OMAP2+: cleaned-up DT support " had the
declarations which were required for above build errors.
---
include/linux/platform_data/mtd-nand-omap2.h
enum omap_ecc {
+ /* 4-bit ECC calculation by GPMC, Error detection by Software */
+ OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
...
+ /* 8-bit ECC calculation by GPMC, Error detection by Software */
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
---
But patches should not have inter dependency for compilation. It will affect
the bisect process.
Regards
Mugunthan V N
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Re: [PATCH -next] net: ethernet: davinci_emac: remove redundant dev_err call in davinci_emac_probe()
On Tuesday 02 July 2013 06:27 AM, Wei Yongjun wrote: From: Wei Yongjun There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun Acked-by: Mugunthan V N Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 0/3] Add pinmux DT nodes to CPSW for AM335x
On 6/7/2013 5:02 PM, Mugunthan V N wrote: Add pinmux DT nodes to CPSW for the following AM335x boards * AM335x Beaglebone * AM335x EVM * AM335x EVMsk default state contains the pinmux required for active mode and sleep mode contains pinmux reset values for energy saving. Mugunthan V N (3): ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM arch/arm/boot/dts/am335x-bone.dts | 67 ++ arch/arm/boot/dts/am335x-evm.dts | 64 + arch/arm/boot/dts/am335x-evmsk.dts | 92 3 files changed, 223 insertions(+) Benoit Do you have any comments on this patch series, if not can you queue it for v3.11 Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [net-next PATCH v4 1/5] net: cpsw: enhance pinctrl support
On 6/7/2013 1:12 PM, David Miller wrote: From: Linus Walleij Date: Fri, 7 Jun 2013 09:31:58 +0200 On Thu, Jun 6, 2013 at 10:50 AM, Mark Brown wrote: On Thu, Jun 06, 2013 at 11:29:39AM +0530, Mugunthan V N wrote: On 6/6/2013 12:53 AM, Mark Brown wrote: Linus Walleij posted some patches which factor the state setting code out into generic functions earlier on today - it probably makes sense to pick those up rather than open coding But this can go in as Linus Walleij's patch is not accepted yet. Once that is accepted and present in net git repo I will submit a separate patch to use those APIs from pin ctrl core. Linus' change has pretty much gone in already but in any case what would be sensible here would be to write this in turns of Linus' changes and then send the patch to him to add to his series so it can go in via the same route. One of the major reasons for the patch was that lots of people were querying the amount of noise caused by this sort of change. I agree. We should be able to settle on the new core API quite soon, then I can carry the patch to this driver if you obtain David's ACK. If you want to merge the direct networking parts of this series into another tree, I'm fine with that: Acked-by: David S. Miller David Can you the below patch series as i have adopted pinctrl PM api in another series, this patch has direct usage of pinctrl_select_state apis http://marc.info/?l=linux-netdev&m=137054250018667&w=2 Linus Walleij Please drop this patch series and take my other [atch set mentioned above with David's Ack. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH 3/3] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Sleep mode is nothing but the values required for the module during
inactive state. The pins are configured to its reset state to optimize
energy usage for the pins for the suspend/resume cycle
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evm.dts | 64 ++
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 2c53247..a1a0880 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -91,6 +91,58 @@
0x9c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txen.rgmii1_tctl */
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxdv.rgmii1_rctl */
+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd3.rgmii1_td3 */
+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd2.rgmii1_td2 */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd1.rgmii1_td1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd0.rgmii1_td0 */
+ 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txclk.rgmii1_tclk */
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxclk.rgmii1_rclk */
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd3.rgmii1_rd3 */
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd2.rgmii1_rd2 */
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd1.rgmii1_rd1 */
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd0.rgmii1_rd0 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
MUX_MODE0)/* mdio_data.mdio_data */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)
/* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
};
ocp {
@@ -378,6 +430,18 @@
};
};
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+};
+
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
};
--
1.7.9.5
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[PATCH 1/3] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Sleep mode is nothing but the values required for the module during
inactive state. The pins are configured to its reset state to optimize
energy usage for the pins for the suspend/resume cycle
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-bone.dts | 67 +
1 file changed, 67 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index fd48173..04feaf8 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -56,6 +56,60 @@
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /*
xdma_event_intr1.clkout2 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x110 (PIN_INPUT_PULLUP | MUX_MODE0)/*
mii1_rxerr.mii1_rxerr */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /*
mii1_txen.mii1_txen */
+ 0x118 (PIN_INPUT_PULLUP | MUX_MODE0)/*
mii1_rxdv.mii1_rxdv */
+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /*
mii1_txd3.mii1_txd3 */
+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /*
mii1_txd2.mii1_txd2 */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /*
mii1_txd1.mii1_txd1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /*
mii1_txd0.mii1_txd0 */
+ 0x12c (PIN_INPUT_PULLUP | MUX_MODE0)/*
mii1_txclk.mii1_txclk */
+ 0x130 (PIN_INPUT_PULLUP | MUX_MODE0)/*
mii1_rxclk.mii1_rxclk */
+ 0x134 (PIN_INPUT_PULLUP | MUX_MODE0)/*
mii1_rxd3.mii1_rxd3 */
+ 0x138 (PIN_INPUT_PULLUP | MUX_MODE0)/*
mii1_rxd2.mii1_rxd2 */
+ 0x13c (PIN_INPUT_PULLUP | MUX_MODE0)/*
mii1_rxd1.mii1_rxd1 */
+ 0x140 (PIN_INPUT_PULLUP | MUX_MODE0)/*
mii1_rxd0.mii1_rxd0 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
MUX_MODE0)/* mdio_data.mdio_data */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)
/* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
};
ocp {
@@ -165,3 +219,16 @@
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+};
--
1.7.9.5
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[PATCH 0/3] Add pinmux DT nodes to CPSW for AM335x
Add pinmux DT nodes to CPSW for the following AM335x boards * AM335x Beaglebone * AM335x EVM * AM335x EVMsk default state contains the pinmux required for active mode and sleep mode contains pinmux reset values for energy saving. Mugunthan V N (3): ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM arch/arm/boot/dts/am335x-bone.dts | 67 ++ arch/arm/boot/dts/am335x-evm.dts | 64 + arch/arm/boot/dts/am335x-evmsk.dts | 92 3 files changed, 223 insertions(+) -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH 2/3] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
Add pinmux configurations for RGMII based CPSW ethernet to AM335x EVMsk.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Sleep mode is nothing but the values required for the module during
inactive state. The pins are configured to its reset state to optimize
energy usage for the pins for the suspend/resume cycle
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts | 92
1 file changed, 92 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 338b681..a0c201d 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -71,6 +71,86 @@
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)
/* xdma_event_intr1.clkout2 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txen.rgmii1_tctl */
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxdv.rgmii1_rctl */
+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd3.rgmii1_td3 */
+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd2.rgmii1_td2 */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd1.rgmii1_td1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txd0.rgmii1_td0 */
+ 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
mii1_txclk.rgmii1_tclk */
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxclk.rgmii1_rclk */
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd3.rgmii1_rd3 */
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd2.rgmii1_rd2 */
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd1.rgmii1_rd1 */
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
mii1_rxd0.rgmii1_rd0 */
+
+ /* Slave 2 */
+ 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a0.rgmii2_tctl */
+ 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a1.rgmii2_rctl */
+ 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a2.rgmii2_td3 */
+ 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a3.rgmii2_td2 */
+ 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a4.rgmii2_td1 */
+ 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a5.rgmii2_td0 */
+ 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a6.rgmii2_tclk */
+ 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a7.rgmii2_rclk */
+ 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a8.rgmii2_rd3 */
+ 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a9.rgmii2_rd2 */
+ 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a10.rgmii2_rd1 */
+ 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a11.rgmii2_rd0 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+
+ /* Slave 2 reset value*/
+ 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x50 (PIN_INPUT_PULLDOWN
Re: [net-next PATCH v4 0/5] Adding pinctrl PM support for CPSW and MDIO
On 6/6/2013 1:12 PM, Benoit Cousson wrote: Hi Mugunthan, On 06/05/2013 07:08 PM, Mugunthan V N wrote: This patch series adds the following features * Adding pinctrl PM support for CPSW and MDIO for Power Optimization * Adding phy address to the CPSW node for EVMsk board Changes from initial version * Fixed the multiline function call indentation as per David Miller recommendation. Changes from v2 * Fixed the multi comment style as per net coding style * Fixed checkpatch error (more than 80 characters) Changes from v3 * Removed below patch as it has already merged to net-next ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk * Rebased to net-next as there was a merge conflict in DT files You should try to avoid pushing DTS patches outside the arm-soc tree, it will generate a bunch a conflict when arm-soc and net trees will be merged. Could you post separately all the DTS patches and rebase them on the for_3.11/dts branch that already contains a bunch of AM33xx patches? Benoit Will separate out the DT patches and will submit on top of for_3.11/dts today as v5. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [net-next PATCH v4 3/5] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
On 6/6/2013 12:36 PM, Florian Vaussard wrote:
Hello,
On 06/05/2013 07:08 PM, Mugunthan V N wrote:
Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-bone.dts | 38
+
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 4b5a8e0..008a13b 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,33 @@
0x60 0x17/* gpmc_a8.gpio1_24, OUTPUT_PULLUP |
MODE7 */
>;
};
+
+cpsw_default: cpsw_default {
+pinctrl-single,pins = <
+/* Slave 1 */
+0x110 0x20/* mii1_rxerr.mii1_rxerr, MODE0 |
INPUT */
Here I guess that the comment should be INPUT_PULLDOWN, instead of INPUT.
Good catch, I will modify this and submit next version today.
+0x114 0x0/* mii1_txen.mii1_txen, MODE0 | OUTPUT */
As bit PULLUDENABLE is 0, the pulldown is enabled according to the
TRM, right?
Is this a desirable behaviour, as it will consume power when
outputting a high level?
This is the desirable behavior.
And consequently, the comment should probably be OUTPUT_PULLDOWN, no?
Will update this in next version of patch series.
Regards
Mugunthan V N
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Re: [net-next PATCH v4 1/5] net: cpsw: enhance pinctrl support
On 6/6/2013 12:53 AM, Mark Brown wrote: On Wed, Jun 05, 2013 at 10:38:15PM +0530, Mugunthan V N wrote: From: Hebbar Gururaja Amend cpsw controller to optionally take a pin control handle and set the state of the pins to: - "default" on boot, resume - "sleep" on suspend() Linus Walleij posted some patches which factor the state setting code out into generic functions earlier on today - it probably makes sense to pick those up rather than open coding But this can go in as Linus Walleij's patch is not accepted yet. Once that is accepted and present in net git repo I will submit a separate patch to use those APIs from pin ctrl core. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[net-next PATCH v4 2/5] net: davinci_mdio: enhance pinctrl support
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/davinci_mdio.c | 45
1 file changed, 45 insertions(+)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c
b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec17..9e6aaeb 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -38,6 +38,7 @@
#include
#include
#include
+#include
/*
* This timeout definition is a worst-case ultra defensive measure against
@@ -94,6 +95,11 @@ struct davinci_mdio_data {
struct mii_bus *bus;
boolsuspended;
unsigned long access_time; /* jiffies */
+
+ /* Two optional pin states - default & sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_def;
+ struct pinctrl_state*pins_sleep;
};
static void __davinci_mdio_reset(struct davinci_mdio_data *data)
@@ -347,6 +353,35 @@ static int davinci_mdio_probe(struct platform_device *pdev)
data->bus->parent = dev;
data->bus->priv = data;
+ data->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (!IS_ERR(data->pinctrl)) {
+ data->pins_def = pinctrl_lookup_state(data->pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(data->pins_def))
+ dev_warn(&pdev->dev, "could not get default
pinstate\n");
+ else
+ if (pinctrl_select_state(data->pinctrl,
+data->pins_def))
+ dev_err(&pdev->dev,
+ "could not set default pins\n");
+
+ data->pins_sleep = pinctrl_lookup_state(data->pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(data->pins_sleep))
+ dev_warn(&pdev->dev, "could not get sleep pinstate\n");
+ } else {
+ /* Since we continue even when pinctrl node is not found,
+* Invalidate pins as not available. This is to make sure that
+* IS_ERR(pins_xxx) results in failure when used.
+*/
+ data->pins_def = ERR_PTR(-ENODATA);
+ data->pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(&pdev->dev,
+"pins are not configured from the driver\n");
+ }
+
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
data->clk = clk_get(&pdev->dev, "fck");
@@ -454,6 +489,11 @@ static int davinci_mdio_suspend(struct device *dev)
data->suspended = true;
spin_unlock(&data->lock);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(data->pins_sleep))
+ if (pinctrl_select_state(data->pinctrl, data->pins_sleep))
+ dev_err(dev, "could not set pins to sleep state\n");
+
return 0;
}
@@ -465,6 +505,11 @@ static int davinci_mdio_resume(struct device *dev)
spin_lock(&data->lock);
pm_runtime_get_sync(data->dev);
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(data->pins_def))
+ if (pinctrl_select_state(data->pinctrl, data->pins_def))
+ dev_err(dev, "could not set default pins\n");
+
/* restart the scan state machine */
ctrl = __raw_readl(&data->regs->control);
ctrl |= CONTROL_ENABLE;
--
1.7.9.5
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[net-next PATCH v4 5/5] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evm.dts | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 814ee03..5db4b05 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,32 @@
0x154 0x27 /* spi0_d0.gpio0_3, INPUT |
MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -237,6 +263,16 @@
};
};
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
+
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
--
1.7.9.5
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[net-next PATCH v4 4/5] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts | 50
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 4297899..4827486 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,46 @@
0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT
| MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+
+ /* Slave 2 */
+ 0x40 0x2/* gpmc_a0.rgmii2_tctl", MODE2
| OUTPUT */
+ 0x44 0x22 /* gpmc_a1.rgmii2_rctl", MODE2
| INPUT_PULLDOWN */
+ 0x48 0x2/* gpmc_a2.rgmii2_td3", MODE2 |
OUTPUT */
+ 0x4c 0x2/* gpmc_a3.rgmii2_td2", MODE2 |
OUTPUT */
+ 0x50 0x2/* gpmc_a4.rgmii2_td1", MODE2 |
OUTPUT */
+ 0x54 0x2/* gpmc_a5.rgmii2_td0", MODE2 |
OUTPUT */
+ 0x58 0x2/* gpmc_a6.rgmii2_tclk", MODE2
| OUTPUT */
+ 0x5c 0x22 /* gpmc_a7.rgmii2_rclk", MODE2
| INPUT_PULLDOWN */
+ 0x60 0x22 /* gpmc_a8.rgmii2_rd3", MODE2 |
INPUT_PULLDOWN */
+ 0x64 0x22 /* gpmc_a9.rgmii2_rd2", MODE2 |
INPUT_PULLDOWN */
+ 0x68 0x22 /* gpmc_a10.rgmii2_rd1", MODE2
| INPUT_PULLDOWN */
+ 0x6c 0x22 /* gpmc_a11.rgmii2_rd0", MODE2
| INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -249,6 +289,16 @@
};
};
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
+
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
--
1.7.9.5
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[net-next PATCH v4 3/5] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-bone.dts | 38 +
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 4b5a8e0..008a13b 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,33 @@
0x60 0x17 /* gpmc_a8.gpio1_24,
OUTPUT_PULLUP | MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x110 0x20 /* mii1_rxerr.mii1_rxerr, MODE0
| INPUT */
+ 0x114 0x0 /* mii1_txen.mii1_txen, MODE0 |
OUTPUT */
+ 0x118 0x20 /* mii1_rxdv.mii1_rxdv, MODE0 |
INPUT_PULLDOWN */
+ 0x11c 0x0 /* mii1_txd3.mii1_txd3, MODE0 |
OUTPUT */
+ 0x120 0x0 /* mii1_txd2.mii1_txd2, MODE0 |
OUTPUT */
+ 0x124 0x0 /* mii1_txd1.mii1_txd1, MODE0 |
OUTPUT */
+ 0x128 0x0 /* mii1_txd0.mii1_txd0, MODE0 |
OUTPUT */
+ 0x12c 0x20 /* mii1_txclk.mii1_txclk, MODE0
| INPUT_PULLDOWN */
+ 0x130 0x20 /* mii1_rxclk.mii1_rxclk, MODE0
| INPUT_PULLDOWN */
+ 0x134 0x20 /* mii1_rxd3.mii1_rxd3, MODE0 |
INPUT_PULLDOWN */
+ 0x138 0x20 /* mii1_rxd2.mii1_rxd2, MODE0 |
INPUT_PULLDOWN */
+ 0x13c 0x20 /* mii1_rxd1.mii1_rxd1, MODE0 |
INPUT_PULLDOWN */
+ 0x140 0x20 /* mii1_rxd0.mii1_rxd0, MODE0 |
INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -138,3 +165,14 @@
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
};
+
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
--
1.7.9.5
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[net-next PATCH v4 1/5] net: cpsw: enhance pinctrl support
From: Hebbar Gururaja
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index a45f64e..0599515 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
#include
#include
+#include
#include "cpsw_ale.h"
#include "cpts.h"
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+ /* Two optional pin states - default & sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_def;
+ struct pinctrl_state*pins_sleep;
};
#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
@@ -1691,6 +1697,35 @@ static int cpsw_probe(struct platform_device *pdev)
*/
pm_runtime_enable(&pdev->dev);
+ priv->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (!IS_ERR(priv->pinctrl)) {
+ priv->pins_def = pinctrl_lookup_state(priv->pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(priv->pins_def))
+ dev_warn(&pdev->dev, "could not get default
pinstate\n");
+ else
+ if (pinctrl_select_state(priv->pinctrl,
+priv->pins_def))
+ dev_err(&pdev->dev,
+ "could not set default pins\n");
+
+ priv->pins_sleep = pinctrl_lookup_state(priv->pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(priv->pins_sleep))
+ dev_warn(&pdev->dev, "could not get sleep pinstate\n");
+ } else {
+ /* Since we continue even when pinctrl node is not found,
+* Invalidate pins as not available. This is to make sure that
+* IS_ERR(pins_xxx) results in failure when used.
+*/
+ priv->pins_def = ERR_PTR(-ENODATA);
+ priv->pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(&pdev->dev,
+"pins are not configured from the driver\n");
+ }
+
if (cpsw_probe_dt(&priv->data, pdev)) {
pr_err("cpsw: platform data missing\n");
ret = -ENODEV;
@@ -1974,11 +2009,17 @@ static int cpsw_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
if (netif_running(ndev))
cpsw_ndo_stop(ndev);
pm_runtime_put_sync(&pdev->dev);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(priv->pins_sleep))
+ if (pinctrl_select_state(priv->pinctrl, priv->pins_sleep))
+ dev_err(dev, "could not set pins to sleep state\n");
+
return 0;
}
@@ -1986,8 +2027,15 @@ static int cpsw_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
pm_runtime_get_sync(&pdev->dev);
+
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(priv->pins_def))
+ if (pinctrl_select_state(priv->pinctrl, priv->pins_def))
+ dev_err(dev, "could not set default pins\n");
+
if (netif_running(ndev))
cpsw_ndo_open(ndev);
return 0;
--
1.7.9.5
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[net-next PATCH v4 0/5] Adding pinctrl PM support for CPSW and MDIO
This patch series adds the following features * Adding pinctrl PM support for CPSW and MDIO for Power Optimization * Adding phy address to the CPSW node for EVMsk board Changes from initial version * Fixed the multiline function call indentation as per David Miller recommendation. Changes from v2 * Fixed the multi comment style as per net coding style * Fixed checkpatch error (more than 80 characters) Changes from v3 * Removed below patch as it has already merged to net-next ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk * Rebased to net-next as there was a merge conflict in DT files Hebbar Gururaja (1): net: cpsw: enhance pinctrl support Mugunthan V N (4): net: davinci_mdio: enhance pinctrl support ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM arch/arm/boot/dts/am335x-bone.dts | 38 arch/arm/boot/dts/am335x-evm.dts | 36 +++ arch/arm/boot/dts/am335x-evmsk.dts | 50 drivers/net/ethernet/ti/cpsw.c | 48 ++ drivers/net/ethernet/ti/davinci_mdio.c | 45 5 files changed, 217 insertions(+) -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [net-next PATCH v3 1/6] net: cpsw: enhance pinctrl support
On 6/5/2013 9:19 PM, Tony Lindgren wrote:
* Mugunthan V N [130530 01:14]:
On 5/28/2013 7:35 PM, Mugunthan V N wrote:
On 5/28/2013 3:06 AM, Tony Lindgren wrote:
* Mugunthan V N [130526 11:28]:
From: Hebbar Gururaja
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c
b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..c9ed730 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
#include
#include
+#include
#include "cpsw_ale.h"
#include "cpts.h"
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+/* Two optional pin states - default & sleep */
+struct pinctrl*pinctrl;
+struct pinctrl_state*pins_def;
+struct pinctrl_state*pins_sleep;
};
Which pins do you need to dynamically remux? If it's not all
the pins, you should have three sets: default, active and idle.
This way the static pins in the default group don't need to be
constantly toggled.
Regards,
Tony
Tony
I am using this for all the pins, in probe all the cpsw pins will
be configured
and i have used the same in suspend/resume callback for power saving.
Tony
Do you have any comments on this, or is it ok with two pinctrl_state nodes?
If you always need to remux all the pins, then yes that's fine with me.
Regards,
Tony
David
As Tony accepted the implementation, I will resend the patch series as one
of the patch (pasted below) in this series is already merged in net-next.
f6655d6 Mugunthan V N ARM: dts: AM33XX: Add CPSW phy_id device tree
data to am335x-evmsk Mon Jun 3 20:10:09 2013 +
Regards
Mugunthan V N
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Re: [net-next PATCH 1/8] drivers: net: phy: at803x code cleanup on register and unregister driver
On 6/4/2013 5:32 PM, Sergei Shtylyov wrote:
Hello.
On 04-06-2013 10:10, Mugunthan V N wrote:
Make use of phy_drivers_register/phy_drivers_unregister to
register/unregister
multiple phy drivers in a single module.
Cc: Matus Ujhelyi
Signed-off-by: Mugunthan V N
---
drivers/net/phy/at803x.c | 35 ++-
1 file changed, 10 insertions(+), 25 deletions(-)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 45cbc10..a1063e1 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -108,8 +108,9 @@ static int at803x_config_init(struct phy_device
*phydev)
return 0;
}
-/* ATHEROS 8035 */
-static struct phy_driver at8035_driver = {
+static struct phy_driver at803x_driver[] = {
+{
+/* ATHEROS 8035 */
.phy_id= 0x004dd072,
.name= "Atheros 8035 ethernet",
.phy_id_mask= 0xffef,
That's improper indentation. Needs to be shifted by one tab.
This indentation is as per the coding style followed in all ethernet
phy drivers. If this need so to be changed, it must be a separate patch
for all the ethernet phy drivers.
@@ -136,32 +135,18 @@ static struct phy_driver at8030_driver = {
.driver= {
.owner = THIS_MODULE,
},
-};
+} };
Looks ugly...
This is also the same as per the style followed in ethernet phy drivers
Please refer the below grep output
$ grep -rnaI "} };" drivers/net/phy/*
drivers/net/phy/at803x.c:201:} };
drivers/net/phy/bcm63xx.c:101:} };
drivers/net/phy/bcm87xx.c:217:} };
drivers/net/phy/broadcom.c:829:} };
drivers/net/phy/cicada.c:130:} };
drivers/net/phy/davicom.c:183:} };
drivers/net/phy/icplus.c:254:} };
drivers/net/phy/lxt.c:313:} };
drivers/net/phy/micrel.c:323:} };
drivers/net/phy/smsc.c:242:} };
drivers/net/phy/ste10Xp.c:113:} };
drivers/net/phy/vitesse.c:192:} };
Regards
Mugunthan V N
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[net-next PATCH 8/8] ARM: dts: AM33XX: Add phy-mode to CPSW node
Adding phy-mode to CPSW node for beaglebone, EVM and EVMsk.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-bone.dts |2 ++
arch/arm/boot/dts/am335x-evm.dts |2 ++
arch/arm/boot/dts/am335x-evmsk.dts |2 ++
3 files changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 5302f79..4b5a8e0 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -131,8 +131,10 @@
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "mii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "mii";
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0423298..814ee03 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -239,8 +239,10 @@
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rgmii-txid";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rgmii-txid";
};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index acbcac3..4297899 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -251,8 +251,10 @@
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rgmii-txid";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rgmii-txid";
};
--
1.7.9.5
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[net-next PATCH 7/8] drivers: net: ethernet: cpsw: add phy-mode support to cpsw driver
Adding phy-mode support to cpsw driver and updating the cpsw binding
documentation.
Signed-off-by: Mugunthan V N
---
Documentation/devicetree/bindings/net/cpsw.txt |6 ++
drivers/net/ethernet/ti/cpsw.c |2 ++
2 files changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt
b/Documentation/devicetree/bindings/net/cpsw.txt
index 4f2ca6b..05d660e 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -28,6 +28,8 @@ Optional properties:
Slave Properties:
Required properties:
- phy_id : Specifies slave phy id
+- phy-mode : The interface between the SoC and the PHY (a string
+ that of_get_phy_mode() can understand)
- mac-address : Specifies slave MAC address
Optional properties:
@@ -58,11 +60,13 @@ Examples:
cpts_clock_shift = <29>;
cpsw_emac0: slave@0 {
phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rgmii-txid";
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@1 {
phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rgmii-txid";
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
@@ -84,11 +88,13 @@ Examples:
cpts_clock_shift = <29>;
cpsw_emac0: slave@0 {
phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rgmii-txid";
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@1 {
phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rgmii-txid";
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 89a4c40..a45f64e 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1554,6 +1554,8 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
if (mac_addr)
memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
+ slave_data->phy_if = of_get_phy_mode(slave_node);
+
if (data->dual_emac) {
if (of_property_read_u32(slave_node,
"dual_emac_res_vlan",
&prop)) {
--
1.7.9.5
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[net-next PATCH 5/8] ARM: OMAP2+: omap2plus_defconfig: Enable Atheros support
Enable Atheros 803X phy driver support in defconfig which is present in AM335x EVM and EVM Starter Kit. Signed-off-by: Mugunthan V N --- arch/arm/configs/omap2plus_defconfig |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 435d69b..aa21009 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -283,3 +283,4 @@ CONFIG_SOC_OMAP5=y CONFIG_TI_DAVINCI_MDIO=y CONFIG_TI_DAVINCI_CPDMA=y CONFIG_TI_CPSW=y +CONFIG_AT803X_PHY=y -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[net-next PATCH 6/8] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360..acbcac3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
--
1.7.9.5
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[net-next PATCH 3/8] drivers: net: phy: at803x: add interface mode support
This patch adds support for RGMII TX delay configuration on Atheros 803X,
this can be enabled in debug registers. With this patch,
PHY_INTERFACE_MODE_RGMII_TXID modes are now supported.
Signed-off-by: Mugunthan V N
---
drivers/net/phy/at803x.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 63444b7..dda07ed 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -27,6 +27,10 @@
#define AT803X_MMD_ACCESS_CONTROL 0x0D
#define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
#define AT803X_FUNC_DATA 0x4003
+#define AT803X_DEBUG_ADDR 0x1D
+#define AT803X_DEBUG_DATA 0x1E
+#define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
+#define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8)
MODULE_DESCRIPTION("Atheros 803x PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
@@ -99,6 +103,7 @@ static void at803x_get_wol(struct phy_device *phydev,
static int at803x_config_init(struct phy_device *phydev)
{
int val;
+ int ret;
u32 features;
features = SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_AUI |
@@ -133,6 +138,17 @@ static int at803x_config_init(struct phy_device *phydev)
phydev->supported = features;
phydev->advertising = features;
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+ ret = phy_write(phydev, AT803X_DEBUG_ADDR,
+ AT803X_DEBUG_SYSTEM_MODE_CTRL);
+ if (ret)
+ return ret;
+ ret = phy_write(phydev, AT803X_DEBUG_DATA,
+ AT803X_DEBUG_RGMII_TX_CLK_DLY);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
--
1.7.9.5
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[net-next PATCH 4/8] drivers: net: phy: at803x: add support for AT8031
This patch adds support for Atheros 8031 phy driver.
Signed-off-by: Mugunthan V N
---
drivers/net/phy/at803x.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index dda07ed..1f7091b 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -183,6 +183,21 @@ static struct phy_driver at803x_driver[] = {
.driver = {
.owner = THIS_MODULE,
},
+}, {
+ /* ATHEROS 8031 */
+ .phy_id = 0x004dd074,
+ .name = "Atheros 8031 ethernet",
+ .phy_id_mask= 0xffef,
+ .config_init= at803x_config_init,
+ .set_wol= at803x_set_wol,
+ .get_wol= at803x_get_wol,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_aneg= &genphy_config_aneg,
+ .read_status= &genphy_read_status,
+ .driver = {
+ .owner = THIS_MODULE,
+ },
} };
static int __init atheros_init(void)
--
1.7.9.5
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[net-next PATCH 1/8] drivers: net: phy: at803x code cleanup on register and unregister driver
Make use of phy_drivers_register/phy_drivers_unregister to register/unregister
multiple phy drivers in a single module.
Cc: Matus Ujhelyi
Signed-off-by: Mugunthan V N
---
drivers/net/phy/at803x.c | 35 ++-
1 file changed, 10 insertions(+), 25 deletions(-)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 45cbc10..a1063e1 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -108,8 +108,9 @@ static int at803x_config_init(struct phy_device *phydev)
return 0;
}
-/* ATHEROS 8035 */
-static struct phy_driver at8035_driver = {
+static struct phy_driver at803x_driver[] = {
+{
+ /* ATHEROS 8035 */
.phy_id = 0x004dd072,
.name = "Atheros 8035 ethernet",
.phy_id_mask= 0xffef,
@@ -121,10 +122,8 @@ static struct phy_driver at8035_driver = {
.driver = {
.owner = THIS_MODULE,
},
-};
-
-/* ATHEROS 8030 */
-static struct phy_driver at8030_driver = {
+}, {
+ /* ATHEROS 8030 */
.phy_id = 0x004dd076,
.name = "Atheros 8030 ethernet",
.phy_id_mask= 0xffef,
@@ -136,32 +135,18 @@ static struct phy_driver at8030_driver = {
.driver = {
.owner = THIS_MODULE,
},
-};
+} };
static int __init atheros_init(void)
{
- int ret;
-
- ret = phy_driver_register(&at8035_driver);
- if (ret)
- goto err1;
-
- ret = phy_driver_register(&at8030_driver);
- if (ret)
- goto err2;
-
- return 0;
-
-err2:
- phy_driver_unregister(&at8035_driver);
-err1:
- return ret;
+ return phy_drivers_register(at803x_driver,
+ ARRAY_SIZE(at803x_driver));
}
static void __exit atheros_exit(void)
{
- phy_driver_unregister(&at8035_driver);
- phy_driver_unregister(&at8030_driver);
+ return phy_drivers_unregister(at803x_driver,
+ ARRAY_SIZE(at803x_driver));
}
module_init(atheros_init);
--
1.7.9.5
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[net-next PATCH 2/8] drivers: net: phy: at803x: seperate wol specific code to wol standard apis
WOL is initilized in phy config_init, but there are standard apis
(set_wol/get_wol) for WOL in phy frame work. So this patch moves
WOL specific code from config_init to wol standard apis.
Cc: Matus Ujhelyi
Signed-off-by: Mugunthan V N
---
drivers/net/phy/at803x.c | 64 ++
1 file changed, 48 insertions(+), 16 deletions(-)
diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index a1063e1..63444b7 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -32,10 +32,13 @@ MODULE_DESCRIPTION("Atheros 803x PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_LICENSE("GPL");
-static void at803x_set_wol_mac_addr(struct phy_device *phydev)
+static int at803x_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
{
struct net_device *ndev = phydev->attached_dev;
const u8 *mac;
+ int ret;
+ u32 value;
unsigned int i, offsets[] = {
AT803X_LOC_MAC_ADDR_32_47_OFFSET,
AT803X_LOC_MAC_ADDR_16_31_OFFSET,
@@ -43,30 +46,60 @@ static void at803x_set_wol_mac_addr(struct phy_device
*phydev)
};
if (!ndev)
- return;
+ return -ENODEV;
- mac = (const u8 *) ndev->dev_addr;
+ if (wol->wolopts & WAKE_MAGIC) {
+ mac = (const u8 *) ndev->dev_addr;
- if (!is_valid_ether_addr(mac))
- return;
+ if (!is_valid_ether_addr(mac))
+ return -EFAULT;
- for (i = 0; i < 3; i++) {
- phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
+ for (i = 0; i < 3; i++) {
+ phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
AT803X_DEVICE_ADDR);
- phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
+ phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
offsets[i]);
- phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
+ phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
AT803X_FUNC_DATA);
- phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
+ phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
+ }
+
+ value = phy_read(phydev, AT803X_INTR_ENABLE);
+ value |= AT803X_WOL_ENABLE;
+ ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
+ if (ret)
+ return ret;
+ value = phy_read(phydev, AT803X_INTR_STATUS);
+ } else {
+ value = phy_read(phydev, AT803X_INTR_ENABLE);
+ value &= (~AT803X_WOL_ENABLE);
+ ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
+ if (ret)
+ return ret;
+ value = phy_read(phydev, AT803X_INTR_STATUS);
}
+
+ return ret;
+}
+
+static void at803x_get_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ u32 value;
+
+ wol->supported = WAKE_MAGIC;
+ wol->wolopts = 0;
+
+ value = phy_read(phydev, AT803X_INTR_ENABLE);
+ if (value & AT803X_WOL_ENABLE)
+ wol->wolopts |= WAKE_MAGIC;
}
static int at803x_config_init(struct phy_device *phydev)
{
int val;
u32 features;
- int status;
features = SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_AUI |
SUPPORTED_FIBRE | SUPPORTED_BNC;
@@ -100,11 +133,6 @@ static int at803x_config_init(struct phy_device *phydev)
phydev->supported = features;
phydev->advertising = features;
- /* enable WOL */
- at803x_set_wol_mac_addr(phydev);
- status = phy_write(phydev, AT803X_INTR_ENABLE, AT803X_WOL_ENABLE);
- status = phy_read(phydev, AT803X_INTR_STATUS);
-
return 0;
}
@@ -115,6 +143,8 @@ static struct phy_driver at803x_driver[] = {
.name = "Atheros 8035 ethernet",
.phy_id_mask= 0xffef,
.config_init= at803x_config_init,
+ .set_wol= at803x_set_wol,
+ .get_wol= at803x_get_wol,
.features = PHY_GBIT_FEATURES,
.flags = PHY_HAS_INTERRUPT,
.config_aneg= &genphy_config_aneg,
@@ -128,6 +158,8 @@ static struct phy_driver at803x_driver[] = {
.name = "Atheros 8030 ethernet",
.phy_id_mask= 0xffef,
.config_init= at803x_config_init,
+ .set_wol= at803x_set_wol,
+ .get_wol= at803x_get_wol,
.features = PHY_GBIT_FEATURES,
.flags = PHY_HAS_INTERRUPT,
.config_aneg= &genphy_config_aneg,
--
1.7.9.5
__
[net-next PATCH 0/8] add phy driver for Atheros AR8031 and CPSW phy-mode DT enhancement
This patch series adds the following feature * Atheros phy driver code cleanup * Add AT8031 phy driver to at803x driver * Add RGMII tx delay support via phy_if * Add phy_if DT enhancement to CPSW Driver and DT Mugunthan V N (8): drivers: net: phy: at803x code cleanup on register and unregister driver drivers: net: phy: at803x: seperate wol specific code to wol standard apis drivers: net: phy: at803x: add interface mode support drivers: net: phy: at803x: add support for AT8031 ARM: OMAP2+: omap2plus_defconfig: Enable Atheros support ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk drivers: net: ethernet: cpsw: add phy-mode support to cpsw driver ARM: dts: AM33XX: Add phy-mode to CPSW node Documentation/devicetree/bindings/net/cpsw.txt |6 ++ arch/arm/boot/dts/am335x-bone.dts |2 + arch/arm/boot/dts/am335x-evm.dts |2 + arch/arm/boot/dts/am335x-evmsk.dts | 10 ++ arch/arm/configs/omap2plus_defconfig |1 + drivers/net/ethernet/ti/cpsw.c |2 + drivers/net/phy/at803x.c | 128 7 files changed, 111 insertions(+), 40 deletions(-) -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [net-next PATCH v3 1/6] net: cpsw: enhance pinctrl support
On 5/28/2013 7:35 PM, Mugunthan V N wrote:
On 5/28/2013 3:06 AM, Tony Lindgren wrote:
* Mugunthan V N [130526 11:28]:
From: Hebbar Gururaja
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c
b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..c9ed730 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
#include
#include
+#include
#include "cpsw_ale.h"
#include "cpts.h"
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+/* Two optional pin states - default & sleep */
+struct pinctrl*pinctrl;
+struct pinctrl_state*pins_def;
+struct pinctrl_state*pins_sleep;
};
Which pins do you need to dynamically remux? If it's not all
the pins, you should have three sets: default, active and idle.
This way the static pins in the default group don't need to be
constantly toggled.
Regards,
Tony
Tony
I am using this for all the pins, in probe all the cpsw pins will be
configured
and i have used the same in suspend/resume callback for power saving.
Tony
Do you have any comments on this, or is it ok with two pinctrl_state nodes?
Regards
Mugunthan V N
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Re: [net-next PATCH v3 1/6] net: cpsw: enhance pinctrl support
On 5/28/2013 3:06 AM, Tony Lindgren wrote:
* Mugunthan V N [130526 11:28]:
From: Hebbar Gururaja
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..c9ed730 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
#include
#include
+#include
#include "cpsw_ale.h"
#include "cpts.h"
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+ /* Two optional pin states - default & sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_def;
+ struct pinctrl_state*pins_sleep;
};
Which pins do you need to dynamically remux? If it's not all
the pins, you should have three sets: default, active and idle.
This way the static pins in the default group don't need to be
constantly toggled.
Regards,
Tony
Tony
I am using this for all the pins, in probe all the cpsw pins will be
configured
and i have used the same in suspend/resume callback for power saving.
Regards
Mugunthan V N
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[net-next PATCH v3 6/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evm.dts | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0423298..beb2fbf 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,32 @@
0x154 0x27 /* spi0_d0.gpio0_3, INPUT |
MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -237,6 +263,16 @@
};
};
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
+
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
};
--
1.7.9.5
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[net-next PATCH v3 5/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts | 50
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index acbcac3..12cbe4e 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,46 @@
0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT
| MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+
+ /* Slave 2 */
+ 0x40 0x2/* gpmc_a0.rgmii2_tctl", MODE2
| OUTPUT */
+ 0x44 0x22 /* gpmc_a1.rgmii2_rctl", MODE2
| INPUT_PULLDOWN */
+ 0x48 0x2/* gpmc_a2.rgmii2_td3", MODE2 |
OUTPUT */
+ 0x4c 0x2/* gpmc_a3.rgmii2_td2", MODE2 |
OUTPUT */
+ 0x50 0x2/* gpmc_a4.rgmii2_td1", MODE2 |
OUTPUT */
+ 0x54 0x2/* gpmc_a5.rgmii2_td0", MODE2 |
OUTPUT */
+ 0x58 0x2/* gpmc_a6.rgmii2_tclk", MODE2
| OUTPUT */
+ 0x5c 0x22 /* gpmc_a7.rgmii2_rclk", MODE2
| INPUT_PULLDOWN */
+ 0x60 0x22 /* gpmc_a8.rgmii2_rd3", MODE2 |
INPUT_PULLDOWN */
+ 0x64 0x22 /* gpmc_a9.rgmii2_rd2", MODE2 |
INPUT_PULLDOWN */
+ 0x68 0x22 /* gpmc_a10.rgmii2_rd1", MODE2
| INPUT_PULLDOWN */
+ 0x6c 0x22 /* gpmc_a11.rgmii2_rd0", MODE2
| INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -249,6 +289,16 @@
};
};
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
+
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
};
--
1.7.9.5
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[net-next PATCH v3 4/6] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360..acbcac3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
--
1.7.9.5
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[net-next PATCH v3 3/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-bone.dts | 38 +
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 5302f79..97294a6 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,33 @@
0x60 0x17 /* gpmc_a8.gpio1_24,
OUTPUT_PULLUP | MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x110 0x20 /* mii1_rxerr.mii1_rxerr, MODE0
| INPUT */
+ 0x114 0x0 /* mii1_txen.mii1_txen, MODE0 |
OUTPUT */
+ 0x118 0x20 /* mii1_rxdv.mii1_rxdv, MODE0 |
INPUT_PULLDOWN */
+ 0x11c 0x0 /* mii1_txd3.mii1_txd3, MODE0 |
OUTPUT */
+ 0x120 0x0 /* mii1_txd2.mii1_txd2, MODE0 |
OUTPUT */
+ 0x124 0x0 /* mii1_txd1.mii1_txd1, MODE0 |
OUTPUT */
+ 0x128 0x0 /* mii1_txd0.mii1_txd0, MODE0 |
OUTPUT */
+ 0x12c 0x20 /* mii1_txclk.mii1_txclk, MODE0
| INPUT_PULLDOWN */
+ 0x130 0x20 /* mii1_rxclk.mii1_rxclk, MODE0
| INPUT_PULLDOWN */
+ 0x134 0x20 /* mii1_rxd3.mii1_rxd3, MODE0 |
INPUT_PULLDOWN */
+ 0x138 0x20 /* mii1_rxd2.mii1_rxd2, MODE0 |
INPUT_PULLDOWN */
+ 0x13c 0x20 /* mii1_rxd1.mii1_rxd1, MODE0 |
INPUT_PULLDOWN */
+ 0x140 0x20 /* mii1_rxd0.mii1_rxd0, MODE0 |
INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -136,3 +163,14 @@
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
};
+
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
--
1.7.9.5
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[net-next PATCH v3 2/6] net: davinci_mdio: enhance pinctrl support
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/davinci_mdio.c | 45
1 file changed, 45 insertions(+)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c
b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec17..9e6aaeb 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -38,6 +38,7 @@
#include
#include
#include
+#include
/*
* This timeout definition is a worst-case ultra defensive measure against
@@ -94,6 +95,11 @@ struct davinci_mdio_data {
struct mii_bus *bus;
boolsuspended;
unsigned long access_time; /* jiffies */
+
+ /* Two optional pin states - default & sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_def;
+ struct pinctrl_state*pins_sleep;
};
static void __davinci_mdio_reset(struct davinci_mdio_data *data)
@@ -347,6 +353,35 @@ static int davinci_mdio_probe(struct platform_device *pdev)
data->bus->parent = dev;
data->bus->priv = data;
+ data->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (!IS_ERR(data->pinctrl)) {
+ data->pins_def = pinctrl_lookup_state(data->pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(data->pins_def))
+ dev_warn(&pdev->dev, "could not get default
pinstate\n");
+ else
+ if (pinctrl_select_state(data->pinctrl,
+data->pins_def))
+ dev_err(&pdev->dev,
+ "could not set default pins\n");
+
+ data->pins_sleep = pinctrl_lookup_state(data->pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(data->pins_sleep))
+ dev_warn(&pdev->dev, "could not get sleep pinstate\n");
+ } else {
+ /* Since we continue even when pinctrl node is not found,
+* Invalidate pins as not available. This is to make sure that
+* IS_ERR(pins_xxx) results in failure when used.
+*/
+ data->pins_def = ERR_PTR(-ENODATA);
+ data->pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(&pdev->dev,
+"pins are not configured from the driver\n");
+ }
+
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
data->clk = clk_get(&pdev->dev, "fck");
@@ -454,6 +489,11 @@ static int davinci_mdio_suspend(struct device *dev)
data->suspended = true;
spin_unlock(&data->lock);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(data->pins_sleep))
+ if (pinctrl_select_state(data->pinctrl, data->pins_sleep))
+ dev_err(dev, "could not set pins to sleep state\n");
+
return 0;
}
@@ -465,6 +505,11 @@ static int davinci_mdio_resume(struct device *dev)
spin_lock(&data->lock);
pm_runtime_get_sync(data->dev);
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(data->pins_def))
+ if (pinctrl_select_state(data->pinctrl, data->pins_def))
+ dev_err(dev, "could not set default pins\n");
+
/* restart the scan state machine */
ctrl = __raw_readl(&data->regs->control);
ctrl |= CONTROL_ENABLE;
--
1.7.9.5
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[net-next PATCH v3 1/6] net: cpsw: enhance pinctrl support
From: Hebbar Gururaja
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..c9ed730 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
#include
#include
+#include
#include "cpsw_ale.h"
#include "cpts.h"
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+ /* Two optional pin states - default & sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_def;
+ struct pinctrl_state*pins_sleep;
};
#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
@@ -1689,6 +1695,35 @@ static int cpsw_probe(struct platform_device *pdev)
*/
pm_runtime_enable(&pdev->dev);
+ priv->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (!IS_ERR(priv->pinctrl)) {
+ priv->pins_def = pinctrl_lookup_state(priv->pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(priv->pins_def))
+ dev_warn(&pdev->dev, "could not get default
pinstate\n");
+ else
+ if (pinctrl_select_state(priv->pinctrl,
+priv->pins_def))
+ dev_err(&pdev->dev,
+ "could not set default pins\n");
+
+ priv->pins_sleep = pinctrl_lookup_state(priv->pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(priv->pins_sleep))
+ dev_warn(&pdev->dev, "could not get sleep pinstate\n");
+ } else {
+ /* Since we continue even when pinctrl node is not found,
+* Invalidate pins as not available. This is to make sure that
+* IS_ERR(pins_xxx) results in failure when used.
+*/
+ priv->pins_def = ERR_PTR(-ENODATA);
+ priv->pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(&pdev->dev,
+"pins are not configured from the driver\n");
+ }
+
if (cpsw_probe_dt(&priv->data, pdev)) {
pr_err("cpsw: platform data missing\n");
ret = -ENODEV;
@@ -1973,11 +2008,17 @@ static int cpsw_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
if (netif_running(ndev))
cpsw_ndo_stop(ndev);
pm_runtime_put_sync(&pdev->dev);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(priv->pins_sleep))
+ if (pinctrl_select_state(priv->pinctrl, priv->pins_sleep))
+ dev_err(dev, "could not set pins to sleep state\n");
+
return 0;
}
@@ -1985,8 +2026,15 @@ static int cpsw_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
pm_runtime_get_sync(&pdev->dev);
+
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(priv->pins_def))
+ if (pinctrl_select_state(priv->pinctrl, priv->pins_def))
+ dev_err(dev, "could not set default pins\n");
+
if (netif_running(ndev))
cpsw_ndo_open(ndev);
return 0;
--
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[net-next PATCH v3 0/6] Adding pinctrl PM support for CPSW and MDIO
This patch series adds the following features * Adding pinctrl PM support for CPSW and MDIO for Power Optimization * Adding phy address to the CPSW node for EVMsk board Changes from initial version * Fixed the multiline function call indentation as per David Miller recommendation. Changes from v2 * Fixed the multi comment style as per net coding style * Fixed checkpatch error (more than 80 characters) Hebbar Gururaja (1): net: cpsw: enhance pinctrl support Mugunthan V N (5): net: davinci_mdio: enhance pinctrl support ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM arch/arm/boot/dts/am335x-bone.dts | 38 + arch/arm/boot/dts/am335x-evm.dts | 36 arch/arm/boot/dts/am335x-evmsk.dts | 58 drivers/net/ethernet/ti/cpsw.c | 48 ++ drivers/net/ethernet/ti/davinci_mdio.c | 45 + 5 files changed, 225 insertions(+) -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [net-next PATCH v2 1/6] net: cpsw: enhance pinctrl support
On 5/26/2013 12:12 PM, David Miller wrote: From: Mugunthan V N Date: Thu, 23 May 2013 18:00:23 +0530 From: Hebbar Gururaja Amend cpsw controller to optionally take a pin control handle and set the state of the pins to: - "default" on boot, resume - "sleep" on suspend() This should make it possible to optimize energy usage for the pins for the suspend/resume cycle. If any of the above pin states are missing in dt, a warning message about the missing state is displayed. If certain pin-states are not available, to remove this warning message pass respective state name with null phandler. Signed-off-by: Hebbar Gururaja Signed-off-by: Mugunthan V N This still needs some work: + /* + * Since we continue even when pinctrl node is not found, + * Invalidate pins as not available. This is to make sure that + * IS_ERR(pins_xxx) results in failure when used. + */ The second, third, fourth, and fifth lines are not tabbed correctly. They should all be two TABs and a SPACE. Secondly, comments in the networking are to be formatted: /* Like * this. */ Will fix this and will resubmit the next version today. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[net-next PATCH v2 6/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evm.dts | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0423298..beb2fbf 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,32 @@
0x154 0x27 /* spi0_d0.gpio0_3, INPUT |
MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -237,6 +263,16 @@
};
};
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
+
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
};
--
1.7.9.5
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[net-next PATCH v2 5/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts | 50
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index acbcac3..12cbe4e 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,46 @@
0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT
| MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+
+ /* Slave 2 */
+ 0x40 0x2/* gpmc_a0.rgmii2_tctl", MODE2
| OUTPUT */
+ 0x44 0x22 /* gpmc_a1.rgmii2_rctl", MODE2
| INPUT_PULLDOWN */
+ 0x48 0x2/* gpmc_a2.rgmii2_td3", MODE2 |
OUTPUT */
+ 0x4c 0x2/* gpmc_a3.rgmii2_td2", MODE2 |
OUTPUT */
+ 0x50 0x2/* gpmc_a4.rgmii2_td1", MODE2 |
OUTPUT */
+ 0x54 0x2/* gpmc_a5.rgmii2_td0", MODE2 |
OUTPUT */
+ 0x58 0x2/* gpmc_a6.rgmii2_tclk", MODE2
| OUTPUT */
+ 0x5c 0x22 /* gpmc_a7.rgmii2_rclk", MODE2
| INPUT_PULLDOWN */
+ 0x60 0x22 /* gpmc_a8.rgmii2_rd3", MODE2 |
INPUT_PULLDOWN */
+ 0x64 0x22 /* gpmc_a9.rgmii2_rd2", MODE2 |
INPUT_PULLDOWN */
+ 0x68 0x22 /* gpmc_a10.rgmii2_rd1", MODE2
| INPUT_PULLDOWN */
+ 0x6c 0x22 /* gpmc_a11.rgmii2_rd0", MODE2
| INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -249,6 +289,16 @@
};
};
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
+
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
};
--
1.7.9.5
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[net-next PATCH v2 4/6] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360..acbcac3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
--
1.7.9.5
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[net-next PATCH v2 3/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-bone.dts | 38 +
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 5302f79..97294a6 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,33 @@
0x60 0x17 /* gpmc_a8.gpio1_24,
OUTPUT_PULLUP | MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x110 0x20 /* mii1_rxerr.mii1_rxerr, MODE0
| INPUT */
+ 0x114 0x0 /* mii1_txen.mii1_txen, MODE0 |
OUTPUT */
+ 0x118 0x20 /* mii1_rxdv.mii1_rxdv, MODE0 |
INPUT_PULLDOWN */
+ 0x11c 0x0 /* mii1_txd3.mii1_txd3, MODE0 |
OUTPUT */
+ 0x120 0x0 /* mii1_txd2.mii1_txd2, MODE0 |
OUTPUT */
+ 0x124 0x0 /* mii1_txd1.mii1_txd1, MODE0 |
OUTPUT */
+ 0x128 0x0 /* mii1_txd0.mii1_txd0, MODE0 |
OUTPUT */
+ 0x12c 0x20 /* mii1_txclk.mii1_txclk, MODE0
| INPUT_PULLDOWN */
+ 0x130 0x20 /* mii1_rxclk.mii1_rxclk, MODE0
| INPUT_PULLDOWN */
+ 0x134 0x20 /* mii1_rxd3.mii1_rxd3, MODE0 |
INPUT_PULLDOWN */
+ 0x138 0x20 /* mii1_rxd2.mii1_rxd2, MODE0 |
INPUT_PULLDOWN */
+ 0x13c 0x20 /* mii1_rxd1.mii1_rxd1, MODE0 |
INPUT_PULLDOWN */
+ 0x140 0x20 /* mii1_rxd0.mii1_rxd0, MODE0 |
INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -136,3 +163,14 @@
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
};
+
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
--
1.7.9.5
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[net-next PATCH v2 2/6] net: davinci_mdio: enhance pinctrl support
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/davinci_mdio.c | 46
1 file changed, 46 insertions(+)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c
b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec17..0026006 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -38,6 +38,7 @@
#include
#include
#include
+#include
/*
* This timeout definition is a worst-case ultra defensive measure against
@@ -94,6 +95,11 @@ struct davinci_mdio_data {
struct mii_bus *bus;
boolsuspended;
unsigned long access_time; /* jiffies */
+
+ /* Two optional pin states - default & sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_default;
+ struct pinctrl_state*pins_sleep;
};
static void __davinci_mdio_reset(struct davinci_mdio_data *data)
@@ -347,6 +353,36 @@ static int davinci_mdio_probe(struct platform_device *pdev)
data->bus->parent = dev;
data->bus->priv = data;
+ data->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (!IS_ERR(data->pinctrl)) {
+ data->pins_default = pinctrl_lookup_state(data->pinctrl,
+
PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(data->pins_default))
+ dev_warn(&pdev->dev, "could not get default
pinstate\n");
+ else
+ if (pinctrl_select_state(data->pinctrl,
+data->pins_default))
+ dev_err(&pdev->dev,
+ "could not set default pins\n");
+
+ data->pins_sleep = pinctrl_lookup_state(data->pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(data->pins_sleep))
+ dev_warn(&pdev->dev, "could not get sleep pinstate\n");
+ } else {
+ /*
+ * Since we continue even when pinctrl node is not found,
+ * Invalidate pins as not available. This is to make sure that
+ * IS_ERR(pins_xxx) results in failure when used.
+ */
+ data->pins_default = ERR_PTR(-ENODATA);
+ data->pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(&pdev->dev,
+"pins are not configured from the driver\n");
+ }
+
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
data->clk = clk_get(&pdev->dev, "fck");
@@ -454,6 +490,11 @@ static int davinci_mdio_suspend(struct device *dev)
data->suspended = true;
spin_unlock(&data->lock);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(data->pins_sleep))
+ if (pinctrl_select_state(data->pinctrl, data->pins_sleep))
+ dev_err(dev, "could not set pins to sleep state\n");
+
return 0;
}
@@ -465,6 +506,11 @@ static int davinci_mdio_resume(struct device *dev)
spin_lock(&data->lock);
pm_runtime_get_sync(data->dev);
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(data->pins_default))
+ if (pinctrl_select_state(data->pinctrl, data->pins_default))
+ dev_err(dev, "could not set default pins\n");
+
/* restart the scan state machine */
ctrl = __raw_readl(&data->regs->control);
ctrl |= CONTROL_ENABLE;
--
1.7.9.5
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[net-next PATCH v2 1/6] net: cpsw: enhance pinctrl support
From: Hebbar Gururaja
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 49
1 file changed, 49 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..1150f06 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
#include
#include
+#include
#include "cpsw_ale.h"
#include "cpts.h"
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+ /* Two optional pin states - default & sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_default;
+ struct pinctrl_state*pins_sleep;
};
#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
@@ -1689,6 +1695,36 @@ static int cpsw_probe(struct platform_device *pdev)
*/
pm_runtime_enable(&pdev->dev);
+ priv->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (!IS_ERR(priv->pinctrl)) {
+ priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
+
PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(priv->pins_default))
+ dev_warn(&pdev->dev, "could not get default
pinstate\n");
+ else
+ if (pinctrl_select_state(priv->pinctrl,
+priv->pins_default))
+ dev_err(&pdev->dev,
+ "could not set default pins\n");
+
+ priv->pins_sleep = pinctrl_lookup_state(priv->pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(priv->pins_sleep))
+ dev_warn(&pdev->dev, "could not get sleep pinstate\n");
+ } else {
+ /*
+ * Since we continue even when pinctrl node is not found,
+ * Invalidate pins as not available. This is to make sure that
+ * IS_ERR(pins_xxx) results in failure when used.
+ */
+ priv->pins_default = ERR_PTR(-ENODATA);
+ priv->pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(&pdev->dev,
+"pins are not configured from the driver\n");
+ }
+
if (cpsw_probe_dt(&priv->data, pdev)) {
pr_err("cpsw: platform data missing\n");
ret = -ENODEV;
@@ -1973,11 +2009,17 @@ static int cpsw_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
if (netif_running(ndev))
cpsw_ndo_stop(ndev);
pm_runtime_put_sync(&pdev->dev);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(priv->pins_sleep))
+ if (pinctrl_select_state(priv->pinctrl, priv->pins_sleep))
+ dev_err(dev, "could not set pins to sleep state\n");
+
return 0;
}
@@ -1985,8 +2027,15 @@ static int cpsw_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
pm_runtime_get_sync(&pdev->dev);
+
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(priv->pins_default))
+ if (pinctrl_select_state(priv->pinctrl, priv->pins_default))
+ dev_err(dev, "could not set default pins\n");
+
if (netif_running(ndev))
cpsw_ndo_open(ndev);
return 0;
--
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[net-next PATCH v2 0/6] Adding pinctrl PM support for CPSW and MDIO
This patch series adds the following features * Adding pinctrl PM support for CPSW and MDIO for Power Optimization * Adding phy address to the CPSW node for EVMsk board Changes from initial version * Fixed the multiline function call indentation as per David Miller recommendation. Hebbar Gururaja (1): net: cpsw: enhance pinctrl support Mugunthan V N (5): net: davinci_mdio: enhance pinctrl support ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM arch/arm/boot/dts/am335x-bone.dts | 38 + arch/arm/boot/dts/am335x-evm.dts | 36 arch/arm/boot/dts/am335x-evmsk.dts | 58 drivers/net/ethernet/ti/cpsw.c | 49 +++ drivers/net/ethernet/ti/davinci_mdio.c | 46 + 5 files changed, 227 insertions(+) -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [net-next resend PATCH 1/6] net: cpsw: enhance pinctrl support
On 5/23/2013 12:27 PM, David Miller wrote: From: Mugunthan V N Date: Tue, 21 May 2013 15:24:58 +0530 + priv->pins_default = pinctrl_lookup_state(priv->pinctrl, + PINCTRL_STATE_DEFAULT); This is not indented correctly. Argument on the second, and subsequent, lines of a function call must start at the first column after the openning parenthesis of the function call itself. Please audit for this problem in your entire patch series, fix it up, and resubmit the full set of patches. Thanks. Will fix it and submit the patch. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[net-next resend PATCH 6/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evm.dts | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0423298..beb2fbf 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,32 @@
0x154 0x27 /* spi0_d0.gpio0_3, INPUT |
MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -237,6 +263,16 @@
};
};
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
+
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
};
--
1.7.9.5
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[net-next resend PATCH 5/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts | 50
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index acbcac3..12cbe4e 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,46 @@
0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT
| MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+
+ /* Slave 2 */
+ 0x40 0x2/* gpmc_a0.rgmii2_tctl", MODE2
| OUTPUT */
+ 0x44 0x22 /* gpmc_a1.rgmii2_rctl", MODE2
| INPUT_PULLDOWN */
+ 0x48 0x2/* gpmc_a2.rgmii2_td3", MODE2 |
OUTPUT */
+ 0x4c 0x2/* gpmc_a3.rgmii2_td2", MODE2 |
OUTPUT */
+ 0x50 0x2/* gpmc_a4.rgmii2_td1", MODE2 |
OUTPUT */
+ 0x54 0x2/* gpmc_a5.rgmii2_td0", MODE2 |
OUTPUT */
+ 0x58 0x2/* gpmc_a6.rgmii2_tclk", MODE2
| OUTPUT */
+ 0x5c 0x22 /* gpmc_a7.rgmii2_rclk", MODE2
| INPUT_PULLDOWN */
+ 0x60 0x22 /* gpmc_a8.rgmii2_rd3", MODE2 |
INPUT_PULLDOWN */
+ 0x64 0x22 /* gpmc_a9.rgmii2_rd2", MODE2 |
INPUT_PULLDOWN */
+ 0x68 0x22 /* gpmc_a10.rgmii2_rd1", MODE2
| INPUT_PULLDOWN */
+ 0x6c 0x22 /* gpmc_a11.rgmii2_rd0", MODE2
| INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -249,6 +289,16 @@
};
};
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
+
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
};
--
1.7.9.5
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[net-next resend PATCH 4/6] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360..acbcac3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
--
1.7.9.5
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[net-next resend PATCH 3/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-bone.dts | 38 +
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 5302f79..97294a6 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,33 @@
0x60 0x17 /* gpmc_a8.gpio1_24,
OUTPUT_PULLUP | MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x110 0x20 /* mii1_rxerr.mii1_rxerr, MODE0
| INPUT */
+ 0x114 0x0 /* mii1_txen.mii1_txen, MODE0 |
OUTPUT */
+ 0x118 0x20 /* mii1_rxdv.mii1_rxdv, MODE0 |
INPUT_PULLDOWN */
+ 0x11c 0x0 /* mii1_txd3.mii1_txd3, MODE0 |
OUTPUT */
+ 0x120 0x0 /* mii1_txd2.mii1_txd2, MODE0 |
OUTPUT */
+ 0x124 0x0 /* mii1_txd1.mii1_txd1, MODE0 |
OUTPUT */
+ 0x128 0x0 /* mii1_txd0.mii1_txd0, MODE0 |
OUTPUT */
+ 0x12c 0x20 /* mii1_txclk.mii1_txclk, MODE0
| INPUT_PULLDOWN */
+ 0x130 0x20 /* mii1_rxclk.mii1_rxclk, MODE0
| INPUT_PULLDOWN */
+ 0x134 0x20 /* mii1_rxd3.mii1_rxd3, MODE0 |
INPUT_PULLDOWN */
+ 0x138 0x20 /* mii1_rxd2.mii1_rxd2, MODE0 |
INPUT_PULLDOWN */
+ 0x13c 0x20 /* mii1_rxd1.mii1_rxd1, MODE0 |
INPUT_PULLDOWN */
+ 0x140 0x20 /* mii1_rxd0.mii1_rxd0, MODE0 |
INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -136,3 +163,14 @@
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
};
+
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
--
1.7.9.5
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[net-next resend PATCH 2/6] net: davinci_mdio: enhance pinctrl support
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/davinci_mdio.c | 46
1 file changed, 46 insertions(+)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c
b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec17..be81d3e 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -38,6 +38,7 @@
#include
#include
#include
+#include
/*
* This timeout definition is a worst-case ultra defensive measure against
@@ -94,6 +95,11 @@ struct davinci_mdio_data {
struct mii_bus *bus;
boolsuspended;
unsigned long access_time; /* jiffies */
+
+ /* Two optional pin states - default & sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_default;
+ struct pinctrl_state*pins_sleep;
};
static void __davinci_mdio_reset(struct davinci_mdio_data *data)
@@ -347,6 +353,36 @@ static int davinci_mdio_probe(struct platform_device *pdev)
data->bus->parent = dev;
data->bus->priv = data;
+ data->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (!IS_ERR(data->pinctrl)) {
+ data->pins_default = pinctrl_lookup_state(data->pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(data->pins_default))
+ dev_warn(&pdev->dev, "could not get default
pinstate\n");
+ else
+ if (pinctrl_select_state(data->pinctrl,
+data->pins_default))
+ dev_err(&pdev->dev,
+ "could not set default pins\n");
+
+ data->pins_sleep = pinctrl_lookup_state(data->pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(data->pins_sleep))
+ dev_warn(&pdev->dev, "could not get sleep pinstate\n");
+ } else {
+ /*
+ * Since we continue even when pinctrl node is not found,
+ * Invalidate pins as not available. This is to make sure that
+ * IS_ERR(pins_xxx) results in failure when used.
+ */
+ data->pins_default = ERR_PTR(-ENODATA);
+ data->pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(&pdev->dev,
+"pins are not configured from the driver\n");
+ }
+
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
data->clk = clk_get(&pdev->dev, "fck");
@@ -454,6 +490,11 @@ static int davinci_mdio_suspend(struct device *dev)
data->suspended = true;
spin_unlock(&data->lock);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(data->pins_sleep))
+ if (pinctrl_select_state(data->pinctrl, data->pins_sleep))
+ dev_err(dev, "could not set pins to sleep state\n");
+
return 0;
}
@@ -465,6 +506,11 @@ static int davinci_mdio_resume(struct device *dev)
spin_lock(&data->lock);
pm_runtime_get_sync(data->dev);
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(data->pins_default))
+ if (pinctrl_select_state(data->pinctrl, data->pins_default))
+ dev_err(dev, "could not set default pins\n");
+
/* restart the scan state machine */
ctrl = __raw_readl(&data->regs->control);
ctrl |= CONTROL_ENABLE;
--
1.7.9.5
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[net-next resend PATCH 1/6] net: cpsw: enhance pinctrl support
From: Hebbar Gururaja
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 49
1 file changed, 49 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..4a6f94b 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
#include
#include
+#include
#include "cpsw_ale.h"
#include "cpts.h"
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+ /* Two optional pin states - default & sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_default;
+ struct pinctrl_state*pins_sleep;
};
#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
@@ -1689,6 +1695,36 @@ static int cpsw_probe(struct platform_device *pdev)
*/
pm_runtime_enable(&pdev->dev);
+ priv->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (!IS_ERR(priv->pinctrl)) {
+ priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(priv->pins_default))
+ dev_warn(&pdev->dev, "could not get default
pinstate\n");
+ else
+ if (pinctrl_select_state(priv->pinctrl,
+priv->pins_default))
+ dev_err(&pdev->dev,
+ "could not set default pins\n");
+
+ priv->pins_sleep = pinctrl_lookup_state(priv->pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(priv->pins_sleep))
+ dev_warn(&pdev->dev, "could not get sleep pinstate\n");
+ } else {
+ /*
+ * Since we continue even when pinctrl node is not found,
+ * Invalidate pins as not available. This is to make sure that
+ * IS_ERR(pins_xxx) results in failure when used.
+ */
+ priv->pins_default = ERR_PTR(-ENODATA);
+ priv->pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(&pdev->dev,
+"pins are not configured from the driver\n");
+ }
+
if (cpsw_probe_dt(&priv->data, pdev)) {
pr_err("cpsw: platform data missing\n");
ret = -ENODEV;
@@ -1973,11 +2009,17 @@ static int cpsw_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
if (netif_running(ndev))
cpsw_ndo_stop(ndev);
pm_runtime_put_sync(&pdev->dev);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(priv->pins_sleep))
+ if (pinctrl_select_state(priv->pinctrl, priv->pins_sleep))
+ dev_err(dev, "could not set pins to sleep state\n");
+
return 0;
}
@@ -1985,8 +2027,15 @@ static int cpsw_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
pm_runtime_get_sync(&pdev->dev);
+
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(priv->pins_default))
+ if (pinctrl_select_state(priv->pinctrl, priv->pins_default))
+ dev_err(dev, "could not set default pins\n");
+
if (netif_running(ndev))
cpsw_ndo_open(ndev);
return 0;
--
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[net-next resend PATCH 0/6] Adding pinctrl PM support for CPSW and MDIO
Resending the same patch series as it is dropped which was sent during merge window This patch series adds the following features * Adding pinctrl PM support for CPSW and MDIO for Power Optimization * Adding phy address to the CPSW node for EVMsk board Hebbar Gururaja (1): net: cpsw: enhance pinctrl support Mugunthan V N (5): net: davinci_mdio: enhance pinctrl support ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM arch/arm/boot/dts/am335x-bone.dts | 38 + arch/arm/boot/dts/am335x-evm.dts | 36 arch/arm/boot/dts/am335x-evmsk.dts | 58 drivers/net/ethernet/ti/cpsw.c | 49 +++ drivers/net/ethernet/ti/davinci_mdio.c | 46 + 5 files changed, 227 insertions(+) -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [net-next PATCH 0/6] Adding pinctrl PM support for CPSW and Davinci MDIO drivers
On 5/3/2013 1:12 PM, David Miller wrote: Please read: http://marc.info/?l=linux-netdev&m=136730964130303&w=2 Sorry, will resend the patch series one net is merged with net-next. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[net-next PATCH 6/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evm.dts | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..e7f91e8 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,32 @@
0x154 0x27 /* spi0_d0.gpio0_3, INPUT |
MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -237,6 +263,16 @@
};
};
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
+
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
};
--
1.7.9.5
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[net-next PATCH 5/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
Add pinmux configurations for MII based CPSW ethernet to AM335x EVMsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts | 50
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f297b85..d2c4b45 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -51,6 +51,46 @@
0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT
| MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+
+ /* Slave 2 */
+ 0x40 0x2/* gpmc_a0.rgmii2_tctl", MODE2
| OUTPUT */
+ 0x44 0x22 /* gpmc_a1.rgmii2_rctl", MODE2
| INPUT_PULLDOWN */
+ 0x48 0x2/* gpmc_a2.rgmii2_td3", MODE2 |
OUTPUT */
+ 0x4c 0x2/* gpmc_a3.rgmii2_td2", MODE2 |
OUTPUT */
+ 0x50 0x2/* gpmc_a4.rgmii2_td1", MODE2 |
OUTPUT */
+ 0x54 0x2/* gpmc_a5.rgmii2_td0", MODE2 |
OUTPUT */
+ 0x58 0x2/* gpmc_a6.rgmii2_tclk", MODE2
| OUTPUT */
+ 0x5c 0x22 /* gpmc_a7.rgmii2_rclk", MODE2
| INPUT_PULLDOWN */
+ 0x60 0x22 /* gpmc_a8.rgmii2_rd3", MODE2 |
INPUT_PULLDOWN */
+ 0x64 0x22 /* gpmc_a9.rgmii2_rd2", MODE2 |
INPUT_PULLDOWN */
+ 0x68 0x22 /* gpmc_a10.rgmii2_rd1", MODE2
| INPUT_PULLDOWN */
+ 0x6c 0x22 /* gpmc_a11.rgmii2_rd0", MODE2
| INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -249,6 +289,16 @@
};
};
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
+
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
};
--
1.7.9.5
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[net-next PATCH 4/6] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f5a6162..f297b85 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
--
1.7.9.5
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[net-next PATCH 3/6] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Todo:
- if an idle state is available for pins, add support for it.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-bone.dts | 38 +
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 11b240c..60565f5 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,6 +36,33 @@
0x60 0x17 /* gpmc_a8.gpio1_24,
OUTPUT_PULLUP | MODE7 */
>;
};
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x110 0x20 /* mii1_rxerr.mii1_rxerr, MODE0
| INPUT */
+ 0x114 0x0 /* mii1_txen.mii1_txen, MODE0 |
OUTPUT */
+ 0x118 0x20 /* mii1_rxdv.mii1_rxdv, MODE0 |
INPUT_PULLDOWN */
+ 0x11c 0x0 /* mii1_txd3.mii1_txd3, MODE0 |
OUTPUT */
+ 0x120 0x0 /* mii1_txd2.mii1_txd2, MODE0 |
OUTPUT */
+ 0x124 0x0 /* mii1_txd1.mii1_txd1, MODE0 |
OUTPUT */
+ 0x128 0x0 /* mii1_txd0.mii1_txd0, MODE0 |
OUTPUT */
+ 0x12c 0x20 /* mii1_txclk.mii1_txclk, MODE0
| INPUT_PULLDOWN */
+ 0x130 0x20 /* mii1_rxclk.mii1_rxclk, MODE0
| INPUT_PULLDOWN */
+ 0x134 0x20 /* mii1_rxd3.mii1_rxd3, MODE0 |
INPUT_PULLDOWN */
+ 0x138 0x20 /* mii1_rxd2.mii1_rxd2, MODE0 |
INPUT_PULLDOWN */
+ 0x13c 0x20 /* mii1_rxd1.mii1_rxd1, MODE0 |
INPUT_PULLDOWN */
+ 0x140 0x20 /* mii1_rxd0.mii1_rxd0, MODE0 |
INPUT_PULLDOWN */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
@@ -136,3 +163,14 @@
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
};
+
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+};
--
1.7.9.5
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[net-next PATCH 2/6] net: davinci_mdio: enhance pinctrl support
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/davinci_mdio.c | 46
1 file changed, 46 insertions(+)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c
b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec17..be81d3e 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -38,6 +38,7 @@
#include
#include
#include
+#include
/*
* This timeout definition is a worst-case ultra defensive measure against
@@ -94,6 +95,11 @@ struct davinci_mdio_data {
struct mii_bus *bus;
boolsuspended;
unsigned long access_time; /* jiffies */
+
+ /* Two optional pin states - default & sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_default;
+ struct pinctrl_state*pins_sleep;
};
static void __davinci_mdio_reset(struct davinci_mdio_data *data)
@@ -347,6 +353,36 @@ static int davinci_mdio_probe(struct platform_device *pdev)
data->bus->parent = dev;
data->bus->priv = data;
+ data->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (!IS_ERR(data->pinctrl)) {
+ data->pins_default = pinctrl_lookup_state(data->pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(data->pins_default))
+ dev_warn(&pdev->dev, "could not get default
pinstate\n");
+ else
+ if (pinctrl_select_state(data->pinctrl,
+data->pins_default))
+ dev_err(&pdev->dev,
+ "could not set default pins\n");
+
+ data->pins_sleep = pinctrl_lookup_state(data->pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(data->pins_sleep))
+ dev_warn(&pdev->dev, "could not get sleep pinstate\n");
+ } else {
+ /*
+ * Since we continue even when pinctrl node is not found,
+ * Invalidate pins as not available. This is to make sure that
+ * IS_ERR(pins_xxx) results in failure when used.
+ */
+ data->pins_default = ERR_PTR(-ENODATA);
+ data->pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(&pdev->dev,
+"pins are not configured from the driver\n");
+ }
+
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
data->clk = clk_get(&pdev->dev, "fck");
@@ -454,6 +490,11 @@ static int davinci_mdio_suspend(struct device *dev)
data->suspended = true;
spin_unlock(&data->lock);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(data->pins_sleep))
+ if (pinctrl_select_state(data->pinctrl, data->pins_sleep))
+ dev_err(dev, "could not set pins to sleep state\n");
+
return 0;
}
@@ -465,6 +506,11 @@ static int davinci_mdio_resume(struct device *dev)
spin_lock(&data->lock);
pm_runtime_get_sync(data->dev);
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(data->pins_default))
+ if (pinctrl_select_state(data->pinctrl, data->pins_default))
+ dev_err(dev, "could not set default pins\n");
+
/* restart the scan state machine */
ctrl = __raw_readl(&data->regs->control);
ctrl |= CONTROL_ENABLE;
--
1.7.9.5
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[net-next PATCH 1/6] net: cpsw: enhance pinctrl support
From: Hebbar Gururaja
Amend cpsw controller to optionally take a pin control handle and set
the state of the pins to:
- "default" on boot, resume
- "sleep" on suspend()
This should make it possible to optimize energy usage for the pins
for the suspend/resume cycle.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 49
1 file changed, 49 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 21a5b29..4a6f94b 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -35,6 +35,7 @@
#include
#include
+#include
#include "cpsw_ale.h"
#include "cpts.h"
@@ -351,6 +352,11 @@ struct cpsw_priv {
bool irq_enabled;
struct cpts *cpts;
u32 emac_port;
+
+ /* Two optional pin states - default & sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_default;
+ struct pinctrl_state*pins_sleep;
};
#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
@@ -1689,6 +1695,36 @@ static int cpsw_probe(struct platform_device *pdev)
*/
pm_runtime_enable(&pdev->dev);
+ priv->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (!IS_ERR(priv->pinctrl)) {
+ priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ /* enable pins to be muxed in and configured */
+ if (IS_ERR(priv->pins_default))
+ dev_warn(&pdev->dev, "could not get default
pinstate\n");
+ else
+ if (pinctrl_select_state(priv->pinctrl,
+priv->pins_default))
+ dev_err(&pdev->dev,
+ "could not set default pins\n");
+
+ priv->pins_sleep = pinctrl_lookup_state(priv->pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(priv->pins_sleep))
+ dev_warn(&pdev->dev, "could not get sleep pinstate\n");
+ } else {
+ /*
+ * Since we continue even when pinctrl node is not found,
+ * Invalidate pins as not available. This is to make sure that
+ * IS_ERR(pins_xxx) results in failure when used.
+ */
+ priv->pins_default = ERR_PTR(-ENODATA);
+ priv->pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_warn(&pdev->dev,
+"pins are not configured from the driver\n");
+ }
+
if (cpsw_probe_dt(&priv->data, pdev)) {
pr_err("cpsw: platform data missing\n");
ret = -ENODEV;
@@ -1973,11 +2009,17 @@ static int cpsw_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
if (netif_running(ndev))
cpsw_ndo_stop(ndev);
pm_runtime_put_sync(&pdev->dev);
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(priv->pins_sleep))
+ if (pinctrl_select_state(priv->pinctrl, priv->pins_sleep))
+ dev_err(dev, "could not set pins to sleep state\n");
+
return 0;
}
@@ -1985,8 +2027,15 @@ static int cpsw_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct net_device *ndev = platform_get_drvdata(pdev);
+ struct cpsw_priv*priv = netdev_priv(ndev);
pm_runtime_get_sync(&pdev->dev);
+
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(priv->pins_default))
+ if (pinctrl_select_state(priv->pinctrl, priv->pins_default))
+ dev_err(dev, "could not set default pins\n");
+
if (netif_running(ndev))
cpsw_ndo_open(ndev);
return 0;
--
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[net-next PATCH 0/6] Adding pinctrl PM support for CPSW and Davinci MDIO drivers
This patch series adds the following features * Adding pinctrl PM support for CPSW and MDIO for Power Optimization * Adding phy address to the CPSW node for EVMsk board Hebbar Gururaja (1): net: cpsw: enhance pinctrl support Mugunthan V N (5): net: davinci_mdio: enhance pinctrl support ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM arch/arm/boot/dts/am335x-bone.dts | 38 + arch/arm/boot/dts/am335x-evm.dts | 36 arch/arm/boot/dts/am335x-evmsk.dts | 58 drivers/net/ethernet/ti/cpsw.c | 49 +++ drivers/net/ethernet/ti/davinci_mdio.c | 46 + 5 files changed, 227 insertions(+) -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [net-next PATCH 1/3] drivers: of: add phy fixup support in DT
On 4/25/2013 1:26 PM, David Miller wrote: From: Mugunthan V N Date: Mon, 22 Apr 2013 23:50:36 +0530 In earlier case phy fixup are added in board file as this is no more the case so adding support for phy register fixup in Device Tree Signed-off-by: Mugunthan V N When people put a series of undocumented PHY register writes using constants, we tell them it's firmware. If these PHY registers are actually documented in the driver, write a function in that driver which does the programming sequence, then add a property that the driver looks for in order to determine whether to call that sequence or not. I don't want people putting random PHY raw programming sequences and other crap like that into the OF device nodes. It's extremely inelegant and inviting abuse. Will modify the source as per your comments and will submit v2 patch set. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [net-next PATCH 0/3] Adding phy register fixup in DT
On 4/23/2013 1:32 PM, Sascha Hauer wrote: On Mon, Apr 22, 2013 at 11:50:35PM +0530, Mugunthan V N wrote: In earlier days phy fixup was added to phy frame work in board files. As there won't be any board files here after the same has to be done in DT This patch series adds the following features * support for adding phy resigter fixup via DT * adds phy id for EVMsk n DTS file * adds phy fixup for AM335x EVM and EVMsk Mugunthan V N (3): drivers: of: add phy fixup support in DT ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk ARM: dts: AM33XX: add phy fixup for evm and evmsk boards I generally do not offend to phy fixups from the devicetree. I see though that becomes more and more common that we have to configure the tx delays in phys. The current way seems to be to hardcode register values for each board which seems not very flexible and forces us to read phy datasheets each time for a new board. Wouldn't it make more sense to configure the actual delays (in ns) and let the phy drivers figure out how to turn this into register values? Not that I volunteer to write such things... :-/ There is no calculation done for enabling RGMII Tx internal delay. Its all pre-calculated in Hardware (Either in Phy or EMAC) In this patch as CPSW IP in AM335x doesn't support internal delay inside SoC, so enabling the same in Phy and it is just a bit set in the phy debug registers Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[net-next PATCH 3/3] ARM: dts: AM33XX: add phy fixup for evm and evmsk boards
As RGMII tx clock internal delay is not supported in AM335x, the same has
to be enabled in phy. This patch adds support for enabling tx clock internal
delay via phy debug registers
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evm.dts | 10 ++
arch/arm/boot/dts/am335x-evmsk.dts | 10 ++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..72805c5 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -244,3 +244,13 @@
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
};
+
+&davinci_mdio {
+ phy-fixup-registers = <&atheros_txclk_delay_fixup>;
+
+ atheros_txclk_delay_fixup: atheros_txclk_delay_fixup {
+ phy-id = <0x4dd074>;
+ phy-mask = <0xfffe>;
+ fixup-registers = <0x1d 0x5 0x1e 0x100>;
+ };
+};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f297b85..f398cb3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -256,3 +256,13 @@
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
};
+
+&davinci_mdio {
+ phy-fixup-registers = <&atheros_txclk_delay_fixup>;
+
+ atheros_txclk_delay_fixup: atheros_txclk_delay_fixup {
+ phy-id = <0x4dd074>;
+ phy-mask = <0xfffe>;
+ fixup-registers = <0x1d 0x5 0x1e 0x100>;
+ };
+};
--
1.7.9.5
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[net-next PATCH 2/3] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f5a6162..f297b85 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
--
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[net-next PATCH 1/3] drivers: of: add phy fixup support in DT
In earlier case phy fixup are added in board file as this is no more the case
so adding support for phy register fixup in Device Tree
Signed-off-by: Mugunthan V N
---
.../devicetree/bindings/net/phy-fixup.txt | 26 ++
drivers/of/of_net.c| 92
include/linux/of_net.h |6 ++
3 files changed, 124 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/phy-fixup.txt
diff --git a/Documentation/devicetree/bindings/net/phy-fixup.txt
b/Documentation/devicetree/bindings/net/phy-fixup.txt
new file mode 100644
index 000..460f76d
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/phy-fixup.txt
@@ -0,0 +1,26 @@
+Ethernet Phy fixup Device Tree Bindings
+---
+
+The following DT fields can be added to MDIO DT notes and can be used to
+add phy fix up needed
+
+Required properties:
+- phy-fixup-registers : Will contain a array of register fix nodes which has
+ the following node parameters
+- phy-id : Specifies the phy id for which the fix belongs to
+- phy-mask : Specifies the phy mask for which the fix belongs to
+- fixup-registers : Specifies the fix up registers and values in array
+ of offset value pair
+Optional properties:
+
+Examples:
+
+&davinci_mdio {
+ phy-fixup-registers = <&atheros_txclk_delay_fixup>;
+
+ atheros_txclk_delay_fixup: atheros_txclk_delay_fixup {
+ phy-id = <0x4dd074>;
+ phy-mask = <0xfffe>;
+ fixup-registers = <0x1d 0x5 0x1e 0x100>;
+ };
+};
diff --git a/drivers/of/of_net.c b/drivers/of/of_net.c
index ffab033..50ad671 100644
--- a/drivers/of/of_net.c
+++ b/drivers/of/of_net.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
/**
* It maps 'enum phy_interface_t' found in include/linux/phy.h
@@ -92,3 +93,94 @@ const void *of_get_mac_address(struct device_node *np)
return NULL;
}
EXPORT_SYMBOL(of_get_mac_address);
+
+static int __of_phy_fixup_cb(struct phy_device *phydev)
+{
+ struct device_node *node = phydev->bus->parent->of_node;
+ struct device_node *phy_fixup_node;
+ const __be32 *parp;
+ int lenp;
+ int i, j;
+
+ parp = of_get_property(node, "phy-fixup-registers", &lenp);
+ if (parp == NULL)
+ return 0;
+ lenp /= sizeof(void *);
+
+ for (i = 0; i < lenp; i++) {
+ u32 phy_id;
+ const __be32 *fixups;
+ int fixup_len;
+
+ phy_fixup_node = of_find_node_by_phandle(be32_to_cpup(parp+i));
+ if (of_property_read_u32(phy_fixup_node, "phy-id", &phy_id)) {
+ pr_err("Missing PHY id in Phy fixup\n");
+ return -EINVAL;
+ }
+ if (phy_id != phydev->phy_id)
+ continue;
+
+ fixups = of_get_property(phy_fixup_node, "fixup-registers",
+&fixup_len);
+ if (fixups == NULL) {
+ pr_err("Missing fixup registers in Phy fixup\n");
+ return -EINVAL;
+ }
+ fixup_len /= sizeof(void *);
+ for (j = 0; j < fixup_len; j += 2) {
+ u16 regnum = be32_to_cpup(fixups + j);
+ u16 val = be32_to_cpup(fixups + j + 1);
+ phy_write(phydev, regnum, val);
+ }
+ }
+
+ return 0;
+}
+
+int of_add_phy_fixup_register(struct device_node *node)
+{
+ struct device_node *phy_fixup_node;
+ const __be32 *parp;
+ int lenp;
+ int i;
+
+ parp = of_get_property(node, "phy-fixup-registers", &lenp);
+ if (parp == NULL)
+ return 0;
+ lenp /= sizeof(void *);
+
+ for (i = 0; i < lenp; i++) {
+ u32 phy_id;
+ u32 phy_mask;
+ const __be32 *fixups;
+ int fixup_len;
+
+ phy_fixup_node = of_find_node_by_phandle(be32_to_cpup(parp+i));
+ if (of_property_read_u32(phy_fixup_node, "phy-id", &phy_id)) {
+ pr_err("Missing PHY id in Phy fixup\n");
+ continue;
+ }
+
+ if (of_property_read_u32(phy_fixup_node, "phy-mask",
+&phy_mask)) {
+ pr_err("Missing PHY mask in Phy fixup\n");
+ continue;
+ }
+
+ fixups = of_get_property(phy_fixup_node, "fixup-registers",
+&fixup_len);
+ if (fixups == NULL) {
+
[net-next PATCH 0/3] Adding phy register fixup in DT
In earlier days phy fixup was added to phy frame work in board files. As there won't be any board files here after the same has to be done in DT This patch series adds the following features * support for adding phy resigter fixup via DT * adds phy id for EVMsk n DTS file * adds phy fixup for AM335x EVM and EVMsk Mugunthan V N (3): drivers: of: add phy fixup support in DT ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk ARM: dts: AM33XX: add phy fixup for evm and evmsk boards .../devicetree/bindings/net/phy-fixup.txt | 26 ++ arch/arm/boot/dts/am335x-evm.dts | 10 +++ arch/arm/boot/dts/am335x-evmsk.dts | 18 drivers/of/of_net.c| 92 include/linux/of_net.h |6 ++ 5 files changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/phy-fixup.txt -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH 0/3] add pin-mux configuration for AM33xx CPSW
Adding pinmux configuration to AM33xx board dts file. Mugunthan V N (3): ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM arch/arm/boot/dts/am335x-bone.dts | 25 +++- arch/arm/boot/dts/am335x-evm.dts | 24 ++- arch/arm/boot/dts/am335x-evmsk.dts | 38 +++- 3 files changed, 84 insertions(+), 3 deletions(-) -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH 1/3] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-bone.dts | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 11b240c..f90e665 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -26,7 +26,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";
- pinctrl-0 = <&user_leds_s0>;
+ pinctrl-0 = <&user_leds_s0 &cpsw_s0>;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
@@ -36,6 +36,29 @@
0x60 0x17 /* gpmc_a8.gpio1_24,
OUTPUT_PULLUP | MODE7 */
>;
};
+
+ cpsw_s0: cpsw_s0 {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x110 0x20 /* mii1_rxerr.mii1_rxerr, MODE0
| INPUT */
+ 0x114 0x0 /* mii1_txen.mii1_txen, MODE0 |
OUTPUT */
+ 0x118 0x20 /* mii1_rxdv.mii1_rxdv, MODE0 |
INPUT_PULLDOWN */
+ 0x11c 0x0 /* mii1_txd3.mii1_txd3, MODE0 |
OUTPUT */
+ 0x120 0x0 /* mii1_txd2.mii1_txd2, MODE0 |
OUTPUT */
+ 0x124 0x0 /* mii1_txd1.mii1_txd1, MODE0 |
OUTPUT */
+ 0x128 0x0 /* mii1_txd0.mii1_txd0, MODE0 |
OUTPUT */
+ 0x12c 0x20 /* mii1_txclk.mii1_txclk, MODE0
| INPUT_PULLDOWN */
+ 0x130 0x20 /* mii1_rxclk.mii1_rxclk, MODE0
| INPUT_PULLDOWN */
+ 0x134 0x20 /* mii1_rxd3.mii1_rxd3, MODE0 |
INPUT_PULLDOWN */
+ 0x138 0x20 /* mii1_rxd2.mii1_rxd2, MODE0 |
INPUT_PULLDOWN */
+ 0x13c 0x20 /* mii1_rxd1.mii1_rxd1, MODE0 |
INPUT_PULLDOWN */
+ 0x140 0x20 /* mii1_rxd0.mii1_rxd0, MODE0 |
INPUT_PULLDOWN */
+
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
--
1.7.9.5
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[PATCH 2/3] ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
Add pinmux configurations for RGMII based CPSW ethernet to am335x-evmsk.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts | 38 +++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f297b85..9b29ad4 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -32,7 +32,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";
- pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>;
+ pinctrl-0 = <&user_leds_s0 &gpio_keys_s0 &cpsw_s0>;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
@@ -51,6 +51,42 @@
0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT
| MODE7 */
>;
};
+
+ cpsw_s0: cpsw_s0 {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+
+ /* Slave 2 */
+ 0x40 0x2/* gpmc_a0.rgmii2_tctl", MODE2
| OUTPUT */
+ 0x44 0x22 /* gpmc_a1.rgmii2_rctl", MODE2
| INPUT_PULLDOWN */
+ 0x48 0x2/* gpmc_a2.rgmii2_td3", MODE2 |
OUTPUT */
+ 0x4c 0x2/* gpmc_a3.rgmii2_td2", MODE2 |
OUTPUT */
+ 0x50 0x2/* gpmc_a4.rgmii2_td1", MODE2 |
OUTPUT */
+ 0x54 0x2/* gpmc_a5.rgmii2_td0", MODE2 |
OUTPUT */
+ 0x58 0x2/* gpmc_a6.rgmii2_tclk", MODE2
| OUTPUT */
+ 0x5c 0x22 /* gpmc_a7.rgmii2_rclk", MODE2
| INPUT_PULLDOWN */
+ 0x60 0x22 /* gpmc_a8.rgmii2_rd3", MODE2 |
INPUT_PULLDOWN */
+ 0x64 0x22 /* gpmc_a9.rgmii2_rd2", MODE2 |
INPUT_PULLDOWN */
+ 0x68 0x22 /* gpmc_a10.rgmii2_rd1", MODE2
| INPUT_PULLDOWN */
+ 0x6c 0x22 /* gpmc_a11.rgmii2_rd0", MODE2
| INPUT_PULLDOWN */
+
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
--
1.7.9.5
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[PATCH 3/3] ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.
Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evm.dts | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d649644..9327d7d 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -26,7 +26,7 @@
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";
- pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
+ pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &cpsw_s0>;
matrix_keypad_s0: matrix_keypad_s0 {
pinctrl-single,pins = <
@@ -44,6 +44,28 @@
0x154 0x27 /* spi0_d0.gpio0_3, INPUT |
MODE7 */
>;
};
+
+ cpsw_s0: cpsw_s0 {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x114 0x2 /* mii1_txen.rgmii1_tctl, MODE2
| OUTPUT */
+ 0x118 0x22 /* mii1_rxdv.rgmii1_rctl, MODE2
| INPUT_PULLDOWN */
+ 0x11c 0x2 /* mii1_txd3.rgmii1_td3, MODE2
| OUTPUT */
+ 0x120 0x2 /* mii1_txd2.rgmii1_td2, MODE2
| OUTPUT */
+ 0x124 0x2 /* mii1_txd1.rgmii1_td1, MODE2
| OUTPUT */
+ 0x128 0x2 /* mii1_txd0.rgmii1_td0, MODE2
| OUTPUT */
+ 0x12c 0x2 /* mii1_txclk.rgmii1_tclk,
MODE2 | OUTPUT */
+ 0x130 0x22 /* mii1_rxclk.rgmii1_rclk,
MODE2 | INPUT_PULLDOWN */
+ 0x134 0x22 /* mii1_rxd3.rgmii1_rd3, MODE2
| INPUT_PULLDOWN */
+ 0x138 0x22 /* mii1_rxd2.rgmii1_rd2, MODE2
| INPUT_PULLDOWN */
+ 0x13c 0x22 /* mii1_rxd1.rgmii1_rd1, MODE2
| INPUT_PULLDOWN */
+ 0x140 0x22 /* mii1_rxd0.rgmii1_rd0, MODE2
| INPUT_PULLDOWN */
+
+ /* MDIO */
+ 0x148 0x30 /* mdio_data.mdio_data, MODE0 |
INPUT_PULLUP */
+ 0x14c 0x10 /* mdio_clk.mdio_clk, MODE0 |
OUTPUT_PULLUP */
+ >;
+ };
};
ocp {
--
1.7.9.5
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Re: [PATCH] net: ethernet: davinci_emac: make local function emac_poll_controller() static
On 3/20/2013 8:31 PM, Wei Yongjun wrote: From: Wei Yongjun emac_poll_controller() was not declared. It should be static. Signed-off-by: Wei Yongjun Acked-by: Mugunthan V N Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[RESEND PATCH 1/1] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360..acbcac3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
--
1.7.9.5
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[PATCH v2 3/5] driver: net: ethernet: cpsw: implement ethtool get/set phy setting
This patch implements get/set of the phy settings via ethtool apis
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 98aa17a..83ce890 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -139,6 +139,10 @@ do {
\
disable_irq_nosync(priv->irqs_table[i]); \
} while (0);
+#define cpsw_slave_index(priv) \
+ ((priv->data.dual_emac) ? priv->emac_port : \
+ priv->data.active_slave)
+
static int debug_level;
module_param(debug_level, int, 0);
MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
@@ -1244,12 +1248,37 @@ static int cpsw_get_ts_info(struct net_device *ndev,
return 0;
}
+static int cpsw_get_settings(struct net_device *ndev,
+struct ethtool_cmd *ecmd)
+{
+ struct cpsw_priv *priv = netdev_priv(ndev);
+ int slave_no = cpsw_slave_index(priv);
+
+ if (priv->slaves[slave_no].phy)
+ return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
+ else
+ return -EOPNOTSUPP;
+}
+
+static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
+{
+ struct cpsw_priv *priv = netdev_priv(ndev);
+ int slave_no = cpsw_slave_index(priv);
+
+ if (priv->slaves[slave_no].phy)
+ return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
+ else
+ return -EOPNOTSUPP;
+}
+
static const struct ethtool_ops cpsw_ethtool_ops = {
.get_drvinfo= cpsw_get_drvinfo,
.get_msglevel = cpsw_get_msglevel,
.set_msglevel = cpsw_set_msglevel,
.get_link = ethtool_op_get_link,
.get_ts_info= cpsw_get_ts_info,
+ .get_settings = cpsw_get_settings,
+ .set_settings = cpsw_set_settings,
};
static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
--
1.7.9.5
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[PATCH v2 0/5] cpsw interrupt pacing and get/set phy setting implementation
This patch serires implements the following features in CPSW driver * get/set phy link settings * interrupt pacing * get phy id via ioctl cmd SIOCGMIIPHY Changes from initial version * Made active-slave common for cpts, ethtool and SIOCGMIIPHY ioctl * Cleaned CPSW DT binding documentation by seperating slave nodes under sub-section * implemented get phy id via ioctl cmd SIOCGMIIPHY Mugunthan V N (5): documentation: dt: bindings: cpsw: cleanup documentation drivers: net: ethernet: cpsw: change cpts_active_slave to active_slave driver: net: ethernet: cpsw: implement ethtool get/set phy setting driver: net: ethernet: cpsw: implement interrupt pacing via ethtool drivers: net: ethernet: cpsw: implement get phy_id via ioctl Documentation/devicetree/bindings/net/cpsw.txt | 16 ++- arch/arm/boot/dts/am33xx.dtsi |2 +- drivers/net/ethernet/ti/cpsw.c | 159 ++-- include/linux/platform_data/cpsw.h |2 +- 4 files changed, 165 insertions(+), 14 deletions(-) -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v2 2/5] drivers: net: ethernet: cpsw: change cpts_active_slave to active_slave
Change cpts_active_slave to active_slave so that the same DT property
can be used to ethtool and SIOCGMIIPHY.
CC: Richard Cochran
Signed-off-by: Mugunthan V N
---
Documentation/devicetree/bindings/net/cpsw.txt |7 ---
arch/arm/boot/dts/am33xx.dtsi |2 +-
drivers/net/ethernet/ti/cpsw.c | 10 +-
include/linux/platform_data/cpsw.h |2 +-
4 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt
b/Documentation/devicetree/bindings/net/cpsw.txt
index 8e49c42..4f2ca6b 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -15,7 +15,8 @@ Required properties:
- mac_control : Specifies Default MAC control register content
for the specific platform
- slaves : Specifies number for slaves
-- cpts_active_slave: Specifies the slave to use for time stamping
+- active_slave : Specifies the slave to use for time stamping,
+ ethtool and SIOCGMIIPHY
- cpts_clock_mult : Numerator to convert input clock ticks into
nanoseconds
- cpts_clock_shift : Denominator to convert input clock ticks into
nanoseconds
@@ -52,7 +53,7 @@ Examples:
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
- cpts_active_slave = <0>;
+ active_slave = <0>;
cpts_clock_mult = <0x8000>;
cpts_clock_shift = <29>;
cpsw_emac0: slave@0 {
@@ -78,7 +79,7 @@ Examples:
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
- cpts_active_slave = <0>;
+ active_slave = <0>;
cpts_clock_mult = <0x8000>;
cpts_clock_shift = <29>;
cpsw_emac0: slave@0 {
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 0957645..91fe4f1 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -349,7 +349,7 @@
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
- cpts_active_slave = <0>;
+ active_slave = <0>;
cpts_clock_mult = <0x8000>;
cpts_clock_shift = <29>;
reg = <0x4a10 0x800
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 01ffbc4..98aa17a 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -942,7 +942,7 @@ static void cpsw_ndo_change_rx_flags(struct net_device
*ndev, int flags)
static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
{
- struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave];
+ struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
u32 ts_en, seq_id;
if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
@@ -971,7 +971,7 @@ static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
if (priv->data.dual_emac)
slave = &priv->slaves[priv->emac_port];
else
- slave = &priv->slaves[priv->data.cpts_active_slave];
+ slave = &priv->slaves[priv->data.active_slave];
ctrl = slave_read(slave, CPSW2_CONTROL);
ctrl &= ~CTRL_ALL_TS_MASK;
@@ -1282,12 +1282,12 @@ static int cpsw_probe_dt(struct cpsw_platform_data
*data,
}
data->slaves = prop;
- if (of_property_read_u32(node, "cpts_active_slave", &prop)) {
- pr_err("Missing cpts_active_slave property in the DT.\n");
+ if (of_property_read_u32(node, "active_slave", &prop)) {
+ pr_err("Missing active_slave property in the DT.\n");
ret = -EINVAL;
goto error_ret;
}
- data->cpts_active_slave = prop;
+ data->active_slave = prop;
if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
pr_err("Missing cpts_clock_mult property in the DT.\n");
diff --git a/include/linux/platform_data/cpsw.h
b/include/linux/platform_data/cpsw.h
index 798fb80..bb3cd58 100644
--- a/include/linux/platform_data/cpsw.h
+++ b/include/linux/platform_data/cpsw.h
@@ -30,7 +30,7 @@ struct cpsw_platform_data {
u32 channels; /* number of cpdma channels (symmetric) */
u32 slaves; /* number of slave cpgmac ports */
struct cpsw_slave_data *slave_data;
- u32 cpts_active_slave; /* time stamping slave */
+ u32 acti
[PATCH v2 4/5] driver: net: ethernet: cpsw: implement interrupt pacing via ethtool
This patch implements support for interrupt pacing block of CPSW via ethtool
Inetrrupt pacing block is common of both the ethernet interface in
dual emac mode
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 104
1 file changed, 104 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 83ce890..d6cf698 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -126,6 +126,13 @@ do {
\
#define CPSW_FIFO_DUAL_MAC_MODE(1 << 15)
#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
+#define CPSW_INTPACEEN (0x3f << 16)
+#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
+#define CPSW_CMINTMAX_CNT 63
+#define CPSW_CMINTMIN_CNT 2
+#define CPSW_CMINTMAX_INTVL(1000 / CPSW_CMINTMIN_CNT)
+#define CPSW_CMINTMIN_INTVL((1000 / CPSW_CMINTMAX_CNT) + 1)
+
#define cpsw_enable_irq(priv) \
do {\
u32 i; \
@@ -164,6 +171,15 @@ struct cpsw_wr_regs {
u32 rx_en;
u32 tx_en;
u32 misc_en;
+ u32 mem_allign1[8];
+ u32 rx_thresh_stat;
+ u32 rx_stat;
+ u32 tx_stat;
+ u32 misc_stat;
+ u32 mem_allign2[8];
+ u32 rx_imax;
+ u32 tx_imax;
+
};
struct cpsw_ss_regs {
@@ -318,6 +334,8 @@ struct cpsw_priv {
struct cpsw_host_regs __iomem *host_port_regs;
u32 msg_enable;
u32 version;
+ u32 coal_intvl;
+ u32 bus_freq_mhz;
struct net_device_stats stats;
int rx_packet_max;
int host_port;
@@ -616,6 +634,77 @@ static void cpsw_adjust_link(struct net_device *ndev)
}
}
+static int cpsw_get_coalesce(struct net_device *ndev,
+ struct ethtool_coalesce *coal)
+{
+ struct cpsw_priv *priv = netdev_priv(ndev);
+
+ coal->rx_coalesce_usecs = priv->coal_intvl;
+ return 0;
+}
+
+static int cpsw_set_coalesce(struct net_device *ndev,
+ struct ethtool_coalesce *coal)
+{
+ struct cpsw_priv *priv = netdev_priv(ndev);
+ u32 int_ctrl;
+ u32 num_interrupts = 0;
+ u32 prescale = 0;
+ u32 addnl_dvdr = 1;
+ u32 coal_intvl = 0;
+
+ if (!coal->rx_coalesce_usecs)
+ return -EINVAL;
+
+ coal_intvl = coal->rx_coalesce_usecs;
+
+ int_ctrl = readl(&priv->wr_regs->int_control);
+ prescale = priv->bus_freq_mhz * 4;
+
+ if (coal_intvl < CPSW_CMINTMIN_INTVL)
+ coal_intvl = CPSW_CMINTMIN_INTVL;
+
+ if (coal_intvl > CPSW_CMINTMAX_INTVL) {
+ /* Interrupt pacer works with 4us Pulse, we can
+* throttle further by dilating the 4us pulse.
+*/
+ addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
+
+ if (addnl_dvdr > 1) {
+ prescale *= addnl_dvdr;
+ if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
+ coal_intvl = (CPSW_CMINTMAX_INTVL
+ * addnl_dvdr);
+ } else {
+ addnl_dvdr = 1;
+ coal_intvl = CPSW_CMINTMAX_INTVL;
+ }
+ }
+
+ num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
+ writel(num_interrupts, &priv->wr_regs->rx_imax);
+ writel(num_interrupts, &priv->wr_regs->tx_imax);
+
+ int_ctrl |= CPSW_INTPACEEN;
+ int_ctrl &= (~CPSW_INTPRESCALE_MASK);
+ int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
+ writel(int_ctrl, &priv->wr_regs->int_control);
+
+ cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
+ if (priv->data.dual_emac) {
+ int i;
+
+ for (i = 0; i < priv->data.slaves; i++) {
+ priv = netdev_priv(priv->slaves[i].ndev);
+ priv->coal_intvl = coal_intvl;
+ }
+ } else {
+ priv->coal_intvl = coal_intvl;
+ }
+
+ return 0;
+}
+
static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
{
static char *leader = "";
@@ -838,6 +927,14 @@ static int cpsw_ndo_open(struct net_device *ndev)
cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
}
+ /* Enable Interrupt pacing if configured */
+ if (priv->coal_intvl != 0) {
+ struct ethtool_coalesce coal;
+
+
[PATCH v2 5/5] drivers: net: ethernet: cpsw: implement get phy_id via ioctl
Implement get phy_id via ioctl SIOCGMIIPHY. In switch mode active phy_id
is returned and in dual EMAC mode slave's specific phy_id is returned.
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index d6cf698..8ff1d3d 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1157,14 +1157,26 @@ static int cpsw_hwtstamp_ioctl(struct net_device *dev,
struct ifreq *ifr)
static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
{
+ struct cpsw_priv *priv = netdev_priv(dev);
+ struct mii_ioctl_data *data = if_mii(req);
+ int slave_no = cpsw_slave_index(priv);
+
if (!netif_running(dev))
return -EINVAL;
+ switch (cmd) {
#ifdef CONFIG_TI_CPTS
- if (cmd == SIOCSHWTSTAMP)
+ case SIOCSHWTSTAMP:
return cpsw_hwtstamp_ioctl(dev, req);
#endif
- return -ENOTSUPP;
+ case SIOCGMIIPHY:
+ data->phy_id = priv->slaves[slave_no].phy->addr;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ return 0;
}
static void cpsw_ndo_tx_timeout(struct net_device *ndev)
--
1.7.9.5
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[PATCH v2 1/5] documentation: dt: bindings: cpsw: cleanup documentation
Move all the slave note properties to separate section to reduce the confusion between slave note properties and cpsw node properties Signed-off-by: Mugunthan V N --- Documentation/devicetree/bindings/net/cpsw.txt |9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt index ecfdf75..8e49c42 100644 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ b/Documentation/devicetree/bindings/net/cpsw.txt @@ -18,13 +18,18 @@ Required properties: - cpts_active_slave: Specifies the slave to use for time stamping - cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds - cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds -- phy_id : Specifies slave phy id -- mac-address : Specifies slave MAC address Optional properties: - ti,hwmods: Must be "cpgmac0" - no_bd_ram: Must be 0 or 1 - dual_emac: Specifies Switch to act as Dual EMAC + +Slave Properties: +Required properties: +- phy_id : Specifies slave phy id +- mac-address : Specifies slave MAC address + +Optional properties: - dual_emac_res_vlan : Specifies VID to be used to segregate the ports Note: "ti,hwmods" field is used to fetch the base address and irq -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 1/3] driver: net: ethernet: cpsw: implement ethtool get/set phy setting
On 3/8/2013 8:34 PM, Peter Korsgaard wrote: "Ben" == Ben Hutchings writes: Hi, Ben> The 'active slave' property would also be needed for the SIOCGMIIPHY Ben> ioctl and not just ethtool. But it's really quite arbitrary. Perhaps Ben> each of them should have their own net device (as with DSA). Indeed, I think that would simplify all of this quite a bit. I will update this in the next patch series Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 1/3] driver: net: ethernet: cpsw: implement ethtool get/set phy setting
On 3/8/2013 8:23 PM, Ben Hutchings wrote: On Fri, 2013-03-08 at 12:53 +0530, Mugunthan V N wrote: On 3/8/2013 1:29 AM, Ben Hutchings wrote: On Thu, 2013-03-07 at 14:24 +0100, Peter Korsgaard wrote: "M" == Mugunthan V N writes: M> This patch implements get/set of the phy settings via ethtool apis M> Signed-off-by: Mugunthan V N M> --- M> Documentation/devicetree/bindings/net/cpsw.txt |3 +++ M> drivers/net/ethernet/ti/cpsw.c | 32 M> include/linux/platform_data/cpsw.h |1 + M> 3 files changed, 36 insertions(+) M> diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt M> index ecfdf75..8d61300 100644 M> --- a/Documentation/devicetree/bindings/net/cpsw.txt M> +++ b/Documentation/devicetree/bindings/net/cpsw.txt M> @@ -20,6 +20,7 @@ Required properties: M> - cpts_clock_shift: Denominator to convert input clock ticks into nanoseconds M> - phy_id : Specifies slave phy id M> - mac-address : Specifies slave MAC address M> +- ethtool-active-slave: Specifies the slave to use for ethtool command That again sounds like something Linux specific rather than a hardware property. Yes, indeed. Isn't it redundant with the phy_id? Ben. phy_id is part of slave data and will be present for both the slaves. so phy_id cannot be used for get/set phy setting until phy framework allows to change settings without going through eth interface. Now I've looked at the examples in this file, I think I see what you're getting at. What confused me is that you're adding to a single list of properties without a proper distinction of which devices they are applied to. It really ought to be properly divided between switch and 'slave' properties. Will fix this in next patch series. The 'active slave' property would also be needed for the SIOCGMIIPHY ioctl and not just ethtool. But it's really quite arbitrary. Perhaps each of them should have their own net device (as with DSA). But if we have net device for each of the slaves then it is dual EMAC which will kill hardware switching functionality. To achieve switching bridge has to be done and there will be a performance drop as well. As Peter Korsgaard mentioned we need to have infrastructure to handle CPSW kind of hardware. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 1/3] driver: net: ethernet: cpsw: implement ethtool get/set phy setting
On 3/8/2013 1:29 AM, Ben Hutchings wrote: On Thu, 2013-03-07 at 14:24 +0100, Peter Korsgaard wrote: "M" == Mugunthan V N writes: M> This patch implements get/set of the phy settings via ethtool apis M> Signed-off-by: Mugunthan V N M> --- M> Documentation/devicetree/bindings/net/cpsw.txt |3 +++ M> drivers/net/ethernet/ti/cpsw.c | 32 M> include/linux/platform_data/cpsw.h |1 + M> 3 files changed, 36 insertions(+) M> diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt M> index ecfdf75..8d61300 100644 M> --- a/Documentation/devicetree/bindings/net/cpsw.txt M> +++ b/Documentation/devicetree/bindings/net/cpsw.txt M> @@ -20,6 +20,7 @@ Required properties: M> - cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds M> - phy_id : Specifies slave phy id M> - mac-address : Specifies slave MAC address M> +- ethtool-active-slave : Specifies the slave to use for ethtool command That again sounds like something Linux specific rather than a hardware property. Yes, indeed. Isn't it redundant with the phy_id? Ben. phy_id is part of slave data and will be present for both the slaves. so phy_id cannot be used for get/set phy setting until phy framework allows to change settings without going through eth interface. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 2/3] arm: dts: am33xx: add default ethtool slave to cpsw node
On 3/7/2013 9:43 PM, Tony Lindgren wrote: * Mugunthan V N [130307 04:35]: Can you please add a description and send this separately so Benoit can queue it. Will send this patch separately after this patch series has been reviewed and accepted by netdev maintainer. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 1/3] driver: net: ethernet: cpsw: implement ethtool get/set phy setting
On 3/7/2013 6:54 PM, Peter Korsgaard wrote: "M" == Mugunthan V N writes: M> This patch implements get/set of the phy settings via ethtool apis M> Signed-off-by: Mugunthan V N M> --- M> Documentation/devicetree/bindings/net/cpsw.txt |3 +++ M> drivers/net/ethernet/ti/cpsw.c | 32 M> include/linux/platform_data/cpsw.h |1 + M> 3 files changed, 36 insertions(+) M> diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt M> index ecfdf75..8d61300 100644 M> --- a/Documentation/devicetree/bindings/net/cpsw.txt M> +++ b/Documentation/devicetree/bindings/net/cpsw.txt M> @@ -20,6 +20,7 @@ Required properties: M> - cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds M> - phy_id : Specifies slave phy id M> - mac-address : Specifies slave MAC address M> +- ethtool-active-slave : Specifies the slave to use for ethtool command That again sounds like something Linux specific rather than a hardware property. It would be good if all these special things (dual emac mode, vlan handling, switching) could be handled using the existing kernel (bridging/vlan) infrastructure, and the driver always just exposing 2 network interfaces instead of these configuration properties. Switch and Dual Emac modes of operation of CPSW are two different features of the hardware and packet routing between the slaves in the hardware are different in both the modes. If by default it is brought up as Dual EMAC then hardware switching is blocked and use-cases like IP phone etc cannot be achieved. Since CPSW as a hardware Switch, it cannot not be handled in existing kernel feature. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH 1/3] driver: net: ethernet: cpsw: implement ethtool get/set phy setting
This patch implements get/set of the phy settings via ethtool apis
Signed-off-by: Mugunthan V N
---
Documentation/devicetree/bindings/net/cpsw.txt |3 +++
drivers/net/ethernet/ti/cpsw.c | 32
include/linux/platform_data/cpsw.h |1 +
3 files changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt
b/Documentation/devicetree/bindings/net/cpsw.txt
index ecfdf75..8d61300 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -20,6 +20,7 @@ Required properties:
- cpts_clock_shift : Denominator to convert input clock ticks into
nanoseconds
- phy_id : Specifies slave phy id
- mac-address : Specifies slave MAC address
+- ethtool-active-slave : Specifies the slave to use for ethtool command
Optional properties:
- ti,hwmods: Must be "cpgmac0"
@@ -50,6 +51,7 @@ Examples:
cpts_active_slave = <0>;
cpts_clock_mult = <0x8000>;
cpts_clock_shift = <29>;
+ ethtool-active-slave = <0>;
cpsw_emac0: slave@0 {
phy_id = <&davinci_mdio>, <0>;
/* Filled in by U-Boot */
@@ -76,6 +78,7 @@ Examples:
cpts_active_slave = <0>;
cpts_clock_mult = <0x8000>;
cpts_clock_shift = <29>;
+ ethtool-active-slave = <0>;
cpsw_emac0: slave@0 {
phy_id = <&davinci_mdio>, <0>;
/* Filled in by U-Boot */
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 01ffbc4..fa91eec 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1244,12 +1244,41 @@ static int cpsw_get_ts_info(struct net_device *ndev,
return 0;
}
+#define cpsw_slave_phy_index(priv) \
+ ((priv->data.dual_emac) ? priv->emac_port : \
+ priv->data.ethtool_active_slave)
+
+static int cpsw_get_settings(struct net_device *ndev,
+struct ethtool_cmd *ecmd)
+{
+ struct cpsw_priv *priv = netdev_priv(ndev);
+ int slave_no = cpsw_slave_phy_index(priv);
+
+ if (priv->slaves[slave_no].phy)
+ return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
+ else
+ return -EOPNOTSUPP;
+}
+
+static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
+{
+ struct cpsw_priv *priv = netdev_priv(ndev);
+ int slave_no = cpsw_slave_phy_index(priv);
+
+ if (priv->slaves[slave_no].phy)
+ return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
+ else
+ return -EOPNOTSUPP;
+}
+
static const struct ethtool_ops cpsw_ethtool_ops = {
.get_drvinfo= cpsw_get_drvinfo,
.get_msglevel = cpsw_get_msglevel,
.set_msglevel = cpsw_set_msglevel,
.get_link = ethtool_op_get_link,
.get_ts_info= cpsw_get_ts_info,
+ .get_settings = cpsw_get_settings,
+ .set_settings = cpsw_set_settings,
};
static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
@@ -1346,6 +1375,9 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
if (!of_property_read_u32(node, "dual_emac", &prop))
data->dual_emac = prop;
+ if (!of_property_read_u32(node, "ethtool-active-slave", &prop))
+ data->ethtool_active_slave = prop;
+
/*
* Populate all the child nodes here...
*/
diff --git a/include/linux/platform_data/cpsw.h
b/include/linux/platform_data/cpsw.h
index 798fb80..e87e5cb 100644
--- a/include/linux/platform_data/cpsw.h
+++ b/include/linux/platform_data/cpsw.h
@@ -39,6 +39,7 @@ struct cpsw_platform_data {
u32 mac_control;/* Mac control register */
u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/
booldual_emac; /* Enable Dual EMAC mode */
+ u32 ethtool_active_slave; /* ethtool slave */
};
#endif /* __CPSW_H__ */
--
1.7.9.5
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[PATCH 0/3] cpsw interrupt pacing and get/set phy setting implementation
This patch serires implements the following features in CPSW driver * get/set phy link settings * interrupt pacing Mugunthan V N (3): driver: net: ethernet: cpsw: implement ethtool get/set phy setting arm: dts: am33xx: add default ethtool slave to cpsw node driver: net: ethernet: cpsw: implement interrupt pacing via ethtool Documentation/devicetree/bindings/net/cpsw.txt |3 + arch/arm/boot/dts/am33xx.dtsi |1 + drivers/net/ethernet/ti/cpsw.c | 127 include/linux/platform_data/cpsw.h |1 + 4 files changed, 132 insertions(+) -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH 3/3] driver: net: ethernet: cpsw: implement interrupt pacing via ethtool
This patch implements support for interrupt pacing block of CPSW via ethtool
Signed-off-by: Mugunthan V N
---
drivers/net/ethernet/ti/cpsw.c | 95
1 file changed, 95 insertions(+)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index fa91eec..da7276d 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -126,6 +126,13 @@ do {
\
#define CPSW_FIFO_DUAL_MAC_MODE(1 << 15)
#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
+#define CPSW_INTPACEEN (0x3f << 16)
+#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
+#define CPSW_CMINTMAX_CNT 63
+#define CPSW_CMINTMIN_CNT 2
+#define CPSW_CMINTMAX_INTVL(1000 / CPSW_CMINTMIN_CNT)
+#define CPSW_CMINTMIN_INTVL((1000 / CPSW_CMINTMAX_CNT) + 1)
+
#define cpsw_enable_irq(priv) \
do {\
u32 i; \
@@ -160,6 +167,15 @@ struct cpsw_wr_regs {
u32 rx_en;
u32 tx_en;
u32 misc_en;
+ u32 mem_allign1[8];
+ u32 rx_thresh_stat;
+ u32 rx_stat;
+ u32 tx_stat;
+ u32 misc_stat;
+ u32 mem_allign2[8];
+ u32 rx_imax;
+ u32 tx_imax;
+
};
struct cpsw_ss_regs {
@@ -314,6 +330,8 @@ struct cpsw_priv {
struct cpsw_host_regs __iomem *host_port_regs;
u32 msg_enable;
u32 version;
+ u32 coal_intvl;
+ u32 bus_freq_mhz;
struct net_device_stats stats;
int rx_packet_max;
int host_port;
@@ -612,6 +630,68 @@ static void cpsw_adjust_link(struct net_device *ndev)
}
}
+static int cpsw_get_coalesce(struct net_device *ndev,
+ struct ethtool_coalesce *coal)
+{
+ struct cpsw_priv *priv = netdev_priv(ndev);
+
+ coal->rx_coalesce_usecs = priv->coal_intvl;
+ return 0;
+}
+
+static int cpsw_set_coalesce(struct net_device *ndev,
+ struct ethtool_coalesce *coal)
+{
+ struct cpsw_priv *priv = netdev_priv(ndev);
+ u32 int_ctrl;
+ u32 num_interrupts = 0;
+ u32 prescale = 0;
+ u32 addnl_dvdr = 1;
+ u32 coal_intvl = 0;
+
+ if (!coal->rx_coalesce_usecs)
+ return -EINVAL;
+
+ coal_intvl = coal->rx_coalesce_usecs;
+
+ int_ctrl = readl(&priv->wr_regs->int_control);
+ prescale = priv->bus_freq_mhz * 4;
+
+ if (coal_intvl < CPSW_CMINTMIN_INTVL)
+ coal_intvl = CPSW_CMINTMIN_INTVL;
+
+ if (coal_intvl > CPSW_CMINTMAX_INTVL) {
+ /* Interrupt pacer works with 4us Pulse, we can
+* throttle further by dilating the 4us pulse.
+*/
+ addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
+
+ if (addnl_dvdr > 1) {
+ prescale *= addnl_dvdr;
+ if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
+ coal_intvl = (CPSW_CMINTMAX_INTVL
+ * addnl_dvdr);
+ } else {
+ addnl_dvdr = 1;
+ coal_intvl = CPSW_CMINTMAX_INTVL;
+ }
+ }
+
+ num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
+ writel(num_interrupts, &priv->wr_regs->rx_imax);
+ writel(num_interrupts, &priv->wr_regs->tx_imax);
+
+ int_ctrl |= CPSW_INTPACEEN;
+ int_ctrl &= (~CPSW_INTPRESCALE_MASK);
+ int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
+ writel(int_ctrl, &priv->wr_regs->int_control);
+
+ cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
+ priv->coal_intvl = coal_intvl;
+
+ return 0;
+}
+
static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
{
static char *leader = "";
@@ -834,6 +914,14 @@ static int cpsw_ndo_open(struct net_device *ndev)
cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
}
+ /* Enable Interrupt pacing if configured */
+ if (priv->coal_intvl != 0) {
+ struct ethtool_coalesce coal;
+
+ coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
+ cpsw_set_coalesce(ndev, &coal);
+ }
+
cpdma_ctlr_start(priv->dma);
cpsw_intr_enable(priv);
napi_enable(&priv->napi);
@@ -1279,6 +1367,8 @@ static const struct ethtool_ops cpsw_ethtool_ops = {
.get_ts_info= cpsw_get_ts_info,
.get_setting
[PATCH 2/3] arm: dts: am33xx: add default ethtool slave to cpsw node
Signed-off-by: Mugunthan V N --- arch/arm/boot/dts/am33xx.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 0957645..f8c83a1 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -352,6 +352,7 @@ cpts_active_slave = <0>; cpts_clock_mult = <0x8000>; cpts_clock_shift = <29>; + ethtool-active-slave = <0>; reg = <0x4a10 0x800 0x4a101200 0x100>; #address-cells = <1>; -- 1.7.9.5 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 3/3] driver: net: ethernet: cpsw: dual emac interface implementation
On 2/18/2013 7:06 PM, Peter Korsgaard wrote: "M" == Mugunthan V N writes: M> The CPSW switch can act as Dual EMAC by segregating the switch ports M> using VLAN and port VLAN as per the TRM description in M> 14.3.2.10.2 Dual Mac Mode M> Following CPSW components will be common for both the interfaces. M> * Interrupt source is common for both eth interfaces M> * Interrupt pacing is common for both interfaces M> * Hardware statistics is common for all the ports M> * CPDMA is common for both eth interface M> * CPTS is common for both the interface and it should not be enabled on M> both the interface as timestamping information doesn't contain port M> information. M> Constrains M> * Reserved VID of One port should not be used in other interface which will M> enable switching functionality M> * Same VID must not be used in both the interface which will enable switching M> functionality M> Signed-off-by: Mugunthan V N M> --- M> Documentation/devicetree/bindings/net/cpsw.txt |2 + M> drivers/net/ethernet/ti/cpsw.c | 335 M> include/linux/platform_data/cpsw.h |3 + M> 3 files changed, 288 insertions(+), 52 deletions(-) M> diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt M> index 6ddd028..ecfdf75 100644 M> --- a/Documentation/devicetree/bindings/net/cpsw.txt M> +++ b/Documentation/devicetree/bindings/net/cpsw.txt M> @@ -24,6 +24,8 @@ Required properties: M> Optional properties: M> - ti,hwmods: Must be "cpgmac0" M> - no_bd_ram: Must be 0 or 1 M> +- dual_emac: Specifies Switch to act as Dual EMAC M> +- dual_emac_res_vlan : Specifies VID to be used to segregate the ports You forgot to CC devicetree-discuss. Properties normally use dashes (-) instead of underscores (_). These properties are more about configuration and not hardware. It is not clear to me from the description that dual_emac is a boolean (0/1). Shouldn't dual_emacs_res_vlan be a property of the slave? It would also be good to update the example below with this. Since the series is already applied in net-next tree, i will submit a patch with incorporating the above comments. Will add devicetree-discuss in my future patches. Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH 1/1] ARM: dts: AM33XX: Add CPSW phy_id device tree data to am335x-evmsk
Add phy_id device tree data to am335x-evmsk device to bring up CPSW
ethernet present on am335x starter kit.
Signed-off-by: Mugunthan V N
---
arch/arm/boot/dts/am335x-evmsk.dts |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index f5a6162..f297b85 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -248,3 +248,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
--
1.7.9.5
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Re: [PATCHv2] am33xx: cpsw: default to ethernet hwaddr from efuse if not defined in dt
On 1/18/2013 3:48 AM, Peter Korsgaard wrote: When booting with CONFIG_ARM_APPENDED_DTB (either because of using an old U-Boot, not wanting the hassle of 2 files or when using Falcon fast boot mode in U-Boot), nothing updates the ethernet hwaddr specified for the CPSW slaves, causing the driver to use a random hwaddr, which is some times troublesome. The am33xx has unique ethernet hwaddrs programmed in the efuse, so it makes more sense to default to these rather than random ones. Add a fixup step which adds mac-address dt properties using the efuse addresses if the DTB didn't contain valid ones. Signed-off-by: Peter Korsgaard This implementation looks fine. Acked-by: Mugunthan V N Regards Mugunthan V N ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH 1/1] ARM: dts: am335x-evmsk: Add cpsw phy_id
Add phy id for CPSW
Signed-off-by: Mugunthan V N
---
The patch is verified with CPSW patches present in the following git repo
git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
arch/arm/boot/dts/am335x-evmsk.dts |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index 6f53879..c629086 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -164,3 +164,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
--
1.7.0.4
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[PATCH V5 3/7] cpsw: simplify the setup of the register pointers
From: Richard Cochran
Instead of having a host of different register offsets in the device tree,
this patch simplifies the CPSW code by letting the driver set the proper
register offsets automatically, based on the CPSW version.
Signed-off-by: Richard Cochran
Signed-off-by: Mugunthan V N
---
Documentation/devicetree/bindings/net/cpsw.txt | 42 +
drivers/net/ethernet/ti/cpsw.c | 242 ++--
include/linux/platform_data/cpsw.h | 21 +--
3 files changed, 108 insertions(+), 197 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt
b/Documentation/devicetree/bindings/net/cpsw.txt
index 2214607..6ddd028 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -9,15 +9,7 @@ Required properties:
number
- interrupt-parent : The parent interrupt controller
- cpdma_channels : Specifies number of channels in CPDMA
-- host_port_no : Specifies host port shift
-- cpdma_reg_ofs: Specifies CPDMA submodule register offset
-- cpdma_sram_ofs : Specifies CPDMA SRAM offset
-- ale_reg_ofs : Specifies ALE submodule register offset
- ale_entries : Specifies No of entries ALE can hold
-- host_port_reg_ofs: Specifies host port register offset
-- hw_stats_reg_ofs : Specifies hardware statistics register offset
-- cpts_reg_ofs : Specifies the offset of the CPTS registers
-- bd_ram_ofs : Specifies internal desciptor RAM offset
- bd_ram_size : Specifies internal descriptor RAM size
- rx_descs : Specifies number of Rx descriptors
- mac_control : Specifies Default MAC control register content
@@ -26,8 +18,6 @@ Required properties:
- cpts_active_slave: Specifies the slave to use for time stamping
- cpts_clock_mult : Numerator to convert input clock ticks into
nanoseconds
- cpts_clock_shift : Denominator to convert input clock ticks into
nanoseconds
-- slave_reg_ofs: Specifies slave register offset
-- sliver_reg_ofs : Specifies slave sliver register offset
- phy_id : Specifies slave phy id
- mac-address : Specifies slave MAC address
@@ -49,15 +39,7 @@ Examples:
interrupts = <55 0x4>;
interrupt-parent = <&intc>;
cpdma_channels = <8>;
- host_port_no = <0>;
- cpdma_reg_ofs = <0x800>;
- cpdma_sram_ofs = <0xa00>;
- ale_reg_ofs = <0xd00>;
ale_entries = <1024>;
- host_port_reg_ofs = <0x108>;
- hw_stats_reg_ofs = <0x900>;
- cpts_reg_ofs = <0xc00>;
- bd_ram_ofs = <0x2000>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
rx_descs = <64>;
@@ -67,16 +49,12 @@ Examples:
cpts_clock_mult = <0x8000>;
cpts_clock_shift = <29>;
cpsw_emac0: slave@0 {
- slave_reg_ofs = <0x200>;
- sliver_reg_ofs = <0xd80>;
- phy_id = "davinci_mdio.16:00";
+ phy_id = <&davinci_mdio>, <0>;
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@1 {
- slave_reg_ofs = <0x300>;
- sliver_reg_ofs = <0xdc0>;
- phy_id = "davinci_mdio.16:01";
+ phy_id = <&davinci_mdio>, <1>;
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
@@ -87,15 +65,7 @@ Examples:
compatible = "ti,cpsw";
ti,hwmods = "cpgmac0";
cpdma_channels = <8>;
- host_port_no = <0>;
- cpdma_reg_ofs = <0x800>;
- cpdma_sram_ofs = <0xa00>;
- ale_reg_ofs = <0xd00>;
ale_entries = <1024>;
- host_port_reg_ofs = <0x108>;
- hw_stats_reg_ofs = <0x900>;
- cpts_reg_ofs = <0xc00>;
- bd_ram_ofs = <0x2000>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
rx_descs = <64>;
@@ -105,16 +75,12 @@ Examples:
cpts_clock_mult = <0x8000>;
cpts_clock_shift = <29>;
cpsw_emac0: slave@0 {
- slave_reg_ofs = <0x200>;
- sliver_reg_ofs = <0xd80>;
-
[PATCH V5 2/7] net: cpsw: Add parent<->child relation support between cpsw and mdio
From: Vaibhav Hiremath
CPGMAC SubSystem consist of various sub-modules, like, mdio, cpdma,
cpsw, etc... These sub-modules are also used in some of Davinci family
of devices. Now based on requirement, use-case and available technology
nodes the integration of these sub-modules varies across devices.
So coming back to Linux net driver, currently separate and independent
platform devices & drivers for CPSW and MDIO is implemented. In case of
Davinci they both has separate control, from resources perspective,
like clock.
In case of AM33XX, the resources are shared and only one register
bit-field is provided to control module/clock enable/disable, makes it
difficult to handle common resource.
So the solution here implemented in this patch is,
Create parent<->child relationship between both the drivers, making
CPSW as a parent and MDIO as its child and enumerate all the child nodes
under CPSW module.
Both the drivers will function exactly the way it was operating before,
including runtime-pm functionality. No change is required in MDIO driver
(for that matter to any child driver).
As this is only supported during DT boot, the parent<->child relationship
is created and populated in DT execution flow. The only required change
is inside DTS file, making MDIO as a child to CPSW node.
Signed-off-by: Vaibhav Hiremath
Signed-off-by: Mugunthan V N
Acked-by: Peter Korsgaard
Acked-by: Richard Cochran
---
drivers/net/ethernet/ti/cpsw.c | 16 ++--
1 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 7654a62..7007aba 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1144,7 +1144,7 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
}
data->mac_control = prop;
- for_each_child_of_node(node, slave_node) {
+ for_each_node_by_name(slave_node, "slave") {
struct cpsw_slave_data *slave_data = data->slave_data + i;
const char *phy_id = NULL;
const void *mac_addr = NULL;
@@ -1179,6 +1179,14 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
i++;
}
+ /*
+* Populate all the child nodes here...
+*/
+ ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
+ /* We do not want to force this, as in some cases may not have child */
+ if (ret)
+ pr_warn("Doesn't have any child node\n");
+
return 0;
error_ret:
@@ -1212,6 +1220,11 @@ static int __devinit cpsw_probe(struct platform_device
*pdev)
priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
priv->rx_packet_max = max(rx_packet_max, 128);
+ /*
+* This may be required here for child devices.
+*/
+ pm_runtime_enable(&pdev->dev);
+
if (cpsw_probe_dt(&priv->data, pdev)) {
pr_err("cpsw: platform data missing\n");
ret = -ENODEV;
@@ -1238,7 +1251,6 @@ static int __devinit cpsw_probe(struct platform_device
*pdev)
for (i = 0; i < data->slaves; i++)
priv->slaves[i].slave_num = i;
- pm_runtime_enable(&pdev->dev);
priv->clk = clk_get(&pdev->dev, "fck");
if (IS_ERR(priv->clk)) {
dev_err(&pdev->dev, "fck is not found\n");
--
1.7.0.4
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[PATCH V5 5/7] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio module
This patch adds hwmod entry for davinci MDIO module,
creating parent<->child relationship between CPSW and MDIO module.
This Parent-child relation is required in order to use common resources
like, clock, but still maintaining the logical separation between them.
CPGMAC SubSystem consist of various sub-modules, like, mdio, cpdma,
cpsw, etc... These sub-modules are also used in some of Davinci
family of devices, so separate and independent platform devices &
drivers for CPSW and MDIO is implemented.
In case of AM33XX, the resources are shared and common register
bit-field is provided to control module/clock enable/disable,
makes it difficult to handle common resources from both drivers.
So the solution is, create parent<->child relationship between
CPGMAC & MDIO modules.
Signed-off-by: Mugunthan V N
Signed-off-by: Vaibhav Hiremath
Cc: Paul Walmsley
Acked-by: Peter Korsgaard
Acked-by: Richard Cochran
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 31
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 59d5c1c..3125835 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -674,6 +674,7 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
.name = "cpgmac0",
.class = &am33xx_cpgmac0_hwmod_class,
.clkdm_name = "cpsw_125mhz_clkdm",
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.mpu_irqs = am33xx_cpgmac0_irqs,
.main_clk = "cpsw_125mhz_gclk",
.prcm = {
@@ -685,6 +686,20 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
};
/*
+ * mdio class
+ */
+static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
+ .name = "davinci_mdio",
+};
+
+static struct omap_hwmod am33xx_mdio_hwmod = {
+ .name = "davinci_mdio",
+ .class = &am33xx_mdio_hwmod_class,
+ .clkdm_name = "cpsw_125mhz_clkdm",
+ .main_clk = "cpsw_125mhz_gclk",
+};
+
+/*
* dcan class
*/
static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
@@ -2501,6 +2516,21 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
.user = OCP_USER_MPU,
};
+struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
+ {
+ .pa_start = 0x4A101000,
+ .pa_end = 0x4A101000 + SZ_256 - 1,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
+ .master = &am33xx_cpgmac0_hwmod,
+ .slave = &am33xx_mdio_hwmod,
+ .addr = am33xx_mdio_addr_space,
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
{
.pa_start = 0x4808,
@@ -3371,6 +3401,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[]
__initdata = {
&am33xx_l3_main__tptc2,
&am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0,
+ &am33xx_cpgmac0__mdio,
NULL,
};
--
1.7.0.4
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[PATCH V5 7/7] arm/dts: am33xx: Add CPSW and MDIO module nodes for AM33XX
Add CPSW and MDIO related device tree data for AM33XX.
Also enable them into board/evm dts files by providing
respective phy-id.
Signed-off-by: Mugunthan V N
Signed-off-by: Vaibhav Hiremath
Cc: Benoit Cousson
Acked-by: Peter Korsgaard
Acked-by: Richard Cochran
---
arch/arm/boot/dts/am335x-bone.dts |8 ++
arch/arm/boot/dts/am335x-evm.dts |8 ++
arch/arm/boot/dts/am33xx.dtsi | 48 +
3 files changed, 64 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index c634f87..4fcd218 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -78,3 +78,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 185d632..366d929 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -118,3 +118,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff..a4615b4 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -210,5 +210,53 @@
interrupt-parent = <&intc>;
interrupts = <91>;
};
+
+ mac: ethernet@4a10 {
+ compatible = "ti,cpsw";
+ ti,hwmods = "cpgmac0";
+ cpdma_channels = <8>;
+ ale_entries = <1024>;
+ bd_ram_size = <0x2000>;
+ no_bd_ram = <0>;
+ rx_descs = <64>;
+ mac_control = <0x20>;
+ slaves = <2>;
+ cpts_active_slave = <0>;
+ cpts_clock_mult = <0x8000>;
+ cpts_clock_shift = <29>;
+ reg = <0x4a10 0x800
+ 0x4a101200 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ /*
+* c0_rx_thresh_pend
+* c0_rx_pend
+* c0_tx_pend
+* c0_misc_pend
+*/
+ interrupts = <40 41 42 43>;
+ ranges;
+
+ davinci_mdio: mdio@4a101000 {
+ compatible = "ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "davinci_mdio";
+ bus_freq = <100>;
+ reg = <0x4a101000 0x100>;
+ };
+
+ cpsw_emac0: slave@4a100200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave@4a100300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ };
};
};
--
1.7.0.4
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[PATCH V5 1/7] net: davinci_mdio: Fix typo mistake in calling runtime-pm api
From: Vaibhav Hiremath By mistake (most likely a copy-paste), instead of pm_runtime_get_sync() api, driver is calling pm_runtime_put_sync() api in resume callback function. The bug was introduced by commit id (ae2c07aaf74: davinci_mdio: runtime PM support). Now, the reason why it didn't impact functionality is, the patch has been tested on AM335x-EVM and BeagleBone platform while submitting; and in case of AM335x the MDIO driver doesn't control the module enable/disable part, which is handled by CPSW driver. Signed-off-by: Vaibhav Hiremath Signed-off-by: Mugunthan V N Acked-by: Peter Korsgaard Acked-by: Richard Cochran --- drivers/net/ethernet/ti/davinci_mdio.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c index 51a96db..ae74280 100644 --- a/drivers/net/ethernet/ti/davinci_mdio.c +++ b/drivers/net/ethernet/ti/davinci_mdio.c @@ -465,7 +465,7 @@ static int davinci_mdio_resume(struct device *dev) u32 ctrl; spin_lock(&data->lock); - pm_runtime_put_sync(data->dev); + pm_runtime_get_sync(data->dev); /* restart the scan state machine */ ctrl = __raw_readl(&data->regs->control); -- 1.7.0.4 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH V5 0/7] ARM: AM33XX: net: Add DT support to CPSW and MDIO driver
This patch-series adds support for, [1/7]: Typo mistake in CPSW driver while invoking runtime_pm api's [2/7]: Adds parent<->child relation between CPSW & MDIO module inside cpsw driver, as in case of AM33XX, the resources are shared and common register bit-field is provided to control module/clock enable/disable, makes it difficult to handle common resource. So the solution here is, to create parent<->child relation between them. [3/7]: cpsw: simplify the setup of the register pointers [4/7]: cpsw: Kernel warn fix during suspend [5/7]: Add hwmod entry for MDIO module, required for MDIO driver. [6/7]: Enable CPSW support to omap2plus_defconfig [7/7]: Add DT device nodes for both CPSW and MDIO modules in am33xx.dtsi, am335x-evm.dts and am335x-bone.dts file This patch series has been created on top of net-next/master and tested on BeagleBone platform for NFS boot and basic ping test cases. Changes from V3: * Removed unnecessary flags in Davinci MDIO Hwmod entry. Changes from V4: * Changed CPSW phy ID in DT to make it generic. * Applied cosmetic changed in AM33XX dts file from Benoit Cousson Mugunthan V N (4): net: cpsw: halt network stack before halting the device during suspend ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio module ARM: OMAP2+: omap2plus_defconfig: Enable CPSW support arm/dts: am33xx: Add CPSW and MDIO module nodes for AM33XX Richard Cochran (1): cpsw: simplify the setup of the register pointers Vaibhav Hiremath (2): net: davinci_mdio: Fix typo mistake in calling runtime-pm api net: cpsw: Add parent<->child relation support between cpsw and mdio Documentation/devicetree/bindings/net/cpsw.txt | 42 + arch/arm/boot/dts/am335x-bone.dts |8 + arch/arm/boot/dts/am335x-evm.dts |8 + arch/arm/boot/dts/am33xx.dtsi | 48 + arch/arm/configs/omap2plus_defconfig |3 + arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 31 +++ drivers/net/ethernet/ti/cpsw.c | 248 +++- drivers/net/ethernet/ti/davinci_mdio.c |2 +- include/linux/platform_data/cpsw.h | 21 +-- 9 files changed, 216 insertions(+), 195 deletions(-) ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH V5 6/7] ARM: OMAP2+: omap2plus_defconfig: Enable CPSW support
Enable CPSW support in defconfig which is present in AM33xx SoC Signed-off-by: Mugunthan V N Acked-by: Richard Cochran --- arch/arm/configs/omap2plus_defconfig |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index a4b330e..41b595e 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -242,3 +242,6 @@ CONFIG_CRC_ITU_T=y CONFIG_CRC7=y CONFIG_LIBCRC32C=y CONFIG_SOC_OMAP5=y +CONFIG_TI_DAVINCI_MDIO=y +CONFIG_TI_DAVINCI_CPDMA=y +CONFIG_TI_CPSW=y -- 1.7.0.4 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH V5 4/7] net: cpsw: halt network stack before halting the device during suspend
Move network stack halt APIs before halting the hardware to ensure no packets are queued to hardware during closing the device during suspend sequence. Signed-off-by: Mugunthan V N Acked-by: Richard Cochran --- drivers/net/ethernet/ti/cpsw.c |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 0da9c75..02c2477 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -698,12 +698,12 @@ static int cpsw_ndo_stop(struct net_device *ndev) struct cpsw_priv *priv = netdev_priv(ndev); cpsw_info(priv, ifdown, "shutting down cpsw device\n"); - cpsw_intr_disable(priv); - cpdma_ctlr_int_ctrl(priv->dma, false); - cpdma_ctlr_stop(priv->dma); netif_stop_queue(priv->ndev); napi_disable(&priv->napi); netif_carrier_off(priv->ndev); + cpsw_intr_disable(priv); + cpdma_ctlr_int_ctrl(priv->dma, false); + cpdma_ctlr_stop(priv->dma); cpsw_ale_stop(priv->ale); for_each_slave(priv, cpsw_slave_stop, priv); pm_runtime_put_sync(&priv->pdev->dev); -- 1.7.0.4 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
