Re: [Discuss-gnuradio] Re: interfacing a DSP array card to USRP2
Matt, In our effort to distill the gemac core and related logic, we have pulled out the following module under u2_core SERDES, Dsp core, UART, external RAM interface and the buffer pool The mac is all contained in simple_gemac, and above that in simple_gemac_wrapper: which is instantiated in u2_core. Most of the buffering happens in simple_gemac_wrapper in the fifo_2clock_cascade files. (a) Is any buffering for the gemac done using buffers in the buffer pool or is it ok to eliminate that module all together ? (b) The synthesis report currently shows that 24 BRAM's are being used by the design. Does this sound about right ? Are there modules unrelated to gemac or aeMB that we can pull out, to reduce BRAM usage ? Thanks and Regards, Vikram. ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Re: [Discuss-gnuradio] Re: interfacing a DSP array card to USRP2
Matt, 3) Do you have an FPGA internal achitecture block diagram of any type? Is there another group you're aware of doing such major modification FPGA work that we might talk to? There were some on the wiki at one time. If they're not still there I'll post a talk I did which covers the architecture. I have looked at the wiki (http://gnuradio.org/redmine/wiki/gnuradio), however i was not able to find any block diagrams for the internal architecture of the FPGA for USRP2. I still might not be look in the correct place. Could you please point me in the right direction ? It would be nice if you could post the presentation that you made, that covered the architecture. Thanks and Regards, Vikram. ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
Re: [Discuss-gnuradio] Re: interfacing a DSP array card to USRP2
Matt, Thank you for your email. The mac is all contained in simple_gemac, and above that in simple_gemac_wrapper: http://code.ettus.com/redmine/ettus/projects/fpga/repository/revisions/master/show/usrp2/simple_gemac simple_gemac_wrapper in the fifo_2clock_cascade files. which is instantiated in u2_core. Most of the buffering happens in I would just start with the u2_core and simple_gemac_wrapper. If you're not using the SERDES, that is a good place to start ripping out. Does this imply that we can pull out the aeMB core, the 32K RAM and the buffer pool under module u2_core ? To carry out preliminary testing we need to be able to pass data to the gemac and configure appropriate control registers. Could you please suggest what existing modules we could reuse to send data to the gemac ? 3) Do you have an FPGA internal achitecture block diagram of any type? Is there another group you're aware of doing such major modification FPGA work that we might talk to? There were some on the wiki at one time. If they're not still there I'll post a talk I did which covers the architecture. I have looked at the wiki (http://gnuradio.org/redmine/wiki/gnuradio), however i was not able to find any block diagrams for the internal architecture of the FPGA for USRP2. I still might not be look at the right place. Could you please point me in the right direction ? From forum discussions over the past couple of months it appears that USRP2 does not support the 10/100 mode. Could you please help us understand the work effort involved in getting the 10/100 mode working ? Thanks and Regards, Vikram. ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
