[PATCH 1/3] r600: add span support for 2D tiling

[Alan Cox]

> Note if it is known that x and y are less than or equal to 7 it can be
> done in 11 operations.

And bsr is one instruction for x86, cntlzw for ppc

Alan

[RFC] Avoid quadratic behavior in relocs/cs

[Mathias Fröhlich]

Hi,

Attached is a change to the radeon reloc emitting code, that stores the reloc 
index in the buffer object. This avoids quadratic runtime behavior in the 
number of emitted buffer object relocs per command stream.
The reloc index is held in an array indexed by command stream number, which 
means that it should be safe to use with multiple command stream objects in 
place.

The patch itself is bigger than needed since it reindents the 'buffer object 
already has an index' case in cs_gem_write_reloc.

This change is driven by cs_gem_write_reloc already showing up noticable in 
profiles of some of my use cases.

Comments?

By the way, it appears to me that space_accounted should be also a per command 
stream member of the buffer object. True?

Greetings

Mathias
diff --git a/radeon/radeon_bo_gem.c b/radeon/radeon_bo_gem.c
index 081ccb9..6f0a1b7 100644
--- a/radeon/radeon_bo_gem.c
+++ b/radeon/radeon_bo_gem.c
@@ -39,7 +39,6 @@
 #include 
 #include 
 #include "xf86drm.h"
-#include "xf86atomic.h"
 #include "drm.h"
 #include "radeon_drm.h"
 #include "radeon_bo.h"
@@ -50,7 +49,6 @@ struct radeon_bo_gem {
 struct radeon_bo_int base;
 uint32_tname;
 int map_count;
-atomic_treloc_in_cs;
 void *priv_ptr;
 };
 
@@ -68,7 +66,7 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
  uint32_t flags)
 {
 struct radeon_bo_gem *bo;
-int r;
+int i, r;
 
 bo = (struct radeon_bo_gem*)calloc(1, sizeof(struct radeon_bo_gem));
 if (bo == NULL) {
@@ -82,7 +80,8 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
 bo->base.domains = domains;
 bo->base.flags = flags;
 bo->base.ptr = NULL;
-atomic_set(&bo->reloc_in_cs, 0);
+for (i = 0; i < sizeof(bo->base.idx_by_cs)/sizeof(bo->base.idx_by_cs[0]); ++i)
+bo->base.idx_by_cs[i] = -1;
 bo->map_count = 0;
 if (handle) {
 struct drm_gem_open open_arg;
@@ -312,12 +311,6 @@ uint32_t radeon_gem_name_bo(struct radeon_bo *bo)
 return bo_gem->name;
 }
 
-void *radeon_gem_get_reloc_in_cs(struct radeon_bo *bo)
-{
-struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
-return &bo_gem->reloc_in_cs;
-}
-
 int radeon_gem_get_kernel_name(struct radeon_bo *bo, uint32_t *name)
 {
 struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
diff --git a/radeon/radeon_bo_gem.h b/radeon/radeon_bo_gem.h
index 0af8610..c56c58e 100644
--- a/radeon/radeon_bo_gem.h
+++ b/radeon/radeon_bo_gem.h
@@ -38,7 +38,6 @@ struct radeon_bo_manager *radeon_bo_manager_gem_ctor(int fd);
 void radeon_bo_manager_gem_dtor(struct radeon_bo_manager *bom);
 
 uint32_t radeon_gem_name_bo(struct radeon_bo *bo);
-void *radeon_gem_get_reloc_in_cs(struct radeon_bo *bo);
 int radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain);
 int radeon_gem_get_kernel_name(struct radeon_bo *bo, uint32_t *name);
 #endif
diff --git a/radeon/radeon_bo_int.h b/radeon/radeon_bo_int.h
index 9589ead..f47f790 100644
--- a/radeon/radeon_bo_int.h
+++ b/radeon/radeon_bo_int.h
@@ -6,6 +6,8 @@ struct radeon_bo_manager {
 int fd;
 };
 
+#define MAX_CS_COUNT 32
+
 struct radeon_bo_int {
 void*ptr;
 uint32_tflags;
@@ -18,6 +20,8 @@ struct radeon_bo_int {
 struct radeon_bo_manager*bom;
 uint32_tspace_accounted;
 uint32_treferenced_in_cs;
+/* store the reloc index indexed by the cs index number */
+uint32_tidx_by_cs[MAX_CS_COUNT];
 };
 
 /* bo functions */
diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c
index 81bd393..00440e6 100644
--- a/radeon/radeon_cs_gem.c
+++ b/radeon/radeon_cs_gem.c
@@ -43,7 +43,6 @@
 #include "radeon_bo_gem.h"
 #include "drm.h"
 #include "xf86drm.h"
-#include "xf86atomic.h"
 #include "radeon_drm.h"
 #include "bof.h"
 
@@ -94,6 +93,9 @@ static uint32_t get_first_zero(const uint32_t n)
 static uint32_t generate_id(void)
 {
 uint32_t r = 0;
+
+assert(MAX_CS_COUNT == 8*sizeof(r));
+
 pthread_mutex_lock( &id_mutex );
 /* check for free ids */
 if (cs_id_source != ~r) {
@@ -142,6 +144,7 @@ static struct radeon_cs_int *cs_gem_create(struct radeon_cs_manager *csm,
 csg->base.relocs_total_size = 0;
 csg->base.crelocs = 0;
 csg->base.id = generate_id();
+csg->base.index = get_first_zero(csg->base.id) - 2;
 csg->nrelocs = 4096 / (4 * 4) ;
 csg->relocs_bo = (struct radeon_bo_int**)calloc(1,
 csg->nrelocs*sizeof(void*));
@@ -176,7 +179,6 @@ static int cs_gem_write_reloc(struct radeon_cs_int *cs,
 struct cs_gem *csg = (struct cs_gem*)cs;
 struct cs_reloc_gem *reloc;
 uint32_t idx;
-unsigned i;
 
 assert(boi->space_accounted);
 
@@ -193,46 +195,38 @@ static int cs_gem_write_reloc(struct radeon_cs_int *cs,
 if (write_domain == RADEON_GEM_DOM

[Bug 28284] [r300, r600] celestia core dumps - Assertion `dstRowStride' failed.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=28284

--- Comment #4 from Will Dyson  2010-05-27 21:56:22 PDT 
---
Created an attachment (id=35898)
 View: https://bugs.freedesktop.org/attachment.cgi?id=35898
 Review: https://bugs.freedesktop.org/review?bug=28284&attachment=35898

Alternate patch for mipmap HW generation

Contains a revert of the bad changes

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[Bug 28284] [r300, r600] celestia core dumps - Assertion `dstRowStride' failed.

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=28284

--- Comment #4 from Will Dyson  2010-05-27 21:56:22 
PDT ---
Created an attachment (id=35898)
 View: https://bugs.freedesktop.org/attachment.cgi?id=35898
 Review: https://bugs.freedesktop.org/review?bug=28284&attachment=35898

Alternate patch for mipmap HW generation

Contains a revert of the bad changes

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[Bug 28284] [r300, r600] celestia core dumps - Assertion `dstRowStride' failed.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=28284

--- Comment #3 from Will Dyson  2010-05-27 21:53:52 PDT 
---
(In reply to comment #2)
> (In reply to comment #1)
> > Is this a recent regression?  If so, can you bisect it?  I suspect one of 
> > the
> > recent mipmap patches if so.
> 
> My (admitted limited) git-fu says:
> 
> a9ee95651131e27d5acf3d10909b5b7e5c8d3e92 is the first bad commit
> commit a9ee95651131e27d5acf3d10909b5b7e5c8d3e92
> Author: Will Dyson 
> Date:   Tue May 25 01:10:20 2010 -0400

Crap. The driver really does allocate memory based on the maxlevel of the
texture object. I've got an alternate patch though...

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[Bug 28284] [r300, r600] celestia core dumps - Assertion `dstRowStride' failed.

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=28284

--- Comment #3 from Will Dyson  2010-05-27 21:53:52 
PDT ---
(In reply to comment #2)
> (In reply to comment #1)
> > Is this a recent regression?  If so, can you bisect it?  I suspect one of 
> > the
> > recent mipmap patches if so.
> 
> My (admitted limited) git-fu says:
> 
> a9ee95651131e27d5acf3d10909b5b7e5c8d3e92 is the first bad commit
> commit a9ee95651131e27d5acf3d10909b5b7e5c8d3e92
> Author: Will Dyson 
> Date:   Tue May 25 01:10:20 2010 -0400

Crap. The driver really does allocate memory based on the maxlevel of the
texture object. I've got an alternate patch though...

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[PATCH 1/3] r600: add span support for 2D tiling

[Matt Turner]

On Thu, May 27, 2010 at 7:52 PM, Alan Cox  wrote:
>> Look up tables have some hidden penalties but I think it might be a
>> win. Looks like we may have to benchmark the solutions against one
>> another to really know which is best in real life.
>
> For x86 and ppc the single assembler instruction is fastest. Can you wire
> an R600 to anything else ?

2400HD and 4350HD are available as PCI, so I could get one in an
Alpha, but I haven't yet.

(Alpha has count-{leading,trailing} zero instructions too)

Matt

[PATCH 1/3] r600: add span support for 2D tiling

[Alex Deucher]

On Thu, May 27, 2010 at 7:52 PM, Alan Cox  wrote:
>> Look up tables have some hidden penalties but I think it might be a
>> win. Looks like we may have to benchmark the solutions against one
>> another to really know which is best in real life.
>
> For x86 and ppc the single assembler instruction is fastest. Can you wire
> an R600 to anything else ?

Anything with a pci or pcie bus in theory.  This is a slow path
already, so I doesn't really matter what we use.  I'd prefer to keep
the code readable.

Alex

[PATCH] drm/radeon/kms/pm: add support for SetVoltage cmd table (V2)

[Alex Deucher]

- This enables voltage adjustment on r6xx+ and certain
r5xx asics.
- Voltage drop support is already available for most
r1xx-r5xx asics.

V2: endian fix for voltage table.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/r600.c|6 +
 drivers/gpu/drm/radeon/radeon.h  |1 +
 drivers/gpu/drm/radeon/radeon_atombios.c |   36 ++
 drivers/gpu/drm/radeon/rs600.c   |3 +-
 4 files changed, 45 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index dac2534..d84d7cf 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -475,6 +475,12 @@ void r600_pm_init_profile(struct radeon_device *rdev)

 void r600_pm_misc(struct radeon_device *rdev)
 {
+   int requested_index = rdev->pm.requested_power_state_index;
+   struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
+   struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
+
+   if ((voltage->type == VOLTAGE_SW) && voltage->voltage)
+   radeon_atom_set_voltage(rdev, voltage->voltage);

 }

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 78b59a7..a2561c0 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -176,6 +176,7 @@ void radeon_pm_suspend(struct radeon_device *rdev);
 void radeon_pm_resume(struct radeon_device *rdev);
 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
+void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);

 /*
  * Fences.
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
b/drivers/gpu/drm/radeon/radeon_atombios.c
index da42306..107ada0 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2015,6 +2015,42 @@ void radeon_atom_set_memory_clock(struct radeon_device 
*rdev,
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t 
*)&args);
 }

+union set_voltage {
+   struct _SET_VOLTAGE_PS_ALLOCATION alloc;
+   struct _SET_VOLTAGE_PARAMETERS v1;
+   struct _SET_VOLTAGE_PARAMETERS_V2 v2;
+};
+
+void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
+{
+   union set_voltage args;
+   int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
+   u8 frev, crev, volt_index = level;
+
+   if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 
&crev))
+   return;
+
+   switch (crev) {
+   case 1:
+   args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
+   args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
+   args.v1.ucVoltageIndex = volt_index;
+   break;
+   case 2:
+   args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
+   args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
+   args.v2.usVoltageLevel = cpu_to_le16(level);
+   break;
+   default:
+   DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
+   return;
+   }
+
+   atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t 
*)&args);
+}
+
+
+
 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
 {
struct radeon_device *rdev = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 79887ca..7bb4c3e 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -74,7 +74,8 @@ void rs600_pm_misc(struct radeon_device *rdev)
if (voltage->delay)
udelay(voltage->delay);
}
-   }
+   } else if (voltage->type == VOLTAGE_VDDC)
+   radeon_atom_set_voltage(rdev, voltage->vddc_id);

dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
-- 
1.5.6.3

No subject

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0x44f497f0  0x44f64288  Yes (*) /lib/libk5crypto.so.3
0x4687ea00  0x468

[PATCH]: radeon: Fix uninitialized variable warning in atombios_crtc_set_pll()

[Prarit Bhargava]

Fixes:

drivers/gpu/drm/radeon/atombios_crtc.c: In function ???atombios_crtc_set_pll???:
drivers/gpu/drm/radeon/atombios_crtc.c:678: error: ???pll??? may be used 
uninitialized in this function

Signed-off-by: Prarit Bhargava 

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c 
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 3feca6a..520deae 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -675,7 +675,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, 
struct drm_display_mode
union set_pixel_clock args;
u32 pll_clock = mode->clock;
u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
-   struct radeon_pll *pll;
+   struct radeon_pll *(uninitialized_var(pll);
u32 adjusted_clock;
int encoder_mode = 0;

[PATCH 1/4] drm: Remove drm_resource wrappers

[Matt Turner]

Seems like a good simplification.

Reviewed-by: Matt Turner 

Re: [PATCH 1/3] r600: add span support for 2D tiling

[Matt Turner]

On Thu, May 27, 2010 at 7:52 PM, Alan Cox  wrote:
>> Look up tables have some hidden penalties but I think it might be a
>> win. Looks like we may have to benchmark the solutions against one
>> another to really know which is best in real life.
>
> For x86 and ppc the single assembler instruction is fastest. Can you wire
> an R600 to anything else ?

2400HD and 4350HD are available as PCI, so I could get one in an
Alpha, but I haven't yet.

(Alpha has count-{leading,trailing} zero instructions too)

Matt
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[PATCH] drm/radeon/kms/pm: add support for SetVoltage cmd table

[Alex Deucher]

- This enables voltage adjustment on r6xx+ and certain
r5xx asics.
- Voltage drop support is already available for most
r1xx-r5xx asics.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/r600.c|6 +
 drivers/gpu/drm/radeon/radeon.h  |1 +
 drivers/gpu/drm/radeon/radeon_atombios.c |   36 ++
 drivers/gpu/drm/radeon/rs600.c   |3 +-
 4 files changed, 45 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index dac2534..d84d7cf 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -475,6 +475,12 @@ void r600_pm_init_profile(struct radeon_device *rdev)

 void r600_pm_misc(struct radeon_device *rdev)
 {
+   int requested_index = rdev->pm.requested_power_state_index;
+   struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
+   struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
+
+   if ((voltage->type == VOLTAGE_SW) && voltage->voltage)
+   radeon_atom_set_voltage(rdev, voltage->voltage);

 }

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 78b59a7..a2561c0 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -176,6 +176,7 @@ void radeon_pm_suspend(struct radeon_device *rdev);
 void radeon_pm_resume(struct radeon_device *rdev);
 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
+void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);

 /*
  * Fences.
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
b/drivers/gpu/drm/radeon/radeon_atombios.c
index da42306..be5f755 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2015,6 +2015,42 @@ void radeon_atom_set_memory_clock(struct radeon_device 
*rdev,
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t 
*)&args);
 }

+union set_voltage {
+   struct _SET_VOLTAGE_PS_ALLOCATION alloc;
+   struct _SET_VOLTAGE_PARAMETERS v1;
+   struct _SET_VOLTAGE_PARAMETERS_V2 v2;
+};
+
+void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
+{
+   union set_voltage args;
+   int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
+   u8 frev, crev, volt_index = level;
+
+   if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 
&crev))
+   return;
+
+   switch (crev) {
+   case 1:
+   args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
+   args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
+   args.v1.ucVoltageIndex = volt_index;
+   break;
+   case 2:
+   args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
+   args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
+   args.v2.usVoltageLevel = level;
+   break;
+   default:
+   DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
+   return;
+   }
+
+   atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t 
*)&args);
+}
+
+
+
 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
 {
struct radeon_device *rdev = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 79887ca..7bb4c3e 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -74,7 +74,8 @@ void rs600_pm_misc(struct radeon_device *rdev)
if (voltage->delay)
udelay(voltage->delay);
}
-   }
+   } else if (voltage->type == VOLTAGE_VDDC)
+   radeon_atom_set_voltage(rdev, voltage->vddc_id);

dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
-- 
1.5.6.3

[PATCH] drm/radeon/kms/pm: voltage fixes

[Alex Deucher]

- Enable GPIO voltage for non pm modes as well so resetting
the default voltage works.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/radeon_atombios.c |9 ++---
 drivers/gpu/drm/radeon/radeon_combios.c  |7 ++-
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
b/drivers/gpu/drm/radeon/radeon_atombios.c
index ebfe8fd..da42306 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1529,7 +1529,8 @@ void radeon_atombios_get_power_modes(struct radeon_device 
*rdev)

rdev->pm.power_state[state_index].pcie_lanes =

power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
misc = 
le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
-   if (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
+   if ((misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
+   (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {

rdev->pm.power_state[state_index].clock_info[0].voltage.type =
VOLTAGE_GPIO;

rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
@@ -1596,7 +1597,8 @@ void radeon_atombios_get_power_modes(struct radeon_device 
*rdev)

power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
misc = 
le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
misc2 = 
le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
-   if (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
+   if ((misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
+   (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {

rdev->pm.power_state[state_index].clock_info[0].voltage.type =
VOLTAGE_GPIO;

rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
@@ -1670,7 +1672,8 @@ void radeon_atombios_get_power_modes(struct radeon_device 
*rdev)

power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
misc = 
le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
misc2 = 
le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
-   if (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
+   if ((misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
+   (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {

rdev->pm.power_state[state_index].clock_info[0].voltage.type =
VOLTAGE_GPIO;

rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c 
b/drivers/gpu/drm/radeon/radeon_combios.c
index 7b5e10d..102c744 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -2454,7 +2454,12 @@ default_mode:
rdev->pm.power_state[state_index].clock_info[0].mclk = 
rdev->clock.default_mclk;
rdev->pm.power_state[state_index].clock_info[0].sclk = 
rdev->clock.default_sclk;
rdev->pm.power_state[state_index].default_clock_mode = 
&rdev->pm.power_state[state_index].clock_info[0];
-   rdev->pm.power_state[state_index].clock_info[0].voltage.type = 
VOLTAGE_NONE;
+   if ((state_index > 0) &&
+   (rdev->pm.power_state[0].clock_info[0].voltage.type = VOLTAGE_GPIO))
+   rdev->pm.power_state[state_index].clock_info[0].voltage =
+   rdev->pm.power_state[0].clock_info[0].voltage;
+   else
+   rdev->pm.power_state[state_index].clock_info[0].voltage.type = 
VOLTAGE_NONE;
rdev->pm.power_state[state_index].pcie_lanes = 16;
rdev->pm.power_state[state_index].flags = 0;
rdev->pm.default_power_state_index = state_index;
-- 
1.5.6.3

[PATCH] drm/radeon/kms/pm: radeon_set_power_state fixes

[Alex Deucher]

- wait for vbl for both profile and dynpm
- unify profile and dynpm code paths more
- call pm_misc before of after clocks to make
sure voltage is changed in the proper order.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/radeon_pm.c |   75 ---
 1 files changed, 34 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_pm.c 
b/drivers/gpu/drm/radeon/radeon_pm.c
index c88edae..a51326c 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -151,6 +151,7 @@ static void radeon_sync_with_vblank(struct radeon_device 
*rdev)
 static void radeon_set_power_state(struct radeon_device *rdev)
 {
u32 sclk, mclk;
+   bool misc_after = false;

if ((rdev->pm.requested_clock_mode_index == 
rdev->pm.current_clock_mode_index) &&
(rdev->pm.requested_power_state_index == 
rdev->pm.current_power_state_index))
@@ -167,55 +168,47 @@ static void radeon_set_power_state(struct radeon_device 
*rdev)
if (mclk > rdev->clock.default_mclk)
mclk = rdev->clock.default_mclk;

-   /* voltage, pcie lanes, etc.*/
-   radeon_pm_misc(rdev);
+   /* upvolt before raising clocks, downvolt after lowering clocks 
*/
+   if (sclk < rdev->pm.current_sclk)
+   misc_after = true;

-   if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
-   radeon_sync_with_vblank(rdev);
+   radeon_sync_with_vblank(rdev);

+   if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
if (!radeon_pm_in_vbl(rdev))
return;
+   }

-   radeon_pm_prepare(rdev);
-   /* set engine clock */
-   if (sclk != rdev->pm.current_sclk) {
-   radeon_pm_debug_check_in_vbl(rdev, false);
-   radeon_set_engine_clock(rdev, sclk);
-   radeon_pm_debug_check_in_vbl(rdev, true);
-   rdev->pm.current_sclk = sclk;
-   DRM_DEBUG("Setting: e: %d\n", sclk);
-   }
+   radeon_pm_prepare(rdev);

-   /* set memory clock */
-   if (rdev->asic->set_memory_clock && (mclk != 
rdev->pm.current_mclk)) {
-   radeon_pm_debug_check_in_vbl(rdev, false);
-   radeon_set_memory_clock(rdev, mclk);
-   radeon_pm_debug_check_in_vbl(rdev, true);
-   rdev->pm.current_mclk = mclk;
-   DRM_DEBUG("Setting: m: %d\n", mclk);
-   }
-   radeon_pm_finish(rdev);
-   } else {
-   /* set engine clock */
-   if (sclk != rdev->pm.current_sclk) {
-   radeon_sync_with_vblank(rdev);
-   radeon_pm_prepare(rdev);
-   radeon_set_engine_clock(rdev, sclk);
-   radeon_pm_finish(rdev);
-   rdev->pm.current_sclk = sclk;
-   DRM_DEBUG("Setting: e: %d\n", sclk);
-   }
-   /* set memory clock */
-   if (rdev->asic->set_memory_clock && (mclk != 
rdev->pm.current_mclk)) {
-   radeon_sync_with_vblank(rdev);
-   radeon_pm_prepare(rdev);
-   radeon_set_memory_clock(rdev, mclk);
-   radeon_pm_finish(rdev);
-   rdev->pm.current_mclk = mclk;
-   DRM_DEBUG("Setting: m: %d\n", mclk);
-   }
+   if (!misc_after)
+   /* voltage, pcie lanes, etc.*/
+   radeon_pm_misc(rdev);
+
+   /* set engine clock */
+   if (sclk != rdev->pm.current_sclk) {
+   radeon_pm_debug_check_in_vbl(rdev, false);
+   radeon_set_engine_clock(rdev, sclk);
+   radeon_pm_debug_check_in_vbl(rdev, true);
+   rdev->pm.current_sclk = sclk;
+   DRM_DEBUG("Setting: e: %d\n", sclk);
+   }
+
+   /* set memory clock */
+   if (rdev->asic->set_memory_clock && (mclk != 
rdev->pm.current_mclk)) {
+   radeon_pm_debug_check_in_vbl(rdev, false);
+   radeon_set_memory_clock(rdev, mclk);
+   radeon_pm_debug_check_in_vbl(rdev, true);
+   rdev->pm.current_mclk = mclk;
+   DRM_DEBUG("Setting: m: %d\n", mclk);
}

+   if (misc_after)
+  

[PATCH] drm/radeon/kms/pm: patch default power state with default clocks/voltages on r6xx+

[Alex Deucher]

The default power state does not always match the default clocks and voltage
for a particular card.  The information in the firmware info table is correct
and should be used in preference to the info the default power state.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/radeon_atombios.c |   25 -
 1 files changed, 24 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
b/drivers/gpu/drm/radeon/radeon_atombios.c
index f858be0..ebfe8fd 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1746,9 +1746,22 @@ void radeon_atombios_get_power_modes(struct 
radeon_device *rdev)
rdev->pm.power_state[state_index].misc2 = 0;
}
} else {
+   int fw_index = GetIndexIntoMasterTable(DATA, 
FirmwareInfo);
+   uint8_t fw_frev, fw_crev;
+   uint16_t fw_data_offset, vddc = 0;
+   union firmware_info *firmware_info;
+   ATOM_PPLIB_THERMALCONTROLLER *controller = 
&power_info->info_4.sThermalController;
+
+   if (atom_parse_data_header(mode_info->atom_context, 
fw_index, NULL,
+  &fw_frev, &fw_crev, 
&fw_data_offset)) {
+   firmware_info =
+   (union firmware_info 
*)(mode_info->atom_context->bios +
+   fw_data_offset);
+   vddc = 
firmware_info->info_14.usBootUpVDDCVoltage;
+   }
+
/* add the i2c bus for thermal/fan chip */
/* no support for internal controller yet */
-   ATOM_PPLIB_THERMALCONTROLLER *controller = 
&power_info->info_4.sThermalController;
if (controller->ucType > 0) {
if ((controller->ucType == 
ATOM_PP_THERMALCONTROLLER_RV6xx) ||
(controller->ucType == 
ATOM_PP_THERMALCONTROLLER_RV770) ||
@@ -1895,6 +1908,16 @@ void radeon_atombios_get_power_modes(struct 
radeon_device *rdev)

rdev->pm.default_power_state_index = state_index;

rdev->pm.power_state[state_index].default_clock_mode =

&rdev->pm.power_state[state_index].clock_info[mode_index - 1];
+   /* patch the table values with 
the default slck/mclk from firmware info */
+   for (j = 0; j < mode_index; 
j++) {
+   
rdev->pm.power_state[state_index].clock_info[j].mclk =
+   
rdev->clock.default_mclk;
+   
rdev->pm.power_state[state_index].clock_info[j].sclk =
+   
rdev->clock.default_sclk;
+   if (vddc)
+   
rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
+   vddc;
+   }
}
state_index++;
}
-- 
1.5.6.3

Re: [PATCH 1/3] r600: add span support for 2D tiling

[Alex Deucher]

On Thu, May 27, 2010 at 7:52 PM, Alan Cox  wrote:
>> Look up tables have some hidden penalties but I think it might be a
>> win. Looks like we may have to benchmark the solutions against one
>> another to really know which is best in real life.
>
> For x86 and ppc the single assembler instruction is fastest. Can you wire
> an R600 to anything else ?

Anything with a pci or pcie bus in theory.  This is a slow path
already, so I doesn't really matter what we use.  I'd prefer to keep
the code readable.

Alex
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Re: [PATCH 1/3] r600: add span support for 2D tiling

[Alan Cox]

> Look up tables have some hidden penalties but I think it might be a
> win. Looks like we may have to benchmark the solutions against one
> another to really know which is best in real life.

For x86 and ppc the single assembler instruction is fastest. Can you wire
an R600 to anything else ?
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[PATCH 1/3] r600: add span support for 2D tiling

[Alan Cox]

On Thu, 27 May 2010 11:20:59 -0400
Alex Deucher  wrote:

> On Thu, May 27, 2010 at 10:55 AM, Matt Turner  wrote:
> >> +static inline GLint r600_log2(GLint n)
> >> +{
> >> + ? ? ? GLint log2 = 0;
> >> +
> >> + ? ? ? while (n >>= 1)
> >> + ? ? ? ? ? ? ? ++log2;
> >> + ? ? ? return log2;
> >> +}
> >
> > Does mesa not provide something like this?
> 
> The only one I could find was a gallium utility function.

include/linux/log2.h

The original is from Red Hat so if you need it non GPL maybe Red Hat can
help ?

Re: [PATCH 1/3] r600: add span support for 2D tiling

[Conn Clark]

On Thu, May 27, 2010 at 4:01 PM, Frieder Ferlemann
 wrote:
> Hi,
>
> Am 28.05.2010 00:04, schrieb Conn Clark:
>> On Thu, May 27, 2010 at 8:51 AM, Brian Paul  wrote:
>>
>> This code could be written with a faster algorithm requiring  just 13 
>> operations
>>
>> +               pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
>> +               pixel_number |= ((y >> 0) & 1) << 1; // pn[1] = y[0]
>> +               pixel_number |= ((x >> 1) & 1) << 2; // pn[2] = x[1]
>> +               pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1]
>> +               pixel_number |= ((x >> 2) & 1) << 4; // pn[4] = x[2]
>> +               pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
>>
>
>
>> /* suitable for all 16 bit or greater processors that can do an
>> unsigned 16 bit or greater multiply */
>> /*  tested and verified  */
>>
>> pixel_number = x & 0x07) * 0x & 0x8421) * 0x1249 >> 9) & 0x55 ) |
>>                              y & 0x07) * 0x & 0x8421) * 0x1249
 8) & 0xAA );
>>
>> Note if it is known that x and y are less than or equal to 7 it can be
>> done in 11 operations.
>
> Cool. How does it compare to:
>
>        const unsigned char /*int*/ spread_bits[8] = {
>                0x00,  /* 0b000 to 0b0 */
>                0x01,  /* 0b001 to 0b1 */
>                0x04,  /* 0b010 to 0b00100 */
>                0x05,  /* 0b011 to 0b00101 */
>                0x10,  /* 0b100 to 0b1 */
>                0x11,  /* 0b101 to 0b10001 */
>                0x14,  /* 0b110 to 0b10100 */
>                0x15,  /* 0b111 to 0b10101 */
>        };
>
>        pixel_number |= spread_bits[x & 0x07];
>        pixel_number |= spread_bits[y & 0x07] << 1;
>
>
> Greetings,
> Frieder
>

Look up tables have some hidden penalties but I think it might be a
win. Looks like we may have to benchmark the solutions against one
another to really know which is best in real life.

Conn

-- 

Conn O. Clark

Observation: In formal computer science advances are made
by standing on the shoulders of giants. Linux has proved
that if there are enough of you, you can advance just as
far by stepping on each others toes.
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[PATCH 1/3] r600: add span support for 2D tiling

[Conn Clark]

On Thu, May 27, 2010 at 4:01 PM, Frieder Ferlemann
 wrote:
> Hi,
>
> Am 28.05.2010 00:04, schrieb Conn Clark:
>> On Thu, May 27, 2010 at 8:51 AM, Brian Paul  wrote:
>>
>> This code could be written with a faster algorithm requiring ?just 13 
>> operations
>>
>> + ? ? ? ? ? ? ? pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
>> + ? ? ? ? ? ? ? pixel_number |= ((y >> 0) & 1) << 1; // pn[1] = y[0]
>> + ? ? ? ? ? ? ? pixel_number |= ((x >> 1) & 1) << 2; // pn[2] = x[1]
>> + ? ? ? ? ? ? ? pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1]
>> + ? ? ? ? ? ? ? pixel_number |= ((x >> 2) & 1) << 4; // pn[4] = x[2]
>> + ? ? ? ? ? ? ? pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
>>
>
>
>> /* suitable for all 16 bit or greater processors that can do an
>> unsigned 16 bit or greater multiply */
>> /* ?tested and verified ?*/
>>
>> pixel_number = x & 0x07) * 0x & 0x8421) * 0x1249 >> 9) & 0x55 ) |
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?y & 0x07) * 0x & 0x8421) * 0x1249
 8) & 0xAA );
>>
>> Note if it is known that x and y are less than or equal to 7 it can be
>> done in 11 operations.
>
> Cool. How does it compare to:
>
> ? ? ? ?const unsigned char /*int*/ spread_bits[8] = {
> ? ? ? ? ? ? ? ?0x00, ?/* 0b000 to 0b0 */
> ? ? ? ? ? ? ? ?0x01, ?/* 0b001 to 0b1 */
> ? ? ? ? ? ? ? ?0x04, ?/* 0b010 to 0b00100 */
> ? ? ? ? ? ? ? ?0x05, ?/* 0b011 to 0b00101 */
> ? ? ? ? ? ? ? ?0x10, ?/* 0b100 to 0b1 */
> ? ? ? ? ? ? ? ?0x11, ?/* 0b101 to 0b10001 */
> ? ? ? ? ? ? ? ?0x14, ?/* 0b110 to 0b10100 */
> ? ? ? ? ? ? ? ?0x15, ?/* 0b111 to 0b10101 */
> ? ? ? ?};
>
> ? ? ? ?pixel_number |= spread_bits[x & 0x07];
> ? ? ? ?pixel_number |= spread_bits[y & 0x07] << 1;
>
>
> Greetings,
> Frieder
>

Look up tables have some hidden penalties but I think it might be a
win. Looks like we may have to benchmark the solutions against one
another to really know which is best in real life.

Conn

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that if there are enough of you, you can advance just as
far by stepping on each others toes.

[PATCH] drm/radeon/kms/pm: add support for SetVoltage cmd table (V2)

[Alex Deucher]

- This enables voltage adjustment on r6xx+ and certain
r5xx asics.
- Voltage drop support is already available for most
r1xx-r5xx asics.

V2: endian fix for voltage table.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/r600.c|6 +
 drivers/gpu/drm/radeon/radeon.h  |1 +
 drivers/gpu/drm/radeon/radeon_atombios.c |   36 ++
 drivers/gpu/drm/radeon/rs600.c   |3 +-
 4 files changed, 45 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index dac2534..d84d7cf 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -475,6 +475,12 @@ void r600_pm_init_profile(struct radeon_device *rdev)
 
 void r600_pm_misc(struct radeon_device *rdev)
 {
+   int requested_index = rdev->pm.requested_power_state_index;
+   struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
+   struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
+
+   if ((voltage->type == VOLTAGE_SW) && voltage->voltage)
+   radeon_atom_set_voltage(rdev, voltage->voltage);
 
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 78b59a7..a2561c0 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -176,6 +176,7 @@ void radeon_pm_suspend(struct radeon_device *rdev);
 void radeon_pm_resume(struct radeon_device *rdev);
 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
+void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
 
 /*
  * Fences.
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
b/drivers/gpu/drm/radeon/radeon_atombios.c
index da42306..107ada0 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2015,6 +2015,42 @@ void radeon_atom_set_memory_clock(struct radeon_device 
*rdev,
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t 
*)&args);
 }
 
+union set_voltage {
+   struct _SET_VOLTAGE_PS_ALLOCATION alloc;
+   struct _SET_VOLTAGE_PARAMETERS v1;
+   struct _SET_VOLTAGE_PARAMETERS_V2 v2;
+};
+
+void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
+{
+   union set_voltage args;
+   int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
+   u8 frev, crev, volt_index = level;
+
+   if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 
&crev))
+   return;
+
+   switch (crev) {
+   case 1:
+   args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
+   args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
+   args.v1.ucVoltageIndex = volt_index;
+   break;
+   case 2:
+   args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
+   args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
+   args.v2.usVoltageLevel = cpu_to_le16(level);
+   break;
+   default:
+   DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
+   return;
+   }
+
+   atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t 
*)&args);
+}
+
+
+
 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
 {
struct radeon_device *rdev = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 79887ca..7bb4c3e 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -74,7 +74,8 @@ void rs600_pm_misc(struct radeon_device *rdev)
if (voltage->delay)
udelay(voltage->delay);
}
-   }
+   } else if (voltage->type == VOLTAGE_VDDC)
+   radeon_atom_set_voltage(rdev, voltage->vddc_id);
 
dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
-- 
1.5.6.3

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Re: [PATCH 1/3] r600: add span support for 2D tiling

[Frieder Ferlemann]

Hi,

Am 28.05.2010 00:04, schrieb Conn Clark:
> On Thu, May 27, 2010 at 8:51 AM, Brian Paul  wrote:
> 
> This code could be written with a faster algorithm requiring  just 13 
> operations
> 
> +   pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
> +   pixel_number |= ((y >> 0) & 1) << 1; // pn[1] = y[0]
> +   pixel_number |= ((x >> 1) & 1) << 2; // pn[2] = x[1]
> +   pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1]
> +   pixel_number |= ((x >> 2) & 1) << 4; // pn[4] = x[2]
> +   pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
> 


> /* suitable for all 16 bit or greater processors that can do an
> unsigned 16 bit or greater multiply */
> /*  tested and verified  */
> 
> pixel_number = x & 0x07) * 0x & 0x8421) * 0x1249 >> 9) & 0x55 ) |
>  y & 0x07) * 0x & 0x8421) * 0x1249
>>> 8) & 0xAA );
> 
> Note if it is known that x and y are less than or equal to 7 it can be
> done in 11 operations.

Cool. How does it compare to:

const unsigned char /*int*/ spread_bits[8] = {
0x00,  /* 0b000 to 0b0 */
0x01,  /* 0b001 to 0b1 */
0x04,  /* 0b010 to 0b00100 */
0x05,  /* 0b011 to 0b00101 */
0x10,  /* 0b100 to 0b1 */
0x11,  /* 0b101 to 0b10001 */
0x14,  /* 0b110 to 0b10100 */
0x15,  /* 0b111 to 0b10101 */
};

pixel_number |= spread_bits[x & 0x07];
pixel_number |= spread_bits[y & 0x07] << 1;


Greetings,
Frieder
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Re: [PATCH 1/3] r600: add span support for 2D tiling

[Alan Cox]

> Note if it is known that x and y are less than or equal to 7 it can be
> done in 11 operations.

And bsr is one instruction for x86, cntlzw for ppc

Alan
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[PATCH]: radeon: Fix uninitialized variable warning in atombios_crtc_set_pll()

[Prarit Bhargava]

Fixes:

drivers/gpu/drm/radeon/atombios_crtc.c: In function ‘atombios_crtc_set_pll’:
drivers/gpu/drm/radeon/atombios_crtc.c:678: error: ‘pll’ may be used 
uninitialized in this function

Signed-off-by: Prarit Bhargava 

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c 
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 3feca6a..520deae 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -675,7 +675,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, 
struct drm_display_mode
union set_pixel_clock args;
u32 pll_clock = mode->clock;
u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
-   struct radeon_pll *pll;
+   struct radeon_pll *(uninitialized_var(pll);
u32 adjusted_clock;
int encoder_mode = 0;
 
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[Bug 28284] [r300, r600] celestia core dumps - Assertion `dstRowStride' failed.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=28284

--- Comment #2 from Chris Rankin  2010-05-27 15:12:52 
PDT ---
(In reply to comment #1)
> Is this a recent regression?  If so, can you bisect it?  I suspect one of the
> recent mipmap patches if so.

My (admitted limited) git-fu says:

a9ee95651131e27d5acf3d10909b5b7e5c8d3e92 is the first bad commit
commit a9ee95651131e27d5acf3d10909b5b7e5c8d3e92
Author: Will Dyson 
Date:   Tue May 25 01:10:20 2010 -0400

Fix image_matches_texture_obj() MaxLevel check

When generating or uploading a new (higher) mipmap level for an image,
we can need to allocate a miptree for a level greater than
texObj->MaxLevel.

Signed-off-by: Maciej Cencora 
Signed-off-by: Alex Deucher 

:04 04 4e72a3914fd8572238c211c806b19d274557d5a9
ff974b144171e820cf2c22af344905ba62dcd446 Msrc

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[Bug 28284] [r300, r600] celestia core dumps - Assertion `dstRowStride' failed.

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=28284

--- Comment #2 from Chris Rankin  2010-05-27 
15:12:52 PDT ---
(In reply to comment #1)
> Is this a recent regression?  If so, can you bisect it?  I suspect one of the
> recent mipmap patches if so.

My (admitted limited) git-fu says:

a9ee95651131e27d5acf3d10909b5b7e5c8d3e92 is the first bad commit
commit a9ee95651131e27d5acf3d10909b5b7e5c8d3e92
Author: Will Dyson 
Date:   Tue May 25 01:10:20 2010 -0400

Fix image_matches_texture_obj() MaxLevel check

When generating or uploading a new (higher) mipmap level for an image,
we can need to allocate a miptree for a level greater than
texObj->MaxLevel.

Signed-off-by: Maciej Cencora 
Signed-off-by: Alex Deucher 

:04 04 4e72a3914fd8572238c211c806b19d274557d5a9
ff974b144171e820cf2c22af344905ba62dcd446 Msrc

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Re: [PATCH 1/3] r600: add span support for 2D tiling

[Conn Clark]

On Thu, May 27, 2010 at 8:51 AM, Brian Paul  wrote:
> Alex Deucher wrote:
>>
>> On Thu, May 27, 2010 at 10:55 AM, Matt Turner  wrote:

 +static inline GLint r600_log2(GLint n)
 +{
 +       GLint log2 = 0;
 +
 +       while (n >>= 1)
 +               ++log2;
 +       return log2;
 +}
>>>
>>> Does mesa not provide something like this?
>>
>> The only one I could find was a gallium utility function.
>
> There's a logbase2() function in teximage.c but it might not be equivalent.
>
> -Brian
>
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>

This code could be written with a faster algorithm requiring  just 13 operations

+   pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+   pixel_number |= ((y >> 0) & 1) << 1; // pn[1] = y[0]
+   pixel_number |= ((x >> 1) & 1) << 2; // pn[2] = x[1]
+   pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1]
+   pixel_number |= ((x >> 2) & 1) << 4; // pn[4] = x[2]
+   pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]



/* suitable for all 16 bit or greater processors that can do an
unsigned 16 bit or greater multiply */
/*  tested and verified  */

pixel_number = x & 0x07) * 0x & 0x8421) * 0x1249 >> 9) & 0x55 ) |
 y & 0x07) * 0x & 0x8421) * 0x1249
>> 8) & 0xAA );

Note if it is known that x and y are less than or equal to 7 it can be
done in 11 operations.

Cheers

Conn
-- 

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Observation: In formal computer science advances are made
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that if there are enough of you, you can advance just as
far by stepping on each others toes.
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[PATCH 1/3] r600: add span support for 2D tiling

[Conn Clark]

On Thu, May 27, 2010 at 8:51 AM, Brian Paul  wrote:
> Alex Deucher wrote:
>>
>> On Thu, May 27, 2010 at 10:55 AM, Matt Turner  wrote:

 +static inline GLint r600_log2(GLint n)
 +{
 + ? ? ? GLint log2 = 0;
 +
 + ? ? ? while (n >>= 1)
 + ? ? ? ? ? ? ? ++log2;
 + ? ? ? return log2;
 +}
>>>
>>> Does mesa not provide something like this?
>>
>> The only one I could find was a gallium utility function.
>
> There's a logbase2() function in teximage.c but it might not be equivalent.
>
> -Brian
>
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>

This code could be written with a faster algorithm requiring  just 13 operations

+   pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+   pixel_number |= ((y >> 0) & 1) << 1; // pn[1] = y[0]
+   pixel_number |= ((x >> 1) & 1) << 2; // pn[2] = x[1]
+   pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1]
+   pixel_number |= ((x >> 2) & 1) << 4; // pn[4] = x[2]
+   pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]



/* suitable for all 16 bit or greater processors that can do an
unsigned 16 bit or greater multiply */
/*  tested and verified  */

pixel_number = x & 0x07) * 0x & 0x8421) * 0x1249 >> 9) & 0x55 ) |
 y & 0x07) * 0x & 0x8421) * 0x1249
>> 8) & 0xAA );

Note if it is known that x and y are less than or equal to 7 it can be
done in 11 operations.

Cheers

Conn
-- 

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Observation: In formal computer science advances are made
by standing on the shoulders of giants. Linux has proved
that if there are enough of you, you can advance just as
far by stepping on each others toes.

Re: [PATCH 1/4] drm: Remove drm_resource wrappers

[Matt Turner]

Seems like a good simplification.

Reviewed-by: Matt Turner 
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Resend: [PATCH 0/2] drm/ttm: A couple of small fixes

[Thomas Hellstrom]

Ping!

On 04/28/2010 11:33 AM, Thomas Hellstrom wrote:
> The first patch removes some leftover debug messages in the ttm_lock code
> so far only used by the vmwgfx driver.
>
> The second patch removes the ttm_bo_block_reservation() function, since
> it is buggy. A bo shouldn't be reserved while remaining on lru lists.
>
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/Thomas

[PATCH] drm/radeon/kms/pm: add support for SetVoltage cmd table

[Alex Deucher]

- This enables voltage adjustment on r6xx+ and certain
r5xx asics.
- Voltage drop support is already available for most
r1xx-r5xx asics.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/r600.c|6 +
 drivers/gpu/drm/radeon/radeon.h  |1 +
 drivers/gpu/drm/radeon/radeon_atombios.c |   36 ++
 drivers/gpu/drm/radeon/rs600.c   |3 +-
 4 files changed, 45 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index dac2534..d84d7cf 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -475,6 +475,12 @@ void r600_pm_init_profile(struct radeon_device *rdev)
 
 void r600_pm_misc(struct radeon_device *rdev)
 {
+   int requested_index = rdev->pm.requested_power_state_index;
+   struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
+   struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
+
+   if ((voltage->type == VOLTAGE_SW) && voltage->voltage)
+   radeon_atom_set_voltage(rdev, voltage->voltage);
 
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 78b59a7..a2561c0 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -176,6 +176,7 @@ void radeon_pm_suspend(struct radeon_device *rdev);
 void radeon_pm_resume(struct radeon_device *rdev);
 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
+void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
 
 /*
  * Fences.
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
b/drivers/gpu/drm/radeon/radeon_atombios.c
index da42306..be5f755 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2015,6 +2015,42 @@ void radeon_atom_set_memory_clock(struct radeon_device 
*rdev,
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t 
*)&args);
 }
 
+union set_voltage {
+   struct _SET_VOLTAGE_PS_ALLOCATION alloc;
+   struct _SET_VOLTAGE_PARAMETERS v1;
+   struct _SET_VOLTAGE_PARAMETERS_V2 v2;
+};
+
+void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
+{
+   union set_voltage args;
+   int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
+   u8 frev, crev, volt_index = level;
+
+   if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 
&crev))
+   return;
+
+   switch (crev) {
+   case 1:
+   args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
+   args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
+   args.v1.ucVoltageIndex = volt_index;
+   break;
+   case 2:
+   args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
+   args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
+   args.v2.usVoltageLevel = level;
+   break;
+   default:
+   DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
+   return;
+   }
+
+   atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t 
*)&args);
+}
+
+
+
 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
 {
struct radeon_device *rdev = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 79887ca..7bb4c3e 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -74,7 +74,8 @@ void rs600_pm_misc(struct radeon_device *rdev)
if (voltage->delay)
udelay(voltage->delay);
}
-   }
+   } else if (voltage->type == VOLTAGE_VDDC)
+   radeon_atom_set_voltage(rdev, voltage->vddc_id);
 
dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
-- 
1.5.6.3

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[PATCH] drm/radeon/kms/pm: voltage fixes

[Alex Deucher]

- Enable GPIO voltage for non pm modes as well so resetting
the default voltage works.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/radeon_atombios.c |9 ++---
 drivers/gpu/drm/radeon/radeon_combios.c  |7 ++-
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
b/drivers/gpu/drm/radeon/radeon_atombios.c
index ebfe8fd..da42306 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1529,7 +1529,8 @@ void radeon_atombios_get_power_modes(struct radeon_device 
*rdev)

rdev->pm.power_state[state_index].pcie_lanes =

power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
misc = 
le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
-   if (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
+   if ((misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
+   (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {

rdev->pm.power_state[state_index].clock_info[0].voltage.type =
VOLTAGE_GPIO;

rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
@@ -1596,7 +1597,8 @@ void radeon_atombios_get_power_modes(struct radeon_device 
*rdev)

power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
misc = 
le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
misc2 = 
le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
-   if (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
+   if ((misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
+   (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {

rdev->pm.power_state[state_index].clock_info[0].voltage.type =
VOLTAGE_GPIO;

rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
@@ -1670,7 +1672,8 @@ void radeon_atombios_get_power_modes(struct radeon_device 
*rdev)

power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
misc = 
le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
misc2 = 
le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
-   if (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
+   if ((misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
+   (misc & 
ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {

rdev->pm.power_state[state_index].clock_info[0].voltage.type =
VOLTAGE_GPIO;

rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c 
b/drivers/gpu/drm/radeon/radeon_combios.c
index 7b5e10d..102c744 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -2454,7 +2454,12 @@ default_mode:
rdev->pm.power_state[state_index].clock_info[0].mclk = 
rdev->clock.default_mclk;
rdev->pm.power_state[state_index].clock_info[0].sclk = 
rdev->clock.default_sclk;
rdev->pm.power_state[state_index].default_clock_mode = 
&rdev->pm.power_state[state_index].clock_info[0];
-   rdev->pm.power_state[state_index].clock_info[0].voltage.type = 
VOLTAGE_NONE;
+   if ((state_index > 0) &&
+   (rdev->pm.power_state[0].clock_info[0].voltage.type = VOLTAGE_GPIO))
+   rdev->pm.power_state[state_index].clock_info[0].voltage =
+   rdev->pm.power_state[0].clock_info[0].voltage;
+   else
+   rdev->pm.power_state[state_index].clock_info[0].voltage.type = 
VOLTAGE_NONE;
rdev->pm.power_state[state_index].pcie_lanes = 16;
rdev->pm.power_state[state_index].flags = 0;
rdev->pm.default_power_state_index = state_index;
-- 
1.5.6.3

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[PATCH] drm/radeon/kms/pm: radeon_set_power_state fixes

[Alex Deucher]

- wait for vbl for both profile and dynpm
- unify profile and dynpm code paths more
- call pm_misc before of after clocks to make
sure voltage is changed in the proper order.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/radeon_pm.c |   75 ---
 1 files changed, 34 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_pm.c 
b/drivers/gpu/drm/radeon/radeon_pm.c
index c88edae..a51326c 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -151,6 +151,7 @@ static void radeon_sync_with_vblank(struct radeon_device 
*rdev)
 static void radeon_set_power_state(struct radeon_device *rdev)
 {
u32 sclk, mclk;
+   bool misc_after = false;
 
if ((rdev->pm.requested_clock_mode_index == 
rdev->pm.current_clock_mode_index) &&
(rdev->pm.requested_power_state_index == 
rdev->pm.current_power_state_index))
@@ -167,55 +168,47 @@ static void radeon_set_power_state(struct radeon_device 
*rdev)
if (mclk > rdev->clock.default_mclk)
mclk = rdev->clock.default_mclk;
 
-   /* voltage, pcie lanes, etc.*/
-   radeon_pm_misc(rdev);
+   /* upvolt before raising clocks, downvolt after lowering clocks 
*/
+   if (sclk < rdev->pm.current_sclk)
+   misc_after = true;
 
-   if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
-   radeon_sync_with_vblank(rdev);
+   radeon_sync_with_vblank(rdev);
 
+   if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
if (!radeon_pm_in_vbl(rdev))
return;
+   }
 
-   radeon_pm_prepare(rdev);
-   /* set engine clock */
-   if (sclk != rdev->pm.current_sclk) {
-   radeon_pm_debug_check_in_vbl(rdev, false);
-   radeon_set_engine_clock(rdev, sclk);
-   radeon_pm_debug_check_in_vbl(rdev, true);
-   rdev->pm.current_sclk = sclk;
-   DRM_DEBUG("Setting: e: %d\n", sclk);
-   }
+   radeon_pm_prepare(rdev);
 
-   /* set memory clock */
-   if (rdev->asic->set_memory_clock && (mclk != 
rdev->pm.current_mclk)) {
-   radeon_pm_debug_check_in_vbl(rdev, false);
-   radeon_set_memory_clock(rdev, mclk);
-   radeon_pm_debug_check_in_vbl(rdev, true);
-   rdev->pm.current_mclk = mclk;
-   DRM_DEBUG("Setting: m: %d\n", mclk);
-   }
-   radeon_pm_finish(rdev);
-   } else {
-   /* set engine clock */
-   if (sclk != rdev->pm.current_sclk) {
-   radeon_sync_with_vblank(rdev);
-   radeon_pm_prepare(rdev);
-   radeon_set_engine_clock(rdev, sclk);
-   radeon_pm_finish(rdev);
-   rdev->pm.current_sclk = sclk;
-   DRM_DEBUG("Setting: e: %d\n", sclk);
-   }
-   /* set memory clock */
-   if (rdev->asic->set_memory_clock && (mclk != 
rdev->pm.current_mclk)) {
-   radeon_sync_with_vblank(rdev);
-   radeon_pm_prepare(rdev);
-   radeon_set_memory_clock(rdev, mclk);
-   radeon_pm_finish(rdev);
-   rdev->pm.current_mclk = mclk;
-   DRM_DEBUG("Setting: m: %d\n", mclk);
-   }
+   if (!misc_after)
+   /* voltage, pcie lanes, etc.*/
+   radeon_pm_misc(rdev);
+
+   /* set engine clock */
+   if (sclk != rdev->pm.current_sclk) {
+   radeon_pm_debug_check_in_vbl(rdev, false);
+   radeon_set_engine_clock(rdev, sclk);
+   radeon_pm_debug_check_in_vbl(rdev, true);
+   rdev->pm.current_sclk = sclk;
+   DRM_DEBUG("Setting: e: %d\n", sclk);
+   }
+
+   /* set memory clock */
+   if (rdev->asic->set_memory_clock && (mclk != 
rdev->pm.current_mclk)) {
+   radeon_pm_debug_check_in_vbl(rdev, false);
+   radeon_set_memory_clock(rdev, mclk);
+   radeon_pm_debug_check_in_vbl(rdev, true);
+   rdev->pm.current_mclk = mclk;
+   DRM_DEBUG("Setting: m: %d\n", mclk);
}
 
+   if (misc_after)

[PATCH] drm/radeon/kms/pm: patch default power state with default clocks/voltages on r6xx+

[Alex Deucher]

The default power state does not always match the default clocks and voltage
for a particular card.  The information in the firmware info table is correct
and should be used in preference to the info the default power state.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/radeon_atombios.c |   25 -
 1 files changed, 24 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
b/drivers/gpu/drm/radeon/radeon_atombios.c
index f858be0..ebfe8fd 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1746,9 +1746,22 @@ void radeon_atombios_get_power_modes(struct 
radeon_device *rdev)
rdev->pm.power_state[state_index].misc2 = 0;
}
} else {
+   int fw_index = GetIndexIntoMasterTable(DATA, 
FirmwareInfo);
+   uint8_t fw_frev, fw_crev;
+   uint16_t fw_data_offset, vddc = 0;
+   union firmware_info *firmware_info;
+   ATOM_PPLIB_THERMALCONTROLLER *controller = 
&power_info->info_4.sThermalController;
+
+   if (atom_parse_data_header(mode_info->atom_context, 
fw_index, NULL,
+  &fw_frev, &fw_crev, 
&fw_data_offset)) {
+   firmware_info =
+   (union firmware_info 
*)(mode_info->atom_context->bios +
+   fw_data_offset);
+   vddc = 
firmware_info->info_14.usBootUpVDDCVoltage;
+   }
+
/* add the i2c bus for thermal/fan chip */
/* no support for internal controller yet */
-   ATOM_PPLIB_THERMALCONTROLLER *controller = 
&power_info->info_4.sThermalController;
if (controller->ucType > 0) {
if ((controller->ucType == 
ATOM_PP_THERMALCONTROLLER_RV6xx) ||
(controller->ucType == 
ATOM_PP_THERMALCONTROLLER_RV770) ||
@@ -1895,6 +1908,16 @@ void radeon_atombios_get_power_modes(struct 
radeon_device *rdev)

rdev->pm.default_power_state_index = state_index;

rdev->pm.power_state[state_index].default_clock_mode =

&rdev->pm.power_state[state_index].clock_info[mode_index - 1];
+   /* patch the table values with 
the default slck/mclk from firmware info */
+   for (j = 0; j < mode_index; 
j++) {
+   
rdev->pm.power_state[state_index].clock_info[j].mclk =
+   
rdev->clock.default_mclk;
+   
rdev->pm.power_state[state_index].clock_info[j].sclk =
+   
rdev->clock.default_sclk;
+   if (vddc)
+   
rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
+   vddc;
+   }
}
state_index++;
}
-- 
1.5.6.3

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[PATCH 4/4] drm: Make sure the DRM offset matches the CPU

[jcro...@codeaurora.org]

From: Jordan Crouse 

The pgoff option in mmap() is defined as an unsigned long
so the offset generated by DRM needs to fit into
BITS_PER_LONG for the CPU in question.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/drm_gem.c |   10 ++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 33dad3f..8601b72 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -68,8 +68,18 @@
  * We make up offsets for buffer objects so we can recognize them at
  * mmap time.
  */
+
+/* pgoff in mmap is an unsigned long, so we need to make sure that
+ * the faked up offset will fit
+ */
+
+#if BITS_PER_LONG == 64
 #define DRM_FILE_PAGE_OFFSET_START ((0xUL >> PAGE_SHIFT) + 1)
 #define DRM_FILE_PAGE_OFFSET_SIZE ((0xUL >> PAGE_SHIFT) * 16)
+#else
+#define DRM_FILE_PAGE_OFFSET_START ((0xFFFUL >> PAGE_SHIFT) + 1)
+#define DRM_FILE_PAGE_OFFSET_SIZE ((0xFFFUL >> PAGE_SHIFT) * 16)
+#endif

 /**
  * Initialize the GEM device fields
-- 
1.7.0.1

[PATCH 3/4] drm: Add __arm defines to DRM

[jcro...@codeaurora.org]

From: Jordan Crouse 

Add __arm defines to specify behavior specific for
an ARM processor.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/drm_bufs.c |2 +-
 drivers/gpu/drm/drm_vm.c   |   14 +-
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 3c2c663..a5c9ce9 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -176,7 +176,7 @@ static int drm_addmap_core(struct drm_device * dev, 
resource_size_t offset,
switch (map->type) {
case _DRM_REGISTERS:
case _DRM_FRAME_BUFFER:
-#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && 
!defined(__powerpc64__) && !defined(__x86_64__)
+#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && 
!defined(__powerpc64__) && !defined(__x86_64__) && !defined(__arm__)
if (map->offset + (map->size-1) < map->offset ||
map->offset < virt_to_phys(high_memory)) {
kfree(map);
diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
index c3b13fb..3778360 100644
--- a/drivers/gpu/drm/drm_vm.c
+++ b/drivers/gpu/drm/drm_vm.c
@@ -61,7 +61,7 @@ static pgprot_t drm_io_prot(uint32_t map_type, struct 
vm_area_struct *vma)
tmp = pgprot_writecombine(tmp);
else
tmp = pgprot_noncached(tmp);
-#elif defined(__sparc__)
+#elif defined(__sparc__) || defined(__arm__)
tmp = pgprot_noncached(tmp);
 #endif
return tmp;
@@ -601,6 +601,7 @@ int drm_mmap_locked(struct file *filp, struct 
vm_area_struct *vma)
}

switch (map->type) {
+#if !defined(__arm__)
case _DRM_AGP:
if (drm_core_has_AGP(dev) && dev->agp->cant_use_aperture) {
/*
@@ -615,20 +616,31 @@ int drm_mmap_locked(struct file *filp, struct 
vm_area_struct *vma)
break;
}
/* fall through to _DRM_FRAME_BUFFER... */
+#endif
case _DRM_FRAME_BUFFER:
case _DRM_REGISTERS:
offset = dev->driver->get_reg_ofs(dev);
vma->vm_flags |= VM_IO; /* not in core dump */
vma->vm_page_prot = drm_io_prot(map->type, vma);
+#if !defined(__arm__)
if (io_remap_pfn_range(vma, vma->vm_start,
   (map->offset + offset) >> PAGE_SHIFT,
   vma->vm_end - vma->vm_start,
   vma->vm_page_prot))
return -EAGAIN;
+#else
+   if (remap_pfn_range(vma, vma->vm_start,
+   (map->offset + offset) >> PAGE_SHIFT,
+   vma->vm_end - vma->vm_start,
+   vma->vm_page_prot))
+   return -EAGAIN;
+#endif
+
DRM_DEBUG("   Type = %d; start = 0x%lx, end = 0x%lx,"
  " offset = 0x%llx\n",
  map->type,
  vma->vm_start, vma->vm_end, (unsigned long 
long)(map->offset + offset));
+
vma->vm_ops = &drm_vm_ops;
break;
case _DRM_CONSISTENT:
-- 
1.7.0.1

[PATCH 2/4] drm: Add support for platform devices to register as DRM devices

[jcro...@codeaurora.org]

From: Jordan Crouse 

Allow platform devices without PCI resources to be DRM devices.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/Kconfig   |4 +-
 drivers/gpu/drm/Makefile  |2 +-
 drivers/gpu/drm/drm_drv.c |   37 +---
 drivers/gpu/drm/drm_edid.c|4 +-
 drivers/gpu/drm/drm_info.c|   23 --
 drivers/gpu/drm/drm_ioctl.c   |   77 --
 drivers/gpu/drm/drm_irq.c |   15 ++--
 drivers/gpu/drm/drm_pci.c |  143 +
 drivers/gpu/drm/drm_platform.c|  122 
 drivers/gpu/drm/drm_stub.c|   89 +
 drivers/gpu/drm/drm_sysfs.c   |3 +-
 drivers/gpu/drm/i915/i915_dma.c   |1 +
 drivers/gpu/drm/i915/i915_drv.c   |2 +-
 drivers/gpu/drm/nouveau/nouveau_drv.c |2 +-
 drivers/gpu/drm/radeon/radeon_drv.c   |2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c   |2 +-
 include/drm/drmP.h|   52 ++--
 17 files changed, 405 insertions(+), 175 deletions(-)
 create mode 100644 drivers/gpu/drm/drm_platform.c

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 88910e5..520ab23 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -6,7 +6,7 @@
 #
 menuconfig DRM
tristate "Direct Rendering Manager (XFree86 4.1.0 and higher DRI 
support)"
-   depends on (AGP || AGP=n) && PCI && !EMULATED_CMPXCHG && MMU
+   depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && MMU
select I2C
select I2C_ALGOBIT
select SLOW_WORK
@@ -17,7 +17,7 @@ menuconfig DRM
  These modules provide support for synchronization, security, and
  DMA transfers. Please see  for more
  details.  You should also select and configure AGP
- (/dev/agpgart) support.
+ (/dev/agpgart) support if it is available for your platform.

 config DRM_KMS_HELPER
tristate
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index abe3f44..b4b2b48 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -9,7 +9,7 @@ drm-y   :=  drm_auth.o drm_buffer.o drm_bufs.o drm_cache.o \
drm_drv.o drm_fops.o drm_gem.o drm_ioctl.o drm_irq.o \
drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \
drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \
-   drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \
+   drm_platform.o drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \
drm_crtc.o drm_modes.o drm_edid.o \
drm_info.o drm_debugfs.o drm_encoder_slave.o

diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 4a66201..510bc87 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -243,47 +243,20 @@ int drm_lastclose(struct drm_device * dev)
  *
  * Initializes an array of drm_device structures, and attempts to
  * initialize all available devices, using consecutive minors, registering the
- * stubs and initializing the AGP device.
+ * stubs and initializing the device.
  *
  * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and
  * after the initialization for driver customization.
  */
 int drm_init(struct drm_driver *driver)
 {
-   struct pci_dev *pdev = NULL;
-   const struct pci_device_id *pid;
-   int i;
-
DRM_DEBUG("\n");
-
INIT_LIST_HEAD(&driver->device_list);

-   if (driver->driver_features & DRIVER_MODESET)
-   return pci_register_driver(&driver->pci_driver);
-
-   /* If not using KMS, fall back to stealth mode manual scanning. */
-   for (i = 0; driver->pci_driver.id_table[i].vendor != 0; i++) {
-   pid = &driver->pci_driver.id_table[i];
-
-   /* Loop around setting up a DRM device for each PCI device
-* matching our ID and device class.  If we had the internal
-* function that pci_get_subsys and pci_get_class used, we'd
-* be able to just pass pid in instead of doing a two-stage
-* thing.
-*/
-   pdev = NULL;
-   while ((pdev =
-   pci_get_subsys(pid->vendor, pid->device, pid->subvendor,
-  pid->subdevice, pdev)) != NULL) {
-   if ((pdev->class & pid->class_mask) != pid->class)
-   continue;
-
-   /* stealth mode requires a manual probe */
-   pci_dev_get(pdev);
-   drm_get_dev(pdev, pid, driver);
-   }
-   }
-   return 0;
+   if (driver->driver_features & DRIVER_USE_PLATFORM_DEVICE)
+   return drm_platform_init(driver);
+   else
+   return drm_pci_init(driver);
 }

 EXPORT_SYMBOL(drm_init);
diff --git a/

[PATCH 1/4] drm: Remove drm_resource wrappers

[jcro...@codeaurora.org]

From: Jordan Crouse 

Remove the drm_resource wrappers and directly use the
actual PCI and/or platform functions in their place.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/drm_bufs.c|   13 -
 drivers/gpu/drm/i915/i915_dma.c   |6 +++---
 drivers/gpu/drm/mga/mga_dma.c |4 ++--
 drivers/gpu/drm/nouveau/nouveau_bo.c  |2 +-
 drivers/gpu/drm/nouveau/nouveau_channel.c |3 ++-
 drivers/gpu/drm/nouveau/nouveau_mem.c |   16 +---
 drivers/gpu/drm/nouveau/nv20_graph.c  |4 ++--
 drivers/gpu/drm/nouveau/nv40_graph.c  |2 +-
 drivers/gpu/drm/nouveau/nv50_instmem.c|3 ++-
 drivers/gpu/drm/radeon/evergreen.c|4 ++--
 drivers/gpu/drm/radeon/r100.c |4 ++--
 drivers/gpu/drm/radeon/r600.c |4 ++--
 drivers/gpu/drm/radeon/radeon_bios.c  |2 +-
 drivers/gpu/drm/radeon/radeon_cp.c|8 
 drivers/gpu/drm/radeon/radeon_device.c|4 ++--
 drivers/gpu/drm/radeon/rs600.c|4 ++--
 drivers/gpu/drm/radeon/rs690.c|4 ++--
 drivers/gpu/drm/radeon/rv770.c|4 ++--
 drivers/gpu/drm/savage/savage_bci.c   |   24 +---
 include/drm/drmP.h|4 
 20 files changed, 54 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 2092e7b..3c2c663 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -39,19 +39,6 @@
 #include 
 #include "drmP.h"

-resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int 
resource)
-{
-   return pci_resource_start(dev->pdev, resource);
-}
-EXPORT_SYMBOL(drm_get_resource_start);
-
-resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int 
resource)
-{
-   return pci_resource_len(dev->pdev, resource);
-}
-
-EXPORT_SYMBOL(drm_get_resource_len);
-
 static struct drm_map_list *drm_find_matching_map(struct drm_device *dev,
  struct drm_local_map *map)
 {
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2a6b5de..9fe2d08 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1429,7 +1429,7 @@ static int i915_load_modeset_init(struct drm_device *dev,
int fb_bar = IS_I9XX(dev) ? 2 : 0;
int ret = 0;

-   dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
+   dev->mode_config.fb_base = pci_resource_start(dev->pdev, fb_bar) &
0xff00;

/* Basic memrange allocator for stolen space (aka vram) */
@@ -1612,8 +1612,8 @@ int i915_driver_load(struct drm_device *dev, unsigned 
long flags)

/* Add register map (needed for suspend/resume) */
mmio_bar = IS_I9XX(dev) ? 0 : 1;
-   base = drm_get_resource_start(dev, mmio_bar);
-   size = drm_get_resource_len(dev, mmio_bar);
+   base = pci_resource_start(dev->pdev, mmio_bar);
+   size = pci_resource_len(dev->pdev, mmio_bar);

if (i915_get_bridge_dev(dev)) {
ret = -EIO;
diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c
index 3c917fb..ccc129c 100644
--- a/drivers/gpu/drm/mga/mga_dma.c
+++ b/drivers/gpu/drm/mga/mga_dma.c
@@ -405,8 +405,8 @@ int mga_driver_load(struct drm_device * dev, unsigned long 
flags)
dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
dev_priv->chipset = flags;

-   dev_priv->mmio_base = drm_get_resource_start(dev, 1);
-   dev_priv->mmio_size = drm_get_resource_len(dev, 1);
+   dev_priv->mmio_base = pci_resource_start(dev->pdev, 1);
+   dev_priv->mmio_size = pci_resource_len(dev->pdev, 1);

dev->counters += 3;
dev->types[6] = _DRM_STAT_IRQ;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 6f3c195..1dad392 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -783,7 +783,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, 
struct ttm_mem_reg *mem)
break;
case TTM_PL_VRAM:
mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
-   mem->bus.base = drm_get_resource_start(dev, 1);
+   man->bus.base = pci_resource_start(dev->pdev, 1);
mem->bus.is_iomem = true;
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c 
b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 1fc57ef..06555c7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -62,7 +62,8 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel 
*chan)
 * VRAM.
 */
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
-drm_get_resource_start(dev, 1),
+  

[PATCH v2] DRM platform device support

[jcro...@codeaurora.org]

Here is the second revision implementing platform device
support for DRM.  I've split the original patch into three
and applied most of the comments I got from the previous
go-around.  The first patch removes the resource wrappers from
DRM and switches the drivers to use the bus level functions.
The second patch adds the platform support, and the third patch
adds the ARM specific #ifdefs.

Plus, a bonus patch that ensures that the DRM offset fits into
the pgoff (unsigned long) offset for mmap.  The original code made
a 64 bit value that didn't fly with a 32 bit processor.

Thanks for the comments and keep em coming.

Jordan

[PATCH]: i915: fix uninitialized variable warning in i915_setup_compression()

[Prarit Bhargava]

Fixes:

drivers/gpu/drm/i915/i915_dma.c: In function ???i915_setup_compression???:
drivers/gpu/drm/i915/i915_dma.c:1311: error: ???compressed_llb??? may be used 
uninitialized in this function

Signed-off-by: Prarit Bhargava 

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4c03ee5..e6a63d1 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1308,7 +1308,7 @@ static void i915_warn_stolen(struct drm_device *dev)
 static void i915_setup_compression(struct drm_device *dev, int size)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
-   struct drm_mm_node *compressed_fb, *compressed_llb;
+   struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
unsigned long cfb_base;
unsigned long ll_base = 0;

Re: Resend: [PATCH 0/2] drm/ttm: A couple of small fixes

[Dave Airlie]

On Thu, 2010-05-27 at 14:14 +0200, Thomas Hellstrom wrote:
> Ping!
> 

Ack!

Should have been in 2.6.34.

Dave.


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[Bug 28284] [r300, r600] celestia core dumps - Assertion `dstRowStride' failed.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=28284

--- Comment #1 from Alex Deucher  2010-05-27 13:10:44 PDT ---
Is this a recent regression?  If so, can you bisect it?  I suspect one of the
recent mipmap patches if so.

-- 
Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email
--- You are receiving this mail because: ---
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[Bug 28284] [r300, r600] celestia core dumps - Assertion `dstRowStride' failed.

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=28284

--- Comment #1 from Alex Deucher  2010-05-27 13:10:44 PDT 
---
Is this a recent regression?  If so, can you bisect it?  I suspect one of the
recent mipmap patches if so.

-- 
Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email
--- You are receiving this mail because: ---
You are the assignee for the bug.

[Bug 28284] New: [r300, r600] celestia core dumps - Assertion `dstRowStride' failed.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=28284

   Summary: [r300, r600] celestia core dumps - Assertion
`dstRowStride' failed.
   Product: Mesa
   Version: git
  Platform: x86 (IA32)
OS/Version: Linux (All)
Status: NEW
  Severity: major
  Priority: medium
 Component: Drivers/DRI/r300
AssignedTo: dri-devel@lists.freedesktop.org
ReportedBy: ranki...@googlemail.com


I am getting the following core dump with my Radeon 9550 and Mesa-git. (My
HD4890 seems affected too.)

Core was generated by `/usr/bin/celestia'.
Program terminated with signal 6, Aborted.
#0  0xb77e7424 in __kernel_vsyscall ()

Thread 1 (Thread 26350):
#0  0xb77e7424 in __kernel_vsyscall ()
No symbol table info available.
#1  0x466c3a81 in raise (sig=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:64
resultvar = 
resultvar = 
pid = 1182830580
selftid = 26350
#2  0x466c534a in abort () at abort.c:92
save_stage = 2
act = {__sigaction_handler = {sa_handler = 0x4680a380 , 
sa_sigaction = 0x4680a380 }, sa_mask = {__val = {
1182830580, 96, 1, 3218383328, 3218383116, 0, 104, 89, 1182835584, 
1182830580, 89, 88, 3218383288, 1181745554, 156360952, 89, 3218383328, 
156360952, 0, 4222451712, 156360952, 156360952, 156360952, 156360952, 
156361040, 156361052, 156360952, 156361052, 0, 0, 0, 0}}, sa_flags = 0, 
  sa_restorer = 0}
sigs = {__val = {32, 0 }}
#3  0x466bcbd8 in __assert_fail (assertion=0xb697b153 "dstRowStride", file=
0xb697b0e8 "radeon_texture.c", line=703, function=
0xb697b1c9 "radeon_store_teximage") at assert.c:81
buf = 
0x951e0f8 "celestia: radeon_texture.c:703: radeon_store_teximage: Assertion
`dstRowStride' failed.\n"
#4  0xb67d5c76 in radeon_store_teximage (ctx=0x91c6288, dims=2, xoffset=0, 
yoffset=0, zoffset=0, width=8, height=8, depth=1, imageSize=0, format=
6407, type=5121, pixels=0x95750d0, packing=0x91d5058, texObj=0x957ad28, 
texImage=0x93a4360, compressed=0) at radeon_texture.c:703
rmesa = 
image = 0x93a4360
dstRowStride = 26350
dstImageOffsets = 
__func__ = "radeon_store_teximage"
__PRETTY_FUNCTION__ = "radeon_store_teximage"
#5  0xb67d62d3 in radeon_teximage (ctx=0x91c6288, dims=2, target=3553, level=
3, internalFormat=3, width=8, height=8, depth=1, imageSize=0, format=
6407, type=5121, pixels=0x95750d0, packing=0x91d5058, texObj=0x957ad28, 
texImage=0x93a4360, compressed=0) at radeon_texture.c:847
rmesa = 0x91c04d8
t = 0x957ad28
image = 0x93a4360
postConvWidth = 8
postConvHeight = 8
face = 0
__func__ = "radeon_teximage"
__PRETTY_FUNCTION__ = "radeon_teximage"
#6  0xb67d67a7 in radeonTexImage2D (ctx=0x91c6288, target=3553, level=3, 
internalFormat=3, width=8, height=8, border=0, format=6407, type=5121, 
pixels=0x95750d0, packing=0x91d5058, texObj=0x957ad28, texImage=0x93a4360)
at radeon_texture.c:880
No locals.
#7  0xb68594bc in _mesa_TexImage2D (target=3553, level=3, 
internalFormat=, width=8, height=8, border=0, format=
6407, type=5121, pixels=0x95750d0) at main/teximage.c:2251
texObj = 0x957ad28
texImage = 
face = 0
postConvWidth = 8
postConvHeight = 8
ctx = 0x91c6288
#8  0xb776718d in gluBuild2DMipmapLevelsCore (target=3553, internalFormat=3, 
width=64, height=64, widthPowerOf2=64, heightPowerOf2=64, format=6407, 
type=5121, userLevel=0, baseLevel=0, maxLevel=6, data=0x95b7988)
at libutil/mipmap.c:4494
rowPad = 
newwidth = 8
newheight = 8
level = 
levels = 6
usersImage = 0xb775cf70
srcImage = 0x95750d0
dstImage = 0x95ba990
tmpImage = 0x95ba990
memreq = 
cmpts = 24
myswap_bytes = 0
groups_per_line = 
element_size = 1
group_size = 3
rowsize = 24
padding = 
psm = {pack_alignment = 4, pack_row_length = 0, pack_skip_rows = 0, 
  pack_skip_pixels = 0, pack_lsb_first = 0, pack_swap_bytes = 0, 
  pack_skip_images = -1076583004, pack_image_height = 3553, 
  unpack_alignment = 4, unpack_row_length = 0, unpack_skip_rows = 0, 
  unpack_skip_pixels = 0, unpack_lsb_first = 0, unpack_swap_bytes = 
0, unpack_skip_images = 32, unpack_image_height = 32}
#9  0xb776e8bb in gluBuild2DMipmaps (target=3553, internalFormat=3, width=64, 
height=64, format=6407, type=5121, data=0x95b7988)
at libutil/mipmap.c:4606
widthPowerOf2 = 64
heightPowerOf2 = 64
level = 26350
levels = 
rc = 
#10 0x081699fe in ImageTexture::ImageTexture(Image&, Texture::AddressMode,
Texture::MipMapMode) ()
No symbol table info available.
#11 0x08169dbe in CreateProceduralTexture(int, int, int, void (*)(float, float,
float

[Bug 28284] New: [r300, r600] celestia core dumps - Assertion `dstRowStride' failed.

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=28284

   Summary: [r300, r600] celestia core dumps - Assertion
`dstRowStride' failed.
   Product: Mesa
   Version: git
  Platform: x86 (IA32)
OS/Version: Linux (All)
Status: NEW
  Severity: major
  Priority: medium
 Component: Drivers/DRI/r300
AssignedTo: dri-devel at lists.freedesktop.org
ReportedBy: rankincj at googlemail.com


I am getting the following core dump with my Radeon 9550 and Mesa-git. (My
HD4890 seems affected too.)

Core was generated by `/usr/bin/celestia'.
Program terminated with signal 6, Aborted.
#0  0xb77e7424 in __kernel_vsyscall ()

Thread 1 (Thread 26350):
#0  0xb77e7424 in __kernel_vsyscall ()
No symbol table info available.
#1  0x466c3a81 in raise (sig=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:64
resultvar = 
resultvar = 
pid = 1182830580
selftid = 26350
#2  0x466c534a in abort () at abort.c:92
save_stage = 2
act = {__sigaction_handler = {sa_handler = 0x4680a380 , 
sa_sigaction = 0x4680a380 }, sa_mask = {__val = {
1182830580, 96, 1, 3218383328, 3218383116, 0, 104, 89, 1182835584, 
1182830580, 89, 88, 3218383288, 1181745554, 156360952, 89, 3218383328, 
156360952, 0, 4222451712, 156360952, 156360952, 156360952, 156360952, 
156361040, 156361052, 156360952, 156361052, 0, 0, 0, 0}}, sa_flags = 0, 
  sa_restorer = 0}
sigs = {__val = {32, 0 }}
#3  0x466bcbd8 in __assert_fail (assertion=0xb697b153 "dstRowStride", file=
0xb697b0e8 "radeon_texture.c", line=703, function=
0xb697b1c9 "radeon_store_teximage") at assert.c:81
buf = 
0x951e0f8 "celestia: radeon_texture.c:703: radeon_store_teximage: Assertion
`dstRowStride' failed.\n"
#4  0xb67d5c76 in radeon_store_teximage (ctx=0x91c6288, dims=2, xoffset=0, 
yoffset=0, zoffset=0, width=8, height=8, depth=1, imageSize=0, format=
6407, type=5121, pixels=0x95750d0, packing=0x91d5058, texObj=0x957ad28, 
texImage=0x93a4360, compressed=0) at radeon_texture.c:703
rmesa = 
image = 0x93a4360
dstRowStride = 26350
dstImageOffsets = 
__func__ = "radeon_store_teximage"
__PRETTY_FUNCTION__ = "radeon_store_teximage"
#5  0xb67d62d3 in radeon_teximage (ctx=0x91c6288, dims=2, target=3553, level=
3, internalFormat=3, width=8, height=8, depth=1, imageSize=0, format=
6407, type=5121, pixels=0x95750d0, packing=0x91d5058, texObj=0x957ad28, 
texImage=0x93a4360, compressed=0) at radeon_texture.c:847
rmesa = 0x91c04d8
t = 0x957ad28
image = 0x93a4360
postConvWidth = 8
postConvHeight = 8
face = 0
__func__ = "radeon_teximage"
__PRETTY_FUNCTION__ = "radeon_teximage"
#6  0xb67d67a7 in radeonTexImage2D (ctx=0x91c6288, target=3553, level=3, 
internalFormat=3, width=8, height=8, border=0, format=6407, type=5121, 
pixels=0x95750d0, packing=0x91d5058, texObj=0x957ad28, texImage=0x93a4360)
at radeon_texture.c:880
No locals.
#7  0xb68594bc in _mesa_TexImage2D (target=3553, level=3, 
internalFormat=, width=8, height=8, border=0, format=
6407, type=5121, pixels=0x95750d0) at main/teximage.c:2251
texObj = 0x957ad28
texImage = 
face = 0
postConvWidth = 8
postConvHeight = 8
ctx = 0x91c6288
#8  0xb776718d in gluBuild2DMipmapLevelsCore (target=3553, internalFormat=3, 
width=64, height=64, widthPowerOf2=64, heightPowerOf2=64, format=6407, 
type=5121, userLevel=0, baseLevel=0, maxLevel=6, data=0x95b7988)
at libutil/mipmap.c:4494
rowPad = 
newwidth = 8
newheight = 8
level = 
levels = 6
usersImage = 0xb775cf70
srcImage = 0x95750d0
dstImage = 0x95ba990
tmpImage = 0x95ba990
memreq = 
cmpts = 24
myswap_bytes = 0
groups_per_line = 
element_size = 1
group_size = 3
rowsize = 24
padding = 
psm = {pack_alignment = 4, pack_row_length = 0, pack_skip_rows = 0, 
  pack_skip_pixels = 0, pack_lsb_first = 0, pack_swap_bytes = 0, 
  pack_skip_images = -1076583004, pack_image_height = 3553, 
  unpack_alignment = 4, unpack_row_length = 0, unpack_skip_rows = 0, 
  unpack_skip_pixels = 0, unpack_lsb_first = 0, unpack_swap_bytes = 
0, unpack_skip_images = 32, unpack_image_height = 32}
#9  0xb776e8bb in gluBuild2DMipmaps (target=3553, internalFormat=3, width=64, 
height=64, format=6407, type=5121, data=0x95b7988)
at libutil/mipmap.c:4606
widthPowerOf2 = 64
heightPowerOf2 = 64
level = 26350
levels = 
rc = 
#10 0x081699fe in ImageTexture::ImageTexture(Image&, Texture::AddressMode,
Texture::MipMapMode) ()
No symbol table info available.
#11 0x08169dbe in CreateProceduralTexture(int, int, int, void (*)(float, float,

[PATCH 2/4] drm: Add support for platform devices to register as DRM devices

[jcrouse]

From: Jordan Crouse 

Allow platform devices without PCI resources to be DRM devices.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/Kconfig   |4 +-
 drivers/gpu/drm/Makefile  |2 +-
 drivers/gpu/drm/drm_drv.c |   37 +---
 drivers/gpu/drm/drm_edid.c|4 +-
 drivers/gpu/drm/drm_info.c|   23 --
 drivers/gpu/drm/drm_ioctl.c   |   77 --
 drivers/gpu/drm/drm_irq.c |   15 ++--
 drivers/gpu/drm/drm_pci.c |  143 +
 drivers/gpu/drm/drm_platform.c|  122 
 drivers/gpu/drm/drm_stub.c|   89 +
 drivers/gpu/drm/drm_sysfs.c   |3 +-
 drivers/gpu/drm/i915/i915_dma.c   |1 +
 drivers/gpu/drm/i915/i915_drv.c   |2 +-
 drivers/gpu/drm/nouveau/nouveau_drv.c |2 +-
 drivers/gpu/drm/radeon/radeon_drv.c   |2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c   |2 +-
 include/drm/drmP.h|   52 ++--
 17 files changed, 405 insertions(+), 175 deletions(-)
 create mode 100644 drivers/gpu/drm/drm_platform.c

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 88910e5..520ab23 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -6,7 +6,7 @@
 #
 menuconfig DRM
tristate "Direct Rendering Manager (XFree86 4.1.0 and higher DRI 
support)"
-   depends on (AGP || AGP=n) && PCI && !EMULATED_CMPXCHG && MMU
+   depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && MMU
select I2C
select I2C_ALGOBIT
select SLOW_WORK
@@ -17,7 +17,7 @@ menuconfig DRM
  These modules provide support for synchronization, security, and
  DMA transfers. Please see  for more
  details.  You should also select and configure AGP
- (/dev/agpgart) support.
+ (/dev/agpgart) support if it is available for your platform.
 
 config DRM_KMS_HELPER
tristate
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index abe3f44..b4b2b48 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -9,7 +9,7 @@ drm-y   :=  drm_auth.o drm_buffer.o drm_bufs.o drm_cache.o \
drm_drv.o drm_fops.o drm_gem.o drm_ioctl.o drm_irq.o \
drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \
drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \
-   drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \
+   drm_platform.o drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \
drm_crtc.o drm_modes.o drm_edid.o \
drm_info.o drm_debugfs.o drm_encoder_slave.o
 
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 4a66201..510bc87 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -243,47 +243,20 @@ int drm_lastclose(struct drm_device * dev)
  *
  * Initializes an array of drm_device structures, and attempts to
  * initialize all available devices, using consecutive minors, registering the
- * stubs and initializing the AGP device.
+ * stubs and initializing the device.
  *
  * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and
  * after the initialization for driver customization.
  */
 int drm_init(struct drm_driver *driver)
 {
-   struct pci_dev *pdev = NULL;
-   const struct pci_device_id *pid;
-   int i;
-
DRM_DEBUG("\n");
-
INIT_LIST_HEAD(&driver->device_list);
 
-   if (driver->driver_features & DRIVER_MODESET)
-   return pci_register_driver(&driver->pci_driver);
-
-   /* If not using KMS, fall back to stealth mode manual scanning. */
-   for (i = 0; driver->pci_driver.id_table[i].vendor != 0; i++) {
-   pid = &driver->pci_driver.id_table[i];
-
-   /* Loop around setting up a DRM device for each PCI device
-* matching our ID and device class.  If we had the internal
-* function that pci_get_subsys and pci_get_class used, we'd
-* be able to just pass pid in instead of doing a two-stage
-* thing.
-*/
-   pdev = NULL;
-   while ((pdev =
-   pci_get_subsys(pid->vendor, pid->device, pid->subvendor,
-  pid->subdevice, pdev)) != NULL) {
-   if ((pdev->class & pid->class_mask) != pid->class)
-   continue;
-
-   /* stealth mode requires a manual probe */
-   pci_dev_get(pdev);
-   drm_get_dev(pdev, pid, driver);
-   }
-   }
-   return 0;
+   if (driver->driver_features & DRIVER_USE_PLATFORM_DEVICE)
+   return drm_platform_init(driver);
+   else
+   return drm_pci_init(driver);
 }
 
 EXPORT_SYMBOL(drm_init);
diff --gi

[PATCH 3/4] drm: Add __arm defines to DRM

[jcrouse]

From: Jordan Crouse 

Add __arm defines to specify behavior specific for
an ARM processor.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/drm_bufs.c |2 +-
 drivers/gpu/drm/drm_vm.c   |   14 +-
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 3c2c663..a5c9ce9 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -176,7 +176,7 @@ static int drm_addmap_core(struct drm_device * dev, 
resource_size_t offset,
switch (map->type) {
case _DRM_REGISTERS:
case _DRM_FRAME_BUFFER:
-#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && 
!defined(__powerpc64__) && !defined(__x86_64__)
+#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && 
!defined(__powerpc64__) && !defined(__x86_64__) && !defined(__arm__)
if (map->offset + (map->size-1) < map->offset ||
map->offset < virt_to_phys(high_memory)) {
kfree(map);
diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
index c3b13fb..3778360 100644
--- a/drivers/gpu/drm/drm_vm.c
+++ b/drivers/gpu/drm/drm_vm.c
@@ -61,7 +61,7 @@ static pgprot_t drm_io_prot(uint32_t map_type, struct 
vm_area_struct *vma)
tmp = pgprot_writecombine(tmp);
else
tmp = pgprot_noncached(tmp);
-#elif defined(__sparc__)
+#elif defined(__sparc__) || defined(__arm__)
tmp = pgprot_noncached(tmp);
 #endif
return tmp;
@@ -601,6 +601,7 @@ int drm_mmap_locked(struct file *filp, struct 
vm_area_struct *vma)
}
 
switch (map->type) {
+#if !defined(__arm__)
case _DRM_AGP:
if (drm_core_has_AGP(dev) && dev->agp->cant_use_aperture) {
/*
@@ -615,20 +616,31 @@ int drm_mmap_locked(struct file *filp, struct 
vm_area_struct *vma)
break;
}
/* fall through to _DRM_FRAME_BUFFER... */
+#endif
case _DRM_FRAME_BUFFER:
case _DRM_REGISTERS:
offset = dev->driver->get_reg_ofs(dev);
vma->vm_flags |= VM_IO; /* not in core dump */
vma->vm_page_prot = drm_io_prot(map->type, vma);
+#if !defined(__arm__)
if (io_remap_pfn_range(vma, vma->vm_start,
   (map->offset + offset) >> PAGE_SHIFT,
   vma->vm_end - vma->vm_start,
   vma->vm_page_prot))
return -EAGAIN;
+#else
+   if (remap_pfn_range(vma, vma->vm_start,
+   (map->offset + offset) >> PAGE_SHIFT,
+   vma->vm_end - vma->vm_start,
+   vma->vm_page_prot))
+   return -EAGAIN;
+#endif
+
DRM_DEBUG("   Type = %d; start = 0x%lx, end = 0x%lx,"
  " offset = 0x%llx\n",
  map->type,
  vma->vm_start, vma->vm_end, (unsigned long 
long)(map->offset + offset));
+
vma->vm_ops = &drm_vm_ops;
break;
case _DRM_CONSISTENT:
-- 
1.7.0.1

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[PATCH v2] DRM platform device support

[jcrouse]

Here is the second revision implementing platform device
support for DRM.  I've split the original patch into three
and applied most of the comments I got from the previous
go-around.  The first patch removes the resource wrappers from
DRM and switches the drivers to use the bus level functions.
The second patch adds the platform support, and the third patch
adds the ARM specific #ifdefs.

Plus, a bonus patch that ensures that the DRM offset fits into
the pgoff (unsigned long) offset for mmap.  The original code made
a 64 bit value that didn't fly with a 32 bit processor.

Thanks for the comments and keep em coming.

Jordan
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[PATCH 1/4] drm: Remove drm_resource wrappers

[jcrouse]

From: Jordan Crouse 

Remove the drm_resource wrappers and directly use the
actual PCI and/or platform functions in their place.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/drm_bufs.c|   13 -
 drivers/gpu/drm/i915/i915_dma.c   |6 +++---
 drivers/gpu/drm/mga/mga_dma.c |4 ++--
 drivers/gpu/drm/nouveau/nouveau_bo.c  |2 +-
 drivers/gpu/drm/nouveau/nouveau_channel.c |3 ++-
 drivers/gpu/drm/nouveau/nouveau_mem.c |   16 +---
 drivers/gpu/drm/nouveau/nv20_graph.c  |4 ++--
 drivers/gpu/drm/nouveau/nv40_graph.c  |2 +-
 drivers/gpu/drm/nouveau/nv50_instmem.c|3 ++-
 drivers/gpu/drm/radeon/evergreen.c|4 ++--
 drivers/gpu/drm/radeon/r100.c |4 ++--
 drivers/gpu/drm/radeon/r600.c |4 ++--
 drivers/gpu/drm/radeon/radeon_bios.c  |2 +-
 drivers/gpu/drm/radeon/radeon_cp.c|8 
 drivers/gpu/drm/radeon/radeon_device.c|4 ++--
 drivers/gpu/drm/radeon/rs600.c|4 ++--
 drivers/gpu/drm/radeon/rs690.c|4 ++--
 drivers/gpu/drm/radeon/rv770.c|4 ++--
 drivers/gpu/drm/savage/savage_bci.c   |   24 +---
 include/drm/drmP.h|4 
 20 files changed, 54 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 2092e7b..3c2c663 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -39,19 +39,6 @@
 #include 
 #include "drmP.h"
 
-resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int 
resource)
-{
-   return pci_resource_start(dev->pdev, resource);
-}
-EXPORT_SYMBOL(drm_get_resource_start);
-
-resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int 
resource)
-{
-   return pci_resource_len(dev->pdev, resource);
-}
-
-EXPORT_SYMBOL(drm_get_resource_len);
-
 static struct drm_map_list *drm_find_matching_map(struct drm_device *dev,
  struct drm_local_map *map)
 {
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2a6b5de..9fe2d08 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1429,7 +1429,7 @@ static int i915_load_modeset_init(struct drm_device *dev,
int fb_bar = IS_I9XX(dev) ? 2 : 0;
int ret = 0;
 
-   dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
+   dev->mode_config.fb_base = pci_resource_start(dev->pdev, fb_bar) &
0xff00;
 
/* Basic memrange allocator for stolen space (aka vram) */
@@ -1612,8 +1612,8 @@ int i915_driver_load(struct drm_device *dev, unsigned 
long flags)
 
/* Add register map (needed for suspend/resume) */
mmio_bar = IS_I9XX(dev) ? 0 : 1;
-   base = drm_get_resource_start(dev, mmio_bar);
-   size = drm_get_resource_len(dev, mmio_bar);
+   base = pci_resource_start(dev->pdev, mmio_bar);
+   size = pci_resource_len(dev->pdev, mmio_bar);
 
if (i915_get_bridge_dev(dev)) {
ret = -EIO;
diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c
index 3c917fb..ccc129c 100644
--- a/drivers/gpu/drm/mga/mga_dma.c
+++ b/drivers/gpu/drm/mga/mga_dma.c
@@ -405,8 +405,8 @@ int mga_driver_load(struct drm_device * dev, unsigned long 
flags)
dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
dev_priv->chipset = flags;
 
-   dev_priv->mmio_base = drm_get_resource_start(dev, 1);
-   dev_priv->mmio_size = drm_get_resource_len(dev, 1);
+   dev_priv->mmio_base = pci_resource_start(dev->pdev, 1);
+   dev_priv->mmio_size = pci_resource_len(dev->pdev, 1);
 
dev->counters += 3;
dev->types[6] = _DRM_STAT_IRQ;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c 
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 6f3c195..1dad392 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -783,7 +783,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, 
struct ttm_mem_reg *mem)
break;
case TTM_PL_VRAM:
mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
-   mem->bus.base = drm_get_resource_start(dev, 1);
+   man->bus.base = pci_resource_start(dev->pdev, 1);
mem->bus.is_iomem = true;
break;
default:
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c 
b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 1fc57ef..06555c7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -62,7 +62,8 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel 
*chan)
 * VRAM.
 */
ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
-drm_get_resource_start(dev, 1),
+   

[PATCH 4/4] drm: Make sure the DRM offset matches the CPU

[jcrouse]

From: Jordan Crouse 

The pgoff option in mmap() is defined as an unsigned long
so the offset generated by DRM needs to fit into
BITS_PER_LONG for the CPU in question.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/drm_gem.c |   10 ++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 33dad3f..8601b72 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -68,8 +68,18 @@
  * We make up offsets for buffer objects so we can recognize them at
  * mmap time.
  */
+
+/* pgoff in mmap is an unsigned long, so we need to make sure that
+ * the faked up offset will fit
+ */
+
+#if BITS_PER_LONG == 64
 #define DRM_FILE_PAGE_OFFSET_START ((0xUL >> PAGE_SHIFT) + 1)
 #define DRM_FILE_PAGE_OFFSET_SIZE ((0xUL >> PAGE_SHIFT) * 16)
+#else
+#define DRM_FILE_PAGE_OFFSET_START ((0xFFFUL >> PAGE_SHIFT) + 1)
+#define DRM_FILE_PAGE_OFFSET_SIZE ((0xFFFUL >> PAGE_SHIFT) * 16)
+#endif
 
 /**
  * Initialize the GEM device fields
-- 
1.7.0.1

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[PATCH]: i915: Fix missing linux/types.h warning in header

[Prarit Bhargava]

>
> Prarit Bhargava wrote:
>
>> Fixes warning:
>>
>> /usr/include/drm/i915_drm.h:119: found __[us]{8,16,32,64} type without 
>> #include
>>
>> Signed-off-by: Prarit Bhargava
>>
>> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
>> index b64a8d7..5cf7f5b 100644
>> --- a/include/drm/i915_drm.h
>> +++ b/include/drm/i915_drm.h
>> @@ -27,6 +27,7 @@
>>   #ifndef _I915_DRM_H_
>>   #define _I915_DRM_H_
>>
>> +#include
>>   #include "drm.h"
>>  
> drm.h includes it, safely tucked inside #ifdef __linux__ so it won't
> break BSD&  OpenSolaris DRI builds - isn't that good enough?
>

Hmm ... it doesn't appear to be :/  From a week-old compile of linux-next

/home/linux-next/usr/include/drm/drm_mode.h:84: found __[us]{8,16,32,64} 
type without #include 
/home/linux-next/usr/include/drm/i915_drm.h:119: found 
__[us]{8,16,32,64} type without #include 
/home/linux-next/usr/include/drm/mga_drm.h:260: found __[us]{8,16,32,64} 
type without #include 
/home/linux-next/usr/include/drm/radeon_drm.h:758: found 
__[us]{8,16,32,64} type without #include 
/home/linux-next/usr/include/drm/via_drm.h:117: found __[us]{8,16,32,64} 
type without #include 

It could certainly be that the error check is busted ...

P.
>

[PATCH]: i915: Fix missing linux/types.h warning in header

[Prarit Bhargava]

Fixes warning:

/usr/include/drm/i915_drm.h:119: found __[us]{8,16,32,64} type without #include 


Signed-off-by: Prarit Bhargava 

diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index b64a8d7..5cf7f5b 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -27,6 +27,7 @@
 #ifndef _I915_DRM_H_
 #define _I915_DRM_H_

+#include 
 #include "drm.h"

 /* Please note that modifications to all structs defined here are

[PATCH 1/3] r600: add span support for 2D tiling

[Alex Deucher]

On Thu, May 27, 2010 at 10:55 AM, Matt Turner  wrote:
>> +static inline GLint r600_log2(GLint n)
>> +{
>> + ? ? ? GLint log2 = 0;
>> +
>> + ? ? ? while (n >>= 1)
>> + ? ? ? ? ? ? ? ++log2;
>> + ? ? ? return log2;
>> +}
>
> Does mesa not provide something like this?

The only one I could find was a gallium utility function.

Alex

[PATCH 0/5] Add tiling support for r6xx/r7xx

[Michel Dänzer]

On Die, 2010-05-25 at 19:09 -0400, Alex Deucher wrote: 
> 
> Also, on r6xx/r7xx, we don't enable tiling of the front buffer as
> that would require the use of wfb or tiled to untiled blits for CPU
> access. Tiled to untiled blits works (I've tested it), but shows an
> approximately 40% performance hit for software fallbacks (tested with
> non-aa text in x11perf).  I'm not sure what how that compared to sw
> detiling with wfb since the algo is pretty complex.  In practice, I
> didn't notice any difference in performance on the desktop.

How exactly did you implement the (un)tiling blits? I'd suggest doing it
similarly to the way we're handling byte swapping with KMS on big endian
machines: return FALSE from the PrepareAccess hook and handle the
(un)tiling in the DownloadFrom/UploadToScreen hooks.

In my experience, wfb is excruciatingly inefficient (one callback per
byte in the worst case).


-- 
Earthling Michel D?nzer   |http://www.vmware.com
Libre software enthusiast |  Debian, X and DRI developer

[PATCH 0/5] Add tiling support for r6xx/r7xx

[Alex Deucher]

2010/5/27 Michel D?nzer :
> On Die, 2010-05-25 at 19:09 -0400, Alex Deucher wrote:
>>
>> Also, on r6xx/r7xx, we don't enable tiling of the front buffer as
>> that would require the use of wfb or tiled to untiled blits for CPU
>> access. Tiled to untiled blits works (I've tested it), but shows an
>> approximately 40% performance hit for software fallbacks (tested with
>> non-aa text in x11perf). ?I'm not sure what how that compared to sw
>> detiling with wfb since the algo is pretty complex. ?In practice, I
>> didn't notice any difference in performance on the desktop.
>
> How exactly did you implement the (un)tiling blits? I'd suggest doing it
> similarly to the way we're handling byte swapping with KMS on big endian
> machines: return FALSE from the PrepareAccess hook and handle the
> (un)tiling in the DownloadFrom/UploadToScreen hooks.
>

I used that exact method.

> In my experience, wfb is excruciatingly inefficient (one callback per
> byte in the worst case).

It's horrible.  There's also no way to handle multiple cards sanely as
there's nothing to attach a driver priv to.

Alex

>
>
> --
> Earthling Michel D?nzer ? ? ? ? ? | ? ? ? ? ? ? ? ?http://www.vmware.com
> Libre software enthusiast ? ? ? ? | ? ? ? ? ?Debian, X and DRI developer
>

[PATCH 1/3] r600: add span support for 2D tiling

[Matt Turner]

> +static inline GLint r600_log2(GLint n)
> +{
> + ? ? ? GLint log2 = 0;
> +
> + ? ? ? while (n >>= 1)
> + ? ? ? ? ? ? ? ++log2;
> + ? ? ? return log2;
> +}

Does mesa not provide something like this?

Matt

[PATCH]: i915: fix uninitialized variable warning in i915_setup_compression()

[Prarit Bhargava]

Fixes:

drivers/gpu/drm/i915/i915_dma.c: In function ‘i915_setup_compression’:
drivers/gpu/drm/i915/i915_dma.c:1311: error: ‘compressed_llb’ may be used 
uninitialized in this function

Signed-off-by: Prarit Bhargava 

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4c03ee5..e6a63d1 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1308,7 +1308,7 @@ static void i915_warn_stolen(struct drm_device *dev)
 static void i915_setup_compression(struct drm_device *dev, int size)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
-   struct drm_mm_node *compressed_fb, *compressed_llb;
+   struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
unsigned long cfb_base;
unsigned long ll_base = 0;
 
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[PATCH 1/3] r600: add span support for 2D tiling

[Frieder Ferlemann]

Hi Alex,

not tested (admittedly I haven't compiled it),
and probably not really relevant but these
switch cases could be more compact:

+static inline GLint r600_2d_tile_helper(const struct radeon_renderbuffer * rrb,
+GLint x, GLint y, GLint is_depth, GLint is_stencil)

...

+switch (element_bytes) {
+case 1:
+pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1]
+pixel_number |= ((x >> 2) & 1) << 2; // pn[2] = x[2]
+pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1]
+pixel_number |= ((y >> 0) & 1) << 4; // pn[4] = y[0]
+pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+break;
+case 2:
+pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1]
+pixel_number |= ((x >> 2) & 1) << 2; // pn[2] = x[2]
+pixel_number |= ((y >> 0) & 1) << 3; // pn[3] = y[0]
+pixel_number |= ((y >> 1) & 1) << 4; // pn[4] = y[1]
+pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+break;
+case 4:
+pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1]
+pixel_number |= ((y >> 0) & 1) << 2; // pn[2] = y[0]
+pixel_number |= ((x >> 2) & 1) << 3; // pn[3] = x[2]
+pixel_number |= ((y >> 1) & 1) << 4; // pn[4] = y[1]
+pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+break;
+}


when using 

+switch (element_bytes) {
+case 1:
+pixel_number |= (x & 0x07) << 0;  // pn[0] = x[0], pn[1] = 
x[1], pn[2] = x[2]
+pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1]
+pixel_number |= ((y >> 0) & 1) << 4; // pn[4] = y[0]
+pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+break;
+case 2:
+pixel_number |= (x & 0x07) << 0; // pn[0] = x[0], pn[1] = 
x[1], pn[2] = x[2]
+pixel_number |= (y & 0x07) << 3; // pn[3] = y[0], pn[4] = 
y[1], pn[5] = y[2]
+break;
+case 4:
+pixel_number |= (x & 0x03) << 0; // pn[0] = x[0], pn[1] = x[1]
+pixel_number |= (y & 0x01) << 2; // pn[2] = y[0]
+pixel_number |= (x & 0x04) << 1; // pn[3] = x[2]
+pixel_number |= (y & 0x06) << 3; // pn[4] = y[1], pn[5] = y[2]
+break;
+}

Greetings,
Frieder
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[PATCH 1/3] r600: add span support for 2D tiling

[Brian Paul]

Alex Deucher wrote:
> On Thu, May 27, 2010 at 10:55 AM, Matt Turner  wrote:
>>> +static inline GLint r600_log2(GLint n)
>>> +{
>>> +   GLint log2 = 0;
>>> +
>>> +   while (n >>= 1)
>>> +   ++log2;
>>> +   return log2;
>>> +}
>> Does mesa not provide something like this?
> 
> The only one I could find was a gallium utility function.

There's a logbase2() function in teximage.c but it might not be 
equivalent.

-Brian

Re: [PATCH 1/3] r600: add span support for 2D tiling

[Brian Paul]

Alex Deucher wrote:

On Thu, May 27, 2010 at 10:55 AM, Matt Turner  wrote:

+static inline GLint r600_log2(GLint n)
+{
+   GLint log2 = 0;
+
+   while (n >>= 1)
+   ++log2;
+   return log2;
+}

Does mesa not provide something like this?


The only one I could find was a gallium utility function.


There's a logbase2() function in teximage.c but it might not be 
equivalent.


-Brian

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Re: [PATCH]: i915: Fix missing linux/types.h warning in header

[Prarit Bhargava]

Prarit Bhargava wrote:
   

Fixes warning:

/usr/include/drm/i915_drm.h:119: found __[us]{8,16,32,64} type without 
#include

Signed-off-by: Prarit Bhargava

diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index b64a8d7..5cf7f5b 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -27,6 +27,7 @@
  #ifndef _I915_DRM_H_
  #define _I915_DRM_H_

+#include
  #include "drm.h"
 

drm.h includes it, safely tucked inside #ifdef __linux__ so it won't
break BSD&  OpenSolaris DRI builds - isn't that good enough?
   


Hmm ... it doesn't appear to be :/  From a week-old compile of linux-next

/home/linux-next/usr/include/drm/drm_mode.h:84: found __[us]{8,16,32,64} 
type without #include 
/home/linux-next/usr/include/drm/i915_drm.h:119: found 
__[us]{8,16,32,64} type without #include 
/home/linux-next/usr/include/drm/mga_drm.h:260: found __[us]{8,16,32,64} 
type without #include 
/home/linux-next/usr/include/drm/radeon_drm.h:758: found 
__[us]{8,16,32,64} type without #include 
/home/linux-next/usr/include/drm/via_drm.h:117: found __[us]{8,16,32,64} 
type without #include 


It could certainly be that the error check is busted ...

P.
   

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Re: [PATCH]: i915: Fix missing linux/types.h warning in header

[Alan Coopersmith]

Prarit Bhargava wrote:
> Fixes warning:
> 
> /usr/include/drm/i915_drm.h:119: found __[us]{8,16,32,64} type without 
> #include 
> 
> Signed-off-by: Prarit Bhargava 
> 
> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> index b64a8d7..5cf7f5b 100644
> --- a/include/drm/i915_drm.h
> +++ b/include/drm/i915_drm.h
> @@ -27,6 +27,7 @@
>  #ifndef _I915_DRM_H_
>  #define _I915_DRM_H_
>  
> +#include 
>  #include "drm.h"

drm.h includes it, safely tucked inside #ifdef __linux__ so it won't
break BSD & OpenSolaris DRI builds - isn't that good enough?

-- 
-Alan Coopersmith-alan.coopersm...@oracle.com
 Oracle Solaris Platform Engineering: X Window System

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Re: [PATCH 1/3] r600: add span support for 2D tiling

[Alan Cox]

On Thu, 27 May 2010 11:20:59 -0400
Alex Deucher  wrote:

> On Thu, May 27, 2010 at 10:55 AM, Matt Turner  wrote:
> >> +static inline GLint r600_log2(GLint n)
> >> +{
> >> +       GLint log2 = 0;
> >> +
> >> +       while (n >>= 1)
> >> +               ++log2;
> >> +       return log2;
> >> +}
> >
> > Does mesa not provide something like this?
> 
> The only one I could find was a gallium utility function.

include/linux/log2.h

The original is from Red Hat so if you need it non GPL maybe Red Hat can
help ?
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[PATCH]: i915: Fix missing linux/types.h warning in header

[Alan Coopersmith]

Prarit Bhargava wrote:
> Fixes warning:
> 
> /usr/include/drm/i915_drm.h:119: found __[us]{8,16,32,64} type without 
> #include 
> 
> Signed-off-by: Prarit Bhargava 
> 
> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> index b64a8d7..5cf7f5b 100644
> --- a/include/drm/i915_drm.h
> +++ b/include/drm/i915_drm.h
> @@ -27,6 +27,7 @@
>  #ifndef _I915_DRM_H_
>  #define _I915_DRM_H_
>  
> +#include 
>  #include "drm.h"

drm.h includes it, safely tucked inside #ifdef __linux__ so it won't
break BSD & OpenSolaris DRI builds - isn't that good enough?

-- 
-Alan Coopersmith-alan.coopersmith at oracle.com
 Oracle Solaris Platform Engineering: X Window System

[PATCH]: i915: Fix missing linux/types.h warning in header

[Prarit Bhargava]

Fixes warning:

/usr/include/drm/i915_drm.h:119: found __[us]{8,16,32,64} type without #include 


Signed-off-by: Prarit Bhargava 

diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index b64a8d7..5cf7f5b 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -27,6 +27,7 @@
 #ifndef _I915_DRM_H_
 #define _I915_DRM_H_
 
+#include 
 #include "drm.h"
 
 /* Please note that modifications to all structs defined here are
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Re: [PATCH 1/3] r600: add span support for 2D tiling

[Alex Deucher]

On Thu, May 27, 2010 at 10:55 AM, Matt Turner  wrote:
>> +static inline GLint r600_log2(GLint n)
>> +{
>> +       GLint log2 = 0;
>> +
>> +       while (n >>= 1)
>> +               ++log2;
>> +       return log2;
>> +}
>
> Does mesa not provide something like this?

The only one I could find was a gallium utility function.

Alex
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Re: [PATCH 0/5] Add tiling support for r6xx/r7xx

[Alex Deucher]

2010/5/27 Michel Dänzer :
> On Die, 2010-05-25 at 19:09 -0400, Alex Deucher wrote:
>>
>> Also, on r6xx/r7xx, we don't enable tiling of the front buffer as
>> that would require the use of wfb or tiled to untiled blits for CPU
>> access. Tiled to untiled blits works (I've tested it), but shows an
>> approximately 40% performance hit for software fallbacks (tested with
>> non-aa text in x11perf).  I'm not sure what how that compared to sw
>> detiling with wfb since the algo is pretty complex.  In practice, I
>> didn't notice any difference in performance on the desktop.
>
> How exactly did you implement the (un)tiling blits? I'd suggest doing it
> similarly to the way we're handling byte swapping with KMS on big endian
> machines: return FALSE from the PrepareAccess hook and handle the
> (un)tiling in the DownloadFrom/UploadToScreen hooks.
>

I used that exact method.

> In my experience, wfb is excruciatingly inefficient (one callback per
> byte in the worst case).

It's horrible.  There's also no way to handle multiple cards sanely as
there's nothing to attach a driver priv to.

Alex

>
>
> --
> Earthling Michel Dänzer           |                http://www.vmware.com
> Libre software enthusiast         |          Debian, X and DRI developer
>
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Re: [PATCH 1/3] r600: add span support for 2D tiling

[Matt Turner]

> +static inline GLint r600_log2(GLint n)
> +{
> +       GLint log2 = 0;
> +
> +       while (n >>= 1)
> +               ++log2;
> +       return log2;
> +}

Does mesa not provide something like this?

Matt
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Resend: [PATCH 0/2] drm/ttm: A couple of small fixes

[Thomas Hellstrom]

Ping!

On 04/28/2010 11:33 AM, Thomas Hellstrom wrote:

The first patch removes some leftover debug messages in the ttm_lock code
so far only used by the vmwgfx driver.

The second patch removes the ttm_bo_block_reservation() function, since
it is buggy. A bo shouldn't be reserved while remaining on lru lists.

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/Thomas

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Re: [PATCH 0/5] Add tiling support for r6xx/r7xx

[Michel Dänzer]

On Die, 2010-05-25 at 19:09 -0400, Alex Deucher wrote: 
> 
> Also, on r6xx/r7xx, we don't enable tiling of the front buffer as
> that would require the use of wfb or tiled to untiled blits for CPU
> access. Tiled to untiled blits works (I've tested it), but shows an
> approximately 40% performance hit for software fallbacks (tested with
> non-aa text in x11perf).  I'm not sure what how that compared to sw
> detiling with wfb since the algo is pretty complex.  In practice, I
> didn't notice any difference in performance on the desktop.

How exactly did you implement the (un)tiling blits? I'd suggest doing it
similarly to the way we're handling byte swapping with KMS on big endian
machines: return FALSE from the PrepareAccess hook and handle the
(un)tiling in the DownloadFrom/UploadToScreen hooks.

In my experience, wfb is excruciatingly inefficient (one callback per
byte in the worst case).


-- 
Earthling Michel Dänzer   |http://www.vmware.com
Libre software enthusiast |  Debian, X and DRI developer
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Re: [PATCH 1/3] r600: add span support for 2D tiling

[Frieder Ferlemann]

Hi Alex,

not tested (admittedly I haven't compiled it),
and probably not really relevant but these
switch cases could be more compact:

+static inline GLint r600_2d_tile_helper(const struct radeon_renderbuffer * rrb,
+GLint x, GLint y, GLint is_depth, GLint is_stencil)

...

+switch (element_bytes) {
+case 1:
+pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1]
+pixel_number |= ((x >> 2) & 1) << 2; // pn[2] = x[2]
+pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1]
+pixel_number |= ((y >> 0) & 1) << 4; // pn[4] = y[0]
+pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+break;
+case 2:
+pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1]
+pixel_number |= ((x >> 2) & 1) << 2; // pn[2] = x[2]
+pixel_number |= ((y >> 0) & 1) << 3; // pn[3] = y[0]
+pixel_number |= ((y >> 1) & 1) << 4; // pn[4] = y[1]
+pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+break;
+case 4:
+pixel_number |= ((x >> 0) & 1) << 0; // pn[0] = x[0]
+pixel_number |= ((x >> 1) & 1) << 1; // pn[1] = x[1]
+pixel_number |= ((y >> 0) & 1) << 2; // pn[2] = y[0]
+pixel_number |= ((x >> 2) & 1) << 3; // pn[3] = x[2]
+pixel_number |= ((y >> 1) & 1) << 4; // pn[4] = y[1]
+pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+break;
+}


when using 

+switch (element_bytes) {
+case 1:
+pixel_number |= (x & 0x07) << 0;  // pn[0] = x[0], pn[1] = 
x[1], pn[2] = x[2]
+pixel_number |= ((y >> 1) & 1) << 3; // pn[3] = y[1]
+pixel_number |= ((y >> 0) & 1) << 4; // pn[4] = y[0]
+pixel_number |= ((y >> 2) & 1) << 5; // pn[5] = y[2]
+break;
+case 2:
+pixel_number |= (x & 0x07) << 0; // pn[0] = x[0], pn[1] = 
x[1], pn[2] = x[2]
+pixel_number |= (y & 0x07) << 3; // pn[3] = y[0], pn[4] = 
y[1], pn[5] = y[2]
+break;
+case 4:
+pixel_number |= (x & 0x03) << 0; // pn[0] = x[0], pn[1] = x[1]
+pixel_number |= (y & 0x01) << 2; // pn[2] = y[0]
+pixel_number |= (x & 0x04) << 1; // pn[3] = x[2]
+pixel_number |= (y & 0x06) << 3; // pn[4] = y[1], pn[5] = y[2]
+break;
+}

Greetings,
Frieder
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