Re: [PATCH] drm/qxl: Fix build errors
Hi, > I guess things are never quite so easy :-). It looks like Daniel's > patch is in drm-misc-fixes and Sidong's patch is in drm-misc-next. On > their own they're fine, but once they are merged in drm-tip the build > error shows up. Ah, ok. I've already wondered how that got past my build testing. This explains it. thanks for looking into it, Gerd ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v11 4/5] drm/msm/dpu: add display port support in DPU
From: Jeykumar Sankaran
Add display port support in DPU by creating hooks
for DP encoder enumeration and encoder mode
initialization.
changes in v2:
- rebase on [2] (Sean Paul)
- remove unwanted error checks and
switch cases (Jordan Crouse)
[1] https://lwn.net/Articles/768265/
[2] https://lkml.org/lkml/2018/11/17/87
changes in V3:
-- Moved this change as part of the DP driver changes.
-- Addressed compilation issues on the latest code base.
Changes in v6:
-- Fix checkpatch.pl warning
Changes in v7: Remove depends-on tag from commit message.
Changes in v8: None
Changes in v9: None
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Chandan Uddaraju
Signed-off-by: Vara Reddy
Signed-off-by: Tanmay Shah
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 65 +
2 files changed, 58 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 8b14d7c42f37..6a9e257d2fe6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2025,7 +2025,7 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
{
int ret = 0;
int i = 0;
- enum dpu_intf_type intf_type;
+ enum dpu_intf_type intf_type = INTF_NONE;
struct dpu_enc_phys_init_params phys_params;
if (!dpu_enc) {
@@ -2047,9 +2047,9 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
case DRM_MODE_ENCODER_DSI:
intf_type = INTF_DSI;
break;
- default:
- DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n");
- return -EINVAL;
+ case DRM_MODE_ENCODER_TMDS:
+ intf_type = INTF_DP;
+ break;
}
WARN_ON(disp_info->num_of_h_tiles < 1);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index c0a4d4e16d82..62bc33cb0d3a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -479,6 +479,33 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
return rc;
}
+static int _dpu_kms_initialize_displayport(struct drm_device *dev,
+ struct msm_drm_private *priv,
+ struct dpu_kms *dpu_kms)
+{
+ struct drm_encoder *encoder = NULL;
+ int rc = 0;
+
+ if (!priv->dp)
+ return rc;
+
+ encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS);
+ if (IS_ERR(encoder)) {
+ DPU_ERROR("encoder init failed for dsi display\n");
+ return PTR_ERR(encoder);
+ }
+
+ rc = msm_dp_modeset_init(priv->dp, dev, encoder);
+ if (rc) {
+ DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
+ drm_encoder_cleanup(encoder);
+ return rc;
+ }
+
+ priv->encoders[priv->num_encoders++] = encoder;
+ return rc;
+}
+
/**
* _dpu_kms_setup_displays - create encoders, bridges and connectors
* for underlying displays
@@ -491,12 +518,21 @@ static int _dpu_kms_setup_displays(struct drm_device *dev,
struct msm_drm_private *priv,
struct dpu_kms *dpu_kms)
{
- /**
-* Extend this function to initialize other
-* types of displays
-*/
+ int rc = 0;
+
+ rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
+ if (rc) {
+ DPU_ERROR("initialize_dsi failed, rc = %d\n", rc);
+ return rc;
+ }
- return _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
+ rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms);
+ if (rc) {
+ DPU_ERROR("initialize_DP failed, rc = %d\n", rc);
+ return rc;
+ }
+
+ return rc;
}
static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms)
@@ -681,13 +717,20 @@ static void _dpu_kms_set_encoder_mode(struct msm_kms *kms,
info.capabilities = cmd_mode ? MSM_DISPLAY_CAP_CMD_MODE :
MSM_DISPLAY_CAP_VID_MODE;
- /* TODO: No support for DSI swap */
- for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
- if (priv->dsi[i]) {
- info.h_tile_instance[info.num_of_h_tiles] = i;
- info.num_of_h_tiles++;
+ switch (info.intf_type) {
+ case DRM_MODE_ENCODER_DSI:
+ /* TODO: No support for DSI swap */
+ for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
+ if (priv->dsi[i]) {
+ info.h_tile_instance[info.num_of_h_tiles] = i;
+ info.num_of_h_tiles++;
+ }
}
- }
+
[PATCH v11 3/5] drm/msm/dp: add support for DP PLL driver
From: Chandan Uddaraju
Add the needed DP PLL specific files to support
display port interface on msm targets.
The DP driver calls the DP PLL driver registration.
The DP driver sets the link and pixel clock sources.
Changes in v2:
-- Update copyright markings on all relevant files.
-- Use DRM_DEBUG_DP for debug msgs.
Changes in v4:
-- Update the DP link clock provider names
Changes in V5:
-- Addressed comments from Stephen Boyd, Rob clark.
Changes in V6:
-- Remove PLL as separate driver and include PLL as DP module
-- Remove redundant clock parsing from PLL module and make DP as
clock provider
-- Map USB3 DPCOM and PHY IO using hardcoded register address and
move mapping form parser to PLL module
-- Access DP PHY modules from same base address using offsets instead of
deriving base address of individual module from device tree.
-- Remove dp_pll_10nm_util.c and include its functionality in
dp_pll_10nm.c
-- Introduce new data structures private to PLL module
Changes in v7:
-- Remove DRM_MSM_DP_PLL config from Makefile and Kconfig
-- Remove set_parent from determin_rate API
-- Remove phy_pll_vco_div_clk from parent list
-- Remove flag CLK_DIVIDER_ONE_BASED
-- Remove redundant cell-index property parsing
Changes in v8:
-- Unregister hardware clocks during driver cleanup
Changes in v9:
-- Remove redundant Kconfig option DRM_MSM_DP_10NM_PLL
Changes in v10:
-- Limit 10nm PLL function scope
Signed-off-by: Chandan Uddaraju
Signed-off-by: Vara Reddy
Signed-off-by: Tanmay Shah
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/Makefile| 4 +-
drivers/gpu/drm/msm/dp/dp_catalog.c | 31 +-
drivers/gpu/drm/msm/dp/dp_display.c | 18 +-
drivers/gpu/drm/msm/dp/dp_display.h | 3 +
drivers/gpu/drm/msm/dp/dp_parser.c | 2 +
drivers/gpu/drm/msm/dp/dp_parser.h | 7 +-
drivers/gpu/drm/msm/dp/dp_pll.c | 99 +++
drivers/gpu/drm/msm/dp/dp_pll.h | 61 ++
drivers/gpu/drm/msm/dp/dp_pll_10nm.c| 930
drivers/gpu/drm/msm/dp/dp_pll_private.h | 89 +++
drivers/gpu/drm/msm/dp/dp_power.c | 10 +
drivers/gpu/drm/msm/dp/dp_power.h | 40 +-
drivers/gpu/drm/msm/dp/dp_reg.h | 16 +
14 files changed, 1294 insertions(+), 17 deletions(-)
create mode 100644 drivers/gpu/drm/msm/dp/dp_pll.c
create mode 100644 drivers/gpu/drm/msm/dp/dp_pll.h
create mode 100644 drivers/gpu/drm/msm/dp/dp_pll_10nm.c
create mode 100644 drivers/gpu/drm/msm/dp/dp_pll_private.h
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 0b59e4f184fb..8e6ca119ea94 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -60,6 +60,7 @@ config DRM_MSM_HDMI_HDCP
config DRM_MSM_DP
bool "Enable DisplayPort support in MSM DRM driver"
depends on DRM_MSM
+ default y
help
Compile in support for DP driver in MSM DRM driver. DP external
display support is enabled through this config option. It can
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index af868e791210..6d31188cc776 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -109,7 +109,9 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
dp/dp_link.o \
dp/dp_panel.o \
dp/dp_parser.o \
- dp/dp_power.o
+ dp/dp_power.o \
+ dp/dp_pll.o \
+ dp/dp_pll_10nm.o
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 497f97f86c82..e506e0756e92 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -5,6 +5,7 @@
#define pr_fmt(fmt)"[drm-dp] %s: " fmt, __func__
+#include
#include
#include
#include
@@ -131,51 +132,58 @@ static inline void dp_write_ahb(struct dp_catalog_private
*catalog,
static inline void dp_write_phy(struct dp_catalog_private *catalog,
u32 offset, u32 data)
{
+ offset += DP_PHY_REG_OFFSET;
/*
* To make sure phy reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
- writel(data, catalog->io->phy_io.base + offset);
+ writel(data, catalog->io->phy_reg.base + offset);
}
static inline u32 dp_read_phy(struct dp_catalog_private *catalog,
u32 offset)
{
+ offset += DP_PHY_REG_OFFSET;
/*
* To make sure phy reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
- return readl_relaxed(catalog->io->phy_io.base + offset);
+ return readl_relaxed(catalog->io->phy_reg.base + offset);
}
static inline void dp_write_pll(struct dp_catalog_private *catalog,
u32 offset, u32 data)
{
-
[PATCH v11 5/5] drm/msm/dp: Add Display Port HPD feature
Configure HPD registers in DP controller and
enable HPD interrupt.
Add interrupt to handle HPD connect and disconnect events.
Changes in v8: None
Signed-off-by: Tanmay Shah
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18
drivers/gpu/drm/msm/dp/dp_catalog.c | 63 --
drivers/gpu/drm/msm/dp/dp_catalog.h | 5 +-
drivers/gpu/drm/msm/dp/dp_ctrl.c| 1 -
drivers/gpu/drm/msm/dp/dp_display.c | 108 ++--
drivers/gpu/drm/msm/dp/dp_reg.h | 12 +++
drivers/gpu/drm/msm/msm_drv.h | 6 ++
7 files changed, 180 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 62bc33cb0d3a..5e977d5ff341 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -752,6 +752,23 @@ static void dpu_irq_preinstall(struct msm_kms *kms)
dpu_core_irq_preinstall(dpu_kms);
}
+static int dpu_irq_postinstall(struct msm_kms *kms)
+{
+ struct msm_drm_private *priv;
+ struct dpu_kms *dpu_kms = to_dpu_kms(kms);
+
+ if (!dpu_kms || !dpu_kms->dev)
+ return -EINVAL;
+
+ priv = dpu_kms->dev->dev_private;
+ if (!priv)
+ return -EINVAL;
+
+ msm_dp_irq_postinstall(priv->dp);
+
+ return 0;
+}
+
static void dpu_irq_uninstall(struct msm_kms *kms)
{
struct dpu_kms *dpu_kms = to_dpu_kms(kms);
@@ -762,6 +779,7 @@ static void dpu_irq_uninstall(struct msm_kms *kms)
static const struct msm_kms_funcs kms_funcs = {
.hw_init = dpu_kms_hw_init,
.irq_preinstall = dpu_irq_preinstall,
+ .irq_postinstall = dpu_irq_postinstall,
.irq_uninstall = dpu_irq_uninstall,
.irq = dpu_irq,
.enable_commit = dpu_kms_enable_commit,
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
b/drivers/gpu/drm/msm/dp/dp_catalog.c
index e506e0756e92..d186424044b1 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -17,7 +17,6 @@
#define POLLING_SLEEP_US 1000
#define POLLING_TIMEOUT_US 1
-#define REFTIMER_DEFAULT_VALUE 0x2
#define SCRAMBLER_RESET_COUNT_VALUE0xFC
#define DP_INTERRUPT_STATUS_ACK_SHIFT 1
@@ -731,35 +730,51 @@ void dp_catalog_ctrl_enable_irq(struct dp_catalog
*dp_catalog,
}
}
-void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog, bool en)
+void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog,
+ u32 intr_mask, bool en)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- if (en) {
- u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER);
+ u32 config = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK);
- dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK,
- DP_DP_HPD_PLUG_INT_ACK |
- DP_DP_IRQ_HPD_INT_ACK |
- DP_DP_HPD_REPLUG_INT_ACK |
- DP_DP_HPD_UNPLUG_INT_ACK);
- dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK,
- DP_DP_HPD_PLUG_INT_MASK |
- DP_DP_IRQ_HPD_INT_MASK |
- DP_DP_HPD_REPLUG_INT_MASK |
- DP_DP_HPD_UNPLUG_INT_MASK);
+ config = (en ? config | intr_mask : config & ~intr_mask);
- /* Configure REFTIMER */
- reftimer |= REFTIMER_DEFAULT_VALUE;
- dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer);
- /* Enable HPD */
- dp_write_aux(catalog, REG_DP_DP_HPD_CTRL,
- DP_DP_HPD_CTRL_HPD_EN);
- } else {
- /* Disable HPD */
- dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, 0x0);
- }
+ dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK,
+ config & DP_DP_HPD_INT_MASK);
+}
+
+void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+
+ u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER);
+
+ /* enable HPD interrupts */
+ dp_catalog_hpd_config_intr(dp_catalog,
+ DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK
+ | DP_DP_HPD_UNPLUG_INT_MASK, true);
+
+ /* Configure REFTIMER and enable it */
+ reftimer |= DP_DP_HPD_REFTIMER_ENABLE;
+ dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer);
+
+ /* Enable HPD */
+ dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
+}
+
+u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog)
+{
+ struct
[PATCH v11 0/5] Add support for DisplayPort driver on SnapDragon
These patches add Display-Port driver on SnapDragon/msm hardware. This series also contains device-tree bindings for msm DP driver. It also contains Makefile and Kconfig changes to compile msm DP driver. The block diagram of DP driver is shown below: +-+ |DRM FRAMEWORK| +--+--+ | +v+ | DP DRM | +++ | +v+ ++| DP+--++--+ ++---+| DISPLAY |+---+ | | |++-+-+-+| | | || | | | | | || | | | | | || | | | | | vv v v v v v +--+ +--+ +---+ ++ ++ +---+ +-+ | DP | | DP | |DP | | DP | | DP | |DP | | DP | |PARSER| | HPD | |AUX| |LINK| |CTRL| |PHY| |POWER| +--+---+ +---+--+ +---+ ++ +--+-+ +-+-+ +-+ | | | +--v---+ +v-v+ |DEVICE| | DP | | TREE | |CATALOG| +--+ +---+---+ | +---v+ |CTRL/PHY| | HW | ++ Changes in v7: - Modify cover letter description and fix title. - Introduce dp-controller.yaml for common bindings across SOC - Rename dp-sc7180.yaml to dp-controller-sc7180.yaml for SC7180 bindings - Rename compatible string to qcom,sc7180-dp - Add assigned-clocks and assigned-clock-parents properties in bindings - Remove redundant code from driver - Extend series to include HPD detection logic Changes in v8: - Add MDSS AHB clock in bindings - Replace mode->vrefresh use with drm_mode_vrefresh API - Remove redundant aux config code from parser and aux module - Assign default max lanes if data-lanes property is not available - Fix use-after-free during DP driver remove - Unregister hardware clocks during driver cleanup Changes in v9: - Drop YAML bindings change from the series - Use assigne-clock-parents property and remove clk_set_parent use from code - Access register address space without name - Fix DP register dump utility - Disable DP clocks after vsync generated - Avoid 64-bit modulo operation - Drop any unused code and fix function proptotyes to avoid W=1 warnings - Drop DRM_MSM_DP_10NM_PLL config as only 10nm PLL is available Changes in v10: - Fix help description of Kconfig entry Changes in v11: - Fix "stream_pixel" string parsing - Limit 10nm PLL functions' scope Chandan Uddaraju (4): dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon drm: add constant N value in helper file drm/msm/dp: add displayPort driver support drm/msm/dp: add support for DP PLL driver Jeykumar Sankaran (1): drm/msm/dpu: add display port support in DPU Tanmay Shah (1): drm/msm/dp: Add Display Port HPD feature drivers/gpu/drm/i915/display/intel_display.c |2 +- drivers/gpu/drm/msm/Kconfig |9 + drivers/gpu/drm/msm/Makefile | 14 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 27 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c |8 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 83 +- drivers/gpu/drm/msm/dp/dp_aux.c | 510 + drivers/gpu/drm/msm/dp/dp_aux.h | 29 + drivers/gpu/drm/msm/dp/dp_catalog.c | 1030 ++ drivers/gpu/drm/msm/dp/dp_catalog.h | 104 + drivers/gpu/drm/msm/dp/dp_ctrl.c | 1693 + drivers/gpu/drm/msm/dp/dp_ctrl.h | 35 + drivers/gpu/drm/msm/dp/dp_display.c | 1017 ++ drivers/gpu/drm/msm/dp/dp_display.h | 31 + drivers/gpu/drm/msm/dp/dp_drm.c | 168 ++ drivers/gpu/drm/msm/dp/dp_drm.h | 18 + drivers/gpu/drm/msm/dp/dp_hpd.c | 69 + drivers/gpu/drm/msm/dp/dp_hpd.h | 79 + drivers/gpu/drm/msm/dp/dp_link.c | 1214 drivers/gpu/drm/msm/dp/dp_link.h | 132 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 486 + drivers/gpu/drm/msm/dp/dp_panel.h | 95 + drivers/gpu/drm/msm/dp/dp_parser.c| 267 +++ drivers/gpu/drm/msm/dp/dp_parser.h| 138 ++ drivers/gpu/drm/msm/dp/dp_pll.c | 99 + drivers/gpu/drm/msm/dp/dp_pll.h | 61 + drivers/gpu/drm/msm/dp/dp_pll_10nm.c | 930 + drivers/gpu/drm/msm/dp/dp_pll_private.h | 89 + drivers/gpu/drm/msm/dp/dp_power.c | 373 drivers/gpu/drm/msm/dp/dp_power.h | 103 + drivers/gpu/drm/msm/dp/dp_reg.h | 517
[PATCH v11 1/5] drm: add constant N value in helper file
From: Chandan Uddaraju The constant N value (0x8000) is used by i915 DP driver. Define this value in dp helper header file to use in multiple Display Port drivers. Change i915 driver accordingly. Change in v6: Change commit message Signed-off-by: Chandan Uddaraju Signed-off-by: Vara Reddy Signed-off-by: Tanmay Shah Reviewed-by: Stephen Boyd Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- include/drm/drm_dp_helper.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 729ec6e0d43a..10b8310f290b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8114,7 +8114,7 @@ static void compute_m_n(unsigned int m, unsigned int n, * which the devices expect also in synchronous clock mode. */ if (constant_n) - *ret_n = 0x8000; + *ret_n = DP_LINK_CONSTANT_N_VALUE; else *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e47dc22ebf50..a31d7aebb8b8 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1134,6 +1134,7 @@ #define DP_MST_PHYSICAL_PORT_0 0 #define DP_MST_LOGICAL_PORT_0 8 +#define DP_LINK_CONSTANT_N_VALUE 0x8000 #define DP_LINK_STATUS_SIZE 6 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [RFC] Experimental DMA-BUF Device Heaps
On Sun, Aug 16, 2020 at 10:23 AM Ezequiel Garcia wrote: > > This heap is basically a wrapper around DMA-API dma_alloc_attrs, > which will allocate memory suitable for the given device. > > The implementation is mostly a port of the Contiguous Videobuf2 > memory allocator (see videobuf2/videobuf2-dma-contig.c) > over to the DMA-BUF Heap interface. > > The intention of this allocator is to provide applications > with a more system-agnostic API: the only thing the application > needs to know is which device to get the buffer for. > > Whether the buffer is backed by CMA, IOMMU or a DMA Pool > is unknown to the application. My hesitancy here is that the main reason we have DMA BUF Heaps, and ION before it, was to expose different types of memory allocations to userspace. The main premise that often these buffers are shared with multiple devices, which have differing constraints and it is userspace that best understands the path a buffer will take through a series of devices. So userspace is best positioned to determine what type of memory should be allocated to satisfy the various devices constraints (there were some design attempts to allow DMA BUFs to use multiple attach with deferred alloc at map time to handle this constraint solving in-kernel, but it was never adopted in practice). This however, requires some system specific policy - implemented in the Android userspace by gralloc which maps "usage" types (device pipeline flows) to heaps. I liken it to fstab, which helps map mount points to partitions - it's not going to be the same on every system. What you seem to be proposing seems a bit contrary to this premise - Userland doesn't know what type of memory it needs, but given a device can somehow find the heap it should allocate for? This seems to assume the buffer is only to be used with a single device? There was at some point a discussion where folks (maybe it was DanielV? I can't remember...) suggested having something like a sysfs device node link from a device to a dma-buf heap chardev. This seems like it would add a similar behavior as what you're proposing, however without adding possibly a ton of new device specific heaps to the /dev/dma_heap/ dir. However, we would potentially need any missing heap types added first. > I'm not really expecting this patch to be correct or even > a good idea, but just submitting it to start a discussion on DMA-BUF > heap discovery and negotiation. > > Given Plumbers is just a couple weeks from now, I've submitted > a BoF proposal to discuss this, as perhaps it would make > sense to discuss this live? I do think it's an interesting idea. I agree that having every driver implement a dmabuf exporter is a bit silly, but I also think Brian's point that maybe we need some drm helper functions that provide similar functionality along with a more standardized device ioctl for single device allocations might be better. thanks -john ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [RFC] Experimental DMA-BUF Device Heaps
On 8/17/20 8:18 AM, Brian Starkey wrote: Hi Ezequiel, On Sun, Aug 16, 2020 at 02:22:46PM -0300, Ezequiel Garcia wrote: This heap is basically a wrapper around DMA-API dma_alloc_attrs, which will allocate memory suitable for the given device. The implementation is mostly a port of the Contiguous Videobuf2 memory allocator (see videobuf2/videobuf2-dma-contig.c) over to the DMA-BUF Heap interface. The intention of this allocator is to provide applications with a more system-agnostic API: the only thing the application needs to know is which device to get the buffer for. Whether the buffer is backed by CMA, IOMMU or a DMA Pool is unknown to the application. I'm not really expecting this patch to be correct or even a good idea, but just submitting it to start a discussion on DMA-BUF heap discovery and negotiation. My initial reaction is that I thought dmabuf heaps are meant for use to allocate buffers for sharing across devices, which doesn't fit very well with having per-device heaps. For single-device allocations, would using the buffer allocation functionality of that device's native API be better in most cases? (Some other possibly relevant discussion at [1]) I can see that this can save some boilerplate for devices that want to expose private chunks of memory, but might it also lead to 100 aliases for the system's generic coherent memory pool? I wonder if a set of helpers to allow devices to expose whatever they want with minimal effort would be better. I'm rather interested on where this goes, as I was toying with using some sort of heap ID as a basis for a "device-local" constraint in the memory constraints proposals Simon and I will be discussing at XDC this year. It would be rather elegant if there was one type of heap ID used universally throughout the kernel that could provide a unique handle for the shared system memory heap(s), as well as accelerator-local heaps on fancy NICs, GPUs, NN accelerators, capture devices, etc. so apps could negotiate a location among themselves. This patch seems to be a step towards that in a way, but I agree it would be counterproductive if a bunch of devices that were using the same underlying system memory ended up each getting their own heap ID just because they used some SW framework that worked that way. Would appreciate it if you could send along a pointer to your BoF if it happens! Thanks, -James Cheers, -Brian 1. https://lore.kernel.org/dri-devel/57062477-30e7-a3de-6723-a50d03a40...@kapsi.fi/ Given Plumbers is just a couple weeks from now, I've submitted a BoF proposal to discuss this, as perhaps it would make sense to discuss this live? Not-signed-off-by: Ezequiel Garcia ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3] arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node
This node defines alternate DP HPD functionality of GPIO.
Signed-off-by: Tanmay Shah
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index bf2f2bb1aa79..2e2a0631ab65 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1082,6 +1082,19 @@ tlmm: pinctrl@350 {
gpio-ranges = < 0 0 120>;
wakeup-parent = <>;
+ dp_hot_plug_det: dp-hot-plug-det {
+ pinmux {
+ pins = "gpio117";
+ function = "dp_hot";
+ };
+
+ pinconf {
+ pins = "gpio117";
+ bias-disable;
+ input-enable;
+ };
+ };
+
qspi_clk: qspi-clk {
pinmux {
pins = "gpio63";
base-commit: 62975d27d647a40c58d3b96c29b911fc4f33c310
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Re: [PATCH v6] arm64: dts: qcom: sc7180: Add Display Port dt node
On 2020-08-17 17:24, Stephen Boyd wrote:
Quoting Tanmay Shah (2020-08-17 15:53:00)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 31b9217bb5bf..bf2f2bb1aa79 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2440,6 +2447,71 @@ dsi_phy: dsi-phy@ae94400 {
status = "disabled";
};
+
+ msm_dp: displayport-controller@ae9 {
This should come before dsi-phy and dsi node. It should be sorted by
the
address (0xae9).
+ status = "disabled";
+ compatible = "qcom,sc7180-dp";
+
+ reg = <0 0x0ae9 0 0x1400>;
+
+ interrupt-parent = <>;
+ interrupts = <12>;
+
[...]
};
dispcc: clock-controller@af0 {
@@ -2449,8 +2521,8 @@ dispcc: clock-controller@af0 {
< GCC_DISP_GPLL0_CLK_SRC>,
<_phy 0>,
<_phy 1>,
-<0>,
-<0>;
+<_dp 0>,
+<_dp 1>;
Don't think we should apply this still because the binding will change
when the phy is split out to qmp node. Maybe just leave this part off
for now?
Ok fine. But, that will break DP driver functionality.
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Re: [PATCH v2] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp
On Tue, 2020-08-18 at 07:42 +0800, Chun-Kuang Hu wrote:
> Hi, Jitao:
>
> Jitao Shi 於 2020年8月17日 週一 下午9:07寫道：
> >
> > horizontal_backporch_byte should be hbp * bpp - hbp extra bytes.
> > So remove the wrong subtraction 10.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/mediatek/mtk_dsi.c | 9 -
> > 1 file changed, 4 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > index 270bf22c98fe..5d031e634571 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > @@ -473,14 +473,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi
> > *dsi)
> > horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp -
> > 10);
>
> So this subtraction 10 is correct?
>
> Regards,
> Chun-Kuang.
>
Yes, It is right.
In the cea861 and dmt spec the mini hsync is 40 pixels.
So the vm->hsync_len * dsi_tmp_buf_bpp >= 120 > 10
Best Regards
jitao
> >
> > if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> > - horizontal_backporch_byte =
> > - (vm->hback_porch * dsi_tmp_buf_bpp - 10);
> > + horizontal_backporch_byte = vm->hback_porch *
> > dsi_tmp_buf_bpp;
> > else
> > - horizontal_backporch_byte = ((vm->hback_porch +
> > vm->hsync_len) *
> > - dsi_tmp_buf_bpp - 10);
> > + horizontal_backporch_byte = (vm->hback_porch +
> > vm->hsync_len) *
> > + dsi_tmp_buf_bpp;
> >
> > data_phy_cycles = timing->lpx + timing->da_hs_prepare +
> > - timing->da_hs_zero + timing->da_hs_exit + 3;
> > + timing->da_hs_zero + timing->da_hs_exit;
> >
> > if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
> > if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
> > --
> > 2.12.5
> > ___
> > Linux-mediatek mailing list
> > linux-media...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
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[drm-tip:drm-tip 5/10] drivers/gpu/drm/qxl/qxl_display.c:187:2: error: implicit declaration of function 'drm_drv_uses_atomic_modeset'
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: d6cb40f33c1b213c96924b8fb68db613862fc2c5
commit: a012dc947ede8d940b6f79de96429af04a9360c4 [5/10] Merge remote-tracking
branch 'drm-misc/drm-misc-next' into drm-tip
config: x86_64-randconfig-a016-20200817 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
de71b46a519db014ce906a39f8a0e1b235ef1568)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
git checkout a012dc947ede8d940b6f79de96429af04a9360c4
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/qxl/qxl_display.c:187:2: error: implicit declaration of
>> function 'drm_drv_uses_atomic_modeset'
>> [-Werror,-Wimplicit-function-declaration]
DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx,
DRM_MODESET_ACQUIRE_INTERRUPTIBLE, ret);
^
include/drm/drm_modeset_lock.h:167:7: note: expanded from macro
'DRM_MODESET_LOCK_ALL_BEGIN'
if (!drm_drv_uses_atomic_modeset(dev)) \
^
>> drivers/gpu/drm/qxl/qxl_display.c:189:35: error: too few arguments provided
>> to function-like macro invocation
DRM_MODESET_LOCK_ALL_END(ctx, ret);
^
include/drm/drm_modeset_lock.h:194:9: note: macro 'DRM_MODESET_LOCK_ALL_END'
defined here
#define DRM_MODESET_LOCK_ALL_END(dev, ctx, ret) \
^
>> drivers/gpu/drm/qxl/qxl_display.c:189:2: error: use of undeclared identifier
>> 'DRM_MODESET_LOCK_ALL_END'
DRM_MODESET_LOCK_ALL_END(ctx, ret);
^
>> drivers/gpu/drm/qxl/qxl_display.c:187:2: error: use of undeclared label
>> 'modeset_lock_fail'
DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx,
DRM_MODESET_ACQUIRE_INTERRUPTIBLE, ret);
^
include/drm/drm_modeset_lock.h:173:8: note: expanded from macro
'DRM_MODESET_LOCK_ALL_BEGIN'
goto modeset_lock_fail;
^
drivers/gpu/drm/qxl/qxl_display.c:411:2: error: implicit declaration of
function 'drm_drv_uses_atomic_modeset' [-Werror,-Wimplicit-function-declaration]
DRM_MODESET_LOCK_ALL_BEGIN(fb->dev, ctx,
DRM_MODESET_ACQUIRE_INTERRUPTIBLE, ret);
^
include/drm/drm_modeset_lock.h:167:7: note: expanded from macro
'DRM_MODESET_LOCK_ALL_BEGIN'
if (!drm_drv_uses_atomic_modeset(dev)) \
^
drivers/gpu/drm/qxl/qxl_display.c:434:35: error: too few arguments provided
to function-like macro invocation
DRM_MODESET_LOCK_ALL_END(ctx, ret);
^
include/drm/drm_modeset_lock.h:194:9: note: macro 'DRM_MODESET_LOCK_ALL_END'
defined here
#define DRM_MODESET_LOCK_ALL_END(dev, ctx, ret) \
^
drivers/gpu/drm/qxl/qxl_display.c:434:2: error: use of undeclared identifier
'DRM_MODESET_LOCK_ALL_END'
DRM_MODESET_LOCK_ALL_END(ctx, ret);
^
drivers/gpu/drm/qxl/qxl_display.c:411:2: error: use of undeclared label
'modeset_lock_fail'
DRM_MODESET_LOCK_ALL_BEGIN(fb->dev, ctx,
DRM_MODESET_ACQUIRE_INTERRUPTIBLE, ret);
^
include/drm/drm_modeset_lock.h:173:8: note: expanded from macro
'DRM_MODESET_LOCK_ALL_BEGIN'
goto modeset_lock_fail;
^
8 errors generated.
git remote add drm-tip git://anongit.freedesktop.org/drm/drm-tip
git fetch --no-tags drm-tip drm-tip
git checkout a012dc947ede8d940b6f79de96429af04a9360c4
vim +/drm_drv_uses_atomic_modeset +187 drivers/gpu/drm/qxl/qxl_display.c
7dea0941f8806e Dave Airlie 2014-10-28 161
f64122c1f6ade3 Dave Airlie 2013-02-25 162 void
qxl_display_read_client_monitors_config(struct qxl_device *qdev)
f64122c1f6ade3 Dave Airlie 2013-02-25 163 {
cbdded7f8a633e Gabriel Krisman Bertazi 2017-01-26 164 struct
drm_device *dev = >ddev;
bbaac1354cc984 Sidong Yang 2020-05-24 165 struct
drm_modeset_acquire_ctx ctx;
bbaac1354cc984 Sidong Yang 2020-05-24 166 int status,
retries, ret;
9e3b317839298a Christophe Fergeau 2016-11-08 167
9062155de0dfdc Gerd Hoffmann 2017-03-01 168 for (retries =
0; retries < 10; retries++) {
9e3b317839298a Christophe Fergeau 2016-11-08 169 status
= qxl_display_copy_rom_client_monitors_config(qdev);
9062155de0dfdc Gerd Hoffmann
[Bug 208947] amdgpu DisplayPort won't recognize all display modes after 5.9 merges
https://bugzilla.kernel.org/show_bug.cgi?id=208947 Coleman Kane (ck...@colemankane.org) changed: What|Removed |Added Regression|No |Yes -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp
Hi, Jitao:
Jitao Shi 於 2020年8月17日 週一 下午9:07寫道：
>
> horizontal_backporch_byte should be hbp * bpp - hbp extra bytes.
> So remove the wrong subtraction 10.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 9 -
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 270bf22c98fe..5d031e634571 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -473,14 +473,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi
> *dsi)
> horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
So this subtraction 10 is correct?
Regards,
Chun-Kuang.
>
> if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> - horizontal_backporch_byte =
> - (vm->hback_porch * dsi_tmp_buf_bpp - 10);
> + horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp;
> else
> - horizontal_backporch_byte = ((vm->hback_porch +
> vm->hsync_len) *
> - dsi_tmp_buf_bpp - 10);
> + horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len)
> *
> + dsi_tmp_buf_bpp;
>
> data_phy_cycles = timing->lpx + timing->da_hs_prepare +
> - timing->da_hs_zero + timing->da_hs_exit + 3;
> + timing->da_hs_zero + timing->da_hs_exit;
>
> if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
> if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
> --
> 2.12.5
> ___
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> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
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[PATCH v2] arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node
This node defines alternate DP HPD functionality of GPIO.
Signed-off-by: Tanmay Shah
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index bf2f2bb1aa79..0eedf057acc1 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1457,6 +1457,19 @@ pinconf-sd-cd {
drive-strength = <2>;
};
};
+
+ dp_hot_plug_det: dp-hot-plug-det {
+ pinmux {
+ pins = "gpio117";
+ function = "dp_hot";
+ };
+
+ pinconf {
+ pins = "gpio117";
+ bias-disable;
+ input-enable;
+ };
+ };
};
gpu: gpu@500 {
base-commit: 62975d27d647a40c58d3b96c29b911fc4f33c310
prerequisite-patch-id: a4d3e51b6e1200ff7d4550f206db98a92c0a098f
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[PATCH v6] arm64: dts: qcom: sc7180: Add Display Port dt node
Add DP device node on sc7180.
Changes in v2:
- Add assigned-clocks and assigned-clock-parents
- Remove cell-index and pixel_rcg
- Change compatible to qcom,sc7180-dp
Changes in v3:
- Update commit text
- Make DP child node of MDSS
- Remove data-lanes property from SOC dts
- Disable DP node in SOC dts
- Assign DP to Port2 in MDP node
- Add MDSS AHB clock in DP device node
Changes in v4:
- Remove redundant reg-names property
- Use IRQ flag instead had hard coded value.
- Add link clock source in assigned-clocks list.
Changes in v5:
- Add OPP table and power-domains for DisplayPort
Changes in v6:
- Remove redundant IRQ flag
Signed-off-by: Tanmay Shah
Co-developed-by: Kuogee Hsieh
Signed-off-by: Kuogee Hsieh
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 76 +++-
1 file changed, 74 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 31b9217bb5bf..bf2f2bb1aa79 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2371,6 +2371,13 @@ dpu_intf1_out: endpoint {
remote-endpoint =
<_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
};
};
@@ -2440,6 +2447,71 @@ dsi_phy: dsi-phy@ae94400 {
status = "disabled";
};
+
+ msm_dp: displayport-controller@ae9 {
+ status = "disabled";
+ compatible = "qcom,sc7180-dp";
+
+ reg = <0 0x0ae9 0 0x1400>;
+
+ interrupt-parent = <>;
+ interrupts = <12>;
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_DP_AUX_CLK>,
+< DISP_CC_MDSS_DP_LINK_CLK>,
+<
DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+< DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface", "core_aux",
"ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <
DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <_dp 0>, <_dp
1>;
+
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SC7180_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dp_in: endpoint {
+ remote-endpoint =
<_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_out: endpoint { };
+ };
+ };
+
+ dp_opp_table: dp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-16000 {
+ opp-hz = /bits/ 64 <16000>;
+ required-opps =
<_opp_low_svs>;
+ };
+
+ opp-27000 {
+ opp-hz = /bits/ 64 <27000>;
+ required-opps =
<_opp_svs>;
+ };
+
+ opp-54000 {
+ opp-hz = /bits/ 64 <54000>;
+ required-opps =
<_opp_svs_l1>;
+ };
+
+ opp-81000 {
+ opp-hz = /bits/ 64 <81000>;
+
[PATCH v1] arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node
This node defines alternate DP HPD functionality of GPIO.
Signed-off-by: Tanmay Shah
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index bf2f2bb1aa79..9f97cf5dd9ab 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1457,6 +1457,20 @@ pinconf-sd-cd {
drive-strength = <2>;
};
};
+
+ dp_hot_plug_det: dp-hot-plug-det {
+ pinmux {
+ pins = "gpio117";
+ function = "dp_hot";
+ };
+
+ config {
+ pins = "gpio117";
+ bias-disable;
+ input-enable;
+ drive-strength = <2>;
+ };
+ };
};
gpu: gpu@500 {
base-commit: 62975d27d647a40c58d3b96c29b911fc4f33c310
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 4/5] drm/msm/dp: signal the hotplug disconnect in the event handler
Signal the hotplug disconnect event to the audio side in the
event handler so that they are notified earlier and have more
time to process the disconnect event.
Changes in v3: none
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 5b4dcd5621d8..fcf30d8cc040 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -504,6 +504,13 @@ static int dp_hpd_plug_handle(struct dp_display_private
*dp, u32 data)
return 0;
};
+static void dp_display_handle_plugged_change(struct msm_dp *dp_display,
+ bool plugged)
+{
+ if (dp_display->plugged_cb && dp_display->codec_dev)
+ dp_display->plugged_cb(dp_display->codec_dev, plugged);
+}
+
static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data)
{
struct dp_usbpd *hpd = dp->usbpd;
@@ -544,6 +551,9 @@ static int dp_hpd_unplug_handle(struct dp_display_private
*dp, u32 data)
*/
dp_display_usbpd_disconnect_cb(>pdev->dev);
+ /* signal the disconnect event early to ensure proper teardown */
+ dp_display_handle_plugged_change(g_dp_display, false);
+
dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK |
DP_DP_IRQ_HPD_INT_MASK, true);
@@ -709,13 +719,6 @@ static int dp_display_prepare(struct msm_dp *dp)
return 0;
}
-static void dp_display_handle_plugged_change(struct msm_dp *dp_display,
- bool plugged)
-{
- if (dp_display->plugged_cb && dp_display->codec_dev)
- dp_display->plugged_cb(dp_display->codec_dev, plugged);
-}
-
static int dp_display_enable(struct dp_display_private *dp, u32 data)
{
int rc = 0;
@@ -757,9 +760,6 @@ static int dp_display_pre_disable(struct msm_dp *dp_display)
dp = container_of(dp_display, struct dp_display_private, dp_display);
- /* signal the disconnect event early to ensure proper teardown */
- dp_display_handle_plugged_change(dp_display, false);
-
return 0;
}
--
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a Linux Foundation Collaborative Project
___
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[PATCH v3 5/5] drm/msm/dp: wait for audio notification before disabling clocks
In the current implementation, there is a very small window for
the audio side to safely signal the hdmi_code_shutdown() before
the clocks are disabled.
Add some synchronization between the DP display and DP audio module
to safely disable the clocks to avoid unclocked access from audio
side.
In addition, audio side can open the sound card even if DP monitor
is not connected. Avoid programming hardware registers in this case
and bail out early.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_audio.c | 32 +
drivers/gpu/drm/msm/dp/dp_display.c | 28 +
drivers/gpu/drm/msm/dp/dp_display.h | 2 ++
3 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c
b/drivers/gpu/drm/msm/dp/dp_audio.c
index 11fa5ad7a801..a51659be8f82 100644
--- a/drivers/gpu/drm/msm/dp/dp_audio.c
+++ b/drivers/gpu/drm/msm/dp/dp_audio.c
@@ -497,8 +497,23 @@ int dp_audio_hw_params(struct device *dev,
int rc = 0;
struct dp_audio_private *audio;
struct platform_device *pdev;
+ struct msm_dp *dp_display;
pdev = to_platform_device(dev);
+ dp_display = platform_get_drvdata(pdev);
+
+ /*
+* There could be cases where sound card can be opened even
+* before OR even when DP is not connected . This can cause
+* unclocked access as the audio subsystem relies on the DP
+* driver to maintain the correct state of clocks. To protect
+* such cases check for connection status and bail out if not
+* connected.
+*/
+ if (!dp_display->is_connected) {
+ rc = -EINVAL;
+ goto end;
+ }
audio = dp_audio_get_data(pdev);
if (IS_ERR(audio)) {
@@ -512,6 +527,8 @@ int dp_audio_hw_params(struct device *dev,
dp_audio_setup_acr(audio);
dp_audio_safe_to_exit_level(audio);
dp_audio_enable(audio, true);
+ dp_display->audio_enabled = true;
+
end:
return rc;
}
@@ -520,15 +537,30 @@ static void dp_audio_shutdown(struct device *dev, void
*data)
{
struct dp_audio_private *audio;
struct platform_device *pdev;
+ struct msm_dp *dp_display;
pdev = to_platform_device(dev);
+ dp_display = platform_get_drvdata(pdev);
audio = dp_audio_get_data(pdev);
if (IS_ERR(audio)) {
DRM_ERROR("failed to get audio data\n");
return;
}
+ /*
+* if audio was not enabled there is no need
+* to execute the shutdown and we can bail out early.
+* This also makes sure that we dont cause an unclocked
+* access when audio subsystem calls this without DP being
+* connected. is_connected cannot be used here as its set
+* to false earlier than this call
+*/
+ if (!dp_display->audio_enabled)
+ return;
+
dp_audio_enable(audio, false);
+ /* signal the dp display to safely shutdown clocks */
+ dp_display_signal_audio_complete(dp_display);
}
static const struct hdmi_codec_ops dp_audio_codec_ops = {
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index fcf30d8cc040..1d6210dc62fc 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -95,6 +95,9 @@ struct dp_display_private {
struct dp_display_mode dp_mode;
struct msm_dp dp_display;
+ /* wait for audio signaling */
+ struct completion audio_comp;
+
/* event related only access by event thread */
struct mutex event_mutex;
wait_queue_head_t event_q;
@@ -166,6 +169,15 @@ static int dp_del_event(struct dp_display_private
*dp_priv, u32 event)
return 0;
}
+void dp_display_signal_audio_complete(struct msm_dp *dp_display)
+{
+ struct dp_display_private *dp;
+
+ dp = container_of(dp_display, struct dp_display_private, dp_display);
+
+ complete_all(>audio_comp);
+}
+
static int dp_display_bind(struct device *dev, struct device *master,
void *data)
{
@@ -553,6 +565,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private
*dp, u32 data)
/* signal the disconnect event early to ensure proper teardown */
dp_display_handle_plugged_change(g_dp_display, false);
+ reinit_completion(>audio_comp);
dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK |
DP_DP_IRQ_HPD_INT_MASK, true);
@@ -765,9 +778,22 @@ static int dp_display_pre_disable(struct msm_dp
*dp_display)
static int dp_display_disable(struct dp_display_private *dp, u32 data)
{
+ struct msm_dp *dp_display;
+
if (!dp->power_on)
return -EINVAL;
+ dp_display = g_dp_display;
+
+ /* wait only if audio was enabled */
+ if (dp_display->audio_enabled) {
+ if (!wait_for_completion_timeout(>audio_comp,
[PATCH v3 2/5] drm/msm/dp: add audio support for Display Port on MSM
Introduce audio support for Display Port on MSM chipsets.
This change integrates DP audio sub-module with the main
Display Port platform driver.
In addition, this change leverages hdmi_codec_ops to expose
the operations to the audio driver.
Changes in v2: fix up a compilation issue on drm-next branch
Changes in v3: none
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/Makefile| 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +
drivers/gpu/drm/msm/dp/dp_audio.c | 583
drivers/gpu/drm/msm/dp/dp_audio.h | 72 +++
drivers/gpu/drm/msm/dp/dp_catalog.c | 192 +++
drivers/gpu/drm/msm/dp/dp_catalog.h | 29 +
drivers/gpu/drm/msm/dp/dp_display.c | 48 ++
drivers/gpu/drm/msm/dp/dp_display.h | 2 +
8 files changed, 934 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/msm/dp/dp_audio.c
create mode 100644 drivers/gpu/drm/msm/dp/dp_audio.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 6d31188cc776..db1bdd35bbf5 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -111,7 +111,8 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
dp/dp_parser.o \
dp/dp_power.o \
dp/dp_pll.o \
- dp/dp_pll_10nm.o
+ dp/dp_pll_10nm.o \
+ dp/dp_audio.o
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index fe0d538099f9..e6940293086a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1077,6 +1077,12 @@ static void _dpu_encoder_virt_enable_helper(struct
drm_encoder *drm_enc)
return;
}
+ if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
+ dpu_enc->cur_master->hw_mdptop &&
+ dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
+ dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
+ dpu_enc->cur_master->hw_mdptop);
+
if (dpu_enc->cur_master->hw_mdptop &&
dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc)
dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc(
diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c
b/drivers/gpu/drm/msm/dp/dp_audio.c
new file mode 100644
index ..75556eea1059
--- /dev/null
+++ b/drivers/gpu/drm/msm/dp/dp_audio.c
@@ -0,0 +1,583 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ */
+
+
+#define pr_fmt(fmt)"[drm-dp] %s: " fmt, __func__
+
+#include
+
+#include
+#include
+#include
+
+#include "dp_catalog.h"
+#include "dp_audio.h"
+#include "dp_panel.h"
+#include "dp_display.h"
+
+#define HEADER_BYTE_2_BIT 0
+#define PARITY_BYTE_2_BIT 8
+#define HEADER_BYTE_1_BIT 16
+#define PARITY_BYTE_1_BIT 24
+#define HEADER_BYTE_3_BIT 16
+#define PARITY_BYTE_3_BIT 24
+
+struct dp_audio_private {
+ struct platform_device *audio_pdev;
+ struct platform_device *pdev;
+ struct dp_catalog *catalog;
+ struct dp_panel *panel;
+
+ bool engine_on;
+ u32 channels;
+
+ struct dp_audio dp_audio;
+};
+
+static u8 dp_audio_get_g0_value(u8 data)
+{
+ u8 c[4];
+ u8 g[4];
+ u8 ret_data = 0;
+ u8 i;
+
+ for (i = 0; i < 4; i++)
+ c[i] = (data >> i) & 0x01;
+
+ g[0] = c[3];
+ g[1] = c[0] ^ c[3];
+ g[2] = c[1];
+ g[3] = c[2];
+
+ for (i = 0; i < 4; i++)
+ ret_data = ((g[i] & 0x01) << i) | ret_data;
+
+ return ret_data;
+}
+
+static u8 dp_audio_get_g1_value(u8 data)
+{
+ u8 c[4];
+ u8 g[4];
+ u8 ret_data = 0;
+ u8 i;
+
+ for (i = 0; i < 4; i++)
+ c[i] = (data >> i) & 0x01;
+
+ g[0] = c[0] ^ c[3];
+ g[1] = c[0] ^ c[1] ^ c[3];
+ g[2] = c[1] ^ c[2];
+ g[3] = c[2] ^ c[3];
+
+ for (i = 0; i < 4; i++)
+ ret_data = ((g[i] & 0x01) << i) | ret_data;
+
+ return ret_data;
+}
+
+static u8 dp_audio_calculate_parity(u32 data)
+{
+ u8 x0 = 0;
+ u8 x1 = 0;
+ u8 ci = 0;
+ u8 iData = 0;
+ u8 i = 0;
+ u8 parity_byte;
+ u8 num_byte = (data & 0xFF00) > 0 ? 8 : 2;
+
+ for (i = 0; i < num_byte; i++) {
+ iData = (data >> i*4) & 0xF;
+
+ ci = iData ^ x1;
+ x1 = x0 ^ dp_audio_get_g1_value(ci);
+ x0 = dp_audio_get_g0_value(ci);
+ }
+
+ parity_byte = x1 | (x0 << 4);
+
+ return parity_byte;
+}
+
+static u32 dp_audio_get_header(struct dp_catalog *catalog,
+ enum dp_catalog_audio_sdp_type sdp,
+ enum dp_catalog_audio_header_type header)
+{
+ catalog->sdp_type = sdp;
+ catalog->sdp_header =
[PATCH v3 3/5] drm/msm/dp: add hook_plugged_cb hdmi-codec op for MSM DP driver
Add the hook_plugged_cb op for the MSM DP driver to signal connect
and disconnect events to the hdmi-codec driver which in-turn shall
notify the audio subsystem to start a new or teardown an existing
session.
Changes in v2: none
Changes in v3: none
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_audio.c | 25 -
drivers/gpu/drm/msm/dp/dp_display.c | 25 +
drivers/gpu/drm/msm/dp/dp_display.h | 7 +++
3 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c
b/drivers/gpu/drm/msm/dp/dp_audio.c
index 75556eea1059..11fa5ad7a801 100644
--- a/drivers/gpu/drm/msm/dp/dp_audio.c
+++ b/drivers/gpu/drm/msm/dp/dp_audio.c
@@ -10,7 +10,6 @@
#include
#include
-#include
#include "dp_catalog.h"
#include "dp_audio.h"
@@ -442,6 +441,29 @@ static struct dp_audio_private *dp_audio_get_data(struct
platform_device *pdev)
return container_of(dp_audio, struct dp_audio_private, dp_audio);
}
+static int dp_audio_hook_plugged_cb(struct device *dev, void *data,
+ hdmi_codec_plugged_cb fn,
+ struct device *codec_dev)
+{
+
+ struct platform_device *pdev;
+ struct msm_dp *dp_display;
+
+ pdev = to_platform_device(dev);
+ if (!pdev) {
+ pr_err("invalid input\n");
+ return -ENODEV;
+ }
+
+ dp_display = platform_get_drvdata(pdev);
+ if (!dp_display) {
+ pr_err("invalid input\n");
+ return -ENODEV;
+ }
+
+ return dp_display_set_plugged_cb(dp_display, fn, codec_dev);
+}
+
static int dp_audio_get_eld(struct device *dev,
void *data, uint8_t *buf, size_t len)
{
@@ -513,6 +535,7 @@ static const struct hdmi_codec_ops dp_audio_codec_ops = {
.hw_params = dp_audio_hw_params,
.audio_shutdown = dp_audio_shutdown,
.get_eld = dp_audio_get_eld,
+ .hook_plugged_cb = dp_audio_hook_plugged_cb,
};
static struct hdmi_codec_pdata codec_data = {
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 3120e172adc2..5b4dcd5621d8 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -709,6 +709,13 @@ static int dp_display_prepare(struct msm_dp *dp)
return 0;
}
+static void dp_display_handle_plugged_change(struct msm_dp *dp_display,
+ bool plugged)
+{
+ if (dp_display->plugged_cb && dp_display->codec_dev)
+ dp_display->plugged_cb(dp_display->codec_dev, plugged);
+}
+
static int dp_display_enable(struct dp_display_private *dp, u32 data)
{
int rc = 0;
@@ -739,6 +746,8 @@ static int dp_display_post_enable(struct msm_dp *dp_display)
dp->audio->lane_count = dp->link->link_params.num_lanes;
}
+ /* signal the connect event late to synchronize video and display */
+ dp_display_handle_plugged_change(dp_display, true);
return 0;
}
@@ -748,6 +757,9 @@ static int dp_display_pre_disable(struct msm_dp *dp_display)
dp = container_of(dp_display, struct dp_display_private, dp_display);
+ /* signal the disconnect event early to ensure proper teardown */
+ dp_display_handle_plugged_change(dp_display, false);
+
return 0;
}
@@ -770,6 +782,19 @@ static int dp_display_unprepare(struct msm_dp *dp)
return 0;
}
+int dp_display_set_plugged_cb(struct msm_dp *dp_display,
+ hdmi_codec_plugged_cb fn, struct device *codec_dev)
+{
+ bool plugged;
+
+ dp_display->plugged_cb = fn;
+ dp_display->codec_dev = codec_dev;
+ plugged = dp_display->is_connected;
+ dp_display_handle_plugged_change(dp_display, plugged);
+
+ return 0;
+}
+
int dp_display_validate_mode(struct msm_dp *dp, u32 mode_pclk_khz)
{
const u32 num_components = 3, default_bpp = 24;
diff --git a/drivers/gpu/drm/msm/dp/dp_display.h
b/drivers/gpu/drm/msm/dp/dp_display.h
index 1e0d2b9d9a2a..5020faf360db 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.h
+++ b/drivers/gpu/drm/msm/dp/dp_display.h
@@ -7,18 +7,25 @@
#define _DP_DISPLAY_H_
#include "dp_panel.h"
+#include
struct msm_dp {
struct drm_device *drm_dev;
+ struct device *codec_dev;
struct drm_connector *connector;
struct drm_encoder *encoder;
bool is_connected;
+
+ hdmi_codec_plugged_cb plugged_cb;
+
u32 max_pclk_khz;
u32 max_dp_lanes;
struct dp_audio *dp_audio;
};
+int dp_display_set_plugged_cb(struct msm_dp *dp_display,
+ hdmi_codec_plugged_cb fn, struct device *codec_dev);
int dp_display_validate_mode(struct msm_dp *dp_display, u32 mode_pclk_khz);
int dp_display_get_modes(struct msm_dp *dp_display,
struct dp_display_mode *dp_mode);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[PATCH v3 1/5] drm/msm/dp: store dp_display in the driver data
Store the dp_display in the platform driver data instead of the
dp_display_private.
This is required to allow other sub-modules to reuse the platform
driver data.
Changes in v3: none
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_display.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 4cce7e5017a5..d32ce6753883 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -170,11 +170,11 @@ static int dp_display_bind(struct device *dev, struct
device *master,
struct dp_display_private *dp;
struct drm_device *drm;
struct msm_drm_private *priv;
- struct platform_device *pdev = to_platform_device(dev);
drm = dev_get_drvdata(master);
- dp = platform_get_drvdata(pdev);
+ dp = container_of(g_dp_display,
+ struct dp_display_private, dp_display);
if (!dp) {
DRM_ERROR("DP driver bind failed. Invalid driver data\n");
return -EINVAL;
@@ -209,11 +209,11 @@ static void dp_display_unbind(struct device *dev, struct
device *master,
void *data)
{
struct dp_display_private *dp;
- struct platform_device *pdev = to_platform_device(dev);
struct drm_device *drm = dev_get_drvdata(master);
struct msm_drm_private *priv = drm->dev_private;
- dp = platform_get_drvdata(pdev);
+ dp = container_of(g_dp_display,
+ struct dp_display_private, dp_display);
if (!dp) {
DRM_ERROR("Invalid DP driver data\n");
return;
@@ -348,7 +348,8 @@ static int dp_display_usbpd_configure_cb(struct device *dev)
goto end;
}
- dp = dev_get_drvdata(dev);
+ dp = container_of(g_dp_display,
+ struct dp_display_private, dp_display);
if (!dp) {
DRM_ERROR("no driver data found\n");
rc = -ENODEV;
@@ -372,7 +373,8 @@ static int dp_display_usbpd_disconnect_cb(struct device
*dev)
int rc = 0;
struct dp_display_private *dp;
- dp = dev_get_drvdata(dev);
+ dp = container_of(g_dp_display,
+ struct dp_display_private, dp_display);
dp_add_event(dp, EV_USER_NOTIFICATION, false, 0);
@@ -424,7 +426,8 @@ static int dp_display_usbpd_attention_cb(struct device *dev)
return -EINVAL;
}
- dp = dev_get_drvdata(dev);
+ dp = container_of(g_dp_display,
+ struct dp_display_private, dp_display);
if (!dp) {
DRM_ERROR("no driver data found\n");
return -ENODEV;
@@ -995,11 +998,12 @@ static int dp_display_probe(struct platform_device *pdev)
return -EPROBE_DEFER;
}
- platform_set_drvdata(pdev, dp);
-
mutex_init(>event_mutex);
+
g_dp_display = >dp_display;
+ platform_set_drvdata(pdev, g_dp_display);
+
rc = component_add(>dev, _display_comp_ops);
if (rc) {
DRM_ERROR("component add failed, rc=%d\n", rc);
@@ -1013,7 +1017,8 @@ static int dp_display_remove(struct platform_device *pdev)
{
struct dp_display_private *dp;
- dp = platform_get_drvdata(pdev);
+ dp = container_of(g_dp_display,
+ struct dp_display_private, dp_display);
dp_display_deinit_sub_modules(dp);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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[PATCH v3 0/5] add audio support for Display Port on MSM
This series adds audio support for DP on MSM chipsets. It leverages the hdmi-codec interface [1] to communicate between the Display Port driver and the audio subsystem. These changes depend on the series [2] which adds Display Port support to MSM chipsets. [1] https://patchwork.kernel.org/patch/11047883/ [2] https://patchwork.kernel.org/patch/11708677/ changes in v2: - fix up a compilation issue on drm-next branch changes in v3: - add support to synchronize DP driver and audio during shutdown Abhinav Kumar (5): drm/msm/dp: store dp_display in the driver data drm/msm/dp: add audio support for Display Port on MSM drm/msm/dp: add hook_plugged_cb hdmi-codec op for MSM DP driver drm/msm/dp: signal the hotplug disconnect in the event handler drm/msm/dp: wait for audio notification before disabling clocks drivers/gpu/drm/msm/Makefile| 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 + drivers/gpu/drm/msm/dp/dp_audio.c | 638 drivers/gpu/drm/msm/dp/dp_audio.h | 72 +++ drivers/gpu/drm/msm/dp/dp_catalog.c | 192 ++ drivers/gpu/drm/msm/dp/dp_catalog.h | 29 + drivers/gpu/drm/msm/dp/dp_display.c | 126 +++- drivers/gpu/drm/msm/dp/dp_display.h | 11 + 8 files changed, 1066 insertions(+), 11 deletions(-) create mode 100644 drivers/gpu/drm/msm/dp/dp_audio.c create mode 100644 drivers/gpu/drm/msm/dp/dp_audio.h -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 20/20] drm/msm: show process names in gem_describe
From: Rob Clark
In $debugfs/gem we already show any vma(s) associated with an object.
Also show process names if the vma's address space is a per-process
address space.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
drivers/gpu/drm/msm/msm_gem.c | 25 +
drivers/gpu/drm/msm/msm_gem.h | 5 +
drivers/gpu/drm/msm/msm_gem_vma.c | 1 +
drivers/gpu/drm/msm/msm_gpu.c | 8 +---
drivers/gpu/drm/msm/msm_gpu.h | 2 +-
6 files changed, 34 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 8e70d220bba8..8d5c4f98c332 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -597,7 +597,7 @@ static int context_init(struct drm_device *dev, struct
drm_file *file)
kref_init(>ref);
msm_submitqueue_init(dev, ctx);
- ctx->aspace = msm_gpu_create_private_address_space(priv->gpu);
+ ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
file->driver_priv = ctx;
return 0;
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 3cb7aeb93fd3..76a6c5271e57 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -842,11 +842,28 @@ void msm_gem_describe(struct drm_gem_object *obj, struct
seq_file *m)
seq_puts(m, " vmas:");
- list_for_each_entry(vma, _obj->vmas, list)
- seq_printf(m, " [%s: %08llx,%s,inuse=%d]",
- vma->aspace != NULL ? vma->aspace->name : NULL,
- vma->iova, vma->mapped ? "mapped" : "unmapped",
+ list_for_each_entry(vma, _obj->vmas, list) {
+ const char *name, *comm;
+ if (vma->aspace) {
+ struct msm_gem_address_space *aspace =
vma->aspace;
+ struct task_struct *task =
+ get_pid_task(aspace->pid, PIDTYPE_PID);
+ if (task) {
+ comm = kstrdup(task->comm, GFP_KERNEL);
+ } else {
+ comm = NULL;
+ }
+ name = aspace->name;
+ } else {
+ name = comm = NULL;
+ }
+ seq_printf(m, " [%s%s%s: aspace=%p,
%08llx,%s,inuse=%d]",
+ name, comm ? ":" : "", comm ? comm : "",
+ vma->aspace, vma->iova,
+ vma->mapped ? "mapped" : "unmapped",
vma->inuse);
+ kfree(comm);
+ }
seq_puts(m, "\n");
}
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index 9c573c4269cb..7b1c7a5f8eef 100644
--- a/drivers/gpu/drm/msm/msm_gem.h
+++ b/drivers/gpu/drm/msm/msm_gem.h
@@ -24,6 +24,11 @@ struct msm_gem_address_space {
spinlock_t lock; /* Protects drm_mm node allocation/removal */
struct msm_mmu *mmu;
struct kref kref;
+
+ /* For address spaces associated with a specific process, this
+* will be non-NULL:
+*/
+ struct pid *pid;
};
struct msm_gem_vma {
diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c
b/drivers/gpu/drm/msm/msm_gem_vma.c
index 29cc1305cf37..80a8a266d68f 100644
--- a/drivers/gpu/drm/msm/msm_gem_vma.c
+++ b/drivers/gpu/drm/msm/msm_gem_vma.c
@@ -17,6 +17,7 @@ msm_gem_address_space_destroy(struct kref *kref)
drm_mm_takedown(>mm);
if (aspace->mmu)
aspace->mmu->funcs->destroy(aspace->mmu);
+ put_pid(aspace->pid);
kfree(aspace);
}
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 951850804d77..ac8961187a73 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -825,10 +825,9 @@ static int get_clocks(struct platform_device *pdev, struct
msm_gpu *gpu)
/* Return a new address space for a msm_drm_private instance */
struct msm_gem_address_space *
-msm_gpu_create_private_address_space(struct msm_gpu *gpu)
+msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct
*task)
{
struct msm_gem_address_space *aspace = NULL;
-
if (!gpu)
return NULL;
@@ -836,8 +835,11 @@ msm_gpu_create_private_address_space(struct msm_gpu *gpu)
* If the target doesn't support private address spaces then return
* the global one
*/
- if (gpu->funcs->create_private_address_space)
+ if (gpu->funcs->create_private_address_space) {
aspace = gpu->funcs->create_private_address_space(gpu);
+ if (!IS_ERR(aspace))
+ aspace->pid =
[PATCH 15/20] drm/msm: Add support for private address space instances
From: Jordan Crouse
Add support for allocating private address space instances. Targets that
support per-context pagetables should implement their own function to
allocate private address spaces.
The default will return a pointer to the global address space.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c | 13 +++--
drivers/gpu/drm/msm/msm_drv.h | 5 +
drivers/gpu/drm/msm/msm_gem_vma.c | 9 +
drivers/gpu/drm/msm/msm_gpu.c | 22 ++
drivers/gpu/drm/msm/msm_gpu.h | 5 +
5 files changed, 48 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 01845a3b8d52..8e70d220bba8 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -597,7 +597,7 @@ static int context_init(struct drm_device *dev, struct
drm_file *file)
kref_init(>ref);
msm_submitqueue_init(dev, ctx);
- ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;
+ ctx->aspace = msm_gpu_create_private_address_space(priv->gpu);
file->driver_priv = ctx;
return 0;
@@ -780,18 +780,19 @@ static int msm_ioctl_gem_cpu_fini(struct drm_device *dev,
void *data,
}
static int msm_ioctl_gem_info_iova(struct drm_device *dev,
- struct drm_gem_object *obj, uint64_t *iova)
+ struct drm_file *file, struct drm_gem_object *obj,
+ uint64_t *iova)
{
- struct msm_drm_private *priv = dev->dev_private;
+ struct msm_file_private *ctx = file->driver_priv;
- if (!priv->gpu)
+ if (!ctx->aspace)
return -EINVAL;
/*
* Don't pin the memory here - just get an address so that userspace can
* be productive
*/
- return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
+ return msm_gem_get_iova(obj, ctx->aspace, iova);
}
static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
@@ -830,7 +831,7 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void
*data,
args->value = msm_gem_mmap_offset(obj);
break;
case MSM_INFO_GET_IOVA:
- ret = msm_ioctl_gem_info_iova(dev, obj, >value);
+ ret = msm_ioctl_gem_info_iova(dev, file, obj, >value);
break;
case MSM_INFO_SET_NAME:
/* length check should leave room for terminating null: */
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 4561bfb5e745..2ca9c3c03845 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -249,6 +249,10 @@ int msm_gem_map_vma(struct msm_gem_address_space *aspace,
void msm_gem_close_vma(struct msm_gem_address_space *aspace,
struct msm_gem_vma *vma);
+
+struct msm_gem_address_space *
+msm_gem_address_space_get(struct msm_gem_address_space *aspace);
+
void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
struct msm_gem_address_space *
@@ -434,6 +438,7 @@ static inline void __msm_file_private_destroy(struct kref
*kref)
struct msm_file_private *ctx = container_of(kref,
struct msm_file_private, ref);
+ msm_gem_address_space_put(ctx->aspace);
kfree(ctx);
}
diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c
b/drivers/gpu/drm/msm/msm_gem_vma.c
index 5f6a11211b64..29cc1305cf37 100644
--- a/drivers/gpu/drm/msm/msm_gem_vma.c
+++ b/drivers/gpu/drm/msm/msm_gem_vma.c
@@ -27,6 +27,15 @@ void msm_gem_address_space_put(struct msm_gem_address_space
*aspace)
kref_put(>kref, msm_gem_address_space_destroy);
}
+struct msm_gem_address_space *
+msm_gem_address_space_get(struct msm_gem_address_space *aspace)
+{
+ if (!IS_ERR_OR_NULL(aspace))
+ kref_get(>kref);
+
+ return aspace;
+}
+
/* Actually unmap memory for the vma */
void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
struct msm_gem_vma *vma)
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index e1a3cbe25a0c..951850804d77 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -823,6 +823,28 @@ static int get_clocks(struct platform_device *pdev, struct
msm_gpu *gpu)
return 0;
}
+/* Return a new address space for a msm_drm_private instance */
+struct msm_gem_address_space *
+msm_gpu_create_private_address_space(struct msm_gpu *gpu)
+{
+ struct msm_gem_address_space *aspace = NULL;
+
+ if (!gpu)
+ return NULL;
+
+ /*
+* If the target doesn't support private address spaces then return
+* the global one
+*/
+ if (gpu->funcs->create_private_address_space)
+ aspace = gpu->funcs->create_private_address_space(gpu);
+
+ if (IS_ERR_OR_NULL(aspace))
+ aspace = msm_gem_address_space_get(gpu->aspace);
+
+ return aspace;
+}
+
int msm_gpu_init(struct
[PATCH 19/20] iommu/arm-smmu: add a way for implementations to influence SCTLR
From: Rob Clark
For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
pending translations are not terminated on iova fault. Otherwise
a terminated CP read could hang the GPU by returning invalid
command-stream data.
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++
drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++
drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++
3 files changed, 12 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 5640d9960610..2aa6249050ff 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -127,6 +127,12 @@ static int qcom_adreno_smmu_init_context(struct
arm_smmu_domain *smmu_domain,
(smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
+ /*
+* On the GPU device we want to process subsequent transactions after a
+* fault to keep the GPU from hanging
+*/
+ smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF;
+
/*
* Initialize private interface with GPU:
*/
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index e63a480d7f71..bbec5793faf8 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device
*smmu, int idx)
if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
reg |= ARM_SMMU_SCTLR_E;
+ reg |= cfg->sctlr_set;
+ reg &= ~cfg->sctlr_clr;
+
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h
b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index cd75a33967bb..2df3a70a8a41 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -144,6 +144,7 @@ enum arm_smmu_cbar_type {
#define ARM_SMMU_CB_SCTLR 0x0
#define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12)
#define ARM_SMMU_SCTLR_CFCFG BIT(7)
+#define ARM_SMMU_SCTLR_HUPCF BIT(8)
#define ARM_SMMU_SCTLR_CFIEBIT(6)
#define ARM_SMMU_SCTLR_CFREBIT(5)
#define ARM_SMMU_SCTLR_E BIT(4)
@@ -341,6 +342,8 @@ struct arm_smmu_cfg {
u16 asid;
u16 vmid;
};
+ u32 sctlr_set;/* extra bits to set in
SCTLR */
+ u32 sctlr_clr;/* bits to mask in SCTLR
*/
enum arm_smmu_cbar_type cbar;
enum arm_smmu_context_fmt fmt;
};
--
2.26.2
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[PATCH 18/20] arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMU
From: Rob Clark
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables and per-instance pagetables for drm/msm.
Signed-off-by: Rob Clark
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index d46b3833e52f..61ae67186691 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1937,7 +1937,7 @@ opp-18000 {
};
adreno_smmu: iommu@504 {
- compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
+ compatible = "qcom,adreno-smmu", "qcom,smmu-v2";
reg = <0 0x0504 0 0x1>;
#iommu-cells = <1>;
#global-interrupts = <2>;
--
2.26.2
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[PATCH 12/20] drm/msm: Drop context arg to gpu->submit()
From: Jordan Crouse
Now that we can get the ctx from the submitqueue, the extra arg is
redundant.
Signed-off-by: Jordan Crouse
[split out of previous patch to reduce churny noise]
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ++---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +--
drivers/gpu/drm/msm/msm_gem_submit.c| 2 +-
drivers/gpu/drm/msm/msm_gpu.c | 9 -
drivers/gpu/drm/msm/msm_gpu.h | 6 ++
7 files changed, 17 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 9e63a190642c..eff2439ea57b 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -43,8 +43,7 @@ static void a5xx_flush(struct msm_gpu *gpu, struct
msm_ringbuffer *ring)
gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr);
}
-static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit
*submit,
- struct msm_file_private *ctx)
+static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit
*submit)
{
struct msm_drm_private *priv = gpu->dev->dev_private;
struct msm_ringbuffer *ring = submit->ring;
@@ -57,7 +56,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct
msm_gem_submit *submit
case MSM_SUBMIT_CMD_IB_TARGET_BUF:
break;
case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
- if (priv->lastctx == ctx)
+ if (priv->lastctx == submit->queue->ctx)
break;
/* fall-thru */
case MSM_SUBMIT_CMD_BUF:
@@ -103,8 +102,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct
msm_gem_submit *submit
msm_gpu_retire(gpu);
}
-static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
- struct msm_file_private *ctx)
+static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
@@ -114,7 +112,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit,
if (IS_ENABLED(CONFIG_DRM_MSM_GPU_SUDO) && submit->in_rb) {
priv->lastctx = NULL;
- a5xx_submit_in_rb(gpu, submit, ctx);
+ a5xx_submit_in_rb(gpu, submit);
return;
}
@@ -148,7 +146,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit,
case MSM_SUBMIT_CMD_IB_TARGET_BUF:
break;
case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
- if (priv->lastctx == ctx)
+ if (priv->lastctx == submit->queue->ctx)
break;
/* fall-thru */
case MSM_SUBMIT_CMD_BUF:
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index c5a3e4d4c007..5eabb0109577 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -81,8 +81,7 @@ static void get_stats_counter(struct msm_ringbuffer *ring,
u32 counter,
OUT_RING(ring, upper_32_bits(iova));
}
-static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
- struct msm_file_private *ctx)
+static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
{
unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
struct msm_drm_private *priv = gpu->dev->dev_private;
@@ -115,7 +114,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit,
case MSM_SUBMIT_CMD_IB_TARGET_BUF:
break;
case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
- if (priv->lastctx == ctx)
+ if (priv->lastctx == submit->queue->ctx)
break;
/* fall-thru */
case MSM_SUBMIT_CMD_BUF:
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index d2dbb6968cba..533a34b4cce2 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -457,8 +457,7 @@ void adreno_recover(struct msm_gpu *gpu)
}
}
-void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
- struct msm_file_private *ctx)
+void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct msm_drm_private *priv = gpu->dev->dev_private;
@@ -472,7 +471,7 @@ void adreno_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit,
break;
case
[PATCH 10/20] dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU
From: Jordan Crouse Every Qcom Adreno GPU has an embedded SMMU for its own use. These devices depend on unique features such as split pagetables, different stall/halt requirements and other settings. Identify them with a compatible string so that they can be identified in the arm-smmu implementation specific code. Signed-off-by: Jordan Crouse Reviewed-by: Rob Herring Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 503160a7b9a0..5ec5d0d691f6 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -40,6 +40,10 @@ properties: - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - const: arm,mmu-500 + - description: Qcom Adreno GPUs implementing "arm,smmu-v2" +items: + - const: qcom,adreno-smmu + - const: qcom,smmu-v2 - description: Marvell SoCs implementing "arm,mmu-500" items: - const: marvell,ap806-smmu-500 -- 2.26.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 09/20] iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU
From: Jordan Crouse
Add a special implementation for the SMMU attached to most Adreno GPU
target triggered from the qcom,adreno-smmu compatible string.
The new Adreno SMMU implementation will enable split pagetables
(TTBR1) for the domain attached to the GPU device (SID 0) and
hard code it context bank 0 so the GPU hardware can implement
per-instance pagetables.
Co-developed-by: Rob Clark
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 +
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 149 -
drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 +
3 files changed, 151 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
index 88f17cc33023..d199b4bff15d 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
@@ -223,6 +223,9 @@ struct arm_smmu_device *arm_smmu_impl_init(struct
arm_smmu_device *smmu)
of_device_is_compatible(np, "qcom,sm8250-smmu-500"))
return qcom_smmu_impl_init(smmu);
+ if (of_device_is_compatible(smmu->dev->of_node, "qcom,adreno-smmu"))
+ return qcom_adreno_smmu_impl_init(smmu);
+
if (of_device_is_compatible(np, "marvell,ap806-smmu-500"))
smmu->impl = _mmu500_impl;
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index be4318044f96..5640d9960610 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -3,6 +3,7 @@
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
+#include
#include
#include
@@ -12,6 +13,132 @@ struct qcom_smmu {
struct arm_smmu_device smmu;
};
+#define QCOM_ADRENO_SMMU_GPU_SID 0
+
+static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
+{
+ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+ int i;
+
+ /*
+* The GPU will always use SID 0 so that is a handy way to uniquely
+* identify it and configure it for per-instance pagetables
+*/
+ for (i = 0; i < fwspec->num_ids; i++) {
+ u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);
+
+ if (sid == QCOM_ADRENO_SMMU_GPU_SID)
+ return true;
+ }
+
+ return false;
+}
+
+static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
+ const void *cookie)
+{
+ struct arm_smmu_domain *smmu_domain = (void *)cookie;
+ struct io_pgtable *pgtable =
+ io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
+ return >cfg;
+}
+
+/*
+ * Local implementation to configure TTBR0 with the specified pagetable config.
+ * The GPU driver will call this to enable TTBR0 when per-instance pagetables
+ * are active
+ */
+
+static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
+ const struct io_pgtable_cfg *pgtbl_cfg)
+{
+ struct arm_smmu_domain *smmu_domain = (void *)cookie;
+ struct io_pgtable *pgtable =
io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
+ struct arm_smmu_cfg *cfg = _domain->cfg;
+ struct arm_smmu_cb *cb = _domain->smmu->cbs[cfg->cbndx];
+
+ /* The domain must have split pagetables already enabled */
+ if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
+ return -EINVAL;
+
+ /* If the pagetable config is NULL, disable TTBR0 */
+ if (!pgtbl_cfg) {
+ /* Do nothing if it is already disabled */
+ if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
+ return -EINVAL;
+
+ /* Set TCR to the original configuration */
+ cb->tcr[0] = arm_smmu_lpae_tcr(>cfg);
+ cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
+ } else {
+ u32 tcr = cb->tcr[0];
+
+ /* Don't call this again if TTBR0 is already enabled */
+ if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
+ return -EINVAL;
+
+ tcr |= arm_smmu_lpae_tcr(pgtbl_cfg);
+ tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1);
+
+ cb->tcr[0] = tcr;
+ cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
+ cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
+ }
+
+ arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
+
+ return 0;
+}
+
+static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain
*smmu_domain,
+ struct device *dev, int start, int count)
+{
+ struct arm_smmu_device *smmu = smmu_domain->smmu;
+
+ /*
+* Assign context bank 0 to the GPU device so the GPU hardware can
+* switch pagetables
+*/
+ if (qcom_adreno_smmu_is_gpu_device(dev)) {
+ start = 0;
+ count = 1;
+ } else {
+ start
[PATCH 16/20] drm/msm/a6xx: Add support for per-instance pagetables
From: Jordan Crouse
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 63 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
3 files changed, 65 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 5eabb0109577..d7ad6c78d787 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -81,6 +81,49 @@ static void get_stats_counter(struct msm_ringbuffer *ring,
u32 counter,
OUT_RING(ring, upper_32_bits(iova));
}
+static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
+ struct msm_ringbuffer *ring, struct msm_file_private *ctx)
+{
+ phys_addr_t ttbr;
+ u32 asid;
+ u64 memptr = rbmemptr(ring, ttbr0);
+
+ if (ctx == a6xx_gpu->cur_ctx)
+ return;
+
+ if (msm_iommu_pagetable_params(ctx->aspace->mmu, , ))
+ return;
+
+ /* Execute the table update */
+ OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
+ OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
+
+ OUT_RING(ring,
+ CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
+ CP_SMMU_TABLE_UPDATE_1_ASID(asid));
+ OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
+ OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
+
+ /*
+* Write the new TTBR0 to the memstore. This is good for debugging.
+*/
+ OUT_PKT7(ring, CP_MEM_WRITE, 4);
+ OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
+ OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
+ OUT_RING(ring, lower_32_bits(ttbr));
+ OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));
+
+ /*
+* And finally, trigger a uche flush to be sure there isn't anything
+* lingering in that part of the GPU
+*/
+
+ OUT_PKT7(ring, CP_EVENT_WRITE, 1);
+ OUT_RING(ring, 0x31);
+
+ a6xx_gpu->cur_ctx = ctx;
+}
+
static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
{
unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
@@ -90,6 +133,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit)
struct msm_ringbuffer *ring = submit->ring;
unsigned int i;
+ a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
+
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
rbmemptr_stats(ring, index, cpcycles_start));
@@ -696,6 +741,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
/* Always come up on rb 0 */
a6xx_gpu->cur_ring = gpu->rb[0];
+ a6xx_gpu->cur_ctx = NULL;
+
/* Enable the SQE_to start the CP engine */
gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
@@ -1008,6 +1055,21 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
return (unsigned long)busy_time;
}
+static struct msm_gem_address_space *
+a6xx_create_private_address_space(struct msm_gpu *gpu)
+{
+ struct msm_gem_address_space *aspace = NULL;
+ struct msm_mmu *mmu;
+
+ mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
+
+ if (!IS_ERR(mmu))
+ aspace = msm_gem_address_space_create(mmu,
+ "gpu", 0x1ULL, 0x1ULL);
+
+ return aspace;
+}
+
static const struct adreno_gpu_funcs funcs = {
.base = {
.get_param = adreno_get_param,
@@ -1031,6 +1093,7 @@ static const struct adreno_gpu_funcs funcs = {
.gpu_state_put = a6xx_gpu_state_put,
#endif
.create_address_space = adreno_iommu_create_address_space,
+ .create_private_address_space =
a6xx_create_private_address_space,
},
.get_timestamp = a6xx_get_timestamp,
};
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 03ba60d5b07f..da22d7549d9b 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -19,6 +19,7 @@ struct a6xx_gpu {
uint64_t sqe_iova;
struct msm_ringbuffer *cur_ring;
+ struct msm_file_private *cur_ctx;
struct a6xx_gmu gmu;
};
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h
b/drivers/gpu/drm/msm/msm_ringbuffer.h
index 7764373d0ed2..0987d6bf848c 100644
--- a/drivers/gpu/drm/msm/msm_ringbuffer.h
+++ b/drivers/gpu/drm/msm/msm_ringbuffer.h
@@ -31,6 +31,7 @@ struct msm_rbmemptrs {
volatile uint32_t fence;
volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT];
+ volatile u64 ttbr0;
};
struct msm_ringbuffer {
--
2.26.2
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[PATCH 11/20] drm/msm: Add a context pointer to the submitqueue
From: Jordan Crouse
Each submitqueue is attached to a context. Add a pointer to the
context to the submitqueue at create time and refcount it so
that it stays around through the life of the queue.
Co-developed-by: Rob Clark
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
drivers/gpu/drm/msm/msm_drv.h | 20
drivers/gpu/drm/msm/msm_gem.h | 1 +
drivers/gpu/drm/msm/msm_gem_submit.c | 6 +++---
drivers/gpu/drm/msm/msm_gpu.h | 1 +
drivers/gpu/drm/msm/msm_submitqueue.c | 3 +++
6 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 7d641c7e3514..01845a3b8d52 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -594,6 +594,7 @@ static int context_init(struct drm_device *dev, struct
drm_file *file)
if (!ctx)
return -ENOMEM;
+ kref_init(>ref);
msm_submitqueue_init(dev, ctx);
ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;
@@ -615,7 +616,7 @@ static int msm_open(struct drm_device *dev, struct drm_file
*file)
static void context_close(struct msm_file_private *ctx)
{
msm_submitqueue_close(ctx);
- kfree(ctx);
+ msm_file_private_put(ctx);
}
static void msm_postclose(struct drm_device *dev, struct drm_file *file)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index af259b0573ea..4561bfb5e745 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -57,6 +57,7 @@ struct msm_file_private {
struct list_head submitqueues;
int queueid;
struct msm_gem_address_space *aspace;
+ struct kref ref;
};
enum msm_mdp_plane_property {
@@ -428,6 +429,25 @@ void msm_submitqueue_close(struct msm_file_private *ctx);
void msm_submitqueue_destroy(struct kref *kref);
+static inline void __msm_file_private_destroy(struct kref *kref)
+{
+ struct msm_file_private *ctx = container_of(kref,
+ struct msm_file_private, ref);
+
+ kfree(ctx);
+}
+
+static inline void msm_file_private_put(struct msm_file_private *ctx)
+{
+ kref_put(>ref, __msm_file_private_destroy);
+}
+
+static inline struct msm_file_private *msm_file_private_get(
+ struct msm_file_private *ctx)
+{
+ kref_get(>ref);
+ return ctx;
+}
#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index 972490b14ba5..9c573c4269cb 100644
--- a/drivers/gpu/drm/msm/msm_gem.h
+++ b/drivers/gpu/drm/msm/msm_gem.h
@@ -142,6 +142,7 @@ struct msm_gem_submit {
bool valid; /* true if no cmdstream patching needed */
bool in_rb; /* "sudo" mode, copy cmds into RB */
struct msm_ringbuffer *ring;
+ struct msm_file_private *ctx;
unsigned int nr_cmds;
unsigned int nr_bos;
u32 ident; /* A "identifier" for the submit for logging */
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index 8cb9aa15ff90..1464b04d25d3 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -27,7 +27,7 @@
#define BO_PINNED 0x2000
static struct msm_gem_submit *submit_create(struct drm_device *dev,
- struct msm_gpu *gpu, struct msm_gem_address_space *aspace,
+ struct msm_gpu *gpu,
struct msm_gpu_submitqueue *queue, uint32_t nr_bos,
uint32_t nr_cmds)
{
@@ -43,7 +43,7 @@ static struct msm_gem_submit *submit_create(struct drm_device
*dev,
return NULL;
submit->dev = dev;
- submit->aspace = aspace;
+ submit->aspace = queue->ctx->aspace;
submit->gpu = gpu;
submit->fence = NULL;
submit->cmd = (void *)>bos[nr_bos];
@@ -677,7 +677,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
}
}
- submit = submit_create(dev, gpu, ctx->aspace, queue, args->nr_bos,
+ submit = submit_create(dev, gpu, queue, args->nr_bos,
args->nr_cmds);
if (!submit) {
ret = -ENOMEM;
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index f91b141add75..97c527e98391 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -190,6 +190,7 @@ struct msm_gpu_submitqueue {
u32 flags;
u32 prio;
int faults;
+ struct msm_file_private *ctx;
struct list_head node;
struct kref ref;
};
diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c
b/drivers/gpu/drm/msm/msm_submitqueue.c
index 90c9d84e6155..c3d206105d28 100644
--- a/drivers/gpu/drm/msm/msm_submitqueue.c
+++ b/drivers/gpu/drm/msm/msm_submitqueue.c
@@ -12,6 +12,8 @@ void
[PATCH 07/20] drm/msm: set adreno_smmu as gpu's drvdata
From: Rob Clark
This will be populated by adreno-smmu, to provide a way for coordinating
enabling/disabling TTBR0 translation.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 2 --
drivers/gpu/drm/msm/msm_gpu.c | 2 +-
drivers/gpu/drm/msm/msm_gpu.h | 6 +-
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 26664e1b30c0..58e03b20e1c7 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -417,8 +417,6 @@ static int adreno_bind(struct device *dev, struct device
*master, void *data)
return PTR_ERR(gpu);
}
- dev_set_drvdata(dev, gpu);
-
return 0;
}
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 6aa9e04e52e7..806eb0957280 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -892,7 +892,7 @@ int msm_gpu_init(struct drm_device *drm, struct
platform_device *pdev,
gpu->gpu_cx = NULL;
gpu->pdev = pdev;
- platform_set_drvdata(pdev, gpu);
+ platform_set_drvdata(pdev, >adreno_smmu);
msm_devfreq_init(gpu);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 8bda7beaed4b..f91b141add75 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -7,6 +7,7 @@
#ifndef __MSM_GPU_H__
#define __MSM_GPU_H__
+#include
#include
#include
#include
@@ -73,6 +74,8 @@ struct msm_gpu {
struct platform_device *pdev;
const struct msm_gpu_funcs *funcs;
+ struct adreno_smmu_priv adreno_smmu;
+
/* performance counters (hw & sw): */
spinlock_t perf_lock;
bool perfcntr_active;
@@ -143,7 +146,8 @@ struct msm_gpu {
static inline struct msm_gpu *dev_to_gpu(struct device *dev)
{
- return dev_get_drvdata(dev);
+ struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
+ return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
}
/* It turns out that all targets use the same ringbuffer size */
--
2.26.2
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[PATCH 17/20] arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU
From: Jordan Crouse
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables and per-instance pagetables for drm/msm.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2884577dcb77..6a9adaa401a9 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4058,7 +4058,7 @@ opp-25700 {
};
adreno_smmu: iommu@504 {
- compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
+ compatible = "qcom,adreno-smmu", "qcom,smmu-v2";
reg = <0 0x504 0 0x1>;
#iommu-cells = <1>;
#global-interrupts = <2>;
--
2.26.2
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[PATCH 13/20] drm/msm: Set the global virtual address range from the IOMMU domain
From: Jordan Crouse
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--
drivers/gpu/drm/msm/msm_iommu.c | 7 +++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 533a34b4cce2..34e6242c1767 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -192,9 +192,18 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
struct iommu_domain *iommu = iommu_domain_alloc(_bus_type);
struct msm_mmu *mmu = msm_iommu_new(>dev, iommu);
struct msm_gem_address_space *aspace;
+ u64 start, size;
- aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,
- 0x - SZ_16M);
+ /*
+* Use the aperture start or SZ_16M, whichever is greater. This will
+* ensure that we align with the allocated pagetable range while still
+* allowing room in the lower 32 bits for GMEM and whatnot
+*/
+ start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
+ size = iommu->geometry.aperture_end - start + 1;
+
+ aspace = msm_gem_address_space_create(mmu, "gpu",
+ start & GENMASK(48, 0), size);
if (IS_ERR(aspace) && !IS_ERR(mmu))
mmu->funcs->destroy(mmu);
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index 3a381a9674c9..1b6635504069 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -36,6 +36,10 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova,
struct msm_iommu *iommu = to_msm_iommu(mmu);
size_t ret;
+ /* The arm-smmu driver expects the addresses to be sign extended */
+ if (iova & BIT_ULL(48))
+ iova |= GENMASK_ULL(63, 49);
+
ret = iommu_map_sg(iommu->domain, iova, sgt->sgl, sgt->nents, prot);
WARN_ON(!ret);
@@ -46,6 +50,9 @@ static int msm_iommu_unmap(struct msm_mmu *mmu, uint64_t
iova, size_t len)
{
struct msm_iommu *iommu = to_msm_iommu(mmu);
+ if (iova & BIT_ULL(48))
+ iova |= GENMASK_ULL(63, 49);
+
iommu_unmap(iommu->domain, iova, len);
return 0;
--
2.26.2
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[PATCH 14/20] drm/msm: Add support to create a local pagetable
From: Jordan Crouse
Add support to create a io-pgtable for use by targets that support
per-instance pagetables. In order to support per-instance pagetables the
GPU SMMU device needs to have the qcom,adreno-smmu compatible string and
split pagetables enabled.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpummu.c | 2 +-
drivers/gpu/drm/msm/msm_iommu.c | 199 ++-
drivers/gpu/drm/msm/msm_mmu.h| 16 ++-
3 files changed, 214 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpummu.c b/drivers/gpu/drm/msm/msm_gpummu.c
index 310a31b05faa..aab121f4beb7 100644
--- a/drivers/gpu/drm/msm/msm_gpummu.c
+++ b/drivers/gpu/drm/msm/msm_gpummu.c
@@ -102,7 +102,7 @@ struct msm_mmu *msm_gpummu_new(struct device *dev, struct
msm_gpu *gpu)
}
gpummu->gpu = gpu;
- msm_mmu_init(>base, dev, );
+ msm_mmu_init(>base, dev, , MSM_MMU_GPUMMU);
return >base;
}
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index 1b6635504069..697cc0a059d6 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -4,15 +4,210 @@
* Author: Rob Clark
*/
+#include
+#include
#include "msm_drv.h"
#include "msm_mmu.h"
struct msm_iommu {
struct msm_mmu base;
struct iommu_domain *domain;
+ atomic_t pagetables;
};
+
#define to_msm_iommu(x) container_of(x, struct msm_iommu, base)
+struct msm_iommu_pagetable {
+ struct msm_mmu base;
+ struct msm_mmu *parent;
+ struct io_pgtable_ops *pgtbl_ops;
+ phys_addr_t ttbr;
+ u32 asid;
+};
+static struct msm_iommu_pagetable *to_pagetable(struct msm_mmu *mmu)
+{
+ return container_of(mmu, struct msm_iommu_pagetable, base);
+}
+
+static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova,
+ size_t size)
+{
+ struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
+ struct io_pgtable_ops *ops = pagetable->pgtbl_ops;
+ size_t unmapped = 0;
+
+ /* Unmap the block one page at a time */
+ while (size) {
+ unmapped += ops->unmap(ops, iova, 4096, NULL);
+ iova += 4096;
+ size -= 4096;
+ }
+
+ iommu_flush_tlb_all(to_msm_iommu(pagetable->parent)->domain);
+
+ return (unmapped == size) ? 0 : -EINVAL;
+}
+
+static int msm_iommu_pagetable_map(struct msm_mmu *mmu, u64 iova,
+ struct sg_table *sgt, size_t len, int prot)
+{
+ struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
+ struct io_pgtable_ops *ops = pagetable->pgtbl_ops;
+ struct scatterlist *sg;
+ size_t mapped = 0;
+ u64 addr = iova;
+ unsigned int i;
+
+ for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+ size_t size = sg->length;
+ phys_addr_t phys = sg_phys(sg);
+
+ /* Map the block one page at a time */
+ while (size) {
+ if (ops->map(ops, addr, phys, 4096, prot, GFP_KERNEL)) {
+ msm_iommu_pagetable_unmap(mmu, iova, mapped);
+ return -EINVAL;
+ }
+
+ phys += 4096;
+ addr += 4096;
+ size -= 4096;
+ mapped += 4096;
+ }
+ }
+
+ return 0;
+}
+
+static void msm_iommu_pagetable_destroy(struct msm_mmu *mmu)
+{
+ struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
+ struct msm_iommu *iommu = to_msm_iommu(pagetable->parent);
+ struct adreno_smmu_priv *adreno_smmu =
+ dev_get_drvdata(pagetable->parent->dev);
+
+ /*
+* If this is the last attached pagetable for the parent,
+* disable TTBR0 in the arm-smmu driver
+*/
+ if (atomic_dec_return(>pagetables) == 0)
+ adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, NULL);
+
+ free_io_pgtable_ops(pagetable->pgtbl_ops);
+ kfree(pagetable);
+}
+
+int msm_iommu_pagetable_params(struct msm_mmu *mmu,
+ phys_addr_t *ttbr, int *asid)
+{
+ struct msm_iommu_pagetable *pagetable;
+
+ if (mmu->type != MSM_MMU_IOMMU_PAGETABLE)
+ return -EINVAL;
+
+ pagetable = to_pagetable(mmu);
+
+ if (ttbr)
+ *ttbr = pagetable->ttbr;
+
+ if (asid)
+ *asid = pagetable->asid;
+
+ return 0;
+}
+
+static const struct msm_mmu_funcs pagetable_funcs = {
+ .map = msm_iommu_pagetable_map,
+ .unmap = msm_iommu_pagetable_unmap,
+ .destroy = msm_iommu_pagetable_destroy,
+};
+
+static void msm_iommu_tlb_flush_all(void *cookie)
+{
+}
+
+static void msm_iommu_tlb_flush_walk(unsigned long iova, size_t size,
+ size_t granule, void *cookie)
+{
+}
+
+static void msm_iommu_tlb_add_page(struct iommu_iotlb_gather *gather,
+ unsigned
[PATCH 05/20] iommu: add private interface for adreno-smmu
From: Rob Clark
This interface will be used for drm/msm to coordinate with the
qcom_adreno_smmu_impl to enable/disable TTBR0 translation.
Once TTBR0 translation is enabled, the GPU's CP (Command Processor)
will directly switch TTBR0 pgtables (and do the necessary TLB inv)
synchronized to the GPU's operation. But help from the SMMU driver
is needed to initially bootstrap TTBR0 translation, which cannot be
done from the GPU.
Since this is a very special case, a private interface is used to
avoid adding highly driver specific things to the public iommu
interface.
Signed-off-by: Rob Clark
---
include/linux/adreno-smmu-priv.h | 36
1 file changed, 36 insertions(+)
create mode 100644 include/linux/adreno-smmu-priv.h
diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h
new file mode 100644
index ..a889f28afb42
--- /dev/null
+++ b/include/linux/adreno-smmu-priv.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 Google, Inc
+ */
+
+#ifndef __ADRENO_SMMU_PRIV_H
+#define __ADRENO_SMMU_PRIV_H
+
+#include
+
+/**
+ * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
+ *
+ * @cookie:An opque token provided by adreno-smmu and passed
+ * back into the callbacks
+ * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank
+ * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A
+ * NULL config disables TTBR0 translation, otherwise
+ * TTBR0 translation is enabled with the specified cfg
+ *
+ * The GPU driver (drm/msm) and adreno-smmu work together for controlling
+ * the GPU's SMMU instance. This is by necessity, as the GPU is directly
+ * updating the SMMU for context switches, while on the other hand we do
+ * not want to duplicate all of the initial setup logic from arm-smmu.
+ *
+ * This private interface is used for the two drivers to coordinate. The
+ * cookie and callback functions are populated when the GPU driver attaches
+ * it's domain.
+ */
+struct adreno_smmu_priv {
+const void *cookie;
+const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
+int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
+};
+
+#endif /* __ADRENO_SMMU_PRIV_H */
\ No newline at end of file
--
2.26.2
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[PATCH 08/20] iommu/arm-smmu: constify some helpers
From: Rob Clark
Sprinkle a few `const`s where helpers don't need write access.
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h
b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index 59ff3fc5c6c8..27c8fc50 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -377,7 +377,7 @@ struct arm_smmu_master_cfg {
s16 smendx[];
};
-static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg)
+static inline u32 arm_smmu_lpae_tcr(const struct io_pgtable_cfg *cfg)
{
u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |
FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |
@@ -398,13 +398,13 @@ static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg
*cfg)
return tcr;
}
-static inline u32 arm_smmu_lpae_tcr2(struct io_pgtable_cfg *cfg)
+static inline u32 arm_smmu_lpae_tcr2(const struct io_pgtable_cfg *cfg)
{
return FIELD_PREP(ARM_SMMU_TCR2_PASIZE, cfg->arm_lpae_s1_cfg.tcr.ips) |
FIELD_PREP(ARM_SMMU_TCR2_SEP, ARM_SMMU_TCR2_SEP_UPSTREAM);
}
-static inline u32 arm_smmu_lpae_vtcr(struct io_pgtable_cfg *cfg)
+static inline u32 arm_smmu_lpae_vtcr(const struct io_pgtable_cfg *cfg)
{
return ARM_SMMU_VTCR_RES1 |
FIELD_PREP(ARM_SMMU_VTCR_PS, cfg->arm_lpae_s2_cfg.vtcr.ps) |
--
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[PATCH 04/20] iommu/arm-smmu: Prepare for the adreno-smmu implementation
From: Jordan Crouse
Do a bit of prep work to add the upcoming adreno-smmu implementation.
Add an hook to allow the implementation to choose which context banks
to allocate.
Move some of the common structs to arm-smmu.h in anticipation of them
being used by the implementations and update some of the existing hooks
to pass more information that the implementation will need.
These modifications will be used by the upcoming Adreno SMMU
implementation to identify the GPU device and properly configure it
for pagetable switching.
Co-developed-by: Rob Clark
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +-
drivers/iommu/arm/arm-smmu/arm-smmu.c | 69 ++
drivers/iommu/arm/arm-smmu/arm-smmu.h | 51 +++-
3 files changed, 68 insertions(+), 54 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
index a9861dcd0884..88f17cc33023 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
@@ -69,7 +69,7 @@ static int cavium_cfg_probe(struct arm_smmu_device *smmu)
}
static int cavium_init_context(struct arm_smmu_domain *smmu_domain,
- struct io_pgtable_cfg *pgtbl_cfg)
+ struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
{
struct cavium_smmu *cs = container_of(smmu_domain->smmu,
struct cavium_smmu, smmu);
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 976d43a7f2ff..e63a480d7f71 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -65,41 +65,10 @@ module_param(disable_bypass, bool, S_IRUGO);
MODULE_PARM_DESC(disable_bypass,
"Disable bypass streams such that incoming transactions from devices
that are not attached to an iommu domain will report an abort back to the
device and will not be allowed to pass through the SMMU.");
-struct arm_smmu_s2cr {
- struct iommu_group *group;
- int count;
- enum arm_smmu_s2cr_type type;
- enum arm_smmu_s2cr_privcfg privcfg;
- u8 cbndx;
-};
-
#define s2cr_init_val (struct arm_smmu_s2cr){ \
.type = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS,\
}
-struct arm_smmu_smr {
- u16 mask;
- u16 id;
- boolvalid;
-};
-
-struct arm_smmu_cb {
- u64 ttbr[2];
- u32 tcr[2];
- u32 mair[2];
- struct arm_smmu_cfg *cfg;
-};
-
-struct arm_smmu_master_cfg {
- struct arm_smmu_device *smmu;
- s16 smendx[];
-};
-#define INVALID_SMENDX -1
-#define cfg_smendx(cfg, fw, i) \
- (i >= fw->num_ids ? INVALID_SMENDX : cfg->smendx[i])
-#define for_each_cfg_sme(cfg, fw, i, idx) \
- for (i = 0; idx = cfg_smendx(cfg, fw, i), i < fw->num_ids; ++i)
-
static bool using_legacy_binding, using_generic_binding;
static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu)
@@ -234,19 +203,6 @@ static int arm_smmu_register_legacy_master(struct device
*dev,
}
#endif /* CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS */
-static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
-{
- int idx;
-
- do {
- idx = find_next_zero_bit(map, end, start);
- if (idx == end)
- return -ENOSPC;
- } while (test_and_set_bit(idx, map));
-
- return idx;
-}
-
static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
{
clear_bit(idx, map);
@@ -578,7 +534,7 @@ static void arm_smmu_init_context_bank(struct
arm_smmu_domain *smmu_domain,
}
}
-static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
+void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
{
u32 reg;
bool stage1;
@@ -665,7 +621,8 @@ static void arm_smmu_write_context_bank(struct
arm_smmu_device *smmu, int idx)
}
static int arm_smmu_init_domain_context(struct iommu_domain *domain,
- struct arm_smmu_device *smmu)
+ struct arm_smmu_device *smmu,
+ struct device *dev)
{
int irq, start, ret = 0;
unsigned long ias, oas;
@@ -780,10 +737,20 @@ static int arm_smmu_init_domain_context(struct
iommu_domain *domain,
ret = -EINVAL;
goto out_unlock;
}
- ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
+
+ smmu_domain->smmu = smmu;
+
+ if (smmu->impl && smmu->impl->alloc_context_bank)
+
[PATCH 00/20] iommu/arm-smmu + drm/msm: per-process GPU pgtables
From: Rob Clark This series adds an Adreno SMMU implementation to arm-smmu to allow GPU hardware pagetable switching. The Adreno GPU has built in capabilities to switch the TTBR0 pagetable during runtime to allow each individual instance or application to have its own pagetable. In order to take advantage of the HW capabilities there are certain requirements needed of the SMMU hardware. This series adds support for an Adreno specific arm-smmu implementation. The new implementation 1) ensures that the GPU domain is always assigned context bank 0, 2) enables split pagetable support (TTBR1) so that the instance specific pagetable can be swapped while the global memory remains in place and 3) shares the current pagetable configuration with the GPU driver to allow it to create its own io-pgtable instances. The series then adds the drm/msm code to enable these features. For targets that support it allocate new pagetables using the io-pgtable configuration shared by the arm-smmu driver and swap them in during runtime. This version of the series merges the previous patchset(s) [1] and [2] with the following improvements: v14: (Respin by Rob) - Minor update to 16/20 (only force ASID to zero in one place) - Addition of sc7180 dtsi patch. v13: (Respin by Rob) - Switch to a private interface between adreno-smmu and GPU driver, dropping the custom domain attr (Will Deacon) - Rework the SCTLR.HUPCF patch to add new fields in smmu_domain->cfg rather than adding new impl hook (Will Deacon) - Drop for_each_cfg_sme() in favor of plain for() loop (Will Deacon) - Fix context refcnt'ing issue which was causing problems with GPU crash recover stress testing. - Spiff up $debugfs/gem to show process information associated with VMAs v12: - Nitpick cleanups in gpu/drm/msm/msm_iommu.c (Rob Clark) - Reorg in gpu/drm/msm/msm_gpu.c (Rob Clark) - Use the default asid for the context bank so that iommu_tlb_flush_all works - Flush the UCHE after a page switch - Add the SCTLR.HUPCF patch at the end of the series v11: - Add implementation specific get_attr/set_attr functions (per Rob Clark) - Fix context bank allocation (per Bjorn Andersson) v10: - arm-smmu: add implementation hook to allocate context banks - arm-smmu: Match the GPU domain by stream ID instead of compatible string - arm-smmu: Make DOMAIN_ATTR_PGTABLE_CFG bi-directional. The leaf driver queries the configuration to create a pagetable and then sends the newly created configuration back to the smmu-driver to enable TTBR0 - drm/msm: Add context reference counting for submissions - drm/msm: Use dummy functions to skip TLB operations on per-instance pagetables [1] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045653.html [2] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045659.html Jordan Crouse (12): iommu/arm-smmu: Pass io-pgtable config to implementation specific function iommu/arm-smmu: Add support for split pagetables iommu/arm-smmu: Prepare for the adreno-smmu implementation iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU drm/msm: Add a context pointer to the submitqueue drm/msm: Drop context arg to gpu->submit() drm/msm: Set the global virtual address range from the IOMMU domain drm/msm: Add support to create a local pagetable drm/msm: Add support for private address space instances drm/msm/a6xx: Add support for per-instance pagetables arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU Rob Clark (8): drm/msm: remove dangling submitqueue references iommu: add private interface for adreno-smmu drm/msm/gpu: add dev_to_gpu() helper drm/msm: set adreno_smmu as gpu's drvdata iommu/arm-smmu: constify some helpers arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMU iommu/arm-smmu: add a way for implementations to influence SCTLR drm/msm: show process names in gem_describe .../devicetree/bindings/iommu/arm,smmu.yaml | 4 + arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 68 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/adreno_device.c| 12 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 18 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +- drivers/gpu/drm/msm/msm_drv.c | 16 +- drivers/gpu/drm/msm/msm_drv.h | 25 +++ drivers/gpu/drm/msm/msm_gem.c | 25 ++- drivers/gpu/drm/msm/msm_gem.h | 6 + drivers/gpu/drm/msm/msm_gem_submit.c | 8 +- drivers/gpu/drm/msm/msm_gem_vma.c | 10 + drivers/gpu/drm/msm/msm_gpu.c | 41 +++- drivers/gpu/drm/msm/msm_gpu.h | 21 +-
[PATCH 06/20] drm/msm/gpu: add dev_to_gpu() helper
From: Rob Clark
In a later patch, the drvdata will not directly be 'struct msm_gpu *',
so add a helper to reduce the churn.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 10 --
drivers/gpu/drm/msm/msm_gpu.c | 6 +++---
drivers/gpu/drm/msm/msm_gpu.h | 5 +
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 9eeb46bf2a5d..26664e1b30c0 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -282,7 +282,7 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
int ret;
if (pdev)
- gpu = platform_get_drvdata(pdev);
+ gpu = dev_to_gpu(>dev);
if (!gpu) {
dev_err_once(dev->dev, "no GPU device was found\n");
@@ -425,7 +425,7 @@ static int adreno_bind(struct device *dev, struct device
*master, void *data)
static void adreno_unbind(struct device *dev, struct device *master,
void *data)
{
- struct msm_gpu *gpu = dev_get_drvdata(dev);
+ struct msm_gpu *gpu = dev_to_gpu(dev);
pm_runtime_force_suspend(dev);
gpu->funcs->destroy(gpu);
@@ -490,16 +490,14 @@ static const struct of_device_id dt_match[] = {
#ifdef CONFIG_PM
static int adreno_resume(struct device *dev)
{
- struct platform_device *pdev = to_platform_device(dev);
- struct msm_gpu *gpu = platform_get_drvdata(pdev);
+ struct msm_gpu *gpu = dev_to_gpu(dev);
return gpu->funcs->pm_resume(gpu);
}
static int adreno_suspend(struct device *dev)
{
- struct platform_device *pdev = to_platform_device(dev);
- struct msm_gpu *gpu = platform_get_drvdata(pdev);
+ struct msm_gpu *gpu = dev_to_gpu(dev);
return gpu->funcs->pm_suspend(gpu);
}
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index d5645472b25d..6aa9e04e52e7 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -24,7 +24,7 @@
static int msm_devfreq_target(struct device *dev, unsigned long *freq,
u32 flags)
{
- struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
+ struct msm_gpu *gpu = dev_to_gpu(dev);
struct dev_pm_opp *opp;
opp = devfreq_recommended_opp(dev, freq, flags);
@@ -45,7 +45,7 @@ static int msm_devfreq_target(struct device *dev, unsigned
long *freq,
static int msm_devfreq_get_dev_status(struct device *dev,
struct devfreq_dev_status *status)
{
- struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
+ struct msm_gpu *gpu = dev_to_gpu(dev);
ktime_t time;
if (gpu->funcs->gpu_get_freq)
@@ -64,7 +64,7 @@ static int msm_devfreq_get_dev_status(struct device *dev,
static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
{
- struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
+ struct msm_gpu *gpu = dev_to_gpu(dev);
if (gpu->funcs->gpu_get_freq)
*freq = gpu->funcs->gpu_get_freq(gpu);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 0db117a7339b..8bda7beaed4b 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -141,6 +141,11 @@ struct msm_gpu {
struct msm_gpu_state *crashstate;
};
+static inline struct msm_gpu *dev_to_gpu(struct device *dev)
+{
+ return dev_get_drvdata(dev);
+}
+
/* It turns out that all targets use the same ringbuffer size */
#define MSM_GPU_RINGBUFFER_SZ SZ_32K
#define MSM_GPU_RINGBUFFER_BLKSIZE 32
--
2.26.2
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[PATCH 01/20] drm/msm: remove dangling submitqueue references
From: Rob Clark
Currently it doesn't matter, since we free the ctx immediately. But
when we start refcnt'ing the ctx, we don't want old dangling list
entries to hang around.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c
b/drivers/gpu/drm/msm/msm_submitqueue.c
index a1d94be7883a..90c9d84e6155 100644
--- a/drivers/gpu/drm/msm/msm_submitqueue.c
+++ b/drivers/gpu/drm/msm/msm_submitqueue.c
@@ -49,8 +49,10 @@ void msm_submitqueue_close(struct msm_file_private *ctx)
* No lock needed in close and there won't
* be any more user ioctls coming our way
*/
- list_for_each_entry_safe(entry, tmp, >submitqueues, node)
+ list_for_each_entry_safe(entry, tmp, >submitqueues, node) {
+ list_del(>node);
msm_submitqueue_put(entry);
+ }
}
int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private
*ctx,
--
2.26.2
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[PATCH 02/20] iommu/arm-smmu: Pass io-pgtable config to implementation specific function
From: Jordan Crouse
Construct the io-pgtable config before calling the implementation specific
init_context function and pass it so the implementation specific function
can get a chance to change it before the io-pgtable is created.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 ++-
drivers/iommu/arm/arm-smmu/arm-smmu.c | 11 ++-
drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 ++-
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
index f4ff124a1967..a9861dcd0884 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
@@ -68,7 +68,8 @@ static int cavium_cfg_probe(struct arm_smmu_device *smmu)
return 0;
}
-static int cavium_init_context(struct arm_smmu_domain *smmu_domain)
+static int cavium_init_context(struct arm_smmu_domain *smmu_domain,
+ struct io_pgtable_cfg *pgtbl_cfg)
{
struct cavium_smmu *cs = container_of(smmu_domain->smmu,
struct cavium_smmu, smmu);
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 09c42af9f31e..37d8d49299b4 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -795,11 +795,6 @@ static int arm_smmu_init_domain_context(struct
iommu_domain *domain,
cfg->asid = cfg->cbndx;
smmu_domain->smmu = smmu;
- if (smmu->impl && smmu->impl->init_context) {
- ret = smmu->impl->init_context(smmu_domain);
- if (ret)
- goto out_unlock;
- }
pgtbl_cfg = (struct io_pgtable_cfg) {
.pgsize_bitmap = smmu->pgsize_bitmap,
@@ -810,6 +805,12 @@ static int arm_smmu_init_domain_context(struct
iommu_domain *domain,
.iommu_dev = smmu->dev,
};
+ if (smmu->impl && smmu->impl->init_context) {
+ ret = smmu->impl->init_context(smmu_domain, _cfg);
+ if (ret)
+ goto out_clear_smmu;
+ }
+
if (smmu_domain->non_strict)
pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h
b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index d890a4a968e8..83294516ac08 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -386,7 +386,8 @@ struct arm_smmu_impl {
u64 val);
int (*cfg_probe)(struct arm_smmu_device *smmu);
int (*reset)(struct arm_smmu_device *smmu);
- int (*init_context)(struct arm_smmu_domain *smmu_domain);
+ int (*init_context)(struct arm_smmu_domain *smmu_domain,
+ struct io_pgtable_cfg *cfg);
void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync,
int status);
int (*def_domain_type)(struct device *dev);
--
2.26.2
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[PATCH 03/20] iommu/arm-smmu: Add support for split pagetables
From: Jordan Crouse
Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected
by the io-pgtable configuration.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 21 -
drivers/iommu/arm/arm-smmu/arm-smmu.h | 25 +++--
2 files changed, 35 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 37d8d49299b4..976d43a7f2ff 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -552,11 +552,15 @@ static void arm_smmu_init_context_bank(struct
arm_smmu_domain *smmu_domain,
cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr;
cb->ttbr[1] = 0;
} else {
- cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
- cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID,
- cfg->asid);
+ cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,
+ cfg->asid);
cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,
-cfg->asid);
+ cfg->asid);
+
+ if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
+ cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
+ else
+ cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
}
} else {
cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
@@ -822,7 +826,14 @@ static int arm_smmu_init_domain_context(struct
iommu_domain *domain,
/* Update the domain's page sizes to reflect the page table format */
domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
- domain->geometry.aperture_end = (1UL << ias) - 1;
+
+ if (pgtbl_cfg.quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {
+ domain->geometry.aperture_start = ~0UL << ias;
+ domain->geometry.aperture_end = ~0UL;
+ } else {
+ domain->geometry.aperture_end = (1UL << ias) - 1;
+ }
+
domain->geometry.force_aperture = true;
/* Initialise the context bank with our page table cfg */
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h
b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index 83294516ac08..f3e456893f28 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -169,10 +169,12 @@ enum arm_smmu_cbar_type {
#define ARM_SMMU_CB_TCR0x30
#define ARM_SMMU_TCR_EAE BIT(31)
#define ARM_SMMU_TCR_EPD1 BIT(23)
+#define ARM_SMMU_TCR_A1BIT(22)
#define ARM_SMMU_TCR_TG0 GENMASK(15, 14)
#define ARM_SMMU_TCR_SH0 GENMASK(13, 12)
#define ARM_SMMU_TCR_ORGN0 GENMASK(11, 10)
#define ARM_SMMU_TCR_IRGN0 GENMASK(9, 8)
+#define ARM_SMMU_TCR_EPD0 BIT(7)
#define ARM_SMMU_TCR_T0SZ GENMASK(5, 0)
#define ARM_SMMU_VTCR_RES1 BIT(31)
@@ -350,12 +352,23 @@ struct arm_smmu_domain {
static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg)
{
- return ARM_SMMU_TCR_EPD1 |
- FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |
- FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |
- FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) |
- FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) |
- FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz);
+ u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |
+ FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |
+ FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) |
+ FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) |
+ FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz);
+
+ /*
+ * When TTBR1 is selected shift the TCR fields by 16 bits and disable
+ * translation in TTBR0
+ */
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {
+ tcr = (tcr << 16) & ~ARM_SMMU_TCR_A1;
+ tcr |= ARM_SMMU_TCR_EPD0;
+ } else
+ tcr |= ARM_SMMU_TCR_EPD1;
+
+ return tcr;
}
static inline u32 arm_smmu_lpae_tcr2(struct io_pgtable_cfg *cfg)
--
2.26.2
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[PATCH] drm/panel: s6e63m0: Order enable/disable sequence
The upstream S6E63M0 driver has some pecularities around the prepare/enable disable/unprepare sequence: the screen is taken out of sleep in prepare() as part of s6e63m0_init() the put to on with MIPI_DCS_SET_DISPLAY_ON in enable(). However it is just put into sleep mode directly in disable(). As disable()/enable() can be called without unprepare()/prepare() being called, this is unbalanced, we should take the display out of sleep in enable() then turn it off(). Further MIPI_DCS_SET_DISPLAY_OFF is never called balanced with MIPI_DCS_SET_DISPLAY_ON. The vendor driver for Samsung GT-I8190 (Golden) does all of these things in strict order. Augment the driver to do exit sleep/set display on in enable() and set display off/enter sleep in disable(). Further send an explict reset pulse in power_on() so we come up in a known state, and issue the MCS_ERROR_CHECK command after setting display on like the vendor driver does. Also use the timings from the vendor driver in the sequence. Doing all of these things makes the display much more stable on the Samsung GT-I8190 when enabling/disabling the display pipeline. Cc: Paweł Chmiel Cc: Stephan Gerhold Signed-off-by: Linus Walleij --- This is based on top of the earlier patches for s6e63m0. --- drivers/gpu/drm/panel/panel-samsung-s6e63m0.c | 18 +++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c b/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c index f1d96ec3b57f..49b0470bcccd 100644 --- a/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c +++ b/drivers/gpu/drm/panel/panel-samsung-s6e63m0.c @@ -26,6 +26,7 @@ #define MCS_ELVSS_ON0xb1 #define MCS_MIECTL10xc0 #define MCS_BCMODE 0xc1 +#define MCS_ERROR_CHECK0xd5 #define MCS_READ_ID1 0xda #define MCS_READ_ID2 0xdb #define MCS_READ_ID3 0xdc @@ -281,8 +282,6 @@ static void s6e63m0_init(struct s6e63m0 *ctx) s6e63m0_dcs_write_seq_static(ctx, MCS_ELVSS_ON, 0x0b); - - s6e63m0_dcs_write_seq_static(ctx, MIPI_DCS_EXIT_SLEEP_MODE); } static int s6e63m0_power_on(struct s6e63m0 *ctx) @@ -295,6 +294,9 @@ static int s6e63m0_power_on(struct s6e63m0 *ctx) msleep(25); + /* Be sure to send a reset pulse */ + gpiod_set_value(ctx->reset_gpio, 1); + msleep(5); gpiod_set_value(ctx->reset_gpio, 0); msleep(120); @@ -324,8 +326,10 @@ static int s6e63m0_disable(struct drm_panel *panel) backlight_disable(ctx->bl_dev); + s6e63m0_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_OFF); + msleep(10); s6e63m0_dcs_write_seq_static(ctx, MIPI_DCS_ENTER_SLEEP_MODE); - msleep(200); + msleep(120); ctx->enabled = false; @@ -391,7 +395,15 @@ static int s6e63m0_enable(struct drm_panel *panel) if (ctx->enabled) return 0; + s6e63m0_dcs_write_seq_static(ctx, MIPI_DCS_EXIT_SLEEP_MODE); + msleep(120); s6e63m0_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_ON); + msleep(10); + + s6e63m0_dcs_write_seq_static(ctx, MCS_ERROR_CHECK, +0xE7, 0x14, 0x60, 0x17, 0x0A, 0x49, 0xC3, +0x8F, 0x19, 0x64, 0x91, 0x84, 0x76, 0x20, +0x0F, 0x00); backlight_enable(ctx->bl_dev); -- 2.26.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 208947] New: amdgpu DisplayPort won't recognize all display modes after 5.9 merges
https://bugzilla.kernel.org/show_bug.cgi?id=208947 Bug ID: 208947 Summary: amdgpu DisplayPort won't recognize all display modes after 5.9 merges Product: Drivers Version: 2.5 Kernel Version: 5.9 staging-testing, rc1, and latest linux.git Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-...@kernel-bugs.osdl.org Reporter: ck...@colemankane.org Regression: No I've got an AMD Ryzen 7 1700 and a POLARIS10 Radeon RX 580M GPU in an ASUS ROG GL702ZC laptop. I'm using the regular 5.8.1 kernel on Arch linux, and also have been tracking in-development kernel changes via the "staging-testing" branch on the gregkh/staging.git Linux tree as well as the torvalds/linux.git tree. Sometime during the course of the 5.9 updates getting merged into those trees, the 5.9 kernels I build no longer recognize all of the graphics modes for my 4K (3840x2160) monitor when it is plugged into the DisplayPort. Instead, the highest mode reported available is 1024x768, and Xorg also gets limited to these choices. This behavior appears limited to the monitor being plugged in via its DisplayPort input. When I use an HDMI input, all of the supported graphics modes are reported properly. I am using /sys/class/drm/card0-DP-1/modes to display the available modes, and also starting Xorg to test it as well. Would be happy to test patches if this is a known regression, or would appreciate some help/direction in tracking down potential likely culprits of the problem so I can try to diagnose it myself. I am somewhat familiar with kernel development, so I'm capable of hacking on it a bit if anyone can point me in a good direction. I'm just not too familiar with the inner workings of the AMDGPU, KMS, or DRM code. Not even certain if this is an issue specific to AMDGPU or something agnostic to the specific video hw. I also tried dumping the /sys/class/drm/card0-DP-1/edid after booting into 5.8.1 and then 5.9-latest and I get exactly the same data for both, so it seems like the EDID data is at least being fetched properly. I also tried saving that EDID data to a *.bin file and manually loading that via kernel arguments (drm.edid_firmware): verified it was loading properly for DP-1, but I still got the same results (no high-resolution video modes). Let me know what data would be helpful to attach to this issue, as well. Thanks, Coleman Kane -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/qxl: Fix build errors
On Mon, Aug 17, 2020 at 4:09 PM Sean Paul wrote:
>
> On Mon, Aug 17, 2020 at 4:05 PM Sam Ravnborg wrote:
> >
> > Hi Sean.
> >
> > On Mon, Aug 17, 2020 at 03:58:38PM -0400, Sean Paul wrote:
> > > From: Sean Paul
> > >
> > > Introduced in the patch below, the END macro was missing 'dev' and BEGIN
> > > macro needs drm_drv_uses_atomic_modeset() from drm_drv.h
> > >
> > > Fixes: bbaac1354cc9 ("drm/qxl: Replace deprecated function in
> > > qxl_display")
> > We should not use Fixes for local fixes like this, as we do not want the
> > robots to pick this commit.
> > With the Fixes: dropped (maybe just reference the commit in the
> > changelog):
> > Acked-by: Sam Ravnborg
> >
>
> Ok, I'll fix up the Fixes: tag and apply to -misc-next.
>
I guess things are never quite so easy :-). It looks like Daniel's
patch is in drm-misc-fixes and Sidong's patch is in drm-misc-next. On
their own they're fine, but once they are merged in drm-tip the build
error shows up.
So I think this needs to be resolved in drm-tip. I see
https://drm.pages.freedesktop.org/maintainer-tools/drm-tip.html#fixing-silent-conflicts,
but that seems like a maintainer thing, so I'll wait for -misc
maintainers to chime in.
Sean
> Thanks for the quick response!
>
> Sean
>
> >
> > > Cc: Sidong Yang
> > > Cc: Gerd Hoffmann
> > > Cc: Dave Airlie
> > > Cc: virtualizat...@lists.linux-foundation.org
> > > Signed-off-by: Sean Paul
> > > ---
> > > drivers/gpu/drm/qxl/qxl_display.c | 5 +++--
> > > 1 file changed, 3 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/qxl/qxl_display.c
> > > b/drivers/gpu/drm/qxl/qxl_display.c
> > > index fa79688013b7..5b4fd6952b53 100644
> > > --- a/drivers/gpu/drm/qxl/qxl_display.c
> > > +++ b/drivers/gpu/drm/qxl/qxl_display.c
> > > @@ -28,6 +28,7 @@
> > >
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > > #include
> > > @@ -186,7 +187,7 @@ void qxl_display_read_client_monitors_config(struct
> > > qxl_device *qdev)
> > >
> > > DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx,
> > > DRM_MODESET_ACQUIRE_INTERRUPTIBLE, ret);
> > > qxl_update_offset_props(qdev);
> > > - DRM_MODESET_LOCK_ALL_END(ctx, ret);
> > > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
> > > if (!drm_helper_hpd_irq_event(dev)) {
> > > /* notify that the monitor configuration changed, to
> > > adjust at the arbitrary resolution */
> > > @@ -431,7 +432,7 @@ static int qxl_framebuffer_surface_dirty(struct
> > > drm_framebuffer *fb,
> > > clips, num_clips, inc, 0);
> > >
> > > out_lock_end:
> > > - DRM_MODESET_LOCK_ALL_END(ctx, ret);
> > > + DRM_MODESET_LOCK_ALL_END(fb->dev, ctx, ret);
> > >
> > > return 0;
> > > }
> > > --
> > > Sean Paul, Software Engineer, Google / Chromium OS
> > >
> > > ___
> > > dri-devel mailing list
> > > dri-devel@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [Freedreno] [PATCH v10 3/5] drm/msm/dp: add support for DP PLL driver
On Mon, Aug 17, 2020 at 1:32 PM Dmitry Baryshkov
wrote:
>
> On 16/08/2020 01:45, Rob Clark wrote:
> > On Sat, Aug 15, 2020 at 2:21 PM Jonathan Marek wrote:
> >>
> >> On 8/15/20 4:20 PM, Rob Clark wrote:
> >>> On Fri, Aug 14, 2020 at 10:05 AM Dmitry Baryshkov
> >>> wrote:
>
>
> On 12/08/2020 07:42, Tanmay Shah wrote:
> > From: Chandan Uddaraju
> >
> > Add the needed DP PLL specific files to support
> > display port interface on msm targets.
>
> [skipped]
>
> > diff --git a/drivers/gpu/drm/msm/dp/dp_pll_private.h
> b/drivers/gpu/drm/msm/dp/dp_pll_private.h
> > new file mode 100644
> > index ..475ba6ed59ab
> > --- /dev/null
> > +++ b/drivers/gpu/drm/msm/dp/dp_pll_private.h
> > @@ -0,0 +1,98 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2016-2020, The Linux Foundation. All rights
> reserved.
> > + */
> > +
> > +#ifndef __DP_PLL_10NM_H
> > +#define __DP_PLL_10NM_H
> > +
> > +#include "dp_pll.h"
> > +#include "dp_reg.h"
> > +
> > +#define DP_VCO_HSCLK_RATE_1620MHZDIV1000162UL
> > +#define DP_VCO_HSCLK_RATE_2700MHZDIV1000270UL
> > +#define DP_VCO_HSCLK_RATE_5400MHZDIV1000540UL
> > +#define DP_VCO_HSCLK_RATE_8100MHZDIV1000810UL
> > +
> > +#define NUM_DP_CLOCKS_MAX6
> > +
> > +#define DP_PHY_PLL_POLL_SLEEP_US500
> > +#define DP_PHY_PLL_POLL_TIMEOUT_US1
> > +
> > +#define DP_VCO_RATE_8100MHZDIV1000810UL
> > +#define DP_VCO_RATE_9720MHZDIV1000972UL
> > +#define DP_VCO_RATE_10800MHZDIV10001080UL
> > +
> > +struct dp_pll_vco_clk {
> > +struct clk_hw hw;
> > +unsigned longrate;/* current vco rate */
> > +u64min_rate;/* min vco rate */
> > +u64max_rate;/* max vco rate */
> > +void*priv;
> > +};
> > +
> > +struct dp_pll_db {
>
> This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for
> example, will use slightly different structure.
> >>>
> >>> Note that sboyd has a WIP series to move all of the pll code out to a
> >>> phy driver. If there is work already happening on 7nm support, it
> >>> might be better to go with the separate phy driver approach? I'm
> >>> still a bit undecided about whether to land the dp code initially with
> >>> the pll stuff in drm, and then continue refactoring to move to
> >>> separate phy driver upstream, or to strip out the pll code from the
> >>> beginning. If you/someone is working on 7nm support, then feedback
> >>> about which approach is easier is welcome.
> >>>
> >>> https://lore.kernel.org/dri-devel/20200611091919.108018-1-swb...@chromium.org/
> >>>
> >>
> >> I have a sm8150/sm8250 (7nm) upstream kernel stack with DP enabled, and
> >> I have done something similar, with the PLL driver in the QMP phy,
> >> although not based on sboyd's series (along with some typec changes to
> >> negotiate the DP alt mode and get HPD events, etc.). I don't think
> >> having PLL in drm/msm makes sense, the drm/msm DP driver shouldn't need
> >> to be aware of the DP PLL/PHY driver, it only needs to set the
> >> link/pixel clock rates which are in dispcc (and those then have the PLL
> >> clocks as a parent).
> >
> > yeah, in the dp case, having phy split out makes a ton of sense.. it
> > would maybe be a nice cleanup in other cases (dsi, hdmi) but the
> > combination of usb+dp makes burying this in drm not so great..
> >
> > It would be good if you could work w/ sboyd on this.. based on what
> > I've seen on previous gens, it is probably a different phy driver for
> > 7nm vs 10nm, but I think where we want to end up upstream is with phy
> > split out of drm.
>
> 7nm differs in registers programming, so it would end up with a separate
> set of tables in qmp phy driver. There is also a 14nm version of dp phy,
> but I don't know if it usable in any actual hardware design.
>
I'll defer to Stephen about phy stuff, but was kinda just expecting to
have different phy drivers for different process sizes, rather than
trying to bundle it all in one phy driver. At least what I've seen
before for dsi/hdmi/etc phy's is that the register programming is
different enough to not really share much.
BR,
-R
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Re: [PATCH 1/2] drm/scheduler: Scheduler priority fixes (v2)
On 2020-08-17 9:53 a.m., Christian König wrote:
> Am 15.08.20 um 04:48 schrieb Luben Tuikov:
>> Remove DRM_SCHED_PRIORITY_LOW, as it was used
>> in only one place.
>>
>> Rename and separate by a line
>> DRM_SCHED_PRIORITY_MAX to DRM_SCHED_PRIORITY_COUNT
>> as it represents a (total) count of said
>> priorities and it is used as such in loops
>> throughout the code. (0-based indexing is the
>> the count number.)
>>
>> Remove redundant word HIGH in priority names,
>> and rename *KERNEL* to *HIGH*, as it really
>> means that, high.
>>
>> v2: Add back KERNEL and remove SW and HW,
>> in lieu of a single HIGH between NORMAL and KERNEL.
>>
>> Signed-off-by: Luben Tuikov
>
> I can't really judge the difference between MAX and COUNT, but the we
> rename the values and get rid of the invalid one sounds like a good idea
> to me.
Thanks Christian.
As to "max" vs. "count", I alluded to the difference
in the patch cover letter text:
> For instance, renaming MAX to COUNT, as usually a maximum value
> is a value which is part of the set of values, (e.g. a maxima of
> a function), and thus assignable, whereby a count is the size of
> a set (the enumeration in this case). It also makes it clearer
> when used to define size of arrays.
A "maximum" value is value which *can be attained.* For instance,
some would say, "The maximum temperature we expect today is 35 degC."
While a "count" is just the (usually integer) number of objects in a set.
The set could be composed of various objects, not necessarily integers.
It is possible that the maximum number in a set of integers to also
be the size of that set, e.g. A = { 1, 2, 3 }, max(A) = 3, sizeof(A) = 3,
but as you can see this is a special case; consider A = { Red, Green, Blue },
or A = { 2, 3, 5 }, or A = { 3 }.
To me it is confusing to read "MAX", as this is usually used
as a "watermark", say in temperature of a unit or something like that,
which we monitor and perform certain actions depending on whether
the maximum temperature is/has been attained. Usually, there'd
be one above it, called "CRITICAL".
And I've seen bugs where people would assume that MAX is an attainable
value, e.g. MAX_PRIORITY, "This is the maximum priority a task could
run at."
I'll add your RB to the patch! Thanks for your review.
Regards,
Luben
>
> Reviewed-by: Christian König for the series.
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
>> drivers/gpu/drm/scheduler/sched_main.c| 4 ++--
>> include/drm/gpu_scheduler.h | 12 +++-
>> 8 files changed, 18 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> index d85d13f7a043..68eaa4f687a6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> @@ -46,7 +46,7 @@ const unsigned int
>> amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = {
>> static int amdgpu_ctx_priority_permit(struct drm_file *filp,
>>enum drm_sched_priority priority)
>> {
>> -if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
>> +if (priority < 0 || priority >= DRM_SCHED_PRIORITY_COUNT)
>> return -EINVAL;
>>
>> /* NORMAL and below are accessible by everyone */
>> @@ -65,7 +65,7 @@ static int amdgpu_ctx_priority_permit(struct drm_file
>> *filp,
>> static enum gfx_pipe_priority amdgpu_ctx_sched_prio_to_compute_prio(enum
>> drm_sched_priority prio)
>> {
>> switch (prio) {
>> -case DRM_SCHED_PRIORITY_HIGH_HW:
>> +case DRM_SCHED_PRIORITY_HIGH:
>> case DRM_SCHED_PRIORITY_KERNEL:
>> return AMDGPU_GFX_PIPE_PRIO_HIGH;
>> default:
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
>> index 75d37dfb51aa..bb9e5481ff3c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
>> @@ -251,7 +251,7 @@ void amdgpu_job_stop_all_jobs_on_sched(struct
>> drm_gpu_scheduler *sched)
>> int i;
>>
>> /* Signal all jobs not yet scheduled */
>> -for (i = DRM_SCHED_PRIORITY_MAX - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
>> +for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN;
>> i--) {
>> struct drm_sched_rq *rq = >sched_rq[i];
>>
>> if (!rq)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
>> index 13ea8ebc421c..6d4fc79bf84a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
>> @@ -267,7 +267,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct
>>
Re: [PATCH] drm/qxl: Fix build errors
On Mon, Aug 17, 2020 at 4:05 PM Sam Ravnborg wrote:
>
> Hi Sean.
>
> On Mon, Aug 17, 2020 at 03:58:38PM -0400, Sean Paul wrote:
> > From: Sean Paul
> >
> > Introduced in the patch below, the END macro was missing 'dev' and BEGIN
> > macro needs drm_drv_uses_atomic_modeset() from drm_drv.h
> >
> > Fixes: bbaac1354cc9 ("drm/qxl: Replace deprecated function in qxl_display")
> We should not use Fixes for local fixes like this, as we do not want the
> robots to pick this commit.
> With the Fixes: dropped (maybe just reference the commit in the
> changelog):
> Acked-by: Sam Ravnborg
>
Ok, I'll fix up the Fixes: tag and apply to -misc-next.
Thanks for the quick response!
Sean
>
> > Cc: Sidong Yang
> > Cc: Gerd Hoffmann
> > Cc: Dave Airlie
> > Cc: virtualizat...@lists.linux-foundation.org
> > Signed-off-by: Sean Paul
> > ---
> > drivers/gpu/drm/qxl/qxl_display.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/qxl/qxl_display.c
> > b/drivers/gpu/drm/qxl/qxl_display.c
> > index fa79688013b7..5b4fd6952b53 100644
> > --- a/drivers/gpu/drm/qxl/qxl_display.c
> > +++ b/drivers/gpu/drm/qxl/qxl_display.c
> > @@ -28,6 +28,7 @@
> >
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -186,7 +187,7 @@ void qxl_display_read_client_monitors_config(struct
> > qxl_device *qdev)
> >
> > DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx,
> > DRM_MODESET_ACQUIRE_INTERRUPTIBLE, ret);
> > qxl_update_offset_props(qdev);
> > - DRM_MODESET_LOCK_ALL_END(ctx, ret);
> > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
> > if (!drm_helper_hpd_irq_event(dev)) {
> > /* notify that the monitor configuration changed, to
> > adjust at the arbitrary resolution */
> > @@ -431,7 +432,7 @@ static int qxl_framebuffer_surface_dirty(struct
> > drm_framebuffer *fb,
> > clips, num_clips, inc, 0);
> >
> > out_lock_end:
> > - DRM_MODESET_LOCK_ALL_END(ctx, ret);
> > + DRM_MODESET_LOCK_ALL_END(fb->dev, ctx, ret);
> >
> > return 0;
> > }
> > --
> > Sean Paul, Software Engineer, Google / Chromium OS
> >
> > ___
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> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [PATCH] drm/qxl: Fix build errors
On Mon, Aug 17, 2020 at 3:58 PM Sean Paul wrote:
>
> From: Sean Paul
>
> Introduced in the patch below, the END macro was missing 'dev' and BEGIN
> macro needs drm_drv_uses_atomic_modeset() from drm_drv.h
>
> Fixes: bbaac1354cc9 ("drm/qxl: Replace deprecated function in qxl_display")
> Cc: Sidong Yang
> Cc: Gerd Hoffmann
> Cc: Dave Airlie
> Cc: virtualizat...@lists.linux-foundation.org
Apologies, this should be:
Fixes: 77ef38574beb ("drm/modeset-lock: Take the modeset BKL for
legacy drivers")
Cc: Alex Deucher
Cc: Michal Orzel
Cc: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
Cc: dri-devel@lists.freedesktop.org
Cc: # v5.8+
Cc: Daniel Vetter
Cc: Alex Deucher
> Signed-off-by: Sean Paul
> ---
> drivers/gpu/drm/qxl/qxl_display.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/qxl/qxl_display.c
> b/drivers/gpu/drm/qxl/qxl_display.c
> index fa79688013b7..5b4fd6952b53 100644
> --- a/drivers/gpu/drm/qxl/qxl_display.c
> +++ b/drivers/gpu/drm/qxl/qxl_display.c
> @@ -28,6 +28,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -186,7 +187,7 @@ void qxl_display_read_client_monitors_config(struct
> qxl_device *qdev)
>
> DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx,
> DRM_MODESET_ACQUIRE_INTERRUPTIBLE, ret);
> qxl_update_offset_props(qdev);
> - DRM_MODESET_LOCK_ALL_END(ctx, ret);
> + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
> if (!drm_helper_hpd_irq_event(dev)) {
> /* notify that the monitor configuration changed, to
>adjust at the arbitrary resolution */
> @@ -431,7 +432,7 @@ static int qxl_framebuffer_surface_dirty(struct
> drm_framebuffer *fb,
> clips, num_clips, inc, 0);
>
> out_lock_end:
> - DRM_MODESET_LOCK_ALL_END(ctx, ret);
> + DRM_MODESET_LOCK_ALL_END(fb->dev, ctx, ret);
>
> return 0;
> }
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
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Re: [PATCH] drm/qxl: Fix build errors
Hi Sean.
On Mon, Aug 17, 2020 at 03:58:38PM -0400, Sean Paul wrote:
> From: Sean Paul
>
> Introduced in the patch below, the END macro was missing 'dev' and BEGIN
> macro needs drm_drv_uses_atomic_modeset() from drm_drv.h
>
> Fixes: bbaac1354cc9 ("drm/qxl: Replace deprecated function in qxl_display")
We should not use Fixes for local fixes like this, as we do not want the
robots to pick this commit.
With the Fixes: dropped (maybe just reference the commit in the
changelog):
Acked-by: Sam Ravnborg
> Cc: Sidong Yang
> Cc: Gerd Hoffmann
> Cc: Dave Airlie
> Cc: virtualizat...@lists.linux-foundation.org
> Signed-off-by: Sean Paul
> ---
> drivers/gpu/drm/qxl/qxl_display.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/qxl/qxl_display.c
> b/drivers/gpu/drm/qxl/qxl_display.c
> index fa79688013b7..5b4fd6952b53 100644
> --- a/drivers/gpu/drm/qxl/qxl_display.c
> +++ b/drivers/gpu/drm/qxl/qxl_display.c
> @@ -28,6 +28,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -186,7 +187,7 @@ void qxl_display_read_client_monitors_config(struct
> qxl_device *qdev)
>
> DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE,
> ret);
> qxl_update_offset_props(qdev);
> - DRM_MODESET_LOCK_ALL_END(ctx, ret);
> + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
> if (!drm_helper_hpd_irq_event(dev)) {
> /* notify that the monitor configuration changed, to
> adjust at the arbitrary resolution */
> @@ -431,7 +432,7 @@ static int qxl_framebuffer_surface_dirty(struct
> drm_framebuffer *fb,
> clips, num_clips, inc, 0);
>
> out_lock_end:
> - DRM_MODESET_LOCK_ALL_END(ctx, ret);
> + DRM_MODESET_LOCK_ALL_END(fb->dev, ctx, ret);
>
> return 0;
> }
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
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Re: [Freedreno] [PATCH v10 3/5] drm/msm/dp: add support for DP PLL driver
On 2020-08-15 15:45, Rob Clark wrote:
On Sat, Aug 15, 2020 at 2:21 PM Jonathan Marek
wrote:
On 8/15/20 4:20 PM, Rob Clark wrote:
> On Fri, Aug 14, 2020 at 10:05 AM Dmitry Baryshkov
> wrote:
>>
>>
>> On 12/08/2020 07:42, Tanmay Shah wrote:
>> > From: Chandan Uddaraju
>> >
>> > Add the needed DP PLL specific files to support
>> > display port interface on msm targets.
>>
>> [skipped]
>>
>> > diff --git a/drivers/gpu/drm/msm/dp/dp_pll_private.h
>> b/drivers/gpu/drm/msm/dp/dp_pll_private.h
>> > new file mode 100644
>> > index ..475ba6ed59ab
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/msm/dp/dp_pll_private.h
>> > @@ -0,0 +1,98 @@
>> > +/* SPDX-License-Identifier: GPL-2.0-only */
>> > +/*
>> > + * Copyright (c) 2016-2020, The Linux Foundation. All rights
reserved.
>> > + */
>> > +
>> > +#ifndef __DP_PLL_10NM_H
>> > +#define __DP_PLL_10NM_H
>> > +
>> > +#include "dp_pll.h"
>> > +#include "dp_reg.h"
>> > +
>> > +#define DP_VCO_HSCLK_RATE_1620MHZDIV1000162UL
>> > +#define DP_VCO_HSCLK_RATE_2700MHZDIV1000270UL
>> > +#define DP_VCO_HSCLK_RATE_5400MHZDIV1000540UL
>> > +#define DP_VCO_HSCLK_RATE_8100MHZDIV1000810UL
>> > +
>> > +#define NUM_DP_CLOCKS_MAX6
>> > +
>> > +#define DP_PHY_PLL_POLL_SLEEP_US500
>> > +#define DP_PHY_PLL_POLL_TIMEOUT_US1
>> > +
>> > +#define DP_VCO_RATE_8100MHZDIV1000810UL
>> > +#define DP_VCO_RATE_9720MHZDIV1000972UL
>> > +#define DP_VCO_RATE_10800MHZDIV10001080UL
>> > +
>> > +struct dp_pll_vco_clk {
>> > +struct clk_hw hw;
>> > +unsigned longrate;/* current vco rate */
>> > +u64min_rate;/* min vco rate */
>> > +u64max_rate;/* max vco rate */
>> > +void*priv;
>> > +};
>> > +
>> > +struct dp_pll_db {
>>
>> This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for
>> example, will use slightly different structure.
>
> Note that sboyd has a WIP series to move all of the pll code out to a
> phy driver. If there is work already happening on 7nm support, it
> might be better to go with the separate phy driver approach? I'm
> still a bit undecided about whether to land the dp code initially with
> the pll stuff in drm, and then continue refactoring to move to
> separate phy driver upstream, or to strip out the pll code from the
> beginning. If you/someone is working on 7nm support, then feedback
> about which approach is easier is welcome.
>
>
https://lore.kernel.org/dri-devel/20200611091919.108018-1-swboyd@chromium.
org/
>
I have a sm8150/sm8250 (7nm) upstream kernel stack with DP enabled,
and
I have done something similar, with the PLL driver in the QMP phy,
although not based on sboyd's series (along with some typec changes to
negotiate the DP alt mode and get HPD events, etc.). I don't think
having PLL in drm/msm makes sense, the drm/msm DP driver shouldn't
need
to be aware of the DP PLL/PHY driver, it only needs to set the
link/pixel clock rates which are in dispcc (and those then have the
PLL
clocks as a parent).
yeah, in the dp case, having phy split out makes a ton of sense.. it
would maybe be a nice cleanup in other cases (dsi, hdmi) but the
combination of usb+dp makes burying this in drm not so great..
It would be good if you could work w/ sboyd on this.. based on what
I've seen on previous gens, it is probably a different phy driver for
7nm vs 10nm, but I think where we want to end up upstream is with phy
split out of drm.
FYI, since it sounds you are considering landing this: it is
completely
broken, for example:
- ioremap()'s to #define'd addresses in the PLL driver
- main DP driver reading/writing to registers in the PHY region, but
getting the base address from devicetree was removed since earlier
revisions, so it just fails completely. Look at usb3_dp_com (for
example), which in dp_catalog_ctrl_usb_reset() would be used to
overwrite registers already being driven by the qmp phy driver - but
now
the usb3_dp_com.base is never initialized.
Yeah, the idea to land dp isn't that it is perfect (or even not
broken), so much as having something upstream gives a common base for
others to work against.. maybe we should make the dp parts 'depends on
STAGING'?
I could keep a separate msm-next-dp branch that I rebase, to give a
common point for folks working dp support for various different gens
to coordinate work on.. that kinda sounds like a bunch of extra work
for me, so might as well land what we have somehow and work together
from there ;-)
But it does sound like you are making the case for including the patch
to drop the pll stuff and use phy framework as part of what initially
goes upstream.
I agree with Rob on landing what we have in DP driver. Of course, by
addressing any outstanding comments. That would help in setting base
functional code for DisplayPort
Bring-up. Other features
[PATCH] drm/qxl: Fix build errors
From: Sean Paul
Introduced in the patch below, the END macro was missing 'dev' and BEGIN
macro needs drm_drv_uses_atomic_modeset() from drm_drv.h
Fixes: bbaac1354cc9 ("drm/qxl: Replace deprecated function in qxl_display")
Cc: Sidong Yang
Cc: Gerd Hoffmann
Cc: Dave Airlie
Cc: virtualizat...@lists.linux-foundation.org
Signed-off-by: Sean Paul
---
drivers/gpu/drm/qxl/qxl_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/qxl/qxl_display.c
b/drivers/gpu/drm/qxl/qxl_display.c
index fa79688013b7..5b4fd6952b53 100644
--- a/drivers/gpu/drm/qxl/qxl_display.c
+++ b/drivers/gpu/drm/qxl/qxl_display.c
@@ -28,6 +28,7 @@
#include
#include
+#include
#include
#include
#include
@@ -186,7 +187,7 @@ void qxl_display_read_client_monitors_config(struct
qxl_device *qdev)
DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE,
ret);
qxl_update_offset_props(qdev);
- DRM_MODESET_LOCK_ALL_END(ctx, ret);
+ DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
if (!drm_helper_hpd_irq_event(dev)) {
/* notify that the monitor configuration changed, to
adjust at the arbitrary resolution */
@@ -431,7 +432,7 @@ static int qxl_framebuffer_surface_dirty(struct
drm_framebuffer *fb,
clips, num_clips, inc, 0);
out_lock_end:
- DRM_MODESET_LOCK_ALL_END(ctx, ret);
+ DRM_MODESET_LOCK_ALL_END(fb->dev, ctx, ret);
return 0;
}
--
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH] block: convert tasklets to use new tasklet_setup() API
On Mon, Aug 17, 2020 at 12:44:34PM -0700, Jens Axboe wrote: > On 8/17/20 12:29 PM, Kees Cook wrote: > > On Mon, Aug 17, 2020 at 06:56:47AM -0700, Jens Axboe wrote: > >> On 8/17/20 2:15 AM, Allen Pais wrote: > >>> From: Allen Pais > >>> > >>> In preparation for unconditionally passing the > >>> struct tasklet_struct pointer to all tasklet > >>> callbacks, switch to using the new tasklet_setup() > >>> and from_tasklet() to pass the tasklet pointer explicitly. > >> > >> Who came up with the idea to add a macro 'from_tasklet' that is just > >> container_of? container_of in the code would be _much_ more readable, > >> and not leave anyone guessing wtf from_tasklet is doing. > >> > >> I'd fix that up now before everything else goes in... > > > > As I mentioned in the other thread, I think this makes things much more > > readable. It's the same thing that the timer_struct conversion did > > (added a container_of wrapper) to avoid the ever-repeating use of > > typeof(), long lines, etc. > > But then it should use a generic name, instead of each sub-system using > some random name that makes people look up exactly what it does. I'm not > huge fan of the container_of() redundancy, but adding private variants > of this doesn't seem like the best way forward. Let's have a generic > helper that does this, and use it everywhere. I'm open to suggestions, but as things stand, these kinds of treewide changes end up getting whole-release delays because of the need to have the API in place for everyone before patches to do the changes can be sent to multiple maintainers, etc. -- Kees Cook ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] block: convert tasklets to use new tasklet_setup() API
On Mon, Aug 17, 2020 at 06:56:47AM -0700, Jens Axboe wrote: > On 8/17/20 2:15 AM, Allen Pais wrote: > > From: Allen Pais > > > > In preparation for unconditionally passing the > > struct tasklet_struct pointer to all tasklet > > callbacks, switch to using the new tasklet_setup() > > and from_tasklet() to pass the tasklet pointer explicitly. > > Who came up with the idea to add a macro 'from_tasklet' that is just > container_of? container_of in the code would be _much_ more readable, > and not leave anyone guessing wtf from_tasklet is doing. > > I'd fix that up now before everything else goes in... As I mentioned in the other thread, I think this makes things much more readable. It's the same thing that the timer_struct conversion did (added a container_of wrapper) to avoid the ever-repeating use of typeof(), long lines, etc. -- Kees Cook ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v10 3/5] drm/msm/dp: add support for DP PLL driver
On 2020-08-15 04:45, Dmitry Baryshkov wrote:
On 15/08/2020 02:22, Tanmay Shah wrote:
On 2020-08-14 10:05, Dmitry Baryshkov wrote:
On 12/08/2020 07:42, Tanmay Shah wrote:
From: Chandan Uddaraju
Add the needed DP PLL specific files to support
display port interface on msm targets.
[skipped]
diff --git a/drivers/gpu/drm/msm/dp/dp_pll_private.h
b/drivers/gpu/drm/msm/dp/dp_pll_private.h
new file mode 100644
index ..475ba6ed59ab
--- /dev/null
+++ b/drivers/gpu/drm/msm/dp/dp_pll_private.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights
reserved.
+ */
+
+#ifndef __DP_PLL_10NM_H
+#define __DP_PLL_10NM_H
+
+#include "dp_pll.h"
+#include "dp_reg.h"
+
+#define DP_VCO_HSCLK_RATE_1620MHZDIV1000162UL
+#define DP_VCO_HSCLK_RATE_2700MHZDIV1000270UL
+#define DP_VCO_HSCLK_RATE_5400MHZDIV1000540UL
+#define DP_VCO_HSCLK_RATE_8100MHZDIV1000810UL
+
+#define NUM_DP_CLOCKS_MAX6
+
+#define DP_PHY_PLL_POLL_SLEEP_US500
+#define DP_PHY_PLL_POLL_TIMEOUT_US1
+
+#define DP_VCO_RATE_8100MHZDIV1000810UL
+#define DP_VCO_RATE_9720MHZDIV1000972UL
+#define DP_VCO_RATE_10800MHZDIV10001080UL
+
+struct dp_pll_vco_clk {
+struct clk_hw hw;
+unsigned longrate;/* current vco rate */
+u64min_rate;/* min vco rate */
+u64max_rate;/* max vco rate */
+void*priv;
+};
+
+struct dp_pll_db {
This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for
example, will use slightly different structure.
Sure, it sounds good. I will give it try. Thanks!
+struct msm_dp_pll *base;
+
+int id;
+struct platform_device *pdev;
+
+/* private clocks: */
+bool fixed_factor_clk[NUM_DP_CLOCKS_MAX];
+struct clk_hw *hws[NUM_DP_CLOCKS_MAX];
Then these two fields can use exact number of clocks rather than
NUM_DP_CLOCKS_MAX.
I didn't get this. I think NUM_DP_CLOCKS_MAX is doing same?
Not exactly. We'd need fixed_factor_clk[4] for 10nm rather than 6.
It's not that important, just a small nitpick.
+u32 num_hws;
+
+/* lane and orientation settings */
+u8 lane_cnt;
+u8 orientation;
+
+/* COM PHY settings */
+u32 hsclk_sel;
+u32 dec_start_mode0;
+u32 div_frac_start1_mode0;
+u32 div_frac_start2_mode0;
+u32 div_frac_start3_mode0;
+u32 integloop_gain0_mode0;
+u32 integloop_gain1_mode0;
+u32 vco_tune_map;
+u32 lock_cmp1_mode0;
+u32 lock_cmp2_mode0;
+u32 lock_cmp3_mode0;
+u32 lock_cmp_en;
+
+/* PHY vco divider */
+u32 phy_vco_div;
+/*
+ * Certain pll's needs to update the same vco rate after resume
in
+ * suspend/resume scenario. Cached the vco rate for such plls.
+ */
+unsigned longvco_cached_rate;
+u32cached_cfg0;
+u32cached_cfg1;
+u32cached_outdiv;
+
+uint32_t index;
+};
+
+static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw
*hw)
+{
+return container_of(hw, struct dp_pll_vco_clk, hw);
+}
+
+#define to_msm_dp_pll(vco) ((struct msm_dp_pll *)vco->priv)
+
+#define to_dp_pll_db(x)((struct dp_pll_db *)x->priv)
+
+int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate,
+unsigned long parent_rate);
+unsigned long dp_vco_recalc_rate_10nm(struct clk_hw *hw,
+unsigned long parent_rate);
+long dp_vco_round_rate_10nm(struct clk_hw *hw, unsigned long rate,
+unsigned long *parent_rate);
+int dp_vco_prepare_10nm(struct clk_hw *hw);
+void dp_vco_unprepare_10nm(struct clk_hw *hw);
+
+int msm_dp_pll_10nm_init(struct msm_dp_pll *dp_pll, int id);
+void msm_dp_pll_10nm_deinit(struct msm_dp_pll *dp_pll);
These functions don't seem to be used outside of dp_pll_10nm. What
about making them static?
I can't declare static to "init" and "deinit" as they are exported to
dp_pll.c.
Rest of them I can move to dp_pll_10nm and then define static.
Please exuse me for not being exact enough. Of course I meant
dp_vco_FOO_10nm() functions, not init/exit.
Ok got it. Sorry I didn't mean to nitpick here.
BTW: as I'm looking onto 7nm dp pll, which naming would you prefer?
I didn't get this. Did you mean naming convention of functions and
structure between
7nm and 10 nm? Could you point me where 7nm dp pll code is posted?
We can have separate DP_PLL_10nm/DP_PLL_7nm namespaces (as DSI PLLs
do) or I can override only a set of constants (like downstream driver
does).
Having separate namespace sounds good.
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[Bug 208909] amdgpu Ryzen 7 4700U NULL pointer dereference multi monitor with rotation
https://bugzilla.kernel.org/show_bug.cgi?id=208909 Alex Deucher (alexdeuc...@gmail.com) changed: What|Removed |Added CC||alexdeuc...@gmail.com --- Comment #1 from Alex Deucher (alexdeuc...@gmail.com) --- Please attach your full dmesg output and xorg log (if using X). -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 23/24] drm/virtio: implement blob resources: resource create blob ioctl
On Thu, Aug 13, 2020 at 07:39:59PM -0700, Gurchetan Singh wrote:
From: Gerd Hoffmann
Implement resource create blob as specified.
Signed-off-by: Gerd Hoffmann
Co-developed-by: Gurchetan Singh
Signed-off-by: Gurchetan Singh
Acked-by: Tomeu Vizoso
---
drivers/gpu/drm/virtio/virtgpu_drv.h| 4 +-
drivers/gpu/drm/virtio/virtgpu_ioctl.c | 136
drivers/gpu/drm/virtio/virtgpu_object.c | 5 +-
drivers/gpu/drm/virtio/virtgpu_vram.c | 2 +
4 files changed, 144 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h
b/drivers/gpu/drm/virtio/virtgpu_drv.h
index 444b65c8d4ee..3e9ec5b1fb63 100644
--- a/drivers/gpu/drm/virtio/virtgpu_drv.h
+++ b/drivers/gpu/drm/virtio/virtgpu_drv.h
@@ -255,8 +255,8 @@ struct virtio_gpu_fpriv {
struct mutex context_lock;
};
-/* virtgpu_ioctl.c */
-#define DRM_VIRTIO_NUM_IOCTLS 10
+/* virtio_ioctl.c */
+#define DRM_VIRTIO_NUM_IOCTLS 11
extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];
void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file);
diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
index 7dbe24248a20..47ac32b7031a 100644
--- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
+++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
@@ -34,6 +34,10 @@
#include "virtgpu_drv.h"
+#define VIRTGPU_BLOB_FLAG_USE_MASK (VIRTGPU_BLOB_FLAG_USE_MAPPABLE | \
+ VIRTGPU_BLOB_FLAG_USE_SHAREABLE | \
+ VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE)
+
void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file)
{
struct virtio_gpu_device *vgdev = dev->dev_private;
@@ -520,6 +524,134 @@ static int virtio_gpu_get_caps_ioctl(struct drm_device
*dev,
return 0;
}
+static int verify_blob(struct virtio_gpu_device *vgdev,
+ struct virtio_gpu_fpriv *vfpriv,
+ struct virtio_gpu_object_params *params,
+ struct drm_virtgpu_resource_create_blob *rc_blob,
+ bool *guest_blob, bool *host3d_blob)
+{
+ if (!vgdev->has_resource_blob)
+ return -EINVAL;
+
+ if ((rc_blob->blob_flags & ~VIRTGPU_BLOB_FLAG_USE_MASK) ||
+ !rc_blob->blob_flags)
+ return -EINVAL;
+
+ if (rc_blob->blob_flags & VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE) {
+ if (!vgdev->has_resource_assign_uuid)
+ return -EINVAL;
+ }
+
+ switch (rc_blob->blob_mem) {
+ case VIRTGPU_BLOB_MEM_GUEST:
+ *guest_blob = true;
+ break;
+ case VIRTGPU_BLOB_MEM_HOST3D_GUEST:
+ *guest_blob = true;
+ fallthrough;
+ case VIRTGPU_BLOB_MEM_HOST3D:
+ *host3d_blob = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (*host3d_blob) {
+ if (!vgdev->has_virgl_3d)
+ return -EINVAL;
+
+ /* Must be dword aligned. */
+ if ((rc_blob->cmd_size) % 4 != 0)
+ return -EINVAL;
+
+ params->ctx_id = vfpriv->ctx_id;
+ params->blob_id = rc_blob->blob_id;
+ } else {
+ if (rc_blob->blob_id != 0)
+ return -EINVAL;
+
+ if (rc_blob->cmd_size != 0)
+ return -EINVAL;
+ }
+
+ params->blob_mem = rc_blob->blob_mem;
+ params->size = rc_blob->size;
+ params->blob = true;
+ params->blob_flags = rc_blob->blob_flags;
+ return 0;
+}
+
+static int virtio_gpu_resource_create_blob(struct drm_device *dev,
+ void *data, struct drm_file *file)
+{
+ int ret = 0;
+ uint32_t handle = 0;
+ struct drm_gem_object *obj;
+ struct virtio_gpu_object *bo;
+ bool host3d_blob, guest_blob;
+ struct virtio_gpu_object_params params = { 0 };
+ struct virtio_gpu_device *vgdev = dev->dev_private;
+ struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
+ struct drm_virtgpu_resource_create_blob *rc_blob = data;
+
+ guest_blob = host3d_blob = false;
+ if (verify_blob(vgdev, vfpriv, , rc_blob,
+ _blob, _blob))
+ return -EINVAL;
+
+ if (vgdev->has_virgl_3d)
+ virtio_gpu_create_context(dev, file);
+
+ if (rc_blob->cmd_size) {
+ void *buf;
+
+ buf = memdup_user(u64_to_user_ptr(rc_blob->cmd),
+ rc_blob->cmd_size);
+
+ if (IS_ERR(buf))
+ return PTR_ERR(buf);
+
+ virtio_gpu_cmd_submit(vgdev, buf, rc_blob->cmd_size,
+ vfpriv->ctx_id, NULL, NULL);
+ }
+
+ if (guest_blob)
+ ret = virtio_gpu_object_create(vgdev, , , NULL);
+ else if (!guest_blob
Re: [Freedreno] [PATCH] drm/msm/adreno: remove return value of function XX_print
On Fri, Aug 14, 2020 at 01:17:44AM -0700, Bernard Zhao wrote:
> XX_print like pfp_print/me_print/meq_print/roq_print are just
> used in file a5xx_debugfs.c. And these function always return
> 0, this return value is meaningless.
> This change is to make the code a bit more readable.
This is reasonable. I'm always for negative lines.
Reviewed-by: Jordan Crouse
> Signed-off-by: Bernard Zhao
> ---
> drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 21 +++--
> 1 file changed, 7 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_debugfs.c
> b/drivers/gpu/drm/msm/adreno/a5xx_debugfs.c
> index 68eddac7771c..fc2c905b6c9e 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_debugfs.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_debugfs.c
> @@ -11,7 +11,7 @@
>
> #include "a5xx_gpu.h"
>
> -static int pfp_print(struct msm_gpu *gpu, struct drm_printer *p)
> +static void pfp_print(struct msm_gpu *gpu, struct drm_printer *p)
> {
> int i;
>
> @@ -22,11 +22,9 @@ static int pfp_print(struct msm_gpu *gpu, struct
> drm_printer *p)
> drm_printf(p, " %02x: %08x\n", i,
> gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA));
> }
> -
> - return 0;
> }
>
> -static int me_print(struct msm_gpu *gpu, struct drm_printer *p)
> +static void me_print(struct msm_gpu *gpu, struct drm_printer *p)
> {
> int i;
>
> @@ -37,11 +35,9 @@ static int me_print(struct msm_gpu *gpu, struct
> drm_printer *p)
> drm_printf(p, " %02x: %08x\n", i,
> gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA));
> }
> -
> - return 0;
> }
>
> -static int meq_print(struct msm_gpu *gpu, struct drm_printer *p)
> +static void meq_print(struct msm_gpu *gpu, struct drm_printer *p)
> {
> int i;
>
> @@ -52,11 +48,9 @@ static int meq_print(struct msm_gpu *gpu, struct
> drm_printer *p)
> drm_printf(p, " %02x: %08x\n", i,
> gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA));
> }
> -
> - return 0;
> }
>
> -static int roq_print(struct msm_gpu *gpu, struct drm_printer *p)
> +static void roq_print(struct msm_gpu *gpu, struct drm_printer *p)
> {
> int i;
>
> @@ -71,8 +65,6 @@ static int roq_print(struct msm_gpu *gpu, struct
> drm_printer *p)
> drm_printf(p, " %02x: %08x %08x %08x %08x\n", i,
> val[0], val[1], val[2], val[3]);
> }
> -
> - return 0;
> }
>
> static int show(struct seq_file *m, void *arg)
> @@ -81,10 +73,11 @@ static int show(struct seq_file *m, void *arg)
> struct drm_device *dev = node->minor->dev;
> struct msm_drm_private *priv = dev->dev_private;
> struct drm_printer p = drm_seq_file_printer(m);
> - int (*show)(struct msm_gpu *gpu, struct drm_printer *p) =
> + void (*show)(struct msm_gpu *gpu, struct drm_printer *p) =
> node->info_ent->data;
>
> - return show(priv->gpu, );
> + show(priv->gpu, );
> + return 0;
> }
>
> #define ENT(n) { .name = #n, .show = show, .data = n ##_print }
> --
> 2.26.2
>
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Re: drm modeset bugs
On Mon, Aug 17, 2020 at 3:08 AM Paul Blazejowski wrote: > > I would like to report some stack traces, while running kernel 5.8.x > I have observed these in my log (kernel 5.7.x is unaffected). Fixed with: https://patchwork.freedesktop.org/patch/385617/ Alex > > [4.996442] [drm] amdgpu kernel modesetting enabled. > [5.000833] CRAT table not found > [5.001889] Virtual CRAT table created for CPU > [5.003018] amdgpu: Topology: Add CPU node > [5.008825] kvm: Nested Virtualization enabled > [5.009899] SVM: kvm: Nested Paging enabled > [5.013884] checking generic (c000 7f) vs hw (c000 1000) > [5.014823] fb0: switching to amdgpudrmfb from EFI VGA > [5.016731] videodev: Linux video capture interface: v2.00 > [5.022065] Console: switching to colour dummy device 80x25 > [5.022112] amdgpu :01:00.0: vgaarb: deactivate vga console > [5.022234] [drm] initializing kernel modesetting (VERDE > 0x1002:0x683F 0x1682:0x7251 0x00). > [5.022240] amdgpu :01:00.0: amdgpu: Trusted Memory Zone (TMZ) > feature not supported > [5.022255] [drm] register mmio base: 0xFEA0 > [5.022258] [drm] register mmio size: 262144 > [5.022262] [drm] PCIE atomic ops is not supported > [5.022268] [drm] add ip block number 0 > [5.022271] [drm] add ip block number 1 > [5.022273] [drm] add ip block number 2 > [5.022276] [drm] add ip block number 3 > [5.022278] [drm] add ip block number 4 > [5.022281] [drm] add ip block number 5 > [5.022283] [drm] add ip block number 6 > [5.022288] kfd kfd: VERDE not supported in kfd > [5.050108] [drm] BIOS signature incorrect 0 0 > [5.050126] amdgpu :01:00.0: No more image in the PCI ROM > [5.050205] amdgpu: ATOM BIOS: 113-250EZNP10-W8 > [5.050701] [drm] vm size is 64 GB, 2 levels, block size is 10-bit, > fragment size is 9-bit > [5.053518] amdgpu :01:00.0: amdgpu: VRAM: 1024M > 0x00F4 - 0x00F43FFF (1024M used) > [5.053526] amdgpu :01:00.0: amdgpu: GART: 1024M > 0x00FF - 0x00FF3FFF > [5.053540] [drm] Detected VRAM RAM=1024M, BAR=256M > [5.053543] [drm] RAM width 128bits GDDR5 > [5.053607] [TTM] Zone kernel: Available graphics memory: 8181002 KiB > [5.053611] [TTM] Zone dma32: Available graphics memory: 2097152 KiB > [5.053614] [TTM] Initializing pool allocator > [5.053647] [TTM] Initializing DMA pool allocator > [5.053688] [drm] amdgpu: 1024M of VRAM memory ready > [5.053694] [drm] amdgpu: 3072M of GTT memory ready. > [5.053700] [drm] GART: num cpu pages 262144, num gpu pages 262144 > [5.054767] amdgpu :01:00.0: amdgpu: PCIE GART of 1024M enabled > (table at 0x00F4007E9000). > [5.054872] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > [5.061180] [drm] Internal thermal controller with fan control > [5.061195] [drm] amdgpu: dpm initialized > [5.061243] [drm] AMDGPU Display Connectors > [5.061246] [drm] Connector 0: > [5.061249] [drm] DP-1 > [5.061251] [drm] HPD4 > [5.061254] [drm] DDC: 0x1950 0x1950 0x1951 0x1951 0x1952 0x1952 > 0x1953 0x1953 > [5.061257] [drm] Encoders: > [5.061260] [drm] DFP1: INTERNAL_UNIPHY2 > [5.061262] [drm] Connector 1: > [5.061264] [drm] HDMI-A-1 > [5.061266] [drm] HPD1 > [5.061269] [drm] DDC: 0x195c 0x195c 0x195d 0x195d 0x195e 0x195e > 0x195f 0x195f > [5.061272] [drm] Encoders: > [5.061274] [drm] DFP2: INTERNAL_UNIPHY2 > [5.061277] [drm] Connector 2: > [5.061279] [drm] DVI-I-1 > [5.061281] [drm] HPD2 > [5.061283] [drm] DDC: 0x1958 0x1958 0x1959 0x1959 0x195a 0x195a > 0x195b 0x195b > [5.061287] [drm] Encoders: > [5.061289] [drm] DFP3: INTERNAL_UNIPHY > [5.061291] [drm] CRT1: INTERNAL_KLDSCP_DAC1 > [5.061824] usb 1-2: Warning! Unlikely big volume range (=3072), > cval->res is probably wrong. > [5.061834] usb 1-2: [5] FU [Mic Capture Volume] ch = 1, val = > 4608/7680/1 > [5.062076] [drm] PCIE gen 2 link speeds already enabled > [5.062405] usbcore: registered new interface driver snd-usb-audio > [5.062433] uvcvideo: Found UVC 1.00 device (046d:0990) > [5.108277] uvcvideo 1-2:1.0: Entity type for entity Extension 4 was > not initialized! > [5.108287] uvcvideo 1-2:1.0: Entity type for entity Extension 10 was > not initialized! > [5.108292] uvcvideo 1-2:1.0: Entity type for entity Extension 12 was > not initialized! > [5.108297] uvcvideo 1-2:1.0: Entity type for entity Extension 8 was > not initialized! > [5.108302] uvcvideo 1-2:1.0: Entity type for entity Extension 11 was > not initialized! > [5.108307] uvcvideo 1-2:1.0: Entity type for entity Extension 9 was > not initialized! > [5.108311] uvcvideo 1-2:1.0: Entity type for entity Processing 2 was > not initialized! > [5.108317] uvcvideo 1-2:1.0: Entity type for entity Extension 13 was > not
Re: [Freedreno] [PATCH 19/19] drm/msm: show process names in gem_describe
On Thu, Aug 13, 2020 at 07:41:14PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> In $debugfs/gem we already show any vma(s) associated with an object.
> Also show process names if the vma's address space is a per-process
> address space.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_drv.c | 2 +-
> drivers/gpu/drm/msm/msm_gem.c | 25 +
> drivers/gpu/drm/msm/msm_gem.h | 5 +
> drivers/gpu/drm/msm/msm_gem_vma.c | 1 +
> drivers/gpu/drm/msm/msm_gpu.c | 8 +---
> drivers/gpu/drm/msm/msm_gpu.h | 2 +-
> 6 files changed, 34 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index 8e70d220bba8..8d5c4f98c332 100644
> --- a/drivers/gpu/drm/msm/msm_drv.c
> +++ b/drivers/gpu/drm/msm/msm_drv.c
> @@ -597,7 +597,7 @@ static int context_init(struct drm_device *dev, struct
> drm_file *file)
> kref_init(>ref);
> msm_submitqueue_init(dev, ctx);
>
> - ctx->aspace = msm_gpu_create_private_address_space(priv->gpu);
> + ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
> file->driver_priv = ctx;
>
> return 0;
> diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
> index 3cb7aeb93fd3..76a6c5271e57 100644
> --- a/drivers/gpu/drm/msm/msm_gem.c
> +++ b/drivers/gpu/drm/msm/msm_gem.c
> @@ -842,11 +842,28 @@ void msm_gem_describe(struct drm_gem_object *obj,
> struct seq_file *m)
>
> seq_puts(m, " vmas:");
>
> - list_for_each_entry(vma, _obj->vmas, list)
> - seq_printf(m, " [%s: %08llx,%s,inuse=%d]",
> - vma->aspace != NULL ? vma->aspace->name : NULL,
> - vma->iova, vma->mapped ? "mapped" : "unmapped",
> + list_for_each_entry(vma, _obj->vmas, list) {
> + const char *name, *comm;
> + if (vma->aspace) {
> + struct msm_gem_address_space *aspace =
> vma->aspace;
> + struct task_struct *task =
> + get_pid_task(aspace->pid, PIDTYPE_PID);
> + if (task) {
> + comm = kstrdup(task->comm, GFP_KERNEL);
> + } else {
> + comm = NULL;
> + }
> + name = aspace->name;
> + } else {
> + name = comm = NULL;
> + }
> + seq_printf(m, " [%s%s%s: aspace=%p,
> %08llx,%s,inuse=%d]",
> + name, comm ? ":" : "", comm ? comm : "",
> + vma->aspace, vma->iova,
> + vma->mapped ? "mapped" : "unmapped",
> vma->inuse);
> + kfree(comm);
> + }
>
> seq_puts(m, "\n");
> }
> diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
> index 9c573c4269cb..7b1c7a5f8eef 100644
> --- a/drivers/gpu/drm/msm/msm_gem.h
> +++ b/drivers/gpu/drm/msm/msm_gem.h
> @@ -24,6 +24,11 @@ struct msm_gem_address_space {
> spinlock_t lock; /* Protects drm_mm node allocation/removal */
> struct msm_mmu *mmu;
> struct kref kref;
> +
> + /* For address spaces associated with a specific process, this
> + * will be non-NULL:
> + */
> + struct pid *pid;
> };
>
> struct msm_gem_vma {
> diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c
> b/drivers/gpu/drm/msm/msm_gem_vma.c
> index 29cc1305cf37..80a8a266d68f 100644
> --- a/drivers/gpu/drm/msm/msm_gem_vma.c
> +++ b/drivers/gpu/drm/msm/msm_gem_vma.c
> @@ -17,6 +17,7 @@ msm_gem_address_space_destroy(struct kref *kref)
> drm_mm_takedown(>mm);
> if (aspace->mmu)
> aspace->mmu->funcs->destroy(aspace->mmu);
> + put_pid(aspace->pid);
> kfree(aspace);
> }
>
> diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
> index 951850804d77..ac8961187a73 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.c
> +++ b/drivers/gpu/drm/msm/msm_gpu.c
> @@ -825,10 +825,9 @@ static int get_clocks(struct platform_device *pdev,
> struct msm_gpu *gpu)
>
> /* Return a new address space for a msm_drm_private instance */
> struct msm_gem_address_space *
> -msm_gpu_create_private_address_space(struct msm_gpu *gpu)
> +msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct
> *task)
> {
> struct msm_gem_address_space *aspace = NULL;
> -
> if (!gpu)
> return NULL;
>
> @@ -836,8 +835,11 @@ msm_gpu_create_private_address_space(struct msm_gpu *gpu)
>* If the target doesn't support private address spaces then return
>* the global one
>*/
> - if
Re: [PATCH] drm/msm/gpu: make ringbuffer readonly
On Mon, Aug 17, 2020 at 09:23:09AM -0700, Rob Clark wrote:
> From: Rob Clark
>
> The GPU has no business writing into the ringbuffer, let's make it
> readonly to the GPU.
Yep. There are some additional things we can do in the a6xx family to make this
even more robust but for the vast majority of targets out in this world this is
a good and necessary fix.
Reviewed-by: Jordan Crouse
> Fixes: 7198e6b03155 ("drm/msm: add a3xx gpu support")
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_ringbuffer.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c
> b/drivers/gpu/drm/msm/msm_ringbuffer.c
> index e397c44cc011..39ecb5a18431 100644
> --- a/drivers/gpu/drm/msm/msm_ringbuffer.c
> +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
> @@ -27,7 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu
> *gpu, int id,
> ring->id = id;
>
> ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
> - MSM_BO_WC, gpu->aspace, >bo, >iova);
> + MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, >bo,
> + >iova);
>
> if (IS_ERR(ring->start)) {
> ret = PTR_ERR(ring->start);
> --
> 2.26.2
>
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Re: [PATCH 07/19] drm/msm: set adreno_smmu as gpu's drvdata
On Thu, Aug 13, 2020 at 07:41:02PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> This will be populated by adreno-smmu, to provide a way for coordinating
> enabling/disabling TTBR0 translation.
>
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 2 --
> drivers/gpu/drm/msm/msm_gpu.c | 2 +-
> drivers/gpu/drm/msm/msm_gpu.h | 6 +-
> 3 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
> b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index 26664e1b30c0..58e03b20e1c7 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -417,8 +417,6 @@ static int adreno_bind(struct device *dev, struct device
> *master, void *data)
> return PTR_ERR(gpu);
> }
>
> - dev_set_drvdata(dev, gpu);
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
> index 6aa9e04e52e7..806eb0957280 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.c
> +++ b/drivers/gpu/drm/msm/msm_gpu.c
> @@ -892,7 +892,7 @@ int msm_gpu_init(struct drm_device *drm, struct
> platform_device *pdev,
> gpu->gpu_cx = NULL;
>
> gpu->pdev = pdev;
> - platform_set_drvdata(pdev, gpu);
> + platform_set_drvdata(pdev, >adreno_smmu);
>
> msm_devfreq_init(gpu);
>
> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> index 8bda7beaed4b..f91b141add75 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.h
> +++ b/drivers/gpu/drm/msm/msm_gpu.h
> @@ -7,6 +7,7 @@
> #ifndef __MSM_GPU_H__
> #define __MSM_GPU_H__
>
> +#include
> #include
> #include
> #include
> @@ -73,6 +74,8 @@ struct msm_gpu {
> struct platform_device *pdev;
> const struct msm_gpu_funcs *funcs;
>
> + struct adreno_smmu_priv adreno_smmu;
> +
> /* performance counters (hw & sw): */
> spinlock_t perf_lock;
> bool perfcntr_active;
> @@ -143,7 +146,8 @@ struct msm_gpu {
>
> static inline struct msm_gpu *dev_to_gpu(struct device *dev)
> {
> - return dev_get_drvdata(dev);
> + struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
> + return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
> }
>
> /* It turns out that all targets use the same ringbuffer size */
> --
> 2.26.2
>
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Re: [Freedreno] [PATCH 06/19] drm/msm/gpu: add dev_to_gpu() helper
On Thu, Aug 13, 2020 at 07:41:01PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> In a later patch, the drvdata will not directly be 'struct msm_gpu *',
> so add a helper to reduce the churn.
>
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 10 --
> drivers/gpu/drm/msm/msm_gpu.c | 6 +++---
> drivers/gpu/drm/msm/msm_gpu.h | 5 +
> 3 files changed, 12 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
> b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index 9eeb46bf2a5d..26664e1b30c0 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -282,7 +282,7 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
> int ret;
>
> if (pdev)
> - gpu = platform_get_drvdata(pdev);
> + gpu = dev_to_gpu(>dev);
>
> if (!gpu) {
> dev_err_once(dev->dev, "no GPU device was found\n");
> @@ -425,7 +425,7 @@ static int adreno_bind(struct device *dev, struct device
> *master, void *data)
> static void adreno_unbind(struct device *dev, struct device *master,
> void *data)
> {
> - struct msm_gpu *gpu = dev_get_drvdata(dev);
> + struct msm_gpu *gpu = dev_to_gpu(dev);
>
> pm_runtime_force_suspend(dev);
> gpu->funcs->destroy(gpu);
> @@ -490,16 +490,14 @@ static const struct of_device_id dt_match[] = {
> #ifdef CONFIG_PM
> static int adreno_resume(struct device *dev)
> {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct msm_gpu *gpu = platform_get_drvdata(pdev);
> + struct msm_gpu *gpu = dev_to_gpu(dev);
>
> return gpu->funcs->pm_resume(gpu);
> }
>
> static int adreno_suspend(struct device *dev)
> {
> - struct platform_device *pdev = to_platform_device(dev);
> - struct msm_gpu *gpu = platform_get_drvdata(pdev);
> + struct msm_gpu *gpu = dev_to_gpu(dev);
>
> return gpu->funcs->pm_suspend(gpu);
> }
> diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
> index d5645472b25d..6aa9e04e52e7 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.c
> +++ b/drivers/gpu/drm/msm/msm_gpu.c
> @@ -24,7 +24,7 @@
> static int msm_devfreq_target(struct device *dev, unsigned long *freq,
> u32 flags)
> {
> - struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
> + struct msm_gpu *gpu = dev_to_gpu(dev);
> struct dev_pm_opp *opp;
>
> opp = devfreq_recommended_opp(dev, freq, flags);
> @@ -45,7 +45,7 @@ static int msm_devfreq_target(struct device *dev, unsigned
> long *freq,
> static int msm_devfreq_get_dev_status(struct device *dev,
> struct devfreq_dev_status *status)
> {
> - struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
> + struct msm_gpu *gpu = dev_to_gpu(dev);
> ktime_t time;
>
> if (gpu->funcs->gpu_get_freq)
> @@ -64,7 +64,7 @@ static int msm_devfreq_get_dev_status(struct device *dev,
>
> static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
> {
> - struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
> + struct msm_gpu *gpu = dev_to_gpu(dev);
>
> if (gpu->funcs->gpu_get_freq)
> *freq = gpu->funcs->gpu_get_freq(gpu);
> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> index 0db117a7339b..8bda7beaed4b 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.h
> +++ b/drivers/gpu/drm/msm/msm_gpu.h
> @@ -141,6 +141,11 @@ struct msm_gpu {
> struct msm_gpu_state *crashstate;
> };
>
> +static inline struct msm_gpu *dev_to_gpu(struct device *dev)
> +{
> + return dev_get_drvdata(dev);
> +}
> +
> /* It turns out that all targets use the same ringbuffer size */
> #define MSM_GPU_RINGBUFFER_SZ SZ_32K
> #define MSM_GPU_RINGBUFFER_BLKSIZE 32
> --
> 2.26.2
>
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Re: [Freedreno] [PATCH 05/19] iommu: add private interface for adreno-smmu
On Thu, Aug 13, 2020 at 07:41:00PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> This interface will be used for drm/msm to coordinate with the
> qcom_adreno_smmu_impl to enable/disable TTBR0 translation.
>
> Once TTBR0 translation is enabled, the GPU's CP (Command Processor)
> will directly switch TTBR0 pgtables (and do the necessary TLB inv)
> synchronized to the GPU's operation. But help from the SMMU driver
> is needed to initially bootstrap TTBR0 translation, which cannot be
> done from the GPU.
>
> Since this is a very special case, a private interface is used to
> avoid adding highly driver specific things to the public iommu
> interface.
>
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> include/linux/adreno-smmu-priv.h | 36
> 1 file changed, 36 insertions(+)
> create mode 100644 include/linux/adreno-smmu-priv.h
>
> diff --git a/include/linux/adreno-smmu-priv.h
> b/include/linux/adreno-smmu-priv.h
> new file mode 100644
> index ..a889f28afb42
> --- /dev/null
> +++ b/include/linux/adreno-smmu-priv.h
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2020 Google, Inc
> + */
> +
> +#ifndef __ADRENO_SMMU_PRIV_H
> +#define __ADRENO_SMMU_PRIV_H
> +
> +#include
> +
> +/**
> + * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
> + *
> + * @cookie:An opque token provided by adreno-smmu and passed
> + * back into the callbacks
> + * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank
> + * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A
> + * NULL config disables TTBR0 translation, otherwise
> + * TTBR0 translation is enabled with the specified cfg
> + *
> + * The GPU driver (drm/msm) and adreno-smmu work together for controlling
> + * the GPU's SMMU instance. This is by necessity, as the GPU is directly
> + * updating the SMMU for context switches, while on the other hand we do
> + * not want to duplicate all of the initial setup logic from arm-smmu.
> + *
> + * This private interface is used for the two drivers to coordinate. The
> + * cookie and callback functions are populated when the GPU driver attaches
> + * it's domain.
> + */
> +struct adreno_smmu_priv {
> +const void *cookie;
> +const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
> +int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg
> *cfg);
> +};
> +
> +#endif /* __ADRENO_SMMU_PRIV_H */
> \ No newline at end of file
> --
> 2.26.2
>
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Re: [PATCH 01/19] drm/msm: remove dangling submitqueue references
On Thu, Aug 13, 2020 at 07:40:56PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> Currently it doesn't matter, since we free the ctx immediately. But
> when we start refcnt'ing the ctx, we don't want old dangling list
> entries to hang around.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c
> b/drivers/gpu/drm/msm/msm_submitqueue.c
> index a1d94be7883a..90c9d84e6155 100644
> --- a/drivers/gpu/drm/msm/msm_submitqueue.c
> +++ b/drivers/gpu/drm/msm/msm_submitqueue.c
> @@ -49,8 +49,10 @@ void msm_submitqueue_close(struct msm_file_private *ctx)
>* No lock needed in close and there won't
>* be any more user ioctls coming our way
>*/
> - list_for_each_entry_safe(entry, tmp, >submitqueues, node)
> + list_for_each_entry_safe(entry, tmp, >submitqueues, node) {
> + list_del(>node);
> msm_submitqueue_put(entry);
> + }
> }
>
> int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private
> *ctx,
> --
> 2.26.2
>
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Re: [PATCH 00/19] iommu/arm-smmu + drm/msm: per-process GPU pgtables
On Thu, Aug 13, 2020 at 07:40:55PM -0700, Rob Clark wrote: > From: Rob Clark > > NOTE: Since Jordan was out today, and I wanted to keep things moving on > this, I took the liberty of respinning his series (originally > titled "iommu/arm-smmu: Add Adreno SMMU specific implementation") > with updates based on Will's review comments, and some fixes and > extra bits that I found in stress testing the series. Original > commit msg and updated version history below. > > In general I like the private interface between adreno-smmu and > the GPU driver. It should make for a more straightforward way > to extend things to optimize TLB invalidation in the future, for > example, rather than shoe-horning everything thru domain attrs. > And it lets us describe the get_ttbr1_cfg/set_ttrb0_cfg dance > more clearly. Although it is going to make landing this via > iommu vs drm tree a bit more difficult. Maybe there are some > arm-smmu parts of this series that could be pulled out to make > it not conflicty to land the private interface and adreno-smmu > bits via the drm tree? (But I'm jumping a bit ahead here. Just > wanted to point out that issue.) > > The complete series can be found at: > https://gitlab.freedesktop.org/drm/msm/-/commits/msm-next-pgtables > > This series adds an Adreno SMMU implementation to arm-smmu to allow GPU > hardware > pagetable switching. > > The Adreno GPU has built in capabilities to switch the TTBR0 pagetable during > runtime to allow each individual instance or application to have its own > pagetable. In order to take advantage of the HW capabilities there are > certain > requirements needed of the SMMU hardware. > > This series adds support for an Adreno specific arm-smmu implementation. The > new > implementation 1) ensures that the GPU domain is always assigned context bank > 0, > 2) enables split pagetable support (TTBR1) so that the instance specific > pagetable can be swapped while the global memory remains in place and 3) > shares > the current pagetable configuration with the GPU driver to allow it to create > its own io-pgtable instances. > > The series then adds the drm/msm code to enable these features. For targets > that > support it allocate new pagetables using the io-pgtable configuration shared > by > the arm-smmu driver and swap them in during runtime. > > This version of the series merges the previous patchset(s) [1] and [2] > with the following improvements: > > v13: (Respin by Rob) > - Switch to a private interface between adreno-smmu and GPU driver, > dropping the custom domain attr (Will Deacon) > - Rework the SCTLR.HUPCF patch to add new fields in smmu_domain->cfg > rather than adding new impl hook (Will Deacon) > - Drop for_each_cfg_sme() in favor of plain for() loop (Will Deacon) > - Fix context refcnt'ing issue which was causing problems with GPU > crash recover stress testing. > - Spiff up $debugfs/gem to show process information associated with > VMAs I'll add the tags to Rob's code but in general I ack all these changes. I also like the private interface - it gives us the most flexibility without either changing the IOMMU API or giving up entirely and making an internal SMMU implementation inside drm/msm. Jordan -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 16/19] drm/msm/a6xx: Add support for per-instance pagetables
On Mon, Aug 17, 2020 at 09:10:46PM +0530, Akhil P Oommen wrote:
> On 8/14/2020 8:11 AM, Rob Clark wrote:
> >From: Jordan Crouse
> >
> >Add support for using per-instance pagetables if all the dependencies are
> >available.
> >
> >Signed-off-by: Jordan Crouse
> >Signed-off-by: Rob Clark
> >---
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 +++
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
> > drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
> > 3 files changed, 72 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >index 5eabb0109577..9653ac9b3cb8 100644
> >--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >@@ -81,6 +81,56 @@ static void get_stats_counter(struct msm_ringbuffer
> >*ring, u32 counter,
> > OUT_RING(ring, upper_32_bits(iova));
> > }
> >+static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
> >+struct msm_ringbuffer *ring, struct msm_file_private *ctx)
> >+{
> >+phys_addr_t ttbr;
> >+u32 asid;
> >+u64 memptr = rbmemptr(ring, ttbr0);
> >+
> >+if (ctx == a6xx_gpu->cur_ctx)
> >+return;
> >+
> >+if (msm_iommu_pagetable_params(ctx->aspace->mmu, , ))
> >+return;
> >+
> >+/* Execute the table update */
> >+OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
> >+OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
> >+
> >+/*
> >+ * For now ignore the asid since the smmu driver uses a TLBIASID to
> >+ * flush the TLB when we use iommu_flush_tlb_all() and the smmu driver
> >+ * isn't aware that the asid changed. Instead, keep the default asid
> >+ * (0, same as the context bank) to make sure the TLB is properly
> >+ * flushed.
> >+ */
> >+OUT_RING(ring,
> >+CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
> >+CP_SMMU_TABLE_UPDATE_1_ASID(0));
> >+OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
> >+OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
> >+
> >+/*
> >+ * Write the new TTBR0 to the memstore. This is good for debugging.
> >+ */
> >+OUT_PKT7(ring, CP_MEM_WRITE, 4);
> >+OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
> >+OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
> >+OUT_RING(ring, lower_32_bits(ttbr));
> >+OUT_RING(ring, (0 << 16) | upper_32_bits(ttbr));
> why (0 << 16) is required here?
Because that is the ASID we are using and we would want the debug TTBR0 to match
the hardware as closely as possible.
> >+
> >+/*
> >+ * And finally, trigger a uche flush to be sure there isn't anything
> >+ * lingering in that part of the GPU
> >+ */
> >+
> >+OUT_PKT7(ring, CP_EVENT_WRITE, 1);
> >+OUT_RING(ring, 0x31);
> This may be unnecessary, but no harm in keeping it. SMMU_TABLE_UPDATE is
> supposed to do a UCHE flush.
Correct but I think it is wise to try to match the downstream sequence as much
as possible.
Jordan
> -Akhil
> >+
> >+a6xx_gpu->cur_ctx = ctx;
> >+}
> >+
> > static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
> > {
> > unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
> >@@ -90,6 +140,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct
> >msm_gem_submit *submit)
> > struct msm_ringbuffer *ring = submit->ring;
> > unsigned int i;
> >+a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
> >+
> > get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
> > rbmemptr_stats(ring, index, cpcycles_start));
> >@@ -696,6 +748,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
> > /* Always come up on rb 0 */
> > a6xx_gpu->cur_ring = gpu->rb[0];
> >+a6xx_gpu->cur_ctx = NULL;
> >+
> > /* Enable the SQE_to start the CP engine */
> > gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
> >@@ -1008,6 +1062,21 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu
> >*gpu)
> > return (unsigned long)busy_time;
> > }
> >+static struct msm_gem_address_space *
> >+a6xx_create_private_address_space(struct msm_gpu *gpu)
> >+{
> >+struct msm_gem_address_space *aspace = NULL;
> >+struct msm_mmu *mmu;
> >+
> >+mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
> >+
> >+if (!IS_ERR(mmu))
> >+aspace = msm_gem_address_space_create(mmu,
> >+"gpu", 0x1ULL, 0x1ULL);
> >+
> >+return aspace;
> >+}
> >+
> > static const struct adreno_gpu_funcs funcs = {
> > .base = {
> > .get_param = adreno_get_param,
> >@@ -1031,6 +1100,7 @@ static const struct adreno_gpu_funcs funcs = {
> > .gpu_state_put = a6xx_gpu_state_put,
> > #endif
> > .create_address_space = adreno_iommu_create_address_space,
> >+.create_private_address_space =
> >a6xx_create_private_address_space,
> > },
> > .get_timestamp = a6xx_get_timestamp,
> >
Re: [PATCH] drm/msm/adreno: fix updating ring fence
On Wed, Aug 12, 2020 at 05:03:09PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> We need to set it to the most recent completed fence, not the most
> recent submitted. Otherwise we have races where we think we can retire
> submits that the GPU is not finished with, if the GPU doesn't manage to
> overwrite the seqno before we look at it.
>
> This can show up with hang recovery if one of the submits after the
> crashing submit also hangs after it is replayed.
Reviewed-by: Jordan Crouse
> Fixes: f97decac5f4c ("drm/msm: Support multiple ringbuffers")
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index f9e3badf2fca..34e6242c1767 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -405,7 +405,7 @@ int adreno_hw_init(struct msm_gpu *gpu)
> ring->next = ring->start;
>
> /* reset completed fence seqno: */
> - ring->memptrs->fence = ring->seqno;
> + ring->memptrs->fence = ring->fctx->completed_fence;
> ring->memptrs->rptr = 0;
> }
>
> --
> 2.26.2
>
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Re: [RFC PATCH v1] dma-fence-array: Deal with sub-fences that are signaled late
On Thu, Aug 13, 2020 at 07:49:24AM +0100, Chris Wilson wrote: > Quoting Jordan Crouse (2020-08-13 00:55:44) > > This is an RFC because I'm still trying to grok the correct behavior. > > > > Consider a dma_fence_array created two two fence and signal_on_any is true. > > A reference to dma_fence_array is taken for each waiting fence. > > > > When the client calls dma_fence_wait() only one of the fences is signaled. > > The client returns successfully from the wait and puts it's reference to > > the array fence but the array fence still remains because of the remaining > > un-signaled fence. > > > > Now consider that the unsignaled fence is signaled while the timeline is > > being > > destroyed much later. The timeline destroy calls dma_fence_signal_locked(). > > The > > following sequence occurs: > > > > 1) dma_fence_array_cb_func is called > > > > 2) array->num_pending is 0 (because it was set to 1 due to signal_on_any) > > so the > > callback function calls dma_fence_put() instead of triggering the irq work > > > > 3) The array fence is released which in turn puts the lingering fence which > > is > > then released > > > > 4) deadlock with the timeline > > It's the same recursive lock as we previously resolved in sw_sync.c by > removing the locking from timeline_fence_release(). Ah, yep. I'm working on a not-quite-ready-for-primetime version of a vulkan timeline implementation for drm/msm and I was doing something similar to how sw_sync used to work in the release function. Getting rid of the recursive lock in the timeline seems a better solution than this. Thanks for taking the time to respond. Jordan > -Chris -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/msm/gpu: make ringbuffer readonly
From: Rob Clark
The GPU has no business writing into the ringbuffer, let's make it
readonly to the GPU.
Fixes: 7198e6b03155 ("drm/msm: add a3xx gpu support")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_ringbuffer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c
b/drivers/gpu/drm/msm/msm_ringbuffer.c
index e397c44cc011..39ecb5a18431 100644
--- a/drivers/gpu/drm/msm/msm_ringbuffer.c
+++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
@@ -27,7 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu
*gpu, int id,
ring->id = id;
ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
- MSM_BO_WC, gpu->aspace, >bo, >iova);
+ MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, >bo,
+ >iova);
if (IS_ERR(ring->start)) {
ret = PTR_ERR(ring->start);
--
2.26.2
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[PATCH 5.4 132/270] drm/stm: repair runtime power management
From: Marek Vasut
[ Upstream commit ebd267b2e3c25d5f93a08528b47c036569eb8744 ]
Add missing pm_runtime_get_sync() into ltdc_crtc_atomic_enable() to
match pm_runtime_put_sync() in ltdc_crtc_atomic_disable(), otherwise
the LTDC might suspend via runtime PM, disable clock, and then fail
to resume later on.
The test which triggers it is roughly -- run qt5 application which
uses eglfs platform and etnaviv, stop the application, sleep for 15
minutes, run the application again. This leads to a timeout waiting
for vsync, because the LTDC has suspended, but did not resume.
Fixes: 35ab6cfbf211 ("drm/stm: support runtime power management")
Signed-off-by: Marek Vasut
Cc: Yannick Fertré
Cc: Philippe Cornu
Cc: Benjamin Gaignard
Cc: Vincent Abriou
Cc: Maxime Coquelin
Cc: Alexandre Torgue
To: dri-devel@lists.freedesktop.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Acked-by: Philippe Cornu
Tested-by: Yannick Fertre
Signed-off-by: Benjamin Gaignard
Link:
https://patchwork.freedesktop.org/patch/msgid/20200229221649.90813-1-ma...@denx.de
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/stm/ltdc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 3ab4fbf8eb0d1..51571f7246abf 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -424,9 +424,12 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
{
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ struct drm_device *ddev = crtc->dev;
DRM_DEBUG_DRIVER("\n");
+ pm_runtime_get_sync(ddev->dev);
+
/* Sets the background color value */
reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
--
2.25.1
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[PATCH 5.7 192/393] drm/stm: repair runtime power management
From: Marek Vasut
[ Upstream commit ebd267b2e3c25d5f93a08528b47c036569eb8744 ]
Add missing pm_runtime_get_sync() into ltdc_crtc_atomic_enable() to
match pm_runtime_put_sync() in ltdc_crtc_atomic_disable(), otherwise
the LTDC might suspend via runtime PM, disable clock, and then fail
to resume later on.
The test which triggers it is roughly -- run qt5 application which
uses eglfs platform and etnaviv, stop the application, sleep for 15
minutes, run the application again. This leads to a timeout waiting
for vsync, because the LTDC has suspended, but did not resume.
Fixes: 35ab6cfbf211 ("drm/stm: support runtime power management")
Signed-off-by: Marek Vasut
Cc: Yannick Fertré
Cc: Philippe Cornu
Cc: Benjamin Gaignard
Cc: Vincent Abriou
Cc: Maxime Coquelin
Cc: Alexandre Torgue
To: dri-devel@lists.freedesktop.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Acked-by: Philippe Cornu
Tested-by: Yannick Fertre
Signed-off-by: Benjamin Gaignard
Link:
https://patchwork.freedesktop.org/patch/msgid/20200229221649.90813-1-ma...@denx.de
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/stm/ltdc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index df585fe64f614..60ffe5bbc1294 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -425,9 +425,12 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
{
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ struct drm_device *ddev = crtc->dev;
DRM_DEBUG_DRIVER("\n");
+ pm_runtime_get_sync(ddev->dev);
+
/* Sets the background color value */
reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
--
2.25.1
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Re: [PATCH 16/19] drm/msm/a6xx: Add support for per-instance pagetables
On Mon, Aug 17, 2020 at 8:41 AM Akhil P Oommen wrote:
>
> On 8/14/2020 8:11 AM, Rob Clark wrote:
> > From: Jordan Crouse
> >
> > Add support for using per-instance pagetables if all the dependencies are
> > available.
> >
> > Signed-off-by: Jordan Crouse
> > Signed-off-by: Rob Clark
> > ---
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 +++
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
> > drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
> > 3 files changed, 72 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > index 5eabb0109577..9653ac9b3cb8 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > @@ -81,6 +81,56 @@ static void get_stats_counter(struct msm_ringbuffer
> > *ring, u32 counter,
> > OUT_RING(ring, upper_32_bits(iova));
> > }
> >
> > +static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
> > + struct msm_ringbuffer *ring, struct msm_file_private *ctx)
> > +{
> > + phys_addr_t ttbr;
> > + u32 asid;
> > + u64 memptr = rbmemptr(ring, ttbr0);
> > +
> > + if (ctx == a6xx_gpu->cur_ctx)
> > + return;
> > +
> > + if (msm_iommu_pagetable_params(ctx->aspace->mmu, , ))
> > + return;
> > +
> > + /* Execute the table update */
> > + OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
> > + OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
> > +
> > + /*
> > + * For now ignore the asid since the smmu driver uses a TLBIASID to
> > + * flush the TLB when we use iommu_flush_tlb_all() and the smmu driver
> > + * isn't aware that the asid changed. Instead, keep the default asid
> > + * (0, same as the context bank) to make sure the TLB is properly
> > + * flushed.
> > + */
> > + OUT_RING(ring,
> > + CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
> > + CP_SMMU_TABLE_UPDATE_1_ASID(0));
> > + OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
> > + OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
> > +
> > + /*
> > + * Write the new TTBR0 to the memstore. This is good for debugging.
> > + */
> > + OUT_PKT7(ring, CP_MEM_WRITE, 4);
> > + OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
> > + OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
> > + OUT_RING(ring, lower_32_bits(ttbr));
> > + OUT_RING(ring, (0 << 16) | upper_32_bits(ttbr));
> why (0 << 16) is required here?
That would normally be (asid << 16), except due to the way we
currently flush tlb, we need to use asid==0..
(Although msm_iommu_pagetable_params() should return asid==0, I fixed
that in msm_iommu_pagetable_create() and didn't notice that Jordan had
fixed that here instead)
BR,
-R
> > +
> > + /*
> > + * And finally, trigger a uche flush to be sure there isn't anything
> > + * lingering in that part of the GPU
> > + */
> > +
> > + OUT_PKT7(ring, CP_EVENT_WRITE, 1);
> > + OUT_RING(ring, 0x31);
> This may be unnecessary, but no harm in keeping it. SMMU_TABLE_UPDATE is
> supposed to do a UCHE flush.
>
> -Akhil
> > +
> > + a6xx_gpu->cur_ctx = ctx;
> > +}
> > +
> > static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit
> > *submit)
> > {
> > unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
> > @@ -90,6 +140,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct
> > msm_gem_submit *submit)
> > struct msm_ringbuffer *ring = submit->ring;
> > unsigned int i;
> >
> > + a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
> > +
> > get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
> > rbmemptr_stats(ring, index, cpcycles_start));
> >
> > @@ -696,6 +748,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
> > /* Always come up on rb 0 */
> > a6xx_gpu->cur_ring = gpu->rb[0];
> >
> > + a6xx_gpu->cur_ctx = NULL;
> > +
> > /* Enable the SQE_to start the CP engine */
> > gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
> >
> > @@ -1008,6 +1062,21 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu
> > *gpu)
> > return (unsigned long)busy_time;
> > }
> >
> > +static struct msm_gem_address_space *
> > +a6xx_create_private_address_space(struct msm_gpu *gpu)
> > +{
> > + struct msm_gem_address_space *aspace = NULL;
> > + struct msm_mmu *mmu;
> > +
> > + mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
> > +
> > + if (!IS_ERR(mmu))
> > + aspace = msm_gem_address_space_create(mmu,
> > + "gpu", 0x1ULL, 0x1ULL);
> > +
> > + return aspace;
> > +}
> > +
> > static const struct adreno_gpu_funcs funcs = {
> > .base = {
> > .get_param = adreno_get_param,
> > @@ -1031,6 +1100,7 @@ static const struct adreno_gpu_funcs funcs = {
> >
Re: [PATCH 16/19] drm/msm/a6xx: Add support for per-instance pagetables
On 8/14/2020 8:11 AM, Rob Clark wrote:
From: Jordan Crouse
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
3 files changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 5eabb0109577..9653ac9b3cb8 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -81,6 +81,56 @@ static void get_stats_counter(struct msm_ringbuffer *ring,
u32 counter,
OUT_RING(ring, upper_32_bits(iova));
}
+static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
+ struct msm_ringbuffer *ring, struct msm_file_private *ctx)
+{
+ phys_addr_t ttbr;
+ u32 asid;
+ u64 memptr = rbmemptr(ring, ttbr0);
+
+ if (ctx == a6xx_gpu->cur_ctx)
+ return;
+
+ if (msm_iommu_pagetable_params(ctx->aspace->mmu, , ))
+ return;
+
+ /* Execute the table update */
+ OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
+ OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
+
+ /*
+* For now ignore the asid since the smmu driver uses a TLBIASID to
+* flush the TLB when we use iommu_flush_tlb_all() and the smmu driver
+* isn't aware that the asid changed. Instead, keep the default asid
+* (0, same as the context bank) to make sure the TLB is properly
+* flushed.
+*/
+ OUT_RING(ring,
+ CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
+ CP_SMMU_TABLE_UPDATE_1_ASID(0));
+ OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
+ OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
+
+ /*
+* Write the new TTBR0 to the memstore. This is good for debugging.
+*/
+ OUT_PKT7(ring, CP_MEM_WRITE, 4);
+ OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
+ OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
+ OUT_RING(ring, lower_32_bits(ttbr));
+ OUT_RING(ring, (0 << 16) | upper_32_bits(ttbr));
why (0 << 16) is required here?
+
+ /*
+* And finally, trigger a uche flush to be sure there isn't anything
+* lingering in that part of the GPU
+*/
+
+ OUT_PKT7(ring, CP_EVENT_WRITE, 1);
+ OUT_RING(ring, 0x31);
This may be unnecessary, but no harm in keeping it. SMMU_TABLE_UPDATE is
supposed to do a UCHE flush.
-Akhil
+
+ a6xx_gpu->cur_ctx = ctx;
+}
+
static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
{
unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
@@ -90,6 +140,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit)
struct msm_ringbuffer *ring = submit->ring;
unsigned int i;
+ a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
+
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
rbmemptr_stats(ring, index, cpcycles_start));
@@ -696,6 +748,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
/* Always come up on rb 0 */
a6xx_gpu->cur_ring = gpu->rb[0];
+ a6xx_gpu->cur_ctx = NULL;
+
/* Enable the SQE_to start the CP engine */
gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
@@ -1008,6 +1062,21 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
return (unsigned long)busy_time;
}
+static struct msm_gem_address_space *
+a6xx_create_private_address_space(struct msm_gpu *gpu)
+{
+ struct msm_gem_address_space *aspace = NULL;
+ struct msm_mmu *mmu;
+
+ mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
+
+ if (!IS_ERR(mmu))
+ aspace = msm_gem_address_space_create(mmu,
+ "gpu", 0x1ULL, 0x1ULL);
+
+ return aspace;
+}
+
static const struct adreno_gpu_funcs funcs = {
.base = {
.get_param = adreno_get_param,
@@ -1031,6 +1100,7 @@ static const struct adreno_gpu_funcs funcs = {
.gpu_state_put = a6xx_gpu_state_put,
#endif
.create_address_space = adreno_iommu_create_address_space,
+ .create_private_address_space =
a6xx_create_private_address_space,
},
.get_timestamp = a6xx_get_timestamp,
};
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 03ba60d5b07f..da22d7549d9b 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -19,6 +19,7 @@ struct a6xx_gpu {
uint64_t sqe_iova;
struct msm_ringbuffer *cur_ring;
+ struct msm_file_private *cur_ctx;
struct a6xx_gmu gmu;
};
diff --git
[PATCH 5.8 218/464] drm/stm: repair runtime power management
From: Marek Vasut
[ Upstream commit ebd267b2e3c25d5f93a08528b47c036569eb8744 ]
Add missing pm_runtime_get_sync() into ltdc_crtc_atomic_enable() to
match pm_runtime_put_sync() in ltdc_crtc_atomic_disable(), otherwise
the LTDC might suspend via runtime PM, disable clock, and then fail
to resume later on.
The test which triggers it is roughly -- run qt5 application which
uses eglfs platform and etnaviv, stop the application, sleep for 15
minutes, run the application again. This leads to a timeout waiting
for vsync, because the LTDC has suspended, but did not resume.
Fixes: 35ab6cfbf211 ("drm/stm: support runtime power management")
Signed-off-by: Marek Vasut
Cc: Yannick Fertré
Cc: Philippe Cornu
Cc: Benjamin Gaignard
Cc: Vincent Abriou
Cc: Maxime Coquelin
Cc: Alexandre Torgue
To: dri-devel@lists.freedesktop.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Acked-by: Philippe Cornu
Tested-by: Yannick Fertre
Signed-off-by: Benjamin Gaignard
Link:
https://patchwork.freedesktop.org/patch/msgid/20200229221649.90813-1-ma...@denx.de
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/stm/ltdc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index f894968d6e452..3f590d916e916 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -423,9 +423,12 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
{
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ struct drm_device *ddev = crtc->dev;
DRM_DEBUG_DRIVER("\n");
+ pm_runtime_get_sync(ddev->dev);
+
/* Sets the background color value */
reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
--
2.25.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/dp_mst: Don't return error code when crtc is null
Oh-just noticed this is also missing a CC for sta...@vger.kernel.org. I'll add it before pushing but please make sure to follow the guidelines here when submitting fixes, since otherwise they might not get backported automatically to older kernels: https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html (you can ignore the "It cannot be bigger than 100 lines, with context." part, as long as you're not trying to backport new functionality to stable and you're actually fixing something they're pretty leniant about that rule) On Mon, 2020-08-17 at 11:21 -0400, Lyude Paul wrote: > Reviewed-by: Lyude Paul > > I will go ahead and push this to drm-misc-fixes, thanks! > > On Fri, 2020-08-14 at 13:01 -0400, Bhawanpreet Lakha wrote: > > [Why] > > In certain cases the crtc can be NULL and returning -EINVAL causes > > atomic check to fail when it shouln't. This leads to valid > > configurations failing because atomic check fails. > > > > [How] > > Don't early return if crtc is null > > > > Signed-off-by: Bhawanpreet Lakha > > --- > > drivers/gpu/drm/drm_dp_mst_topology.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > > b/drivers/gpu/drm/drm_dp_mst_topology.c > > index 70c4b7afed12..bc90a1485699 100644 > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > @@ -5037,8 +5037,8 @@ int drm_dp_mst_add_affected_dsc_crtcs(struct > > drm_atomic_state *state, struct drm > > > > crtc = conn_state->crtc; > > > > - if (WARN_ON(!crtc)) > > - return -EINVAL; > > + if (!crtc) > > + continue; > > > > if (!drm_dp_mst_dsc_aux_for_port(pos->port)) > > continue; -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/dp_mst: Don't return error code when crtc is null
Reviewed-by: Lyude Paul I will go ahead and push this to drm-misc-fixes, thanks! On Fri, 2020-08-14 at 13:01 -0400, Bhawanpreet Lakha wrote: > [Why] > In certain cases the crtc can be NULL and returning -EINVAL causes > atomic check to fail when it shouln't. This leads to valid > configurations failing because atomic check fails. > > [How] > Don't early return if crtc is null > > Signed-off-by: Bhawanpreet Lakha > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > b/drivers/gpu/drm/drm_dp_mst_topology.c > index 70c4b7afed12..bc90a1485699 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -5037,8 +5037,8 @@ int drm_dp_mst_add_affected_dsc_crtcs(struct > drm_atomic_state *state, struct drm > > crtc = conn_state->crtc; > > - if (WARN_ON(!crtc)) > - return -EINVAL; > + if (!crtc) > + continue; > > if (!drm_dp_mst_dsc_aux_for_port(pos->port)) > continue; -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [RFC] Experimental DMA-BUF Device Heaps
Hi Ezequiel, On Sun, Aug 16, 2020 at 02:22:46PM -0300, Ezequiel Garcia wrote: > This heap is basically a wrapper around DMA-API dma_alloc_attrs, > which will allocate memory suitable for the given device. > > The implementation is mostly a port of the Contiguous Videobuf2 > memory allocator (see videobuf2/videobuf2-dma-contig.c) > over to the DMA-BUF Heap interface. > > The intention of this allocator is to provide applications > with a more system-agnostic API: the only thing the application > needs to know is which device to get the buffer for. > > Whether the buffer is backed by CMA, IOMMU or a DMA Pool > is unknown to the application. > > I'm not really expecting this patch to be correct or even > a good idea, but just submitting it to start a discussion on DMA-BUF > heap discovery and negotiation. > My initial reaction is that I thought dmabuf heaps are meant for use to allocate buffers for sharing across devices, which doesn't fit very well with having per-device heaps. For single-device allocations, would using the buffer allocation functionality of that device's native API be better in most cases? (Some other possibly relevant discussion at [1]) I can see that this can save some boilerplate for devices that want to expose private chunks of memory, but might it also lead to 100 aliases for the system's generic coherent memory pool? I wonder if a set of helpers to allow devices to expose whatever they want with minimal effort would be better. Cheers, -Brian 1. https://lore.kernel.org/dri-devel/57062477-30e7-a3de-6723-a50d03a40...@kapsi.fi/ > Given Plumbers is just a couple weeks from now, I've submitted > a BoF proposal to discuss this, as perhaps it would make > sense to discuss this live? > > Not-signed-off-by: Ezequiel Garcia ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 207763] Noisy Screen in Linux with kernel 5
https://bugzilla.kernel.org/show_bug.cgi?id=207763 --- Comment #4 from Alex Deucher (alexdeuc...@gmail.com) --- Created attachment 290955 --> https://bugzilla.kernel.org/attachment.cgi?id=290955=edit revert Does this revert fix the issue? -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 1/2] drm/scheduler: Scheduler priority fixes (v2)
Am 15.08.20 um 04:48 schrieb Luben Tuikov:
Remove DRM_SCHED_PRIORITY_LOW, as it was used
in only one place.
Rename and separate by a line
DRM_SCHED_PRIORITY_MAX to DRM_SCHED_PRIORITY_COUNT
as it represents a (total) count of said
priorities and it is used as such in loops
throughout the code. (0-based indexing is the
the count number.)
Remove redundant word HIGH in priority names,
and rename *KERNEL* to *HIGH*, as it really
means that, high.
v2: Add back KERNEL and remove SW and HW,
in lieu of a single HIGH between NORMAL and KERNEL.
Signed-off-by: Luben Tuikov
I can't really judge the difference between MAX and COUNT, but the we
rename the values and get rid of the invalid one sounds like a good idea
to me.
Reviewed-by: Christian König for the series.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
drivers/gpu/drm/scheduler/sched_main.c| 4 ++--
include/drm/gpu_scheduler.h | 12 +++-
8 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index d85d13f7a043..68eaa4f687a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -46,7 +46,7 @@ const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM]
= {
static int amdgpu_ctx_priority_permit(struct drm_file *filp,
enum drm_sched_priority priority)
{
- if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
+ if (priority < 0 || priority >= DRM_SCHED_PRIORITY_COUNT)
return -EINVAL;
/* NORMAL and below are accessible by everyone */
@@ -65,7 +65,7 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp,
static enum gfx_pipe_priority amdgpu_ctx_sched_prio_to_compute_prio(enum
drm_sched_priority prio)
{
switch (prio) {
- case DRM_SCHED_PRIORITY_HIGH_HW:
+ case DRM_SCHED_PRIORITY_HIGH:
case DRM_SCHED_PRIORITY_KERNEL:
return AMDGPU_GFX_PIPE_PRIO_HIGH;
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 75d37dfb51aa..bb9e5481ff3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -251,7 +251,7 @@ void amdgpu_job_stop_all_jobs_on_sched(struct
drm_gpu_scheduler *sched)
int i;
/* Signal all jobs not yet scheduled */
- for (i = DRM_SCHED_PRIORITY_MAX - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
+ for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN;
i--) {
struct drm_sched_rq *rq = >sched_rq[i];
if (!rq)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 13ea8ebc421c..6d4fc79bf84a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -267,7 +267,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct
amdgpu_ring *ring,
>sched;
}
- for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
+ for (i = DRM_SCHED_PRIORITY_MIN; i < DRM_SCHED_PRIORITY_COUNT; ++i)
atomic_set(>num_jobs[i], 0);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index da871d84b742..7112137689db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -243,7 +243,7 @@ struct amdgpu_ring {
boolhas_compute_vm_bug;
boolno_scheduler;
- atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX];
+ atomic_tnum_jobs[DRM_SCHED_PRIORITY_COUNT];
struct mutexpriority_mutex;
/* protected by priority_mutex */
int priority;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
index c799691dfa84..17661ede9488 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
@@ -36,14 +36,14 @@ enum drm_sched_priority amdgpu_to_sched_priority(int
amdgpu_priority)
{
switch (amdgpu_priority) {
case AMDGPU_CTX_PRIORITY_VERY_HIGH:
- return DRM_SCHED_PRIORITY_HIGH_HW;
+ return DRM_SCHED_PRIORITY_HIGH;
case AMDGPU_CTX_PRIORITY_HIGH:
- return DRM_SCHED_PRIORITY_HIGH_SW;
+ return DRM_SCHED_PRIORITY_HIGH;
case AMDGPU_CTX_PRIORITY_NORMAL:
return DRM_SCHED_PRIORITY_NORMAL;
case AMDGPU_CTX_PRIORITY_LOW:
case AMDGPU_CTX_PRIORITY_VERY_LOW:
- return
[PATCH v2 2/2] tty/sysrq: Add configurable handler to execute a compound action
Userland might want to execute e.g. 'w' (show blocked tasks), followed
by 's' (sync), followed by 1000 ms delay and then followed by 'c' (crash)
upon a single magic SysRq. Or one might want to execute the famous "Raising
Elephants Is So Utterly Boring" action. This patch adds a configurable
handler, triggered with 'C', for this exact purpose. The user specifies the
composition of the compound action using syntax similar to getopt, where
each letter corresponds to an individual action and a colon followed by a
number corresponds to a delay of that many milliseconds, e.g.:
ws:1000c
or
r:100eis:1000ub
Signed-off-by: Andrzej Pietrasiewicz
---
Documentation/admin-guide/sysrq.rst | 9
drivers/tty/sysrq.c | 82 -
include/linux/sysrq.h | 1 +
3 files changed, 91 insertions(+), 1 deletion(-)
diff --git a/Documentation/admin-guide/sysrq.rst
b/Documentation/admin-guide/sysrq.rst
index 67dfa4c29093..80bdd8bf9636 100644
--- a/Documentation/admin-guide/sysrq.rst
+++ b/Documentation/admin-guide/sysrq.rst
@@ -32,6 +32,7 @@ to 1. Here is the list of possible values in
/proc/sys/kernel/sysrq:
64 = 0x40 - enable signalling of processes (term, kill, oom-kill)
128 = 0x80 - allow reboot/poweroff
256 = 0x100 - allow nicing of all RT tasks
+512 = 0x200 - allow compound action
You can set the value in the file by the following command::
@@ -148,6 +149,14 @@ CommandFunction
``z`` Dump the ftrace buffer
+``C`` Execute a predefined, compound action. The action is defined with
+ sysrq.sysrq_compound_action module parameter, whose value contains
known
+ command keys (except ``C`` to prevent recursion). The command keys
can
+ be optionally followed by a colon and a number of milliseconds to
wait
+ after executing the last action. For example:
+
+ sysrq.sysrq_compound_action=r:100eis:1000ub
+
``0``-``9`` Sets the console log level, controlling which kernel messages
will be printed to your console. (``0``, for example would make
it so that only emergency messages like PANICs or OOPSes would
diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c
index 959f9e121cc6..fec770de325b 100644
--- a/drivers/tty/sysrq.c
+++ b/drivers/tty/sysrq.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -438,6 +439,15 @@ static const struct sysrq_key_op sysrq_unrt_op = {
.enable_mask= SYSRQ_ENABLE_RTNICE,
};
+static void sysrq_action_compound(int key);
+
+static struct sysrq_key_op sysrq_action_compound_op = {
+ .handler= sysrq_action_compound,
+ .help_msg = "execute-compound-action(C)",
+ .action_msg = "Execute compound action",
+ .enable_mask= SYSRQ_ENABLE_COMPOUND,
+};
+
/* Key Operations table and lock */
static DEFINE_SPINLOCK(sysrq_key_table_lock);
@@ -500,7 +510,7 @@ static const struct sysrq_key_op *sysrq_key_table[62] = {
_ftrace_dump_op, /* z */
NULL, /* A */
NULL, /* B */
- NULL, /* C */
+ _action_compound_op, /* C */
NULL, /* D */
NULL, /* E */
NULL, /* F */
@@ -633,6 +643,7 @@ EXPORT_SYMBOL(handle_sysrq);
#ifdef CONFIG_INPUT
static int sysrq_reset_downtime_ms;
+static char *sysrq_compound_action;
/* Simple translation table for the SysRq keys */
static const unsigned char sysrq_xlate[KEY_CNT] =
@@ -786,6 +797,62 @@ static void sysrq_of_get_keyreset_config(void)
{
}
#endif
+#define SYSRQ_COMPOUND_ACTION_VALIDATE 0
+#define SYSRQ_COMPOUND_ACTION_RUN 1
+
+static int sysrq_process_compound_action(int pass)
+{
+ const char *action = sysrq_compound_action;
+ const struct sysrq_key_op *op_p;
+ int ret;
+ unsigned int delay;
+
+ while (*action) {
+ op_p = __sysrq_get_key_op(*action);
+ if (!op_p)
+ return -EINVAL;
+
+ /* Don't allow calling ourselves recursively */
+ if (op_p == _action_compound_op)
+ return -EINVAL;
+
+ if (pass == SYSRQ_COMPOUND_ACTION_RUN)
+ __handle_sysrq(*action, false);
+
+ if (*++action == ':') {
+ ret = sscanf(action++, ":%u", );
+ if (ret < 1) /* we want at least ":[0-9]" => 1 item */
+ return -EINVAL;
+
+ while (*action >= '0' && *action <= '9')
+ ++action;
+ if (pass == SYSRQ_COMPOUND_ACTION_RUN)
+ mdelay(delay);
+ }
+ }
+
+ return 0;
+}
+
+static void sysrq_action_compound(int
[PATCH v2 1/2] tty/sysrq: Extend the sysrq_key_table to cover capital letters
All slots in sysrq_key_table[] are either used, reserved or at least
commented with their intended use. This patch adds capital letter versions
available, which means adding 26 more entries.
For already existing SysRq operations the user presses Alt-SysRq-, and
for the newly added ones Alt-Shift-SysRq-.
Signed-off-by: Andrzej Pietrasiewicz
---
Documentation/admin-guide/sysrq.rst | 2 ++
drivers/gpu/drm/drm_fb_helper.c | 2 +-
drivers/tty/sysrq.c | 49 +++--
3 files changed, 50 insertions(+), 3 deletions(-)
diff --git a/Documentation/admin-guide/sysrq.rst
b/Documentation/admin-guide/sysrq.rst
index e6424d8c5846..67dfa4c29093 100644
--- a/Documentation/admin-guide/sysrq.rst
+++ b/Documentation/admin-guide/sysrq.rst
@@ -79,6 +79,8 @@ On all
echo t > /proc/sysrq-trigger
+The :kbd:`` is case sensitive.
+
What are the 'command' keys?
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 8697554ccd41..1543d9d10970 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -325,7 +325,7 @@ static void drm_fb_helper_sysrq(int dummy1)
static const struct sysrq_key_op sysrq_drm_fb_helper_restore_op = {
.handler = drm_fb_helper_sysrq,
- .help_msg = "force-fb(V)",
+ .help_msg = "force-fb(v)",
.action_msg = "Restore framebuffer console",
};
#else
diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c
index a8e39b2cdd55..959f9e121cc6 100644
--- a/drivers/tty/sysrq.c
+++ b/drivers/tty/sysrq.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -440,7 +441,7 @@ static const struct sysrq_key_op sysrq_unrt_op = {
/* Key Operations table and lock */
static DEFINE_SPINLOCK(sysrq_key_table_lock);
-static const struct sysrq_key_op *sysrq_key_table[36] = {
+static const struct sysrq_key_op *sysrq_key_table[62] = {
_loglevel_op, /* 0 */
_loglevel_op, /* 1 */
_loglevel_op, /* 2 */
@@ -497,6 +498,32 @@ static const struct sysrq_key_op *sysrq_key_table[36] = {
/* y: May be registered on sparc64 for global register dump */
NULL, /* y */
_ftrace_dump_op, /* z */
+ NULL, /* A */
+ NULL, /* B */
+ NULL, /* C */
+ NULL, /* D */
+ NULL, /* E */
+ NULL, /* F */
+ NULL, /* G */
+ NULL, /* H */
+ NULL, /* I */
+ NULL, /* J */
+ NULL, /* K */
+ NULL, /* L */
+ NULL, /* M */
+ NULL, /* N */
+ NULL, /* O */
+ NULL, /* P */
+ NULL, /* Q */
+ NULL, /* R */
+ NULL, /* S */
+ NULL, /* T */
+ NULL, /* U */
+ NULL, /* V */
+ NULL, /* W */
+ NULL, /* X */
+ NULL, /* Y */
+ NULL, /* Z */
};
/* key2index calculation, -1 on invalid index */
@@ -508,6 +535,8 @@ static int sysrq_key_table_key2index(int key)
retval = key - '0';
else if ((key >= 'a') && (key <= 'z'))
retval = key + 10 - 'a';
+ else if ((key >= 'A') && (key <= 'Z'))
+ retval = key + 36 - 'A';
else
retval = -1;
return retval;
@@ -621,6 +650,8 @@ struct sysrq_state {
unsigned long key_down[BITS_TO_LONGS(KEY_CNT)];
unsigned int alt;
unsigned int alt_use;
+ unsigned int shift;
+ unsigned int shift_use;
bool active;
bool need_reinject;
bool reinjecting;
@@ -805,10 +836,20 @@ static bool sysrq_handle_keypress(struct sysrq_state
*sysrq,
}
break;
+ case KEY_LEFTSHIFT:
+ case KEY_RIGHTSHIFT:
+ if (!value)
+ sysrq->shift = KEY_RESERVED;
+ else if (value != 2)
+ sysrq->shift = code;
+ break;
+
case KEY_SYSRQ:
if (value == 1 && sysrq->alt != KEY_RESERVED) {
sysrq->active = true;
sysrq->alt_use = sysrq->alt;
+ /* either RESERVED (for released) or actual code */
+ sysrq->shift_use = sysrq->shift;
/*
[PATCH v2 0/2] Add configurable handler to execute a compound action
This is a follow-up of this thread: https://www.spinics.net/lists/linux-input/msg68446.html It only touches DRM (dri-devel) in such a way that it changes the help message of sysrq_drm_fb_helper_restore_op, otherwise it is unrelated to DRM. Patch 2/2 adds a configurable handler to execute a compound action. Userland might want to execute e.g. 'w' (show blocked tasks), followed by 's' (sync), followed by 1000 ms delay and then followed by 'c' (crash) upon a single magic SysRq. Or one might want to execute the famous "Raising Elephants Is So Utterly Boring" action. This patch adds a configurable handler, triggered with 'C', for this exact purpose. The user specifies the composition of the compound action using syntax similar to getopt, where each letter corresponds to an individual action and a colon followed by a number corresponds to a delay of that many milliseconds, e.g.: ws:1000c or r:100eis:1000ub An example of userspace that wants to perform a compound action is Chrome OS, where SysRq-X (pressed for the second time within a certain time period from the first time) causes showing the locked tasks, syncing, waiting a 1000 ms delay and crashing the system. Since all the slots in the sysrq_key_table[] are already taken or reserved, patch 1/2 extends it to cover also capital letter versions. v1..v2: - used toupper() instead of opencoding it (Jiri Slaby) - updated help message of sysrq_drm_fb_helper_restore_op (Jiri Slaby) - used unsigned int for specifying delays (Jiri Slaby) - improved printed messages formatting (Jiri Slaby) Andrzej Pietrasiewicz (2): tty/sysrq: Extend the sysrq_key_table to cover capital letters tty/sysrq: Add configurable handler to execute a compound action Documentation/admin-guide/sysrq.rst | 11 +++ drivers/gpu/drm/drm_fb_helper.c | 2 +- drivers/tty/sysrq.c | 129 +++- include/linux/sysrq.h | 1 + 4 files changed, 140 insertions(+), 3 deletions(-) base-commit: 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2] drm/mediatek: dsi: fix scrolling of panel with small hfp or hbp
horizontal_backporch_byte should be hbp * bpp - hbp extra bytes.
So remove the wrong subtraction 10.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 270bf22c98fe..5d031e634571 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -473,14 +473,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
- horizontal_backporch_byte =
- (vm->hback_porch * dsi_tmp_buf_bpp - 10);
+ horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp;
else
- horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
- dsi_tmp_buf_bpp - 10);
+ horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
+ dsi_tmp_buf_bpp;
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
- timing->da_hs_zero + timing->da_hs_exit + 3;
+ timing->da_hs_zero + timing->da_hs_exit;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
--
2.12.5
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Re: DRM/KMS experimental drivers for HiKey 970
Hi Daniel, Em Wed, 5 Aug 2020 13:04:18 +0200 Daniel Vetter escreveu: > > > > I've been working to get upstream support for the DRM driver on HiKey > > > > 970. > > > > > > > > While the patches are not ready yet for upstream merge, I'm placing > > > > what I've sone so far on this repository: > > > > > > > > > > > > https://github.com/mchehab/linux/tree/hikey970/to_upstream-2.0-v1.1 I already started the process of submitting the pending drivers which are required for the DRM driver to work (regulators and IOMMU). I'm now planning what to do with the DRM KMS driver. This driver is somewhat similar to the Kirin 6220 driver, but the display engine uses a different set of registers which are chipset specific. My port should work with either Kirin 960 or 970, although, so far, I tested only the Kirin 970 part. Besides its size, the driver is pretty much a standard KMS driver that uses emulation framebuffer. Yet, as I said before, it currently has some bugs that are hard to debug and fix, as the downstream version also has them. John has a different port, which works only for Kirin 960, adding some functionality on the existing Kirin 6220 driver. Based on the history on his WIP tree, it sounds to me that the same bugs I'm facing are also present on his port. The known bugs are: - EDID reads via adv7135 don't work properly. Adding a delay on some part of adv7135 code may help, but that sounds to me more like a hack than a final solution; - There are some underflows on a something called LDI. This is the worse bug, as, once it happens, the hardware stops changing the displayed image. At John's tree for Kirin 960, there were several attempts (and several reverts), trying to address it. Based on a comment at the downstream version, at least for Kirin 970 I suspect that this could be due to a too low clock frequency, but increasing it alone breaks the driver. I suspect that other clock frequencies would need to be adjusted, but I don't know how to adjust the other clocks for it to work with a higher frequency; - There's currently a hack at the valid modesetting logic; only modes that are known to work return MODE_OK. I'm planning to test my port on Kirin 960 soon, and ensure that the DRM driver will work for both chipsets. In the future, I'm planning to try merging support for all 3 Kirin variants at the same driver, probably using part of John's approach for Kirin 960. In any case, considering the existing bugs, plus the eventual future work in order to support multiple Kirin variants at the same driver, I would prefer merging this driver first at staging. Would that be acceptable? Thanks, Mauro ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [RESEND PATCH] drm/msm/a6xx: fix frequency not always being restored on GMU resume
Why don't we move the early return in a6xx_gmu_set_freq() to
msm_devfreq_target() instead?
-Akhil.
On 8/14/2020 12:24 AM, Jonathan Marek wrote:
The patch reorganizing the set_freq function made it so the gmu resume
doesn't always set the frequency, because a6xx_gmu_set_freq() exits early
when the frequency hasn't been changed. Note this always happens when
resuming GMU after recovering from a hang.
Use a simple workaround to prevent this from happening.
Fixes: 1f60d11423db ("drm: msm: a6xx: send opp instead of a frequency")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index b67b38c8fadf..bbbd00020f92 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -845,6 +845,7 @@ static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu,
struct a6xx_gmu *gmu)
if (IS_ERR_OR_NULL(gpu_opp))
return;
+ gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
a6xx_gmu_set_freq(gpu, gpu_opp);
dev_pm_opp_put(gpu_opp);
}
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Re: [virtio-dev] Re: [PATCH v5 0/3] Support virtio cross-device resources
On Mon, Aug 17, 2020 at 12:50:08PM +0200, Gerd Hoffmann wrote: > On Tue, Jun 23, 2020 at 10:31:28AM +0900, David Stevens wrote: > > Unless there are any remaining objections to these patches, what are > > the next steps towards getting these merged? Sorry, I'm not familiar > > with the workflow for contributing patches to Linux. > > Sorry, just have been busy and not paying as much attention to drm > patches as usual. Playing catch-up now. Queued for drm-misc-next, > unless something goes wrong in my testing the patches should land > in linux-next soon and be merged upstream in the next merge window. Oh, spoke too soon. scripts/checkpatch.pl has a bunch of codestyle warnings. Can you fix them and resend? thanks, Gerd ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 2/2] xen: add helpers to allocate unpopulated memory
On Thu, Aug 13, 2020 at 08:33:37AM +0100, Christoph Hellwig wrote: > On Tue, Aug 11, 2020 at 11:44:47AM +0200, Roger Pau Monne wrote: > > If enabled (because ZONE_DEVICE is supported) the usage of the new > > functionality untangles Xen balloon and RAM hotplug from the usage of > > unpopulated physical memory ranges to map foreign pages, which is the > > correct thing to do in order to avoid mappings of foreign pages depend > > on memory hotplug. > > So please just select ZONE_DEVICE if this is so much better rather > than maintaining two variants. We still need to other variant for Arm at least, so both need to be maintained anyway, even if we force ZONE_DEVICE on x86. Thanks, Roger. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 2/2] xen: add helpers to allocate unpopulated memory
On Fri, Aug 14, 2020 at 02:54:38PM +0200, Jürgen Groß wrote: > On 14.08.20 14:47, Roger Pau Monné wrote: > > On Fri, Aug 14, 2020 at 12:27:32PM +0200, Jürgen Groß wrote: > > > On 14.08.20 11:56, Roger Pau Monné wrote: > > > > On Fri, Aug 14, 2020 at 08:29:20AM +0100, Christoph Hellwig wrote: > > > > > On Thu, Aug 13, 2020 at 09:54:20AM +0200, Roger Pau Monn?? wrote: > > > > > > On Thu, Aug 13, 2020 at 08:33:37AM +0100, Christoph Hellwig wrote: > > > > > > > On Tue, Aug 11, 2020 at 11:44:47AM +0200, Roger Pau Monne wrote: > > > > > > > > If enabled (because ZONE_DEVICE is supported) the usage of the > > > > > > > > new > > > > > > > > functionality untangles Xen balloon and RAM hotplug from the > > > > > > > > usage of > > > > > > > > unpopulated physical memory ranges to map foreign pages, which > > > > > > > > is the > > > > > > > > correct thing to do in order to avoid mappings of foreign pages > > > > > > > > depend > > > > > > > > on memory hotplug. > > > > > > > > > > > > > > So please just select ZONE_DEVICE if this is so much better rather > > > > > > > than maintaining two variants. > > > > > > > > > > > > We still need to other variant for Arm at least, so both need to be > > > > > > maintained anyway, even if we force ZONE_DEVICE on x86. > > > > > > > > > > Well, it still really helps reproducability if you stick to one > > > > > implementation of x86. > > > > > > > > > > The alternative would be an explicit config option to opt into it, > > > > > but just getting a different implementation based on a random > > > > > kernel option is strange. > > > > > > > > Would adding something like the chunk below to the patch be OK? > > > > > > > > ---8<--- > > > > diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig > > > > index 018020b91baa..5f321a1319e6 100644 > > > > --- a/drivers/xen/Kconfig > > > > +++ b/drivers/xen/Kconfig > > > > @@ -328,7 +328,14 @@ config XEN_FRONT_PGDIR_SHBUF > > > > tristate > > > >config XEN_UNPOPULATED_ALLOC > > > > - bool > > > > - default y if ZONE_DEVICE && !ARM && !ARM64 > > > > + bool "Use unpopulated memory ranges for guest mappings" > > > > + depends on X86 > > > > + select ZONE_DEVICE > > > > + default y > > > > > > I'd rather use "default XEN_BACKEND" here, as mappings of other guest's > > > memory is rarely used for non-backend guests. > > > > There's also the privcmd and gnt devices which make heavy use of this, > > so I'm not sure only selecting by default on XEN_BACKEND is the best > > option. > > I just want to avoid that kernels built for running as Xen guest, but > not as dom0, will be forced to select ZONE_DEVICE. > > As privcmd is dom0-only, this is no problem. Oh, didn't know that, I somehow assumed privcmd would be available to all Xen guests regardless of whether dom0 support was selected. > In case you are worrying about gnt devices, I'd be fine to switch to > > default XEN_BACKEND || XEN_GNTDEV Sure. maybe even: default XEN_BACKEND || XEN_GNTDEV || XEN_DOM0 Do you want me to resend with this changed or are you happy to fixup if there are no further comments? Thanks, Roger. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/qxl: Replace deprecated function in qxl_display
On Sun, May 24, 2020 at 11:26:23AM +0900, Sidong Yang wrote: > Hi, Dave. > > This is resended e-mail for your advice. > > I'm a newbie interested in linux kernel and qxl module. > Please check this patch and give me advice for me. > Also I'll be glad if there is any task that you bothered. > Thanks. > > Sidong. > > Replace deprecated function drm_modeset_lock/unlock_all with > helper function DRM_MODESET_LOCK_ALL_BEGIN/END. > > Signed-off-by: Sidong Yang Queued for drm-misc-next. thanks, Gerd ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 2/2] xen: add helpers to allocate unpopulated memory
On Fri, Aug 14, 2020 at 12:27:32PM +0200, Jürgen Groß wrote: > On 14.08.20 11:56, Roger Pau Monné wrote: > > On Fri, Aug 14, 2020 at 08:29:20AM +0100, Christoph Hellwig wrote: > > > On Thu, Aug 13, 2020 at 09:54:20AM +0200, Roger Pau Monn?? wrote: > > > > On Thu, Aug 13, 2020 at 08:33:37AM +0100, Christoph Hellwig wrote: > > > > > On Tue, Aug 11, 2020 at 11:44:47AM +0200, Roger Pau Monne wrote: > > > > > > If enabled (because ZONE_DEVICE is supported) the usage of the new > > > > > > functionality untangles Xen balloon and RAM hotplug from the usage > > > > > > of > > > > > > unpopulated physical memory ranges to map foreign pages, which is > > > > > > the > > > > > > correct thing to do in order to avoid mappings of foreign pages > > > > > > depend > > > > > > on memory hotplug. > > > > > > > > > > So please just select ZONE_DEVICE if this is so much better rather > > > > > than maintaining two variants. > > > > > > > > We still need to other variant for Arm at least, so both need to be > > > > maintained anyway, even if we force ZONE_DEVICE on x86. > > > > > > Well, it still really helps reproducability if you stick to one > > > implementation of x86. > > > > > > The alternative would be an explicit config option to opt into it, > > > but just getting a different implementation based on a random > > > kernel option is strange. > > > > Would adding something like the chunk below to the patch be OK? > > > > ---8<--- > > diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig > > index 018020b91baa..5f321a1319e6 100644 > > --- a/drivers/xen/Kconfig > > +++ b/drivers/xen/Kconfig > > @@ -328,7 +328,14 @@ config XEN_FRONT_PGDIR_SHBUF > > tristate > > config XEN_UNPOPULATED_ALLOC > > - bool > > - default y if ZONE_DEVICE && !ARM && !ARM64 > > + bool "Use unpopulated memory ranges for guest mappings" > > + depends on X86 > > + select ZONE_DEVICE > > + default y > > I'd rather use "default XEN_BACKEND" here, as mappings of other guest's > memory is rarely used for non-backend guests. There's also the privcmd and gnt devices which make heavy use of this, so I'm not sure only selecting by default on XEN_BACKEND is the best option. Thanks, Roger. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 2/2] xen: add helpers to allocate unpopulated memory
On Fri, Aug 14, 2020 at 08:29:20AM +0100, Christoph Hellwig wrote: > On Thu, Aug 13, 2020 at 09:54:20AM +0200, Roger Pau Monn?? wrote: > > On Thu, Aug 13, 2020 at 08:33:37AM +0100, Christoph Hellwig wrote: > > > On Tue, Aug 11, 2020 at 11:44:47AM +0200, Roger Pau Monne wrote: > > > > If enabled (because ZONE_DEVICE is supported) the usage of the new > > > > functionality untangles Xen balloon and RAM hotplug from the usage of > > > > unpopulated physical memory ranges to map foreign pages, which is the > > > > correct thing to do in order to avoid mappings of foreign pages depend > > > > on memory hotplug. > > > > > > So please just select ZONE_DEVICE if this is so much better rather > > > than maintaining two variants. > > > > We still need to other variant for Arm at least, so both need to be > > maintained anyway, even if we force ZONE_DEVICE on x86. > > Well, it still really helps reproducability if you stick to one > implementation of x86. > > The alternative would be an explicit config option to opt into it, > but just getting a different implementation based on a random > kernel option is strange. Would adding something like the chunk below to the patch be OK? ---8<--- diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig index 018020b91baa..5f321a1319e6 100644 --- a/drivers/xen/Kconfig +++ b/drivers/xen/Kconfig @@ -328,7 +328,14 @@ config XEN_FRONT_PGDIR_SHBUF tristate config XEN_UNPOPULATED_ALLOC - bool - default y if ZONE_DEVICE && !ARM && !ARM64 + bool "Use unpopulated memory ranges for guest mappings" + depends on X86 + select ZONE_DEVICE + default y + help + Use unpopulated memory ranges in order to create mappings for guest + memory regions, including grants maps and foreign pages. This avoids + having to balloon out RAM regions in order to obtain physical memory + space to create such mappings. endmenu ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 0/5] Fixes and improvements for Xen pvdrm
On 8/13/20 10:05 AM, Jürgen Groß wrote: > On 13.08.20 08:32, Oleksandr Andrushchenko wrote: >> Juergen, Boris, >> >> can we please merge these via Xen Linux tree as I have collected enough >> Ack/R-b? >> >> The series has DRM patches, but those anyway are Xen related, so I think >> >> this should be fine from DRI point of view. > > Yes, fine with me. Great, thank you > > > Juergen > >> >> Thank you, >> >> Oleksandr >> >> On 8/13/20 9:21 AM, Oleksandr Andrushchenko wrote: >>> From: Oleksandr Andrushchenko >>> >>> Hello, >>> >>> This series contains an assorted set of fixes and improvements for >>> the Xen para-virtualized display driver and grant device driver which >>> I have collected over the last couple of months: >>> >>> 1. Minor fixes to grant device driver and drm/xen-front. >>> >>> 2. New format (YUYV) added to the list of the PV DRM supported formats >>> which allows the driver to be used in zero-copying use-cases when >>> a camera device is the source of the dma-bufs. >>> >>> 3. Synchronization with the latest para-virtualized protocol definition >>> in Xen [1]. >>> >>> 4. SGT offset is now propagated to the backend: while importing a dmabuf >>> it is possible that the data of the buffer is put with offset which is >>> indicated by the SGT offset. This is needed for some GPUs which have >>> non-zero offset. >>> >>> Thank you, >>> Oleksandr Andrushchenko >>> >>> [1] >>> https://urldefense.com/v3/__https://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=c27a184225eab54d20435c8cab5ad0ef384dc2c0__;!!GF_29dbcQIUBPA!iAHOdk4M167VNM1AypMGVmyKJu-iqC9e5cXyu6N595Np3iyIZDnZl0MIBX3IROJSD1GSMX_GfQ$ >>> [xenbits[.]xen[.]org] >>> >>> Changes since v1: >>> = >>> >>> 1. Removed patch which adds EDID to PV DRM as it needs more time for review: >>> "5. Version 2 of the Xen displif protocol adds XENDISPL_OP_GET_EDID >>> request which allows frontends to request EDID structure per >>> connector. This request is optional and if not supported by the >>> backend then visible area is still defined by the relevant >>> XenStore's "resolution" property. >>> If backend provides EDID with XENDISPL_OP_GET_EDID request then >>> its values must take precedence over the resolutions defined in >>> XenStore." >>> I will send this as a dedicated patch. >>> >>> 2. Added missing CC stable for the patches with fixes >>> >>> Oleksandr Andrushchenko (5): >>> xen/gntdev: Fix dmabuf import with non-zero sgt offset >>> drm/xen-front: Fix misused IS_ERR_OR_NULL checks >>> drm/xen-front: Add YUYV to supported formats >>> xen: Sync up with the canonical protocol definition in Xen >>> drm/xen-front: Pass dumb buffer data offset to the backend >>> >>> drivers/gpu/drm/xen/xen_drm_front.c | 10 +-- >>> drivers/gpu/drm/xen/xen_drm_front.h | 2 +- >>> drivers/gpu/drm/xen/xen_drm_front_conn.c | 1 + >>> drivers/gpu/drm/xen/xen_drm_front_gem.c | 11 +-- >>> drivers/gpu/drm/xen/xen_drm_front_kms.c | 2 +- >>> drivers/xen/gntdev-dmabuf.c | 8 +++ >>> include/xen/interface/io/displif.h | 91 +++- >>> 7 files changed, 111 insertions(+), 14 deletions(-) >>> >> > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 0/5] Fixes and improvements for Xen pvdrm
On 8/13/20 6:02 PM, Jürgen Groß wrote: > On 13.08.20 08:21, Oleksandr Andrushchenko wrote: >> From: Oleksandr Andrushchenko > > Series pushed to: > > xen/tip.git for-linus-5.9 > The top patch has strange title though: "Subject: [PATCH v2 5/5] drm/xen-front: Pass dumb buffer data offset to the backend" > > Juergen Thank you, Oleksandr ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 2/2] xen: add helpers to allocate unpopulated memory
Your email client seems to set 'Reply-to:' to point to everyone on the 'Cc:' field, but not yourself, which is kind of weird. I've manually fixed it on this reply by moving everyone to the 'Cc:' field and setting you on 'To:'. On Thu, Aug 13, 2020 at 11:49:46AM +0200, Daniel Vetter wrote: > On Thu, Aug 13, 2020 at 09:54:20AM +0200, Roger Pau Monné wrote: > > On Thu, Aug 13, 2020 at 08:33:37AM +0100, Christoph Hellwig wrote: > > > On Tue, Aug 11, 2020 at 11:44:47AM +0200, Roger Pau Monne wrote: > > > > If enabled (because ZONE_DEVICE is supported) the usage of the new > > > > functionality untangles Xen balloon and RAM hotplug from the usage of > > > > unpopulated physical memory ranges to map foreign pages, which is the > > > > correct thing to do in order to avoid mappings of foreign pages depend > > > > on memory hotplug. > > > > > > So please just select ZONE_DEVICE if this is so much better rather > > > than maintaining two variants. > > > > We still need to other variant for Arm at least, so both need to be > > maintained anyway, even if we force ZONE_DEVICE on x86. > > Why does arm not have ZONE_DEVICE? It's not that Arm doesn't have ZONE_DEVICE, it's just that the approach used here won't work correctly on an Arm Xen dom0 as-is. This is due to the usage of an identity second stage translation in order to workaround the lack of an IOMMU in some Arm boards. It can be made to work on Arm, but will likely require someone from the Arm side doing that. Roger. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 18/20] drm/xen: Introduce GEM object functions
Hi,
On 8/13/20 11:36 AM, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in xen. The only exception is gem_prime_mmap,
> which is non-trivial to convert.
>
> Signed-off-by: Thomas Zimmermann
> ---
> drivers/gpu/drm/xen/xen_drm_front.c | 12 +---
> drivers/gpu/drm/xen/xen_drm_front.h | 2 ++
> drivers/gpu/drm/xen/xen_drm_front_gem.c | 15 +++
> 3 files changed, 18 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/xen/xen_drm_front.c
> b/drivers/gpu/drm/xen/xen_drm_front.c
> index 3e660fb111b3..bd9af1875af1 100644
> --- a/drivers/gpu/drm/xen/xen_drm_front.c
> +++ b/drivers/gpu/drm/xen/xen_drm_front.c
> @@ -433,7 +433,7 @@ static int xen_drm_drv_dumb_create(struct drm_file *filp,
> return ret;
> }
>
> -static void xen_drm_drv_free_object_unlocked(struct drm_gem_object *obj)
> +void xen_drm_drv_free_object_unlocked(struct drm_gem_object *obj)
Can we please have naming consistent and name it as
xen_drm_front_drv_free_object_unlocked or any other name if this seems to be
too long,
but starting with xen_drm_front_ as the rest of exported functions?
With this,
Acked-by: Oleksandr Andrushchenko
Thank you,
Oleksandr
> {
> struct xen_drm_front_drm_info *drm_info = obj->dev->dev_private;
> int idx;
> @@ -481,22 +481,12 @@ static const struct file_operations xen_drm_dev_fops = {
> .mmap = xen_drm_front_gem_mmap,
> };
>
> -static const struct vm_operations_struct xen_drm_drv_vm_ops = {
> - .open = drm_gem_vm_open,
> - .close = drm_gem_vm_close,
> -};
> -
> static struct drm_driver xen_drm_driver = {
> .driver_features = DRIVER_GEM | DRIVER_MODESET |
> DRIVER_ATOMIC,
> .release = xen_drm_drv_release,
> - .gem_vm_ops= _drm_drv_vm_ops,
> - .gem_free_object_unlocked = xen_drm_drv_free_object_unlocked,
> .prime_handle_to_fd= drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle= drm_gem_prime_fd_to_handle,
> .gem_prime_import_sg_table = xen_drm_front_gem_import_sg_table,
> - .gem_prime_get_sg_table= xen_drm_front_gem_get_sg_table,
> - .gem_prime_vmap= xen_drm_front_gem_prime_vmap,
> - .gem_prime_vunmap = xen_drm_front_gem_prime_vunmap,
> .gem_prime_mmap= xen_drm_front_gem_prime_mmap,
> .dumb_create = xen_drm_drv_dumb_create,
> .fops = _drm_dev_fops,
> diff --git a/drivers/gpu/drm/xen/xen_drm_front.h
> b/drivers/gpu/drm/xen/xen_drm_front.h
> index f92c258350ca..93e60c1db550 100644
> --- a/drivers/gpu/drm/xen/xen_drm_front.h
> +++ b/drivers/gpu/drm/xen/xen_drm_front.h
> @@ -160,4 +160,6 @@ int xen_drm_front_page_flip(struct xen_drm_front_info
> *front_info,
> void xen_drm_front_on_frame_done(struct xen_drm_front_info *front_info,
>int conn_idx, u64 fb_cookie);
>
> +void xen_drm_drv_free_object_unlocked(struct drm_gem_object *obj);
> +
> #endif /* __XEN_DRM_FRONT_H_ */
> diff --git a/drivers/gpu/drm/xen/xen_drm_front_gem.c
> b/drivers/gpu/drm/xen/xen_drm_front_gem.c
> index f0b85e094111..7b315c08bcfc 100644
> --- a/drivers/gpu/drm/xen/xen_drm_front_gem.c
> +++ b/drivers/gpu/drm/xen/xen_drm_front_gem.c
> @@ -56,6 +56,19 @@ static void gem_free_pages_array(struct xen_gem_object
> *xen_obj)
> xen_obj->pages = NULL;
> }
>
> +static const struct vm_operations_struct xen_drm_drv_vm_ops = {
> + .open = drm_gem_vm_open,
> + .close = drm_gem_vm_close,
> +};
> +
> +static const struct drm_gem_object_funcs xen_drm_front_gem_object_funcs = {
> + .free = xen_drm_drv_free_object_unlocked,
> + .get_sg_table = xen_drm_front_gem_get_sg_table,
> + .vmap = xen_drm_front_gem_prime_vmap,
> + .vunmap = xen_drm_front_gem_prime_vunmap,
> + .vm_ops = _drm_drv_vm_ops,
> +};
> +
> static struct xen_gem_object *gem_create_obj(struct drm_device *dev,
>size_t size)
> {
> @@ -66,6 +79,8 @@ static struct xen_gem_object *gem_create_obj(struct
> drm_device *dev,
> if (!xen_obj)
> return ERR_PTR(-ENOMEM);
>
> + xen_obj->base.funcs = _drm_front_gem_object_funcs;
> +
> ret = drm_gem_object_init(dev, _obj->base, size);
> if (ret < 0) {
> kfree(xen_obj);
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Re: [PATCH v2 0/5] Fixes and improvements for Xen pvdrm
On 8/13/20 6:13 PM, Jürgen Groß wrote: > On 13.08.20 17:10, Oleksandr Andrushchenko wrote: >> >> On 8/13/20 6:02 PM, Jürgen Groß wrote: >>> On 13.08.20 08:21, Oleksandr Andrushchenko wrote: From: Oleksandr Andrushchenko >>> >>> Series pushed to: >>> >>> xen/tip.git for-linus-5.9 >>> >> The top patch has strange title though: >> >> "Subject: [PATCH v2 5/5] drm/xen-front: Pass dumb buffer data offset to the >> backend" > > Oh, indeed. I had to repair it manually as it seems some mail system > (probably on my end) mangled it a little bit. > > Will repair it. > Now everything is great, Thank you! > > Juergen ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [virtio-dev] Re: [PATCH v5 0/3] Support virtio cross-device resources
On Tue, Jun 23, 2020 at 10:31:28AM +0900, David Stevens wrote: > Unless there are any remaining objections to these patches, what are > the next steps towards getting these merged? Sorry, I'm not familiar > with the workflow for contributing patches to Linux. Sorry, just have been busy and not paying as much attention to drm patches as usual. Playing catch-up now. Queued for drm-misc-next, unless something goes wrong in my testing the patches should land in linux-next soon and be merged upstream in the next merge window. take care, Gerd ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
