Re: [PATCH] drm/scheduler: set entity to NULL in drm_sched_entity_pop_job()
Am 31.03.23 um 02:06 schrieb Danilo Krummrich: It already happend a few times that patches slipped through which implemented access to an entity through a job that was already removed from the entities queue. Since jobs and entities might have different lifecycles, this can potentially cause UAF bugs. In order to make it obvious that a jobs entity pointer shouldn't be accessed after drm_sched_entity_pop_job() was called successfully, set the jobs entity pointer to NULL once the job is removed from the entity queue. Moreover, debugging a potential NULL pointer dereference is way easier than potentially corrupted memory through a UAF. Signed-off-by: Danilo Krummrich In general "YES PLEASE!", but I fear that this will break amdgpus reset sequence. On the other hand when amdgpu still relies on that pointer it's clearly a bug (which I pointed out tons of times before). Luben any opinion on that? Could you drive cleaning that up as well? Thanks, Christian. --- I'm aware that drivers could already use job->entity in arbitrary places, since they in control of when the entity is actually freed. A quick grep didn't give me any results where this would actually be the case, however maybe I also just didn't catch it. If, therefore, we don't want to set job->entity to NULL I think we should at least add a comment somewhere. --- drivers/gpu/drm/scheduler/sched_entity.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 15d04a0ec623..a9c6118e534b 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -448,6 +448,12 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) drm_sched_rq_update_fifo(entity, next->submit_ts); } + /* Jobs and entities might have different lifecycles. Since we're +* removing the job from the entities queue, set the jobs entity pointer +* to NULL to prevent any future access of the entity through this job. +*/ + sched_job->entity = NULL; + return sched_job; }
Re: [PATCH] drm/sun4i: uncouple DSI dotclock divider from TCON0_DCLK_REG
Hello Frank, On Thu Mar 30, 2023 at 6:45 AM CEST, Frank Oltmanns wrote: > Roman, will you please submit a V2 of the patch I submitted then? Or do > you want me to do it? Yes, I'm already on it, only missing a cover letter. Roman
[Bug 217278] ast 0000:03:00.0: PM: **** DPM device timeout **** during S4 resuming
https://bugzilla.kernel.org/show_bug.cgi?id=217278 The Linux kernel's regression tracker (Thorsten Leemhuis) (regressi...@leemhuis.info) changed: What|Removed |Added CC||regressi...@leemhuis.info --- Comment #1 from The Linux kernel's regression tracker (Thorsten Leemhuis) (regressi...@leemhuis.info) --- Did this work fine or earlier kernels? Which one? -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
Re: [Freedreno] [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods
On 3/30/2023 7:47 PM, Dmitry Baryshkov wrote:
On 31/03/2023 04:33, Abhinav Kumar wrote:
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang
wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 74d38f90398a..7419fe58a941 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -31,6 +31,7 @@
#include "msm_kms.h"
#include "msm_gem.h"
#include "phy/dsi_phy.h"
+#include "disp/msm_dsc_helper.h"
#define DSI_RESET_TOGGLE_DELAY_MS 20
@@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
{
struct drm_dsc_config *dsc = msm_host->dsc;
u32 reg, reg_ctrl, reg_ctrl2;
- u32 slice_per_intf, total_bytes_per_intf;
+ u32 slice_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
/* first calculate dsc parameters and then program
* compress mode registers
*/
- slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
+ slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay);
This looks good
/*
* If slice_count is greater than slice_per_intf
@@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
if (dsc->slice_count > slice_per_intf)
dsc->slice_count = 1;
- total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc,
hdisplay,
+ dsi_get_bpp(msm_host->format));
- eol_byte_num = total_bytes_per_intf % 3;
- pkt_per_line = slice_per_intf / dsc->slice_count;
+ pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT;
And for these values the result is definitely changed. Separate
patch
& description please. Just in case, "values per downstream
kernel" is
not a proper description for such changes.
Hi Dmitry,
Sure, I can put this into a separate patch.
The reason this was changed from slice_count to SLICE_PER_PKT was
because slice count and slice per packet aren't always equivalent.
There can be cases where panel configures DSC to have multiple soft
slices per interface, but the panel only specifies 1 slice per
packet.
Please put this nice description into the commit message. It is
exactly
what I was looking for!
BTW: Do you expect to change MSM_DSC_SLICE_PER_PKT later or it will
stay
at "1"? If so, it might be easier to drop it and instead add a
comment.
MSM_DSC_SLICE_PER_PKT is the default value for panels that don't
specify
a slice_per_pkt value. (Now that I think about it, might be better to
call it MSM_DSC_DEFAULT_SLICE_PER_PKT instead...)
Note, there is no slice_per_pkt in drm_dsc_config, so we must come up
with another way to pass this data from the panel or to deduce the
value in our driver.
I don't expect it to change in the future, but it's a little more
readable than just dividing by 1 IMO. If you prefer dropping the macro
and adding a comment, I'm also okay with that.
There is no need to divide by 1, the value doesn't change. So I'd
probably prefer something like:
/* Default to 1 slice per packet */
if (panel_slice_per_pkt)
pkt_per_line = slice_per_intf / panel_slice_per_pkt;
else
pkt_per_line = slice_per_intf;
Or:
/* Default to 1 slice per packet */
slice_per_pkt = 1;
if (panel_slice_per_pkt)
slice_per_pkt = panel_slice_per_pkt;
pkt_per_line = slice_per_intf / slice_per_pkt;
BTW: could you possibly change 'intf' to 'line' to v2? It seems there
is a mixture of them through the code. If there is a difference
between intf and line which is not yet posted, it's fine to keep the
current code. WDYT?
No, I dont agree with the change from intf to line.
In case of dual DSI, intf is not equal to line.
2 intfs = 1 line
Hence that distinction is necessary.
Ack, this is what I was looking for!
so intf = line / num_intf?
Yes by definition, "line" is one horizontal line of pixels for the panel.
So intf = h_active of panel / num_intf
But here "line" is one line of pixels pulled by the interface.
So for dual dsi cases its = h_active of panel / 2
Maybe I should explain the reason for my question:
msm_dsc_get_pclk_per_line() uses intf_width, calculates pclk_per_line
(not per intf). msm_dsc_get_dce_bytes_per_line() does the same thing
In this patch we take slice_per_intf, divide it with slice_per_pkt and
get pkt_per_line (rather than pkt_per_intf).
This is what prompted my question regarding intf vs line.
Valid question. The terminology gets a bit confusing because.
pclk_per_line can be
Re: [PATCH v2 9/9] drm/i915: Use kmap_local_page() in gem/i915_gem_execbuffer.c
Zhao Liu wrote:
> From: Zhao Liu
>
> The use of kmap_atomic() is being deprecated in favor of
> kmap_local_page()[1], and this patch converts the calls from
> kmap_atomic() to kmap_local_page().
>
> The main difference between atomic and local mappings is that local
> mappings doesn't disable page faults or preemption (the preemption is
> disabled for !PREEMPT_RT case, otherwise it only disables migration).
>
> With kmap_local_page(), we can avoid the often unwanted side effect of
> unnecessary page faults and preemption disables.
>
> In i915_gem_execbuffer.c, eb->reloc_cache.vaddr is mapped by
> kmap_atomic() in eb_relocate_entry(), and is unmapped by
> kunmap_atomic() in reloc_cache_reset().
First off thanks for the series and sticking with this. That said this
patch kind of threw me for a loop because tracing the map/unmap calls did
not make sense to me. See below.
>
> And this mapping/unmapping occurs in two places: one is in
> eb_relocate_vma(), and another is in eb_relocate_vma_slow().
>
> The function eb_relocate_vma() or eb_relocate_vma_slow() doesn't
> need to disable pagefaults and preemption during the above mapping/
> unmapping.
>
> So it can simply use kmap_local_page() / kunmap_local() that can
> instead do the mapping / unmapping regardless of the context.
>
> Convert the calls of kmap_atomic() / kunmap_atomic() to
> kmap_local_page() / kunmap_local().
>
> [1]: https://lore.kernel.org/all/20220813220034.806698-1-ira.we...@intel.com
>
> v2: No code change since v1. Added description of the motivation of
> using kmap_local_page() and "Suggested-by" tag of Fabio.
>
> Suggested-by: Ira Weiny
> Suggested-by: Fabio M. De Francesco
> Signed-off-by: Zhao Liu
> ---
> Suggested by credits:
> Ira: Referred to his task document, review comments.
> Fabio: Referred to his boiler plate commit message and his description
> about why kmap_local_page() should be preferred.
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 9dce2957b4e5..805565edd148 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1151,7 +1151,7 @@ static void reloc_cache_unmap(struct reloc_cache *cache)
>
> vaddr = unmask_page(cache->vaddr);
> if (cache->vaddr & KMAP)
> - kunmap_atomic(vaddr);
> + kunmap_local(vaddr);
In the cover letter you don't mention this unmap path. Rather you mention
only reloc_cache_reset().
After digging into this and considering these are kmap_atomic() calls I
_think_ what you have is ok. But I think I'd like to see the call paths
documented a bit more clearly. Or perhaps cleaned up a lot.
For example I see the following call possibility from a user ioctl. In
this trace I see 2 examples where something is unmapped first. I don't
understand why that is required? I would assume reloc_cache_unmap() and
reloc_kmap() are helpers called from somewhere else requiring a remapping
of the cache but I don't see it.
i915_gem_execbuffer2_ioctl()
eb_relocate_parse()
eb_relocate_parse_slow()
eb_relocate_vma_slow()
eb_relocate_entry()
reloc_cache_unmap()
kunmap_atomic() <=== HERE!
reloc_cache_remap()
kmap_atomic()
relocate_entry()
reloc_vaddr()
reloc_kmap()
kunmap_atomic() <== HERE!
kmap_atomic()
reloc_cache_reset()
kunmap_atomic()
Could these mappings be cleaned up a lot more? Perhaps by removing some
of the helper functions which AFAICT are left over from older versions of
the code?
Also as an aside I think it is really bad that eb_relocate_entry() returns
negative errors in a u64. Better to get the types right IMO.
Thanks for the series!
Ira
> else
> io_mapping_unmap_atomic((void __iomem *)vaddr);
> }
> @@ -1167,7 +1167,7 @@ static void reloc_cache_remap(struct reloc_cache *cache,
> if (cache->vaddr & KMAP) {
> struct page *page = i915_gem_object_get_page(obj, cache->page);
>
> - vaddr = kmap_atomic(page);
> + vaddr = kmap_local_page(page);
> cache->vaddr = unmask_flags(cache->vaddr) |
> (unsigned long)vaddr;
> } else {
> @@ -1197,7 +1197,7 @@ static void reloc_cache_reset(struct reloc_cache
> *cache, struct i915_execbuffer
> if (cache->vaddr & CLFLUSH_AFTER)
> mb();
>
> - kunmap_atomic(vaddr);
> + kunmap_local(vaddr);
> i915_gem_object_finish_access(obj);
> } else {
> struct i915_ggtt *ggtt =
Re: [PATCH][next] drm/i915/uapi: Replace fake flex-array with flexible-array member
Hi all,
Friendly ping: who can take this, please?
Thanks
--
Gustavo
On 3/17/23 12:18, Gustavo A. R. Silva wrote:
Zero-length arrays as fake flexible arrays are deprecated and we are
moving towards adopting C99 flexible-array members instead.
Address the following warning found with GCC-13 and
-fstrict-flex-arrays=3 enabled:
drivers/gpu/drm/i915/gem/i915_gem_context.c: In function
‘set_proto_ctx_engines.isra’:
drivers/gpu/drm/i915/gem/i915_gem_context.c:769:41: warning: array subscript n
is outside array bounds of ‘struct i915_engine_class_instance[0]’
[-Warray-bounds=]
769 | if (copy_from_user(, >engines[n],
sizeof(ci))) {
| ^
./include/uapi/drm/i915_drm.h:2494:43: note: while referencing ‘engines’
2494 | struct i915_engine_class_instance engines[0];
This helps with the ongoing efforts to tighten the FORTIFY_SOURCE
routines on memcpy() and help us make progress towards globally
enabling -fstrict-flex-arrays=3 [1].
Link: https://github.com/KSPP/linux/issues/21
Link: https://github.com/KSPP/linux/issues/271
Link: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/602902.html [1]
Signed-off-by: Gustavo A. R. Silva
---
include/uapi/drm/i915_drm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 8df261c5ab9b..5e458d6f2895 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2491,7 +2491,7 @@ struct i915_context_param_engines {
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see
i915_context_engines_load_balance */
#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see
i915_context_engines_parallel_submit */
- struct i915_engine_class_instance engines[0];
+ struct i915_engine_class_instance engines[];
} __attribute__((packed));
#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
Re: [PATCH] drm/fbdev-generic: optimize out a redundant assignment clause
On 2023/3/30 15:26, Thomas Zimmermann wrote:
Hi
Am 30.03.23 um 09:17 schrieb Sui Jingfeng:
Hi,
On 2023/3/30 14:57, Thomas Zimmermann wrote:
Hi
Am 30.03.23 um 06:17 schrieb Lucas De Marchi:
On Wed, Mar 29, 2023 at 11:04:17AM +0200, Thomas Zimmermann wrote:
(cc'ing Lucas)
Hi
Am 25.03.23 um 08:46 schrieb Sui Jingfeng:
The assignment already done in drm_client_buffer_vmap(),
just trival clean, no functional change.
Signed-off-by: Sui Jingfeng <15330273...@189.cn>
---
drivers/gpu/drm/drm_fbdev_generic.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_fbdev_generic.c
b/drivers/gpu/drm/drm_fbdev_generic.c
index 4d6325e91565..1da48e71c7f1 100644
--- a/drivers/gpu/drm/drm_fbdev_generic.c
+++ b/drivers/gpu/drm/drm_fbdev_generic.c
@@ -282,7 +282,7 @@ static int drm_fbdev_damage_blit(struct
drm_fb_helper *fb_helper,
struct drm_clip_rect *clip)
{
struct drm_client_buffer *buffer = fb_helper->buffer;
- struct iosys_map map, dst;
+ struct iosys_map map;
int ret;
/*
@@ -302,8 +302,7 @@ static int drm_fbdev_damage_blit(struct
drm_fb_helper *fb_helper,
if (ret)
goto out;
- dst = map;
- drm_fbdev_damage_blit_real(fb_helper, clip, );
+ drm_fbdev_damage_blit_real(fb_helper, clip, );
I see what you're doing and it's probably correct in this case.
But there's a larger issue with this iosys interfaces. Sometimes
the address has to be modified (see calls of iosys_map_incr()).
That can prevent incorrect uses of the mapping in other places,
especially in unmap code.
using a initializer for the cases it's needed IMO would make these
kind
of problems go away, because then the intent is explicit
I think it would make sense to consider a separate structure for
the I/O location. The buffer as a whole would still be represented
by struct iosys_map. And that new structure, let's call it struct
iosys_ptr, would point to an actual location within the buffer's
sounds fine to me, but I'd have to take a deeper look later (or when
someone writes the patch). It seems we'd replicate almost the entire
API to just accomodate the 2 structs. And the different types will
lead
to confusion when one or the other should be used
I think we can split the current interface onto two categories:
mapping and I/O. The former would use iosys_map and the latter would
use iosys_ptr. And we'd need a helper that turns gets a ptr for a
given map.
If I find the tine, I'll probably type up a patch.
Here i fix a typo, 'tine' -> 'time'
As far as i can see, they are two major type of memory in the system.
System memory or VRAM, for the gpu with dedicate video ram, VRAM is
belong to the IO memory category.
But there are system choose carveout part of system ram as video
ram(i915?, for example).
the name iosys_map and iosys_ptr have no difference at the first
sight, tell me which one is for mapping system ram
and which one is for mapping vram?
As you say correctly, graphics buffers and be in various locations.
They can even move between I/O and system memory. The idea behind
iosys_map ("I/O and/or system mapping") is that it's a single
interface that can handle both.
They are all pointers in its very nature.
The hard part to make ensure that iosys_map can not be replaced with
iosys_ptr,
They should not overlap in functional, I meant.
Best regards
Thomas
Best regards
Thomas
thanks
Lucas De Marchi
memory range. A few locations and helpers would need changes, but
there are not so many callers that it's an issue. This would also
allow for a few debugging tests that ensure that iosys_ptr always
operates within the bounds of an iosys_map.
I've long considered this idea, but there was no pressure to work
on it. Maybe now.
Best regards
Thomas
drm_client_buffer_vunmap(buffer);
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Ivo Totev
Re: [PATCH v2 8/9] drm/i915: Use kmap_local_page() in i915_cmd_parser.c
Zhao Liu wrote: > From: Zhao Liu > > The use of kmap_atomic() is being deprecated in favor of > kmap_local_page()[1], and this patch converts the call from > kmap_atomic() to kmap_local_page(). > > The main difference between atomic and local mappings is that local > mappings doesn't disable page faults or preemption (the preemption is > disabled for !PREEMPT_RT case, otherwise it only disables migration). > > With kmap_local_page(), we can avoid the often unwanted side effect of > unnecessary page faults and preemption disables. > > There're 2 reasons why function copy_batch() doesn't need to disable > pagefaults and preemption for mapping: > > 1. The flush operation is safe. In i915_cmd_parser.c, copy_batch() calls > drm_clflush_virt_range() to use CLFLUSHOPT or WBINVD to flush. > Since CLFLUSHOPT is global on x86 and WBINVD is called on each cpu > in drm_clflush_virt_range(), the flush operation is global. > > 2. Any context switch caused by preemption or page faults (page fault > may cause sleep) doesn't affect the validity of local mapping. > > Therefore, copy_batch() is a function where the use of > kmap_local_page() in place of kmap_atomic() is correctly suited. > > Convert the calls of kmap_atomic() / kunmap_atomic() to > kmap_local_page() / kunmap_local(). > > [1]: https://lore.kernel.org/all/20220813220034.806698-1-ira.we...@intel.com > > v2: > * Dropped hot plug related description since it has nothing to do with > kmap_local_page(). > * No code change since v1, and added description of the motivation of > using kmap_local_page(). > > Suggested-by: Dave Hansen > Suggested-by: Ira Weiny Reviewed-by: Ira Weiny
Re: [PATCH v2 6/9] drm/i915: Use kmap_local_page() in gem/selftests/i915_gem_context.c
Zhao Liu wrote:
> From: Zhao Liu
>
> The use of kmap_atomic() is being deprecated in favor of
> kmap_local_page()[1], and this patch converts the call from
> kmap_atomic() to kmap_local_page().
>
> The main difference between atomic and local mappings is that local
> mappings doesn't disable page faults or preemption.
>
> With kmap_local_page(), we can avoid the often unwanted side effect of
> unnecessary page faults or preemption disables.
>
> In drm/i915/gem/selftests/i915_gem_context.c, functions cpu_fill() and
> cpu_check() mainly uses mapping to flush cache and check/assign the
> value.
>
> There're 2 reasons why cpu_fill() and cpu_check() don't need to disable
> pagefaults and preemption for mapping:
>
> 1. The flush operation is safe. cpu_fill() and cpu_check() call
> drm_clflush_virt_range() to use CLFLUSHOPT or WBINVD to flush. Since
> CLFLUSHOPT is global on x86 and WBINVD is called on each cpu in
> drm_clflush_virt_range(), the flush operation is global.
>
> 2. Any context switch caused by preemption or page faults (page fault
> may cause sleep) doesn't affect the validity of local mapping.
>
> Therefore, cpu_fill() and cpu_check() are functions where the use of
> kmap_local_page() in place of kmap_atomic() is correctly suited.
>
> Convert the calls of kmap_atomic() / kunmap_atomic() to
> kmap_local_page() / kunmap_local().
>
> [1]: https://lore.kernel.org/all/20220813220034.806698-1-ira.we...@intel.com
>
> v2:
> * Dropped hot plug related description since it has nothing to do with
> kmap_local_page().
> * No code change since v1, and added description of the motivation of
> using kmap_local_page().
>
> Suggested-by: Dave Hansen
> Suggested-by: Ira Weiny
First off I think this is fine.
But as I looked at this final selftests patch I began to wonder how the
memory being mapped here and in the previous selftests patches are
allocated. Does highmem need to be considered at all? Unfortunately, I
could not determine where the memory in the SG list of this test gem
object was allocated.
AFAICS cpu_fill() is only called in create_test_object(). Digging into
huge_gem_object() did not reveal where these pages were allocated from.
I wonder if these kmap_local_page() calls could be removed entirely based
on knowing that the pages were allocated from low mem? Removing yet
another user of highmem altogether would be best if possible.
Do you know how these test objects are created? Do the pages come from
user space somehow?
Regardless this is still a step in the right direction so:
Reviewed-by: Ira Weiny
> Suggested-by: Fabio M. De Francesco
> Signed-off-by: Zhao Liu
> ---
> Suggested by credits:
> Dave: Referred to his explanation about cache flush.
> Ira: Referred to his task document, review comments and explanation
>about cache flush.
> Fabio: Referred to his boiler plate commit message and his description
> about why kmap_local_page() should be preferred.
> ---
> drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index a81fa6a20f5a..dcbc0b8e3323 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -481,12 +481,12 @@ static int cpu_fill(struct drm_i915_gem_object *obj,
> u32 value)
> for (n = 0; n < real_page_count(obj); n++) {
> u32 *map;
>
> - map = kmap_atomic(i915_gem_object_get_page(obj, n));
> + map = kmap_local_page(i915_gem_object_get_page(obj, n));
> for (m = 0; m < DW_PER_PAGE; m++)
> map[m] = value;
> if (!has_llc)
> drm_clflush_virt_range(map, PAGE_SIZE);
> - kunmap_atomic(map);
> + kunmap_local(map);
> }
>
> i915_gem_object_finish_access(obj);
> @@ -512,7 +512,7 @@ static noinline int cpu_check(struct drm_i915_gem_object
> *obj,
> for (n = 0; n < real_page_count(obj); n++) {
> u32 *map, m;
>
> - map = kmap_atomic(i915_gem_object_get_page(obj, n));
> + map = kmap_local_page(i915_gem_object_get_page(obj, n));
> if (needs_flush & CLFLUSH_BEFORE)
> drm_clflush_virt_range(map, PAGE_SIZE);
>
> @@ -538,7 +538,7 @@ static noinline int cpu_check(struct drm_i915_gem_object
> *obj,
> }
>
> out_unmap:
> - kunmap_atomic(map);
> + kunmap_local(map);
> if (err)
> break;
> }
> --
> 2.34.1
>
Re: [PATCH v2 5/9] drm/i915: Use kmap_local_page() in gem/selftests/i915_gem_coherency.c
Zhao Liu wrote: > From: Zhao Liu > > The use of kmap_atomic() is being deprecated in favor of > kmap_local_page()[1], and this patch converts the call from > kmap_atomic() to kmap_local_page(). > > The main difference between atomic and local mappings is that local > mappings doesn't disable page faults or preemption (the preemption is > disabled for !PREEMPT_RT case, otherwise it only disables migration).. > > With kmap_local_page(), we can avoid the often unwanted side effect of > unnecessary page faults or preemption disables. > > In drm/i915/gem/selftests/i915_gem_coherency.c, functions cpu_set() > and cpu_get() mainly uses mapping to flush cache and assign the value. > There're 2 reasons why cpu_set() and cpu_get() don't need to disable > pagefaults and preemption for mapping: > > 1. The flush operation is safe. cpu_set() and cpu_get() call > drm_clflush_virt_range() to use CLFLUSHOPT or WBINVD to flush. Since > CLFLUSHOPT is global on x86 and WBINVD is called on each cpu in > drm_clflush_virt_range(), the flush operation is global. > > 2. Any context switch caused by preemption or page faults (page fault > may cause sleep) doesn't affect the validity of local mapping. > > Therefore, cpu_set() and cpu_get() are functions where the use of > kmap_local_page() in place of kmap_atomic() is correctly suited. > > Convert the calls of kmap_atomic() / kunmap_atomic() to > kmap_local_page() / kunmap_local(). > > [1]: https://lore.kernel.org/all/20220813220034.806698-1-ira.we...@intel.com > > v2: > * Dropped hot plug related description since it has nothing to do with > kmap_local_page(). > * No code change since v1, and added description of the motivation of > using kmap_local_page(). > > Suggested-by: Dave Hansen > Suggested-by: Ira Weiny Reviewed-by: Ira Weiny
Re: [PATCH v2 4/9] drm/i915: Use kmap_local_page() in gem/selftests/huge_pages.c
Zhao Liu wrote: > From: Zhao Liu > > The use of kmap_atomic() is being deprecated in favor of > kmap_local_page()[1], and this patch converts the call from > kmap_atomic() to kmap_local_page(). > > The main difference between atomic and local mappings is that local > mappings doesn't disable page faults or preemption (the preemption is > disabled for !PREEMPT_RT case, otherwise it only disables migration). > > With kmap_local_page(), we can avoid the often unwanted side effect of > unnecessary page faults or preemption disables. > > In drm/i915/gem/selftests/huge_pages.c, function __cpu_check_shmem() > mainly uses mapping to flush cache and check the value. There're > 2 reasons why __cpu_check_shmem() doesn't need to disable pagefaults > and preemption for mapping: > > 1. The flush operation is safe. Function __cpu_check_shmem() calls > drm_clflush_virt_range() to use CLFLUSHOPT or WBINVD to flush. Since > CLFLUSHOPT is global on x86 and WBINVD is called on each cpu in > drm_clflush_virt_range(), the flush operation is global. > > 2. Any context switch caused by preemption or page faults (page fault > may cause sleep) doesn't affect the validity of local mapping. > > Therefore, __cpu_check_shmem() is a function where the use of > kmap_local_page() in place of kmap_atomic() is correctly suited. > > Convert the calls of kmap_atomic() / kunmap_atomic() to > kmap_local_page() / kunmap_local(). > > [1]: https://lore.kernel.org/all/20220813220034.806698-1-ira.we...@intel.com > > v2: > * Dropped hot plug related description since it has nothing to do with > kmap_local_page(). > * No code change since v1, and added description of the motivation of > using kmap_local_page(). > > Suggested-by: Dave Hansen > Suggested-by: Ira Weiny Reviewed-by: Ira Weiny
[PATCH] drm/bridge: ps8640: Use constant sleep time for polling hpd
The default hpd_wait_us in panel_edp.c is 2 seconds. This makes the sleep time in the polling of _ps8640_wait_hpd_asserted become 200ms. Change it to a constant 20ms to speed up the function. Signed-off-by: Pin-yen Lin --- drivers/gpu/drm/bridge/parade-ps8640.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index b823e55650b1..c3eb45179405 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -184,7 +184,7 @@ static int _ps8640_wait_hpd_asserted(struct ps8640 *ps_bridge, unsigned long wai * actually connected to GPIO9). */ ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, - status & PS_GPIO9, wait_us / 10, wait_us); + status & PS_GPIO9, 2, wait_us); /* * The first time we see HPD go high after a reset we delay an extra -- 2.40.0.348.gf938b09366-goog
Re: [Freedreno] [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods
On 31/03/2023 04:33, Abhinav Kumar wrote:
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang
wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 74d38f90398a..7419fe58a941 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -31,6 +31,7 @@
#include "msm_kms.h"
#include "msm_gem.h"
#include "phy/dsi_phy.h"
+#include "disp/msm_dsc_helper.h"
#define DSI_RESET_TOGGLE_DELAY_MS 20
@@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
{
struct drm_dsc_config *dsc = msm_host->dsc;
u32 reg, reg_ctrl, reg_ctrl2;
- u32 slice_per_intf, total_bytes_per_intf;
+ u32 slice_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
/* first calculate dsc parameters and then program
* compress mode registers
*/
- slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
+ slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay);
This looks good
/*
* If slice_count is greater than slice_per_intf
@@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
if (dsc->slice_count > slice_per_intf)
dsc->slice_count = 1;
- total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc,
hdisplay,
+ dsi_get_bpp(msm_host->format));
- eol_byte_num = total_bytes_per_intf % 3;
- pkt_per_line = slice_per_intf / dsc->slice_count;
+ pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT;
And for these values the result is definitely changed. Separate patch
& description please. Just in case, "values per downstream kernel" is
not a proper description for such changes.
Hi Dmitry,
Sure, I can put this into a separate patch.
The reason this was changed from slice_count to SLICE_PER_PKT was
because slice count and slice per packet aren't always equivalent.
There can be cases where panel configures DSC to have multiple soft
slices per interface, but the panel only specifies 1 slice per packet.
Please put this nice description into the commit message. It is exactly
what I was looking for!
BTW: Do you expect to change MSM_DSC_SLICE_PER_PKT later or it will
stay
at "1"? If so, it might be easier to drop it and instead add a comment.
MSM_DSC_SLICE_PER_PKT is the default value for panels that don't specify
a slice_per_pkt value. (Now that I think about it, might be better to
call it MSM_DSC_DEFAULT_SLICE_PER_PKT instead...)
Note, there is no slice_per_pkt in drm_dsc_config, so we must come up
with another way to pass this data from the panel or to deduce the
value in our driver.
I don't expect it to change in the future, but it's a little more
readable than just dividing by 1 IMO. If you prefer dropping the macro
and adding a comment, I'm also okay with that.
There is no need to divide by 1, the value doesn't change. So I'd
probably prefer something like:
/* Default to 1 slice per packet */
if (panel_slice_per_pkt)
pkt_per_line = slice_per_intf / panel_slice_per_pkt;
else
pkt_per_line = slice_per_intf;
Or:
/* Default to 1 slice per packet */
slice_per_pkt = 1;
if (panel_slice_per_pkt)
slice_per_pkt = panel_slice_per_pkt;
pkt_per_line = slice_per_intf / slice_per_pkt;
BTW: could you possibly change 'intf' to 'line' to v2? It seems there
is a mixture of them through the code. If there is a difference
between intf and line which is not yet posted, it's fine to keep the
current code. WDYT?
No, I dont agree with the change from intf to line.
In case of dual DSI, intf is not equal to line.
2 intfs = 1 line
Hence that distinction is necessary.
Ack, this is what I was looking for!
so intf = line / num_intf?
Maybe I should explain the reason for my question:
msm_dsc_get_pclk_per_line() uses intf_width, calculates pclk_per_line
(not per intf). msm_dsc_get_dce_bytes_per_line() does the same thing
In this patch we take slice_per_intf, divide it with slice_per_pkt and
get pkt_per_line (rather than pkt_per_intf).
This is what prompted my question regarding intf vs line.
Thanks,
Jessica Zhang
Regarding eol_byte_num, probably the best explanation would be that is
is a size of a padding rather than a size of a trailer bytes in a line
(and thus original calculation was incorrect).
if (is_cmd_mode) /* packet data type */
reg =
DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
@@ -911,6
Re: [PATCH v14 03/10] drm/display: Add Type-C switch helpers
Hi Dmitry,
Thanks for the review.
On Thu, Mar 23, 2023 at 7:39 AM Dmitry Baryshkov
wrote:
>
> On Wed, 22 Mar 2023 at 12:47, Pin-yen Lin wrote:
> >
> > Add helpers to register and unregister Type-C "switches" for bridges
> > capable of switching their output between two downstream devices.
> >
> > The helper registers USB Type-C mode switches when the "mode-switch"
> > and the "reg" properties are available in Device Tree.
> >
> > Signed-off-by: Pin-yen Lin
> >
> > ---
> >
> > Changes in v14:
> > - Introduce a new Kconfig becuase it didn't build when CONFIG_TYPEC=m
> > - Add comments about devm_* usage
> > - Fix style issues
> >
> > Changes in v13:
> > - Add typec_mode_switch_node_count helper
> > - Fix style issues
> >
> > Changes in v12:
> > - Add fwnode_for_each_typec_mode_switch macro
> > - Remove a duplicated dmesg in the helper
> > - Used IS_REACHABLE instead to guard the function signatures
> >
> > Changes in v11:
> > - Use fwnode helpers instead of DT
> > - Moved the helpers to a new file
> > - Use "reg" instead of "data-lanes" to determine the port number
> > - Dropped collected tags due to new changes
> >
> > Changes in v10:
> > - Collected Reviewed-by and Tested-by tags
> > - Replaced "void *" with "typec_mux_set_fn_t" for mux_set callbacks
> > - Print out the node name when errors on parsing DT
> > - Use dev_dbg instead of dev_warn when no Type-C switch nodes available
> > - Made the return path of drm_dp_register_mode_switch clearer
> >
> > Changes in v8:
> > - Fixed the build issue when CONFIG_TYPEC=m
> > - Fixed some style issues
> >
> > Changes in v7:
> > - Extracted the common codes to a helper function
> > - New in v7
> >
> > drivers/gpu/drm/display/Kconfig | 8 ++
> > drivers/gpu/drm/display/Makefile | 2 +
> > drivers/gpu/drm/display/drm_dp_typec_helper.c | 105 ++
> > include/drm/display/drm_dp_helper.h | 46
> > 4 files changed, 161 insertions(+)
> > create mode 100644 drivers/gpu/drm/display/drm_dp_typec_helper.c
> >
> > diff --git a/drivers/gpu/drm/display/Kconfig
> > b/drivers/gpu/drm/display/Kconfig
> > index 09712b88a5b8..d61076947a1c 100644
> > --- a/drivers/gpu/drm/display/Kconfig
> > +++ b/drivers/gpu/drm/display/Kconfig
> > @@ -29,6 +29,14 @@ config DRM_DISPLAY_HDMI_HELPER
> > help
> > DRM display helpers for HDMI.
> >
> > +config DRM_DISPLAY_DP_TYPEC_HELPER
> > + bool
> > + default y
> > + depends on DRM_DISPLAY_HELPER
> > + depends on DRM_DISPLAY_HELPER=TYPEC || TYPEC=y
>
> If it is a select'able option, it doesn't make sense to use "depends"
> here. Select will override depends.
>
I'm not very familiar with the practices of Kconfigs, but I'll keep
this in the next version per Andy's comment.
> > + help
> > + DRM display helpers for USB Type-C Displayport Alternate mode.
> > +
> > config DRM_DP_AUX_CHARDEV
> > bool "DRM DP AUX Interface"
> > depends on DRM && DRM_DISPLAY_HELPER
> > diff --git a/drivers/gpu/drm/display/Makefile
> > b/drivers/gpu/drm/display/Makefile
> > index 17ac4a1006a8..2202a6aea38e 100644
> > --- a/drivers/gpu/drm/display/Makefile
> > +++ b/drivers/gpu/drm/display/Makefile
> > @@ -8,6 +8,8 @@ drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_HELPER) += \
> > drm_dp_helper.o \
> > drm_dp_mst_topology.o \
> > drm_dsc_helper.o
> > +drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_TYPEC_HELPER) += \
> > + drm_dp_typec_helper.o
> > drm_display_helper-$(CONFIG_DRM_DISPLAY_HDCP_HELPER) += drm_hdcp_helper.o
> > drm_display_helper-$(CONFIG_DRM_DISPLAY_HDMI_HELPER) += \
> > drm_hdmi_helper.o \
> > diff --git a/drivers/gpu/drm/display/drm_dp_typec_helper.c
> > b/drivers/gpu/drm/display/drm_dp_typec_helper.c
> > new file mode 100644
> > index ..1562a9ccdaf2
> > --- /dev/null
> > +++ b/drivers/gpu/drm/display/drm_dp_typec_helper.c
> > @@ -0,0 +1,105 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +
> > +#include
> > +#include
> > +
> > +static int drm_dp_register_mode_switch(struct device *dev,
> > + struct fwnode_handle *fwnode,
> > + struct drm_dp_typec_switch_desc
> > *switch_desc,
> > + void *data, typec_mux_set_fn_t
> > mux_set)
> > +{
> > + struct drm_dp_typec_port_data *port_data;
> > + struct typec_mux_desc mux_desc = {};
> > + char name[32];
>
> Why 32?
This is just a random length that is probably sufficiently large. I
see other users use the pointer from `fwnode_get_name` directly, but
we want to append the port number to ensure the names are unique.
>
> > + u32 port_num;
> > + int ret;
> > +
> > + ret = fwnode_property_read_u32(fwnode, "reg", _num);
> > + if (ret) {
> > + dev_err(dev, "Failed to read reg property: %d\n", ret);
> > + return ret;
> > + }
> > +
> > + port_data
Re: [PATCH v14 03/10] drm/display: Add Type-C switch helpers
Hi Andy,
Thanks for the review.
On Wed, Mar 22, 2023 at 8:01 PM Andy Shevchenko
wrote:
>
> On Wed, Mar 22, 2023 at 06:46:32PM +0800, Pin-yen Lin wrote:
> > Add helpers to register and unregister Type-C "switches" for bridges
> > capable of switching their output between two downstream devices.
> >
> > The helper registers USB Type-C mode switches when the "mode-switch"
> > and the "reg" properties are available in Device Tree.
>
> ...
>
> > +config DRM_DISPLAY_DP_TYPEC_HELPER
>
> > + bool
> > + default y
>
> def_bool y
>
> > + depends on DRM_DISPLAY_HELPER
> > + depends on DRM_DISPLAY_HELPER=TYPEC || TYPEC=y
> > + help
> > + DRM display helpers for USB Type-C Displayport Alternate mode.
>
> Hmm... Dunno if this help is enough.
Okay I'll add more detail in the next version.
>
> ...
>
> > + snprintf(name, sizeof(name), "%pfwP-%u", fwnode, port_num);
>
> Would it be possible to have a dup in name and would it be a problem if so?
>
The port_num is included in the name, so the names should be unique.
Also, the fwnode name actually contains the reg property, so this name
looks like "endpoint@0-1" now... I'll change the name from fwnode name
to dev_name() per Dmitry's comment.
> ...
>
> > +/**
> > + * drm_dp_register_typec_switches() - register Type-C switches
> > + * @dev: Device that registers Type-C switches
> > + * @port: Device node for the switch
> > + * @switch_desc: A Type-C switch descriptor
> > + * @data: Private data for the switches
> > + * @mux_set: Callback function for typec_mux_set
> > + *
> > + * This function registers USB Type-C switches for DP bridges that can
> > switch
> > + * the output signal between their output pins. This function uses
> > devm_kcalloc
> > + * to allocate memory, so it is expected to only call this in the driver
> > probe
> > + * functions.
> > + *
> > + * Currently only mode switches are implemented, and the function assumes
> > the
> > + * given @port device node has endpoints with "mode-switch" property.
> > + * The port number is determined by the "reg" property of the endpoint.
>
> `kernel-doc -v ...` should complain on absence of "Return" section.
>
> > + */
>
> ...
>
> > + switch_desc->typec_ports = devm_kcalloc(dev,
> > switch_desc->num_typec_switches,
> > + sizeof(struct
> > drm_dp_typec_port_data),
>
>
> sizeof(*switch_desc_typec_ports),
>
> ?
>
> > + GFP_KERNEL);
> > + if (!switch_desc->typec_ports)
> > + return -ENOMEM;
>
> ...
>
> > +#ifdef CONFIG_DRM_DISPLAY_DP_TYPEC_HELPER
>
> Ah, maybe this should use IS_REACHABLE() ?
CONFIG_DRM_DISPLAY_DP_TYPEC_HELPER is a boolean. Is there any
difference between IS_REACHABLE and ifdef when the given config is a
boolean?
>
> > +void drm_dp_unregister_typec_switches(struct drm_dp_typec_switch_desc
> > *switch_desc);
> > +int drm_dp_register_typec_switches(struct device *dev, struct
> > fwnode_handle *port,
> > +struct drm_dp_typec_switch_desc
> > *switch_desc,
> > +void *data, typec_mux_set_fn_t mux_set);
> > +#else
> > +static inline void drm_dp_unregister_typec_switches(struct
> > drm_dp_typec_switch_desc *switch_desc)
> > +{
> > +}
> > +static inline int drm_dp_register_typec_switches(
> > + struct device *dev, struct fwnode_handle *port,
> > + struct drm_dp_typec_switch_desc *switch_desc, void *data,
> > + typec_mux_set_fn_t mux_set)
> > +{
> > + return -EOPNOTSUPP;
> > +}
> > +#endif
>
> --
> With Best Regards,
> Andy Shevchenko
>
Best regards,
Pin-yen
>
Re: [PATCH] drm/i915/hwmon: Use 0 to designate disabled PL1 power limit
On Thu, 30 Mar 2023 08:44:34 -0700, Rodrigo Vivi wrote: > > On Wed, Mar 29, 2023 at 10:50:09PM -0700, Dixit, Ashutosh wrote: > > On Tue, 28 Mar 2023 16:35:43 -0700, Ashutosh Dixit wrote: > > > > > > On ATSM the PL1 limit is disabled at power up. The previous uapi assumed > > > that the PL1 limit is always enabled and therefore did not have a notion > > > of > > > a disabled PL1 limit. This results in erroneous PL1 limit values when the > > > PL1 limit is disabled. For example at power up, the disabled ATSM PL1 > > > limit > > > was previously shown as 0 which means a low PL1 limit whereas the limit > > > being disabled actually implies a high effective PL1 limit value. > > > > > > To get round this problem, the PL1 limit uapi is expanded to include a > > > special value 0 to designate a disabled PL1 limit. > > > > This patch is another attempt to show when the PL1 power limit is disabled > > and to disable it when it needs to. Previous abandoned attempts to do this > > are [1] and [2]. > > > > The preferred way to do this was [2] but that was NAK'd by hwmon folks (see > > [2]). That is why here we fall back on the approach in [1]. > > I still don't get it, but let's move on... > > > > > This patch is identical to [1] except that the value used to disable the > > PL1 limit has been changed to 0 (from -1 in [1]) as was suggested in [2] > > (both -1 and 0 seem ok for the purpose). > > > > > Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/8062 > > > Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/8060 > > > > The link between this patch and these pretty serious bugs might not be > > immediately clear so here's an explanation: > > > > * Because on ATSM the PL1 power limit is disabled on power up and there > > were no means to enable it, in 6fd3d8bf89fc we implemented the means to > > enable the limit when the PL1 hwmon entry (power1_max) was written to. > > > > * Now there is an IGT igt@i915_hwmon@hwmon_write which (a) reads orig value > > from all hwmon sysfs (b) does a bunch of random writes and finally (c) > > restores the orig value read. On ATSM since the orig value was 0, when > > the IGT restores the 0 value, the PL1 limit is now enabled with a value > > of 0. > > > > * PL1 limit of 0 implies a low PL1 limit which causes GPU freq to fall to > > 100 MHz. This causes GuC FW load and several IGT's to start timing out > > and gives rise the above (and even more) bugs about GuC FW load timing > > out. > > I believe these 3 bullets are key information that deserves to be in > the commit message itself. Done in v2. > > With that there, > > Reviewed-by: Rodrigo Vivi Thanks. -- Ashutosh > > > > > > * After this patch, writing 0 would disable the PL1 limit instead of > > enabling it, avoiding the freq drop issue above, and resolving this Intel > > CI issue. > > > > Thanks. > > -- > > Ashutosh > > > > [1] https://patchwork.freedesktop.org/patch/522612/?series=113972=1 > > [2] https://patchwork.freedesktop.org/patch/522652/?series=113984=1
[PATCH v2] drm/i915/hwmon: Use 0 to designate disabled PL1 power limit
On ATSM the PL1 limit is disabled at power up. The previous uapi assumed
that the PL1 limit is always enabled and therefore did not have a notion of
a disabled PL1 limit. This results in erroneous PL1 limit values when the
PL1 limit is disabled. For example at power up, the disabled ATSM PL1 limit
was previously shown as 0 which means a low PL1 limit whereas the limit
being disabled actually implies a high effective PL1 limit value.
To get round this problem, the PL1 limit uapi is expanded to include a
special value 0 to designate a disabled PL1 limit. A read value of 0 means
that the PL1 power limit is disabled, writing 0 disables the limit.
The link between this patch and the bugs mentioned below is as follows:
* Because on ATSM the PL1 power limit is disabled on power up and there
were no means to enable it, we previously implemented the means to
enable the limit when the PL1 hwmon entry (power1_max) was written to.
* Now there is a IGT igt@i915_hwmon@hwmon_write which (a) reads orig value
from all hwmon sysfs (b) does a bunch of random writes and finally (c)
restores the orig value read. On ATSM since the orig value is 0, when
the IGT restores the 0 value, the PL1 limit is now enabled with a value
of 0.
* PL1 limit of 0 implies a low PL1 limit which causes GPU freq to fall to
100 MHz. This causes GuC FW load and several IGT's to start timing out
and gives rise to these Intel CI bugs. After this patch, writing 0 would
disable the PL1 limit instead of enabling it, avoiding the freq drop
issue.
v2: Add explanation for bugs mentioned below (Rodrigo)
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8060
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 4 +++-
drivers/gpu/drm/i915/i915_hwmon.c | 24 +++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
index 2d6a472eef885..8d7d8f05f6cd0 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
@@ -14,7 +14,9 @@ Description: RW. Card reactive sustained (PL1/Tau) power
limit in microwatts.
The power controller will throttle the operating frequency
if the power averaged over a window (typically seconds)
- exceeds this limit.
+ exceeds this limit. A read value of 0 means that the PL1
+ power limit is disabled, writing 0 disables the
+ limit. Writing values > 0 will enable the power limit.
Only supported for particular Intel i915 graphics platforms.
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915/i915_hwmon.c
index 596dd2c070106..c099057888914 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -349,6 +349,8 @@ hwm_power_is_visible(const struct hwm_drvdata *ddat, u32
attr, int chan)
}
}
+#define PL1_DISABLE 0
+
/*
* HW allows arbitrary PL1 limits to be set but silently clamps these values to
* "typical but not guaranteed" min/max values in rg.pkg_power_sku. Follow the
@@ -362,6 +364,14 @@ hwm_power_max_read(struct hwm_drvdata *ddat, long *val)
intel_wakeref_t wakeref;
u64 r, min, max;
+ /* Check if PL1 limit is disabled */
+ with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
+ r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit);
+ if (!(r & PKG_PWR_LIM_1_EN)) {
+ *val = PL1_DISABLE;
+ return 0;
+ }
+
*val = hwm_field_read_and_scale(ddat,
hwmon->rg.pkg_rapl_limit,
PKG_PWR_LIM_1,
@@ -385,8 +395,22 @@ static int
hwm_power_max_write(struct hwm_drvdata *ddat, long val)
{
struct i915_hwmon *hwmon = ddat->hwmon;
+ intel_wakeref_t wakeref;
u32 nval;
+ if (val == PL1_DISABLE) {
+ /* Disable PL1 limit */
+ hwm_locked_with_pm_intel_uncore_rmw(ddat,
hwmon->rg.pkg_rapl_limit,
+ PKG_PWR_LIM_1_EN, 0);
+
+ /* Verify, because PL1 limit cannot be disabled on all
platforms */
+ with_intel_runtime_pm(ddat->uncore->rpm, wakeref)
+ nval = intel_uncore_read(ddat->uncore,
hwmon->rg.pkg_rapl_limit);
+ if (nval & PKG_PWR_LIM_1_EN)
+ return -EPERM;
+ return 0;
+ }
+
/* Computation in 64-bits to avoid overflow. Round to nearest. */
nval = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_power,
SF_POWER);
nval = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, nval);
--
2.38.0
[PATCH] dt-bindings: maxim,max98371: Convert to DT schema
Convert the Maxim Integrated MAX98371 audio codec bindings to DT schema.
Signed-off-by: André Morishita
---
.../devicetree/bindings/sound/max98371.txt| 17
.../bindings/sound/maxim,max98371.yaml| 41 +++
2 files changed, 41 insertions(+), 17 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/max98371.txt
create mode 100644 Documentation/devicetree/bindings/sound/maxim,max98371.yaml
diff --git a/Documentation/devicetree/bindings/sound/max98371.txt
b/Documentation/devicetree/bindings/sound/max98371.txt
deleted file mode 100644
index 8b2b2704b574..
--- a/Documentation/devicetree/bindings/sound/max98371.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-max98371 codec
-
-This device supports I2C mode only.
-
-Required properties:
-
-- compatible : "maxim,max98371"
-- reg : The chip select number on the I2C bus
-
-Example:
-
- {
- max98371: max98371@31 {
- compatible = "maxim,max98371";
- reg = <0x31>;
- };
-};
diff --git a/Documentation/devicetree/bindings/sound/maxim,max98371.yaml
b/Documentation/devicetree/bindings/sound/maxim,max98371.yaml
new file mode 100644
index ..df0262473399
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/maxim,max98371.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/maxim,max98371.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX98371 audio codec
+
+maintainers:
+ - anish kumar
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+const: maxim,max98371
+
+ '#sound-dai-cells':
+const: 0
+
+ reg:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+i2c {
+#address-cells = <1>;
+#size-cells = <0>;
+
+max98371: max98371@31 {
+compatible = "maxim,max98371";
+reg = <0x31>;
+};
+};
--
2.40.0
[Bug 217278] New: ast 0000:03:00.0: PM: **** DPM device timeout **** during S4 resuming
https://bugzilla.kernel.org/show_bug.cgi?id=217278 Bug ID: 217278 Summary: ast :03:00.0: PM: DPM device timeout during S4 resuming Product: Drivers Version: 2.5 Kernel Version: v6.3-rc4 Hardware: Intel OS: Linux Tree: Mainline Status: NEW Severity: blocking Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-...@kernel-bugs.osdl.org Reporter: wendy.w...@intel.com Regression: No On Intel Emerald Rapids Server ast driver will trigger unrecoverable kernel panic during S4 resuming. If add "modprobe.blacklist=ast" kernel parameter to disable ast driver Can avoid the kernel call trace. [ 456.012967] CPU251 is up [ 456.015985] smpboot: =_---CPU UP 252 [ 456.022183] smpboot: Booting Node 1 Processor 252 APIC 0xf9 [ 456.028552] smpboot: Setting warm reset code and vector. [ 456.034650] smpboot: Asserting INIT [ 456.038648] smpboot: Waiting for send to finish... [ 456.044128] smpboot: Deasserting INIT [ 456.048334] smpboot: Waiting for send to finish... [ 456.053818] smpboot: #startup loops: 2 [ 456.058131] smpboot: Sending STARTUP #1 [ 456.062542] smpboot: After apic_write [ 456.066768] smpboot: Startup point 1 [ 456.070898] smpboot: Waiting for send to finish... [ 456.076398] smpboot: Sending STARTUP #2 [ 456.080832] smpboot: After apic_write [ 456.085082] smpboot: Startup point 1 [ 456.089215] smpboot: Waiting for send to finish... [ 456.094718] smpboot: After Startup [ 456.124666] microcode: Load ucode for AP [ 456.129185] microcode: __load_ucode_intel: cp_data = 0x cp_size = 0x0 cp_size = 0x0ack at about 937ed697 [ 456.310542] smpboot: Stack at about 7168126e [ 456.316238] microcode: mc_cpu_starting: CPU253, err: 3 [ 456.359827] CPU253 is up [ 456.362823] smpboot: =_---CPU UP 254 [ 456.369003] smpboot: Booting Node 1 Processor 254 APIC 0xfd [ 456.375378] smpboot: Setting warm reset code and vector. [ 456.381450] smpboot: Asserting INIT [ 456.385449] smpboot: Waiting for send to finish... [ 456.390924] smpboot: Deasserting INIT [ 456.395144] smpboot: Waiting for send to finish... [ 456.400590] smpboot: #startup loops: 2 [ 456.404900] smpboot: Sending STARTUP #1 [ 456.409299] smpboot: After apic_write [ 456.413555] smpboot: Startup point 1 [ 456.417686] smpboot: Waiting for send to finish... [ 456.423193] smpboot: Sending STARTUP #2 [ 456.427619] smpboot: After apic_write [ 456.431869] smpboot: Startup point 1 [ 456.435993] smpboot: Waiting for send to finish... [ 456.441476] smpboot: After Startup [ 456.469575] microcode: Load ucode for AP [ 456.474101] microcode: __load_ucode_intel: cp_data = 0x cp_size = 0x0 [ 456.483382] smpboot: Stack [ 457.507476] ttyS ttyS0: 1 input overrun(s) [ 457.509389] power_meter ACPI000D:00: Found ACPI power meter. [ 457.519717] serial 00:04: activated [ 457.524889] serial 00:05: activated [ 457.543671] nvme nvme0: 8/0/0 default/read/poll queues [ 457.840429] ata7: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 457.847500] ata6: SATA link down (SStatus 4 SControl 300) [ 457.853654] ata5: SATA link down (SStatus 4 SControl 300) [ 457.859819] ata1: SATA link down (SStatus 4 SControl 300) [ 457.865967] ata8: SATA link down (SStatus 4 SControl 300) [ 457.872129] ata4: SATA link down (SStatus 4 SControl 300) [ 457.878292] ata2: SATA link down (SStatus 4 SControl 300) [ 457.884470] ata3: SATA link down (SStatus 4 SControl 300) [ 457.890626] ata7.00: supports DRM functions and may not be fully accessible [ 457.900562] ata7.00: supports DRM functions and may not be fully accessible [ 457.909510] ata7.00: configured for UDMA/133 [ 458.532192] virbr0: port 1(ens3) entered disabled state [ 461.085827] igb :27:00.0 ens1: igb: ens1 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX [ 461.233851] igb :a8:00.0 ens3: igb: ens3 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX [ 461.347436] virbr0: port 1(ens3) entered blocking state [ 461.353412] virbr0: port 1(ens3) entered forwarding state [ 461.377813] igc :01:00.0 enp1s0: NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX [ 469.667476] ast :03:00.0: PM: DPM device timeout [ 469.674142] Call Trace: [ 469.676983] [ 469.679427] __schedule+0x27a/0x6e0 [ 469.683446] ? _raw_spin_unlock_irqrestore+0x22/0x40 [ 469.689117] schedule+0x61/0xe0 [ 469.692739] schedule_timeout+0x7a/0xf0 [ 469.697126] ? __pfx_process_timeout+0x10/0x10 [ 469.702216] msleep+0x2d/0x40 [ 469.705623] ast_dp_launch+0x36/0xc0 [ast] [ 469.710328] ast_post_gpu+0x1fa/0x240 [ast] [ 469.715096] ast_pm_thaw+0x16/0x20 [ast] [ 469.719554] pci_pm_thaw+0x44/0xa0 [ 469.723450] ? __pfx_pci_pm_thaw+0x10/0x10 [ 469.728146]
Re: [Freedreno] [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 74d38f90398a..7419fe58a941 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -31,6 +31,7 @@
#include "msm_kms.h"
#include "msm_gem.h"
#include "phy/dsi_phy.h"
+#include "disp/msm_dsc_helper.h"
#define DSI_RESET_TOGGLE_DELAY_MS 20
@@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
{
struct drm_dsc_config *dsc = msm_host->dsc;
u32 reg, reg_ctrl, reg_ctrl2;
-u32 slice_per_intf, total_bytes_per_intf;
+u32 slice_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
/* first calculate dsc parameters and then program
* compress mode registers
*/
-slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
+slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay);
This looks good
/*
* If slice_count is greater than slice_per_intf
@@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
if (dsc->slice_count > slice_per_intf)
dsc->slice_count = 1;
-total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc, hdisplay,
+dsi_get_bpp(msm_host->format));
-eol_byte_num = total_bytes_per_intf % 3;
-pkt_per_line = slice_per_intf / dsc->slice_count;
+pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT;
And for these values the result is definitely changed. Separate patch
& description please. Just in case, "values per downstream kernel" is
not a proper description for such changes.
Hi Dmitry,
Sure, I can put this into a separate patch.
The reason this was changed from slice_count to SLICE_PER_PKT was
because slice count and slice per packet aren't always equivalent.
There can be cases where panel configures DSC to have multiple soft
slices per interface, but the panel only specifies 1 slice per packet.
Please put this nice description into the commit message. It is exactly
what I was looking for!
BTW: Do you expect to change MSM_DSC_SLICE_PER_PKT later or it will stay
at "1"? If so, it might be easier to drop it and instead add a comment.
MSM_DSC_SLICE_PER_PKT is the default value for panels that don't specify
a slice_per_pkt value. (Now that I think about it, might be better to
call it MSM_DSC_DEFAULT_SLICE_PER_PKT instead...)
Note, there is no slice_per_pkt in drm_dsc_config, so we must come up
with another way to pass this data from the panel or to deduce the
value in our driver.
I don't expect it to change in the future, but it's a little more
readable than just dividing by 1 IMO. If you prefer dropping the macro
and adding a comment, I'm also okay with that.
There is no need to divide by 1, the value doesn't change. So I'd
probably prefer something like:
/* Default to 1 slice per packet */
if (panel_slice_per_pkt)
pkt_per_line = slice_per_intf / panel_slice_per_pkt;
else
pkt_per_line = slice_per_intf;
Or:
/* Default to 1 slice per packet */
slice_per_pkt = 1;
if (panel_slice_per_pkt)
slice_per_pkt = panel_slice_per_pkt;
pkt_per_line = slice_per_intf / slice_per_pkt;
BTW: could you possibly change 'intf' to 'line' to v2? It seems there
is a mixture of them through the code. If there is a difference
between intf and line which is not yet posted, it's fine to keep the
current code. WDYT?
No, I dont agree with the change from intf to line.
In case of dual DSI, intf is not equal to line.
2 intfs = 1 line
Hence that distinction is necessary.
Thanks,
Jessica Zhang
Regarding eol_byte_num, probably the best explanation would be that is
is a size of a padding rather than a size of a trailer bytes in a line
(and thus original calculation was incorrect).
if (is_cmd_mode) /* packet data type */
reg =
DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
@@ -911,6 +912,11 @@ static void dsi_timing_setup(struct
msm_dsi_host *msm_host, bool is_bonded_dsi)
DBG("");
+if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)
+/* Default widebus_en to false for now. */
+hdisplay = msm_dsc_get_pclk_per_line(msm_host->dsc,
mode->hdisplay,
+dsi_get_bpp(msm_host->format));
+
This is definitely something new and thus should probably go into a
separate patch and be described. Also I'm not sure how does that
interact with
Re: [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods
On 3/30/2023 6:25 PM, Dmitry Baryshkov wrote:
On 31/03/2023 04:12, Jessica Zhang wrote:
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang
wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 74d38f90398a..7419fe58a941 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -31,6 +31,7 @@
#include "msm_kms.h"
#include "msm_gem.h"
#include "phy/dsi_phy.h"
+#include "disp/msm_dsc_helper.h"
#define DSI_RESET_TOGGLE_DELAY_MS 20
@@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
{
struct drm_dsc_config *dsc = msm_host->dsc;
u32 reg, reg_ctrl, reg_ctrl2;
- u32 slice_per_intf, total_bytes_per_intf;
+ u32 slice_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
/* first calculate dsc parameters and then program
* compress mode registers
*/
- slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
+ slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay);
This looks good
/*
* If slice_count is greater than slice_per_intf
@@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
if (dsc->slice_count > slice_per_intf)
dsc->slice_count = 1;
- total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc,
hdisplay,
+ dsi_get_bpp(msm_host->format));
- eol_byte_num = total_bytes_per_intf % 3;
- pkt_per_line = slice_per_intf / dsc->slice_count;
+ pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT;
And for these values the result is definitely changed. Separate
patch
& description please. Just in case, "values per downstream
kernel" is
not a proper description for such changes.
Hi Dmitry,
Sure, I can put this into a separate patch.
The reason this was changed from slice_count to SLICE_PER_PKT was
because slice count and slice per packet aren't always equivalent.
There can be cases where panel configures DSC to have multiple soft
slices per interface, but the panel only specifies 1 slice per
packet.
Please put this nice description into the commit message. It is
exactly
what I was looking for!
BTW: Do you expect to change MSM_DSC_SLICE_PER_PKT later or it will
stay
at "1"? If so, it might be easier to drop it and instead add a
comment.
MSM_DSC_SLICE_PER_PKT is the default value for panels that don't
specify
a slice_per_pkt value. (Now that I think about it, might be better to
call it MSM_DSC_DEFAULT_SLICE_PER_PKT instead...)
Note, there is no slice_per_pkt in drm_dsc_config, so we must come up
with another way to pass this data from the panel or to deduce the
value in our driver.
AFAIK we aren't developing on any panels that have a non-default
slice-per-packet count right now, so I'm not sure if it would be worth
the effort to add this if there's no panel we can validate it on.
FWIW, downstream reads slice_per_pkt from a custom DT entry [1]
As you might guess, this approach is frowned upon in upstream kernel.
This info should come from panel (e.g. extend drm_dsc_config or deduce
the value in msm driver).
Yes, I am already aware slice_per_pkt should come from the panel
otherwise defaults to 1. Today MSM driver or even drm_panels for that
matter dont support passing this.
We can extend adding it to the drm_panel and coming from there in
another series. Let this series first add the support for DSC 1.2 for
existing DSC 1.1 configurations. Even DSC 1.1 doesnt use custom
slice_per_pkt today. So nothing broken.
[1]
https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd.dtsi#115
I don't expect it to change in the future, but it's a little more
readable than just dividing by 1 IMO. If you prefer dropping the macro
and adding a comment, I'm also okay with that.
There is no need to divide by 1, the value doesn't change. So I'd
probably prefer something like:
/* Default to 1 slice per packet */
if (panel_slice_per_pkt)
pkt_per_line = slice_per_intf / panel_slice_per_pkt;
else
pkt_per_line = slice_per_intf;
Or:
/* Default to 1 slice per packet */
slice_per_pkt = 1;
if (panel_slice_per_pkt)
slice_per_pkt = panel_slice_per_pkt;
pkt_per_line = slice_per_intf / slice_per_pkt;
Acked.
Re: [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods
On 31/03/2023 04:12, Jessica Zhang wrote:
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang
wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 74d38f90398a..7419fe58a941 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -31,6 +31,7 @@
#include "msm_kms.h"
#include "msm_gem.h"
#include "phy/dsi_phy.h"
+#include "disp/msm_dsc_helper.h"
#define DSI_RESET_TOGGLE_DELAY_MS 20
@@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
{
struct drm_dsc_config *dsc = msm_host->dsc;
u32 reg, reg_ctrl, reg_ctrl2;
- u32 slice_per_intf, total_bytes_per_intf;
+ u32 slice_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
/* first calculate dsc parameters and then program
* compress mode registers
*/
- slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
+ slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay);
This looks good
/*
* If slice_count is greater than slice_per_intf
@@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
if (dsc->slice_count > slice_per_intf)
dsc->slice_count = 1;
- total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc,
hdisplay,
+ dsi_get_bpp(msm_host->format));
- eol_byte_num = total_bytes_per_intf % 3;
- pkt_per_line = slice_per_intf / dsc->slice_count;
+ pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT;
And for these values the result is definitely changed. Separate patch
& description please. Just in case, "values per downstream kernel" is
not a proper description for such changes.
Hi Dmitry,
Sure, I can put this into a separate patch.
The reason this was changed from slice_count to SLICE_PER_PKT was
because slice count and slice per packet aren't always equivalent.
There can be cases where panel configures DSC to have multiple soft
slices per interface, but the panel only specifies 1 slice per packet.
Please put this nice description into the commit message. It is exactly
what I was looking for!
BTW: Do you expect to change MSM_DSC_SLICE_PER_PKT later or it will
stay
at "1"? If so, it might be easier to drop it and instead add a comment.
MSM_DSC_SLICE_PER_PKT is the default value for panels that don't specify
a slice_per_pkt value. (Now that I think about it, might be better to
call it MSM_DSC_DEFAULT_SLICE_PER_PKT instead...)
Note, there is no slice_per_pkt in drm_dsc_config, so we must come up
with another way to pass this data from the panel or to deduce the
value in our driver.
AFAIK we aren't developing on any panels that have a non-default
slice-per-packet count right now, so I'm not sure if it would be worth
the effort to add this if there's no panel we can validate it on.
FWIW, downstream reads slice_per_pkt from a custom DT entry [1]
As you might guess, this approach is frowned upon in upstream kernel.
This info should come from panel (e.g. extend drm_dsc_config or deduce
the value in msm driver).
[1]
https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd.dtsi#115
I don't expect it to change in the future, but it's a little more
readable than just dividing by 1 IMO. If you prefer dropping the macro
and adding a comment, I'm also okay with that.
There is no need to divide by 1, the value doesn't change. So I'd
probably prefer something like:
/* Default to 1 slice per packet */
if (panel_slice_per_pkt)
pkt_per_line = slice_per_intf / panel_slice_per_pkt;
else
pkt_per_line = slice_per_intf;
Or:
/* Default to 1 slice per packet */
slice_per_pkt = 1;
if (panel_slice_per_pkt)
slice_per_pkt = panel_slice_per_pkt;
pkt_per_line = slice_per_intf / slice_per_pkt;
Acked.
--
With best wishes
Dmitry
回复: [PATCH] drm/qxl: prevent memory leak
Dear all: Gentle ping on this patch. Thanks 主 题：[PATCH] drm/qxl: prevent memory leak 日 期：2023-03-22 16:58 发件人：zhouzong...@kylinos.cn 收件人：airlied;Gerd Hoffmann;Dave Airlie;Daniel Vetter; The allocated memory for qdev->dumb_heads should be releasedin qxl_destroy_monitors_object before qxl suspend.otherwise,qxl_create_monitors_object will be called toreallocate memory for qdev->dumb_heads after qxl resume,it will cause memory leak.Signed-off-by: Zongmin Zhou---drivers/gpu/drm/qxl/qxl_display.c | 3 +++1 file changed, 3 insertions(+)diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.cindex 6492a70e3c39..404b0483bb7c 100644--- a/drivers/gpu/drm/qxl/qxl_display.c+++ b/drivers/gpu/drm/qxl/qxl_display.c@@ -1229,6 +1229,9 @@ int qxl_destroy_monitors_object(struct qxl_device *qdev)if (!qdev->monitors_config_bo)return 0;+ kfree(qdev->dumb_heads);+ qdev->dumb_heads = NULL;+qdev->monitors_config = NULL;qdev->ram_header->monitors_config = 0;-- 2.34.1No virus foundChecked by Hillstone Network AntiVirus
Re: [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods
On 31.03.2023 03:12, Jessica Zhang wrote:
>
>
> On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
>> On Fri, 31 Mar 2023 at 03:07, Jessica Zhang
>> wrote:
>>>
>>>
>>>
>>> On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
>
>
> On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
>> On 30/03/2023 02:18, Jessica Zhang wrote:
>>> Use MSM and DRM DSC helper methods.
>>>
>>> Signed-off-by: Jessica Zhang
>>> ---
>>> drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
>>> 1 file changed, 12 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
>>> b/drivers/gpu/drm/msm/dsi/dsi_host.c
>>> index 74d38f90398a..7419fe58a941 100644
>>> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
>>> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
>>> @@ -31,6 +31,7 @@
>>> #include "msm_kms.h"
>>> #include "msm_gem.h"
>>> #include "phy/dsi_phy.h"
>>> +#include "disp/msm_dsc_helper.h"
>>> #define DSI_RESET_TOGGLE_DELAY_MS 20
>>> @@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct
>>> msm_dsi_host *msm_host, bool is_cmd_mod
>>> {
>>> struct drm_dsc_config *dsc = msm_host->dsc;
>>> u32 reg, reg_ctrl, reg_ctrl2;
>>> - u32 slice_per_intf, total_bytes_per_intf;
>>> + u32 slice_per_intf;
>>> u32 pkt_per_line;
>>> u32 eol_byte_num;
>>> /* first calculate dsc parameters and then program
>>> * compress mode registers
>>> */
>>> - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
>>> + slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay);
>>
>> This looks good
>>
>>> /*
>>> * If slice_count is greater than slice_per_intf
>>> @@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct
>>> msm_dsi_host *msm_host, bool is_cmd_mod
>>> if (dsc->slice_count > slice_per_intf)
>>> dsc->slice_count = 1;
>>> - total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
>>> + eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc, hdisplay,
>>> + dsi_get_bpp(msm_host->format));
>>> - eol_byte_num = total_bytes_per_intf % 3;
>>> - pkt_per_line = slice_per_intf / dsc->slice_count;
>>> + pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT;
>>
>> And for these values the result is definitely changed. Separate patch
>> & description please. Just in case, "values per downstream kernel" is
>> not a proper description for such changes.
>
> Hi Dmitry,
>
> Sure, I can put this into a separate patch.
>
> The reason this was changed from slice_count to SLICE_PER_PKT was
> because slice count and slice per packet aren't always equivalent.
> There can be cases where panel configures DSC to have multiple soft
> slices per interface, but the panel only specifies 1 slice per packet.
Please put this nice description into the commit message. It is exactly
what I was looking for!
BTW: Do you expect to change MSM_DSC_SLICE_PER_PKT later or it will stay
at "1"? If so, it might be easier to drop it and instead add a comment.
>>>
>>> MSM_DSC_SLICE_PER_PKT is the default value for panels that don't specify
>>> a slice_per_pkt value. (Now that I think about it, might be better to
>>> call it MSM_DSC_DEFAULT_SLICE_PER_PKT instead...)
>>
>> Note, there is no slice_per_pkt in drm_dsc_config, so we must come up
>> with another way to pass this data from the panel or to deduce the
>> value in our driver.
>
> AFAIK we aren't developing on any panels that have a non-default
> slice-per-packet count right now, so I'm not sure if it would be worth the
> effort to add this if there's no panel we can validate it on.
Some (but not all) SONY phones use panels with that set to 2, I'd
greatly appreciate fully implementing this.
Konrad
>
> FWIW, downstream reads slice_per_pkt from a custom DT entry [1]
>
> [1]
> https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd.dtsi#115
>
>>
>>>
>>> I don't expect it to change in the future, but it's a little more
>>> readable than just dividing by 1 IMO. If you prefer dropping the macro
>>> and adding a comment, I'm also okay with that.
>>
>> There is no need to divide by 1, the value doesn't change. So I'd
>> probably prefer something like:
>>
>> /* Default to 1 slice per packet */
>> if (panel_slice_per_pkt)
>> pkt_per_line = slice_per_intf / panel_slice_per_pkt;
>> else
>> pkt_per_line = slice_per_intf;
>>
>> Or:
>>
>> /* Default to 1 slice per packet */
>> slice_per_pkt = 1;
>> if (panel_slice_per_pkt)
>> slice_per_pkt = panel_slice_per_pkt;
>> pkt_per_line = slice_per_intf / slice_per_pkt;
>
> Acked.
>
>>
Re: [PATCH v3 0/5] SM8[12]50 GPU speedbin
On 31.03.2023 03:14, Konrad Dybcio wrote: > This series brings SM8[12]50 (A6[45]0) speedbin support along with a > touch-up for 8150, allowing Adreno to cooperate with the display hw. > > Tested on Xperia 5 II (SM8250 Edo PDX206) and Xperia 5 (SM8150 Kumano > Bahamut). > > v2 -> v3: > - Don't swap speedbin 2 (with fuse val 3) and speedbin 3 (with fuse val 2) > on SM8250 (no functional change, this is all a software construct but > let's stick with the official mapping) [2/5], [5/5] > > I kept all of the tags in good faith. v2: https://lore.kernel.org/linux-arm-msm/20230120172233.1905761-1-konrad.dyb...@linaro.org/ Konrad > > v1 -> v2: > - Drop bindings patches (Applied by Srini) > - Remove leftover comment about missing speedbin in 8150 DTSI (Marijn) > - Collect tags > > Signed-off-by: Konrad Dybcio > --- > Konrad Dybcio (5): > drm/msm/a6xx: Add support for A640 speed binning > drm/msm/a6xx: Add support for A650 speed binning > arm64: dts: qcom: sm8150: Don't start Adreno in headless mode > arm64: dts: qcom: sm8150: Add GPU speedbin support > arm64: dts: qcom: sm8250: Add GPU speedbin support > > arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 5 + > arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 5 + > arch/arm64/boot/dts/qcom/sm8150.dtsi| 31 +-- > arch/arm64/boot/dts/qcom/sm8250.dtsi| 23 ++- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++ > 5 files changed, 84 insertions(+), 11 deletions(-) > --- > base-commit: a6d9e3034536ba4b68ac34490c02267e6eec9c05 > change-id: 20230331-topic-konahana_speedbin-abe0c725f244 > > Best regards,
[PATCH v3 5/5] arm64: dts: qcom: sm8250: Add GPU speedbin support
SM8250 has (at least) four GPU speed bins. With the support added on the
driver side, wire up bin detection in the DTS to restrict lower-quality
SKUs from running at frequencies they were not validated at.
Tested-by: Marijn Suijten # On Sony Xperia 5 II
(speed bin 0x7)
Reviewed-by: Marijn Suijten
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 7b78761f2041..65e6fcff2d6c 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -962,6 +962,18 @@ ipcc: mailbox@408000 {
#mbox-cells = <2>;
};
+ qfprom: efuse@784000 {
+ compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
+ reg = <0 0x00784000 0 0x8ff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpu_speed_bin: gpu_speed_bin@19b {
+ reg = <0x19b 0x1>;
+ bits = <5 3>;
+ };
+ };
+
rng: rng@793000 {
compatible = "qcom,prng-ee";
reg = <0 0x00793000 0 0x1000>;
@@ -2559,49 +2571,58 @@ gpu: gpu@3d0 {
qcom,gmu = <>;
+ nvmem-cells = <_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
status = "disabled";
zap-shader {
memory-region = <_mem>;
};
- /* note: downstream checks gpu binning for 670 Mhz */
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-67000 {
opp-hz = /bits/ 64 <67000>;
opp-level =
;
+ opp-supported-hw = <0xa>;
};
opp-58700 {
opp-hz = /bits/ 64 <58700>;
opp-level = ;
+ opp-supported-hw = <0xb>;
};
opp-52500 {
opp-hz = /bits/ 64 <52500>;
opp-level =
;
+ opp-supported-hw = <0xf>;
};
opp-49000 {
opp-hz = /bits/ 64 <49000>;
opp-level =
;
+ opp-supported-hw = <0xf>;
};
opp-44160 {
opp-hz = /bits/ 64 <44160>;
opp-level =
;
+ opp-supported-hw = <0xf>;
};
opp-4 {
opp-hz = /bits/ 64 <4>;
opp-level = ;
+ opp-supported-hw = <0xf>;
};
opp-30500 {
opp-hz = /bits/ 64 <30500>;
opp-level =
;
+ opp-supported-hw = <0xf>;
};
};
};
--
2.40.0
[PATCH v3 1/5] drm/msm/a6xx: Add support for A640 speed binning
Add support for matching QFPROM fuse values to get the correct speed bin
on A640 (SM8150) GPUs.
Reviewed-by: Akhil P Oommen
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 1e09777cce3f..663090973c1b 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1890,6 +1890,16 @@ static u32 a619_get_speed_bin(u32 fuse)
return UINT_MAX;
}
+static u32 a640_get_speed_bin(u32 fuse)
+{
+ if (fuse == 0)
+ return 0;
+ else if (fuse == 1)
+ return 1;
+
+ return UINT_MAX;
+}
+
static u32 adreno_7c3_get_speed_bin(u32 fuse)
{
if (fuse == 0)
@@ -1915,6 +1925,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct
adreno_rev rev, u32 fuse)
if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
val = adreno_7c3_get_speed_bin(fuse);
+ if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
+ val = a640_get_speed_bin(fuse);
+
if (val == UINT_MAX) {
DRM_DEV_ERROR(dev,
"missing support for speed-bin: %u. Some OPPs may not
be supported by hardware\n",
--
2.40.0
[PATCH v3 4/5] arm64: dts: qcom: sm8150: Add GPU speedbin support
SM8150 has (at least) two GPU speed bins. With the support added on the
driver side, wire up bin detection in the DTS to restrict lower-quality
SKUs from running at frequencies they were not validated at.
Tested-by: Marijn Suijten # On Sony Xperia 5
(speed bin 0x3)
Reviewed-by: Marijn Suijten
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 880483922f22..e4230877555d 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -952,6 +952,17 @@ ethernet: ethernet@2 {
status = "disabled";
};
+ qfprom: efuse@784000 {
+ compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
+ reg = <0 0x00784000 0 0x8ff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpu_speed_bin: gpu_speed_bin@133 {
+ reg = <0x133 0x1>;
+ bits = <5 3>;
+ };
+ };
qupv3_id_0: geniqup@8c {
compatible = "qcom,geni-se-qup";
@@ -2169,44 +2180,52 @@ gpu: gpu@2c0 {
qcom,gmu = <>;
+ nvmem-cells = <_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
status = "disabled";
zap-shader {
memory-region = <_mem>;
};
- /* note: downstream checks gpu binning for 675 Mhz */
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-67500 {
opp-hz = /bits/ 64 <67500>;
opp-level =
;
+ opp-supported-hw = <0x2>;
};
opp-58500 {
opp-hz = /bits/ 64 <58500>;
opp-level = ;
+ opp-supported-hw = <0x3>;
};
opp-49920 {
opp-hz = /bits/ 64 <49920>;
opp-level =
;
+ opp-supported-hw = <0x3>;
};
opp-42700 {
opp-hz = /bits/ 64 <42700>;
opp-level =
;
+ opp-supported-hw = <0x3>;
};
opp-34500 {
opp-hz = /bits/ 64 <34500>;
opp-level = ;
+ opp-supported-hw = <0x3>;
};
opp-25700 {
opp-hz = /bits/ 64 <25700>;
opp-level =
;
+ opp-supported-hw = <0x3>;
};
};
};
--
2.40.0
[PATCH v3 2/5] drm/msm/a6xx: Add support for A650 speed binning
Add support for matching QFPROM fuse values to get the correct speed bin
on A650 (SM8250) GPUs.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 663090973c1b..2afc160cf06a 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1900,6 +1900,21 @@ static u32 a640_get_speed_bin(u32 fuse)
return UINT_MAX;
}
+static u32 a650_get_speed_bin(u32 fuse)
+{
+ if (fuse == 0)
+ return 0;
+ else if (fuse == 1)
+ return 1;
+ /* Yep, 2 and 3 are swapped! :/ */
+ else if (fuse == 2)
+ return 3;
+ else if (fuse == 3)
+ return 2;
+
+ return UINT_MAX;
+}
+
static u32 adreno_7c3_get_speed_bin(u32 fuse)
{
if (fuse == 0)
@@ -1928,6 +1943,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct
adreno_rev rev, u32 fuse)
if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
val = a640_get_speed_bin(fuse);
+ if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
+ val = a650_get_speed_bin(fuse);
+
if (val == UINT_MAX) {
DRM_DEV_ERROR(dev,
"missing support for speed-bin: %u. Some OPPs may not
be supported by hardware\n",
--
2.40.0
[PATCH v3 3/5] arm64: dts: qcom: sm8150: Don't start Adreno in headless mode
Now that there's display support, there is no reason to assume the default
mode for Adreno should be headless. Keep it like that for boards that
previously enabled it, so as not to create regressions though.
Tested-by: Marijn Suijten # On Sony Xperia 5
Reviewed-by: Marijn Suijten
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 5 +
arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 5 +
arch/arm64/boot/dts/qcom/sm8150.dtsi| 10 +-
3 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
index 8f014a232526..c0200e7f3f74 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
@@ -359,6 +359,11 @@ {
};
{
+ /*
+* NOTE: "amd,imageon" makes Adreno start in headless mode, remove it
+* after display support is added on this board.
+*/
+ compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
index eff995a07ab7..34ec84916bdd 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
@@ -354,6 +354,11 @@ {
};
{
+ /*
+* NOTE: "amd,imageon" makes Adreno start in headless mode, remove it
+* after display support is added on this board.
+*/
+ compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 9491be4a6bf0..880483922f22 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -2157,15 +2157,7 @@ compute-cb@3 {
};
gpu: gpu@2c0 {
- /*
-* note: the amd,imageon compatible makes it possible
-* to use the drm/msm driver without the display node,
-* make sure to remove it when display node is added
-*/
- compatible = "qcom,adreno-640.1",
-"qcom,adreno",
-"amd,imageon";
-
+ compatible = "qcom,adreno-640.1", "qcom,adreno";
reg = <0 0x02c0 0 0x4>;
reg-names = "kgsl_3d0_reg_memory";
--
2.40.0
[PATCH v3 0/5] SM8[12]50 GPU speedbin
This series brings SM8[12]50 (A6[45]0) speedbin support along with a touch-up for 8150, allowing Adreno to cooperate with the display hw. Tested on Xperia 5 II (SM8250 Edo PDX206) and Xperia 5 (SM8150 Kumano Bahamut). v2 -> v3: - Don't swap speedbin 2 (with fuse val 3) and speedbin 3 (with fuse val 2) on SM8250 (no functional change, this is all a software construct but let's stick with the official mapping) [2/5], [5/5] I kept all of the tags in good faith. v1 -> v2: - Drop bindings patches (Applied by Srini) - Remove leftover comment about missing speedbin in 8150 DTSI (Marijn) - Collect tags Signed-off-by: Konrad Dybcio --- Konrad Dybcio (5): drm/msm/a6xx: Add support for A640 speed binning drm/msm/a6xx: Add support for A650 speed binning arm64: dts: qcom: sm8150: Don't start Adreno in headless mode arm64: dts: qcom: sm8150: Add GPU speedbin support arm64: dts: qcom: sm8250: Add GPU speedbin support arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 5 + arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 5 + arch/arm64/boot/dts/qcom/sm8150.dtsi| 31 +-- arch/arm64/boot/dts/qcom/sm8250.dtsi| 23 ++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++ 5 files changed, 84 insertions(+), 11 deletions(-) --- base-commit: a6d9e3034536ba4b68ac34490c02267e6eec9c05 change-id: 20230331-topic-konahana_speedbin-abe0c725f244 Best regards, -- Konrad Dybcio
Re: [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods
On 3/30/2023 5:16 PM, Dmitry Baryshkov wrote:
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang wrote:
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 74d38f90398a..7419fe58a941 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -31,6 +31,7 @@
#include "msm_kms.h"
#include "msm_gem.h"
#include "phy/dsi_phy.h"
+#include "disp/msm_dsc_helper.h"
#define DSI_RESET_TOGGLE_DELAY_MS 20
@@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
{
struct drm_dsc_config *dsc = msm_host->dsc;
u32 reg, reg_ctrl, reg_ctrl2;
-u32 slice_per_intf, total_bytes_per_intf;
+u32 slice_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
/* first calculate dsc parameters and then program
* compress mode registers
*/
-slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
+slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay);
This looks good
/*
* If slice_count is greater than slice_per_intf
@@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
if (dsc->slice_count > slice_per_intf)
dsc->slice_count = 1;
-total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc, hdisplay,
+dsi_get_bpp(msm_host->format));
-eol_byte_num = total_bytes_per_intf % 3;
-pkt_per_line = slice_per_intf / dsc->slice_count;
+pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT;
And for these values the result is definitely changed. Separate patch
& description please. Just in case, "values per downstream kernel" is
not a proper description for such changes.
Hi Dmitry,
Sure, I can put this into a separate patch.
The reason this was changed from slice_count to SLICE_PER_PKT was
because slice count and slice per packet aren't always equivalent.
There can be cases where panel configures DSC to have multiple soft
slices per interface, but the panel only specifies 1 slice per packet.
Please put this nice description into the commit message. It is exactly
what I was looking for!
BTW: Do you expect to change MSM_DSC_SLICE_PER_PKT later or it will stay
at "1"? If so, it might be easier to drop it and instead add a comment.
MSM_DSC_SLICE_PER_PKT is the default value for panels that don't specify
a slice_per_pkt value. (Now that I think about it, might be better to
call it MSM_DSC_DEFAULT_SLICE_PER_PKT instead...)
Note, there is no slice_per_pkt in drm_dsc_config, so we must come up
with another way to pass this data from the panel or to deduce the
value in our driver.
AFAIK we aren't developing on any panels that have a non-default
slice-per-packet count right now, so I'm not sure if it would be worth
the effort to add this if there's no panel we can validate it on.
FWIW, downstream reads slice_per_pkt from a custom DT entry [1]
[1]
https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd.dtsi#115
I don't expect it to change in the future, but it's a little more
readable than just dividing by 1 IMO. If you prefer dropping the macro
and adding a comment, I'm also okay with that.
There is no need to divide by 1, the value doesn't change. So I'd
probably prefer something like:
/* Default to 1 slice per packet */
if (panel_slice_per_pkt)
pkt_per_line = slice_per_intf / panel_slice_per_pkt;
else
pkt_per_line = slice_per_intf;
Or:
/* Default to 1 slice per packet */
slice_per_pkt = 1;
if (panel_slice_per_pkt)
slice_per_pkt = panel_slice_per_pkt;
pkt_per_line = slice_per_intf / slice_per_pkt;
Acked.
BTW: could you possibly change 'intf' to 'line' to v2? It seems there
is a mixture of them through the code. If there is a difference
between intf and line which is not yet posted, it's fine to keep the
current code. WDYT?
AFAIK 'line' and 'intf' seem to be equivalent. I'll make this change
once I confirm this.
Thanks,
Jessica Zhang
Thanks,
Jessica Zhang
Regarding eol_byte_num, probably the best explanation would be that is
is a size of a padding rather than a size of a trailer bytes in a line
(and thus original calculation was incorrect).
if (is_cmd_mode) /* packet data type */
reg =
DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
@@ -911,6 +912,11 @@ static void dsi_timing_setup(struct
msm_dsi_host
Re: [PATCH v2 2/5] drm/msm/a6xx: Add support for A650 speed binning
On 20/01/2023 19:22, Konrad Dybcio wrote:
Add support for matching QFPROM fuse values to get the correct speed bin
on A650 (SM8250) GPUs.
Signed-off-by: Konrad Dybcio
Reviewed-by: Dmitry Baryshkov
Thank you for the patch. It took me a while to dive into various ways
vendor kernels handle GPU speed bins.
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 0ee8cb3e490c..c5f5d0bb3fdc 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1894,6 +1894,20 @@ static u32 a640_get_speed_bin(u32 fuse)
return UINT_MAX;
}
+static u32 a650_get_speed_bin(u32 fuse)
+{
+ if (fuse == 0)
+ return 0;
+ else if (fuse == 1)
+ return 1;
+ else if (fuse == 2)
+ return 2;
+ else if (fuse == 3)
+ return 3;
+
+ return UINT_MAX;
+}
+
static u32 adreno_7c3_get_speed_bin(u32 fuse)
{
if (fuse == 0)
@@ -1922,6 +1936,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct
adreno_rev rev, u32 fuse)
if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
val = a640_get_speed_bin(fuse);
+ if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
+ val = a650_get_speed_bin(fuse);
+
if (val == UINT_MAX) {
DRM_DEV_ERROR(dev,
"missing support for speed-bin: %u. Some OPPs may not be
supported by hardware\n",
--
With best wishes
Dmitry
[PATCH 2/3] drm/i915/mtl: workaround coherency issue for Media
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache line. CTB communication
is impacted by this issue because the head and tail pointers are
adjacent words within a cache line (see struct guc_ct_buffer_desc),
where one is written by GuC and the other by the host.
This patch circumvents the issue by making CPU/GPU shared memory
uncacheable (WC on CPU side, and PAT index 2 for GPU). Also for
CTB which is being updated by both CPU and GuC, mfence instruction
is added to make sure the CPU writes are visible to GPU right away
(flush the write combining buffer).
While fixing the CTB issue, we noticed some random GSC firmware
loading failure because the share buffers are cacheable (WB) on CPU
side but uncached on GPU side. To fix these issues we need to map
such shared buffers as WC on CPU side. Since such allocations are
not all done through GuC allocator, to avoid too many code changes,
the i915_coherent_map_type() is now hard coded to return WC for MTL.
BSpec: 45101
Signed-off-by: Fei Yang
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 5 -
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 13 +
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 7 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 18 --
4 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index ecd86130b74f..89fc8ea6bcfc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -469,7 +469,10 @@ enum i915_map_type i915_coherent_map_type(struct
drm_i915_private *i915,
struct drm_i915_gem_object *obj,
bool always_coherent)
{
- if (i915_gem_object_is_lmem(obj))
+ /*
+* Wa_22016122933: always return I915_MAP_WC for MTL
+*/
+ if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
return I915_MAP_WC;
if (HAS_LLC(i915) || always_coherent)
return I915_MAP_WB;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index 1d9fdfb11268..236673c02f9a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -110,6 +110,13 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
if (obj->base.size < gsc->fw.size)
return -ENOSPC;
+ /*
+* Wa_22016122933: For MTL the shared memory needs to be mapped
+* as WC on CPU side and UC (PAT index 2) on GPU side
+*/
+ if (IS_METEORLAKE(i915))
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
+
dst = i915_gem_object_pin_map_unlocked(obj,
i915_coherent_map_type(i915,
obj, true));
if (IS_ERR(dst))
@@ -125,6 +132,12 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
memset(dst, 0, obj->base.size);
memcpy(dst, src, gsc->fw.size);
+ /*
+* Wa_22016122933: Making sure the data in dst is
+* visible to GSC right away
+*/
+ intel_guc_write_barrier(>uc.guc);
+
i915_gem_object_unpin_map(gsc->fw.obj);
i915_gem_object_unpin_map(obj);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index d76508fa3af7..f9bddaa876d9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -743,6 +743,13 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc
*guc, u32 size)
if (IS_ERR(obj))
return ERR_CAST(obj);
+ /*
+* Wa_22016122933: For MTL the shared memory needs to be mapped
+* as WC on CPU side and UC (PAT index 2) on GPU side
+*/
+ if (IS_METEORLAKE(gt->i915))
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
+
vma = i915_vma_instance(obj, >ggtt->vm, NULL);
if (IS_ERR(vma))
goto err;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 1803a633ed64..98e682b7df07 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -415,12 +415,6 @@ static int ct_write(struct intel_guc_ct *ct,
}
GEM_BUG_ON(tail > size);
- /*
-* make sure H2G buffer update and LRC tail update (if this triggering a
-* submission) are visible before updating the descriptor tail
-*/
- intel_guc_write_barrier(ct_to_guc(ct));
-
/* update local copies */
ctb->tail = tail;
GEM_BUG_ON(atomic_read(>space) < len +
[PATCH 1/3] drm/i915/mtl: Define MOCS and PAT tables for MTL
From: Fei Yang
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for ADM/L4 cache calls a
MOCS/PAT table update.
Also add PTE encode functions for MTL as it has different PAT
index definition than previous platforms.
BSpec: 44509, 45101, 44235
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Fei Yang
---
drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 43 --
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 3 +
drivers/gpu/drm/i915/gt/intel_ggtt.c | 36 ++-
drivers/gpu/drm/i915/gt/intel_gtt.c | 23 ++-
drivers/gpu/drm/i915/gt/intel_gtt.h | 20 ++-
drivers/gpu/drm/i915/gt/intel_mocs.c | 76 ++--
drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 1 +
9 files changed, 189 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 2bf5cce232d5..dc82a756c899 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -300,7 +300,7 @@ intel_dpt_create(struct intel_framebuffer *fb)
vm->vma_ops.bind_vma= dpt_bind_vma;
vm->vma_ops.unbind_vma = dpt_unbind_vma;
- vm->pte_encode = gen8_ggtt_pte_encode;
+ vm->pte_encode = vm->gt->ggtt->vm.pte_encode;
dpt->obj = dpt_obj;
dpt->obj->is_dpt = true;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 4daaa6f55668..4197b43150cc 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -55,6 +55,34 @@ static u64 gen8_pte_encode(dma_addr_t addr,
return pte;
}
+static u64 mtl_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
+
+ if (unlikely(flags & PTE_READ_ONLY))
+ pte &= ~GEN8_PAGE_RW;
+
+ if (flags & PTE_LM)
+ pte |= GEN12_PPGTT_PTE_LM | GEN12_PPGTT_PTE_NC;
+
+ switch (level) {
+ case I915_CACHE_NONE:
+ pte |= GEN12_PPGTT_PTE_PAT1;
+ break;
+ case I915_CACHE_LLC:
+ case I915_CACHE_L3_LLC:
+ pte |= GEN12_PPGTT_PTE_PAT0 | GEN12_PPGTT_PTE_PAT1;
+ break;
+ case I915_CACHE_WT:
+ pte |= GEN12_PPGTT_PTE_PAT0;
+ break;
+ }
+
+ return pte;
+}
+
static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
{
struct drm_i915_private *i915 = ppgtt->vm.i915;
@@ -427,7 +455,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
u32 flags)
{
struct i915_page_directory *pd;
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+ const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level,
flags);
gen8_pte_t *vaddr;
pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
@@ -580,7 +608,7 @@ static void gen8_ppgtt_insert_huge(struct
i915_address_space *vm,
enum i915_cache_level cache_level,
u32 flags)
{
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+ const gen8_pte_t pte_encode = vm->pte_encode(0, cache_level, flags);
unsigned int rem = sg_dma_len(iter->sg);
u64 start = vma_res->start;
@@ -743,7 +771,7 @@ static void gen8_ppgtt_insert_entry(struct
i915_address_space *vm,
GEM_BUG_ON(pt->is_compact);
vaddr = px_vaddr(pt);
- vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
+ vaddr[gen8_pd_index(idx, 0)] = vm->pte_encode(addr, level, flags);
drm_clflush_virt_range([gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
@@ -773,7 +801,7 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct
i915_address_space *vm,
}
vaddr = px_vaddr(pt);
- vaddr[gen8_pd_index(idx, 0) / 16] = gen8_pte_encode(addr, level, flags);
+ vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, level, flags);
}
static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
@@ -820,7 +848,7 @@ static int gen8_init_scratch(struct i915_address_space *vm)
pte_flags |= PTE_LM;
vm->scratch[0]->encode =
- gen8_pte_encode(px_dma(vm->scratch[0]),
+ vm->pte_encode(px_dma(vm->scratch[0]),
I915_CACHE_NONE, pte_flags);
for (i = 1; i <= vm->top; i++) {
@@ -963,7 +991,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
*/
ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
- ppgtt->vm.pte_encode = gen8_pte_encode;
+ if (GRAPHICS_VER_FULL(gt->i915) >=
[PATCH 3/3] drm/i915/mtl: end support for set caching ioctl
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
cache.
Signed-off-by: Fei Yang
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 -
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 497de40b8e68..33b73bea1e08 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -335,6 +335,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void
*data,
if (IS_DGFX(i915))
return -ENODEV;
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ return -EOPNOTSUPP;
+
switch (args->caching) {
case I915_CACHING_NONE:
level = I915_CACHE_NONE;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 37d1efcd3ca6..e602c323896b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region
*mem,
obj->write_domain = I915_GEM_DOMAIN_CPU;
obj->read_domains = I915_GEM_DOMAIN_CPU;
- if (HAS_LLC(i915))
+ /*
+* MTL doesn't snooping CPU cache by default for GPU access (namely
+* 1-way coherency). However some UMD's are currently depending on
+* that. Make 1-way coherent the default setting for MTL. A follow
+* up patch will extend the GEM_CREATE uAPI to allow UMD's specify
+* caching mode at BO creation time
+*/
+ if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)))
/* On some devices, we can have the GPU use the LLC (the CPU
* cache) for about a 10% performance improvement
* compared to uncached. Graphics requests other than
--
2.25.1
Re: [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods
On Fri, 31 Mar 2023 at 03:07, Jessica Zhang wrote:
>
>
>
> On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
> > On 31/03/2023 01:49, Jessica Zhang wrote:
> >>
> >>
> >> On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
> >>> On 30/03/2023 02:18, Jessica Zhang wrote:
> Use MSM and DRM DSC helper methods.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
> b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 74d38f90398a..7419fe58a941 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -31,6 +31,7 @@
> #include "msm_kms.h"
> #include "msm_gem.h"
> #include "phy/dsi_phy.h"
> +#include "disp/msm_dsc_helper.h"
> #define DSI_RESET_TOGGLE_DELAY_MS 20
> @@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct
> msm_dsi_host *msm_host, bool is_cmd_mod
> {
> struct drm_dsc_config *dsc = msm_host->dsc;
> u32 reg, reg_ctrl, reg_ctrl2;
> -u32 slice_per_intf, total_bytes_per_intf;
> +u32 slice_per_intf;
> u32 pkt_per_line;
> u32 eol_byte_num;
> /* first calculate dsc parameters and then program
> * compress mode registers
> */
> -slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
> +slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay);
> >>>
> >>> This looks good
> >>>
> /*
> * If slice_count is greater than slice_per_intf
> @@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct
> msm_dsi_host *msm_host, bool is_cmd_mod
> if (dsc->slice_count > slice_per_intf)
> dsc->slice_count = 1;
> -total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
> +eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc, hdisplay,
> +dsi_get_bpp(msm_host->format));
> -eol_byte_num = total_bytes_per_intf % 3;
> -pkt_per_line = slice_per_intf / dsc->slice_count;
> +pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT;
> >>>
> >>> And for these values the result is definitely changed. Separate patch
> >>> & description please. Just in case, "values per downstream kernel" is
> >>> not a proper description for such changes.
> >>
> >> Hi Dmitry,
> >>
> >> Sure, I can put this into a separate patch.
> >>
> >> The reason this was changed from slice_count to SLICE_PER_PKT was
> >> because slice count and slice per packet aren't always equivalent.
> >> There can be cases where panel configures DSC to have multiple soft
> >> slices per interface, but the panel only specifies 1 slice per packet.
> >
> > Please put this nice description into the commit message. It is exactly
> > what I was looking for!
> >
> > BTW: Do you expect to change MSM_DSC_SLICE_PER_PKT later or it will stay
> > at "1"? If so, it might be easier to drop it and instead add a comment.
>
> MSM_DSC_SLICE_PER_PKT is the default value for panels that don't specify
> a slice_per_pkt value. (Now that I think about it, might be better to
> call it MSM_DSC_DEFAULT_SLICE_PER_PKT instead...)
Note, there is no slice_per_pkt in drm_dsc_config, so we must come up
with another way to pass this data from the panel or to deduce the
value in our driver.
>
> I don't expect it to change in the future, but it's a little more
> readable than just dividing by 1 IMO. If you prefer dropping the macro
> and adding a comment, I'm also okay with that.
There is no need to divide by 1, the value doesn't change. So I'd
probably prefer something like:
/* Default to 1 slice per packet */
if (panel_slice_per_pkt)
pkt_per_line = slice_per_intf / panel_slice_per_pkt;
else
pkt_per_line = slice_per_intf;
Or:
/* Default to 1 slice per packet */
slice_per_pkt = 1;
if (panel_slice_per_pkt)
slice_per_pkt = panel_slice_per_pkt;
pkt_per_line = slice_per_intf / slice_per_pkt;
BTW: could you possibly change 'intf' to 'line' to v2? It seems there
is a mixture of them through the code. If there is a difference
between intf and line which is not yet posted, it's fine to keep the
current code. WDYT?
>
> Thanks,
>
> Jessica Zhang
>
> >
> > Regarding eol_byte_num, probably the best explanation would be that is
> > is a size of a padding rather than a size of a trailer bytes in a line
> > (and thus original calculation was incorrect).
> >
> >>
> >>>
> if (is_cmd_mode) /* packet data type */
> reg =
> DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
> @@ -911,6 +912,11 @@ static void dsi_timing_setup(struct
> msm_dsi_host *msm_host, bool is_bonded_dsi)
> DBG("");
> +if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)
> +/* Default widebus_en to false
Re: [GIT PULL] etnaviv-fixes for 6.3
On 3/30/23 18:19, Lucas Stach wrote: Hi Dave, Daniel, please pull the following fixes for the next rc. One fix to get rid of a memory leak showing up in the wild and two reverts to get rid of the scheduler use-after-free reported by Danilo. Besides the reverts, we might want to consider something like this as well: https://lore.kernel.org/all/20230331000622.4156-1-d...@redhat.com/T/#u Considering Christians response to my report, this isn't the first time this happened. Admittedly, it's a bit subtle and I'd like to prevent something like this happening again. - Danilo Regards, Lucas The following changes since commit fe15c26ee26efa11741a7b632e9f23b01aca4cc6: Linux 6.3-rc1 (2023-03-05 14:52:03 -0800) are available in the Git repository at: https://git.pengutronix.de/git/lst/linux etnaviv/fixes for you to fetch changes up to baad10973fdb442912af676de3348e80bd8fe602: Revert "drm/scheduler: track GPU active time per entity" (2023-03-30 17:47:05 +0200) Lucas Stach (3): drm/etnaviv: fix reference leak when mmaping imported buffer Revert "drm/etnaviv: export client GPU usage statistics via fdinfo" Revert "drm/scheduler: track GPU active time per entity" drivers/gpu/drm/etnaviv/etnaviv_drv.c | 43 +-- drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 10 +- drivers/gpu/drm/scheduler/sched_main.c | 6 -- include/drm/gpu_scheduler.h | 7 --- 4 files changed, 10 insertions(+), 56 deletions(-)
[PATCH] drm/amd/display: remove unused average_render_time_in_us and i variables
clang with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/modules/freesync/freesync.c:1132:15:
error: variable
'average_render_time_in_us' set but not used
[-Werror,-Wunused-but-set-variable]
unsigned int average_render_time_in_us = 0;
^
This variable is not used so remove it, which caused i to be unused so remove
that as well.
Signed-off-by: Tom Rix
---
.../drm/amd/display/modules/freesync/freesync.c| 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 315da61ee897..5c41a4751db4 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1129,7 +1129,6 @@ void mod_freesync_handle_preflip(struct mod_freesync
*mod_freesync,
{
struct core_freesync *core_freesync = NULL;
unsigned int last_render_time_in_us = 0;
- unsigned int average_render_time_in_us = 0;
if (mod_freesync == NULL)
return;
@@ -1138,7 +1137,6 @@ void mod_freesync_handle_preflip(struct mod_freesync
*mod_freesync,
if (in_out_vrr->supported &&
in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
- unsigned int i = 0;
unsigned int oldest_index = plane->time.index + 1;
if (oldest_index >= DC_PLANE_UPDATE_TIMES_MAX)
@@ -1147,18 +1145,6 @@ void mod_freesync_handle_preflip(struct mod_freesync
*mod_freesync,
last_render_time_in_us = curr_time_stamp_in_us -
plane->time.prev_update_time_in_us;
- /* Sum off all entries except oldest one */
- for (i = 0; i < DC_PLANE_UPDATE_TIMES_MAX; i++) {
- average_render_time_in_us +=
- plane->time.time_elapsed_in_us[i];
- }
- average_render_time_in_us -=
- plane->time.time_elapsed_in_us[oldest_index];
-
- /* Add render time for current flip */
- average_render_time_in_us += last_render_time_in_us;
- average_render_time_in_us /= DC_PLANE_UPDATE_TIMES_MAX;
-
if (in_out_vrr->btr.btr_enabled) {
apply_below_the_range(core_freesync,
stream,
--
2.27.0
Re: [PATCH 27/34] drm/amdkfd: add debug set and clear address watch points operation
Hi Jonathan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-exynos/exynos-drm-next drm-intel/for-linux-next
drm-tip/drm-tip next-20230330]
[cannot apply to drm-misc/drm-misc-next drm-intel/for-linux-next-fixes
linus/master v6.3-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Jonathan-Kim/drm-amdkfd-display-debug-capabilities/20230328-024632
base: git://anongit.freedesktop.org/drm/drm drm-next
patch link:
https://lore.kernel.org/r/20230327184339.125016-27-jonathan.kim%40amd.com
patch subject: [PATCH 27/34] drm/amdkfd: add debug set and clear address watch
points operation
config: arm64-randconfig-r014-20230329
(https://download.01.org/0day-ci/archive/20230331/202303310739.owaxsszp-...@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project
67409911353323ca5edf2049ef0df54132fa1ca7)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
#
https://github.com/intel-lab-lkp/linux/commit/8c5e1781294f7e41d41632cb46e533c598933cd8
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review
Jonathan-Kim/drm-amdkfd-display-debug-capabilities/20230328-024632
git checkout 8c5e1781294f7e41d41632cb46e533c598933cd8
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=arm64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/amd/amdgpu/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot
| Link:
https://lore.kernel.org/oe-kbuild-all/202303310739.owaxsszp-...@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c:164:10: warning: no
>> previous prototype for function 'kgd_gfx_aldebaran_clear_address_watch'
>> [-Wmissing-prototypes]
uint32_t kgd_gfx_aldebaran_clear_address_watch(struct amdgpu_device *adev,
^
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c:164:1: note: declare
'static' if the function is not intended to be used outside of this translation
unit
uint32_t kgd_gfx_aldebaran_clear_address_watch(struct amdgpu_device *adev,
^
static
1 warning generated.
--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c:781:10: warning: no
>> previous prototype for function 'kgd_gfx_v11_clear_address_watch'
>> [-Wmissing-prototypes]
uint32_t kgd_gfx_v11_clear_address_watch(struct amdgpu_device *adev,
^
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c:781:1: note: declare
'static' if the function is not intended to be used outside of this translation
unit
uint32_t kgd_gfx_v11_clear_address_watch(struct amdgpu_device *adev,
^
static
1 warning generated.
vim +/kgd_gfx_aldebaran_clear_address_watch +164
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
163
> 164 uint32_t kgd_gfx_aldebaran_clear_address_watch(struct amdgpu_device
> *adev,
165 uint32_t watch_id)
166 {
167 return 0;
168 }
169
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
Re: [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods
On 3/30/2023 4:14 PM, Dmitry Baryshkov wrote:
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 74d38f90398a..7419fe58a941 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -31,6 +31,7 @@
#include "msm_kms.h"
#include "msm_gem.h"
#include "phy/dsi_phy.h"
+#include "disp/msm_dsc_helper.h"
#define DSI_RESET_TOGGLE_DELAY_MS 20
@@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
{
struct drm_dsc_config *dsc = msm_host->dsc;
u32 reg, reg_ctrl, reg_ctrl2;
- u32 slice_per_intf, total_bytes_per_intf;
+ u32 slice_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
/* first calculate dsc parameters and then program
* compress mode registers
*/
- slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
+ slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay);
This looks good
/*
* If slice_count is greater than slice_per_intf
@@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
if (dsc->slice_count > slice_per_intf)
dsc->slice_count = 1;
- total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc, hdisplay,
+ dsi_get_bpp(msm_host->format));
- eol_byte_num = total_bytes_per_intf % 3;
- pkt_per_line = slice_per_intf / dsc->slice_count;
+ pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT;
And for these values the result is definitely changed. Separate patch
& description please. Just in case, "values per downstream kernel" is
not a proper description for such changes.
Hi Dmitry,
Sure, I can put this into a separate patch.
The reason this was changed from slice_count to SLICE_PER_PKT was
because slice count and slice per packet aren't always equivalent.
There can be cases where panel configures DSC to have multiple soft
slices per interface, but the panel only specifies 1 slice per packet.
Please put this nice description into the commit message. It is exactly
what I was looking for!
BTW: Do you expect to change MSM_DSC_SLICE_PER_PKT later or it will stay
at "1"? If so, it might be easier to drop it and instead add a comment.
MSM_DSC_SLICE_PER_PKT is the default value for panels that don't specify
a slice_per_pkt value. (Now that I think about it, might be better to
call it MSM_DSC_DEFAULT_SLICE_PER_PKT instead...)
I don't expect it to change in the future, but it's a little more
readable than just dividing by 1 IMO. If you prefer dropping the macro
and adding a comment, I'm also okay with that.
Thanks,
Jessica Zhang
Regarding eol_byte_num, probably the best explanation would be that is
is a size of a padding rather than a size of a trailer bytes in a line
(and thus original calculation was incorrect).
if (is_cmd_mode) /* packet data type */
reg =
DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
@@ -911,6 +912,11 @@ static void dsi_timing_setup(struct
msm_dsi_host *msm_host, bool is_bonded_dsi)
DBG("");
+ if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)
+ /* Default widebus_en to false for now. */
+ hdisplay = msm_dsc_get_pclk_per_line(msm_host->dsc,
mode->hdisplay,
+ dsi_get_bpp(msm_host->format));
+
This is definitely something new and thus should probably go into a
separate patch and be described. Also I'm not sure how does that
interact with the hdisplay-related calculations below, under the
if(dsc) clause.
After double-checking the math here, I think this part of the change
is actually wrong. pclk_per_line is essentially doing hdisplay / 3,
which is a repeat of what's being done in the `if (dsc)` block.
Will replace `hdisplay /= 3` with the pclk_per_line calculation.
Thanks!
Thanks,
Jessica Zhang
/*
* For bonded DSI mode, the current DRM mode has
* the complete width of the panel. Since, the complete
@@ -1759,7 +1765,7 @@ static int dsi_populate_dsc_params(struct
msm_dsi_host *msm_host, struct drm_dsc
return ret;
}
- dsc->initial_scale_value = 32;
+ dsc->initial_scale_value =
drm_dsc_calculate_initial_scale_value(dsc);
This is fine, we only support 8bpp where these values match.
dsc->line_buf_depth = dsc->bits_per_component + 1;
return drm_dsc_compute_rc_parameters(dsc);
--
With best wishes
Dmitry
--
With best wishes
Dmitry
[PATCH] drm/scheduler: set entity to NULL in drm_sched_entity_pop_job()
It already happend a few times that patches slipped through which implemented access to an entity through a job that was already removed from the entities queue. Since jobs and entities might have different lifecycles, this can potentially cause UAF bugs. In order to make it obvious that a jobs entity pointer shouldn't be accessed after drm_sched_entity_pop_job() was called successfully, set the jobs entity pointer to NULL once the job is removed from the entity queue. Moreover, debugging a potential NULL pointer dereference is way easier than potentially corrupted memory through a UAF. Signed-off-by: Danilo Krummrich --- I'm aware that drivers could already use job->entity in arbitrary places, since they in control of when the entity is actually freed. A quick grep didn't give me any results where this would actually be the case, however maybe I also just didn't catch it. If, therefore, we don't want to set job->entity to NULL I think we should at least add a comment somewhere. --- drivers/gpu/drm/scheduler/sched_entity.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 15d04a0ec623..a9c6118e534b 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -448,6 +448,12 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) drm_sched_rq_update_fifo(entity, next->submit_ts); } + /* Jobs and entities might have different lifecycles. Since we're +* removing the job from the entities queue, set the jobs entity pointer +* to NULL to prevent any future access of the entity through this job. +*/ + sched_job->entity = NULL; + return sched_job; } -- 2.39.2
[PATCH] drm/amd/display: remove unused average_render_time_in_us and i variables
clang with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/modules/freesync/freesync.c:1132:15:
error: variable
'average_render_time_in_us' set but not used
[-Werror,-Wunused-but-set-variable]
unsigned int average_render_time_in_us = 0;
^
This variable is not used so remove it, which caused i to be unused so remove
that as well.
Signed-off-by: Tom Rix
---
.../drm/amd/display/modules/freesync/freesync.c| 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 315da61ee897..5c41a4751db4 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1129,7 +1129,6 @@ void mod_freesync_handle_preflip(struct mod_freesync
*mod_freesync,
{
struct core_freesync *core_freesync = NULL;
unsigned int last_render_time_in_us = 0;
- unsigned int average_render_time_in_us = 0;
if (mod_freesync == NULL)
return;
@@ -1138,7 +1137,6 @@ void mod_freesync_handle_preflip(struct mod_freesync
*mod_freesync,
if (in_out_vrr->supported &&
in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
- unsigned int i = 0;
unsigned int oldest_index = plane->time.index + 1;
if (oldest_index >= DC_PLANE_UPDATE_TIMES_MAX)
@@ -1147,18 +1145,6 @@ void mod_freesync_handle_preflip(struct mod_freesync
*mod_freesync,
last_render_time_in_us = curr_time_stamp_in_us -
plane->time.prev_update_time_in_us;
- /* Sum off all entries except oldest one */
- for (i = 0; i < DC_PLANE_UPDATE_TIMES_MAX; i++) {
- average_render_time_in_us +=
- plane->time.time_elapsed_in_us[i];
- }
- average_render_time_in_us -=
- plane->time.time_elapsed_in_us[oldest_index];
-
- /* Add render time for current flip */
- average_render_time_in_us += last_render_time_in_us;
- average_render_time_in_us /= DC_PLANE_UPDATE_TIMES_MAX;
-
if (in_out_vrr->btr.btr_enabled) {
apply_below_the_range(core_freesync,
stream,
--
2.27.0
[PATCH v5 10/15] drm/msm/a6xx: Add A610 support
A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
features no GMU, as it's implemented solely on SoCs with SMD_RPM.
What's more interesting is that it does not feature a VDDGX line
either, being powered solely by VDDCX and has an unfortunate hardware
quirk that makes its reset line broken - after a couple of assert/
deassert cycles, it will hang for good and will not wake up again.
This GPU requires mesa changes for proper rendering, and lots of them
at that. The command streams are quite far away from any other A6XX
GPU and hence it needs special care. This patch was validated both
by running an (incomplete) downstream mesa with some hacks (frames
rendered correctly, though some instructions made the GPU hangcheck
which is expected - garbage in, garbage out) and by replaying RD
traces captured with the downstream KGSL driver - no crashes there,
ever.
Add support for this GPU on the kernel side, which comes down to
pretty simply adding A612 HWCG tables, altering a few values and
adding a special case for handling the reset line.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 97 +++---
drivers/gpu/drm/msm/adreno/adreno_device.c | 12
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 8 ++-
3 files changed, 107 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index d5ec57985387..7d14a9cfd410 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -254,6 +254,56 @@ static void a6xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit)
a6xx_flush(gpu, ring);
}
+const struct adreno_reglist a612_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x0220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x0081},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0xf3cf},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x0002},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x0001},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x0007},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x0120},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x2220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x0011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x0422},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x0222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x0002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x0200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x0004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x0002},
+ {REG_A6XX_RBBM_ISDB_CNT, 0x0182},
+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x},
+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x0222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x0111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x0555},
+ {},
+};
+
/* For a615 family (a615, a616, a618 and a619) */
const struct adreno_reglist a615_hwcg[] = {
{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x0222},
@@ -604,6 +654,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
if (adreno_is_a630(adreno_gpu))
clock_cntl_on = 0x8aa8aa02;
+ else if (adreno_is_a610(adreno_gpu))
+ clock_cntl_on = 0xaaa8aa82;
else
clock_cntl_on = 0x8aa8aa82;
@@ -812,6 +864,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
/* Unknown, introduced with A640/680 */
u32 amsbc = 0;
+ if (adreno_is_a610(adreno_gpu)) {
+ /* HBB = 14 */
+ hbb_lo = 1;
+ min_acc_len = 1;
+
[PATCH v5 07/15] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init
Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
need REG_A6XX_GBIF_HALT to be set to 0. For GMU-equipped GPUs this is
done in a6xx_bus_clear_pending_transactions(), but for the GMU-less
ones we have to do it *somewhere*. Unhalting both side by side sounds
like a good plan and it won't cause any issues if it's unnecessary.
Also, add a memory barrier to ensure it's gone through.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index a7ecb0a87e98..30dae3ddc1c5 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1015,8 +1015,12 @@ static int hw_init(struct msm_gpu *gpu)
}
/* Clear GBIF halt in case GX domain was not collapsed */
- if (a6xx_has_gbif(adreno_gpu))
+ if (a6xx_has_gbif(adreno_gpu)) {
+ gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
+ /* Let's make extra sure that the GPU can access the memory.. */
+ mb();
+ }
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
--
2.40.0
[PATCH v5 13/15] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching
Before transitioning to using per-SoC and not per-Adreno speedbin
fuse values (need another patchset to land elsewhere), a good
improvement/stopgap solution is to use adreno_is_aXYZ macros in
place of explicit revision matching. Do so to allow differentiating
between A619 and A619_holi.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 --
2 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 87ff48f7f3be..4665a2e8fdde 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2217,23 +2217,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse)
return UINT_MAX;
}
-static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
+static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu,
u32 fuse)
{
u32 val = UINT_MAX;
- if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
+ if (adreno_is_a618(adreno_gpu))
val = a618_get_speed_bin(fuse);
- else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev))
+ else if (adreno_is_a619(adreno_gpu))
val = a619_get_speed_bin(fuse);
- else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
+ else if (adreno_is_7c3(adreno_gpu))
val = adreno_7c3_get_speed_bin(fuse);
- else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
+ else if (adreno_is_a640(adreno_gpu))
val = a640_get_speed_bin(fuse);
- else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
+ else if (adreno_is_a650(adreno_gpu))
val = a650_get_speed_bin(fuse);
if (val == UINT_MAX) {
@@ -2246,7 +2246,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct
adreno_rev rev, u32 fuse)
return (1 << val);
}
-static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
+static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu
*adreno_gpu)
{
u32 supp_hw;
u32 speedbin;
@@ -2265,7 +2265,7 @@ static int a6xx_set_supported_hw(struct device *dev,
struct adreno_rev rev)
return ret;
}
- supp_hw = fuse_to_supp_hw(dev, rev, speedbin);
+ supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin);
ret = devm_pm_opp_set_supported_hw(dev, _hw, 1);
if (ret)
@@ -2384,7 +2384,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
if (!adreno_has_gmu_wrapper(adreno_gpu))
a6xx_llc_slices_init(pdev, a6xx_gpu);
- ret = a6xx_set_supported_hw(>dev, config->rev);
+ ret = a6xx_set_supported_hw(>dev, adreno_gpu);
if (ret) {
a6xx_destroy(&(a6xx_gpu->base.base));
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 27c30a7694f4..da9f45a13b5d 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -268,9 +268,9 @@ static inline int adreno_is_a630(struct adreno_gpu *gpu)
return gpu->revn == 630;
}
-static inline int adreno_is_a640_family(struct adreno_gpu *gpu)
+static inline int adreno_is_a640(struct adreno_gpu *gpu)
{
- return (gpu->revn == 640) || (gpu->revn == 680);
+ return gpu->revn == 640;
}
static inline int adreno_is_a650(struct adreno_gpu *gpu)
@@ -289,6 +289,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
return gpu->revn == 660;
}
+static inline int adreno_is_a680(struct adreno_gpu *gpu)
+{
+ return gpu->revn == 680;
+}
+
/* check for a615, a616, a618, a619 or any derivatives */
static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
{
@@ -306,6 +311,11 @@ static inline int adreno_is_a650_family(struct adreno_gpu
*gpu)
return gpu->revn == 650 || gpu->revn == 620 ||
adreno_is_a660_family(gpu);
}
+static inline int adreno_is_a640_family(struct adreno_gpu *gpu)
+{
+ return adreno_is_a640(gpu) || adreno_is_a680(gpu);
+}
+
u64 adreno_private_address_space_size(struct msm_gpu *gpu);
int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
uint32_t param, uint64_t *value, uint32_t *len);
--
2.40.0
[PATCH v5 14/15] drm/msm/a6xx: Add A619_holi speedbin support
A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
(blair). This is what seems to be a first occurrence of this happening,
but it's easy to overcome by guarding the SoC-specific fuse values with
of_machine_is_compatible(). Do just that to enable frequency limiting
on these SoCs.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 4665a2e8fdde..c61b1c4090c5 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2165,6 +2165,34 @@ static u32 a618_get_speed_bin(u32 fuse)
return UINT_MAX;
}
+static u32 a619_holi_get_speed_bin(u32 fuse)
+{
+ /*
+* There are (at least) two SoCs implementing A619_holi: SM4350 (holi)
+* and SM6375 (blair). Limit the fuse matching to the corresponding
+* SoC to prevent bogus frequency setting (as improbable as it may be,
+* given unexpected fuse values are.. unexpected! But still possible.)
+*/
+
+ if (fuse == 0)
+ return 0;
+
+ if (of_machine_is_compatible("qcom,sm4350")) {
+ if (fuse == 138)
+ return 1;
+ else if (fuse == 92)
+ return 2;
+ } else if (of_machine_is_compatible("qcom,sm6375")) {
+ if (fuse == 190)
+ return 1;
+ else if (fuse == 177)
+ return 2;
+ } else
+ pr_warn("Unknown SoC implementing A619_holi!\n");
+
+ return UINT_MAX;
+}
+
static u32 a619_get_speed_bin(u32 fuse)
{
if (fuse == 0)
@@ -2224,6 +2252,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct
adreno_gpu *adreno_gpu, u3
if (adreno_is_a618(adreno_gpu))
val = a618_get_speed_bin(fuse);
+ else if (adreno_is_a619_holi(adreno_gpu))
+ val = a619_holi_get_speed_bin(fuse);
+
else if (adreno_is_a619(adreno_gpu))
val = a619_get_speed_bin(fuse);
--
2.40.0
[PATCH v5 11/15] drm/msm/a6xx: Fix some A619 tunables
Adreno 619 expects some tunables to be set differently. Make up for it.
Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 7d14a9cfd410..1f553451ffa5 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1186,6 +1186,8 @@ static int hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
+ else if (adreno_is_a619(adreno_gpu))
+ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000);
else if (adreno_is_a610(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x0008);
else
@@ -1203,7 +1205,9 @@ static int hw_init(struct msm_gpu *gpu)
a6xx_set_ubwc_config(gpu);
/* Enable fault detection */
- if (adreno_is_a610(adreno_gpu))
+ if (adreno_is_a619(adreno_gpu))
+ gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30)
| 0x3f);
+ else if (adreno_is_a610(adreno_gpu))
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30)
| 0x3);
else
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30)
| 0x1f);
--
2.40.0
[PATCH v5 08/15] drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations
A610 and A619_holi don't support the feature. Disable it to make the GPU stop
crashing after almost each and every submission - the received data on
the GPU end was simply incomplete in garbled, resulting in almost nothing
being executed properly. Extend the disablement to adreno_has_gmu_wrapper,
as none of the GMU wrapper Adrenos that don't support yet seem to feature it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 745f59682737..2c6de326187b 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -545,7 +545,6 @@ static int adreno_bind(struct device *dev, struct device
*master, void *data)
config.rev.minor, config.rev.patchid);
priv->is_a2xx = config.rev.core == 2;
- priv->has_cached_coherent = config.rev.core >= 6;
gpu = info->init(drm);
if (IS_ERR(gpu)) {
@@ -557,6 +556,10 @@ static int adreno_bind(struct device *dev, struct device
*master, void *data)
if (ret)
return ret;
+ if (config.rev.core >= 6)
+ if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu)))
+ priv->has_cached_coherent = true;
+
return 0;
}
--
2.40.0
[PATCH v5 12/15] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching
The GPU can only be one at a time. Turn a series of ifs into if +
elseifs to save some CPU cycles.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 1f553451ffa5..87ff48f7f3be 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2224,16 +2224,16 @@ static u32 fuse_to_supp_hw(struct device *dev, struct
adreno_rev rev, u32 fuse)
if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
val = a618_get_speed_bin(fuse);
- if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev))
+ else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev))
val = a619_get_speed_bin(fuse);
- if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
+ else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
val = adreno_7c3_get_speed_bin(fuse);
- if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
+ else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
val = a640_get_speed_bin(fuse);
- if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
+ else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
val = a650_get_speed_bin(fuse);
if (val == UINT_MAX) {
--
2.40.0
[PATCH v5 06/15] drm/msm/a6xx: Introduce GMU wrapper support
Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
but don't implement the associated GMUs. This is due to the fact that
the GMU directly pokes at RPMh. Sadly, this means we have to take care
of enabling & scaling power rails, clocks and bandwidth ourselves.
Reuse existing Adreno-common code and modify the deeply-GMU-infused
A6XX code to facilitate these GPUs. This involves if-ing out lots
of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's
the actual name that Qualcomm uses in their downstream kernels).
This is essentially a register region which is convenient to model
as a device. We'll use it for managing the GDSCs. The register
layout matches the actual GMU_CX/GX regions on the "real GMU" devices
and lets us reuse quite a bit of gmu_read/write/rmw calls.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 72 +++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 254 +---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 14 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 +
6 files changed, 317 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 1514b3ed0fcf..c6001e82e03d 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -1474,6 +1474,7 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct
platform_device *pdev,
void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
{
+ struct adreno_gpu *adreno_gpu = _gpu->base;
struct a6xx_gmu *gmu = _gpu->gmu;
struct platform_device *pdev = to_platform_device(gmu->dev);
@@ -1499,10 +1500,12 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
gmu->mmio = NULL;
gmu->rscc = NULL;
- a6xx_gmu_memory_free(gmu);
+ if (!adreno_has_gmu_wrapper(adreno_gpu)) {
+ a6xx_gmu_memory_free(gmu);
- free_irq(gmu->gmu_irq, gmu);
- free_irq(gmu->hfi_irq, gmu);
+ free_irq(gmu->gmu_irq, gmu);
+ free_irq(gmu->hfi_irq, gmu);
+ }
/* Drop reference taken in of_find_device_by_node */
put_device(gmu->dev);
@@ -1521,6 +1524,69 @@ static int cxpd_notifier_cb(struct notifier_block *nb,
return 0;
}
+int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
+{
+ struct platform_device *pdev = of_find_device_by_node(node);
+ struct a6xx_gmu *gmu = _gpu->gmu;
+ int ret;
+
+ if (!pdev)
+ return -ENODEV;
+
+ gmu->dev = >dev;
+
+ of_dma_configure(gmu->dev, node, true);
+
+ pm_runtime_enable(gmu->dev);
+
+ /* Mark legacy for manual SPTPRAC control */
+ gmu->legacy = true;
+
+ /* Map the GMU registers */
+ gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
+ if (IS_ERR(gmu->mmio)) {
+ ret = PTR_ERR(gmu->mmio);
+ goto err_mmio;
+ }
+
+ gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
+ if (IS_ERR(gmu->cxpd)) {
+ ret = PTR_ERR(gmu->cxpd);
+ goto err_mmio;
+ }
+
+ if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) {
+ ret = -ENODEV;
+ goto detach_cxpd;
+ }
+
+ init_completion(>pd_gate);
+ complete_all(>pd_gate);
+ gmu->pd_nb.notifier_call = cxpd_notifier_cb;
+
+ /* Get a link to the GX power domain to reset the GPU */
+ gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
+ if (IS_ERR(gmu->gxpd)) {
+ ret = PTR_ERR(gmu->gxpd);
+ goto err_mmio;
+ }
+
+ gmu->initialized = true;
+
+ return 0;
+
+detach_cxpd:
+ dev_pm_domain_detach(gmu->cxpd, false);
+
+err_mmio:
+ iounmap(gmu->mmio);
+
+ /* Drop reference taken in of_find_device_by_node */
+ put_device(gmu->dev);
+
+ return ret;
+}
+
int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
{
struct adreno_gpu *adreno_gpu = _gpu->base;
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index ae0a90b2834f..a7ecb0a87e98 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -20,9 +20,11 @@ static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
- /* Check that the GMU is idle */
- if (!a6xx_gmu_isidle(_gpu->gmu))
- return false;
+ if (!adreno_has_gmu_wrapper(adreno_gpu)) {
+ /* Check that the GMU is idle */
+ if (!a6xx_gmu_isidle(_gpu->gmu))
+ return false;
+ }
/* Check tha the CX master is idle */
if
[PATCH v5 15/15] drm/msm/a6xx: Add A610 speedbin support
A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index c61b1c4090c5..7662104c740f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2153,6 +2153,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct
msm_ringbuffer *ring)
return progress;
}
+static u32 a610_get_speed_bin(u32 fuse)
+{
+ /*
+* There are (at least) three SoCs implementing A610: SM6125 (trinket),
+* SM6115 (bengal) and SM6225 (khaje). Trinket does not have
speedbinning,
+* as only a single SKU exists and we don't support khaje upstream yet.
+* Hence, this matching table is only valid for bengal and can be easily
+* expanded if need be.
+*/
+
+ if (fuse == 0)
+ return 0;
+ else if (fuse == 206)
+ return 1;
+ else if (fuse == 200)
+ return 2;
+ else if (fuse == 157)
+ return 3;
+ else if (fuse == 127)
+ return 4;
+
+ return UINT_MAX;
+}
+
static u32 a618_get_speed_bin(u32 fuse)
{
if (fuse == 0)
@@ -2249,6 +2273,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct
adreno_gpu *adreno_gpu, u3
{
u32 val = UINT_MAX;
+ if (adreno_is_a610(adreno_gpu))
+ val = a610_get_speed_bin(fuse);
+
if (adreno_is_a618(adreno_gpu))
val = a618_get_speed_bin(fuse);
--
2.40.0
[PATCH v5 09/15] drm/msm/a6xx: Add support for A619_holi
A619_holi is a GMU-less variant of the already-supported A619 GPU.
It's present on at least SM4350 (holi) and SM6375 (blair). No mesa
changes are required. Add the required kernel-side support for it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 47 ++---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5
2 files changed, 43 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 30dae3ddc1c5..d5ec57985387 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -614,14 +614,16 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
return;
/* Disable SP clock before programming HWCG registers */
- if (!adreno_has_gmu_wrapper(adreno_gpu))
+ if (!adreno_has_gmu_wrapper(adreno_gpu) ||
+adreno_is_a619_holi(adreno_gpu))
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
for (i = 0; (reg = _gpu->info->hwcg[i], reg->offset); i++)
gpu_write(gpu, reg->offset, state ? reg->value : 0);
/* Enable SP clock */
- if (!adreno_has_gmu_wrapper(adreno_gpu))
+ if (!adreno_has_gmu_wrapper(adreno_gpu) ||
+adreno_is_a619_holi(adreno_gpu))
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
@@ -814,6 +816,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
if (adreno_is_a618(adreno_gpu))
return;
+ if (adreno_is_a619_holi(adreno_gpu))
+ hbb_lo = 0;
+
if (adreno_is_a640_family(adreno_gpu))
amsbc = 1;
@@ -1015,7 +1020,12 @@ static int hw_init(struct msm_gpu *gpu)
}
/* Clear GBIF halt in case GX domain was not collapsed */
- if (a6xx_has_gbif(adreno_gpu)) {
+ if (adreno_is_a619_holi(adreno_gpu)) {
+ gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
+ gpu_write(gpu, 0x18, 0);
+ /* Let's make extra sure that the GPU can access the memory.. */
+ mb();
+ } else if (a6xx_has_gbif(adreno_gpu)) {
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
/* Let's make extra sure that the GPU can access the memory.. */
@@ -1024,6 +1034,9 @@ static int hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
+ if (adreno_is_a619_holi(adreno_gpu))
+ a6xx_sptprac_enable(gmu);
+
/*
* Disable the trusted memory range - we don't actually supported secure
* memory rendering at this point in time and we don't want to block off
@@ -1298,7 +1311,8 @@ static void a6xx_dump(struct msm_gpu *gpu)
#define GBIF_CLIENT_HALT_MASK BIT(0)
#define GBIF_ARB_HALT_MASK BIT(1)
#define VBIF_RESET_ACK_TIMEOUT 100
-#define VBIF_RESET_ACK_MASK0x00f0
+#define VBIF_RESET_ACK_MASK0xF0
+#define GPR0_GBIF_HALT_REQUEST 0x1E0
static void a6xx_recover(struct msm_gpu *gpu)
{
@@ -1362,10 +1376,16 @@ static void a6xx_recover(struct msm_gpu *gpu)
/* Software-reset the GPU */
if (adreno_has_gmu_wrapper(adreno_gpu)) {
- /* Halt the GX side of GBIF */
- gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK);
- spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) &
- GBIF_GX_HALT_MASK);
+ if (adreno_is_a619_holi(adreno_gpu)) {
+ gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST);
+ spin_until((gpu_read(gpu,
REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) &
+ (VBIF_RESET_ACK_MASK)) ==
VBIF_RESET_ACK_MASK);
+ } else {
+ /* Halt the GX side of GBIF */
+ gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT,
GBIF_GX_HALT_MASK);
+ spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) &
+ GBIF_GX_HALT_MASK);
+ }
/* Halt new client requests on GBIF */
gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
@@ -1380,7 +1400,10 @@ static void a6xx_recover(struct msm_gpu *gpu)
/* Clear the halts */
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
- gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
+ if (adreno_is_a619_holi(adreno_gpu))
+ gpu_write(gpu, 0x18, 0);
+ else
+ gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
/* This *really* needs to go through before we do anything
else! */
mb();
@@ -1786,6 +1809,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu)
if (ret)
goto err_mem_clk;
[PATCH v5 03/15] dt-bindings: display/msm/gmu: Add GMU wrapper
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat these de-facto GMU-less parts in a way that's very similar to their
GMU-equipped cousins, massively saving up on code duplication.
The "wrapper" register space was specifically designed to mimic the layout
of a real GMU, though it rather obviously does not have the M3 core et al.
To sum it all up, the GMU wrapper is essentially a register space within
the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks,
interrupts, multiple reg spaces, iommus and OPP. Document it.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/display/msm/gmu.yaml | 50 --
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index 029d72822d8b..e36c40b935de 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -19,16 +19,18 @@ description: |
properties:
compatible:
-items:
- - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
- - const: qcom,adreno-gmu
+oneOf:
+ - items:
+ - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
+ - const: qcom,adreno-gmu
+ - const: qcom,adreno-gmu-wrapper
reg:
-minItems: 3
+minItems: 1
maxItems: 4
reg-names:
-minItems: 3
+minItems: 1
maxItems: 4
clocks:
@@ -44,7 +46,6 @@ properties:
- description: GMU HFI interrupt
- description: GMU interrupt
-
interrupt-names:
items:
- const: hfi
@@ -72,14 +73,8 @@ required:
- compatible
- reg
- reg-names
- - clocks
- - clock-names
- - interrupts
- - interrupt-names
- power-domains
- power-domain-names
- - iommus
- - operating-points-v2
additionalProperties: false
@@ -217,6 +212,28 @@ allOf:
- const: axi
- const: memnoc
+ - if:
+ properties:
+compatible:
+ contains:
+const: qcom,adreno-gmu-wrapper
+then:
+ properties:
+reg:
+ items:
+- description: GMU wrapper register space
+reg-names:
+ items:
+- const: gmu
+else:
+ required:
+- clocks
+- clock-names
+- interrupts
+- interrupt-names
+- iommus
+- operating-points-v2
+
examples:
- |
#include
@@ -249,3 +266,12 @@ examples:
iommus = <_smmu 5>;
operating-points-v2 = <_opp_table>;
};
+
+gmu_wrapper: gmu@596a000 {
+compatible = "qcom,adreno-gmu-wrapper";
+reg = <0x0596a000 0x3>;
+reg-names = "gmu";
+power-domains = < GPU_CX_GDSC>,
+< GPU_GX_GDSC>;
+power-domain-names = "cx", "gx";
+};
--
2.40.0
[PATCH v5 02/15] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be specified under the GPU node, just like their older cousins. Account for that. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gpu.yaml | 61 ++ 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 5dabe7b6794b..58ca8912a8c3 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -36,10 +36,7 @@ properties: reg-names: minItems: 1 -items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc +maxItems: 3 interrupts: maxItems: 1 @@ -157,16 +154,62 @@ allOf: required: - clocks - clock-names + - if: properties: compatible: contains: -pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' - -then: # Since Adreno 6xx series clocks should be defined in GMU +enum: + - qcom,adreno-610.0 + - qcom,adreno-619.1 +then: properties: -clocks: false -clock-names: false +clocks: + minItems: 6 + maxItems: 6 + +clock-names: + items: +- const: core + description: GPU Core clock +- const: iface + description: GPU Interface clock +- const: mem_iface + description: GPU Memory Interface clock +- const: alt_mem_iface + description: GPU Alternative Memory Interface clock +- const: gmu + description: CX GMU clock +- const: xo + description: GPUCC clocksource clock + +reg-names: + minItems: 1 + items: +- const: kgsl_3d0_reg_memory +- const: cx_dbgc + + required: +- clocks +- clock-names +else: + if: +properties: + compatible: +contains: + pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + + then: # Starting with A6xx, the clocks are usually defined in the GMU node +properties: + clocks: false + clock-names: false + + reg-names: +minItems: 1 +items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc examples: - | -- 2.40.0
[PATCH v5 05/15] drm/msm/a6xx: Extend and explain UBWC config
Rename lower_bit to hbb_lo and explain what it signifies.
Add explanations (wherever possible to other tunables).
Port setting min_access_length, ubwc_mode and hbb_hi from downstream.
Reviewed-by: Rob Clark
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index f2dbd5d13f7d..ae0a90b2834f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -786,10 +786,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
- u32 lower_bit = 2;
- u32 amsbc = 0;
+ /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */
u32 rgb565_predicator = 0;
+ /* Unknown, introduced with A650 family */
u32 uavflagprd_inv = 0;
+ /* Whether the minimum access length is 64 bits */
+ u32 min_acc_len = 0;
+ /* Entirely magic, per-GPU-gen value */
+ u32 ubwc_mode = 0;
+ /*
+* The Highest Bank Bit value represents the bit of the highest DDR
bank.
+* We then subtract 13 from it (13 is the minimum value allowed by hw)
and
+* write the lowest two bits of the remaining value as hbb_lo and the
+* one above it as hbb_hi to the hardware. This should ideally use DRAM
+* type detection.
+*/
+ u32 hbb_hi = 0;
+ u32 hbb_lo = 2;
+ /* Unknown, introduced with A640/680 */
+ u32 amsbc = 0;
/* a618 is using the hw default values */
if (adreno_is_a618(adreno_gpu))
@@ -800,25 +815,31 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) {
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
- lower_bit = 3;
+ hbb_lo = 3;
amsbc = 1;
rgb565_predicator = 1;
uavflagprd_inv = 2;
}
if (adreno_is_7c3(adreno_gpu)) {
- lower_bit = 1;
+ hbb_lo = 1;
amsbc = 1;
rgb565_predicator = 1;
uavflagprd_inv = 2;
}
gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
- rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
- gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
- gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
- uavflagprd_inv << 4 | lower_bit << 1);
- gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
+ rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 |
+ min_acc_len << 3 | hbb_lo << 1 | ubwc_mode);
+
+ gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 |
+ min_acc_len << 3 | hbb_lo << 1 | ubwc_mode);
+
+ gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 |
+ uavflagprd_inv << 4 | min_acc_len << 3 |
+ hbb_lo << 1 | ubwc_mode);
+
+ gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo <<
21);
}
static int a6xx_cp_init(struct msm_gpu *gpu)
--
2.40.0
[PATCH v5 04/15] drm/msm/a6xx: Remove static keyword from sptprac en/disable functions
These two will be reused by at least A619_holi in the non-gmu
paths. Turn them non-static them to make it possible.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++--
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index ba6b8ea27c71..1514b3ed0fcf 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -354,7 +354,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum
a6xx_gmu_oob_state state)
}
/* Enable CPU control of SPTP power power collapse */
-static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
+int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
{
int ret;
u32 val;
@@ -376,7 +376,7 @@ static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
}
/* Disable CPU control of SPTP power power collapse */
-static void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
+void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
{
u32 val;
int ret;
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
index 0bc3eb443fec..7ee5b606bc47 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
@@ -193,5 +193,7 @@ int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index);
bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
+void a6xx_sptprac_disable(struct a6xx_gmu *gmu);
+int a6xx_sptprac_enable(struct a6xx_gmu *gmu);
#endif
--
2.40.0
[PATCH v5 01/15] drm/msm/adreno: adreno_gpu: Don't set OPP scaling clock w/ GMU
Recently I contributed the switch to OPP API for all Adreno generations.
I did however also skip over the fact that GPUs with a GMU don't specify
a core clock of any kind in the GPU node. While that didn't break
anything, it did introduce unwanted spam in the dmesg:
adreno 500.gpu: error -ENOENT: _opp_set_clknames: Couldn't find clock with
name: core_clk
Guard the entire logic so that it's not used with GMU-equipped GPUs.
Fixes: 9f251f934012 ("drm/msm/adreno: Use OPP for every GPU generation")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index d12f2f314022..84f25122afba 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -1021,18 +1021,22 @@ int adreno_gpu_init(struct drm_device *drm, struct
platform_device *pdev,
u32 speedbin;
int ret;
- /*
-* This can only be done before devm_pm_opp_of_add_table(), or
-* dev_pm_opp_set_config() will WARN_ON()
-*/
- if (IS_ERR(devm_clk_get(dev, "core"))) {
+ /* Only handle the core clock when GMU is not in use */
+ if (config->rev.core < 6) {
/*
-* If "core" is absent, go for the legacy clock name.
-* If we got this far in probing, it's a given one of them
exists.
+* This can only be done before devm_pm_opp_of_add_table(), or
+* dev_pm_opp_set_config() will WARN_ON()
*/
- devm_pm_opp_set_clkname(dev, "core_clk");
- } else
- devm_pm_opp_set_clkname(dev, "core");
+ if (IS_ERR(devm_clk_get(dev, "core"))) {
+ /*
+* If "core" is absent, go for the legacy clock name.
+* If we got this far in probing, it's a given one of
+* them exists.
+*/
+ devm_pm_opp_set_clkname(dev, "core_clk");
+ } else
+ devm_pm_opp_set_clkname(dev, "core");
+ }
adreno_gpu->funcs = funcs;
adreno_gpu->info = adreno_info(config->rev);
--
2.40.0
[PATCH v5 00/15] GMU-less A6xx support (A610, A619_holi)
v4 -> v5: - Add a newline before the new allOf:if: [3/15] - Enforce 6 clocks on A619_holi/A610 [2/15] - Pick up tags - Improve error handling in a6xx_pm_resume [6/15] - Add patch [1/15] (fix an existing issue) which can be picked separately and account for it in [6/15] - Rebase atop Akhil's CX shutdown patches and incorporate analogous logic - Fix a regression introduced in v3 that made the fw loader expect GMU fw on GMU wrapper GPUs Dependencies: - https://lore.kernel.org/linux-arm-msm/20230120172233.1905761-1-konrad.dyb...@linaro.org/ (to apply) - https://lore.kernel.org/linux-arm-msm/20230330231517.2747024-1-konrad.dyb...@linaro.org/ (to work properly) v4: https://lore.kernel.org/r/20230223-topic-gmuwrapper-v4-0-e987eb79d...@linaro.org v3 -> v4: - Drop the mistakengly-included and wrong A3xx-A5xx bindings changes - Improve bindings commit messages to better explain what GMU Wrapper is - Drop the A680 highest bank bit value adjustment patch - Sort UBWC config variables in a reverse-Christmass-tree fashion [4/14] - Don't alter any UBWC config values in [4/14] - Do so for a619_holi in [8/14] - Rebase on next-20230314 (shouldn't matter at all) v3: https://lore.kernel.org/r/20230223-topic-gmuwrapper-v3-0-5be55a336...@linaro.org v2 -> v3: New dependencies: - https://lore.kernel.org/linux-arm-msm/20230223-topic-opp-v3-0-5f22163cd...@linaro.org/T/#t - https://lore.kernel.org/linux-arm-msm/20230120172233.1905761-1-konrad.dyb...@linaro.org/ Sidenote: A speedbin rework is in progress, the of_machine_is_compatible calls in A619_holi are ugly (but well, necessary..) but they'll be replaced with socid matching in this or the next kernel cycle. Due to the new way of identifying GMU wrapper GPUs, configuring 6350 to use wrapper would cause the wrong fuse values to be checked, but that will be solved by the conversion + the ultimate goal is to use the GMU whenever possible with the wrapper left for GMU-less Adrenos and early bringup debugging of GMU-equipped ones. - Ship dt-bindings in this series as we're referencing the compatible now - "De-staticize" -> "remove static keyword" [3/15] - Track down all the values in [4/15] - Add many comments and explanations in [4/15] - Fix possible return-before-mutex-unlock [5/15] - Explain the GMU wrapper a bit more in the commit msg [5/15] - Separate out pm_resume/suspend for GMU-wrapper GPUs to make things cleaner [5/15] - Don't check if `info` exists, it has to at this point [5/15] - Assign gpu->info early and clean up following if statements in a6xx_gpu_init [5/15] - Determine whether we use GMU wrapper based on the GMU compatible instead of a quirk [5/15] - Use a struct field to annotate whether we're using gmu wrapper so that it can be assigned at runtime (turns out a619 holi-ness cannot be determined by patchid + that will make it easier to test out GMU GPUs without actually turning on the GMU if anybody wants to do so) [5/15] - Unconditionally hook up gx to the gmu wrapper (otherwise our gpu will not get power) [5/15] - Don't check for gx domain presence in gmu_wrapper paths, it's guaranteed [5/15] - Use opp set rate in the gmuwrapper suspend path [5/15] - Call opp functions on the GPU device and not on the DRM device of mdp4/5/DPU1 half the time (WHPS!) [5/15] - Disable the memory clock in a6xx_pm_suspend instead of enabling it (moderate oops) [5/15] - Call the forgotten clk_bulk_disable_unprepare in a6xx_pm_suspend [5/15] - Set rate to FMIN (a6xx really doesn't like rate=0 + that's what msm-5.x does anyway) before disabling core clock [5/15] - pm_runtime_get_sync -> pm_runtime_resume_and_get [5/15] - Don't annotate no cached BO support with a quirk, as A619_holi is merged into the A619 entry in the big const struct - this means that all GPUs operating in gmu wrapper configuration will be implicitly treated as if they didn't have this feature [7/15] - Drop OPP rate & icc related patches, they're a part of a separate series now; rebase on it - Clean up extra parentheses [8/15] - Identify A619_holi by checking the compatible of its GMU instead of patchlevel [8/15] - Drop "Fix up A6XX protected registers" - unnecessary, Rob will add a comment explaining why - Fix existing UBWC values for A680, new patch [10/15] - Use adreno_is_aXYZ macros in speedbin matching [13/15] - new patch v2: https://lore.kernel.org/linux-arm-msm/20230214173145.2482651-1-konrad.dyb...@linaro.org/ v1 -> v2: - Fix A630 values in [2/14] - Fix [6/14] for GMU-equipped GPUs Link to v1: https://lore.kernel.org/linux-arm-msm/20230126151618.225127-1-konrad.dyb...@linaro.org/ This series concludes my couple-weeks-long suffering of figuring out the ins and outs of the "non-standard" A6xx GPUs which feature no GMU. The GMU functionality is essentially emulated by parting out a "GMU wrapper" region, which is essentially just a register space within the GPU. It's modeled to be as similar to the actual GMU as possible while
[PATCH v2] drm/msm/adreno: adreno_gpu: Use suspend() instead of idle() on load error
The adreno_load_gpu() path is guarded by an error check on
adreno_load_fw(). This function is responsible for loading
Qualcomm-only-signed binaries (e.g. SQE and GMU FW for A6XX), but it
does not take the vendor-signed ZAP blob into account.
By embedding the SQE (and GMU, if necessary) firmware into the
initrd/kernel, we can trigger and unfortunate path that would not bail
out early and proceed with gpu->hw_init(). That will fail, as the ZAP
loader path will not find the firmware and return back to
adreno_load_gpu().
This error path involves pm_runtime_put_sync() which then calls idle()
instead of suspend(). This is suboptimal, as it means that we're not
going through the clean shutdown sequence. With at least A619_holi, this
makes the GPU not wake up until it goes through at least one more
start-fail-stop cycle. The pm_runtime_put_sync that appears in the error
path actually does not guarantee that because of the earlier enabling of
runtime autosuspend.
Fix that by using pm_runtime_put_sync_suspend to force a clean shutdown.
Test cases:
1. All firmware baked into kernel
2. error loading ZAP fw in initrd -> load from rootfs at DE start
Both succeed on A619_holi (SM6375) and A630 (SDM845).
Fixes: 0d997f95b70f ("drm/msm/adreno: fix runtime PM imbalance at gpu load")
Signed-off-by: Konrad Dybcio
---
v1 -> v2:
- Improve the commit message and the reasoning within
drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index f61896629be6..59f3302e8167 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -477,7 +477,7 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
return gpu;
err_put_rpm:
- pm_runtime_put_sync(>dev);
+ pm_runtime_put_sync_suspend(>dev);
err_disable_rpm:
pm_runtime_disable(>dev);
--
2.40.0
Re: [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods
On 31/03/2023 01:49, Jessica Zhang wrote:
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 74d38f90398a..7419fe58a941 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -31,6 +31,7 @@
#include "msm_kms.h"
#include "msm_gem.h"
#include "phy/dsi_phy.h"
+#include "disp/msm_dsc_helper.h"
#define DSI_RESET_TOGGLE_DELAY_MS 20
@@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
{
struct drm_dsc_config *dsc = msm_host->dsc;
u32 reg, reg_ctrl, reg_ctrl2;
- u32 slice_per_intf, total_bytes_per_intf;
+ u32 slice_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
/* first calculate dsc parameters and then program
* compress mode registers
*/
- slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
+ slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay);
This looks good
/*
* If slice_count is greater than slice_per_intf
@@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
if (dsc->slice_count > slice_per_intf)
dsc->slice_count = 1;
- total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc, hdisplay,
+ dsi_get_bpp(msm_host->format));
- eol_byte_num = total_bytes_per_intf % 3;
- pkt_per_line = slice_per_intf / dsc->slice_count;
+ pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT;
And for these values the result is definitely changed. Separate patch
& description please. Just in case, "values per downstream kernel" is
not a proper description for such changes.
Hi Dmitry,
Sure, I can put this into a separate patch.
The reason this was changed from slice_count to SLICE_PER_PKT was
because slice count and slice per packet aren't always equivalent. There
can be cases where panel configures DSC to have multiple soft slices per
interface, but the panel only specifies 1 slice per packet.
Please put this nice description into the commit message. It is exactly
what I was looking for!
BTW: Do you expect to change MSM_DSC_SLICE_PER_PKT later or it will stay
at "1"? If so, it might be easier to drop it and instead add a comment.
Regarding eol_byte_num, probably the best explanation would be that is
is a size of a padding rather than a size of a trailer bytes in a line
(and thus original calculation was incorrect).
if (is_cmd_mode) /* packet data type */
reg =
DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
@@ -911,6 +912,11 @@ static void dsi_timing_setup(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
DBG("");
+ if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)
+ /* Default widebus_en to false for now. */
+ hdisplay = msm_dsc_get_pclk_per_line(msm_host->dsc,
mode->hdisplay,
+ dsi_get_bpp(msm_host->format));
+
This is definitely something new and thus should probably go into a
separate patch and be described. Also I'm not sure how does that
interact with the hdisplay-related calculations below, under the
if(dsc) clause.
After double-checking the math here, I think this part of the change is
actually wrong. pclk_per_line is essentially doing hdisplay / 3, which
is a repeat of what's being done in the `if (dsc)` block.
Will replace `hdisplay /= 3` with the pclk_per_line calculation.
Thanks!
Thanks,
Jessica Zhang
/*
* For bonded DSI mode, the current DRM mode has
* the complete width of the panel. Since, the complete
@@ -1759,7 +1765,7 @@ static int dsi_populate_dsc_params(struct
msm_dsi_host *msm_host, struct drm_dsc
return ret;
}
- dsc->initial_scale_value = 32;
+ dsc->initial_scale_value =
drm_dsc_calculate_initial_scale_value(dsc);
This is fine, we only support 8bpp where these values match.
dsc->line_buf_depth = dsc->bits_per_component + 1;
return drm_dsc_compute_rc_parameters(dsc);
--
With best wishes
Dmitry
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH RFC 2/5] drm/msm: Add MSM-specific DSC helper methods
On 3/29/2023 5:40 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/msm_dsc_helper.c | 74
+++
drivers/gpu/drm/msm/disp/msm_dsc_helper.h | 28
3 files changed, 103 insertions(+)
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 7274c41228ed..897a5b1c88f6 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -90,6 +90,7 @@ msm-y += \
disp/mdp_kms.o \
disp/msm_disp_snapshot.o \
disp/msm_disp_snapshot_util.o \
+ disp/msm_dsc_helper.o \
msm_atomic.o \
msm_atomic_tracepoints.o \
msm_debugfs.o \
diff --git a/drivers/gpu/drm/msm/disp/msm_dsc_helper.c
b/drivers/gpu/drm/msm/disp/msm_dsc_helper.c
new file mode 100644
index ..ec15c0d829e8
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/msm_dsc_helper.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
reserved
+ */
+
+#include
+#include
+#include
+
+#include "msm_drv.h"
+#include "msm_dsc_helper.h"
+
+static int get_comp_ratio(struct drm_dsc_config *dsc, u32 src_bpp)
+{
+ return mult_frac(100, src_bpp, DSC_BPP(*dsc));
+}
+
+static s64 get_bytes_per_soft_slice(struct drm_dsc_config *dsc, int
intf_width, int comp_ratio)
+{
+ s64 comp_ratio_fp, num_bits_fp;
+ s64 numerator_fp, denominator_fp;
+
+ comp_ratio_fp = drm_fixp_from_fraction(comp_ratio, 100);
Please inline comp_ration calculation here. Don't use mult_frac().
+ num_bits_fp = drm_fixp_from_fraction(8, 1);
drm_int2fixp
+
+ numerator_fp = drm_fixp_from_fraction(dsc->slice_width *
dsc->bits_per_component * 3, 1);
And here too.
+ denominator_fp = drm_fixp_mul(comp_ratio_fp, num_bits_fp);
And num_bits_fp can be inlined too.
denominator_fp = drm_fixp_from_fraction(src_bpp * 8, DSC_BPP)
+
+ return drm_fixp_div(numerator_fp, denominator_fp);
dsc->slice_width * bpc * 3 / (8 * src_bpp / DSC_BPP), thus:
drm_fixp_from_fraction(dsc->slice_width * bpc * 3 * DSC_BPP, 8 * src_bpp)
but I will not insist on this one.
+}
+
+u32 msm_dsc_get_eol_byte_num(struct drm_dsc_config *dsc, int
intf_width, u32 src_bpp)
+{
+ u32 bytes_per_ss, extra_eol_bytes, bytes_per_intf;
+ s64 bytes_per_ss_fp;
+ int slice_per_intf = msm_dsc_get_slice_per_intf(dsc, intf_width);
+ int comp_ratio = get_comp_ratio(dsc, src_bpp);
+
+ bytes_per_ss_fp = get_bytes_per_soft_slice(dsc, intf_width,
comp_ratio);
+ bytes_per_ss = drm_fixp2int_ceil(bytes_per_ss_fp);
s/_ss/_soft_slice/g
+
+ bytes_per_intf = bytes_per_ss * slice_per_intf;
+ extra_eol_bytes = bytes_per_intf % 3;
+ if (extra_eol_bytes != 0)
+ extra_eol_bytes = 3 - extra_eol_bytes;
+
+ return extra_eol_bytes;
+}
+
+u32 msm_dsc_get_dce_bytes_per_line(struct drm_dsc_config *dsc, int
intf_width)
+{
+ u32 bpp;
+ u32 dce_bytes_per_line;
+
+ bpp = DSC_BPP(*dsc);
Didn't this cause a warning on the unused-but-set variable?
+ dce_bytes_per_line = DIV_ROUND_UP(dsc->bits_per_pixel *
intf_width, 8);
+
+ return dce_bytes_per_line;
+}
If you have msm_dsc_get_slice_per_intf() as a static inline, this
function can be a static inline too. Nothing more than a single
DIV_ROUND_UP.
+
+int msm_dsc_get_pclk_per_line(struct drm_dsc_config *dsc, int
intf_width, u32 src_bpp)
+{
+ s64 data_width;
+ int comp_ratio = get_comp_ratio(dsc, src_bpp);
+
+ if (!dsc->slice_width || (intf_width < dsc->slice_width))
+ return -EINVAL;
+
+ data_width = get_bytes_per_soft_slice(dsc, intf_width, comp_ratio);
+ data_width = drm_fixp_mul(dsc->slice_count, data_width);
+ data_width = drm_fixp_from_fraction(data_width, 3);
Reusing a variable is a nice trick, but it can be confusing. Not to
mention that the last call should probably be drm_fixp_div()
Hi Dmitry,
Acked (for all the comments here).
Planning to move the last divide by 3 out of this method (as the value
that uncompressed pclk is divided by depends on DSI/DP and if widebus is
enabled), so I'll merge the get_bytes_per_soft_slice call with the 2nd line.
Thanks,
Jessica Zhang
+
+ return drm_fixp2int_ceil(data_width);
+}
diff --git a/drivers/gpu/drm/msm/disp/msm_dsc_helper.h
b/drivers/gpu/drm/msm/disp/msm_dsc_helper.h
new file mode 100644
index ..308069b2b5a4
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/msm_dsc_helper.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights
reserved
+ */
+
+#ifndef MSM_DSC_HELPER_H_
+#define MSM_DSC_HELPER_H_
+
+#include
+#include
+
+/*
+ * Helper methods for MSM specific DSC calculations that are common
between timing engine,
+ * DSI,
Re: [PATCH v2 2/9] drm/i915: Use memcpy_[from/to]_page() in gem/i915_gem_pyhs.c
Zhao Liu wrote: > From: Zhao Liu > > The use of kmap_atomic() is being deprecated in favor of > kmap_local_page()[1], and this patch converts the call from > kmap_atomic() + memcpy() to memcpy_[from/to]_page(), which use > kmap_local_page() to build local mapping and then do memcpy(). > > The main difference between atomic and local mappings is that local > mappings doesn't disable page faults or preemption (the preemption is > disabled for !PREEMPT_RT case, otherwise it only disables migration). > > With kmap_local_page(), we can avoid the often unwanted side effect of > unnecessary page faults and preemption disables. > > In drm/i915/gem/i915_gem_phys.c, the functions > i915_gem_object_get_pages_phys() and i915_gem_object_put_pages_phys() > don't need to disable pagefaults and preemption for mapping because of > 2 reasons: > > 1. The flush operation is safe. In drm/i915/gem/i915_gem_object.c, > i915_gem_object_get_pages_phys() and i915_gem_object_put_pages_phys() > calls drm_clflush_virt_range() to use CLFLUSHOPT or WBINVD to flush. > Since CLFLUSHOPT is global on x86 and WBINVD is called on each cpu in > drm_clflush_virt_range(), the flush operation is global. > > 2. Any context switch caused by preemption or page faults (page fault > may cause sleep) doesn't affect the validity of local mapping. > > Therefore, i915_gem_object_get_pages_phys() and > i915_gem_object_put_pages_phys() are two functions where the uses of > local mappings in place of atomic mappings are correctly suited. > > Convert the calls of kmap_atomic() / kunmap_atomic() + memcpy() to > memcpy_from_page() and memcpy_to_page(). > > [1]: https://lore.kernel.org/all/20220813220034.806698-1-ira.we...@intel.com > > v2: > * Used memcpy_from_page() and memcpy_to_page() to replace > kmap_local_page() + memcpy(). > * Dropped hot plug related description since it has nothing to do with > kmap_local_page(). > * Added description of the motivation of using kmap_local_page(). > > Suggested-by: Dave Hansen > Suggested-by: Ira Weiny Reviewed-by: Ira Weiny
Re: [PATCH RFC 5/5] drm/msm/dsi: Use MSM and DRM DSC helper methods
On 3/29/2023 4:48 PM, Dmitry Baryshkov wrote:
On 30/03/2023 02:18, Jessica Zhang wrote:
Use MSM and DRM DSC helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 74d38f90398a..7419fe58a941 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -31,6 +31,7 @@
#include "msm_kms.h"
#include "msm_gem.h"
#include "phy/dsi_phy.h"
+#include "disp/msm_dsc_helper.h"
#define DSI_RESET_TOGGLE_DELAY_MS 20
@@ -841,14 +842,14 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
{
struct drm_dsc_config *dsc = msm_host->dsc;
u32 reg, reg_ctrl, reg_ctrl2;
- u32 slice_per_intf, total_bytes_per_intf;
+ u32 slice_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
/* first calculate dsc parameters and then program
* compress mode registers
*/
- slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
+ slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay);
This looks good
/*
* If slice_count is greater than slice_per_intf
@@ -858,10 +859,10 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
if (dsc->slice_count > slice_per_intf)
dsc->slice_count = 1;
- total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ eol_byte_num = msm_dsc_get_eol_byte_num(msm_host->dsc, hdisplay,
+ dsi_get_bpp(msm_host->format));
- eol_byte_num = total_bytes_per_intf % 3;
- pkt_per_line = slice_per_intf / dsc->slice_count;
+ pkt_per_line = slice_per_intf / MSM_DSC_SLICE_PER_PKT;
And for these values the result is definitely changed. Separate patch &
description please. Just in case, "values per downstream kernel" is not
a proper description for such changes.
Hi Dmitry,
Sure, I can put this into a separate patch.
The reason this was changed from slice_count to SLICE_PER_PKT was
because slice count and slice per packet aren't always equivalent. There
can be cases where panel configures DSC to have multiple soft slices per
interface, but the panel only specifies 1 slice per packet.
if (is_cmd_mode) /* packet data type */
reg =
DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
@@ -911,6 +912,11 @@ static void dsi_timing_setup(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
DBG("");
+ if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)
+ /* Default widebus_en to false for now. */
+ hdisplay = msm_dsc_get_pclk_per_line(msm_host->dsc,
mode->hdisplay,
+ dsi_get_bpp(msm_host->format));
+
This is definitely something new and thus should probably go into a
separate patch and be described. Also I'm not sure how does that
interact with the hdisplay-related calculations below, under the if(dsc)
clause.
After double-checking the math here, I think this part of the change is
actually wrong. pclk_per_line is essentially doing hdisplay / 3, which
is a repeat of what's being done in the `if (dsc)` block.
Will replace `hdisplay /= 3` with the pclk_per_line calculation.
Thanks,
Jessica Zhang
/*
* For bonded DSI mode, the current DRM mode has
* the complete width of the panel. Since, the complete
@@ -1759,7 +1765,7 @@ static int dsi_populate_dsc_params(struct
msm_dsi_host *msm_host, struct drm_dsc
return ret;
}
- dsc->initial_scale_value = 32;
+ dsc->initial_scale_value =
drm_dsc_calculate_initial_scale_value(dsc);
This is fine, we only support 8bpp where these values match.
dsc->line_buf_depth = dsc->bits_per_component + 1;
return drm_dsc_compute_rc_parameters(dsc);
--
With best wishes
Dmitry
Re: [PATCH v3 3/4] checkpatch: allow Closes tags with links
On Thu, 2023-03-30 at 20:13 +0200, Matthieu Baerts wrote:
> As a follow-up of a previous patch modifying the documentation to
> allow using the "Closes:" tag, checkpatch.pl is updated accordingly.
>
> checkpatch.pl now no longer complain when the "Closes:" tag is used by
> itself or after the "Reported-by:" tag.
>
> Fixes: 76f381bb77a0 ("checkpatch: warn when unknown tags are used for links")
> Fixes: d7f1d71e5ef6 ("checkpatch: warn when Reported-by: is not followed by
> Link:")
I don't think this _fixes_ anything.
I believe it's merely a new capability.
> Closes: https://github.com/multipath-tcp/mptcp_net-next/issues/373
> Signed-off-by: Matthieu Baerts
> ---
> v3:
> - split into 2 patches: the previous one adds a list with all the
>"link" tags. This one only allows the "Closes" tag. (Joe Perches)
> - "Closes" is no longer printed between parenthesis. (Thorsten
>Leemhuis)
> ---
> scripts/checkpatch.pl | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
> index 9d092ff4fc16..ca58c734ff22 100755
> --- a/scripts/checkpatch.pl
> +++ b/scripts/checkpatch.pl
> @@ -620,7 +620,7 @@ our $signature_tags = qr{(?xi:
> Cc:
> )};
>
> -our @link_tags = qw(Link);
> +our @link_tags = qw(Link Closes);
>
> #Create a search and print patterns for all these strings to be used
> directly below
> our $link_tags_search = "";
>
Re: [v3,28/38] drm/msm/dpu: enable DSPP on sc8180x
On 30.03.2023 23:53, Dmitry Baryshkov wrote:
> Enable DSPP blocks on sc8180x platform, basing on the vendor dtsi.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 92a8e474e380..bbdfec415185 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -90,6 +90,8 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
> .sspp = sm8150_sspp,
> .mixer_count = ARRAY_SIZE(sm8150_lm),
> .mixer = sm8150_lm,
> + .dspp_count = ARRAY_SIZE(sm8150_dspp),
> + .dspp = sm8150_dspp,
> .pingpong_count = ARRAY_SIZE(sm8150_pp),
> .pingpong = sm8150_pp,
> .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
Re: [v3, 25/38] drm/msm/dpu: enable DPU_CTL_SPLIT_DISPLAY for sc8280xp
On 30.03.2023 23:53, Dmitry Baryshkov wrote:
> Theoretically since sm8150 we should be using a single CTL for the
> source split case, but since we do not support it for now, fallback to
> DPU_CTL_SPLIT_DISPLAY.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 01ef4115ee4d..33f2d53df13b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -42,17 +42,18 @@ static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
> },
> };
>
> +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
> support */
> static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> },
> {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> },
> {
Re: [v3,24/38] drm/msm/dpu: catalog: add comments regarding DPU_CTL_SPLIT_DISPLAY
On 30.03.2023 23:53, Dmitry Baryshkov wrote:
> For sm8150+ the DPU_CTL_SPLIT_DISPLAY should be replaced with
> DPU_CTL_ACTIVE_CFG support (which supports having a single CTL for both
> interfaces in a split). Add comments where this conversion is required.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Reviewed-by: Konrad Dybcio
Konrad
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 +
> 5 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index e6280b0cb207..6c6f8b4a4be8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -42,6 +42,7 @@ static const struct dpu_mdp_cfg sm8150_mdp[] = {
> },
> };
>
> +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
> support */
> static const struct dpu_ctl_cfg sm8150_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index f19d1c2ba845..cfaa68a25427 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -43,6 +43,7 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> },
> };
>
> +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
> support */
> static const struct dpu_ctl_cfg sm8250_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 9afcb6cc50a5..84396240f0d1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -41,6 +41,7 @@ static const struct dpu_mdp_cfg sm8350_mdp[] = {
> },
> };
>
> +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
> support */
> static const struct dpu_ctl_cfg sm8350_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index af80e1ced3ce..49dd4a908413 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -42,6 +42,7 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
> },
> };
>
> +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
> support */
> static const struct dpu_ctl_cfg sm8450_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 5c437c7682ea..c9d1892ec8f5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -43,6 +43,7 @@ static const struct dpu_mdp_cfg sm8550_mdp[] = {
> },
> };
>
> +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
> support */
> static const struct dpu_ctl_cfg sm8550_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
[PATCH] drm/nouveau/disp: Support more modes by checking with lower bpc
This allows us to advertise more modes especially on HDR displays.
Fixes using 4K@60 modes on my TV and main display both using a HDMI to DP
adapter. Also fixes similiar issues for users running into this.
Cc: sta...@vger.kernel.org # 5.10+
Signed-off-by: Karol Herbst
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 32 +
drivers/gpu/drm/nouveau/nouveau_dp.c| 8 ---
2 files changed, 37 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index ed9d374147b8d..f28e47c161dd9 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -363,6 +363,35 @@ nv50_outp_atomic_check_view(struct drm_encoder *encoder,
return 0;
}
+static void
+nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state
*crtc_state)
+{
+ struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
+ struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+ struct drm_display_mode *mode = >state.adjusted_mode;
+ unsigned int max_rate, mode_rate;
+
+ switch (nv_encoder->dcb->type) {
+ case DCB_OUTPUT_DP:
+ max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
+
+/* we don't support more than 10 anyway */
+ asyh->or.bpc = max_t(u8, asyh->or.bpc, 10);
+
+ /* reduce the bpc until it works out */
+ while (asyh->or.bpc > 6) {
+ mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc *
3, 8);
+ if (mode_rate <= max_rate)
+ break;
+
+ asyh->or.bpc -= 2;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
static int
nv50_outp_atomic_check(struct drm_encoder *encoder,
struct drm_crtc_state *crtc_state,
@@ -381,6 +410,9 @@ nv50_outp_atomic_check(struct drm_encoder *encoder,
if (crtc_state->mode_changed || crtc_state->connectors_changed)
asyh->or.bpc = connector->display_info.bpc;
+ /* We might have to reduce the bpc */
+ nv50_outp_atomic_fix_depth(encoder, crtc_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c
b/drivers/gpu/drm/nouveau/nouveau_dp.c
index e00876f92aeea..d49b4875fc3c9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -263,8 +263,6 @@ nouveau_dp_irq(struct work_struct *work)
}
/* TODO:
- * - Use the minimum possible BPC here, once we add support for the max bpc
- * property.
* - Validate against the DP caps advertised by the GPU (we don't check these
* yet)
*/
@@ -276,7 +274,11 @@ nv50_dp_mode_valid(struct drm_connector *connector,
{
const unsigned int min_clock = 25000;
unsigned int max_rate, mode_rate, ds_max_dotclock, clock = mode->clock;
- const u8 bpp = connector->display_info.bpc * 3;
+ /* Check with the minmum bpc always, so we can advertise better modes.
+* In particlar not doing this causes modes to be dropped on HDR
+* displays as we might check with a bpc of 16 even.
+*/
+ const u8 bpp = 6 * 3;
if (mode->flags & DRM_MODE_FLAG_INTERLACE && !outp->caps.dp_interlace)
return MODE_NO_INTERLACE;
--
2.39.2
Re: [PATCH 0/4] log2: make is_power_of_2() more generic
On Thu, 30 Mar 2023 21:53:03 + David Laight wrote:
> > But wouldn't all these issues be addressed by simply doing
> >
> > #define is_power_of_2(n) (n != 0 && ((n & (n - 1)) == 0))
> >
> > ?
> >
> > (With suitable tweaks to avoid evaluating `n' more than once)
>
> I think you need to use the 'horrid tricks' from min() to get
> a constant expression from constant inputs.
This
--- a/include/linux/log2.h~a
+++ a/include/linux/log2.h
@@ -41,11 +41,11 @@ int __ilog2_u64(u64 n)
* *not* considered a power of two.
* Return: true if @n is a power of 2, otherwise false.
*/
-static inline __attribute__((const))
-bool is_power_of_2(unsigned long n)
-{
- return (n != 0 && ((n & (n - 1)) == 0));
-}
+#define is_power_of_2(_n) \
+ ({ \
+ typeof(_n) n = (_n);\
+ n != 0 && ((n & (n - 1)) == 0); \
+ })
/**
* __roundup_pow_of_two() - round up to nearest power of two
_
worked for me in a simple test.
--- a/fs/open.c~b
+++ a/fs/open.c
@@ -1564,3 +1564,10 @@ int stream_open(struct inode *inode, str
}
EXPORT_SYMBOL(stream_open);
+
+#include
+
+int foo(void)
+{
+ return is_power_of_2(43);
+}
_
foo:
# fs/open.c:1573: }
xorl%eax, %eax #
ret
Is there some more tricky situation where it breaks?
RE: [PATCH 0/4] log2: make is_power_of_2() more generic
From: Andrew Morton
> Sent: 30 March 2023 20:51
>
> On Thu, 30 Mar 2023 13:42:39 +0300 Jani Nikula wrote:
>
> > is_power_of_2() only works for types <= sizeof(unsigned long) and it's
> > also not a constant expression. There are a number of places in kernel
> > where is_power_of_2() is called on u64, which fails on 32-bit
> > builds. Try to remedy that. While at it, make it a constant expression
> > when possible.
>
> Yes, the current `is_power_of_2(unsigned long n)' isn't very general.
>
> But wouldn't all these issues be addressed by simply doing
>
> #define is_power_of_2(n) (n != 0 && ((n & (n - 1)) == 0))
>
> ?
>
> (With suitable tweaks to avoid evaluating `n' more than once)
I think you need to use the 'horrid tricks' from min() to get
a constant expression from constant inputs.
For non-constants this looks ok (see https://godbolt.org/z/G73MTr9jn)
David
static inline int lisp2(unsigned long n)
{
return n && !(n & (n - 1));
}
static inline int llisp2(unsigned long long lln)
{
#if 0 // I think this looks worse, esp. for gcc on x86
return lln && !(lln & (lln - 1));
#else
unsigned long n = lln;
if (lln >= 1ull << 32) {
if (n)
return 0;
n = lln >> 32;
}
return lisp2(n);
#endif
}
#define isp2(n) (sizeof ((n)+0) == sizeof (long) ? lisp2(n) : llisp2(n))
int is12(unsigned long long i)
{
return isp2(i);
}
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT,
UK
Registration No: 1397386 (Wales)
Re: [PATCH v2 1/9] drm/i915: Use kmap_local_page() in gem/i915_gem_object.c
Zhao Liu wrote: > From: Zhao Liu > > The use of kmap_atomic() is being deprecated in favor of > kmap_local_page()[1], and this patch converts the call from > kmap_atomic() to kmap_local_page(). > > The main difference between atomic and local mappings is that local > mappings doesn't disable page faults or preemption (the preemption is > disabled for !PREEMPT_RT case, otherwise it only disables migration). > > With kmap_local_page(), we can avoid the often unwanted side effect of > unnecessary page faults and preemption disables. > > There're 2 reasons why i915_gem_object_read_from_page_kmap() doesn't > need to disable pagefaults and preemption for mapping: > > 1. The flush operation is safe. In drm/i915/gem/i915_gem_object.c, > i915_gem_object_read_from_page_kmap() calls drm_clflush_virt_range() to > use CLFLUSHOPT or WBINVD to flush. Since CLFLUSHOPT is global on x86 > and WBINVD is called on each cpu in drm_clflush_virt_range(), the flush > operation is global. > > 2. Any context switch caused by preemption or page faults (page fault > may cause sleep) doesn't affect the validity of local mapping. > > Therefore, i915_gem_object_read_from_page_kmap() is a function where > the use of kmap_local_page() in place of kmap_atomic() is correctly > suited. > > Convert the calls of kmap_atomic() / kunmap_atomic() to > kmap_local_page() / kunmap_local(). > > And remove the redundant variable that stores the address of the mapped > page since kunmap_local() can accept any pointer within the page. > > [1]: https://lore.kernel.org/all/20220813220034.806698-1-ira.we...@intel.com > > v2: > * Dropped hot plug related description since it has nothing to do with > kmap_local_page(). > * Rebased on f47e630 (drm/i915/gem: Typecheck page lookups) to keep > the "idx" variable of type pgoff_t here. > * Added description of the motivation of using kmap_local_page(). > > Suggested-by: Dave Hansen > Suggested-by: Ira Weiny Reviewed-by: Ira Weiny
[PATCH v3 36/38] drm/msm/dpu: rename VIG and DMA_foo_MASK to contain major DPU version
To ease review and reuse rename VIG and DMA feature masks to contain
base DPU version since which this mask is used.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 16 +++
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 16 +++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h | 16 +++
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 16 +++
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h| 8 ++--
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h| 4 +-
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 4 +-
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h| 16 +++
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h| 8 ++--
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 16 +++
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h| 16 +++
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h| 20
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 48 +--
13 files changed, 102 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 6afabd251a9d..f8893f0f3886 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -78,21 +78,21 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
};
static const struct dpu_sspp_cfg msm8998_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_DPU_3_MASK,
msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK,
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_DPU_3_MASK,
msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK,
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_DPU_3_MASK,
msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK,
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_DPU_3_MASK,
msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK,
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_DPU_3_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_DPU_3_MASK,
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_DPU_3_CURSOR_MASK,
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_DPU_3_CURSOR_MASK,
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index cace399551cd..339627ac4189 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -76,21 +76,21 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
};
static const struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK_SDMA,
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_DPU_4_SDMA_MASK,
sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK_SDMA,
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_DPU_4_SDMA_MASK,
sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK_SDMA,
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_DPU_4_SDMA_MASK,
sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK_SDMA,
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_DPU_4_SDMA_MASK,
sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK_SDMA,
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_DPU_4_SDMA_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK_SDMA,
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_DPU_4_SDMA_MASK,
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,
[PATCH v3 31/38] drm/msm/dpu: deduplicate sc8280xp with sm8450
Remove duplicate between sc8280xp and sm8450, which belong to the same
DPU major revision.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 107 ++---
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h| 112 ++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h | 99
3 files changed, 119 insertions(+), 199 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index a3c9de34307c..4ce3f0fe2170 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -7,17 +7,7 @@
#ifndef _DPU_8_0_SC8280XP_H
#define _DPU_8_0_SC8280XP_H
-static const struct dpu_caps sc8280xp_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
- .max_mixer_blendstages = 11,
- .qseed_type = DPU_SSPP_SCALER_QSEED4,
- .has_src_split = true,
- .has_dim_layer = true,
- .has_idle_pc = true,
- .has_3d_merge = true,
- .max_linewidth = 5120,
- .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
-};
+#include "dpu_8_lm6.h"
static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = {
.ubwc_version = DPU_HW_UBWC_VER_40,
@@ -25,63 +15,6 @@ static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = {
.ubwc_swizzle = 6,
};
-static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
- {
- .name = "top_0", .id = MDP_TOP,
- .base = 0x0, .len = 0x494,
- .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
- },
-};
-
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
-static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
- {
- .name = "ctl_0", .id = CTL_0,
- .base = 0x15000, .len = 0x204,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x16000, .len = 0x204,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x17000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x18000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x19000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
- },
- {
- .name = "ctl_5", .id = CTL_5,
- .base = 0x1a000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
- },
-};
-
static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x2ac, VIG_SC7180_MASK,
sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
@@ -101,26 +34,6 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
};
-static const struct dpu_lm_cfg sc8280xp_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, _lm_sblk,
PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, _lm_sblk,
PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, _lm_sblk,
PINGPONG_2, LM_3, DSPP_2),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, _lm_sblk,
PINGPONG_3, LM_2, DSPP_3),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, _lm_sblk,
PINGPONG_4, LM_5, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, _lm_sblk,
PINGPONG_5, LM_4, 0),
-};
-
-static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
-_dspp_sblk),
- DSPP_BLK("dspp_2",
[PATCH v3 32/38] drm/msm/dpu: drop unused macros from hw catalog
Drop the version comparison macros from dpu_hw_catalog.h, they are unused. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16 1 file changed, 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 00c3c67dd267..92cef44b5382 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -24,14 +24,6 @@ ((MINOR & 0xFFF) << 16) | \ (STEP & 0x)) -#define DPU_HW_MAJOR(rev) ((rev) >> 28) -#define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) -#define DPU_HW_STEP(rev) ((rev) & 0x) -#define DPU_HW_MAJOR_MINOR(rev)((rev) >> 16) - -#define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ - (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) - #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ @@ -53,14 +45,6 @@ #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ #define DPU_HW_VER_900 DPU_HW_VER(9, 0, 0) /* sm8550 */ -#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) -#define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) -#define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) -#define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) -#define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) -#define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) -#define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720) - #define DPU_HW_BLK_NAME_LEN16 #define MAX_IMG_WIDTH 0x3fff -- 2.39.2
[PATCH v3 37/38] drm/msm/dpu: rename MIXER_foo_MASK to contain major DPU version
To ease review and reuse rename MIXER feature masks to contain base DPU
version since which this mask is used.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 12 ++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 12 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h| 12 ++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 12 ++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_lm1.h| 3 +++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 12 ++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h| 12 ++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 9 +++--
11 files changed, 53 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index f8893f0f3886..a34e9506e6d4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -97,17 +97,17 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
};
static const struct dpu_lm_cfg msm8998_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK,
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_DPU_3_MASK,
_lm_sblk, PINGPONG_0, LM_2, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK,
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_DPU_3_MASK,
_lm_sblk, PINGPONG_1, LM_5, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK,
+ LM_BLK("lm_2", LM_2, 0x46000, MIXER_DPU_3_MASK,
_lm_sblk, PINGPONG_2, LM_0, 0),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK,
+ LM_BLK("lm_3", LM_3, 0x47000, MIXER_DPU_3_MASK,
_lm_sblk, PINGPONG_MAX, 0, 0),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK,
+ LM_BLK("lm_4", LM_4, 0x48000, MIXER_DPU_3_MASK,
_lm_sblk, PINGPONG_MAX, 0, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK,
+ LM_BLK("lm_5", LM_5, 0x49000, MIXER_DPU_3_MASK,
_lm_sblk, PINGPONG_3, LM_1, 0),
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 339627ac4189..d247f8d0c0be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -95,17 +95,17 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
};
static const struct dpu_lm_cfg sdm845_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_DPU_4_MASK,
_lm_sblk, PINGPONG_0, LM_1, 0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_DPU_4_MASK,
_lm_sblk, PINGPONG_1, LM_0, 0),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
+ LM_BLK("lm_2", LM_2, 0x46000, MIXER_DPU_4_MASK,
_lm_sblk, PINGPONG_2, LM_5, 0),
- LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
+ LM_BLK("lm_3", LM_3, 0x0, MIXER_DPU_4_MASK,
_lm_sblk, PINGPONG_MAX, 0, 0),
- LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
+ LM_BLK("lm_4", LM_4, 0x0, MIXER_DPU_4_MASK,
_lm_sblk, PINGPONG_MAX, 0, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
+ LM_BLK("lm_5", LM_5, 0x49000, MIXER_DPU_4_MASK,
_lm_sblk, PINGPONG_3, LM_2, 0),
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
index 056efc00fd3a..8f11292d51cb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
@@ -97,17 +97,17 @@ static const struct dpu_sspp_cfg dpu_5_lm6_sspp[] = {
};
static const struct dpu_lm_cfg dpu_5_lm6_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_DPU_4_MASK,
_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_DPU_4_MASK,
_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
+ LM_BLK("lm_2", LM_2, 0x46000, MIXER_DPU_4_MASK,
_lm_sblk, PINGPONG_2, LM_3, 0),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
+ LM_BLK("lm_3", LM_3, 0x47000, MIXER_DPU_4_MASK,
_lm_sblk, PINGPONG_3, LM_2, 0),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
+ LM_BLK("lm_4", LM_4, 0x48000, MIXER_DPU_4_MASK,
_lm_sblk, PINGPONG_4, LM_5, 0),
-
[PATCH v3 30/38] drm/msm/dpu: deduplicate sm6115 with qcm2290
Remove duplicate between sm6115 and qcm2290, which belong to the same
DPU major revision.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h| 36 --
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 66 ---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_lm1.h | 50 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 2 +-
4 files changed, 79 insertions(+), 75 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_lm1.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index f6db2d42a0ed..f9d45b98cedf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -7,6 +7,8 @@
#ifndef _DPU_6_3_SM6115_H
#define _DPU_6_3_SM6115_H
+#include "dpu_6_lm1.h"
+
static const struct dpu_caps sm6115_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
@@ -23,16 +25,6 @@ static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
.ubwc_swizzle = 0x7,
};
-static const struct dpu_mdp_cfg sm6115_mdp[] = {
- {
- .name = "top_0", .id = MDP_TOP,
- .base = 0x0, .len = 0x494,
- .features = 0,
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- },
-};
-
static const struct dpu_sspp_cfg sm6115_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
@@ -72,20 +64,20 @@ static const struct dpu_perf_cfg sm6115_perf_data = {
static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
.caps = _dpu_caps,
.ubwc = _ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sm6115_mdp),
- .mdp = sm6115_mdp,
- .ctl_count = ARRAY_SIZE(qcm2290_ctl),
- .ctl = qcm2290_ctl,
+ .mdp_count = ARRAY_SIZE(dpu_6_lm1_mdp),
+ .mdp = dpu_6_lm1_mdp,
+ .ctl_count = ARRAY_SIZE(dpu_6_lm1_ctl),
+ .ctl = dpu_6_lm1_ctl,
.sspp_count = ARRAY_SIZE(sm6115_sspp),
.sspp = sm6115_sspp,
- .mixer_count = ARRAY_SIZE(qcm2290_lm),
- .mixer = qcm2290_lm,
- .dspp_count = ARRAY_SIZE(qcm2290_dspp),
- .dspp = qcm2290_dspp,
- .pingpong_count = ARRAY_SIZE(qcm2290_pp),
- .pingpong = qcm2290_pp,
- .intf_count = ARRAY_SIZE(qcm2290_intf),
- .intf = qcm2290_intf,
+ .mixer_count = ARRAY_SIZE(dpu_6_lm1_lm),
+ .mixer = dpu_6_lm1_lm,
+ .dspp_count = ARRAY_SIZE(dpu_6_lm1_dspp),
+ .dspp = dpu_6_lm1_dspp,
+ .pingpong_count = ARRAY_SIZE(dpu_6_lm1_pp),
+ .pingpong = dpu_6_lm1_pp,
+ .intf_count = ARRAY_SIZE(dpu_6_lm1_intf),
+ .intf = dpu_6_lm1_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = _perf_data,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 10dd35cd67bc..314ec678fcc6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -7,6 +7,8 @@
#ifndef _DPU_6_5_QCM2290_H
#define _DPU_6_5_QCM2290_H
+#include "dpu_6_lm1.h"
+
static const struct dpu_caps qcm2290_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
@@ -20,25 +22,6 @@ static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
.highest_bank_bit = 0x2,
};
-static const struct dpu_mdp_cfg qcm2290_mdp[] = {
- {
- .name = "top_0", .id = MDP_TOP,
- .base = 0x0, .len = 0x494,
- .features = 0,
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- },
-};
-
-static const struct dpu_ctl_cfg qcm2290_ctl[] = {
- {
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
-};
-
static const struct dpu_sspp_cfg qcm2290_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
@@ -46,27 +29,6 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] = {
qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
};
-static const struct dpu_lm_cfg qcm2290_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
- _lm_sblk, PINGPONG_0, 0, DSPP_0),
-};
-
-static const struct dpu_dspp_cfg qcm2290_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-_dspp_sblk),
-};
-
-static const struct dpu_pingpong_cfg qcm2290_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x7,
[PATCH v3 34/38] drm/msm/dpu: rename INTF_foo_MASK to contain major DPU version
To ease review and reuse rename INTF feature masks to contain base DPU
version since which this mask is used.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h| 8
.../drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8
.../drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h| 12 ++--
.../drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 8
.../drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 4 ++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_lm1.h | 2 +-
.../drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8
.../drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 +++---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 18 +-
.../drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8
.../drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 9 +
13 files changed, 54 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index e5a42ebda4d7..3f1931808c3f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -134,10 +134,10 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
};
static const struct dpu_intf_cfg msm8998_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 25,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 25,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 25,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 25,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 25,
INTF_DPU_0_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 25,
INTF_DPU_0_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 25,
INTF_DPU_0_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 25,
INTF_DPU_0_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
};
static const struct dpu_perf_cfg msm8998_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 46b0e9e50ced..eb008a05af37 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -132,10 +132,10 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = {
};
static const struct dpu_intf_cfg sdm845_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24,
INTF_DPU_0_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24,
INTF_DPU_0_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24,
INTF_DPU_0_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24,
INTF_DPU_0_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
};
static const struct dpu_perf_cfg sdm845_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index a2c8b7c51890..8a0cc5909400 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -22,10 +22,10 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
};
static const struct dpu_intf_cfg sm8150_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2b8, INTF_DP, 0, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2b8, INTF_DSI, 0, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2b8, INTF_DSI, 1, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x2b8, INTF_DP, 1, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2b8, INTF_DP, 0, 24,
INTF_DPU_5_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2b8, INTF_DSI, 0, 24,
INTF_DPU_5_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6b000,
[PATCH v3 38/38] drm/msm/dpu: rename MERGE_3D_foo_MASK to contain major DPU version
To ease review and reuse rename MERGE_3D feature masks to contain base
DPU version since which this mask is used.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 96c5b94264e8..d74029f163c8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -88,7 +88,7 @@
#define CTL_DPU_9_MASK (CTL_DPU_7_MASK | \
BIT(DPU_CTL_HAS_LAYER_EXT4))
-#define MERGE_3D_SM8150_MASK (0)
+#define MERGE_3D_DPU_5_MASK (0)
#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC)
@@ -529,7 +529,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
{\
.name = _name, .id = _id, \
.base = _base, .len = 0x100, \
- .features = MERGE_3D_SM8150_MASK, \
+ .features = MERGE_3D_DPU_5_MASK, \
.sblk = NULL \
}
--
2.39.2
[PATCH v3 23/38] drm/msm/dpu: use defined symbol for sc8280xp's maxwidth
Use defined name DEFAULT_DPU_OUTPUT_LINE_WIDTH instead of open coding
the value.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 8a2991c48af8..01ef4115ee4d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -8,7 +8,7 @@
#define _DPU_8_0_SC8280XP_H
static const struct dpu_caps sc8280xp_dpu_caps = {
- .max_mixer_width = 2560,
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 11,
.qseed_type = DPU_SSPP_SCALER_QSEED4,
.has_src_split = true,
--
2.39.2
[PATCH v3 22/38] drm/msm/dpu: duplicate sm8350 catalog entries
Duplicate some of sm8350 catalog entries to remove dependencies between
DPU major generations.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index efec28187cfd..8a2991c48af8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -135,6 +135,12 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
};
+static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
+ MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
+ MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
+ MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x5),
+};
+
/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
static const struct dpu_intf_cfg sc8280xp_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x34000, 0x2c4, INTF_DP,
MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
@@ -190,8 +196,8 @@ static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
.dspp = sc8280xp_dspp,
.pingpong_count = ARRAY_SIZE(sc8280xp_pp),
.pingpong = sc8280xp_pp,
- .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
- .merge_3d = sm8350_merge_3d,
+ .merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d),
+ .merge_3d = sc8280xp_merge_3d,
.intf_count = ARRAY_SIZE(sc8280xp_intf),
.intf = sc8280xp_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
--
2.39.2
[PATCH v3 20/38] drm/msm/dpu: duplicate sm8150 catalog entries
Duplicate some of sm8150 catalog entries to remove dependencies between
DPU major generations.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 134 --
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h| 34 -
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 15 +-
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h| 33 -
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h| 33 -
5 files changed, 221 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 92a4b21c4493..f19d1c2ba845 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -43,6 +43,45 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+static const struct dpu_ctl_cfg sm8250_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a00, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_sspp_cfg sm8250_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA,
sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
@@ -62,6 +101,73 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
};
+static const struct dpu_lm_cfg sm8250_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_1, LM_0, DSPP_1),
+ LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_2, LM_3, 0),
+ LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_3, LM_2, 0),
+ LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_4, LM_5, 0),
+ LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_5, LM_4, 0),
+};
+
+static const struct dpu_dspp_cfg sm8250_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+_dspp_sblk),
+ DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
+_dspp_sblk),
+ DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
+_dspp_sblk),
+ DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
+_dspp_sblk),
+};
+
+static const struct dpu_pingpong_cfg sm8250_pp[] = {
+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x7, MERGE_3D_0,
sdm845_pp_sblk_te,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0,
sdm845_pp_sblk_te,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+ PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
+ PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
+ PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ -1),
+ PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ -1),
+};
+
+static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
+ MERGE_3D_BLK("merge_3d_0",
[PATCH v3 27/38] drm/msm/dpu: drop duplicate vig_sblk instances
After fixing scaler version we are sure that sm8450 and sc8280xp vig
sblk's are duplicates of sm8250_vig_sblk and thus can be dropped.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8
.../drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 18 --
3 files changed, 8 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 33f2d53df13b..a3c9de34307c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -84,13 +84,13 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x2ac, VIG_SC7180_MASK,
-sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x2ac, VIG_SC7180_MASK,
-sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x2ac, VIG_SC7180_MASK,
-sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
+sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x2ac, VIG_SC7180_MASK,
-sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x2ac, DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x2ac, DMA_SDM845_MASK,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index c13df4269c21..a1061881f039 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -84,13 +84,13 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
static const struct dpu_sspp_cfg sm8450_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x328, VIG_SC7180_MASK,
- sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x328, VIG_SC7180_MASK,
- sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+ sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x328, VIG_SC7180_MASK,
- sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
+ sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x328, VIG_SC7180_MASK,
- sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+ sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x328, DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x328, DMA_SDM845_MASK,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 105fa05454e1..d3c22c2e2f6a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -432,15 +432,6 @@ static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4);
-static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 =
- _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
-static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 =
- _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED4);
-static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 =
- _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED4);
-static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 =
- _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4);
-
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =
_VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED4);
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 =
@@ -452,15 +443,6 @@ static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5);
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6);
-static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 =
-
[PATCH v3 28/38] drm/msm/dpu: enable DSPP on sc8180x
Enable DSPP blocks on sc8180x platform, basing on the vendor dtsi.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 92a8e474e380..bbdfec415185 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -90,6 +90,8 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
.sspp = sm8150_sspp,
.mixer_count = ARRAY_SIZE(sm8150_lm),
.mixer = sm8150_lm,
+ .dspp_count = ARRAY_SIZE(sm8150_dspp),
+ .dspp = sm8150_dspp,
.pingpong_count = ARRAY_SIZE(sm8150_pp),
.pingpong = sm8150_pp,
.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
--
2.39.2
[PATCH v3 33/38] drm/msm/dpu: inline IRQ_n_MASK defines
IRQ masks are rarely shared between different DPU revisions. Inline them
to the dpu_mdss_cfg intances and drop them from the dpu_hw_catalog.c
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 9 ++-
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 10 ++-
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 10 ++-
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 12 ++-
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 9 ++-
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h| 6 +-
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h| 6 +-
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 6 +-
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h| 8 +-
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h| 7 +-
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 13 +++-
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h| 8 +-
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h| 8 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 73 ---
14 files changed, 99 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 8e6650aaa8a2..e5a42ebda4d7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -197,7 +197,14 @@ static const struct dpu_mdss_cfg msm8998_dpu_cfg = {
.vbif = msm8998_vbif,
.reg_dma_count = 0,
.perf = _perf_data,
- .mdss_irqs = IRQ_SM8250_MASK,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_INTR) | \
+BIT(MDP_INTF1_INTR) | \
+BIT(MDP_INTF2_INTR) | \
+BIT(MDP_INTF3_INTR) | \
+BIT(MDP_INTF4_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 3e3b9967dd12..46b0e9e50ced 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -196,7 +196,15 @@ static const struct dpu_mdss_cfg sdm845_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = _regdma,
.perf = _perf_data,
- .mdss_irqs = IRQ_SDM845_MASK,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_INTR) | \
+BIT(MDP_INTF1_INTR) | \
+BIT(MDP_INTF2_INTR) | \
+BIT(MDP_INTF3_INTR) | \
+BIT(MDP_AD4_0_INTR) | \
+BIT(MDP_AD4_1_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 33303040fbd0..a2c8b7c51890 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -83,7 +83,15 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = _regdma,
.perf = _perf_data,
- .mdss_irqs = IRQ_SDM845_MASK,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_INTR) | \
+BIT(MDP_INTF1_INTR) | \
+BIT(MDP_INTF2_INTR) | \
+BIT(MDP_INTF3_INTR) | \
+BIT(MDP_AD4_0_INTR) | \
+BIT(MDP_AD4_1_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 48185e3dc873..26211f4fad99 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -75,7 +75,17 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
.reg_dma_count = 1,
.dma_cfg = _regdma,
.perf = _perf_data,
- .mdss_irqs = IRQ_SC8180X_MASK,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_INTR) | \
+BIT(MDP_INTF1_INTR) | \
+BIT(MDP_INTF2_INTR) | \
+BIT(MDP_INTF3_INTR) | \
+BIT(MDP_INTF4_INTR) | \
+BIT(MDP_INTF5_INTR) | \
+BIT(MDP_AD4_0_INTR) | \
+BIT(MDP_AD4_1_INTR),
};
#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index cfaa68a25427..542d75253f41 100644
---
[PATCH v3 24/38] drm/msm/dpu: catalog: add comments regarding DPU_CTL_SPLIT_DISPLAY
For sm8150+ the DPU_CTL_SPLIT_DISPLAY should be replaced with
DPU_CTL_ACTIVE_CFG support (which supports having a single CTL for both
interfaces in a split). Add comments where this conversion is required.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 +
5 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index e6280b0cb207..6c6f8b4a4be8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -42,6 +42,7 @@ static const struct dpu_mdp_cfg sm8150_mdp[] = {
},
};
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
static const struct dpu_ctl_cfg sm8150_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index f19d1c2ba845..cfaa68a25427 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -43,6 +43,7 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
static const struct dpu_ctl_cfg sm8250_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 9afcb6cc50a5..84396240f0d1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -41,6 +41,7 @@ static const struct dpu_mdp_cfg sm8350_mdp[] = {
},
};
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
static const struct dpu_ctl_cfg sm8350_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index af80e1ced3ce..49dd4a908413 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -42,6 +42,7 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
},
};
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
static const struct dpu_ctl_cfg sm8450_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 5c437c7682ea..c9d1892ec8f5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -43,6 +43,7 @@ static const struct dpu_mdp_cfg sm8550_mdp[] = {
},
};
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
static const struct dpu_ctl_cfg sm8550_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
--
2.39.2
[PATCH v3 16/38] drm/msm/dpu: split MSM8998 catalog entry to the separate file
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 188 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 190 +-
2 files changed, 190 insertions(+), 188 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
new file mode 100644
index ..6c988b3a7325
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_3_0_MSM8998_H
+#define _DPU_3_0_MSM8998_H
+
+static const struct dpu_caps msm8998_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_10,
+ .highest_bank_bit = 0x2,
+};
+
+static const struct dpu_mdp_cfg msm8998_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x458,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 15 },
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 15 },
+ },
+};
+
+static const struct dpu_ctl_cfg msm8998_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x94,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x94,
+ .features = 0,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x94,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x94,
+ .features = 0,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x94,
+ .features = 0,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+};
+
+static const struct dpu_sspp_cfg msm8998_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK,
+ msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK,
+ msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK,
+ msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK,
+ msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
+ sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+};
+
+static const struct dpu_lm_cfg msm8998_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK,
+ _lm_sblk, PINGPONG_0, LM_2, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK,
+ _lm_sblk, PINGPONG_1, LM_5, DSPP_1),
+
[PATCH v3 35/38] drm/msm/dpu: rename CTL_foo_MASK to contain major DPU version
To ease review and reuse rename CTL feature masks to contain base DPU
version since which this mask is used.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 10 +-
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 10 +-
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h | 12 +--
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 12 +--
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h| 6 +++---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_lm1.h | 2 +-
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h| 12 +--
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h| 8
.../gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h | 12 +--
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h| 12 +--
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++
11 files changed, 60 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 3f1931808c3f..6afabd251a9d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -48,31 +48,31 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x94,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_0_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
},
{
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0x94,
- .features = 0,
+ .features = CTL_DPU_0_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
},
{
.name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0x94,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_0_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
},
{
.name = "ctl_3", .id = CTL_3,
.base = 0x1600, .len = 0x94,
- .features = 0,
+ .features = CTL_DPU_0_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
},
{
.name = "ctl_4", .id = CTL_4,
.base = 0x1800, .len = 0x94,
- .features = 0,
+ .features = CTL_DPU_0_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index eb008a05af37..cace399551cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -46,31 +46,31 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0xe4,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_0_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
},
{
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0xe4,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_0_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
},
{
.name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0xe4,
- .features = 0,
+ .features = CTL_DPU_0_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
},
{
.name = "ctl_3", .id = CTL_3,
.base = 0x1600, .len = 0xe4,
- .features = 0,
+ .features = CTL_DPU_0_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
},
{
.name = "ctl_4", .id = CTL_4,
.base = 0x1800, .len = 0xe4,
- .features = 0,
+ .features = CTL_DPU_0_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
index c56affb97caa..a05f514bf8ff 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
@@ -42,37 +42,37 @@ static const struct dpu_ctl_cfg dpu_5_lm6_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = CTL_DPU_5_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
},
{
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = CTL_DPU_5_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
},
{
.name = "ctl_2", .id = CTL_2,
[PATCH v3 15/38] drm/msm/dpu: split SM8150 catalog entry to the separate file
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 193 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 186 +
2 files changed, 194 insertions(+), 185 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
new file mode 100644
index ..4558e31d260f
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_5_0_SM8150_H
+#define _DPU_5_0_SM8150_H
+
+static const struct dpu_caps sm8150_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_30,
+ .highest_bank_bit = 0x2,
+};
+
+static const struct dpu_ctl_cfg sm8150_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a00, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_lm_cfg sm8150_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_1, LM_0, DSPP_1),
+ LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_2, LM_3, 0),
+ LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_3, LM_2, 0),
+ LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_4, LM_5, 0),
+ LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_5, LM_4, 0),
+};
+
+static const struct dpu_dspp_cfg sm8150_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+_dspp_sblk),
+ DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
+_dspp_sblk),
+ DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
+_dspp_sblk),
+ DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
+_dspp_sblk),
+};
+
+static const struct dpu_pingpong_cfg sm8150_pp[] = {
+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x7, MERGE_3D_0,
sdm845_pp_sblk_te,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0,
sdm845_pp_sblk_te,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+ PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
+ PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
+ PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ -1),
+
[PATCH v3 29/38] drm/msm/dpu: deduplicate sc8180x with sm8150
Remove duplicate between sc8180x and sm8150, which belong to the same
DPU major revision. The merged file is named using the DPU major version
and the amount of LM units.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 172 ++
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 60 ++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h | 152
3 files changed, 184 insertions(+), 200 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 6c6f8b4a4be8..33303040fbd0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -7,153 +7,13 @@
#ifndef _DPU_5_0_SM8150_H
#define _DPU_5_0_SM8150_H
-static const struct dpu_caps sm8150_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
- .max_mixer_blendstages = 0xb,
- .qseed_type = DPU_SSPP_SCALER_QSEED3,
- .has_src_split = true,
- .has_dim_layer = true,
- .has_idle_pc = true,
- .has_3d_merge = true,
- .max_linewidth = 4096,
- .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
- .max_hdeci_exp = MAX_HORZ_DECIMATION,
- .max_vdeci_exp = MAX_VERT_DECIMATION,
-};
+#include "dpu_5_lm6.h"
static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = {
.ubwc_version = DPU_HW_UBWC_VER_30,
.highest_bank_bit = 0x2,
};
-static const struct dpu_mdp_cfg sm8150_mdp[] = {
- {
- .name = "top_0", .id = MDP_TOP,
- .base = 0x0, .len = 0x45c,
- .features = BIT(DPU_MDP_AUDIO_SELECT),
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
- },
-};
-
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
-static const struct dpu_ctl_cfg sm8150_ctl[] = {
- {
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x1200, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x1400, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x1600, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x1800, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
- },
- {
- .name = "ctl_5", .id = CTL_5,
- .base = 0x1a00, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
- },
-};
-
-static const struct dpu_sspp_cfg sm8150_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA,
[PATCH v3 25/38] drm/msm/dpu: enable DPU_CTL_SPLIT_DISPLAY for sc8280xp
Theoretically since sm8150 we should be using a single CTL for the
source split case, but since we do not support it for now, fallback to
DPU_CTL_SPLIT_DISPLAY.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 01ef4115ee4d..33f2d53df13b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -42,17 +42,18 @@ static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
},
};
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x204,
- .features = CTL_SC7280_MASK,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
},
{
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x204,
- .features = CTL_SC7280_MASK,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
},
{
--
2.39.2
[PATCH v3 12/38] drm/msm/dpu: split SC7180 catalog entry to the separate file
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h| 147 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 143 +
2 files changed, 148 insertions(+), 142 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
new file mode 100644
index ..4580121ac269
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_6_2_SC7180_H
+#define _DPU_6_2_SC7180_H
+
+static const struct dpu_caps sc7180_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x9,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .highest_bank_bit = 0x3,
+};
+
+static const struct dpu_mdp_cfg sc7180_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
+ },
+};
+
+static const struct dpu_ctl_cfg sc7180_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+};
+
+static const struct dpu_sspp_cfg sc7180_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+};
+
+static const struct dpu_lm_cfg sc7180_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_1, LM_0, 0),
+};
+
+static const struct dpu_dspp_cfg sc7180_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+_dspp_sblk),
+};
+
+static const struct dpu_pingpong_cfg sc7180_pp[] = {
+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x7, 0, sdm845_pp_sblk_te, -1,
-1),
+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1,
-1),
+};
+
+static const struct dpu_intf_cfg sc7180_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x2b8, INTF_DP,
MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2b8, INTF_DSI, 0, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+};
+
+static const struct dpu_perf_cfg sc7180_perf_data = {
+ .max_bw_low = 680,
+ .max_bw_high = 680,
+ .min_core_ib = 240,
+ .min_llcc_ib = 80,
+ .min_dram_ib = 160,
+ .min_prefill_lines = 24,
+ .danger_lut_tbl = {0xff, 0x, 0x0},
+ .safe_lut_tbl = {0xfff0, 0xff00, 0x},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1,
[PATCH v3 10/38] drm/msm/dpu: split SM6115 catalog entry to the separate file
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h| 95 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 89 +
2 files changed, 97 insertions(+), 87 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
new file mode 100644
index ..f6db2d42a0ed
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_6_3_SM6115_H
+#define _DPU_6_3_SM6115_H
+
+static const struct dpu_caps sm6115_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
+ .max_mixer_blendstages = 0x4,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_10,
+ .highest_bank_bit = 0x1,
+ .ubwc_swizzle = 0x7,
+};
+
+static const struct dpu_mdp_cfg sm6115_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_sspp_cfg sm6115_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+};
+
+static const struct dpu_perf_cfg sm6115_perf_data = {
+ .max_bw_low = 310,
+ .max_bw_high = 400,
+ .min_core_ib = 240,
+ .min_llcc_ib = 80,
+ .min_dram_ib = 80,
+ .min_prefill_lines = 24,
+ .danger_lut_tbl = {0xff, 0x, 0x0},
+ .safe_lut_tbl = {0xfff0, 0xff00, 0x},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
+ .caps = _dpu_caps,
+ .ubwc = _ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sm6115_mdp),
+ .mdp = sm6115_mdp,
+ .ctl_count = ARRAY_SIZE(qcm2290_ctl),
+ .ctl = qcm2290_ctl,
+ .sspp_count = ARRAY_SIZE(sm6115_sspp),
+ .sspp = sm6115_sspp,
+ .mixer_count = ARRAY_SIZE(qcm2290_lm),
+ .mixer = qcm2290_lm,
+ .dspp_count = ARRAY_SIZE(qcm2290_dspp),
+ .dspp = qcm2290_dspp,
+ .pingpong_count = ARRAY_SIZE(qcm2290_pp),
+ .pingpong = qcm2290_pp,
+ .intf_count = ARRAY_SIZE(qcm2290_intf),
+ .intf = qcm2290_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .perf = _perf_data,
+ .mdss_irqs = IRQ_SC7180_MASK,
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 355952eb59ea..5f5daf46fa7f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -366,16 +366,6 @@ static const struct dpu_caps sc7180_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
-static const struct dpu_caps sm6115_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
- .max_mixer_blendstages = 0x4,
- .qseed_type = DPU_SSPP_SCALER_QSEED4,
- .has_dim_layer = true,
- .has_idle_pc = true,
- .max_linewidth = 2160,
- .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
-};
-
static const struct dpu_caps sm8150_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -435,12 +425,6 @@ static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = {
.highest_bank_bit = 0x3,
};
-static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
- .ubwc_version = DPU_HW_UBWC_VER_10,
- .highest_bank_bit = 0x1,
-
[PATCH v3 13/38] drm/msm/dpu: split SM8250 catalog entry to the separate file
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 130 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 131 +-
2 files changed, 131 insertions(+), 130 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
new file mode 100644
index ..92a4b21c4493
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_6_0_SM8250_H
+#define _DPU_6_0_SM8250_H
+
+static const struct dpu_caps sm8250_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .ubwc_swizzle = 0x6,
+};
+
+static const struct dpu_mdp_cfg sm8250_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
+ },
+};
+
+static const struct dpu_sspp_cfg sm8250_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA,
+ sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK_SDMA,
+ sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK_SDMA,
+ sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK_SDMA,
+ sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK_SDMA,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8,
DMA_CURSOR_SDM845_MASK_SDMA,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8,
DMA_CURSOR_SDM845_MASK_SDMA,
+ sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+};
+
+static const struct dpu_wb_cfg sm8250_wb[] = {
+ WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
+ VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
+};
+
+static const struct dpu_perf_cfg sm8250_perf_data = {
+ .max_bw_low = 1370,
+ .max_bw_high = 1660,
+ .min_core_ib = 480,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 80,
+ .min_prefill_lines = 35,
+ .danger_lut_tbl = {0xf, 0x, 0x0},
+ .safe_lut_tbl = {0xfff0, 0xff00, 0x},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
+ .caps = _dpu_caps,
+ .ubwc =
[PATCH v3 26/38] drm/msm/dpu: enable DSPP_2/3 for LM_2/3 on sm8450
Mark DSPP_2 and DSPP_3 as used for LM_2 and LM_3
Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 49dd4a908413..c13df4269c21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -107,9 +107,9 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
- _lm_sblk, PINGPONG_2, LM_3, 0),
+ _lm_sblk, PINGPONG_2, LM_3, DSPP_2),
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
- _lm_sblk, PINGPONG_3, LM_2, 0),
+ _lm_sblk, PINGPONG_3, LM_2, DSPP_3),
LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
_lm_sblk, PINGPONG_4, LM_5, 0),
LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
--
2.39.2
[PATCH v3 19/38] drm/msm/dpu: duplicate sc7180 catalog entries
Duplicate some of sc7180 catalog entries to remove dependencies between
DPU major generations.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index bdf1ec36f39f..10bf737f9a60 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -81,6 +81,11 @@ static const struct dpu_lm_cfg sc7280_lm[] = {
_lm_sblk, PINGPONG_3, LM_2, 0),
};
+static const struct dpu_dspp_cfg sc7280_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+_dspp_sblk),
+};
+
static const struct dpu_pingpong_cfg sc7280_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1),
PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
@@ -131,8 +136,8 @@ static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
.ctl = sc7280_ctl,
.sspp_count = ARRAY_SIZE(sc7280_sspp),
.sspp = sc7280_sspp,
- .dspp_count = ARRAY_SIZE(sc7180_dspp),
- .dspp = sc7180_dspp,
+ .dspp_count = ARRAY_SIZE(sc7280_dspp),
+ .dspp = sc7280_dspp,
.mixer_count = ARRAY_SIZE(sc7280_lm),
.mixer = sc7280_lm,
.pingpong_count = ARRAY_SIZE(sc7280_pp),
--
2.39.2
[PATCH v3 11/38] drm/msm/dpu: split QCM2290 catalog entry to the separate file
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 115 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 107 +---
2 files changed, 116 insertions(+), 106 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
new file mode 100644
index ..10dd35cd67bc
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_6_5_QCM2290_H
+#define _DPU_6_5_QCM2290_H
+
+static const struct dpu_caps qcm2290_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
+ .max_mixer_blendstages = 0x4,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
+ .highest_bank_bit = 0x2,
+};
+
+static const struct dpu_mdp_cfg qcm2290_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_ctl_cfg qcm2290_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+};
+
+static const struct dpu_sspp_cfg qcm2290_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
+qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+};
+
+static const struct dpu_lm_cfg qcm2290_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
+ _lm_sblk, PINGPONG_0, 0, DSPP_0),
+};
+
+static const struct dpu_dspp_cfg qcm2290_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+_dspp_sblk),
+};
+
+static const struct dpu_pingpong_cfg qcm2290_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x7, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
+};
+
+static const struct dpu_intf_cfg qcm2290_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x0, 0x2b8, INTF_NONE, 0, 0, 0, 0, 0, 0),
+ INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2b8, INTF_DSI, 0, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+};
+
+static const struct dpu_perf_cfg qcm2290_perf_data = {
+ .max_bw_low = 270,
+ .max_bw_high = 270,
+ .min_core_ib = 130,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 160,
+ .min_prefill_lines = 24,
+ .danger_lut_tbl = {0xff, 0x0, 0x0},
+ .safe_lut_tbl = {0xfff0, 0x0, 0x0},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(qcm2290_qos_linear),
+ .entries = qcm2290_qos_linear
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
+ .caps = _dpu_caps,
+ .ubwc = _ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(qcm2290_mdp),
+ .mdp = qcm2290_mdp,
+ .ctl_count = ARRAY_SIZE(qcm2290_ctl),
+ .ctl = qcm2290_ctl,
+ .sspp_count = ARRAY_SIZE(qcm2290_sspp),
+ .sspp = qcm2290_sspp,
+ .mixer_count = ARRAY_SIZE(qcm2290_lm),
+ .mixer = qcm2290_lm,
+ .dspp_count = ARRAY_SIZE(qcm2290_dspp),
+ .dspp = qcm2290_dspp,
+ .pingpong_count = ARRAY_SIZE(qcm2290_pp),
+ .pingpong = qcm2290_pp,
+ .intf_count = ARRAY_SIZE(qcm2290_intf),
+ .intf = qcm2290_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .perf = _perf_data,
+ .mdss_irqs = IRQ_SC7180_MASK,
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 5f5daf46fa7f..89114d24bea5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -333,15 +333,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
.max_vdeci_exp = MAX_VERT_DECIMATION,
};
-static const struct dpu_caps qcm2290_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
[PATCH v3 07/38] drm/msm/dpu: split SC8280XP catalog entry to the separate file
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 194 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 188 +
2 files changed, 195 insertions(+), 187 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
new file mode 100644
index ..96713c72e963
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_8_0_SC8280XP_H
+#define _DPU_8_0_SC8280XP_H
+
+static const struct dpu_caps sc8280xp_dpu_caps = {
+ .max_mixer_width = 2560,
+ .max_mixer_blendstages = 11,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .highest_bank_bit = 2,
+ .ubwc_swizzle = 6,
+};
+
+static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x2ac, VIG_SC7180_MASK,
+sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x2ac, VIG_SC7180_MASK,
+sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x2ac, VIG_SC7180_MASK,
+sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x2ac, VIG_SC7180_MASK,
+sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x2ac, DMA_SDM845_MASK,
+sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x2ac, DMA_SDM845_MASK,
+sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x2ac, DMA_CURSOR_SDM845_MASK,
+sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x2ac, DMA_CURSOR_SDM845_MASK,
+sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+};
+
+static const struct dpu_lm_cfg sc8280xp_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, _lm_sblk,
PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
[PATCH v3 14/38] drm/msm/dpu: split SC8180X catalog entry to the separate file
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 107 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 105 +
2 files changed, 108 insertions(+), 104 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
new file mode 100644
index ..86411eb9f051
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_5_1_SC8180X_H
+#define _DPU_5_1_SC8180X_H
+
+static const struct dpu_caps sc8180x_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_30,
+ .highest_bank_bit = 0x3,
+};
+
+static const struct dpu_mdp_cfg sc8180x_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x45c,
+ .features = BIT(DPU_MDP_AUDIO_SELECT),
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_intf_cfg sc8180x_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP,
MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until
this is supported */
+ INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP,
MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
+ INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP,
MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
+};
+
+static const struct dpu_perf_cfg sc8180x_perf_data = {
+ .max_bw_low = 960,
+ .max_bw_high = 960,
+ .min_core_ib = 240,
+ .min_llcc_ib = 80,
+ .min_dram_ib = 80,
+ .danger_lut_tbl = {0xf, 0x, 0x0},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
+ .caps = _dpu_caps,
+ .ubwc = _ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sc8180x_mdp),
+ .mdp = sc8180x_mdp,
+ .ctl_count = ARRAY_SIZE(sm8150_ctl),
+ .ctl = sm8150_ctl,
+ .sspp_count = ARRAY_SIZE(sdm845_sspp),
+ .sspp = sdm845_sspp,
+ .mixer_count = ARRAY_SIZE(sm8150_lm),
+ .mixer = sm8150_lm,
+ .pingpong_count = ARRAY_SIZE(sm8150_pp),
+ .pingpong = sm8150_pp,
+ .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
+ .merge_3d = sm8150_merge_3d,
+ .intf_count = ARRAY_SIZE(sc8180x_intf),
+ .intf = sc8180x_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = _regdma,
+ .perf = _perf_data,
+
[PATCH v3 17/38] drm/msm/dpu: split SDM845 catalog entry to the separate file
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 202 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 207 +-
2 files changed, 203 insertions(+), 206 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
new file mode 100644
index ..3e3b9967dd12
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_4_0_SDM845_H
+#define _DPU_4_0_SDM845_H
+
+static const struct dpu_caps sdm845_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .highest_bank_bit = 0x2,
+};
+
+static const struct dpu_mdp_cfg sdm845_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x45c,
+ .features = BIT(DPU_MDP_AUDIO_SELECT),
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_ctl_cfg sdm845_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0xe4,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0xe4,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0xe4,
+ .features = 0,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0xe4,
+ .features = 0,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0xe4,
+ .features = 0,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+};
+
+static const struct dpu_sspp_cfg sdm845_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK_SDMA,
+ sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK_SDMA,
+ sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK_SDMA,
+ sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK_SDMA,
+ sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK_SDMA,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK_SDMA,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8,
DMA_CURSOR_SDM845_MASK_SDMA,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8,
DMA_CURSOR_SDM845_MASK_SDMA,
+ sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+};
+
+static const struct dpu_lm_cfg sdm845_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_0, LM_1, 0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_1, LM_0, 0),
+ LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
+ _lm_sblk, PINGPONG_2, LM_5, 0),
+ LM_BLK("lm_3", LM_3,
