[PATCH v2 4/4] drm/msm/dpu: Add support for MSM8917
From: Dmitry Baryshkov
Add support for MSM8917, which has MDP5 v1.15. It looks like
trimmed down version of MSM8937. Even fewer PP, LM and no DSI1.
Signed-off-by: Dmitry Baryshkov
[Remove intr_start from CTLs config, reword the commit]
Signed-off-by: Barnabás Czémán
---
.../drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 187 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
drivers/gpu/drm/msm/msm_drv.c | 1 +
5 files changed, 191 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
new file mode 100644
index
..6bdaecca676144f9162ab1839d99f3e2e3386dc7
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_1_14_MSM8917_H
+#define _DPU_1_14_MSM8917_H
+
+static const struct dpu_caps msm8917_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
+ .max_mixer_blendstages = 0x4,
+ .max_linewidth = DEFAULT_DPU_LINE_WIDTH,
+ .pixel_ram_size = 16 * 1024,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_mdp_cfg msm8917_mdp[] = {
+ {
+ .name = "top_0",
+ .base = 0x0, .len = 0x454,
+ .features = BIT(DPU_MDP_VSYNC_SEL),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0
},
+ [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4
},
+ [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4
},
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8
},
+ [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off =
16 },
+ },
+ },
+};
+
+static const struct dpu_ctl_cfg msm8917_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x64,
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x64,
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x64,
+ },
+};
+
+static const struct dpu_sspp_cfg msm8917_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x150,
+ .features = VIG_MSM8953_MASK,
+ .sblk = &dpu_vig_sblk_qseed2,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_4", .id = SSPP_RGB0,
+ .base = 0x14000, .len = 0x150,
+ .features = RGB_MSM8953_MASK,
+ .sblk = &dpu_rgb_sblk,
+ .xin_id = 1,
+ .type = SSPP_TYPE_RGB,
+ .clk_ctrl = DPU_CLK_CTRL_RGB0,
+ }, {
+ .name = "sspp_5", .id = SSPP_RGB1,
+ .base = 0x16000, .len = 0x150,
+ .features = RGB_MSM8953_MASK,
+ .sblk = &dpu_rgb_sblk,
+ .xin_id = 5,
+ .type = SSPP_TYPE_RGB,
+ .clk_ctrl = DPU_CLK_CTRL_RGB1,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x150,
+ .features = DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR),
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 2,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ },
+};
+
+static const struct dpu_lm_cfg msm8917_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .sblk = &msm8998_lm_sblk,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ },
+};
+
+static const struct dpu_pingpong_cfg msm8917_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x7, .len = 0xd4,
+ .features = PINGPONG_MSM8996_MASK,
+ .sblk = &msm8996_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+ },
+};
+
+static const struct dpu_dspp_cfg msm8917_dspp[] = {
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &msm8998_dspp_sblk,
+ },
+};
+
+static const struct dpu_intf_cfg msm8917_intf[] = {
[PATCH v2 1/4] drm/msm/dpu: Add support for MSM8996
From: Konrad Dybcio
Add support for MSM8996, which - fun fact - was the SoC that this driver
(or rather SDE, its downstream origin) was meant for and first tested on.
It has some hardware that differs from the modern SoCs, so not a lot of
current structs could have been reused. It's also seemingly the only SoC
supported by DPU that uses RGB pipes.
Note, by default this platform is still handled by the MDP5 driver
unless the `msm.prefer_mdp5=false' parameter is provided.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
[DB: rebased on top of sblk changes, add dpu_rgb_sblk]
Signed-off-by: Dmitry Baryshkov
Acked-by: Konrad Dybcio
[Removed intr_start from CTLs config, removed LM_3 and LM_4]
Signed-off-by: Barnabás Czémán
---
.../drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h| 338 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 94 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
drivers/gpu/drm/msm/msm_drv.c | 1 +
5 files changed, 435 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
new file mode 100644
index
..491f6f5827d151011dd3f74bef2a4b8bf69591ab
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
@@ -0,0 +1,338 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_1_7_MSM8996_H
+#define _DPU_1_7_MSM8996_H
+
+static const struct dpu_caps msm8996_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .has_src_split = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_mdp_cfg msm8996_mdp[] = {
+ {
+ .name = "top_0",
+ .base = 0x0, .len = 0x454,
+ .features = BIT(DPU_MDP_VSYNC_SEL),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0
},
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0
},
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0
},
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0
},
+ [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4
},
+ [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4
},
+ [DPU_CLK_CTRL_RGB2] = { .reg_off = 0x2bc, .bit_off = 4
},
+ [DPU_CLK_CTRL_RGB3] = { .reg_off = 0x2c4, .bit_off = 4
},
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8
},
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8
},
+ [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off =
16 },
+ [DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off =
16 },
+ },
+ },
+};
+
+static const struct dpu_ctl_cfg msm8996_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x64,
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x64,
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x64,
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x64,
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x64,
+ },
+};
+
+static const struct dpu_sspp_cfg msm8996_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x150,
+ .features = VIG_MSM8996_MASK,
+ .sblk = &dpu_vig_sblk_qseed2,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x150,
+ .features = VIG_MSM8996_MASK,
+ .sblk = &dpu_vig_sblk_qseed2,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x150,
+ .features = VIG_MSM8996_MASK,
+ .sblk = &dpu_vig_sblk_qseed2,
+
[PATCH v2 0/4] Add MSM8996/MSM8953/MSM8937/MSM8917 dpu catalog
This patch series add dpu support for MSM8996/MSM8953/MSM8937/MSM8917 SoCs. This parch series was tested on many devices: - Xiaomi Redmi 5A (msm8917, video panel) - Xiaomi Redmi Note 5A (msm8917, video panel) - Xiaomi Redmi Note 5A Prime (msm8940, video panel) - Motorola G5S (msm8937, video panel) - Xiaomi Redmi 3S (msm8937, video panel) - Xiaomi Redmi 4x (msm8940, video panel) - Samsung A6+ LTE (sdm450, cmd panel) - Xiaomi Redmi 7 (sdm632, video panel) - Xiaomi Redmi 5 (sdm450, video panel) - Xiaomi Redmi 5 Plus (msm8953, video panel) - Xiaomi Redmi Note 4 (msm8953, video panel) - Xiaomi Mi A1 (msm8953, video panel) - Xiaomi Mi A2 Lite/Redmi 6 Pro (msm8953, video panel) - Xiaomi Redmi S2 (msm8953, video panel) - Motorola G5 Plus (msm8953, video panel) - Xiaomi Mi Note 2 (msm8996, video panel) - Xiaomi Mi 5s (msm8996, cmd panel) All LMs and SSPPs was checked and works, except cmd panel related configs (SSPP_DMA0) on MSM8917 and MSM8937. Note, by default these platforms are still handled by the MDP5 driver unless the `msm.prefer_mdp5=false' parameter is provided. Signed-off-by: Barnabás Czémán --- Changes in v2: - Add MSM8917 and MSM8937 from previous attempts. - Remove LM_3 and LM_4 from msm8996. - Link to v1: https://lore.kernel.org/r/20240628-dpu-msm8953-msm8996-v1-0-a31c77248...@mainlining.org --- Dmitry Baryshkov (3): drm/msm/dpu: Add support for MSM8953 drm/msm/dpu: Add support for MSM8937 drm/msm/dpu: Add support for MSM8917 Konrad Dybcio (1): drm/msm/dpu: Add support for MSM8996 .../drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 210 + .../drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 187 .../drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 218 + .../drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h| 338 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 108 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 4 + drivers/gpu/drm/msm/msm_drv.c | 4 + 8 files changed, 1073 insertions(+) --- base-commit: cea5425829f77e476b03702426f6b3701299b925 change-id: 20240528-dpu-msm8953-msm8996-5d0fb7e387b8 Best regards, -- Barnabás Czémán
[PATCH v2 2/4] drm/msm/dpu: Add support for MSM8953
From: Dmitry Baryshkov
Add support for MSM8953, which has MDP5 v1.16. It looks like
trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
etc.
Signed-off-by: Dmitry Baryshkov
[Remove intr_start from CTLs config, reword the commit]
Signed-off-by: Barnabás Czémán
---
.../drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 218 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
drivers/gpu/drm/msm/msm_drv.c | 1 +
5 files changed, 233 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
new file mode 100644
index
..14f36ea6ad0eb61e87f043437a8cd78bb1bde49c
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_1_16_MSM8953_H
+#define _DPU_1_16_MSM8953_H
+
+static const struct dpu_caps msm8953_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
+ .max_mixer_blendstages = 0x4,
+ .max_linewidth = DEFAULT_DPU_LINE_WIDTH,
+ .pixel_ram_size = 40 * 1024,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_mdp_cfg msm8953_mdp[] = {
+ {
+ .name = "top_0",
+ .base = 0x0, .len = 0x454,
+ .features = BIT(DPU_MDP_VSYNC_SEL),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0
},
+ [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4
},
+ [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4
},
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8
},
+ [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off =
16 },
+ },
+ },
+};
+
+static const struct dpu_ctl_cfg msm8953_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x64,
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x64,
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x64,
+ },
+};
+
+static const struct dpu_sspp_cfg msm8953_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x150,
+ .features = VIG_MSM8953_MASK,
+ .sblk = &dpu_vig_sblk_qseed2,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_4", .id = SSPP_RGB0,
+ .base = 0x14000, .len = 0x150,
+ .features = RGB_MSM8953_MASK,
+ .sblk = &dpu_rgb_sblk,
+ .xin_id = 1,
+ .type = SSPP_TYPE_RGB,
+ .clk_ctrl = DPU_CLK_CTRL_RGB0,
+ }, {
+ .name = "sspp_5", .id = SSPP_RGB1,
+ .base = 0x16000, .len = 0x150,
+ .features = RGB_MSM8953_MASK,
+ .sblk = &dpu_rgb_sblk,
+ .xin_id = 5,
+ .type = SSPP_TYPE_RGB,
+ .clk_ctrl = DPU_CLK_CTRL_RGB1,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x150,
+ .features = DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR),
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 2,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ },
+};
+
+static const struct dpu_lm_cfg msm8953_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ },
+};
+
+static const struct dpu_pingpong_cfg msm8953_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x7, .len = 0xd4,
+ .features = PINGPONG_MSM8996_MASK,
+ .sblk = &msm8996_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+ }, {
+ .name = "pingpong_1", .id = P
[PATCH v2 3/4] drm/msm/dpu: Add support for MSM8937
From: Dmitry Baryshkov
Add support for MSM8937, which has MDP5 v1.14. It looks like
trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
etc.
Signed-off-by: Dmitry Baryshkov
[Remove intr_start from CTLs config, reword the commit]
Signed-off-by: Barnabás Czémán
---
.../drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 210 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
drivers/gpu/drm/msm/msm_drv.c | 1 +
5 files changed, 214 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
new file mode 100644
index
..ab3dfb0b374ead36c7f07b0a77c703fb2c09ff8a
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_1_14_MSM8937_H
+#define _DPU_1_14_MSM8937_H
+
+static const struct dpu_caps msm8937_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
+ .max_mixer_blendstages = 0x4,
+ .max_linewidth = DEFAULT_DPU_LINE_WIDTH,
+ .pixel_ram_size = 40 * 1024,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_mdp_cfg msm8937_mdp[] = {
+ {
+ .name = "top_0",
+ .base = 0x0, .len = 0x454,
+ .features = BIT(DPU_MDP_VSYNC_SEL),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0
},
+ [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4
},
+ [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4
},
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8
},
+ [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off =
16 },
+ },
+ },
+};
+
+static const struct dpu_ctl_cfg msm8937_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x64,
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x64,
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x64,
+ },
+};
+
+static const struct dpu_sspp_cfg msm8937_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x150,
+ .features = VIG_MSM8953_MASK,
+ .sblk = &dpu_vig_sblk_qseed2,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_4", .id = SSPP_RGB0,
+ .base = 0x14000, .len = 0x150,
+ .features = RGB_MSM8953_MASK,
+ .sblk = &dpu_rgb_sblk,
+ .xin_id = 1,
+ .type = SSPP_TYPE_RGB,
+ .clk_ctrl = DPU_CLK_CTRL_RGB0,
+ }, {
+ .name = "sspp_5", .id = SSPP_RGB1,
+ .base = 0x16000, .len = 0x150,
+ .features = RGB_MSM8953_MASK,
+ .sblk = &dpu_rgb_sblk,
+ .xin_id = 5,
+ .type = SSPP_TYPE_RGB,
+ .clk_ctrl = DPU_CLK_CTRL_RGB1,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x150,
+ .features = DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR),
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 2,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ },
+};
+
+static const struct dpu_lm_cfg msm8937_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ },
+};
+
+static const struct dpu_pingpong_cfg msm8937_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x7, .len = 0xd4,
+ .features = PINGPONG_MSM8996_MASK,
+ .sblk = &msm8996_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+ }, {
+ .name = "pingpong_1", .id = P
Re: [PATCH v3] drm/msm/adreno: Add A306A support
I hope it was not forgotten or am I missing something?
On Mon, Jul 22, 2024 at 4:58 PM Barnabás Czémán wrote:
>
> From: Otto Pflüger
>
> Add support for Adreno 306A GPU what is found in MSM8917 SoC.
> This GPU marketing name is Adreno 308.
>
> Signed-off-by: Otto Pflüger
> [use internal name of the GPU, reword the commit message]
> Reviewed-by: Konrad Dybcio
> Signed-off-by: Barnabás Czémán
> ---
> Changes in v3:
> - Fix issues addressed by reviews.
> - Rebase on latest next.
> - Link to v2:
> https://lore.kernel.org/r/20240620-a306a-v2-1-0d388e1de...@gmail.com
>
> Changes in v2:
> - Rebase on https://patchwork.freedesktop.org/series/127393/
> - Link to v1:
> https://lore.kernel.org/r/20240528-a306a-v1-1-03a66dacd...@gmail.com
> ---
> drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 11 +++
> drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 14 +++---
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++
> 3 files changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> index 0de8465b6cf0..2eb6c3e93748 100644
> --- a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> @@ -41,6 +41,17 @@ static const struct adreno_info a3xx_gpus[] = {
> .gmem = SZ_128K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a3xx_gpu_init,
> + }, {
> + .chip_ids = ADRENO_CHIP_IDS(0x03000620),
> + .family = ADRENO_3XX,
> + .revn = 308,
> + .fw = {
> + [ADRENO_FW_PM4] = "a300_pm4.fw",
> + [ADRENO_FW_PFP] = "a300_pfp.fw",
> + },
> + .gmem = SZ_128K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a3xx_gpu_init,
> }, {
> .chip_ids = ADRENO_CHIP_IDS(
> 0x0302,
> diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> index 5273dc849838..b46ff49f47cf 100644
> --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> @@ -145,6 +145,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
> gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x000a);
> gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x000a);
> + } else if (adreno_is_a306a(adreno_gpu)) {
> + gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
> + gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0010);
> + gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0010);
> } else if (adreno_is_a320(adreno_gpu)) {
> /* Set up 16 deep read/write request queues: */
> gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
> @@ -237,7 +241,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x0001);
>
> /* Enable Clock gating: */
> - if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu))
> + if (adreno_is_a305b(adreno_gpu) ||
> + adreno_is_a306(adreno_gpu) ||
> + adreno_is_a306a(adreno_gpu))
> gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0x);
> else if (adreno_is_a320(adreno_gpu))
> gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfff);
> @@ -334,8 +340,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
>
> /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
> - if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) ||
> - adreno_is_a320(adreno_gpu)) {
> + if (adreno_is_a305(adreno_gpu) ||
> + adreno_is_a306(adreno_gpu) ||
> + adreno_is_a306a(adreno_gpu) ||
> + adreno_is_a320(adreno_gpu)) {
> gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
> AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
> AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 1ab523a163a0..c3b7970c2bfa 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -294,6 +294,12 @@ static inline bool adreno_is_a306(const struct
> adreno_gpu *gpu)
> return adreno_is_revn(gpu,
Re: [PATCH 0/2] Add MSM8996/MSM8953 dpu catalog
Should i resend this patch set? On June 28, 2024 4:39:38 PM GMT+02:00, "Barnabás Czémán" wrote: >This patch series add dpu support for MSM8996/MSM8953 devices. > >Note, by default these platforms are still handled by the MDP5 driver >unless the `msm.prefer_mdp5=false' parameter is provided. > >Signed-off-by: Barnabás Czémán >--- >Dmitry Baryshkov (1): > drm/msm/dpu: add support for MSM8953 > >Konrad Dybcio (1): > drm/msm/dpu: Add MSM8996 support > > .../drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 218 + > .../drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h| 348 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 106 +++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 2 + > drivers/gpu/drm/msm/msm_drv.c | 2 + > 6 files changed, 678 insertions(+) >--- >base-commit: df9574a57d02b265322e77fb8628d4d33641dda9 >change-id: 20240528-dpu-msm8953-msm8996-5d0fb7e387b8 > >Best regards,
[PATCH v3] drm/msm/adreno: Add A306A support
From: Otto Pflüger
Add support for Adreno 306A GPU what is found in MSM8917 SoC.
This GPU marketing name is Adreno 308.
Signed-off-by: Otto Pflüger
[use internal name of the GPU, reword the commit message]
Reviewed-by: Konrad Dybcio
Signed-off-by: Barnabás Czémán
---
Changes in v3:
- Fix issues addressed by reviews.
- Rebase on latest next.
- Link to v2:
https://lore.kernel.org/r/20240620-a306a-v2-1-0d388e1de...@gmail.com
Changes in v2:
- Rebase on https://patchwork.freedesktop.org/series/127393/
- Link to v1:
https://lore.kernel.org/r/20240528-a306a-v1-1-03a66dacd...@gmail.com
---
drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 11 +++
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 14 +++---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++
3 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
index 0de8465b6cf0..2eb6c3e93748 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
@@ -41,6 +41,17 @@ static const struct adreno_info a3xx_gpus[] = {
.gmem = SZ_128K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a3xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x03000620),
+ .family = ADRENO_3XX,
+ .revn = 308,
+ .fw = {
+ [ADRENO_FW_PM4] = "a300_pm4.fw",
+ [ADRENO_FW_PFP] = "a300_pfp.fw",
+ },
+ .gmem = SZ_128K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a3xx_gpu_init,
}, {
.chip_ids = ADRENO_CHIP_IDS(
0x0302,
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 5273dc849838..b46ff49f47cf 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -145,6 +145,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x000a);
gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x000a);
+ } else if (adreno_is_a306a(adreno_gpu)) {
+ gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
+ gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0010);
+ gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0010);
} else if (adreno_is_a320(adreno_gpu)) {
/* Set up 16 deep read/write request queues: */
gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
@@ -237,7 +241,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x0001);
/* Enable Clock gating: */
- if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu))
+ if (adreno_is_a305b(adreno_gpu) ||
+ adreno_is_a306(adreno_gpu) ||
+ adreno_is_a306a(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0x);
else if (adreno_is_a320(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfff);
@@ -334,8 +340,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
- if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) ||
- adreno_is_a320(adreno_gpu)) {
+ if (adreno_is_a305(adreno_gpu) ||
+ adreno_is_a306(adreno_gpu) ||
+ adreno_is_a306a(adreno_gpu) ||
+ adreno_is_a320(adreno_gpu)) {
gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 1ab523a163a0..c3b7970c2bfa 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -294,6 +294,12 @@ static inline bool adreno_is_a306(const struct adreno_gpu
*gpu)
return adreno_is_revn(gpu, 307);
}
+static inline bool adreno_is_a306a(const struct adreno_gpu *gpu)
+{
+ /* a306a (marketing name is a308) */
+ return adreno_is_revn(gpu, 308);
+}
+
static inline bool adreno_is_a320(const struct adreno_gpu *gpu)
{
return adreno_is_revn(gpu, 320);
---
base-commit: dee7f101b64219f512bb2f842227bd04c14efe30
change-id: 20240528-a306a-48e173724d6c
Best regards,
--
Barnabás Czémán
Re: [PATCH v2] drm/msm/adreno: Add A306A support
On Sat, Jun 22, 2024 at 1:36 PM Konrad Dybcio wrote:
>
> On 20.06.2024 11:52 PM, Barnabás Czémán wrote:
> > From: Otto Pflüger
> >
> > Add support for Adreno 306A GPU what is found in MSM8917 SoC.
> > This GPU marketing name is Adreno 308.
> >
> > Signed-off-by: Otto Pflüger
> > [use internal name of the GPU, reword the commit message]
> > Signed-off-by: Barnabás Czémán
> > ---
> > Changes in v2:
> > - Rebase on https://patchwork.freedesktop.org/series/127393/
> > - Link to v1:
> > https://lore.kernel.org/r/20240528-a306a-v1-1-03a66dacd...@gmail.com
> > ---
> > drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 11 +++
> > drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 14 +++---
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++
> > 3 files changed, 28 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> > b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> > index 0de8465b6cf0..61aeac5054a2 100644
> > --- a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> > +++ b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> > @@ -41,6 +41,17 @@ static const struct adreno_info a3xx_gpus[] = {
> > .gmem = SZ_128K,
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a3xx_gpu_init,
> > + }, {
> > + .chip_ids = ADRENO_CHIP_IDS(0x03000620),
> > + .family = ADRENO_3XX,
> > + .revn = 308,
>
> Double space
It is similar like other blocks.
>
> > + .fw = {
> > + [ADRENO_FW_PM4] = "a300_pm4.fw",
> > + [ADRENO_FW_PFP] = "a300_pfp.fw",
> > + },
> > + .gmem = SZ_128K,
> > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .init = a3xx_gpu_init,
> > }, {
> > .chip_ids = ADRENO_CHIP_IDS(
> > 0x0302,
> > diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> > b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> > index 5273dc849838..b46ff49f47cf 100644
> > --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> > @@ -145,6 +145,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
> > gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
> > gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x000a);
> > gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x000a);
> > + } else if (adreno_is_a306a(adreno_gpu)) {
> > + gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
> > + gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0010);
> > + gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0010);
> > } else if (adreno_is_a320(adreno_gpu)) {
> > /* Set up 16 deep read/write request queues: */
> > gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
> > @@ -237,7 +241,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
> > gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x0001);
> >
> > /* Enable Clock gating: */
> > - if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu))
> > + if (adreno_is_a305b(adreno_gpu) ||
> > + adreno_is_a306(adreno_gpu) ||
> > + adreno_is_a306a(adreno_gpu))
> > gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0x);
> > else if (adreno_is_a320(adreno_gpu))
> > gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfff);
> > @@ -334,8 +340,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
> > gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
> >
> > /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
> > - if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) ||
> > - adreno_is_a320(adreno_gpu)) {
> > + if (adreno_is_a305(adreno_gpu) ||
> > + adreno_is_a306(adreno_gpu) ||
> > + adreno_is_a306a(adreno_gpu) ||
> > + adreno_is_a320(adreno_gpu)) {
> > gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
> > AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
> > AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index b8ee9320a315..3b361a077688 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++
[PATCH v3] drm/msm/adreno: Add support for Adreno 505 GPU
From: Daniil Titov
This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz),
SDM439 (650 MHz).
Signed-off-by: Daniil Titov
Reviewed-by: Konrad Dybcio
Signed-off-by: Barnabás Czémán
---
Changes in v3:
- Rebase on the latest linux-next.
- Link to v2:
https://lore.kernel.org/r/20240604-a505-v2-1-dfa599a4d...@gmail.com
Changes in v2:
- use DRM_MSM_INACTIVE_PERIOD instead of 250 ms.
- Link to v1:
https://lore.kernel.org/r/20240604-a505-v1-1-82ee1c04d...@gmail.com
---
drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 13 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 29 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +
3 files changed, 35 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
index 455a953dee67..633f31539162 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
@@ -10,6 +10,19 @@
static const struct adreno_info a5xx_gpus[] = {
{
+ .chip_ids = ADRENO_CHIP_IDS(0x05000500),
+ .family = ADRENO_5XX,
+ .revn = 505,
+ .fw = {
+ [ADRENO_FW_PM4] = "a530_pm4.fw",
+ [ADRENO_FW_PFP] = "a530_pfp.fw",
+ },
+ .gmem = (SZ_128K + SZ_8K),
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
+ ADRENO_QUIRK_LMLOADKILL_DISABLE,
+ .init = a5xx_gpu_init,
+ }, {
.chip_ids = ADRENO_CHIP_IDS(0x05000600),
.family = ADRENO_5XX,
.revn = 506,
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index c003f970189b..c0b5373e90d7 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -439,7 +439,8 @@ void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
const struct adreno_five_hwcg_regs *regs;
unsigned int i, sz;
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu)) {
regs = a50x_hwcg;
sz = ARRAY_SIZE(a50x_hwcg);
} else if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu)) {
@@ -483,7 +484,8 @@ static int a5xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x);
/* Specify workarounds for various microcode issues */
- if (adreno_is_a506(adreno_gpu) || adreno_is_a530(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a530(adreno_gpu)) {
/* Workaround for token end syncs
* Force a WFI after every direct-render 3D mode draw and every
* 2D mode 3 draw
@@ -752,10 +754,11 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
0x0010 + adreno_gpu->info->gmem - 1);
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x);
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
- adreno_is_a510(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) {
gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20);
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu))
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
else
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
@@ -771,7 +774,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
}
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu))
gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
(0x100 << 11 | 0x100 << 22));
else if (adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) ||
@@ -789,8 +793,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
* Disable the RB sampler datapath DP2 clock gating optimization
* for 1-SP GPUs, as it is enabled by default.
*/
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
- adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||
+ adreno_is_a512(adreno_gpu))
gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CN
[PATCH 1/2] drm/msm/dpu: Add MSM8996 support
From: Konrad Dybcio
Add support for MSM8996, which - fun fact - was the SoC that this driver
(or rather SDE, its downstream origin) was meant for and first tested on.
It has some hardware that differs from the modern SoCs, so not a lot of
current structs could have been reused. It's also seemingly the only SoC
supported by DPU that uses RGB pipes.
Note, by default this platform is still handled by the MDP5 driver
unless the `msm.prefer_mdp5=false' parameter is provided.
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
[DB: rebased on top of sblk changes, add dpu_rgb_sblk]
Signed-off-by: Dmitry Baryshkov
[Removed intr_start from CTLs config]
Signed-off-by: Barnabás Czémán
---
.../drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h| 348 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 94 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
drivers/gpu/drm/msm/msm_drv.c | 1 +
5 files changed, 445 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
new file mode 100644
index ..29d0cfacf7a9
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
@@ -0,0 +1,348 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_1_7_MSM8996_H
+#define _DPU_1_7_MSM8996_H
+
+static const struct dpu_caps msm8996_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .has_src_split = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_mdp_cfg msm8996_mdp[] = {
+ {
+ .name = "top_0",
+ .base = 0x0, .len = 0x454,
+ .features = BIT(DPU_MDP_VSYNC_SEL),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0
},
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0
},
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0
},
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0
},
+ [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4
},
+ [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4
},
+ [DPU_CLK_CTRL_RGB2] = { .reg_off = 0x2bc, .bit_off = 4
},
+ [DPU_CLK_CTRL_RGB3] = { .reg_off = 0x2c4, .bit_off = 4
},
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8
},
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8
},
+ [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off =
16 },
+ [DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off =
16 },
+ },
+ },
+};
+
+static const struct dpu_ctl_cfg msm8996_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x64,
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x64,
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x64,
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x64,
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x64,
+ },
+};
+
+static const struct dpu_sspp_cfg msm8996_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x150,
+ .features = VIG_MSM8996_MASK,
+ .sblk = &dpu_vig_sblk_qseed2,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x150,
+ .features = VIG_MSM8996_MASK,
+ .sblk = &dpu_vig_sblk_qseed2,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x150,
+ .features = VIG_MSM8996_MASK,
+ .sblk = &dpu_vig_sblk_qseed2,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VI
[PATCH 2/2] drm/msm/dpu: add support for MSM8953
From: Dmitry Baryshkov
Add support for MSM8953, which has MDP5 v1.16. It looks like
trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC,
etc.
Signed-off-by: Dmitry Baryshkov
[Remove intr_start from CTLs config, reword the commit]
Signed-off-by: Barnabás Czémán
---
.../drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 218 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
drivers/gpu/drm/msm/msm_drv.c | 1 +
5 files changed, 233 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
new file mode 100644
index ..14f36ea6ad0e
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_1_16_MSM8953_H
+#define _DPU_1_16_MSM8953_H
+
+static const struct dpu_caps msm8953_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
+ .max_mixer_blendstages = 0x4,
+ .max_linewidth = DEFAULT_DPU_LINE_WIDTH,
+ .pixel_ram_size = 40 * 1024,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_mdp_cfg msm8953_mdp[] = {
+ {
+ .name = "top_0",
+ .base = 0x0, .len = 0x454,
+ .features = BIT(DPU_MDP_VSYNC_SEL),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0
},
+ [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4
},
+ [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4
},
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8
},
+ [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off =
16 },
+ },
+ },
+};
+
+static const struct dpu_ctl_cfg msm8953_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x64,
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x64,
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x64,
+ },
+};
+
+static const struct dpu_sspp_cfg msm8953_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x150,
+ .features = VIG_MSM8953_MASK,
+ .sblk = &dpu_vig_sblk_qseed2,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_4", .id = SSPP_RGB0,
+ .base = 0x14000, .len = 0x150,
+ .features = RGB_MSM8953_MASK,
+ .sblk = &dpu_rgb_sblk,
+ .xin_id = 1,
+ .type = SSPP_TYPE_RGB,
+ .clk_ctrl = DPU_CLK_CTRL_RGB0,
+ }, {
+ .name = "sspp_5", .id = SSPP_RGB1,
+ .base = 0x16000, .len = 0x150,
+ .features = RGB_MSM8953_MASK,
+ .sblk = &dpu_rgb_sblk,
+ .xin_id = 5,
+ .type = SSPP_TYPE_RGB,
+ .clk_ctrl = DPU_CLK_CTRL_RGB1,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x150,
+ .features = DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR),
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 2,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ },
+};
+
+static const struct dpu_lm_cfg msm8953_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ },
+};
+
+static const struct dpu_pingpong_cfg msm8953_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x7, .len = 0xd4,
+ .features = PINGPONG_MSM8996_MASK,
+ .sblk = &msm8996_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+
[PATCH 0/2] Add MSM8996/MSM8953 dpu catalog
This patch series add dpu support for MSM8996/MSM8953 devices. Note, by default these platforms are still handled by the MDP5 driver unless the `msm.prefer_mdp5=false' parameter is provided. Signed-off-by: Barnabás Czémán --- Dmitry Baryshkov (1): drm/msm/dpu: add support for MSM8953 Konrad Dybcio (1): drm/msm/dpu: Add MSM8996 support .../drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 218 + .../drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h| 348 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 106 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 2 + drivers/gpu/drm/msm/msm_drv.c | 2 + 6 files changed, 678 insertions(+) --- base-commit: df9574a57d02b265322e77fb8628d4d33641dda9 change-id: 20240528-dpu-msm8953-msm8996-5d0fb7e387b8 Best regards, -- Barnabás Czémán
[PATCH] drm/msm/mdp5: Remove MDP_CAP_SRC_SPLIT from msm8x53_config
Remove MDP_CAP_SRC_SPLIT from msm8x53_config because
it is not referenced in downstream.
Fixes: fb25d4474fa0 ("drm/msm/mdp5: Add configuration for MDP v1.16")
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
index c5179e4c393c..92d06b7faa0a 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
@@ -837,8 +837,7 @@ static const struct mdp5_cfg_hw msm8x53_config = {
.name = "msm8x53",
.mdp = {
.count = 1,
- .caps = MDP_CAP_CDM |
- MDP_CAP_SRC_SPLIT,
+ .caps = MDP_CAP_CDM,
},
.ctl = {
.count = 3,
---
base-commit: f76698bd9a8ca01d3581236082d786e9a6b72bb7
change-id: 20240624-msm8953-mdp-fix-8af4ec159082
Best regards,
--
Barnabás Czémán
[PATCH v2 4/4] drm/msm/dsi: Add phy configuration for MSM8937
From: Daniil Titov
Add phy configuration for 28nm dsi phy found on MSM8937 SoC. Only
difference from existing msm8916 configuration is number of phy
and io_start addresses.
Signed-off-by: Daniil Titov
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 18 ++
3 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 24a347fe2998..dd58bc0a49eb 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -545,6 +545,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_28nm_lp_cfgs },
{ .compatible = "qcom,dsi-phy-28nm-8226",
.data = &dsi_phy_28nm_8226_cfgs },
+ { .compatible = "qcom,dsi-phy-28nm-8937",
+ .data = &dsi_phy_28nm_8937_cfgs },
#endif
#ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
{ .compatible = "qcom,dsi-phy-20nm",
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 5a5dc3faa971..a9b4eb2c0e8c 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -47,6 +47,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index ceec7bb87bf1..3afc8b1c9bdf 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -917,3 +917,21 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs = {
.num_dsi_phy = 1,
.quirks = DSI_PHY_28NM_QUIRK_PHY_8226,
};
+
+const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs = {
+ .has_phy_regulator = true,
+ .regulator_data = dsi_phy_28nm_regulators,
+ .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators),
+ .ops = {
+ .enable = dsi_28nm_phy_enable,
+ .disable = dsi_28nm_phy_disable,
+ .pll_init = dsi_pll_28nm_init,
+ .save_pll_state = dsi_28nm_pll_save_state,
+ .restore_pll_state = dsi_28nm_pll_restore_state,
+ },
+ .min_pll_rate = VCO_MIN_RATE,
+ .max_pll_rate = VCO_MAX_RATE,
+ .io_start = { 0x1a94400, 0x1a96400 },
+ .num_dsi_phy = 2,
+ .quirks = DSI_PHY_28NM_QUIRK_PHY_LP,
+};
--
2.45.2
[PATCH v2 3/4] dt-bindings: msm: dsi-phy-28nm: Document msm8937 compatible
The MSM8937 SoC uses a slightly different 28nm dsi phy. Add a new compatible for it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Barnabás Czémán --- Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml | 1 + Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml| 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml index 288d8babb76a..a55c2445d189 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - qcom,dsi-phy-28nm-8226 + - qcom,dsi-phy-28nm-8937 - qcom,dsi-phy-28nm-8960 - qcom,dsi-phy-28nm-hpm - qcom,dsi-phy-28nm-hpm-fam-b diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml index e4576546bf0d..7c6462caa442 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -126,6 +126,7 @@ patternProperties: - qcom,dsi-phy-14nm-8953 - qcom,dsi-phy-20nm - qcom,dsi-phy-28nm-8226 + - qcom,dsi-phy-28nm-8937 - qcom,dsi-phy-28nm-hpm - qcom,dsi-phy-28nm-hpm-fam-b - qcom,dsi-phy-28nm-lp -- 2.45.2
[PATCH v2 2/4] drm/msm/mdp5: Add MDP5 configuration for MSM8937
From: Daniil Titov
Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
Signed-off-by: Daniil Titov
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 88
1 file changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
index c5179e4c393c..fac8e276da52 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
@@ -1011,6 +1011,93 @@ static const struct mdp5_cfg_hw msm8917_config = {
.max_clk = 32000,
};
+static const struct mdp5_cfg_hw msm8937_config = {
+ .name = "msm8937",
+ .mdp = {
+ .count = 1,
+ .caps = MDP_CAP_CDM,
+ },
+ .ctl = {
+ .count = 3,
+ .base = { 0x01000, 0x01200, 0x01400 },
+ .flush_hw_mask = 0x,
+ },
+ .pipe_vig = {
+ .count = 1,
+ .base = { 0x04000 },
+ .caps = MDP_PIPE_CAP_HFLIP |
+ MDP_PIPE_CAP_VFLIP |
+ MDP_PIPE_CAP_SCALE |
+ MDP_PIPE_CAP_CSC|
+ MDP_PIPE_CAP_DECIMATION |
+ MDP_PIPE_CAP_SW_PIX_EXT |
+ 0,
+ },
+ .pipe_rgb = {
+ .count = 2,
+ .base = { 0x14000, 0x16000 },
+ .caps = MDP_PIPE_CAP_HFLIP |
+ MDP_PIPE_CAP_VFLIP |
+ MDP_PIPE_CAP_DECIMATION |
+ MDP_PIPE_CAP_SW_PIX_EXT |
+ 0,
+ },
+ .pipe_dma = {
+ .count = 1,
+ .base = { 0x24000 },
+ .caps = MDP_PIPE_CAP_HFLIP |
+ MDP_PIPE_CAP_VFLIP |
+ MDP_PIPE_CAP_SW_PIX_EXT |
+ 0,
+ },
+ .pipe_cursor = {
+ .count = 1,
+ .base = { 0x34000 },
+ .caps = MDP_PIPE_CAP_HFLIP |
+ MDP_PIPE_CAP_VFLIP |
+ MDP_PIPE_CAP_SW_PIX_EXT |
+ MDP_PIPE_CAP_CURSOR |
+ 0,
+ },
+
+ .lm = {
+ .count = 2,
+ .base = { 0x44000, 0x45000 },
+ .instances = {
+ { .id = 0, .pp = 0, .dspp = 0,
+ .caps = MDP_LM_CAP_DISPLAY |
+ MDP_LM_CAP_PAIR },
+ { .id = 1, .pp = 1, .dspp = -1,
+ .caps = MDP_LM_CAP_DISPLAY },
+},
+ .nb_stages = 5,
+ .max_width = 2048,
+ .max_height = 0x,
+ },
+ .dspp = {
+ .count = 1,
+ .base = { 0x54000 },
+
+ },
+ .pp = {
+ .count = 2,
+ .base = { 0x7, 0x70800 },
+ },
+ .cdm = {
+ .count = 1,
+ .base = { 0x79200 },
+ },
+ .intf = {
+ .base = { 0x0, 0x6a800, 0x6b000 },
+ .connect = {
+ [0] = INTF_DISABLED,
+ [1] = INTF_DSI,
+ [2] = INTF_DSI,
+ },
+ },
+ .max_clk = 32000,
+};
+
static const struct mdp5_cfg_hw msm8998_config = {
.name = "msm8998",
.mdp = {
@@ -1325,6 +1412,7 @@ static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
{ .revision = 9, .config = { .hw = &msm8x94_config } },
{ .revision = 7, .config = { .hw = &msm8x96_config } },
{ .revision = 11, .config = { .hw = &msm8x76_config } },
+ { .revision = 14, .config = { .hw = &msm8937_config } },
{ .revision = 15, .config = { .hw = &msm8917_config } },
{ .revision = 16, .config = { .hw = &msm8x53_config } },
};
--
2.45.2
[PATCH v2 1/4] dt-bindings: display/msm: qcom, mdp5: Add msm8937 compatible
Add the compatible for the MDP5 found on MSM8937. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Barnabás Czémán --- Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml index 91c774f106ce..e153f8d26e7a 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml @@ -25,6 +25,7 @@ properties: - qcom,msm8226-mdp5 - qcom,msm8916-mdp5 - qcom,msm8917-mdp5 + - qcom,msm8937-mdp5 - qcom,msm8953-mdp5 - qcom,msm8974-mdp5 - qcom,msm8976-mdp5 -- 2.45.2
[PATCH v2 0/4] MSM8937 MDP/DSI PHY enablement
This patch series adds support for the MDP and DSI PHY as found on the MSM8937 platform. Signed-off-by: Barnabás Czémán --- Changes in v2: - Remove MDP_CAP_SRC_SPLIT from mdp5_cfg - Link to v1: https://lore.kernel.org/r/20240623-dsi-v1-0-4ab560eb5...@gmail.com --- Barnabás Czémán (2): dt-bindings: display/msm: qcom, mdp5: Add msm8937 compatible dt-bindings: msm: dsi-phy-28nm: Document msm8937 compatible Daniil Titov (2): drm/msm/mdp5: Add MDP5 configuration for MSM8937 drm/msm/dsi: Add phy configuration for MSM8937 .../bindings/display/msm/dsi-phy-28nm.yaml | 1 + .../devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 + .../devicetree/bindings/display/msm/qcom,mdss.yaml | 1 + drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 88 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 18 + 7 files changed, 112 insertions(+) --- base-commit: f76698bd9a8ca01d3581236082d786e9a6b72bb7 change-id: 20240607-dsi-851ebb226a8d Best regards, -- Barnabás Czémán
Re: [PATCH 2/4] drm/msm/mdp5: Add MDP5 configuration for MSM8937
On Sun, Jun 23, 2024 at 7:59 AM Dmitry Baryshkov
wrote:
>
> On Sun, Jun 23, 2024 at 01:25:52AM GMT, Barnabás Czémán wrote:
> > From: Daniil Titov
> >
> > Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
> >
> > Signed-off-by: Daniil Titov
> > Signed-off-by: Barnabás Czémán
> > ---
> > drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 89
> >
> > 1 file changed, 89 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
> > b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
> > index c5179e4c393c..6413c0d3e237 100644
> > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
> > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
> > @@ -1011,6 +1011,94 @@ static const struct mdp5_cfg_hw msm8917_config = {
> > .max_clk = 32000,
> > };
> >
> > +static const struct mdp5_cfg_hw msm8937_config = {
> > + .name = "msm8937",
> > + .mdp = {
> > + .count = 1,
> > + .caps = MDP_CAP_CDM |
> > + MDP_CAP_SRC_SPLIT,
>
> Could you please point out the SRC_SPLIT reference?
Is this would be qcom,mdss-has-source-split in downstream, because if
it is i think it is a mistake and it is wrong at msm8953 also.
>
> Other than that LGTM
>
> --
> With best wishes
> Dmitry
[PATCH 3/4] dt-bindings: msm: dsi-phy-28nm: Document msm8937 compatible
The MSM8937 SoC uses a slightly different 28nm dsi phy. Add a new compatible for it. Signed-off-by: Barnabás Czémán --- Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml | 1 + Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml| 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml index 288d8babb76a..a55c2445d189 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - qcom,dsi-phy-28nm-8226 + - qcom,dsi-phy-28nm-8937 - qcom,dsi-phy-28nm-8960 - qcom,dsi-phy-28nm-hpm - qcom,dsi-phy-28nm-hpm-fam-b diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml index e4576546bf0d..7c6462caa442 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -126,6 +126,7 @@ patternProperties: - qcom,dsi-phy-14nm-8953 - qcom,dsi-phy-20nm - qcom,dsi-phy-28nm-8226 + - qcom,dsi-phy-28nm-8937 - qcom,dsi-phy-28nm-hpm - qcom,dsi-phy-28nm-hpm-fam-b - qcom,dsi-phy-28nm-lp -- 2.45.2
[PATCH 4/4] drm/msm/dsi: Add phy configuration for MSM8937
From: Daniil Titov
Add phy configuration for 28nm dsi phy found on MSM8937 SoC. Only
difference from existing msm8916 configuration is number of phy
and io_start addresses.
Signed-off-by: Daniil Titov
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 18 ++
3 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 24a347fe2998..dd58bc0a49eb 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -545,6 +545,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_28nm_lp_cfgs },
{ .compatible = "qcom,dsi-phy-28nm-8226",
.data = &dsi_phy_28nm_8226_cfgs },
+ { .compatible = "qcom,dsi-phy-28nm-8937",
+ .data = &dsi_phy_28nm_8937_cfgs },
#endif
#ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
{ .compatible = "qcom,dsi-phy-20nm",
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 5a5dc3faa971..a9b4eb2c0e8c 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -47,6 +47,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index ceec7bb87bf1..3afc8b1c9bdf 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -917,3 +917,21 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs = {
.num_dsi_phy = 1,
.quirks = DSI_PHY_28NM_QUIRK_PHY_8226,
};
+
+const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs = {
+ .has_phy_regulator = true,
+ .regulator_data = dsi_phy_28nm_regulators,
+ .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators),
+ .ops = {
+ .enable = dsi_28nm_phy_enable,
+ .disable = dsi_28nm_phy_disable,
+ .pll_init = dsi_pll_28nm_init,
+ .save_pll_state = dsi_28nm_pll_save_state,
+ .restore_pll_state = dsi_28nm_pll_restore_state,
+ },
+ .min_pll_rate = VCO_MIN_RATE,
+ .max_pll_rate = VCO_MAX_RATE,
+ .io_start = { 0x1a94400, 0x1a96400 },
+ .num_dsi_phy = 2,
+ .quirks = DSI_PHY_28NM_QUIRK_PHY_LP,
+};
--
2.45.2
[PATCH 1/4] dt-bindings: display/msm: qcom, mdp5: Add msm8937 compatible
Add the compatible for the MDP5 found on MSM8937. Signed-off-by: Barnabás Czémán --- Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml index 91c774f106ce..e153f8d26e7a 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml @@ -25,6 +25,7 @@ properties: - qcom,msm8226-mdp5 - qcom,msm8916-mdp5 - qcom,msm8917-mdp5 + - qcom,msm8937-mdp5 - qcom,msm8953-mdp5 - qcom,msm8974-mdp5 - qcom,msm8976-mdp5 -- 2.45.2
[PATCH 2/4] drm/msm/mdp5: Add MDP5 configuration for MSM8937
From: Daniil Titov
Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937.
Signed-off-by: Daniil Titov
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 89
1 file changed, 89 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
index c5179e4c393c..6413c0d3e237 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
@@ -1011,6 +1011,94 @@ static const struct mdp5_cfg_hw msm8917_config = {
.max_clk = 32000,
};
+static const struct mdp5_cfg_hw msm8937_config = {
+ .name = "msm8937",
+ .mdp = {
+ .count = 1,
+ .caps = MDP_CAP_CDM |
+ MDP_CAP_SRC_SPLIT,
+ },
+ .ctl = {
+ .count = 3,
+ .base = { 0x01000, 0x01200, 0x01400 },
+ .flush_hw_mask = 0x,
+ },
+ .pipe_vig = {
+ .count = 1,
+ .base = { 0x04000 },
+ .caps = MDP_PIPE_CAP_HFLIP |
+ MDP_PIPE_CAP_VFLIP |
+ MDP_PIPE_CAP_SCALE |
+ MDP_PIPE_CAP_CSC|
+ MDP_PIPE_CAP_DECIMATION |
+ MDP_PIPE_CAP_SW_PIX_EXT |
+ 0,
+ },
+ .pipe_rgb = {
+ .count = 2,
+ .base = { 0x14000, 0x16000 },
+ .caps = MDP_PIPE_CAP_HFLIP |
+ MDP_PIPE_CAP_VFLIP |
+ MDP_PIPE_CAP_DECIMATION |
+ MDP_PIPE_CAP_SW_PIX_EXT |
+ 0,
+ },
+ .pipe_dma = {
+ .count = 1,
+ .base = { 0x24000 },
+ .caps = MDP_PIPE_CAP_HFLIP |
+ MDP_PIPE_CAP_VFLIP |
+ MDP_PIPE_CAP_SW_PIX_EXT |
+ 0,
+ },
+ .pipe_cursor = {
+ .count = 1,
+ .base = { 0x34000 },
+ .caps = MDP_PIPE_CAP_HFLIP |
+ MDP_PIPE_CAP_VFLIP |
+ MDP_PIPE_CAP_SW_PIX_EXT |
+ MDP_PIPE_CAP_CURSOR |
+ 0,
+ },
+
+ .lm = {
+ .count = 2,
+ .base = { 0x44000, 0x45000 },
+ .instances = {
+ { .id = 0, .pp = 0, .dspp = 0,
+ .caps = MDP_LM_CAP_DISPLAY |
+ MDP_LM_CAP_PAIR },
+ { .id = 1, .pp = 1, .dspp = -1,
+ .caps = MDP_LM_CAP_DISPLAY },
+},
+ .nb_stages = 5,
+ .max_width = 2048,
+ .max_height = 0x,
+ },
+ .dspp = {
+ .count = 1,
+ .base = { 0x54000 },
+
+ },
+ .pp = {
+ .count = 2,
+ .base = { 0x7, 0x70800 },
+ },
+ .cdm = {
+ .count = 1,
+ .base = { 0x79200 },
+ },
+ .intf = {
+ .base = { 0x0, 0x6a800, 0x6b000 },
+ .connect = {
+ [0] = INTF_DISABLED,
+ [1] = INTF_DSI,
+ [2] = INTF_DSI,
+ },
+ },
+ .max_clk = 32000,
+};
+
static const struct mdp5_cfg_hw msm8998_config = {
.name = "msm8998",
.mdp = {
@@ -1325,6 +1413,7 @@ static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
{ .revision = 9, .config = { .hw = &msm8x94_config } },
{ .revision = 7, .config = { .hw = &msm8x96_config } },
{ .revision = 11, .config = { .hw = &msm8x76_config } },
+ { .revision = 14, .config = { .hw = &msm8937_config } },
{ .revision = 15, .config = { .hw = &msm8917_config } },
{ .revision = 16, .config = { .hw = &msm8x53_config } },
};
--
2.45.2
[PATCH 0/4] MSM8937 MDP/DSI PHY enablement
This patch series adds support for the MDP and DSI PHY as found on the MSM8937 platform. Signed-off-by: Barnabás Czémán --- Barnabás Czémán (2): dt-bindings: display/msm: qcom, mdp5: Add msm8937 compatible dt-bindings: msm: dsi-phy-28nm: Document msm8937 compatible Daniil Titov (2): drm/msm/mdp5: Add MDP5 configuration for MSM8937 drm/msm/dsi: Add phy configuration for MSM8937 .../bindings/display/msm/dsi-phy-28nm.yaml | 1 + .../devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 + .../devicetree/bindings/display/msm/qcom,mdss.yaml | 1 + drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 89 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 18 + 7 files changed, 113 insertions(+) --- base-commit: f76698bd9a8ca01d3581236082d786e9a6b72bb7 change-id: 20240607-dsi-851ebb226a8d Best regards, -- Barnabás Czémán
[PATCH v2] drm/msm/adreno: Add A306A support
From: Otto Pflüger
Add support for Adreno 306A GPU what is found in MSM8917 SoC.
This GPU marketing name is Adreno 308.
Signed-off-by: Otto Pflüger
[use internal name of the GPU, reword the commit message]
Signed-off-by: Barnabás Czémán
---
Changes in v2:
- Rebase on https://patchwork.freedesktop.org/series/127393/
- Link to v1:
https://lore.kernel.org/r/20240528-a306a-v1-1-03a66dacd...@gmail.com
---
drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 11 +++
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 14 +++---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++
3 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
index 0de8465b6cf0..61aeac5054a2 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
@@ -41,6 +41,17 @@ static const struct adreno_info a3xx_gpus[] = {
.gmem = SZ_128K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a3xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x03000620),
+ .family = ADRENO_3XX,
+ .revn = 308,
+ .fw = {
+ [ADRENO_FW_PM4] = "a300_pm4.fw",
+ [ADRENO_FW_PFP] = "a300_pfp.fw",
+ },
+ .gmem = SZ_128K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a3xx_gpu_init,
}, {
.chip_ids = ADRENO_CHIP_IDS(
0x0302,
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 5273dc849838..b46ff49f47cf 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -145,6 +145,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x000a);
gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x000a);
+ } else if (adreno_is_a306a(adreno_gpu)) {
+ gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
+ gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0010);
+ gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0010);
} else if (adreno_is_a320(adreno_gpu)) {
/* Set up 16 deep read/write request queues: */
gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
@@ -237,7 +241,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x0001);
/* Enable Clock gating: */
- if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu))
+ if (adreno_is_a305b(adreno_gpu) ||
+ adreno_is_a306(adreno_gpu) ||
+ adreno_is_a306a(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0x);
else if (adreno_is_a320(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfff);
@@ -334,8 +340,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
- if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) ||
- adreno_is_a320(adreno_gpu)) {
+ if (adreno_is_a305(adreno_gpu) ||
+ adreno_is_a306(adreno_gpu) ||
+ adreno_is_a306a(adreno_gpu) ||
+ adreno_is_a320(adreno_gpu)) {
gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index b8ee9320a315..3b361a077688 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -292,6 +292,12 @@ static inline bool adreno_is_a306(const struct adreno_gpu
*gpu)
return adreno_is_revn(gpu, 307);
}
+static inline bool adreno_is_a306a(const struct adreno_gpu *gpu)
+{
+ /* a306a marketing name is a308 */
+ return adreno_is_revn(gpu, 308);
+}
+
static inline bool adreno_is_a320(const struct adreno_gpu *gpu)
{
return adreno_is_revn(gpu, 320);
---
base-commit: b992b79ca8bc336fa8e2c80990b5af80ed8f36fd
change-id: 20240528-a306a-48e173724d6c
prerequisite-message-id: <20240618164303.66615-1-robdcl...@gmail.com>
prerequisite-patch-id: b26cd6e5aa23ea623fec94f938a06d1e3359de55
prerequisite-patch-id: 301e8fe4c2687a4606ee7debce95a5ada732e27f
prerequisite-patch-id: 24a5654d9b52079c010b0594d8599d84af1659c7
prerequisite-patch-id: b09a3d28d04b7ebe968e05835ebf8397c27f8d7d
prerequisite-patch-id: a74556e25862c22f0ec543b8a7c7d92cb2e55099
[PATCH v2] drm/msm/adreno: Add support for Adreno 505 GPU
From: Daniil Titov
This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz),
SDM439 (650 MHz).
Signed-off-by: Daniil Titov
Signed-off-by: Barnabás Czémán
---
Changes in v2:
- use DRM_MSM_INACTIVE_PERIOD instead of 250 ms.
- Link to v1:
https://lore.kernel.org/r/20240604-a505-v1-1-82ee1c04d...@gmail.com
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 29 +
drivers/gpu/drm/msm/adreno/adreno_device.c | 13 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 5 +
3 files changed, 35 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index c003f970189b..c0b5373e90d7 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -439,7 +439,8 @@ void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
const struct adreno_five_hwcg_regs *regs;
unsigned int i, sz;
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu)) {
regs = a50x_hwcg;
sz = ARRAY_SIZE(a50x_hwcg);
} else if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu)) {
@@ -483,7 +484,8 @@ static int a5xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x);
/* Specify workarounds for various microcode issues */
- if (adreno_is_a506(adreno_gpu) || adreno_is_a530(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a530(adreno_gpu)) {
/* Workaround for token end syncs
* Force a WFI after every direct-render 3D mode draw and every
* 2D mode 3 draw
@@ -752,10 +754,11 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
0x0010 + adreno_gpu->info->gmem - 1);
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x);
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
- adreno_is_a510(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) {
gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20);
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu))
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
else
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
@@ -771,7 +774,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
}
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu))
gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
(0x100 << 11 | 0x100 << 22));
else if (adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) ||
@@ -789,8 +793,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
* Disable the RB sampler datapath DP2 clock gating optimization
* for 1-SP GPUs, as it is enabled by default.
*/
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
- adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||
+ adreno_is_a512(adreno_gpu))
gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9));
/* Disable UCHE global filter as SP can invalidate/flush independently
*/
@@ -1345,7 +1350,7 @@ static int a5xx_pm_resume(struct msm_gpu *gpu)
if (ret)
return ret;
- /* Adreno 506, 508, 509, 510, 512 needs manual RBBM sus/res control */
+ /* Adreno 505, 506, 508, 509, 510, 512 needs manual RBBM sus/res
control */
if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) {
/* Halt the sp_input_clk at HM level */
gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x0055);
@@ -1388,9 +1393,9 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
u32 mask = 0xf;
int i, ret;
- /* A506, A508, A510 have 3 XIN ports in VBIF */
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
- adreno_is_a510(adreno_gpu))
+ /* A505, A506, A508, A510 have 3 XIN ports in VBIF */
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu))
mask = 0x7;
/* Clear the VBIF pipe before shutting down */
diff --g
Re: [PATCH] drm/msm/adreno: Add support for Adreno 505 GPU
On Tue, Jun 4, 2024 at 7:38 PM Konrad Dybcio wrote: > > > > On 6/4/24 19:33, Barnabás Czémán wrote: > > On Tue, Jun 4, 2024 at 7:06 PM Konrad Dybcio > > wrote: > >> > >> > >> > >> On 6/4/24 18:45, Barnabás Czémán wrote: > >>> On Tue, Jun 4, 2024 at 2:27 PM Barnabás Czémán wrote: > >>>> > >>>> On Tue, Jun 4, 2024 at 1:55 PM Konrad Dybcio > >>>> wrote: > >>>>> > >>>>> > >>>>> > >>>>> On 6/4/24 02:20, Barnabás Czémán wrote: > >>>>>> From: Daniil Titov > >>>>>> > >>>>>> This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz), > >>>>>> SDM439 (650 MHz). > >>>>>> > >>>>>> Signed-off-by: Daniil Titov > >>>>>> Signed-off-by: Barnabás Czémán > >>>>>> --- > >>>>> > >>>>> This all looks very good, just a nit > >>>>> > >>>>> [...] > >>>>> > >>>>>> + /* > >>>>>> + * Increase inactive period to 250 to avoid bouncing > >>>>>> + * the GDSC which appears to make it grumpy > >>>>>> + */ > >>>>>> + .inactive_period = 250, > >>>>> > >>>>> Are you sure this is actually necessary? > >>>> Every A5XX GPU is using the same value, but i have never tried with > >>>> DRM_MSM_INACTIVE_PERIOD. > >>> This was the original patch > >>> https://lore.kernel.org/all/20180507224750.9383-1-jcro...@codeaurora.org/ > >>> where the inactive period was increased for a530. I cannot test > >>> suspend on msm8937 yet. > >> > >> The suspend here refers to device suspend, not system suspend. Adreno > >> goes into device suspend every time you stop using it, i.e. after the > >> rendering is done and there's no more work to do. > >> > >> I suppose a good test scenario here would be to keep running and closing > >> kmscube in a rapid fashion and checking if the GPU starts crashing for > >> unknown reasons (the dmesg would denote that) > >> > > I have checked on a505 and a506 with this small script > > while true; do kmscube; kill kmscube; done > > none of them crashing, so i am going to change it. > > Hmm.. not sure if it actually idled when tested in a tight loop.. If you're > running bash, try "while true; do kmscube &; sleep 0.08; pkill -f kmscube; > sleep 0.08;done" > I see no crash > Konrad
Re: [PATCH] drm/msm/adreno: Add support for Adreno 505 GPU
On Tue, Jun 4, 2024 at 7:06 PM Konrad Dybcio wrote: > > > > On 6/4/24 18:45, Barnabás Czémán wrote: > > On Tue, Jun 4, 2024 at 2:27 PM Barnabás Czémán wrote: > >> > >> On Tue, Jun 4, 2024 at 1:55 PM Konrad Dybcio > >> wrote: > >>> > >>> > >>> > >>> On 6/4/24 02:20, Barnabás Czémán wrote: > >>>> From: Daniil Titov > >>>> > >>>> This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz), > >>>> SDM439 (650 MHz). > >>>> > >>>> Signed-off-by: Daniil Titov > >>>> Signed-off-by: Barnabás Czémán > >>>> --- > >>> > >>> This all looks very good, just a nit > >>> > >>> [...] > >>> > >>>> + /* > >>>> + * Increase inactive period to 250 to avoid bouncing > >>>> + * the GDSC which appears to make it grumpy > >>>> + */ > >>>> + .inactive_period = 250, > >>> > >>> Are you sure this is actually necessary? > >> Every A5XX GPU is using the same value, but i have never tried with > >> DRM_MSM_INACTIVE_PERIOD. > > This was the original patch > > https://lore.kernel.org/all/20180507224750.9383-1-jcro...@codeaurora.org/ > > where the inactive period was increased for a530. I cannot test > > suspend on msm8937 yet. > > The suspend here refers to device suspend, not system suspend. Adreno > goes into device suspend every time you stop using it, i.e. after the > rendering is done and there's no more work to do. > > I suppose a good test scenario here would be to keep running and closing > kmscube in a rapid fashion and checking if the GPU starts crashing for > unknown reasons (the dmesg would denote that) > I have checked on a505 and a506 with this small script while true; do kmscube; kill kmscube; done none of them crashing, so i am going to change it. > > I can check on msm8953 with a506 maybe if a506 works fine with > > DRM_MSM_INACTIVE_PERIOD > > then a505 would be fine with it also. > > The more testing the merrier :) > > Konrad
Re: [PATCH] drm/msm/adreno: Add support for Adreno 505 GPU
On Tue, Jun 4, 2024 at 2:27 PM Barnabás Czémán wrote: > > On Tue, Jun 4, 2024 at 1:55 PM Konrad Dybcio wrote: > > > > > > > > On 6/4/24 02:20, Barnabás Czémán wrote: > > > From: Daniil Titov > > > > > > This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz), > > > SDM439 (650 MHz). > > > > > > Signed-off-by: Daniil Titov > > > Signed-off-by: Barnabás Czémán > > > --- > > > > This all looks very good, just a nit > > > > [...] > > > > > + /* > > > + * Increase inactive period to 250 to avoid bouncing > > > + * the GDSC which appears to make it grumpy > > > + */ > > > + .inactive_period = 250, > > > > Are you sure this is actually necessary? > Every A5XX GPU is using the same value, but i have never tried with > DRM_MSM_INACTIVE_PERIOD. This was the original patch https://lore.kernel.org/all/20180507224750.9383-1-jcro...@codeaurora.org/ where the inactive period was increased for a530. I cannot test suspend on msm8937 yet. I can check on msm8953 with a506 maybe if a506 works fine with DRM_MSM_INACTIVE_PERIOD then a505 would be fine with it also. > > > > > Konrad
Re: [PATCH] drm/msm/adreno: Add support for Adreno 505 GPU
On Tue, Jun 4, 2024 at 1:55 PM Konrad Dybcio wrote: > > > > On 6/4/24 02:20, Barnabás Czémán wrote: > > From: Daniil Titov > > > > This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz), > > SDM439 (650 MHz). > > > > Signed-off-by: Daniil Titov > > Signed-off-by: Barnabás Czémán > > --- > > This all looks very good, just a nit > > [...] > > > + /* > > + * Increase inactive period to 250 to avoid bouncing > > + * the GDSC which appears to make it grumpy > > + */ > > + .inactive_period = 250, > > Are you sure this is actually necessary? Every A5XX GPU is using the same value, but i have never tried with DRM_MSM_INACTIVE_PERIOD. > > Konrad
[PATCH] drm/msm/adreno: Add support for Adreno 505 GPU
From: Daniil Titov
This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz),
SDM439 (650 MHz).
Signed-off-by: Daniil Titov
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 29 +
drivers/gpu/drm/msm/adreno/adreno_device.c | 17 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 5 +
3 files changed, 39 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index c003f970189b..c0b5373e90d7 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -439,7 +439,8 @@ void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
const struct adreno_five_hwcg_regs *regs;
unsigned int i, sz;
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu)) {
regs = a50x_hwcg;
sz = ARRAY_SIZE(a50x_hwcg);
} else if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu)) {
@@ -483,7 +484,8 @@ static int a5xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x);
/* Specify workarounds for various microcode issues */
- if (adreno_is_a506(adreno_gpu) || adreno_is_a530(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a530(adreno_gpu)) {
/* Workaround for token end syncs
* Force a WFI after every direct-render 3D mode draw and every
* 2D mode 3 draw
@@ -752,10 +754,11 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
0x0010 + adreno_gpu->info->gmem - 1);
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x);
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
- adreno_is_a510(adreno_gpu)) {
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) {
gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20);
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu))
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
else
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
@@ -771,7 +774,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
}
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu))
gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
(0x100 << 11 | 0x100 << 22));
else if (adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) ||
@@ -789,8 +793,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
* Disable the RB sampler datapath DP2 clock gating optimization
* for 1-SP GPUs, as it is enabled by default.
*/
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
- adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu))
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||
+ adreno_is_a512(adreno_gpu))
gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9));
/* Disable UCHE global filter as SP can invalidate/flush independently
*/
@@ -1345,7 +1350,7 @@ static int a5xx_pm_resume(struct msm_gpu *gpu)
if (ret)
return ret;
- /* Adreno 506, 508, 509, 510, 512 needs manual RBBM sus/res control */
+ /* Adreno 505, 506, 508, 509, 510, 512 needs manual RBBM sus/res
control */
if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) {
/* Halt the sp_input_clk at HM level */
gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x0055);
@@ -1388,9 +1393,9 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
u32 mask = 0xf;
int i, ret;
- /* A506, A508, A510 have 3 XIN ports in VBIF */
- if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
- adreno_is_a510(adreno_gpu))
+ /* A505, A506, A508, A510 have 3 XIN ports in VBIF */
+ if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
+ adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu))
mask = 0x7;
/* Clear the VBIF pipe before shutting down */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index c3703a51287b..7e1ff091acaf 100644
--- a/dr
[PATCH] drm/msm/adreno: Add A306A support
From: Otto Pflüger
Add support for Adreno 306A GPU what is found in MSM8917 SoC.
This GPU marketing name is Adreno 308.
Signed-off-by: Otto Pflüger
[use internal name of the GPU, reword the commit message]
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 14 +++---
drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 6 ++
3 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 5273dc849838..b46ff49f47cf 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -145,6 +145,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x000a);
gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x000a);
+ } else if (adreno_is_a306a(adreno_gpu)) {
+ gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
+ gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0010);
+ gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0010);
} else if (adreno_is_a320(adreno_gpu)) {
/* Set up 16 deep read/write request queues: */
gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
@@ -237,7 +241,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x0001);
/* Enable Clock gating: */
- if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu))
+ if (adreno_is_a305b(adreno_gpu) ||
+ adreno_is_a306(adreno_gpu) ||
+ adreno_is_a306a(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0x);
else if (adreno_is_a320(adreno_gpu))
gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfff);
@@ -334,8 +340,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
- if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) ||
- adreno_is_a320(adreno_gpu)) {
+ if (adreno_is_a305(adreno_gpu) ||
+ adreno_is_a306(adreno_gpu) ||
+ adreno_is_a306a(adreno_gpu) ||
+ adreno_is_a320(adreno_gpu)) {
gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index c3703a51287b..198b2b5b67fb 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -86,6 +86,17 @@ static const struct adreno_info gpulist[] = {
.gmem = SZ_128K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a3xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x03000620),
+ .family = ADRENO_3XX,
+ .revn = 308,
+ .fw = {
+ [ADRENO_FW_PM4] = "a300_pm4.fw",
+ [ADRENO_FW_PFP] = "a300_pfp.fw",
+ },
+ .gmem = SZ_128K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a3xx_gpu_init,
}, {
.chip_ids = ADRENO_CHIP_IDS(
0x0302,
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 77526892eb8c..2645f6f4ad83 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -268,6 +268,12 @@ static inline bool adreno_is_a306(const struct adreno_gpu
*gpu)
return adreno_is_revn(gpu, 307);
}
+static inline bool adreno_is_a306a(const struct adreno_gpu *gpu)
+{
+ /* a306a marketing name is a308 */
+ return adreno_is_revn(gpu, 308);
+}
+
static inline bool adreno_is_a320(const struct adreno_gpu *gpu)
{
return adreno_is_revn(gpu, 320);
---
base-commit: 6dc544b66971c7f9909ff038b62149105272d26a
change-id: 20240528-a306a-48e173724d6c
Best regards,
--
Barnabás Czémán
Re: [PATCH] drm/panel: jdi-fhd-r63452: move DCS off commands to disable
On Fri, May 10, 2024 at 8:02 PM Dmitry Baryshkov wrote: > > On Fri, May 10, 2024 at 09:10:34AM +0200, Barnabás Czémán wrote: > > On Fri, May 10, 2024 at 8:46 AM Barnabás Czémán wrote: > > > > > > On Fri, May 10, 2024 at 2:56 AM Dmitry Baryshkov > > > wrote: > > > > > > > > On Thu, May 09, 2024 at 08:14:07PM +0200, Barnabás Czémán wrote: > > > > > Move DCS off commands from .unprepare to .disable so that they > > > > > actually reach the DSI host. > > > > > > > > > > Signed-off-by: Barnabás Czémán > > > > > --- > > > > > drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c | 12 ++-- > > > > > 1 file changed, 10 insertions(+), 2 deletions(-) > > > > > > > > I don't think this is correct. If the driver sends enable commands in > > > > prepare, it should be able to send commands during unprepare too. > > > > > > > It cannot send commands in unprepare, there are multiple panel drivers > > > what do the same. > > > Every panel drivers which have DCS commands to be sent in unprepare > > > has similar error messages with mdp5/dpu. > > > > > > [ 92.322564] panel-td4320-boeplus c994000.dsi.0: sending command > > > 0x28 failed: -22 > > > [ 92.322635] panel-td4320-boeplus c994000.dsi.0: Failed to > > > un-initialize panel: -22 > > > > > > > > Here is the error messages, these are comes from unprepare by every panel > > off: > > [ 121.295290] panel-jdi-fhd-r63452 994000.dsi.0: transmit data failed: -22 > > [ 121.295368] panel-jdi-fhd-r63452 994000.dsi.0: Failed to > > un-initialize panel: -22 > > [ 184.783019] panel-jdi-fhd-r63452 994000.dsi.0: transmit data failed: -22 > > [ 184.783066] panel-jdi-fhd-r63452 994000.dsi.0: Failed to > > un-initialize panel: -22 > > with this patch these errors no more. > > .prepare works because of this flag ctx->panel.prepare_prev_first = true; > > The flag should also invert the order of post_disable chain. It well > might be that the drm/msm/dsi driver shuts down the DSI link too soon. > Please consider fixing the MSM DSI driver instead. > Ok, thank you i look forward to it. > -- > With best wishes > Dmitry
Re: [PATCH] drm/panel: jdi-fhd-r63452: move DCS off commands to disable
On Fri, May 10, 2024 at 8:46 AM Barnabás Czémán wrote:
>
> On Fri, May 10, 2024 at 2:56 AM Dmitry Baryshkov
> wrote:
> >
> > On Thu, May 09, 2024 at 08:14:07PM +0200, Barnabás Czémán wrote:
> > > Move DCS off commands from .unprepare to .disable so that they
> > > actually reach the DSI host.
> > >
> > > Signed-off-by: Barnabás Czémán
> > > ---
> > > drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c | 12 ++--
> > > 1 file changed, 10 insertions(+), 2 deletions(-)
> >
> > I don't think this is correct. If the driver sends enable commands in
> > prepare, it should be able to send commands during unprepare too.
> >
> It cannot send commands in unprepare, there are multiple panel drivers
> what do the same.
> Every panel drivers which have DCS commands to be sent in unprepare
> has similar error messages with mdp5/dpu.
>
> [ 92.322564] panel-td4320-boeplus c994000.dsi.0: sending command
> 0x28 failed: -22
> [ 92.322635] panel-td4320-boeplus c994000.dsi.0: Failed to
> un-initialize panel: -22
>
>
Here is the error messages, these are comes from unprepare by every panel off:
[ 121.295290] panel-jdi-fhd-r63452 994000.dsi.0: transmit data failed: -22
[ 121.295368] panel-jdi-fhd-r63452 994000.dsi.0: Failed to
un-initialize panel: -22
[ 184.783019] panel-jdi-fhd-r63452 994000.dsi.0: transmit data failed: -22
[ 184.783066] panel-jdi-fhd-r63452 994000.dsi.0: Failed to
un-initialize panel: -22
with this patch these errors no more.
.prepare works because of this flag ctx->panel.prepare_prev_first = true;
> > >
> > > diff --git a/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
> > > b/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
> > > index 483dc88d16d8..f7222974d6ed 100644
> > > --- a/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
> > > +++ b/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
> > > @@ -169,6 +169,15 @@ static int jdi_fhd_r63452_prepare(struct drm_panel
> > > *panel)
> > > }
> > >
> > > static int jdi_fhd_r63452_unprepare(struct drm_panel *panel)
> > > +{
> > > + struct jdi_fhd_r63452 *ctx = to_jdi_fhd_r63452(panel);
> > > +
> > > + gpiod_set_value_cansleep(ctx->reset_gpio, 1);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int jdi_fhd_r63452_disable(struct drm_panel *panel)
> > > {
> > > struct jdi_fhd_r63452 *ctx = to_jdi_fhd_r63452(panel);
> > > struct device *dev = &ctx->dsi->dev;
> > > @@ -178,8 +187,6 @@ static int jdi_fhd_r63452_unprepare(struct drm_panel
> > > *panel)
> > > if (ret < 0)
> > > dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
> > >
> > > - gpiod_set_value_cansleep(ctx->reset_gpio, 1);
> > > -
> > > return 0;
> > > }
> > >
> > > @@ -219,6 +226,7 @@ static int jdi_fhd_r63452_get_modes(struct drm_panel
> > > *panel,
> > > static const struct drm_panel_funcs jdi_fhd_r63452_panel_funcs = {
> > > .prepare = jdi_fhd_r63452_prepare,
> > > .unprepare = jdi_fhd_r63452_unprepare,
> > > + .disable = jdi_fhd_r63452_disable,
> > > .get_modes = jdi_fhd_r63452_get_modes,
> > > };
> > >
> > >
> > > ---
> > > base-commit: 704ba27ac55579704ba1289392448b0c66b56258
> > > change-id: 20240509-jdi-use-disable-ee29098d9c81
> > >
> > > Best regards,
> > > --
> > > Barnabás Czémán
> > >
> >
> > --
> > With best wishes
> > Dmitry
Re: [PATCH] drm/panel: jdi-fhd-r63452: move DCS off commands to disable
On Fri, May 10, 2024 at 2:56 AM Dmitry Baryshkov
wrote:
>
> On Thu, May 09, 2024 at 08:14:07PM +0200, Barnabás Czémán wrote:
> > Move DCS off commands from .unprepare to .disable so that they
> > actually reach the DSI host.
> >
> > Signed-off-by: Barnabás Czémán
> > ---
> > drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c | 12 ++--
> > 1 file changed, 10 insertions(+), 2 deletions(-)
>
> I don't think this is correct. If the driver sends enable commands in
> prepare, it should be able to send commands during unprepare too.
>
It cannot send commands in unprepare, there are multiple panel drivers
what do the same.
Every panel drivers which have DCS commands to be sent in unprepare
has similar error messages with mdp5/dpu.
[ 92.322564] panel-td4320-boeplus c994000.dsi.0: sending command
0x28 failed: -22
[ 92.322635] panel-td4320-boeplus c994000.dsi.0: Failed to
un-initialize panel: -22
> >
> > diff --git a/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
> > b/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
> > index 483dc88d16d8..f7222974d6ed 100644
> > --- a/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
> > +++ b/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
> > @@ -169,6 +169,15 @@ static int jdi_fhd_r63452_prepare(struct drm_panel
> > *panel)
> > }
> >
> > static int jdi_fhd_r63452_unprepare(struct drm_panel *panel)
> > +{
> > + struct jdi_fhd_r63452 *ctx = to_jdi_fhd_r63452(panel);
> > +
> > + gpiod_set_value_cansleep(ctx->reset_gpio, 1);
> > +
> > + return 0;
> > +}
> > +
> > +static int jdi_fhd_r63452_disable(struct drm_panel *panel)
> > {
> > struct jdi_fhd_r63452 *ctx = to_jdi_fhd_r63452(panel);
> > struct device *dev = &ctx->dsi->dev;
> > @@ -178,8 +187,6 @@ static int jdi_fhd_r63452_unprepare(struct drm_panel
> > *panel)
> > if (ret < 0)
> > dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
> >
> > - gpiod_set_value_cansleep(ctx->reset_gpio, 1);
> > -
> > return 0;
> > }
> >
> > @@ -219,6 +226,7 @@ static int jdi_fhd_r63452_get_modes(struct drm_panel
> > *panel,
> > static const struct drm_panel_funcs jdi_fhd_r63452_panel_funcs = {
> > .prepare = jdi_fhd_r63452_prepare,
> > .unprepare = jdi_fhd_r63452_unprepare,
> > + .disable = jdi_fhd_r63452_disable,
> > .get_modes = jdi_fhd_r63452_get_modes,
> > };
> >
> >
> > ---
> > base-commit: 704ba27ac55579704ba1289392448b0c66b56258
> > change-id: 20240509-jdi-use-disable-ee29098d9c81
> >
> > Best regards,
> > --
> > Barnabás Czémán
> >
>
> --
> With best wishes
> Dmitry
[PATCH v2] drm/msm/dpu: fix encoder irq wait skip
The irq_idx is unsigned so it cannot be lower than zero, better
to change the condition to check if it is equal with zero.
It could not cause any issue because a valid irq index starts from one.
Fixes: 5a9d50150c2c ("drm/msm/dpu: shift IRQ indices by 1")
Signed-off-by: Barnabás Czémán
---
Changes in v2:
- Add Fixes in commit message.
- Link to v1:
https://lore.kernel.org/r/20240509-irq_wait-v1-1-41d653e37...@gmail.com
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 119f3ea50a7c..cf7d769ab3b9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -428,7 +428,7 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys
*phys_enc,
return -EWOULDBLOCK;
}
- if (irq_idx < 0) {
+ if (irq_idx == 0) {
DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n",
DRMID(phys_enc->parent), func);
return 0;
---
base-commit: 704ba27ac55579704ba1289392448b0c66b56258
change-id: 20240509-irq_wait-49444cea77e2
Best regards,
--
Barnabás Czémán
Re: [PATCH] drm/msm/dpu: guard ctl irq callback register/unregister
There was some previously sent patch series made by Dmitry for these soc, msm8996 was sent together by sdm660 but in the last version it was dropped. I have recreated msm8996 DPU support from that series but it will need some more test. I am testing msm8953 series but it is depend on msm8996.
[PATCH] drm/panel: jdi-fhd-r63452: move DCS off commands to disable
Move DCS off commands from .unprepare to .disable so that they
actually reach the DSI host.
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
b/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
index 483dc88d16d8..f7222974d6ed 100644
--- a/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
+++ b/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c
@@ -169,6 +169,15 @@ static int jdi_fhd_r63452_prepare(struct drm_panel *panel)
}
static int jdi_fhd_r63452_unprepare(struct drm_panel *panel)
+{
+ struct jdi_fhd_r63452 *ctx = to_jdi_fhd_r63452(panel);
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+
+ return 0;
+}
+
+static int jdi_fhd_r63452_disable(struct drm_panel *panel)
{
struct jdi_fhd_r63452 *ctx = to_jdi_fhd_r63452(panel);
struct device *dev = &ctx->dsi->dev;
@@ -178,8 +187,6 @@ static int jdi_fhd_r63452_unprepare(struct drm_panel *panel)
if (ret < 0)
dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
-
return 0;
}
@@ -219,6 +226,7 @@ static int jdi_fhd_r63452_get_modes(struct drm_panel *panel,
static const struct drm_panel_funcs jdi_fhd_r63452_panel_funcs = {
.prepare = jdi_fhd_r63452_prepare,
.unprepare = jdi_fhd_r63452_unprepare,
+ .disable = jdi_fhd_r63452_disable,
.get_modes = jdi_fhd_r63452_get_modes,
};
---
base-commit: 704ba27ac55579704ba1289392448b0c66b56258
change-id: 20240509-jdi-use-disable-ee29098d9c81
Best regards,
--
Barnabás Czémán
[PATCH] drm/msm/dpu: guard ctl irq callback register/unregister
CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts, so better to skip CTL irq callback register/unregister make dpu_ctl_cfg be able to define without intr_start. Signed-off-by: Barnabás Czémán --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 489be1c0c704..250d83af53a4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -298,7 +298,7 @@ static void dpu_encoder_phys_cmd_irq_enable(struct dpu_encoder_phys *phys_enc) phys_enc); dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true); - if (dpu_encoder_phys_cmd_is_master(phys_enc)) + if (dpu_encoder_phys_cmd_is_master(phys_enc) && phys_enc->irq[INTR_IDX_CTL_START]) dpu_core_irq_register_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_CTL_START], dpu_encoder_phys_cmd_ctl_start_irq, @@ -311,7 +311,7 @@ static void dpu_encoder_phys_cmd_irq_disable(struct dpu_encoder_phys *phys_enc) phys_enc->hw_pp->idx - PINGPONG_0, phys_enc->vblank_refcount); - if (dpu_encoder_phys_cmd_is_master(phys_enc)) + if (dpu_encoder_phys_cmd_is_master(phys_enc) && phys_enc->irq[INTR_IDX_CTL_START]) dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_CTL_START]); --- base-commit: 704ba27ac55579704ba1289392448b0c66b56258 change-id: 20240509-ctl_irq-a90b2d7a0bf5 Best regards, -- Barnabás Czémán
[PATCH] drm/msm/dpu: fix encoder irq wait skip
The irq_idx is unsigned so it cannot be lower than zero, better
to change the condition to check if it is equal with zero.
It could not cause any issue because a valid irq index starts from one.
Signed-off-by: Barnabás Czémán
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 119f3ea50a7c..cf7d769ab3b9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -428,7 +428,7 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys
*phys_enc,
return -EWOULDBLOCK;
}
- if (irq_idx < 0) {
+ if (irq_idx == 0) {
DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n",
DRMID(phys_enc->parent), func);
return 0;
---
base-commit: 704ba27ac55579704ba1289392448b0c66b56258
change-id: 20240509-irq_wait-49444cea77e2
Best regards,
--
Barnabás Czémán
[PATCH] drm/panel: jdi-fhd-r63452: make use of prepare_prev_first
The DSI host must be enabled for the panel to be initialized in prepare(). Set the prepare_prev_first flag to guarantee this. Signed-off-by: Barnabás Czémán --- drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c b/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c index 3e0a8e0d58a0..483dc88d16d8 100644 --- a/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c +++ b/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c @@ -247,6 +247,7 @@ static int jdi_fhd_r63452_probe(struct mipi_dsi_device *dsi) drm_panel_init(&ctx->panel, dev, &jdi_fhd_r63452_panel_funcs, DRM_MODE_CONNECTOR_DSI); + ctx->panel.prepare_prev_first = true; ret = drm_panel_of_backlight(&ctx->panel); if (ret) --- base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8 change-id: 20240423-jdi-fix-986a796a3101 Best regards, -- Barnabás Czémán
