Re: [PATCH] drm/mediatek: Fix potential memory leak if vmap() fail
On 26/06/2023 20:58, Sui Jingfeng wrote:
Also return -ENOMEM if such a failure happens, the implement should take
responsibility for the error handling.
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/mediatek/mtk_drm_gem.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c
b/drivers/gpu/drm/mediatek/mtk_drm_gem.c
index a25b28d3ee90..9f364df52478 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c
@@ -247,7 +247,11 @@ int mtk_drm_gem_prime_vmap(struct drm_gem_object *obj,
struct iosys_map *map)
mtk_gem->kvaddr = vmap(mtk_gem->pages, npages, VM_MAP,
pgprot_writecombine(PAGE_KERNEL));
-
+ if (!mtk_gem->kvaddr) {
+ kfree(sgt);
+ kfree(mtk_gem->pages);
+ return -ENOMEM;
+ }
Reviewed-by: Matthias Brugger
out:
kfree(sgt);
iosys_map_set_vaddr(map, mtk_gem->kvaddr);
Re: [PATCH] dt-bindings: cleanup DTS example whitespaces
On 02/07/2023 20:23, Krzysztof Kozlowski wrote:
The DTS code coding style expects spaces around '=' sign.
Signed-off-by: Krzysztof Kozlowski
---
Rob,
Maybe this could go via your tree? Rebased on your for-next:
v6.4-rc2-45-gf0ac35049606
---
[...]
.../bindings/net/mediatek-dwmac.yaml | 2 +-
[...]
.../bindings/phy/mediatek,dsi-phy.yaml | 2 +-
[...]
.../devicetree/bindings/usb/mediatek,mtu3.yaml | 2 +-
.../devicetree/bindings/usb/ti,am62-usb.yaml | 2 +-
For MediaTek parts:
Reviewed-by: Matthias Brugger
15 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
index 0c5b875cb654..d6c84b6e7fe6 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
@@ -287,7 +287,7 @@ examples:
arm,trig-in-sigs = <0 1>;
arm,trig-in-types = ;
-arm,trig-out-sigs=<0 1 2 >;
+arm,trig-out-sigs = <0 1 2 >;
arm,trig-out-types = ;
@@ -309,24 +309,24 @@ examples:
trig-conns@0 {
reg = <0>;
-arm,trig-in-sigs=<0>;
-arm,trig-in-types=;
-arm,trig-out-sigs=<0>;
-arm,trig-out-types=;
+arm,trig-in-sigs = <0>;
+arm,trig-in-types = ;
+arm,trig-out-sigs = <0>;
+arm,trig-out-types = ;
arm,trig-conn-name = "sys_profiler";
};
trig-conns@1 {
reg = <1>;
-arm,trig-out-sigs=<2 3>;
-arm,trig-out-types=;
+arm,trig-out-sigs = <2 3>;
+arm,trig-out-types = ;
arm,trig-conn-name = "watchdog";
};
trig-conns@2 {
reg = <2>;
-arm,trig-in-sigs=<1 6>;
-arm,trig-in-types=;
+arm,trig-in-sigs = <1 6>;
+arm,trig-in-types = ;
arm,trig-conn-name = "g_counter";
};
};
diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml
b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml
index 91b96065f7df..86b59de7707e 100644
--- a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml
+++ b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml
@@ -96,8 +96,8 @@ examples:
compatible = "ti,k2g-sci";
ti,system-reboot-controller;
mbox-names = "rx", "tx";
- mboxes= < 5 2>,
- < 0 0>;
+ mboxes = < 5 2>,
+ < 0 0>;
reg-names = "debug_messages";
reg = <0x02921800 0x800>;
};
@@ -107,8 +107,8 @@ examples:
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
- mboxes= <_proxy_main 11>,
- <_proxy_main 13>;
+ mboxes = <_proxy_main 11>,
+ <_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x44083000 0x1000>;
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index 029d72822d8b..65b02c7a1211 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -225,7 +225,7 @@ examples:
#include
gmu: gmu@506a000 {
-compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
+compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
reg = <0x506a000 0x3>,
<0xb28 0x1>,
diff --git
a/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.yaml
b/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.yaml
index 1cdc91b3439f..200fbf1c74a0 100644
--- a/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.yaml
+++ b/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.yaml
@@ -74,7 +74,7 @@ examples:
vdd3-supply = <_reg>;
vci-supply = <_reg>;
reset-gpios = < 5 0>;
-power-on-delay= <50>;
+power-on-delay = <50>;
reset-delay = <100>;
init-delay = <100>;
panel-width-mm = <58>;
diff --git
a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
index 6f43d885c9b3..df61cb5f5c54 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
@@ -121,11 +121,11 @@ examples:
#size-cells = <0>;
vopb_out_edp: endpoint@0
Re: [PATCH v2, 3/3] drm/mediatek: dsi: Add dsi cmdq_ctl to send panel initial code
On 16/06/2023 09:36, Shuijing Li wrote:
For mt8188, add dsi cmdq reg control to send long packets to panel
initialization.
Signed-off-by: Shuijing Li
Signed-off-by: Jitao Shi
Reviewed-by: Matthias Brugger
---
Changes in v2:
use mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL); directly,
per suggestion from the previous thread:
https://lore.kernel.org/lkml/015f4c60-ed77-9e1f-8a6b-cda6e4f6a...@gmail.com/
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 500a3054282d..8b43d9f48178 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -86,6 +86,7 @@
#define DSI_CMDQ_SIZE 0x60
#define CMDQ_SIZE 0x3f
+#define CMDQ_SIZE_SEL BIT(15)
#define DSI_HSTX_CKL_WC 0x64
@@ -178,6 +179,7 @@ struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
bool has_shadow_ctl;
bool has_size_ctl;
+ bool cmdq_long_packet_ctl;
};
struct mtk_dsi {
@@ -996,6 +998,8 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct
mipi_dsi_msg *msg)
mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
+ if (dsi->driver_data->cmdq_long_packet_ctl)
+ mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL);
}
static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
@@ -1200,18 +1204,21 @@ static const struct mtk_dsi_driver_data
mt8183_dsi_driver_data = {
.reg_cmdq_off = 0x200,
.has_shadow_ctl = true,
.has_size_ctl = true,
+ .cmdq_long_packet_ctl = false,
};
static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
.reg_cmdq_off = 0xd00,
.has_shadow_ctl = true,
.has_size_ctl = true,
+ .cmdq_long_packet_ctl = false,
};
static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
.reg_cmdq_off = 0xd00,
.has_shadow_ctl = true,
.has_size_ctl = true,
+ .cmdq_long_packet_ctl = true,
};
static const struct of_device_id mtk_dsi_of_match[] = {
Re: [PATCH v8 2/2] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
On 31/05/2023 09:43, Chen-Yu Tsai wrote:
Hi Matthias,
On Mon, Mar 6, 2023 at 4:07 PM Jason-JH.Lin wrote:
After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
Signed-off-by: Jason-JH.Lin
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Rex-BC Chen
Acked-by: Matthias Brugger
CK didn't pick up this patch. Since the other patch already got picked up
in v6.4-rc1, could you merge this for v6.5?
Yes, I gave an acked-by as I thought that CK will take both of them. Anyway
applied now.
Matthias
Thanks
ChenYu
---
include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
b/include/linux/soc/mediatek/mtk-mmsys.h
index dc2963a0a0f7..8eb5846985b4 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -27,8 +27,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
- DDP_COMPONENT_DITHER,
- DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DITHER1,
DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_DP_INTF1,
--
2.18.0
Re: [RESEND 05/15] drm/mediatek/mtk_disp_ccorr: Remove half completed incorrect struct header
On 09/06/2023 10:17, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c:47: warning: Function parameter or
member 'clk' not described in 'mtk_disp_ccorr'
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c:47: warning: Function parameter or
member 'regs' not described in 'mtk_disp_ccorr'
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c:47: warning: Function parameter or
member 'cmdq_reg' not described in 'mtk_disp_ccorr'
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c:47: warning: Function parameter or
member 'data' not described in 'mtk_disp_ccorr'
Cc: Chun-Kuang Hu
Cc: Philipp Zabel
Cc: David Airlie
Cc: Daniel Vetter
Cc: Matthias Brugger
Cc: AngeloGioacchino Del Regno
Cc: dri-devel@lists.freedesktop.org
Cc: linux-media...@lists.infradead.org
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 1773379b24398..720f3c7ef7b4f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -34,11 +34,6 @@ struct mtk_disp_ccorr_data {
u32 matrix_bits;
};
-/**
- * struct mtk_disp_ccorr - DISP_CCORR driver structure
- * @ddp_comp - structure containing type enum and hardware resources
- * @crtc - associated crtc to report irq events to
- */
That surely suppress the warning but I think the correct to do here is to fix
the documentation instead of deleting it.
Regards,
Matthias
struct mtk_disp_ccorr {
struct clk *clk;
void __iomem *regs;
Re: [PATCH] arm64: dts: mediatek: mt8173-elm: remove panel model number in DT
On 29/05/2023 10:45, Icenowy Zheng wrote:
在 2023-05-29星期一的 10:02 +0200，AngeloGioacchino Del Regno写道：
Il 26/05/23 16:24, Doug Anderson ha scritto:
Hi,
On Fri, May 26, 2023 at 3:09 AM Icenowy Zheng
wrote:
Currently a specific panel number is used in the Elm DTSI, which
is
corresponded to a 12" panel. However, according to the official
Chrome
OS devices document, Elm refers to Acer Chromebook R13, which, as
the
name specifies, uses a 13.3" panel, which comes with EDID
information.
As the kernel currently prioritizes the hardcoded timing
parameters
matched with the panel number compatible, a wrong timing will be
applied
to the 13.3" panel on Acer Chromebook R13, which leads to blank
display.
Because the Elm DTSI is shared with Hana board, and Hana
corresponds to
multiple devices from 11" to 14", a certain panel model number
shouldn't
be present, and driving the panel according to its EDID
information is
necessary.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
We went through a bunch of back-and-forth here but in the end in
the
ChromeOS tree we have "edp-panel" as the "compatible" here in the
ChromeOS 5.15 tree and this makes sense.
Reviewed-by: Douglas Anderson
...in theory one would wish for a "Fixes" tag, but I think in
previous
discussions it was decided that it was too complicated. Hardcoding
the
other compatible string has always been technically wrong, but I
guess
it worked at some point in time. The more correct way (as you're
doing
here) needs the DP AUX bus support and the generic eDP panels, both
of
which are significantly newer than the elm dts. So I guess leaving
no
"Fixes" tag is OK, or perhaps you could do the somewhat weak:
Fixes: c2d94f72140a ("arm64: dts: mediatek: mt8173-elm: Move
display
to ps8640 auxiliary bus")
I remember I didn't change the compatible to panel-edp because it
didn't
work at that time, but it does now... I'm not sure what actually
fixed that
and if the commit(s) was/were backported to that suggested point, so
I
would leave the Fixes tag out, as that may break older kernel.
Well at least I developed this patch on v6.3.
(In fact the same kernel config do not boot to system at all on
v6.0/v6.1 when I do make olddefconfig then build)
I applied the patch without the fixes tag. Lets stay on the secure side to not
break older kernels.
Regards,
Matthias
Anyway, for this commit:
Reviewed-by: AngeloGioacchino Del Regno
Re: [PATCH 03/27] dt-bindings: display: mediatek: dpi: Add compatible for MediaTek MT6795
Hi Chun-Kuang Hu, Can you help to merge the missing DT-binding patches in this series? Thanks a lot, Matthias On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for the MediaTek Helio X10 MT6795 SoC, using the same parameters as MT8183. Signed-off-by: AngeloGioacchino Del Regno --- .../display/mediatek/mediatek,dpi.yaml| 23 +++ 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index d976380801e3..803c00f26206 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -17,15 +17,20 @@ description: | properties: compatible: -enum: - - mediatek,mt2701-dpi - - mediatek,mt7623-dpi - - mediatek,mt8173-dpi - - mediatek,mt8183-dpi - - mediatek,mt8186-dpi - - mediatek,mt8188-dp-intf - - mediatek,mt8192-dpi - - mediatek,mt8195-dp-intf +oneOf: + - enum: + - mediatek,mt2701-dpi + - mediatek,mt7623-dpi + - mediatek,mt8173-dpi + - mediatek,mt8183-dpi + - mediatek,mt8186-dpi + - mediatek,mt8188-dp-intf + - mediatek,mt8192-dpi + - mediatek,mt8195-dp-intf + - items: + - enum: + - mediatek,mt6795-dpi + - const: mediatek,mt8183-dpi reg: maxItems: 1
Re: [PATCH 02/27] dt-bindings: phy: mediatek, dsi-phy: Add compatible for MT6795 Helio X10
On 14/04/2023 10:22, Krzysztof Kozlowski wrote: On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795: this SoC uses the same DSI PHY as MT8173. Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 4 1 file changed, 4 insertions(+) Acked-by: Krzysztof Kozlowski Best regards, Krzysztof Applied, thanks!
Re: [PATCH 25/27] arm64: dts: mediatek: mt6795-xperia-m5: Add eMMC, MicroSD slot, SDIO
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Configure and enable the MMC0/1/2 controllers, used for the eMMC chip,
MicroSD card slot and SDIO (WiFi) respectively.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
.../dts/mediatek/mt6795-sony-xperia-m5.dts| 91 +++
1 file changed, 91 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index debe0f2553d9..155a573eac4c 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -17,6 +17,7 @@ / {
aliases {
mmc0 =
mmc1 =
+ mmc2 =
serial0 =
serial1 =
};
@@ -121,7 +122,97 @@ proximity@48 {
};
};
+ {
+ /* eMMC controller */
+ mediatek,latch-ck = <0x14>; /* hs400 */
+ mediatek,hs200-cmd-int-delay = <1>;
+ mediatek,hs400-cmd-int-delay = <1>;
+ mediatek,hs400-ds-dly3 = <0x1a>;
+ non-removable;
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <_pins_default>;
+ pinctrl-1 = <_pins_uhs>;
+ vmmc-supply = <_vemc33_reg>;
+ vqmmc-supply = <_vio18_reg>;
+ status = "okay";
+};
+
+ {
+ /* MicroSD card slot */
+ vmmc-supply = <_vmc_reg>;
+ vqmmc-supply = <_vmch_reg>;
+ status = "okay";
+};
+
+ {
+ /* SDIO WiFi on MMC2 */
+ vmmc-supply = <_vmc_reg>;
+ vqmmc-supply = <_vmch_reg>;
+ status = "okay";
+};
+
{
+ mmc0_pins_default: emmc-sdr-pins {
+ pins-cmd-dat {
+ pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+ input-enable;
+ bias-pull-up = ;
+ };
+
+ pins-clk {
+ pinmux = ;
+ bias-pull-down = ;
+ };
+
+ pins-rst {
+ pinmux = ;
+ bias-pull-up = ;
+ };
+ };
+
+ mmc0_pins_uhs: emmc-uhs-pins {
+ pins-cmd-dat {
+ pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+ input-enable;
+ drive-strength = ;
+ bias-pull-up = ;
+ };
+
+ pins-clk {
+ pinmux = ;
+ drive-strength = ;
+ bias-pull-down = ;
+ };
+
+ pins-rst {
+ pinmux = ;
+ drive-strength = ;
+ bias-pull-up = ;
+ };
+
+ pins-ds {
+ pinmux = ;
+ drive-strength = ;
+ bias-pull-down = ;
+ };
+ };
+
nfc_pins: nfc-pins {
pins-irq {
pinmux = ;
Re: [PATCH 24/27] arm64: dts: mediatek: mt6795-xperia-m5: Add MT6331 Combo PMIC
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
This smartphone uses the Helio X10 standard MT6331+MT6332 combo PMICs:
include the mt6331 devicetree and add the required interrupt.
Note that despite there being two interrupts, one for MT6331 and one
for MT6332, in configurations using the companion PMIC, the interrupt
of the latter fires for both events on MT6331 and for ones on MT6332,
while the interrupt for the main PMIC fires only for events of the
main PMIC.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index a0e01a756f03..debe0f2553d9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include
#include "mt6795.dtsi"
+#include "mt6331.dtsi"
/ {
model = "Sony Xperia M5";
@@ -219,6 +220,15 @@ pins-tx {
};
};
+ {
+ /*
+* Smartphones, including the Xperia M5, are equipped with a companion
+* MT6332 PMIC: when this is present, the main MT6331 PMIC will fire
+* an interrupt on the companion, so we use the MT6332 IRQ GPIO.
+*/
+ interrupts = ;
+};
+
{
status = "okay";
Re: [PATCH 23/27] arm64: dts: mediatek: Add MT6331 PMIC devicetree
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
MT6331 is the primary PMIC for the MediaTek Helio X10 MT6795 smartphone
platforms: add a devicetree describing its regulators, Real Time Clock
and PMIC-keys.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
arch/arm64/boot/dts/mediatek/mt6331.dtsi | 284 +++
1 file changed, 289 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6331.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/mt6331.dtsi
b/arch/arm64/boot/dts/mediatek/mt6331.dtsi
new file mode 100644
index ..fcec8c07fe39
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6331.dtsi
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ * Author: AngeloGioacchino Del Regno
+ */
+#include
+
+ {
+ pmic: mt6331 {
+ compatible = "mediatek,mt6331";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ mt6331regulator: mt6331regulator {
+ compatible = "mediatek,mt6331-regulator";
+
+ mt6331_vdvfs11_reg: buck-vdvfs11 {
+ regulator-name = "vdvfs11";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <1493750>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-allowed-modes = <0 1>;
+ regulator-always-on;
+ };
+
+ mt6331_vdvfs12_reg: buck-vdvfs12 {
+ regulator-name = "vdvfs12";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <1493750>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-allowed-modes = <0 1>;
+ regulator-always-on;
+ };
+
+ mt6331_vdvfs13_reg: buck-vdvfs13 {
+ regulator-name = "vdvfs13";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <1493750>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-allowed-modes = <0 1>;
+ regulator-always-on;
+ };
+
+ mt6331_vdvfs14_reg: buck-vdvfs14 {
+ regulator-name = "vdvfs14";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <1493750>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-allowed-modes = <0 1>;
+ regulator-always-on;
+ };
+
+ mt6331_vcore2_reg: buck-vcore2 {
+ regulator-name = "vcore2";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <1493750>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-allowed-modes = <0 1>;
+ regulator-always-on;
+ };
+
+ mt6331_vio18_reg: buck-vio18 {
+ regulator-name = "vio18";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-allowed-modes = <0 1>;
+ regulator-always-on;
+ };
+
+ mt6331_vtcxo1_reg: ldo-vtcxo1 {
+ regulator-name = "vtcxo1";
+ regulator-min-microvolt = <280>;
+ regulator-max-microvolt = <280>;
+ regulator-ramp-delay = <0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6331_vtcxo2_reg: ldo-vtcxo2 {
+ regulator-name = "vtcxo2";
+ regulator-min-microvolt = <280>;
+ regulator-max-microvolt =
Re: [PATCH 21/27] arm64: dts: mediatek: mt6795: Add PMIC Wrapper node
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Add the pwrap node: this is used to communicate with the PMIC(s).
Signed-off-by: AngeloGioacchino Del Regno
Applied thanks!
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 50d9276d18c6..29ca9a7bf0b3 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -391,6 +391,17 @@ timer: timer@10008000 {
clocks = <_clk>, <>;
};
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt6795-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = ;
+ resets = < MT6795_INFRA_RST0_PMIC_WRAP_RST>;
+ reset-names = "pwrap";
+ clocks = < CLK_TOP_PMICSPI_SEL>, <>;
+ clock-names = "spi", "wrap";
+ };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6795-sysirq",
"mediatek,mt6577-sysirq";
Re: [PATCH 18/27] arm64: dts: mediatek: mt6795: Add support for IOMMU and LARBs
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Add nodes for the multimedia IOMMU and its LARBs: this includes all but
the MJC LARB, which cannot currently be used and will be added later.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 60
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index a8b2c4517e79..9cfa02085f61 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -390,6 +391,17 @@ systimer: timer@10200670 {
clock-names = "clk13m";
};
+ iommu: iommu@10205000 {
+ compatible = "mediatek,mt6795-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ clocks = < CLK_INFRA_M4U>;
+ clock-names = "bclk";
+ interrupts = ;
+ mediatek,larbs = < >;
+ power-domains = < MT6795_POWER_DOMAIN_MM>;
+ #iommu-cells = <1>;
+ };
+
apmixedsys: syscon@10209000 {
compatible = "mediatek,mt6795-apmixedsys", "syscon";
reg = <0 0x10209000 0 0x1000>;
@@ -648,16 +660,64 @@ mmsys: syscon@1400 {
mediatek,gce-client-reg = < SUBSYS_1400 0
0x1000>;
};
+ larb0: larb@14021000 {
+ compatible = "mediatek,mt6795-smi-larb";
+ reg = <0 0x14021000 0 0x1000>;
+ clocks = < CLK_MM_SMI_COMMON>, <
CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ mediatek,smi = <_common>;
+ mediatek,larb-id = <0>;
+ power-domains = < MT6795_POWER_DOMAIN_MM>;
+ };
+
+ smi_common: smi@14022000 {
+ compatible = "mediatek,mt6795-smi-common";
+ reg = <0 0x14022000 0 0x1000>;
+ power-domains = < MT6795_POWER_DOMAIN_MM>;
+ clocks = < CLK_INFRA_SMI>, <
CLK_MM_SMI_COMMON>;
+ clock-names = "apb", "smi";
+ };
+
+ larb2: larb@15001000 {
+ compatible = "mediatek,mt6795-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ clocks = < CLK_MM_SMI_COMMON>, <
CLK_INFRA_SMI>;
+ clock-names = "apb", "smi";
+ mediatek,smi = <_common>;
+ mediatek,larb-id = <2>;
+ power-domains = < MT6795_POWER_DOMAIN_ISP>;
+ };
+
vdecsys: clock-controller@1600 {
compatible = "mediatek,mt6795-vdecsys";
reg = <0 0x1600 0 0x1000>;
#clock-cells = <1>;
};
+ larb1: larb@1601 {
+ compatible = "mediatek,mt6795-smi-larb";
+ reg = <0 0x1601 0 0x1000>;
+ mediatek,smi = <_common>;
+ mediatek,larb-id = <1>;
+ clocks = < CLK_VDEC_CKEN>, <
CLK_VDEC_LARB_CKEN>;
+ clock-names = "apb", "smi";
+ power-domains = < MT6795_POWER_DOMAIN_VDEC>;
+ };
+
vencsys: clock-controller@1800 {
compatible = "mediatek,mt6795-vencsys";
reg = <0 0x1800 0 0x1000>;
#clock-cells = <1>;
};
+
+ larb3: larb@18001000 {
+ compatible = "mediatek,mt6795-smi-larb";
+ reg = <0 0x18001000 0 0x1000>;
+ clocks = < CLK_VENC_VENC>, <
CLK_VENC_LARB>;
+ clock-names = "apb", "smi";
+ mediatek,smi = <_common>;
+ mediatek,larb-id = <3>;
+ power-domains = < MT6795_POWER_DOMAIN_VENC>;
+ };
};
};
Re: [PATCH 17/27] arm64: dts: mediatek: mt6795: Add MMSYS node for multimedia clocks
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Add the MultiMedia System node, providing clocks for the multimedia
hardware blocks and their IOMMU/SMIs.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 99cc4918e6ba..a8b2c4517e79 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -635,6 +635,19 @@ mmc3: mmc@1126 {
status = "disabled";
};
+ mmsys: syscon@1400 {
+ compatible = "mediatek,mt6795-mmsys", "syscon";
+ reg = <0 0x1400 0 0x1000>;
+ power-domains = < MT6795_POWER_DOMAIN_MM>;
+ assigned-clocks = < CLK_TOP_MM_SEL>;
+ assigned-clock-rates = <4>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ mboxes = < 0 CMDQ_THR_PRIO_HIGHEST>,
+< 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0
0x1000>;
+ };
+
vdecsys: clock-controller@1600 {
compatible = "mediatek,mt6795-vdecsys";
reg = <0 0x1600 0 0x1000>;
Re: [PATCH 16/27] arm64: dts: mediatek: mt6795: Add support for the CMDQ/GCE mailbox
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
In preparation for adding multimedia blocks, add the CMDQ/GCE mailbox.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 090400d7fd61..99cc4918e6ba 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -401,6 +402,15 @@ fhctl: clock-controller@10209f00 {
status = "disabled";
};
+ gce: mailbox@10212000 {
+ compatible = "mediatek,mt6795-gce",
"mediatek,mt8173-gce";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ;
+ clocks = < CLK_INFRA_GCE>;
+ clock-names = "gce";
+ #mbox-cells = <2>;
+ };
+
gic: interrupt-controller@10221000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
Re: [PATCH 01/27] dt-bindings: pwm: Add compatible for MediaTek MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795's display PWM block: this is the same as MT8173. Signed-off-by: AngeloGioacchino Del Regno Applied, thanks! --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 0088bc8e7c54..153e146df7d4 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -22,7 +22,9 @@ properties: - mediatek,mt8173-disp-pwm - mediatek,mt8183-disp-pwm - items: - - const: mediatek,mt8167-disp-pwm + - enum: + - mediatek,mt6795-disp-pwm + - mediatek,mt8167-disp-pwm - const: mediatek,mt8173-disp-pwm - items: - enum:
Re: [PATCH v2] phy: mediatek: rework the floating point comparisons to fixed point
On 02/05/2023 16:50, Tom Rix wrote:
gcc on aarch64 reports
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c: In function ‘mtk_hdmi_pll_set_rate’:
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240:52: error: ‘-mgeneral-regs-only’
is incompatible with the use of floating-point types
240 | else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA)
Floating point should not be used, so rework the floating point comparisons
to fixed point.
Signed-off-by: Tom Rix
I think this is worth a fixes tag.
Regards,
Matthias
---
v2: silence robot by casting types to u64
---
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
index abfc077fb0a8..093c4d1da557 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
@@ -237,11 +237,11 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy
*hdmi_phy, struct clk_hw *hw,
*/
if (tmds_clk < 54 * MEGA)
txposdiv = 8;
- else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA)
+ else if (tmds_clk >= 54 * MEGA && (tmds_clk * 100) < 14835 * MEGA)
txposdiv = 4;
- else if (tmds_clk >= 148.35 * MEGA && tmds_clk < 296.7 * MEGA)
+ else if ((tmds_clk * 100) >= 14835 * MEGA && (tmds_clk * 10) < 2967 *
MEGA)
txposdiv = 2;
- else if (tmds_clk >= 296.7 * MEGA && tmds_clk <= 594 * MEGA)
+ else if ((tmds_clk * 10) >= 2967 * MEGA && tmds_clk <= 594 * MEGA)
txposdiv = 1;
else
return -EINVAL;
@@ -328,12 +328,12 @@ static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw)
clk_channel_bias = 0x34; /* 20mA */
impedance_en = 0xf;
impedance = 0x36; /* 100ohm */
- } else if (pixel_clk >= 74.175 * MEGA && pixel_clk <= 300 * MEGA) {
+ } else if (((u64)pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300
* MEGA) {
data_channel_bias = 0x34; /* 20mA */
clk_channel_bias = 0x2c; /* 16mA */
impedance_en = 0xf;
impedance = 0x36; /* 100ohm */
- } else if (pixel_clk >= 27 * MEGA && pixel_clk < 74.175 * MEGA) {
+ } else if (pixel_clk >= 27 * MEGA && ((u64)pixel_clk * 1000) < 74175 *
MEGA) {
data_channel_bias = 0x14; /* 10mA */
clk_channel_bias = 0x14; /* 10mA */
impedance_en = 0x0;
Re: [PATCH 29/53] drm/mediatek: Convert to platform remove callback returning void
On 07/05/2023 18:25, Uwe Kleine-König wrote:
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert the mediatek drm drivers from always returning zero in
the remove callback to the void returning variant.
Signed-off-by: Uwe Kleine-König
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_disp_aal.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_color.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++
drivers/gpu/drm/mediatek/mtk_dp.c | 6 ++
drivers/gpu/drm/mediatek/mtk_dpi.c| 6 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c| 6 ++
drivers/gpu/drm/mediatek/mtk_dsi.c| 6 ++
drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 ++---
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c | 6 ++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 5 ++---
14 files changed, 28 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
index 434e8a9ce8ab..cbd9b4becc43 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
@@ -140,11 +140,9 @@ static int mtk_disp_aal_probe(struct platform_device *pdev)
return ret;
}
-static int mtk_disp_aal_remove(struct platform_device *pdev)
+static void mtk_disp_aal_remove(struct platform_device *pdev)
{
component_del(>dev, _disp_aal_component_ops);
-
- return 0;
}
static const struct mtk_disp_aal_data mt8173_aal_driver_data = {
@@ -161,7 +159,7 @@ MODULE_DEVICE_TABLE(of, mtk_disp_aal_driver_dt_match);
struct platform_driver mtk_disp_aal_driver = {
.probe = mtk_disp_aal_probe,
- .remove = mtk_disp_aal_remove,
+ .remove_new = mtk_disp_aal_remove,
.driver = {
.name = "mediatek-disp-aal",
.owner = THIS_MODULE,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 1773379b2439..fa6dbc4e9c35 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -195,11 +195,9 @@ static int mtk_disp_ccorr_probe(struct platform_device
*pdev)
return ret;
}
-static int mtk_disp_ccorr_remove(struct platform_device *pdev)
+static void mtk_disp_ccorr_remove(struct platform_device *pdev)
{
component_del(>dev, _disp_ccorr_component_ops);
-
- return 0;
}
static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
@@ -221,7 +219,7 @@ MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
struct platform_driver mtk_disp_ccorr_driver = {
.probe = mtk_disp_ccorr_probe,
- .remove = mtk_disp_ccorr_remove,
+ .remove_new = mtk_disp_ccorr_remove,
.driver = {
.name = "mediatek-disp-ccorr",
.owner = THIS_MODULE,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c
b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index cac9206079e7..78e44e6befd6 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -132,11 +132,9 @@ static int mtk_disp_color_probe(struct platform_device
*pdev)
return ret;
}
-static int mtk_disp_color_remove(struct platform_device *pdev)
+static void mtk_disp_color_remove(struct platform_device *pdev)
{
component_del(>dev, _disp_color_component_ops);
-
- return 0;
}
static const struct mtk_disp_color_data mt2701_color_driver_data = {
@@ -164,7 +162,7 @@ MODULE_DEVICE_TABLE(of, mtk_disp_color_driver_dt_match);
struct platform_driver mtk_disp_color_driver = {
.probe = mtk_disp_color_probe,
- .remove = mtk_disp_color_remove,
+ .remove_new = mtk_disp_color_remove,
.driver = {
.name = "mediatek-disp-color",
.owner = THIS_MODULE,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
index c844942603f7..c5237f4eb7fe 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -183,11 +183,9 @@ static int mtk_disp_gamma_probe(struct platform_device
*pdev)
return ret;
}
-static int mtk_disp_gamma_remove(stru
Re: [PATCH 28/53] drm/mediatek: Convert to platform remove callback returning void
On 07/05/2023 18:25, Uwe Kleine-König wrote:
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_cec.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c
b/drivers/gpu/drm/mediatek/mtk_cec.c
index b640bc0559e7..f47f417d8ba6 100644
--- a/drivers/gpu/drm/mediatek/mtk_cec.c
+++ b/drivers/gpu/drm/mediatek/mtk_cec.c
@@ -235,13 +235,12 @@ static int mtk_cec_probe(struct platform_device *pdev)
return 0;
}
-static int mtk_cec_remove(struct platform_device *pdev)
+static void mtk_cec_remove(struct platform_device *pdev)
{
struct mtk_cec *cec = platform_get_drvdata(pdev);
mtk_cec_htplg_irq_disable(cec);
clk_disable_unprepare(cec->clk);
- return 0;
}
static const struct of_device_id mtk_cec_of_ids[] = {
@@ -252,7 +251,7 @@ MODULE_DEVICE_TABLE(of, mtk_cec_of_ids);
struct platform_driver mtk_cec_driver = {
.probe = mtk_cec_probe,
- .remove = mtk_cec_remove,
+ .remove_new = mtk_cec_remove,
.driver = {
.name = "mediatek-cec",
.of_match_table = mtk_cec_of_ids,
Re: [PATCH] phy: mediatek: fix returning garbage
On 08/05/2023 09:48, Vinod Koul wrote: On 05-05-23, 17:37, Matthias Brugger wrote: On 05/05/2023 11:28, Vinod Koul wrote: On 14-04-23, 08:22, Tom Rix wrote: clang reports drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized] if (ret) ^~~ ret should have been set by the preceding call to mtk_hdmi_pll_set_hw. I have applied "phy: mediatek: hdmi: mt8195: fix uninitialized variable usage in pll_calc" Thanks Vinod, that was on my list for today as well. I was a bit puzzled because you took the patch that added it, but I wasn't sure if you would take the fix. How do you want to handle things like this in the future? Fixes should be sent as Fixes patch I'm not sure what do you mean. Patch subject includes the word fix and the patch has a fixes tag. What was missing here? Does this mean you will take fixes for this driver in the future or do you want me to take care of them? Regards, Matthias
Re: [PATCH] phy: mediatek: fix returning garbage
On 05/05/2023 11:28, Vinod Koul wrote: On 14-04-23, 08:22, Tom Rix wrote: clang reports drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized] if (ret) ^~~ ret should have been set by the preceding call to mtk_hdmi_pll_set_hw. I have applied "phy: mediatek: hdmi: mt8195: fix uninitialized variable usage in pll_calc" Thanks Vinod, that was on my list for today as well. I was a bit puzzled because you took the patch that added it, but I wasn't sure if you would take the fix. How do you want to handle things like this in the future? Regards, Matthias
Re: [PATCH v2 2/2] drm/mediatek: Add DSI support for mt8188 vdosys0
On 27/04/2023 10:40, Jason-JH.Lin wrote:
Add DSI as main display output for mt8188 vdosys0.
Signed-off-by: Nathan Lu
Signed-off-by: Jason-JH.Lin
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +
drivers/gpu/drm/mediatek/mtk_dsi.c | 9 +
4 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 72c57442f965..bf06ccb65652 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -48,6 +48,7 @@ int mtk_dpi_encoder_index(struct device *dev);
void mtk_dsi_ddp_start(struct device *dev);
void mtk_dsi_ddp_stop(struct device *dev);
+int mtk_dsi_encoder_index(struct device *dev);
int mtk_gamma_clk_enable(struct device *dev);
void mtk_gamma_clk_disable(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index fe20ce26b19f..214233d36487 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -318,6 +318,7 @@ static const struct mtk_ddp_comp_funcs ddp_dsc = {
static const struct mtk_ddp_comp_funcs ddp_dsi = {
.start = mtk_dsi_ddp_start,
.stop = mtk_dsi_ddp_stop,
+ .encoder_index = mtk_dsi_encoder_index,
};
static const struct mtk_ddp_comp_funcs ddp_gamma = {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index d8c49614a107..7ea4dc87c558 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -191,8 +191,13 @@ static const unsigned int mt8188_mtk_ddp_main_routes_0[] =
{
DDP_COMPONENT_DP_INTF0
};
+static const unsigned int mt8188_mtk_ddp_main_routes_1[] = {
+ DDP_COMPONENT_DSI0
+};
+
static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {
{0, ARRAY_SIZE(mt8188_mtk_ddp_main_routes_0),
mt8188_mtk_ddp_main_routes_0},
+ {0, ARRAY_SIZE(mt8188_mtk_ddp_main_routes_1),
mt8188_mtk_ddp_main_routes_1},
};
static const unsigned int mt8192_mtk_ddp_main[] = {
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 7d5250351193..f9d2d5447e2e 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -865,6 +865,15 @@ static int mtk_dsi_encoder_init(struct drm_device *drm,
struct mtk_dsi *dsi)
return ret;
}
+int mtk_dsi_encoder_index(struct device *dev)
+{
+ struct mtk_dsi *dsi = dev_get_drvdata(dev);
+ int encoder_index = drm_encoder_index(>encoder);
+
+ dev_dbg(dev, "encoder index:%d", encoder_index);
+ return encoder_index;
+}
+
static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
{
int ret;
Re: [PATCH v2 1/2] drm/mediatek: Add ability to support dynamic connector selection
On 27/04/2023 10:40, Jason-JH.Lin wrote:
1. Move output drm connector from each ddp_path array to connector array.
2. Add dynamic select available connector flow in crtc create and enable.
Signed-off-by: Nancy Lin
Signed-off-by: Nathan Lu
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_dpi.c | 9 ++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 112 +++-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 5 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 27 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 8 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 44 ++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 8 ++
8 files changed, 203 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 2254038519e1..72c57442f965 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -44,6 +44,7 @@ void mtk_dither_set_common(void __iomem *regs, struct
cmdq_client_reg *cmdq_reg,
void mtk_dpi_start(struct device *dev);
void mtk_dpi_stop(struct device *dev);
+int mtk_dpi_encoder_index(struct device *dev);
void mtk_dsi_ddp_start(struct device *dev);
void mtk_dsi_ddp_stop(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 948a53f1f4b3..765fc976e41f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -782,6 +782,15 @@ void mtk_dpi_stop(struct device *dev)
mtk_dpi_power_off(dpi);
}
+int mtk_dpi_encoder_index(struct device *dev)
+{
+ struct mtk_dpi *dpi = dev_get_drvdata(dev);
+ int encoder_index = drm_encoder_index(>encoder);
+
+ dev_dbg(dev, "encoder index:%d", encoder_index);
+ return encoder_index;
+}
+
static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
{
struct mtk_dpi *dpi = dev_get_drvdata(dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index d40142842f85..2bafd377dcf4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -60,8 +60,12 @@ struct mtk_drm_crtc {
struct device *mmsys_dev;
struct device *dma_dev;
struct mtk_mutex*mutex;
+ unsigned intddp_comp_nr_ori;
+ unsigned intmax_ddp_comp_nr;
unsigned intddp_comp_nr;
struct mtk_ddp_comp **ddp_comp;
+ unsigned intconn_route_nr;
+ const struct mtk_drm_route *conn_routes;
/* lock for display hardware access */
struct mutexhw_lock;
@@ -649,6 +653,85 @@ static void mtk_drm_crtc_disable_vblank(struct drm_crtc
*crtc)
mtk_ddp_comp_disable_vblank(comp);
}
+static unsigned int mtk_drm_crtc_max_num_route_comp(struct mtk_drm_crtc *mtk_crtc)
+{
+ unsigned int max_num = 0;
+ unsigned int i;
+
+ if (!mtk_crtc->conn_route_nr)
+ return 0;
+
+ for (i = 0; i < mtk_crtc->conn_route_nr; i++)
+ if (max_num < mtk_crtc->conn_routes[i].route_len)
+ max_num = mtk_crtc->conn_routes[i].route_len;
max_num = max(mtk_crtc->conn_routes[i].route_len, max_num);
Regards,
Matthias
+
+ return max_num;
+}
+
+static int mtk_drm_crtc_update_output(struct drm_crtc *crtc,
+ struct drm_atomic_state *state)
+{
+ const struct mtk_drm_route *conn_routes;
+ int crtc_index = drm_crtc_index(crtc);
+ int i;
+ struct device *dev;
+ struct drm_crtc_state *crtc_state = state->crtcs[crtc_index].new_state;
+ struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+ struct mtk_drm_private *priv = crtc->dev->dev_private;
+ unsigned int comp_id;
+ unsigned int encoder_mask = crtc_state->encoder_mask;
+ unsigned int route_len = 0, route_index = 0;
+
+ if (!mtk_crtc->conn_route_nr)
+ return 0;
+
+ priv = priv->all_drm_private[crtc_index];
+ dev = priv->dev;
+
+ dev_dbg(dev, "connector change:%d, encoder mask0x%x for crtc%d",
+ crtc_state->connectors_changed, encoder_mask, crtc_index);
+
+ if (!crtc_state->connectors_changed)
+ return 0;
+
+ conn_routes = mtk_crtc->conn_routes;
+
+ for (i = 0; i < mtk_crtc->conn_route_nr; i++) {
+ route_len = conn_routes[i].route_len;
+ if (route_len > 0) {
+ comp_id = conn_routes[i].route_ddp[route_len - 1];
+ if (priv->comp_node[comp_id]) {
+ if ((1 <<
priv->ddp_comp[comp_id].encoder_index) == encoder_mask) {
+
Re: [PATCH] phy: mediatek/mt8195: fx mtk_hdmi_pll_calc() return code
Hi Arnd,
On 14/04/2023 09:58, Arnd Bergmann wrote:
From: Arnd Bergmann
The newly added function returns an uninitialized variable:
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable 'ret' is
uninitialized when used here [-Werror,-Wuninitialized]
Wire it up to the return code of the function called just before,
assuming that this was the intention originally.
Fixes: 45810d486bb4 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
Signed-off-by: Arnd Bergmann
---
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
index abfc077fb0a8..c8e540665fcb 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
@@ -292,7 +292,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy,
struct clk_hw *hw,
if (!(digital_div <= 32 && digital_div >= 1))
return -EINVAL;
- mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low,
+ ret = mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low,
PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv,
txposdiv, digital_div);
if (ret)
I think this is the third patch that fixes this :) Your solution look quite
similar to this one:
20230413-fixes-for-mt8195-hdmi-phy-v2-1-bbad62e64...@baylibre.com
Regards,
Mmatthias
Re: [PATCH 01/27] dt-bindings: pwm: Add compatible for MediaTek MT6795
On 14/04/2023 07:43, Uwe Kleine-König wrote: Hello, On Wed, Apr 12, 2023 at 01:27:13PM +0200, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795's display PWM block: this is the same as MT8173. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Uwe Kleine-König I assume this patch will go in together with the other patches in this series via an ARM tree? (I.e. not via pwm.) That's totally fine, I'll take this patch through my tree once everything is ready. Regards, Matthias
Re: [PATCH] dt-bindings: display: mediatek: simplify compatibles syntax
On 14/04/2023 10:33, Krzysztof Kozlowski wrote: Lists (items) with one item should be just enum because it is shorter, simpler and does not confuse, if one wants to add new entry with a fallback. Convert all of them to enums. OTOH, leave unused "oneOf" entries in anticipation of further growth of the entire binding. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Matthias Brugger --- Cc: angelogioacchino.delre...@collabora.com --- .../bindings/display/mediatek/mediatek,ccorr.yaml | 7 +++ .../bindings/display/mediatek/mediatek,color.yaml | 10 -- .../bindings/display/mediatek/mediatek,dither.yaml | 4 ++-- .../bindings/display/mediatek/mediatek,dsc.yaml | 4 ++-- .../bindings/display/mediatek/mediatek,gamma.yaml | 7 +++ .../bindings/display/mediatek/mediatek,merge.yaml | 7 +++ .../bindings/display/mediatek/mediatek,od.yaml | 7 +++ .../bindings/display/mediatek/mediatek,ovl-2l.yaml | 7 +++ .../bindings/display/mediatek/mediatek,ovl.yaml | 13 + .../display/mediatek/mediatek,postmask.yaml | 4 ++-- .../bindings/display/mediatek/mediatek,rdma.yaml| 13 + .../bindings/display/mediatek/mediatek,split.yaml | 4 ++-- .../bindings/display/mediatek/mediatek,ufoe.yaml| 4 ++-- .../bindings/display/mediatek/mediatek,wdma.yaml| 4 ++-- 14 files changed, 41 insertions(+), 54 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index b04820c95b22..dc22bd522523 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -21,10 +21,9 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt8183-disp-ccorr - - items: - - const: mediatek,mt8192-disp-ccorr + - enum: + - mediatek,mt8183-disp-ccorr + - mediatek,mt8192-disp-ccorr - items: - enum: - mediatek,mt8188-disp-ccorr diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index 62306c88f485..d0ea77fc4b06 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -22,12 +22,10 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt2701-disp-color - - items: - - const: mediatek,mt8167-disp-color - - items: - - const: mediatek,mt8173-disp-color + - enum: + - mediatek,mt2701-disp-color + - mediatek,mt8167-disp-color + - mediatek,mt8173-disp-color - items: - enum: - mediatek,mt7623-disp-color diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 5c7445c174e5..1588b3f7cec7 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -22,8 +22,8 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt8183-disp-dither + - enum: + - mediatek,mt8183-disp-dither - items: - enum: - mediatek,mt8186-disp-dither diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml index 49248864514b..2cbdd9ee449d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml @@ -20,8 +20,8 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt8195-disp-dsc + - enum: + - mediatek,mt8195-disp-dsc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index a5c6a91fac71..6c2be9d6840b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -21,10 +21,9 @@ description: | properties: compatible: oneOf: - - items: - - const: mediatek,mt8173-disp-gamma - - items: - - const: mediatek,mt8183-disp-gamma + - enum: + - mediatek,mt8173-disp-gamma + - mediatek,mt8183-disp-gamma - items: - enum: - mediatek,mt8186-disp-gamma diff --git a/Documentation/devicetre
Re: [PATCH v2 1/2] phy: mediatek: hdmi: mt8195: fix uninitialized variable usage in pll_calc
On 14/04/2023 18:07, Guillaume Ranquet wrote:
The ret variable in mtk_hdmi_pll_calc() was used unitialized as reported
by the kernel test robot.
Fix the issue by removing the variable altogether and testing out the
return value of mtk_hdmi_pll_set_hw()
Fixes: 45810d486bb44 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
Reported-by: kernel test robot
Signed-off-by: Guillaume Ranquet
Looks good, but got unfortunately already fixed 4 hours ago with
20230414122253.3171524-1-t...@redhat.com
:)
Regards,
Matthias
---
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
index abfc077fb0a8..054b73cb31ee 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
@@ -213,7 +213,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy,
struct clk_hw *hw,
u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw;
u8 txpredivs[4] = { 2, 4, 6, 12 };
u32 fbkdiv_low;
- int i, ret;
+ int i;
pixel_clk = rate;
tmds_clk = pixel_clk;
@@ -292,13 +292,9 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy
*hdmi_phy, struct clk_hw *hw,
if (!(digital_div <= 32 && digital_div >= 1))
return -EINVAL;
- mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low,
+ return mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low,
PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv,
txposdiv, digital_div);
- if (ret)
- return -EINVAL;
-
- return 0;
}
static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw)
Re: [PATCH] phy: mediatek: fix returning garbage
On 14/04/2023 17:43, Matthias Brugger wrote:
On 14/04/2023 14:22, Tom Rix wrote:
clang reports
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable
'ret' is uninitialized when used here [-Werror,-Wuninitialized]
if (ret)
^~~
ret should have been set by the preceding call to mtk_hdmi_pll_set_hw.
Fixes: 45810d486bb4 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
Signed-off-by: Tom Rix
Reviewed-by: Matthias Brugger
Please also add
Reported-by: Linux Kernel Functional Testing
see CA+G9fYu4o0-ZKSthi7kdCjz_kFazZS-rn17Z2NPz3=1oayr...@mail.gmail.com
Regards,
Matthias
---
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
index abfc077fb0a8..c63294e451d6 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
@@ -292,9 +292,9 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy
*hdmi_phy, struct clk_hw *hw,
if (!(digital_div <= 32 && digital_div >= 1))
return -EINVAL;
- mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low,
- PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv,
- txposdiv, digital_div);
+ ret = mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low,
+ PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv,
+ txposdiv, digital_div);
if (ret)
return -EINVAL;
Re: [PATCH] phy: mediatek: fix returning garbage
On 14/04/2023 14:22, Tom Rix wrote:
clang reports
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: error: variable
'ret' is uninitialized when used here [-Werror,-Wuninitialized]
if (ret)
^~~
ret should have been set by the preceding call to mtk_hdmi_pll_set_hw.
Fixes: 45810d486bb4 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
Signed-off-by: Tom Rix
Reviewed-by: Matthias Brugger
---
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
index abfc077fb0a8..c63294e451d6 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
@@ -292,9 +292,9 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy,
struct clk_hw *hw,
if (!(digital_div <= 32 && digital_div >= 1))
return -EINVAL;
- mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low,
- PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv,
- txposdiv, digital_div);
+ ret = mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low,
+ PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv,
+ txposdiv, digital_div);
if (ret)
return -EINVAL;
Re: [PATCH 3/3] drm/mediatek: dsi: Add dsi cmdq_ctl to send panel initial code
On 13/04/2023 08:09, xinlei@mediatek.com wrote:
From: Xinlei Lee
For mt8188, add dsi cmdq reg control to send long packets to panel
initialization.
Signed-off-by: Xinlei Lee
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 500a3054282d..cbfe5df4647c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -86,6 +86,7 @@
#define DSI_CMDQ_SIZE 0x60
#define CMDQ_SIZE 0x3f
+#define CMDQ_SIZE_SEL BIT(15)
#define DSI_HSTX_CKL_WC 0x64
@@ -178,6 +179,7 @@ struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
bool has_shadow_ctl;
bool has_size_ctl;
+ bool cmdq_long_packet_ctl;
};
struct mtk_dsi {
@@ -965,6 +967,11 @@ static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
return 0;
}
+static void mtk_dsi_cmd_packet_ctl(struct mtk_dsi *dsi)
+{
+ mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL);
+}
+
static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
{
const char *tx_buf = msg->tx_buf;
@@ -996,6 +1003,8 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct
mipi_dsi_msg *msg)
mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
+ if (dsi->driver_data->cmdq_long_packet_ctl)
+ mtk_dsi_cmd_packet_ctl(dsi);
Why don't you put the onliner
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL);
directly here. Please help me understand why adding another indirection is
usefull here.
Best regards,
Matthias
}
static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
@@ -1200,18 +1209,21 @@ static const struct mtk_dsi_driver_data
mt8183_dsi_driver_data = {
.reg_cmdq_off = 0x200,
.has_shadow_ctl = true,
.has_size_ctl = true,
+ .cmdq_long_packet_ctl = false,
};
static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
.reg_cmdq_off = 0xd00,
.has_shadow_ctl = true,
.has_size_ctl = true,
+ .cmdq_long_packet_ctl = false,
};
static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
.reg_cmdq_off = 0xd00,
.has_shadow_ctl = true,
.has_size_ctl = true,
+ .cmdq_long_packet_ctl = true,
};
static const struct of_device_id mtk_dsi_of_match[] = {
Re: [PATCH 2/3] drm/mediatek: Add mt8188 dsi compatible to mtk_dsi.c
On 13/04/2023 08:09, xinlei@mediatek.com wrote:
From: Xinlei Lee
Add the compatible because there are different definitions for cmdq
register bit control in mt8188.
Signed-off-by: Xinlei Lee
Signed-off-by: Jitao Shi
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
drivers/gpu/drm/mediatek/mtk_dsi.c | 8
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a13b36ac03a1..9ba05961479d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -654,6 +654,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8186-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8188-dsi",
+ .data = (void *)MTK_DSI },
{ }
};
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 7d5250351193..500a3054282d 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1208,6 +1208,12 @@ static const struct mtk_dsi_driver_data
mt8186_dsi_driver_data = {
.has_size_ctl = true,
};
+static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
+ .reg_cmdq_off = 0xd00,
+ .has_shadow_ctl = true,
+ .has_size_ctl = true,
+};
+
static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt2701-dsi",
.data = _dsi_driver_data },
@@ -1217,6 +1223,8 @@ static const struct of_device_id mtk_dsi_of_match[] = {
.data = _dsi_driver_data },
{ .compatible = "mediatek,mt8186-dsi",
.data = _dsi_driver_data },
+ { .compatible = "mediatek,mt8188-dsi",
+ .data = _dsi_driver_data },
{ },
};
MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
Re: [PATCH 1/3] dt-bindings: display: mediatek: dsi: Add compatible for MediaTek MT8188
On 13/04/2023 08:09, xinlei@mediatek.com wrote: From: Xinlei Lee Add dt-binding documentation of dsi for MediaTek MT8188 SoC. Signed-off-by: Xinlei Lee Signed-off-by: Jitao Shi Reviewed-by: Matthias Brugger --- .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml index 4707b60238b0..13fa76299254 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -29,6 +29,7 @@ properties: - mediatek,mt8173-dsi - mediatek,mt8183-dsi - mediatek,mt8186-dsi + - mediatek,mt8188-dsi reg: maxItems: 1
Re: [PATCH 02/27] dt-bindings: phy: mediatek, dsi-phy: Add compatible for MT6795 Helio X10
On 12/04/2023 15:17, AngeloGioacchino Del Regno wrote: Il 12/04/23 15:12, Alexandre Mergnat ha scritto: On 12/04/2023 15:03, AngeloGioacchino Del Regno wrote: Il 12/04/23 14:59, Alexandre Mergnat ha scritto: On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795: this SoC uses the same DSI PHY as MT8173. Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index 26f2b887cfc1..a9f78344efdb 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -24,6 +24,10 @@ properties: - enum: - mediatek,mt7623-mipi-tx - const: mediatek,mt2701-mipi-tx + - items: + - enum: + - mediatek,mt6795-mipi-tx + - const: mediatek,mt8173-mipi-tx AFAIK, it should be: - items: - const: mediatek,mt6795-mipi-tx - const: mediatek,mt8173-mipi-tx Since it isn't respected above for mt7623, it may be tolerated. Please, take this comment as a suggestion, isn't a NAK from me. First of all, Thanks! I want to explain, though, the reason for that. If you check all the commits, on some I did it as you just proposed, while on some others I did it with an enum before const: that's simply because I *totally expect* some to grow, while others (const - const) I was either unsure, or totally *not* expecting them to grow soon! That's what I thought. IMHO, if someone add another compat later, he will be on charge to change the const by enum front of your "mediatek,mt6795-mipi-tx". But my opinion is probably not the most popular. I will not make the same feedback for the other patches in this series. I honestly don't know what's the most popular opinion about that... but whatever, in any case... just want to make sure to communicate that I don't really have strong opinions about doing it one way or the other. The arguments in favor and against that are probably 1:1... :-D Then let me throw in another one :) Take into account that if we expect the compatible to be added somtimes in the future (not the near future) this code will lay around for some time. People will take this code as an example for new code, then we will need to explain it... In that sense it would make more sense to have all made const: const: and change this to enum once a new compatible is added to the mix. Said all this, I leave it to the DT maintainers to decide :D Regards, Matthias
Re: [PATCH 01/27] dt-bindings: pwm: Add compatible for MediaTek MT6795
On 12/04/2023 23:03, Rob Herring wrote: On Wed, 12 Apr 2023 13:27:13 +0200, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795's display PWM block: this is the same as MT8173. Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. These are not new warnings. I think we should address them in a different patch. In my opinion it shouldn't block this patch. In the end it only add as compatible here. Regards, Matthias Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230412112739.160376-2-angelogioacchino.delre...@collabora.com pwm@1100e000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/mediatek/mt8183-evb.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dtb arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dtb arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dtb pwm@1400a000: compatible: 'oneOf' conditional failed, one must be fixed: arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dtb arch/arm/boot/dts/mt7623n-rfb-emmc.dtb pwm@1401e000: compatible: 'oneOf' conditional failed, one must be fixed: arch/arm64/boot/dts/mediatek/mt8173-elm.dtb arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtb arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dtb arch/arm64/boot/dts/mediatek/mt8173-evb.dtb pwm@1401f000: compatible: 'oneOf' conditional failed, one must be fixed: arch/arm64/boot/dts/mediatek/mt8173-elm.dtb arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtb arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dtb arch/arm64/boot/dts/mediatek/mt8173-evb.dtb
Re: [PATCH 27/27] arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMM050 Magnetometer
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
This smartphone features a Bosch BMM050 Magnetometer on I2C3: enable
it with the BMM150 binding, as that driver supports BMM050 as well.
For this sensor, there is no interrupt pin;
readings were validated in sysfs.
Signed-off-by: AngeloGioacchino Del Regno
Applied :)
---
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index 0b0519f6b2f1..b5746e6d0b15 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -75,6 +75,11 @@ accelerometer@10 {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
};
+
+ magnetometer@12 {
+ compatible = "bosch,bmm150";
+ reg = <0x12>;
+ };
};
{
Re: [PATCH 26/27] arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMA255 Accelerometer
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
Add the BMA255 Accelerometer on I2C3 and its pin definitions.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
.../boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index 155a573eac4c..0b0519f6b2f1 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -68,6 +68,13 @@ {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "okay";
+
+ accelerometer@10 {
+ compatible = "bosch,bma255";
+ reg = <0x10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ };
};
{
@@ -247,6 +254,14 @@ pins-irq {
};
};
+ accel_pins: accelerometer-pins {
+ pins-irq {
+ pinmux = ;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
i2c0_pins: i2c0-pins {
pins-bus {
pinmux = ,
Re: [PATCH 20/27] arm64: dts: mediatek: mt6795: Add tertiary PWM node
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote:
The PWM at 0x11006000 is the tertiary PWM; unlike PWM0, PWM1, this is
not display specific and can be used as a generic PWM controller.
This node is left disabled as usage is board-specific.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks!
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index cf45cb4ad3d2..50d9276d18c6 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -583,6 +583,25 @@ uart3: serial@11005000 {
status = "disabled";
};
+ pwm2: pwm@11006000 {
+ compatible = "mediatek,mt6795-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ #pwm-cells = <2>;
+ interrupts = ;
+ clocks = < CLK_TOP_PWM_SEL>,
+< CLK_PERI_PWM>,
+< CLK_PERI_PWM1>,
+< CLK_PERI_PWM2>,
+< CLK_PERI_PWM3>,
+< CLK_PERI_PWM4>,
+< CLK_PERI_PWM5>,
+< CLK_PERI_PWM6>,
+< CLK_PERI_PWM7>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+ "pwm4", "pwm5", "pwm6", "pwm7";
+ status = "disabled";
+ };
+
i2c0: i2c@11007000 {
compatible = "mediatek,mt6795-i2c",
"mediatek,mt8173-i2c";
reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;
Re: [PATCH 22/27] arm64: dts: mediatek: mt6795: Copyright header additions
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: I have added more than 800 lines to this devicetree: adding myself to the copyright header. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 29ca9a7bf0b3..a4c950b65006 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -2,6 +2,9 @@ /* * Copyright (c) 2015 MediaTek Inc. * Author: Mars.C + * + * Copyright (C) 2023 Collabora Ltd. + *AngeloGioacchino Del Regno Indentation? BTW from what I understand the copyright will be by your employer, Collabora not you, but I'm not an legal expert :) */ #include
Re: [PATCH 15/27] dt-bindings: mailbox: mediatek,gce-mailbox: Add support for MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for the MT6795 Helio X10 SoC using MT8173 binding and add a header for the MT6795's GCE mailbox. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Reviewed-by: Matthias Brugger --- .../mailbox/mediatek,gce-mailbox.yaml | 20 +-- include/dt-bindings/gce/mediatek,mt6795-gce.h | 123 ++ 2 files changed, 135 insertions(+), 8 deletions(-) create mode 100644 include/dt-bindings/gce/mediatek,mt6795-gce.h diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml index d383b2ab3ce8..cef9d7601398 100644 --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml @@ -16,14 +16,18 @@ description: properties: compatible: -enum: - - mediatek,mt6779-gce - - mediatek,mt8173-gce - - mediatek,mt8183-gce - - mediatek,mt8186-gce - - mediatek,mt8188-gce - - mediatek,mt8192-gce - - mediatek,mt8195-gce +oneOf: + - enum: + - mediatek,mt6779-gce + - mediatek,mt8173-gce + - mediatek,mt8183-gce + - mediatek,mt8186-gce + - mediatek,mt8188-gce + - mediatek,mt8192-gce + - mediatek,mt8195-gce + - items: + - const: mediatek,mt6795-gce + - const: mediatek,mt8173-gce "#mbox-cells": const: 2 diff --git a/include/dt-bindings/gce/mediatek,mt6795-gce.h b/include/dt-bindings/gce/mediatek,mt6795-gce.h new file mode 100644 index ..97d5ba2d2b44 --- /dev/null +++ b/include/dt-bindings/gce/mediatek,mt6795-gce.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ +#ifndef _DT_BINDINGS_GCE_MT6795_H +#define _DT_BINDINGS_GCE_MT6795_H + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_NORMAL 1 +#define CMDQ_THR_PRIO_NORMAL_2 2 +#define CMDQ_THR_PRIO_MEDIUM 3 +#define CMDQ_THR_PRIO_MEDIUM_2 4 +#define CMDQ_THR_PRIO_HIGH 5 +#define CMDQ_THR_PRIO_HIGHER 6 +#define CMDQ_THR_PRIO_HIGHEST 7 + +/* GCE SUBSYS */ +#define SUBSYS_13000 +#define SUBSYS_14001 +#define SUBSYS_14012 +#define SUBSYS_14023 +#define SUBSYS_15004 +#define SUBSYS_16005 +#define SUBSYS_17006 +#define SUBSYS_18007 +#define SUBSYS_10008 +#define SUBSYS_10019 +#define SUBSYS_100210 +#define SUBSYS_100311 +#define SUBSYS_100412 +#define SUBSYS_100513 +#define SUBSYS_102014 +#define SUBSYS_102115 +#define SUBSYS_112016 +#define SUBSYS_112117 +#define SUBSYS_112218 +#define SUBSYS_112319 +#define SUBSYS_112420 +#define SUBSYS_112521 +#define SUBSYS_112622 + +/* GCE HW EVENT */ +#define CMDQ_EVENT_MDP_RDMA0_SOF 0 +#define CMDQ_EVENT_MDP_RDMA1_SOF 1 +#define CMDQ_EVENT_MDP_DSI0_TE_SOF 2 +#define CMDQ_EVENT_MDP_DSI1_TE_SOF 3 +#define CMDQ_EVENT_MDP_MVW_SOF 4 +#define CMDQ_EVENT_MDP_TDSHP0_SOF 5 +#define CMDQ_EVENT_MDP_TDSHP1_SOF 6 +#define CMDQ_EVENT_MDP_WDMA_SOF7 +#define CMDQ_EVENT_MDP_WROT0_SOF 8 +#define CMDQ_EVENT_MDP_WROT1_SOF 9 +#define CMDQ_EVENT_MDP_CROP_SOF10 +#define CMDQ_EVENT_DISP_OVL0_SOF 11 +#define CMDQ_EVENT_DISP_OVL1_SOF 12 +#define CMDQ_EVENT_DISP_RDMA0_SOF 13 +#define CMDQ_EVENT_DISP_RDMA1_SOF 14 +#define CMDQ_EVENT_DISP_RDMA2_SOF 15 +#define CMDQ_EVENT_DISP_WDMA0_SOF 16 +#define CMDQ_EVENT_DISP_WDMA1_SOF 17 +#define CMDQ_EVENT_DISP_COLOR0_SOF 18 +#define CMDQ_EVENT_DISP_COLOR1_SOF 19 +#define CMDQ_EVENT_DISP_AAL_SOF20 +#define CMDQ_EVENT_DISP_GAMMA_SOF 2
Re: [PATCH 14/27] dt-bindings: display: mediatek: od: Add compatible for MediaTek MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795's OverDrive (OD) block: this is the same as MT8173. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/display/mediatek/mediatek,od.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml index 853fcb9db2be..691a3644504f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml @@ -25,6 +25,9 @@ properties: - const: mediatek,mt2712-disp-od - items: - const: mediatek,mt8173-disp-od + - items: + - const: mediatek,mt6795-disp-od + - const: mediatek,mt8173-disp-od Reviewed-by: Matthias Brugger reg: maxItems: 1
Re: [PATCH 13/27] dt-bindings: display: mediatek: ufoe: Add compatible for MediaTek MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795's UFOE block: this is the same as MT8173. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/display/mediatek/mediatek,ufoe.yaml| 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml index b8bb135fe96b..282925a73804 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml @@ -24,6 +24,9 @@ properties: oneOf: - items: - const: mediatek,mt8173-disp-ufoe + - items: + - const: mediatek,mt6795-disp-ufoe + - const: mediatek,mt8173-disp-ufoe Reviewed-by: Matthias Brugger reg: maxItems: 1
Re: [PATCH 12/27] dt-bindings: display: mediatek: split: Add compatible for MediaTek MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795's SPLIT block: this is the same as MT8173. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/display/mediatek/mediatek,split.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml index 35ace1f322e8..fa6dd9b649fe 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml @@ -23,6 +23,9 @@ properties: oneOf: - items: - const: mediatek,mt8173-disp-split + - items: + - const: mediatek,mt6795-disp-split + - const: mediatek,mt8173-disp-split Reviewed-by: Matthias Brugger reg: maxItems: 1
Re: [PATCH 11/27] dt-bindings: display: mediatek: merge: Add compatible for MediaTek MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795's MERGE block: this is the same as MT8173. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index 69ba75777dac..be330be1399a 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -25,6 +25,9 @@ properties: - const: mediatek,mt8173-disp-merge - items: - const: mediatek,mt8195-disp-merge + - items: + - const: mediatek,mt6795-disp-merge + - const: mediatek,mt8173-disp-merge Reviewed-by: Matthias Brugger reg: maxItems: 1
Re: [PATCH 09/27] dt-bindings: display: mediatek: color: Add compatible for MediaTek MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795's COLOR block: this is the same as MT8173. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index 62306c88f485..449b37c7560f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -35,6 +35,7 @@ properties: - const: mediatek,mt2701-disp-color - items: - enum: + - mediatek,mt6795-disp-color - mediatek,mt8183-disp-color - mediatek,mt8186-disp-color - mediatek,mt8188-disp-color
Re: [PATCH 08/27] dt-bindings: display: mediatek: wdma: Add compatible for MediaTek MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795's WDMA block: this is the same as MT8173. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/display/mediatek/mediatek,wdma.yaml| 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml index 7d7cc1ab526b..1a19b3ef036f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml @@ -23,6 +23,9 @@ properties: oneOf: - items: - const: mediatek,mt8173-disp-wdma + - items: + - const: mediatek,mt6795-disp-wdma + - const: mediatek,mt8173-disp-wdma :D Reviewed-by: Matthias Brugger reg: maxItems: 1
Re: [PATCH 05/27] dt-bindings: display: mediatek: dsi: Add compatible for MediaTek MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795, using the same DSI block as MT8173. Signed-off-by: AngeloGioacchino Del Regno --- .../display/mediatek/mediatek,dsi.yaml| 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml index 4707b60238b0..12441b937684 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -22,13 +22,18 @@ allOf: properties: compatible: -enum: - - mediatek,mt2701-dsi - - mediatek,mt7623-dsi - - mediatek,mt8167-dsi - - mediatek,mt8173-dsi - - mediatek,mt8183-dsi - - mediatek,mt8186-dsi +oneOf: + - enum: + - mediatek,mt2701-dsi + - mediatek,mt7623-dsi + - mediatek,mt8167-dsi + - mediatek,mt8173-dsi + - mediatek,mt8183-dsi + - mediatek,mt8186-dsi + - items: + - enum: + - mediatek,mt6795-dsi + - const: mediatek,mt8173-dsi Same here, why not const? reg: maxItems: 1
Re: [PATCH 04/27] dt-bindings: display: mediatek: aal: Add compatible for MediaTek MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795: similarly to MT8173, this SoC has the gamma LUT registers in DISP_AAL. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 92741486c24d..7fd42c8fdc32 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - mediatek,mt2712-disp-aal + - mediatek,mt6795-disp-aal - const: mediatek,mt8173-disp-aal - items: - enum:
Re: [PATCH 03/27] dt-bindings: display: mediatek: dpi: Add compatible for MediaTek MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for the MediaTek Helio X10 MT6795 SoC, using the same parameters as MT8183. Signed-off-by: AngeloGioacchino Del Regno --- .../display/mediatek/mediatek,dpi.yaml| 23 +++ 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index d976380801e3..803c00f26206 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -17,15 +17,20 @@ description: | properties: compatible: -enum: - - mediatek,mt2701-dpi - - mediatek,mt7623-dpi - - mediatek,mt8173-dpi - - mediatek,mt8183-dpi - - mediatek,mt8186-dpi - - mediatek,mt8188-dp-intf - - mediatek,mt8192-dpi - - mediatek,mt8195-dp-intf +oneOf: + - enum: + - mediatek,mt2701-dpi + - mediatek,mt7623-dpi + - mediatek,mt8173-dpi + - mediatek,mt8183-dpi + - mediatek,mt8186-dpi + - mediatek,mt8188-dp-intf + - mediatek,mt8192-dpi + - mediatek,mt8195-dp-intf + - items: + - enum: + - mediatek,mt6795-dpi + - const: mediatek,mt8183-dpi Shouldn't we declare both const: ?
Re: [PATCH 02/27] dt-bindings: phy: mediatek, dsi-phy: Add compatible for MT6795 Helio X10
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795: this SoC uses the same DSI PHY as MT8173. Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index 26f2b887cfc1..a9f78344efdb 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -24,6 +24,10 @@ properties: - enum: - mediatek,mt7623-mipi-tx - const: mediatek,mt2701-mipi-tx + - items: + - enum: + - mediatek,mt6795-mipi-tx + - const: mediatek,mt8173-mipi-tx I suppose you expect more SoCs to share the same fallback in the future, apart from keeping in sync with other comaptibles described here, so: Reviewed-by: Matthias Brugger - items: - enum: - mediatek,mt8365-mipi-tx
Re: [PATCH 01/27] dt-bindings: pwm: Add compatible for MediaTek MT6795
On 12/04/2023 13:27, AngeloGioacchino Del Regno wrote: Add a compatible string for MediaTek Helio X10 MT6795's display PWM block: this is the same as MT8173. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 0088bc8e7c54..153e146df7d4 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -22,7 +22,9 @@ properties: - mediatek,mt8173-disp-pwm - mediatek,mt8183-disp-pwm - items: - - const: mediatek,mt8167-disp-pwm + - enum: + - mediatek,mt6795-disp-pwm + - mediatek,mt8167-disp-pwm - const: mediatek,mt8173-disp-pwm - items: - enum:
Re: [PATCH -next 3/3] drm/mediatek: Use devm_platform_ioremap_resource()
On 12/04/2023 08:46, Yang Li wrote:
Remove variable 'res' and convert platform_get_resource(),
devm_ioremap_resource() to a single call to
devm_platform_ioremap_resource(), as this is exactly what this function
does.
Signed-off-by: Yang Li
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 1773379b2439..5cee84cce0be 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -159,7 +159,6 @@ static int mtk_disp_ccorr_probe(struct platform_device
*pdev)
{
struct device *dev = >dev;
struct mtk_disp_ccorr *priv;
- struct resource *res;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -172,8 +171,7 @@ static int mtk_disp_ccorr_probe(struct platform_device
*pdev)
return PTR_ERR(priv->clk);
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->regs = devm_ioremap_resource(dev, res);
+ priv->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->regs)) {
dev_err(dev, "failed to ioremap ccorr\n");
return PTR_ERR(priv->regs);
Re: [PATCH -next 2/3] drm/mediatek: Use devm_platform_ioremap_resource()
On 12/04/2023 08:46, Yang Li wrote:
Remove variable 'res' and convert platform_get_resource(),
devm_ioremap_resource() to a single call to
devm_platform_ioremap_resource(), as this is exactly what this function
does.
Signed-off-by: Yang Li
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_disp_aal.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
index 434e8a9ce8ab..391fa0ece22c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
@@ -104,7 +104,6 @@ static int mtk_disp_aal_probe(struct platform_device *pdev)
{
struct device *dev = >dev;
struct mtk_disp_aal *priv;
- struct resource *res;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -117,8 +116,7 @@ static int mtk_disp_aal_probe(struct platform_device *pdev)
return PTR_ERR(priv->clk);
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->regs = devm_ioremap_resource(dev, res);
+ priv->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->regs)) {
dev_err(dev, "failed to ioremap aal\n");
return PTR_ERR(priv->regs);
Re: [PATCH -next 1/3] drm/mediatek: Use devm_platform_ioremap_resource()
On 12/04/2023 08:46, Yang Li wrote:
Remove variable 'res' and convert platform_get_resource(),
devm_ioremap_resource() to a single call to
devm_platform_ioremap_resource(), as this is exactly what this function
does.
Signed-off-by: Yang Li
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_cec.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c
b/drivers/gpu/drm/mediatek/mtk_cec.c
index b640bc0559e7..03aae9f95606 100644
--- a/drivers/gpu/drm/mediatek/mtk_cec.c
+++ b/drivers/gpu/drm/mediatek/mtk_cec.c
@@ -185,7 +185,6 @@ static int mtk_cec_probe(struct platform_device *pdev)
{
struct device *dev = >dev;
struct mtk_cec *cec;
- struct resource *res;
int ret;
cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
@@ -195,8 +194,7 @@ static int mtk_cec_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, cec);
spin_lock_init(>lock);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- cec->regs = devm_ioremap_resource(dev, res);
+ cec->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(cec->regs)) {
ret = PTR_ERR(cec->regs);
dev_err(dev, "Failed to ioremap cec: %d\n", ret);
Re: [PATCH v3 1/9] drm/mediatek: dp: Cache EDID for eDP panel
On 12/04/2023 10:06, AngeloGioacchino Del Regno wrote:
Il 12/04/23 09:08, Matthias Brugger ha scritto:
On 04/04/2023 12:47, AngeloGioacchino Del Regno wrote:
Since eDP panels are not removable it is safe to cache the EDID:
this will avoid a relatively long read transaction at every PM
resume that is unnecessary only in the "special" case of eDP,
hence speeding it up a little, as from now on, as resume operation,
we will perform only link training.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dp.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c
b/drivers/gpu/drm/mediatek/mtk_dp.c
index 1f94fcc144d3..84f82cc68672 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -118,6 +118,7 @@ struct mtk_dp {
const struct mtk_dp_data *data;
struct mtk_dp_info info;
struct mtk_dp_train_info train_info;
+ struct edid *edid;
struct platform_device *phy_dev;
struct phy *phy;
@@ -1993,7 +1994,11 @@ static struct edid *mtk_dp_get_edid(struct drm_bridge
*bridge,
usleep_range(2000, 5000);
}
- new_edid = drm_get_edid(connector, _dp->aux.ddc);
+ /* eDP panels aren't removable, so we can return a cached EDID. */
+ if (mtk_dp->edid && mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP)
Maybe better like this:
if (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP && mtk_dp->edid)
To in sync with the if statement below. Anyway we are only concerned if it's an
eDP so check that first (and hope the compiler will do so as well ;)
With that:
Reviewed-by: Matthias Brugger
+ new_edid = drm_edid_duplicate(mtk_dp->edid);
+ else
+ new_edid = drm_get_edid(connector, _dp->aux.ddc);
Maybe it would make sense to add a macro for the check of mtk_dp->bridge.type
== DRM_MODE_CONNECTOR_eDP
it would make the code more readable.
I had the same idea... but then avoided that because in most (if not all?) of
the
DRM drivers (at least, the one I've read) this check is always open coded, so I
wrote it like that for consistency and nothing else.
I have no strong opinions on that though!
I think the only reasonable solution would be a macro like:
DRM_CONNECTOR_MODE_IS(mtk_dp->bridge.type, eDP) which in the end is longer then
open-code it, so probably just leave it as it is.
/*
* Parse capability here to let atomic_get_input_bus_fmts and
@@ -2022,6 +2027,10 @@ static struct edid *mtk_dp_get_edid(struct drm_bridge
*bridge,
drm_atomic_bridge_chain_post_disable(bridge, connector->state->state);
}
+ /* If this is an eDP panel and the read EDID is good, cache it for later */
+ if (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP && !mtk_dp->edid &&
new_edid)
+ mtk_dp->edid = drm_edid_duplicate(new_edid);
+
How about putting this in an else if branch of mtk_dp_parse_capabilities. At
least we could get rid of the check regarding if new_edid != NULL.
I was thinking on how to put both if statements in one block, but I think the
problem is, that we would leak memory if the capability parsing failes due to
the call to drm_edid_duplicate(). Correct?
Correct. The only other "good" place would be in the `if (new_edid)`
conditional,
but that wouldn't be as readable as it is right now...
Cheers,
Angelo
Re: [PATCH v3 1/9] drm/mediatek: dp: Cache EDID for eDP panel
On 04/04/2023 12:47, AngeloGioacchino Del Regno wrote:
Since eDP panels are not removable it is safe to cache the EDID:
this will avoid a relatively long read transaction at every PM
resume that is unnecessary only in the "special" case of eDP,
hence speeding it up a little, as from now on, as resume operation,
we will perform only link training.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_dp.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c
b/drivers/gpu/drm/mediatek/mtk_dp.c
index 1f94fcc144d3..84f82cc68672 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -118,6 +118,7 @@ struct mtk_dp {
const struct mtk_dp_data *data;
struct mtk_dp_info info;
struct mtk_dp_train_info train_info;
+ struct edid *edid;
struct platform_device *phy_dev;
struct phy *phy;
@@ -1993,7 +1994,11 @@ static struct edid *mtk_dp_get_edid(struct drm_bridge
*bridge,
usleep_range(2000, 5000);
}
- new_edid = drm_get_edid(connector, _dp->aux.ddc);
+ /* eDP panels aren't removable, so we can return a cached EDID. */
+ if (mtk_dp->edid && mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP)
+ new_edid = drm_edid_duplicate(mtk_dp->edid);
+ else
+ new_edid = drm_get_edid(connector, _dp->aux.ddc);
Maybe it would make sense to add a macro for the check of mtk_dp->bridge.type ==
DRM_MODE_CONNECTOR_eDP
it would make the code more readable.
/*
* Parse capability here to let atomic_get_input_bus_fmts and
@@ -2022,6 +2027,10 @@ static struct edid *mtk_dp_get_edid(struct drm_bridge
*bridge,
drm_atomic_bridge_chain_post_disable(bridge,
connector->state->state);
}
+ /* If this is an eDP panel and the read EDID is good, cache it for later */
+ if (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP && !mtk_dp->edid &&
new_edid)
+ mtk_dp->edid = drm_edid_duplicate(new_edid);
+
How about putting this in an else if branch of mtk_dp_parse_capabilities. At
least we could get rid of the check regarding if new_edid != NULL.
I was thinking on how to put both if statements in one block, but I think the
problem is, that we would leak memory if the capability parsing failes due to
the call to drm_edid_duplicate(). Correct?
Regards,
Matthais
return new_edid;
}./
Re: [PATCH 15/21] dt-bindings: soc: mediatek: add display mutex for MT8365 SoC
On 09/03/2023 15:23, Alexandre Mergnat wrote: Add compatible for the MT8365 SoC. Signed-off-by: Alexandre Mergnat Applied, thanks! --- Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index ca0ca549257d..931d66893dff 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt8186-mdp3-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex + - mediatek,mt8365-disp-mutex reg: maxItems: 1
Re: [PATCH 01/21] dt-bindings: display: mediatek: aal: add binding for MT8365 SoC
Hi Chun-Kuang Hu, On 13/03/2023 16:02, Chun-Kuang Hu wrote: Hi, Alexandre: Alexandre Mergnat 於 2023年3月9日 週四 下午10:23寫道： Display Adaptive Ambient Light for MT8365 is compatible with another SoC. Then, add MT8365 binding along with MT8183 SoC. Reviewed-by: Chun-Kuang Hu I'm a bit puzzled that you give your reviewed by while I would have expected that you will take the display binding patches. Will you take these or do you want someone else to take them? Regards, Matthias Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index d4d585485e7b..d47bc72f09c0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt8186-disp-aal - mediatek,mt8192-disp-aal - mediatek,mt8195-disp-aal + - mediatek,mt8365-disp-aal - const: mediatek,mt8183-disp-aal reg: -- b4 0.10.1
Re: [PATCH 14/21] dt-bindings: soc: mediatek: specify which compatible requires clocks property
On 09/03/2023 15:23, Alexandre Mergnat wrote: According to the mtk-mutex.c driver and the SoC DTS, the clock isn't required to work properly for some of MTK SoC. Improve the clock requirement by adding a condition which is function to the compatible. Signed-off-by: Alexandre Mergnat Applied, thanks. Now I think we can get rid of the no_clk variable in struct mtk_mutex_data, as this should be mandated by the device-tree. Regards, Matthias --- .../bindings/soc/mediatek/mediatek,mutex.yaml| 20 +++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 9241e5fc7cff..ca0ca549257d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -69,12 +69,30 @@ properties: 4 arguments defined in this property. Each GCE subsys id is mapping to a client defined in the header include/dt-bindings/gce/-gce.h. +allOf: + - if: + properties: +compatible: + contains: +enum: + - mediatek,mt2701-disp-mutex + - mediatek,mt2712-disp-mutex + - mediatek,mt6795-disp-mutex + - mediatek,mt8173-disp-mutex + - mediatek,mt8186-disp-mutex + - mediatek,mt8186-mdp3-mutex + - mediatek,mt8192-disp-mutex + - mediatek,mt8195-disp-mutex +then: + required: +- clocks + + required: - compatible - reg - interrupts - power-domains - - clocks additionalProperties: false
Re: [PATCH v2] dt-bindings: display: mediatek: Fix the duplicated fallback
On 06/03/2023 17:15, Alexandre Mergnat wrote:
The item which have the mediatek,mt8192-disp-ccorr const compatible already
exist above. Remove duplicated fallback.
Fixes: 137272ef1b0f ("dt-bindings: display: mediatek: Fix the fallback for
mediatek,mt8186-disp-ccorr")
We can argue if dt-binding patches should have a fixes tag at all. Given the
fact that there are so many warnings still around, I don't see any value add to
backport these to stable kernel.
That said, this is defenitely no fix, as it's only a code clean-up. No warning,
no bug, no functional error fixed here :)
Signed-off-by: Alexandre Mergnat
---
Fix MTK color correction binding
The fallback compatible has been duplicated in the 137272ef1b0f commit.
To: Chun-Kuang Hu
To: Philipp Zabel
To: David Airlie
To: Daniel Vetter
To: Rob Herring
To: Krzysztof Kozlowski
To: Matthias Brugger
To: AngeloGioacchino Del Regno
To: Allen-KH Cheng
Cc: Rob Herring
Cc: dri-devel@lists.freedesktop.org
Cc: linux-media...@lists.infradead.org
Cc: devicet...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
---
Changes in v2:
- Fix commit title.
- Link to v1:
https://lore.kernel.org/r/20230306-ccorr-binding-fix-v1-0-177d81d60...@baylibre.com
---
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 3 ---
1 file changed, 3 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index b04820c95b22..3aaf44719786 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -29,9 +29,6 @@ properties:
- enum:
- mediatek,mt8188-disp-ccorr
- mediatek,mt8195-disp-ccorr
- - const: mediatek,mt8192-disp-ccorr
- - items:
- - enum:
- mediatek,mt8186-disp-ccorr
Please sort compatibles, that will allow for easier reading once we add more to
the file.
Regards,
Matthias
- const: mediatek,mt8192-disp-ccorr
---
base-commit: add072536971d7ce891fde3cdbf68c55e7cfa95a
change-id: 20230306-ccorr-binding-fix-718c6d725088
Best regards,
Re: [PATCH 1/3] drm/mediatek: Refactor pixel format logic
On 02/02/2023 21:41, Justin Green wrote: Yes, I had a comment on the naming in that patch. Never the less, I think if we don't need to "overwrite" the value, we should use just one struct for the values instead of copying them to the different .c files and give them SoC specific names. I don't have a very strong opinion about this, and in fact that is how v1 of the patch worked, but Chun-Kuang specifically suggested moving that struct into the .c files a few versions back. I think it makes sense if we expect additional skew between the different components and what pixel formats they support. Ok, if Chun-Kuang asked to do it this way, then I won't object. In the end he is the maintainer of the driver. Regards, Matthias
Re: [PATCH 1/3] drm/mediatek: Refactor pixel format logic
On 02/02/2023 19:59, Justin Green wrote: Hi Matthias, mt8173_formats are the same as the old struct formats. Maybe we should use that and only overwrite where we actually use a different array. I think this was sort of how the original patch worked, but we wanted to add some flexibility to allow different components to support different formats. In patch 3 of the series, we actually overwrite this field with mt8195_formats. Yes, I had a comment on the naming in that patch. Never the less, I think if we don't need to "overwrite" the value, we should use just one struct for the values instead of copying them to the different .c files and give them SoC specific names. Why can't we use ARRAY_SIZE(formats) here like we did before? I think ARRAY_SIZE is just a macro for getting the length of statically allocated arrays. Because we won't know until runtime which list of pixel formats we will be using, I'm not sure we can use that in this circumstance? You are probably right. Regards, Matthias
Re: [PATCH 3/3] drm/mediatek: Enable AR30 and BA30 overlays on MT8195
On 01/02/2023 18:02, Justin Green wrote:
Tested using "modetest -P" on an MT8195 device.
Signed-off-by: Justin Green
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index a6255e847104..7d26f7055751 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -85,6 +85,22 @@ static const u32 mt8173_formats[] = {
DRM_FORMAT_YUYV,
};
+static const u32 mt8195_formats[] = {
I'd call it mt8195_ovl_formats, to make it explicit that it's only for the OVL.
Regards,
Matthias
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_BGRX,
+ DRM_FORMAT_BGRA,
+ DRM_FORMAT_BGRA1010102,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+};
+
struct mtk_disp_ovl_data {
unsigned int addr;
unsigned int gmc_bits;
@@ -616,8 +632,9 @@ static const struct mtk_disp_ovl_data
mt8195_ovl_driver_data = {
.fmt_rgb565_is_0 = true,
.smi_id_en = true,
.supports_afbc = true,
- .formats = mt8173_formats,
- .num_formats = ARRAY_SIZE(mt8173_formats),
+ .formats = mt8195_formats,
+ .num_formats = ARRAY_SIZE(mt8195_formats),
+ .supports_clrfmt_ext = true,
};
static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
Re: [PATCH 1/3] drm/mediatek: Refactor pixel format logic
On 01/02/2023 18:02, Justin Green wrote:
Add an DDP component interface for querying pixel format support and move list
of supported pixel formats into DDP components instead of mtk_drm_plane.c
Tested by running Chrome on an MT8195.
Signed-off-by: Justin Green
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 ++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 44 +
drivers/gpu/drm/mediatek/mtk_disp_rdma.c| 38 ++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 20 ++
drivers/gpu/drm/mediatek/mtk_drm_plane.c| 24 ---
drivers/gpu/drm/mediatek/mtk_drm_plane.h| 3 +-
8 files changed, 123 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 33e61a136bbc..0df6a06defb8 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -96,6 +96,8 @@ void mtk_ovl_register_vblank_cb(struct device *dev,
void mtk_ovl_unregister_vblank_cb(struct device *dev);
void mtk_ovl_enable_vblank(struct device *dev);
void mtk_ovl_disable_vblank(struct device *dev);
+const u32 *mtk_ovl_get_formats(struct device *dev);
+size_t mtk_ovl_get_num_formats(struct device *dev);
void mtk_rdma_bypass_shadow(struct device *dev);
int mtk_rdma_clk_enable(struct device *dev);
@@ -115,6 +117,8 @@ void mtk_rdma_register_vblank_cb(struct device *dev,
void mtk_rdma_unregister_vblank_cb(struct device *dev);
void mtk_rdma_enable_vblank(struct device *dev);
void mtk_rdma_disable_vblank(struct device *dev);
+const u32 *mtk_rdma_get_formats(struct device *dev);
+size_t mtk_rdma_get_num_formats(struct device *dev);
int mtk_mdp_rdma_clk_enable(struct device *dev);
void mtk_mdp_rdma_clk_disable(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 84daeaffab6a..8743c8047dc9 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -66,6 +66,20 @@
#define OVL_CON_VIRT_FLIP BIT(9)
#define OVL_CON_HORZ_FLIP BIT(10)
+static const u32 mt8173_formats[] = {
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_BGRX,
+ DRM_FORMAT_BGRA,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+};
+
struct mtk_disp_ovl_data {
unsigned int addr;
unsigned int gmc_bits;
@@ -73,6 +87,8 @@ struct mtk_disp_ovl_data {
bool fmt_rgb565_is_0;
bool smi_id_en;
bool supports_afbc;
+ const u32 *formats;
+ size_t num_formats;
};
/*
@@ -138,6 +154,20 @@ void mtk_ovl_disable_vblank(struct device *dev)
writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
}
+const u32 *mtk_ovl_get_formats(struct device *dev)
+{
+ struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+
+ return ovl->data->formats;
+}
+
+size_t mtk_ovl_get_num_formats(struct device *dev)
+{
+ struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+
+ return ovl->data->num_formats;
+}
+
int mtk_ovl_clk_enable(struct device *dev)
{
struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
@@ -495,6 +525,8 @@ static const struct mtk_disp_ovl_data
mt2701_ovl_driver_data = {
.gmc_bits = 8,
.layer_nr = 4,
.fmt_rgb565_is_0 = false,
+ .formats = mt8173_formats,
+ .num_formats = ARRAY_SIZE(mt8173_formats),
};
static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
@@ -502,6 +534,8 @@ static const struct mtk_disp_ovl_data
mt8173_ovl_driver_data = {
.gmc_bits = 8,
.layer_nr = 4,
.fmt_rgb565_is_0 = true,
+ .formats = mt8173_formats,
+ .num_formats = ARRAY_SIZE(mt8173_formats),
mt8173_formats are the same as the old struct formats. Maybe we should use that
and only overwrite where we actually use a different array.
Regarding num_formats, see my comment below.
};
static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
@@ -509,6 +543,8 @@ static const struct mtk_disp_ovl_data
mt8183_ovl_driver_data = {
.gmc_bits = 10,
.layer_nr = 4,
.fmt_rgb565_is_0 = true,
+ .formats = mt8173_formats,
+ .num_formats = ARRAY_SIZE(mt8173_formats),
};
static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
@@ -516,6 +552,8 @@ static const struct mtk_disp_ovl_data
mt8183_ovl_2l_driver_data = {
.gmc_bits = 10,
.layer_nr = 2,
.fmt_rgb565_is_0 = true,
+ .formats = mt8173_formats,
+ .num_formats = ARRAY_SIZE(mt8173_formats),
};
static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
@@ -524,6 +562,8 @@ static
Re: [PATCH v2] drm/mediatek: dp: Only trigger DRM HPD events if bridge is attached
On 02/02/2023 05:57, Chen-Yu Tsai wrote:
The MediaTek DisplayPort interface bridge driver starts its interrupts
as soon as its probed. However when the interrupts trigger the bridge
might not have been attached to a DRM device. As drm_helper_hpd_irq_event()
does not check whether the passed in drm_device is valid or not, a NULL
pointer passed in results in a kernel NULL pointer dereference in it.
Check whether the bridge is attached and only trigger an HPD event if
it is.
Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver")
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Guillaume Ranquet
Reviewed-by: Matthias Brugger
---
Changes since v1
- Dropped prerequisite-patch-ids
- Added Guillaume's Reviewed-by
This applies on top of mediatek-drm-next.
drivers/gpu/drm/mediatek/mtk_dp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c
b/drivers/gpu/drm/mediatek/mtk_dp.c
index 1f94fcc144d3..a82f53e1a146 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -1823,7 +1823,8 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void
*dev)
spin_unlock_irqrestore(_dp->irq_thread_lock, flags);
if (status & MTK_DP_THREAD_CABLE_STATE_CHG) {
- drm_helper_hpd_irq_event(mtk_dp->bridge.dev);
+ if (mtk_dp->bridge.dev)
+ drm_helper_hpd_irq_event(mtk_dp->bridge.dev);
if (!mtk_dp->train_info.cable_plugged_in) {
mtk_dp_disable_sdp_aui(mtk_dp);
Re: [PATCH v2 7/9] arm64: dts: mediatek: mt8186: Add DPI node
On 18/01/2023 10:18, Allen-KH Cheng wrote:
Add DPI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
Tested-by: Chen-Yu Tsai
Applied, thanks!
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index c52f9be1e750..45b9d6777929 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1230,6 +1230,23 @@
power-domains = < MT8186_POWER_DOMAIN_DIS>;
};
+ dpi: dpi@1400a000 {
+ compatible = "mediatek,mt8186-dpi";
+ reg = <0 0x1400a000 0 0x1000>;
+ clocks = < CLK_TOP_DPI>,
+< CLK_MM_DISP_DPI>,
+< CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ assigned-clocks = < CLK_TOP_DPI>;
+ assigned-clock-parents = < CLK_TOP_TVDPLL_D2>;
+ interrupts = ;
+ status = "disabled";
+
+ port {
+ dpi_out: endpoint { };
+ };
+ };
+
dsi0: dsi@14013000 {
compatible = "mediatek,mt8186-dsi";
reg = <0 0x14013000 0 0x1000>;
Re: [PATCH v2 6/9] arm64: dts: mediatek: mt8186: Add audio controller node
On 18/01/2023 10:18, Allen-KH Cheng wrote:
Add audio controller node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
Applied, thanks!
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 62
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 2700c830316f..c52f9be1e750 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -998,6 +998,68 @@
};
};
+ afe: audio-controller@1121 {
+ compatible = "mediatek,mt8186-sound";
+ reg = <0 0x1121 0 0x2000>;
+ clocks = <_ao CLK_INFRA_AO_AUDIO>,
+<_ao CLK_INFRA_AO_AUDIO_26M_BCLK>,
+< CLK_TOP_AUDIO>,
+< CLK_TOP_AUD_INTBUS>,
+< CLK_TOP_MAINPLL_D2_D4>,
+< CLK_TOP_AUD_1>,
+< CLK_APMIXED_APLL1>,
+< CLK_TOP_AUD_2>,
+< CLK_APMIXED_APLL2>,
+< CLK_TOP_AUD_ENGEN1>,
+< CLK_TOP_APLL1_D8>,
+< CLK_TOP_AUD_ENGEN2>,
+< CLK_TOP_APLL2_D8>,
+< CLK_TOP_APLL_I2S0_MCK_SEL>,
+< CLK_TOP_APLL_I2S1_MCK_SEL>,
+< CLK_TOP_APLL_I2S2_MCK_SEL>,
+< CLK_TOP_APLL_I2S4_MCK_SEL>,
+< CLK_TOP_APLL_TDMOUT_MCK_SEL>,
+< CLK_TOP_APLL12_CK_DIV0>,
+< CLK_TOP_APLL12_CK_DIV1>,
+< CLK_TOP_APLL12_CK_DIV2>,
+< CLK_TOP_APLL12_CK_DIV4>,
+< CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
+< CLK_TOP_AUDIO_H>,
+<>;
+ clock-names = "aud_infra_clk",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d2_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d8",
+ "top_mux_aud_eng2",
+ "top_apll2_d8",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s4_m_sel",
+ "top_tdm_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div4",
+ "top_apll12_div_tdm",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ interrupts = ;
+ mediatek,apmixedsys = <>;
+ mediatek,infracfg = <_ao>;
+ mediatek,topckgen = <>;
+ resets = < MT8186_TOPRGU_AUDIO_SW_RST>;
+ reset-names = "audiosys";
+ status = "disabled";
+ };
+
mmc0: mmc@1123 {
compatible = "mediatek,mt8186-mmc",
"mediatek,mt8183-mmc";
Re: [PATCH v2 4/9] arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes
On 18/01/2023 10:18, Allen-KH Cheng wrote:
Add ADSP mailbox node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng
Applied, thanks!
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index a8ff984f1192..a0b7dacc10cd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -640,6 +640,20 @@
interrupts = ;
};
+ adsp_mailbox0: mailbox@10686000 {
+ compatible = "mediatek,mt8186-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10686100 0 0x1000>;
+ interrupts = ;
+ };
+
+ adsp_mailbox1: mailbox@10687000 {
+ compatible = "mediatek,mt8186-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10687100 0 0x1000>;
+ interrupts = ;
+ };
+
nor_flash: spi@1100 {
compatible = "mediatek,mt8186-nor";
reg = <0 0x1100 0 0x1000>;
Re: [PATCH v2 8/9] dt-bindings: display: mediatek: Fix the fallback for mediatek,mt8186-disp-ccorr
On 18/01/2023 10:18, Allen-KH Cheng wrote:
The mt8186-disp-ccorr is not fully compatible with the mt8183-disp-ccorr
implementation. It causes a crash when system resumes if it binds to the
device.
We should use mt8192-disp-ccorr as fallback of mt8186-disp-ccorr.
Fixes: 8a26ea19d4dc ("dt-bindings: display: mediatek: add MT8186 SoC binding")
Signed-off-by: Allen-KH Cheng
Reviewed-by: Rob Herring
Reviewed-by: Matthias Brugger
---
.../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index 63fb02014a56..117e3db43f84 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -32,7 +32,7 @@ properties:
- items:
- enum:
- mediatek,mt8186-disp-ccorr
- - const: mediatek,mt8183-disp-ccorr
+ - const: mediatek,mt8192-disp-ccorr
reg:
maxItems: 1
Re: [PATCH v2 2/9] dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi
On 18/01/2023 10:18, Allen-KH Cheng wrote: The mt8186-spmi is used as compatible with mt8195-spmi on the MT8186, document this situation. Signed-off-by: Allen-KH Cheng Reviewed-by: Rob Herring Reviewed-by: Matthias Brugger --- .../devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml index abcbbe13723f..e4f465abcfe9 100644 --- a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml +++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -18,9 +18,14 @@ allOf: properties: compatible: -enum: - - mediatek,mt6873-spmi - - mediatek,mt8195-spmi +oneOf: + - enum: + - mediatek,mt6873-spmi + - mediatek,mt8195-spmi + - items: + - enum: + - mediatek,mt8186-spmi + - const: mediatek,mt8195-spmi reg: maxItems: 2
Re: [PATCH v4 0/6] Add first version mt8188 vdosys0 driver
Applied patches 2,3,4,5 The rest will go through the DRM driver tree. Thanks! On 06/12/2022 03:00, nathan.lu wrote: From: Nathan Lu This patch is to add first version mt8188 vdosys0 driver Modify and add new files include: 1. bindings documents 2. mtk mmsys 3. mtk mutex 4. mtk drm driver Change in V4: - based on [1] [1] Change mmsys compatible for mt8195 mediatek-drm - https://patchwork.kernel.org/project/linux-mediatek/list/?series=699386 - Modify mediatek,mmsys.yaml, move mt8188-vdosys0 to mmsys - Modify mt8188_mmsysy.h DSI mux setting Change in V3: - based on [1] [1] Change mmsys compatible for mt8195 mediatek-drm - https://patchwork.kernel.org/project/linux-mediatek/list/?series=699386 - Modify mediatek,mmsys.yaml mt8188-mmsys name to mt8188-vdosys0 - Modify mtk-mmsys.c compatible name to mt8188-vdosys0 - Add DSI mutex in mtk-mutex.c - Modify mtk_drm_drv.c mt8188-mmsysy name to mt8188-vdosys0 Change in V2: - based on [2] and [3] [2] Add MediaTek SoC(vdosys1) support for mt8195 - https://patchwork.kernel.org/project/linux-mediatek/list/?series=658416 [3] Add MediaTek SoC DRM (vdosys1) support for mt8195 - https://patchwork.kernel.org/project/linux-mediatek/list/?series=665269 - Seperate bindings doucment into mmsys/mutex/display 3 parts - Remove redundent char in mediatek,gamma.yaml - Add another mediatek,mt8188-disp-rdma in mediatek,rdma.yaml - Remove io_start variable setting in mtk_drm_drv.c and mtk_mmsys.c Nathan Lu (6): dt-bindings: mediatek: modify VDOSYS0 display device tree Documentations for MT8188 dt-bindings: mediatek: modify VDOSYS0 mmsys device tree Documentations for MT8188 dt-bindings: mediatek: modify VDOSYS0 mutex device tree Documentations for MT8188 soc: mediatek: add mtk-mmsys support for mt8188 vdosys0 soc: mediatek: add mtk-mutex support for mt8188 vdosys0 drm/mediatek: add mediatek-drm of vdosys0 support for mt8188 .../bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + .../display/mediatek/mediatek,aal.yaml| 1 + .../display/mediatek/mediatek,ccorr.yaml | 1 + .../display/mediatek/mediatek,color.yaml | 1 + .../display/mediatek/mediatek,dither.yaml | 1 + .../display/mediatek/mediatek,gamma.yaml | 1 + .../display/mediatek/mediatek,ovl.yaml| 1 + .../display/mediatek/mediatek,postmask.yaml | 1 + .../display/mediatek/mediatek,rdma.yaml | 4 + .../bindings/soc/mediatek/mediatek,mutex.yaml | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c| 21 +++ drivers/soc/mediatek/mt8188-mmsys.h | 149 ++ drivers/soc/mediatek/mtk-mmsys.c | 11 ++ drivers/soc/mediatek/mtk-mutex.c | 53 +++ 14 files changed, 247 insertions(+) create mode 100644 drivers/soc/mediatek/mt8188-mmsys.h
Re: [PATCH v4 6/6] drm/mediatek: add mediatek-drm of vdosys0 support for mt8188
On 06/12/2022 03:00, nathan.lu wrote:
From: Nathan Lu
add driver data of mt8188 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: amy zhang
Signed-off-by: Nathan Lu
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b12e5b977c50..8058a5ec2f1d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -176,6 +176,18 @@ static const enum mtk_ddp_comp_id mt8186_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8188_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_POSTMASK0,
+ DDP_COMPONENT_DITHER0,
+ DDP_COMPONENT_DP_INTF0,
+};
+
static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
@@ -259,6 +271,11 @@ static const struct mtk_mmsys_driver_data
mt8186_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
+ .main_path = mt8188_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.main_path = mt8192_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -516,6 +533,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8186-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8188-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8195-disp-mutex",
@@ -600,6 +619,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = _mmsys_driver_data},
{ .compatible = "mediatek,mt8186-mmsys",
.data = _mmsys_driver_data},
+ { .compatible = "mediatek,mt8188-vdosys0",
+ .data = _vdosys0_driver_data},
{ .compatible = "mediatek,mt8192-mmsys",
.data = _mmsys_driver_data},
{ .compatible = "mediatek,mt8195-mmsys",
Re: [PATCH v4 1/6] dt-bindings: mediatek: modify VDOSYS0 display device tree Documentations for MT8188
On 06/12/2022 03:00, nathan.lu wrote: From: Nathan Lu modify VDOSYS0 display device tree Documentations for MT8188. Signed-off-by: Nathan Lu Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- .../devicetree/bindings/display/mediatek/mediatek,aal.yaml| 1 + .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml| 1 + .../bindings/display/mediatek/mediatek,postmask.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 4 8 files changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index d4d585485e7b..92741486c24d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -31,6 +31,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-aal + - mediatek,mt8188-disp-aal - mediatek,mt8192-disp-aal - mediatek,mt8195-disp-aal - const: mediatek,mt8183-disp-aal diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index 63fb02014a56..fe444beff558 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -27,6 +27,7 @@ properties: - const: mediatek,mt8192-disp-ccorr - items: - enum: + - mediatek,mt8188-disp-ccorr - mediatek,mt8195-disp-ccorr - const: mediatek,mt8192-disp-ccorr - items: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index d2f89ee7996f..62306c88f485 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -37,6 +37,7 @@ properties: - enum: - mediatek,mt8183-disp-color - mediatek,mt8186-disp-color + - mediatek,mt8188-disp-color - mediatek,mt8192-disp-color - mediatek,mt8195-disp-color - const: mediatek,mt8173-disp-color diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 8ad8187c02d1..5c7445c174e5 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-dither + - mediatek,mt8188-disp-dither - mediatek,mt8192-disp-dither - mediatek,mt8195-disp-dither - const: mediatek,mt8183-disp-dither diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index a89ea0ea7542..a5c6a91fac71 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -28,6 +28,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-gamma + - mediatek,mt8188-disp-gamma - mediatek,mt8192-disp-gamma - mediatek,mt8195-disp-gamma - const: mediatek,mt8183-disp-gamma diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index a2a27d0ca038..065e526f950e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -36,6 +36,7 @@ properties: - const: mediatek,mt2701-disp-ovl - items: - enum: + - mediatek,mt8188-disp-ovl - mediatek,mt8195-disp-ovl - const: mediatek,mt8183-disp-ovl - items: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml index 654080bfbdfb..27de64495401 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml +++ b
Re: [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
On 22/11/2022 11:51, Nancy Lin (林欣螢) wrote: Dear Matthias, Thanks for the review. On Thu, 2022-11-10 at 14:10 +0100, Matthias Brugger wrote: On 09/11/2022 06:10, Jason-JH Lin (林睿祥) wrote: > On Tue, 2022-11-08 at 18:46 +0100, Matthias Brugger wrote: > > > > On 07/11/2022 08:22, Nancy.Lin wrote: > > > Add vdosys1 mmsys compatible for MT8195 platform. > > > > > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines > > > binding > > > to > > > 2 different power domains, different clock drivers and > > > different > > > mediatek-drm drivers. > > > > > > Signed-off-by: Nancy.Lin > > > Reviewed-by: Nícolas F. R. A. Prado > > > --- > > > > > > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | > > > 4 > > > +++- > > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > > > diff --git > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys > > > .yam > > > l > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys > > > .yam > > > l > > > index 0711f1834fbd..aaabe2196185 100644 > > > --- > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys > > > .yam > > > l > > > +++ > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys > > > .yam > > > l > > > @@ -48,7 +48,9 @@ properties: > > > - const: syscon > > > > > > - items: > > > - - const: mediatek,mt8195-vdosys0 > > > + - enum: > > > + - mediatek,mt8195-vdosys0 > > > + - mediatek,mt8195-vdosys1 > > > - const: mediatek,mt8195-mmsys > > > - const: syscon > > > > > > > I think we had that several times already: > > > > https://lore.kernel.org/all/6bbe9527-ae48-30e0-fb45-519223a74...@linaro.org/ > > > > We will something like this, but please check that this does not > > give > > any > > errors/warnings: > > > > diff --git > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y > > aml > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y > > aml > > index eb451bec23d3d..8e9c4f4d7c389 100644 > > --- > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y > > aml > > +++ > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.y > > aml > > @@ -32,13 +32,22 @@ properties: > > - mediatek,mt8183-mmsys > > - mediatek,mt8186-mmsys > > - mediatek,mt8192-mmsys > > - - mediatek,mt8195-mmsys > > - mediatek,mt8365-mmsys > > - const: syscon > > - items: > > - const: mediatek,mt7623-mmsys > > - const: mediatek,mt2701-mmsys > > - const: syscon > > + - items: > > + - const: mediatek,mt8195-vdosys0 > > + - const: syscon > > + - items: > > + - const: mediatek,mt8195-vdosys1 > > + - const: syscon > > + - items: > > + - const: mediatek,mt8195-mmsys > > + - const: syscon > > + deprecated: true > > > > reg: > > maxItems: 1 > > Hi Matthias, > > As the vdosys0 previous reviewed patch: > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220927152704.12018-2-jason-jh@mediatek.com/__;!!CTRNKA9wMg0ARbw!zRdbIyyAsfqob2kapMAcKYATAguhEV0x0qE5cTOAcWUNhzeAbMHzZoos_2QzUCxS$ > > Should I modify the vdosys0 items format like your example? > > Or should vdosys1 add items format like vdosys0's previous patch? > - items: > - const: mediatek,mt8195-vdosys1 > - const: mediatek,mt8195-mmsys > - const: syscon > No, vdosys1 must not have mediatek,mt8195-mmsys fallback. Regards, Matthias I will fix it and add the following vdosys1 binding base on [1]. - description: vdosys0 and vdosys1 are 2 display HW pipelines, so mt8195 binding should be deprecated. deprecated: true items: - const: mediatek,mt8195-mmsys - const: syscon - items: - const: mediatek,mt7623-mmsys - const: mediatek,mt2701-mmsys - const: syscon - items: - const: mediatek,mt8195-vdosys0 - const: mediatek,mt819
Re: [PATCH v13,2/3] drm: mediatek: Set dpi format in mmsys
On 24/10/2022 04:04, xinlei@mediatek.com wrote:
From: Xinlei Lee
Dpi output needs to adjust the output format to dual edge for MT8186.
Co-developed-by: Jitao Shi
Signed-off-by: Jitao Shi
Signed-off-by: Xinlei Lee
Reviewed-by: CK Hu
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Nícolas F. R. A. Prado
I realized that I took this patch by error. I'll drop it from my tree now.
Regards,
Matthias
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 630a4e301ef6..ad87ecddf58d 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
@@ -30,6 +31,7 @@
#include "mtk_disp_drv.h"
#include "mtk_dpi_regs.h"
#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
enum mtk_dpi_out_bit_num {
MTK_DPI_OUT_BIT_NUM_8BITS,
@@ -67,6 +69,7 @@ struct mtk_dpi {
struct drm_connector *connector;
void __iomem *regs;
struct device *dev;
+ struct device *mmsys_dev;
struct clk *engine_clk;
struct clk *pixel_clk;
struct clk *tvd_clk;
@@ -135,6 +138,7 @@ struct mtk_dpi_yc_limit {
* @yuv422_en_bit: Enable bit of yuv422.
* @csc_enable_bit: Enable bit of CSC.
* @pixels_per_iter: Quantity of transferred pixels per iteration.
+ * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be
set in MMSYS.
*/
struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
@@ -153,6 +157,7 @@ struct mtk_dpi_conf {
u32 yuv422_en_bit;
u32 csc_enable_bit;
u32 pixels_per_iter;
+ bool edge_cfg_in_mmsys;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -449,8 +454,12 @@ static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ?
EDGE_SEL : 0, EDGE_SEL);
+ if (dpi->conf->edge_cfg_in_mmsys)
+ mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev,
MTK_DPI_RGB888_DDR_CON);
} else {
mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0);
+ if (dpi->conf->edge_cfg_in_mmsys)
+ mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev,
MTK_DPI_RGB888_SDR_CON);
}
}
@@ -778,8 +787,10 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
{
struct mtk_dpi *dpi = dev_get_drvdata(dev);
struct drm_device *drm_dev = data;
+ struct mtk_drm_private *priv = drm_dev->dev_private;
int ret;
+ dpi->mmsys_dev = priv->mmsys_dev;
ret = drm_simple_encoder_init(drm_dev, >encoder,
DRM_MODE_ENCODER_TMDS);
if (ret) {
Re: [PATCH v5 5/6] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
On 27/09/2022 17:27, Jason-JH.Lin wrote:
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 2cb90466798c..66cdd0bc1311 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -374,6 +374,10 @@ static const struct mtk_disp_rdma_data
mt8192_rdma_driver_data = {
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+ .fifo_size = 1920,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = _rdma_driver_data},
@@ -383,6 +387,8 @@ static const struct of_device_id
mtk_disp_rdma_driver_dt_match[] = {
.data = _rdma_driver_data},
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = _rdma_driver_data},
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = _rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index adc9a4f4085b..9b5a7a7ddde0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -195,6 +195,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER0,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_DP_INTF0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -253,6 +266,11 @@ static const struct mtk_mmsys_driver_data
mt8192_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .main_path = mt8195_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -470,12 +488,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8183-disp-dither",
.data = (void *)MTK_DISP_DITHER },
+ { .compatible = "mediatek,mt8195-disp-dsc",
+ .data = (void *)MTK_DISP_DSC },
{ .compatible = "mediatek,mt8167-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8183-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)MTK_DISP_MERGE },
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -490,6 +512,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -524,6 +548,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -568,6 +594,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = _mmsys_driver_data},
{ .compatible = "mediatek,mt8192-mmsys",
.data = _mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = _vdosys0_driver_data},
To make this work with older device tree, we will need to provide the same
driver data to the old compatible:
+ { .compatible = "mediatek,,mt8195-mmsys",
+ .data = _vdosys0_driver_data},
+ }
Regards,
Matthias
{ }
};
Re: [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API
On 08/11/2022 20:43, Nícolas F. R. A. Prado wrote:
On Tue, Nov 08, 2022 at 06:37:19PM +0100, Matthias Brugger wrote:
On 07/11/2022 08:22, Nancy.Lin wrote:
Simplify code for update mmsys reg.
Signed-off-by: Nancy.Lin
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: CK Hu
Tested-by: AngeloGioacchino Del Regno
Tested-by: Bo-Chen Chen
Reviewed-by: Nícolas F. R. A. Prado
---
drivers/soc/mediatek/mtk-mmsys.c | 45
1 file changed, 16 insertions(+), 29 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9a327eb5d9d7..73c8bd27e6ae 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -99,22 +99,27 @@ struct mtk_mmsys {
struct reset_controller_dev rcdev;
};
+static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32
mask, u32 val)
+{
+ u32 tmp;
+
+ tmp = readl_relaxed(mmsys->regs + offset);
+ tmp = (tmp & ~mask) | (val & mask);
I'm not sure about the change in the implementation of
mtk_mmsys_update_bits(). Nicolas tried to explain it to me on IRC but I
wasn't totally convincing. As we have to go for at least another round of
this patches, I'd like to get a clear understanding while it is needed that
val bits are set to 1 in the mask.
The point here was to make sure that mtk_mmsys_update_bits() didn't allow
setting bits outside of the mask, since that's never what you want: the entire
point of having a mask is to specify the bits that should be updated (and the
ones that should be kept unchanged). So for example if you had
mask = 0x0ff0
val = 0x00ff
the previous implementation would happily overwrite the 4 least significant bits
on the destination register, despite them not being present in the mask, which
is wrong.
This wrong behavior could easily lead to hard to trace bugs as soon as a badly
formatted/wrong val is passed and an unrelated bit updated due to the mask being
ignored.
For reference, _regmap_update_bits() does the same masking of the value [1].
That said, given that this function already existed and was just being moved,
it would've been cleaner to make this change in a separate commit.
Would have been better, but we can leave it as it.
Regards,
Matthias
[1]
https://elixir.bootlin.com/linux/latest/source/drivers/base/regmap/regmap.c#L3122
Thanks,
Nícolas
Regards,
Matthias
+ writel_relaxed(tmp, mmsys->regs + offset);
+}
[..]
-static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32
mask, u32 val)
-{
- u32 tmp;
-
- tmp = readl_relaxed(mmsys->regs + offset);
- tmp = (tmp & ~mask) | val;
- writel_relaxed(tmp, mmsys->regs + offset);
-}
-
[..]
Re: [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
On 09/11/2022 06:10, Jason-JH Lin (林睿祥) wrote: On Tue, 2022-11-08 at 18:46 +0100, Matthias Brugger wrote: On 07/11/2022 08:22, Nancy.Lin wrote: > Add vdosys1 mmsys compatible for MT8195 platform. > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding > to > 2 different power domains, different clock drivers and different > mediatek-drm drivers. > > Signed-off-by: Nancy.Lin > Reviewed-by: Nícolas F. R. A. Prado > --- > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 > +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > l > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > l > index 0711f1834fbd..aaabe2196185 100644 > --- > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > l > +++ > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > l > @@ -48,7 +48,9 @@ properties: > - const: syscon > > - items: > - - const: mediatek,mt8195-vdosys0 > + - enum: > + - mediatek,mt8195-vdosys0 > + - mediatek,mt8195-vdosys1 > - const: mediatek,mt8195-mmsys > - const: syscon > I think we had that several times already: https://lore.kernel.org/all/6bbe9527-ae48-30e0-fb45-519223a74...@linaro.org/ We will something like this, but please check that this does not give any errors/warnings: diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index eb451bec23d3d..8e9c4f4d7c389 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -32,13 +32,22 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8192-mmsys - - mediatek,mt8195-mmsys - mediatek,mt8365-mmsys - const: syscon - items: - const: mediatek,mt7623-mmsys - const: mediatek,mt2701-mmsys - const: syscon + - items: + - const: mediatek,mt8195-vdosys0 + - const: syscon + - items: + - const: mediatek,mt8195-vdosys1 + - const: syscon + - items: + - const: mediatek,mt8195-mmsys + - const: syscon + deprecated: true reg: maxItems: 1 Hi Matthias, As the vdosys0 previous reviewed patch: https://patchwork.kernel.org/project/linux-mediatek/patch/20220927152704.12018-2-jason-jh@mediatek.com/ Should I modify the vdosys0 items format like your example? Or should vdosys1 add items format like vdosys0's previous patch? - items: - const: mediatek,mt8195-vdosys1 - const: mediatek,mt8195-mmsys - const: syscon No, vdosys1 must not have mediatek,mt8195-mmsys fallback. Regards, Matthias Regards, Jason-JH.Lin * MEDIATEK Confidentiality Notice The information contained in this e-mail message (including any attachments) may be confidential, proprietary, privileged, or otherwise exempt from disclosure under applicable laws. It is intended to be conveyed only to the designated recipient(s). Any use, dissemination, distribution, printing, retaining or copying of this e-mail (including its attachments) by unintended recipient(s) is strictly prohibited and may be unlawful. If you are not an intended recipient of this e-mail, or believe that you have received this e-mail in error, please notify the sender immediately (by replying to this e-mail), delete any and all copies of this e-mail (including any attachments) from your system, and do not disclose the content of this e-mail to any other person. Thank you!
Re: [PATCH v5 3/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
On 05/10/2022 09:08, Jason-JH.Lin wrote: Hi Matthias, Do you have any comment for this binding? Can you help us review the soc/mediatek related patches? Patches 1-3 applied now. Sorry for the late answer. Matthias Regards, Jason-JH.Lin On Wed, 2022-09-28 at 10:14 +0200, AngeloGioacchino Del Regno wrote: Il 27/09/22 17:27, Jason-JH.Lin ha scritto: 1. Add mt8195 driver data with compatible "mediatek-mt8195- vdosys0". 2. Add mt8195 routing table settings of vdosys0. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delre...@collabora.com>
Re: [PATCH v5 6/6] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
On 27/09/2022 17:27, Jason-JH.Lin wrote:
After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
Signed-off-by: Jason-JH.Lin
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Rex-BC Chen
Acked-by: Matthias Brugger
Chun-Kuan, I understand you will take this patch through your tree as it depends
on DRM changes. We can also sync so that I take it once you merged the rest of
the series. Having vdosys1 series around maybe that's better to avoid merge
problems.
Regards,
Matthias
---
include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
b/include/linux/soc/mediatek/mtk-mmsys.h
index d2b02bb43768..16ac0e5847f0 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
- DDP_COMPONENT_DITHER,
- DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DITHER1,
DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_DP_INTF1,
Re: [PATCH v28 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
On 08/11/2022 20:10, Nícolas F. R. A. Prado wrote:
On Tue, Nov 08, 2022 at 06:46:54PM +0100, Matthias Brugger wrote:
On 07/11/2022 08:22, Nancy.Lin wrote:
[..]
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -80,6 +80,12 @@ static const struct mtk_mmsys_driver_data
mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_vdo1_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
@@ -292,6 +298,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = _vdosys0_driver_data,
It seems we are missing a patch in the series. vdosys0 also correct was
never introduced in the driver...
Hi Matthias,
as mentioned in the cover letter, this series is based on the series "Change
mmsys compatible for mt8195 mediatek-drm" [1], which introduces vdosys0. This
compatible entry specifically is added on patch 3 of that series [2].
[1]
https://lore.kernel.org/all/20220927152704.12018-1-jason-jh@mediatek.com/
My bad. Thanks for the link. I realized that yesterday but had to leave
urgently. I'll have a look on this series now.
Regards,
Matthias
[2]
https://lore.kernel.org/all/20220927152704.12018-4-jason-jh@mediatek.com/
Thanks,
Nícolas
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = _vdosys1_driver_data,
+ },
{
.compatible = "mediatek,mt8365-mmsys",
.data = _mmsys_driver_data,
Re: [PATCH v13,0/3] Add dpi output format control for MT8186
Hi Xinlei, On 09/11/2022 03:40, Xinlei Lee (李昕磊) wrote: On Tue, 2022-11-08 at 19:27 +0100, Matthias Brugger wrote: Hi Xinlei, Somehow b4 broke with your thread but I was able to apply patch 1 and 2 by hand. Thanks Matthias On 24/10/2022 04:04, xinlei@mediatek.com wrote: > From: Xinlei Lee > > Base on the branch of linus/master v6.1 rc1. > > Change since v12: > 1. Add MT8186_ prefix to variables added in mt8186-mmsys.h file. > > Change since v11: > 1. Rebase on v6.1-rc1. Change nothing. > > Change since v10: > 1. Modify patch title and add review tag. > > Change since v9: > 1. Modify the location of the mmsys_dev member variable. > > Change since v8: > 1. Modified the title and some description information. > > Changes since v7: > 1. This series is based on the following patch: > [1] soc: mediatek: Add mmsys func to adapt to dpi output for > MT8186 > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/1663161662-1598-2-git-send-email-xinlei@mediatek.com/__;!!CTRNKA9wMg0ARbw!3tXTL3P6SgcP8Q_rcyCro64dxIXE6VuVbcNftU0ZnX6TNtU1akXwd96YfnoJs_fEig$ > > 2. Modify the DPI_FORMAT_MASK macro definition to GENMASK(1, 0); > 3. Add all settings to mtk_mmsys_ddp_dpi_fmt_config; > 4. Modify the commit title to Add mt8186 dpi compatibles and > platform > data. > > Changes since v6: > 1. Different from other ICs, when mt8186 DPI changes the output > format, > the mmsys_base+400 register needs to be set to be valid at the same > time. > In this series, all the situations that mmsys need to be set up > are > perfected (not necessarily used in practice). > 2. Put the value that controls the mmsys function in mtk-mmsys.h. > 3. Encountered the sink ic switched between dual edge and single > edge, > perfected setting and clearing mmsys bit operations in mtk_dpi.c. > > Changes since v5: > 1. Separate the patch that adds edge_cfg_in_mmsys from the patch > that > adds mt8186 dpi support. > 2. Move the mmsys register definition to mmsys driver. > > Changes since v4: > 1. This series of cancellations is based on the following patches: > [1] Add MediaTek SoC(vdosys1) support for mt8195 > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/cover/20220711075245.10492-1-nancy@mediatek.com/__;!!CTRNKA9wMg0ARbw!3tXTL3P6SgcP8Q_rcyCro64dxIXE6VuVbcNftU0ZnX6TNtU1akXwd96Yfnqv0_QYpg$ > > [2] Add MediaTek SoC DRM (vdosys1) support for mt8195 > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/cover/20220804072827.22383-1-nancy@mediatek.com/__;!!CTRNKA9wMg0ARbw!3tXTL3P6SgcP8Q_rcyCro64dxIXE6VuVbcNftU0ZnX6TNtU1akXwd96YfnoZMZ_peA$ > > 2. Added mtk_mmsys_update_bits function in mtk-mmsys.c; > 3. MMSYS 0x400 register is modified to > MT8186_MMSYS_DPI_OUTPUT_FORMAT; > 4. Fix formatting issues. > > Changes since v3: > 1. Fix formatting issues; > 2. Modify the edge output control name & description; > 3. Fix the threading problem. > > Changes since v2: > 1. Modify key nouns in the description; > 2. Add the label of jitao to Co-developed-by; > 3. Macro definition address lowercase problem and function naming; > 4. Add missing a description of this property in the mtk_dpi_conf. > > Change since v1: > 1. Modify mt8186 compatiable location. > 2. Modify MT8186_DPI_OUTPUT_FORMAT name. > > When MT8186 outputs dpi signal, it is necessary to add dual edge > output > format control in mmsys. > > Xinlei Lee (3): >soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config > func >drm: mediatek: Set dpi format in mmsys >drm: mediatek: Add mt8186 dpi compatibles and platform data > > drivers/gpu/drm/mediatek/mtk_dpi.c | 32 > ++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ > drivers/soc/mediatek/mt8186-mmsys.h| 8 --- > drivers/soc/mediatek/mtk-mmsys.c | 27 +-- > --- > include/linux/soc/mediatek/mtk-mmsys.h | 7 ++ > 5 files changed, 67 insertions(+), 9 deletions(-) > Hi Matthias: Is your problem solved? I tried to pull the series in link[1] to the kernel 6.1-rc1 version, the patches are all successfully applied, and the patch in link[1] looks complete. If you still think there is something wrong, please let me know and I can send a new version to try to fix it. Everything is fine, no worries. Thanks for asking. Matthias [1]: https://patchwork.kernel.org/project/linux-mediatek/cover/1666577099-3859-1-git-send-email-xinlei@mediatek.com/ Best Regards! xinlei * MEDIATEK Confidentiality Notice The information contained in this e-mail me
Re: [PATCH v13,0/3] Add dpi output format control for MT8186
Hi Xinlei, Somehow b4 broke with your thread but I was able to apply patch 1 and 2 by hand. Thanks Matthias On 24/10/2022 04:04, xinlei@mediatek.com wrote: From: Xinlei Lee Base on the branch of linus/master v6.1 rc1. Change since v12: 1. Add MT8186_ prefix to variables added in mt8186-mmsys.h file. Change since v11: 1. Rebase on v6.1-rc1. Change nothing. Change since v10: 1. Modify patch title and add review tag. Change since v9: 1. Modify the location of the mmsys_dev member variable. Change since v8: 1. Modified the title and some description information. Changes since v7: 1. This series is based on the following patch: [1] soc: mediatek: Add mmsys func to adapt to dpi output for MT8186 https://patchwork.kernel.org/project/linux-mediatek/patch/1663161662-1598-2-git-send-email-xinlei@mediatek.com/ 2. Modify the DPI_FORMAT_MASK macro definition to GENMASK(1, 0); 3. Add all settings to mtk_mmsys_ddp_dpi_fmt_config; 4. Modify the commit title to Add mt8186 dpi compatibles and platform data. Changes since v6: 1. Different from other ICs, when mt8186 DPI changes the output format, the mmsys_base+400 register needs to be set to be valid at the same time. In this series, all the situations that mmsys need to be set up are perfected (not necessarily used in practice). 2. Put the value that controls the mmsys function in mtk-mmsys.h. 3. Encountered the sink ic switched between dual edge and single edge, perfected setting and clearing mmsys bit operations in mtk_dpi.c. Changes since v5: 1. Separate the patch that adds edge_cfg_in_mmsys from the patch that adds mt8186 dpi support. 2. Move the mmsys register definition to mmsys driver. Changes since v4: 1. This series of cancellations is based on the following patches: [1] Add MediaTek SoC(vdosys1) support for mt8195 https://patchwork.kernel.org/project/linux-mediatek/cover/20220711075245.10492-1-nancy@mediatek.com/ [2] Add MediaTek SoC DRM (vdosys1) support for mt8195 https://patchwork.kernel.org/project/linux-mediatek/cover/20220804072827.22383-1-nancy@mediatek.com/ 2. Added mtk_mmsys_update_bits function in mtk-mmsys.c; 3. MMSYS 0x400 register is modified to MT8186_MMSYS_DPI_OUTPUT_FORMAT; 4. Fix formatting issues. Changes since v3: 1. Fix formatting issues; 2. Modify the edge output control name & description; 3. Fix the threading problem. Changes since v2: 1. Modify key nouns in the description; 2. Add the label of jitao to Co-developed-by; 3. Macro definition address lowercase problem and function naming; 4. Add missing a description of this property in the mtk_dpi_conf. Change since v1: 1. Modify mt8186 compatiable location. 2. Modify MT8186_DPI_OUTPUT_FORMAT name. When MT8186 outputs dpi signal, it is necessary to add dual edge output format control in mmsys. Xinlei Lee (3): soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config func drm: mediatek: Set dpi format in mmsys drm: mediatek: Add mt8186 dpi compatibles and platform data drivers/gpu/drm/mediatek/mtk_dpi.c | 32 ++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ drivers/soc/mediatek/mt8186-mmsys.h| 8 --- drivers/soc/mediatek/mtk-mmsys.c | 27 +- include/linux/soc/mediatek/mtk-mmsys.h | 7 ++ 5 files changed, 67 insertions(+), 9 deletions(-)
Re: [PATCH v13,1/3] soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config func
On 08/11/2022 19:11, Matthias Brugger wrote:
Hi Xinlei,
Can you please fix the threading of this patches. I can see that this 1/3 but
I'm not able to find 3/3 in the series. The first two look good, the third, I
don't know.
Nevermind this message, the problem was on my side.
Regards,
Matthias
Regards,
Matthias
On 24/10/2022 04:04, xinlei@mediatek.com wrote:
From: Xinlei Lee
The difference between MT8186 and other ICs is that when modifying the
output format, we need to modify the mmsys_base+0x400 register to take
effect. So when setting the dpi output format, we need to call
mtk_mmsys_ddp_dpi_fmt_config to set it to MT8186 synchronously.
Commit a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi
output for MT8186") lacked some of the possible output formats and also
had a wrong bitmask.
Add the missing output formats and fix the bitmask.
While at it, also update mtk_mmsys_ddp_dpi_fmt_config() to use generic
formats, so that it is slightly easier to extend for other platforms.
Fixes: a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi output for
MT8186")
Signed-off-by: Xinlei Lee
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: CK Hu
Reviewed-by: Nícolas F. R. A. Prado
---
drivers/soc/mediatek/mt8186-mmsys.h | 8 +---
drivers/soc/mediatek/mtk-mmsys.c | 27 --
include/linux/soc/mediatek/mtk-mmsys.h | 7 +++
3 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h
b/drivers/soc/mediatek/mt8186-mmsys.h
index 09b1ccbc0093..279d4138525b 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -5,9 +5,11 @@
/* Values for DPI configuration in MMSYS address space */
#define MT8186_MMSYS_DPI_OUTPUT_FORMAT 0x400
-#define DPI_FORMAT_MASK 0x1
-#define DPI_RGB888_DDR_CON BIT(0)
-#define DPI_RGB565_SDR_CON BIT(1)
+#define MT8186_DPI_FORMAT_MASK GENMASK(1, 0)
+#define MT8186_DPI_RGB888_SDR_CON 0
+#define MT8186_DPI_RGB888_DDR_CON 1
+#define MT8186_DPI_RGB565_SDR_CON 2
+#define MT8186_DPI_RGB565_DDR_CON 3
#define MT8186_MMSYS_OVL_CON 0xF04
#define MT8186_MMSYS_OVL0_CON_MASK 0x3
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 2e20b24da363..16cd924d8973 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -238,12 +238,27 @@ static void mtk_mmsys_update_bits(struct mtk_mmsys
*mmsys, u32 offset, u32 mask,
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
{
- if (val)
- mtk_mmsys_update_bits(dev_get_drvdata(dev),
MT8186_MMSYS_DPI_OUTPUT_FORMAT,
- DPI_RGB888_DDR_CON, DPI_FORMAT_MASK);
- else
- mtk_mmsys_update_bits(dev_get_drvdata(dev),
MT8186_MMSYS_DPI_OUTPUT_FORMAT,
- DPI_RGB565_SDR_CON, DPI_FORMAT_MASK);
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+
+ switch (val) {
+ case MTK_DPI_RGB888_SDR_CON:
+ mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
+ MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON);
+ break;
+ case MTK_DPI_RGB565_SDR_CON:
+ mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
+ MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON);
+ break;
+ case MTK_DPI_RGB565_DDR_CON:
+ mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
+ MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON);
+ break;
+ case MTK_DPI_RGB888_DDR_CON:
+ default:
+ mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
+ MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON);
+ break;
+ }
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
b/include/linux/soc/mediatek/mtk-mmsys.h
index d2b02bb43768..b85f66db33e1 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -9,6 +9,13 @@
enum mtk_ddp_comp_id;
struct device;
+enum mtk_dpi_out_format_con {
+ MTK_DPI_RGB888_SDR_CON,
+ MTK_DPI_RGB888_DDR_CON,
+ MTK_DPI_RGB565_SDR_CON,
+ MTK_DPI_RGB565_DDR_CON
+};
+
enum mtk_ddp_comp_id {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_AAL1,
Re: [PATCH v13,1/3] soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config func
Hi Xinlei,
Can you please fix the threading of this patches. I can see that this 1/3 but
I'm not able to find 3/3 in the series. The first two look good, the third, I
don't know.
Regards,
Matthias
On 24/10/2022 04:04, xinlei@mediatek.com wrote:
From: Xinlei Lee
The difference between MT8186 and other ICs is that when modifying the
output format, we need to modify the mmsys_base+0x400 register to take
effect. So when setting the dpi output format, we need to call
mtk_mmsys_ddp_dpi_fmt_config to set it to MT8186 synchronously.
Commit a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi
output for MT8186") lacked some of the possible output formats and also
had a wrong bitmask.
Add the missing output formats and fix the bitmask.
While at it, also update mtk_mmsys_ddp_dpi_fmt_config() to use generic
formats, so that it is slightly easier to extend for other platforms.
Fixes: a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi output for MT8186")
Signed-off-by: Xinlei Lee
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: CK Hu
Reviewed-by: Nícolas F. R. A. Prado
---
drivers/soc/mediatek/mt8186-mmsys.h| 8 +---
drivers/soc/mediatek/mtk-mmsys.c | 27 --
include/linux/soc/mediatek/mtk-mmsys.h | 7 +++
3 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h
b/drivers/soc/mediatek/mt8186-mmsys.h
index 09b1ccbc0093..279d4138525b 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -5,9 +5,11 @@
/* Values for DPI configuration in MMSYS address space */
#define MT8186_MMSYS_DPI_OUTPUT_FORMAT0x400
-#define DPI_FORMAT_MASK0x1
-#define DPI_RGB888_DDR_CON BIT(0)
-#define DPI_RGB565_SDR_CON BIT(1)
+#define MT8186_DPI_FORMAT_MASK GENMASK(1, 0)
+#define MT8186_DPI_RGB888_SDR_CON 0
+#define MT8186_DPI_RGB888_DDR_CON 1
+#define MT8186_DPI_RGB565_SDR_CON 2
+#define MT8186_DPI_RGB565_DDR_CON 3
#define MT8186_MMSYS_OVL_CON 0xF04
#define MT8186_MMSYS_OVL0_CON_MASK0x3
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 2e20b24da363..16cd924d8973 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -238,12 +238,27 @@ static void mtk_mmsys_update_bits(struct mtk_mmsys
*mmsys, u32 offset, u32 mask,
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
{
- if (val)
- mtk_mmsys_update_bits(dev_get_drvdata(dev),
MT8186_MMSYS_DPI_OUTPUT_FORMAT,
- DPI_RGB888_DDR_CON, DPI_FORMAT_MASK);
- else
- mtk_mmsys_update_bits(dev_get_drvdata(dev),
MT8186_MMSYS_DPI_OUTPUT_FORMAT,
- DPI_RGB565_SDR_CON, DPI_FORMAT_MASK);
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+
+ switch (val) {
+ case MTK_DPI_RGB888_SDR_CON:
+ mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
+ MT8186_DPI_FORMAT_MASK,
MT8186_DPI_RGB888_SDR_CON);
+ break;
+ case MTK_DPI_RGB565_SDR_CON:
+ mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
+ MT8186_DPI_FORMAT_MASK,
MT8186_DPI_RGB565_SDR_CON);
+ break;
+ case MTK_DPI_RGB565_DDR_CON:
+ mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
+ MT8186_DPI_FORMAT_MASK,
MT8186_DPI_RGB565_DDR_CON);
+ break;
+ case MTK_DPI_RGB888_DDR_CON:
+ default:
+ mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT,
+ MT8186_DPI_FORMAT_MASK,
MT8186_DPI_RGB888_DDR_CON);
+ break;
+ }
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index d2b02bb43768..b85f66db33e1 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -9,6 +9,13 @@
enum mtk_ddp_comp_id;
struct device;
+enum mtk_dpi_out_format_con {
+ MTK_DPI_RGB888_SDR_CON,
+ MTK_DPI_RGB888_DDR_CON,
+ MTK_DPI_RGB565_SDR_CON,
+ MTK_DPI_RGB565_DDR_CON
+};
+
enum mtk_ddp_comp_id {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_AAL1,
Re: [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
On 07/11/2022 08:22, Nancy.Lin wrote: Add vdosys1 mmsys compatible for MT8195 platform. For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to 2 different power domains, different clock drivers and different mediatek-drm drivers. Signed-off-by: Nancy.Lin Reviewed-by: Nícolas F. R. A. Prado --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 0711f1834fbd..aaabe2196185 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -48,7 +48,9 @@ properties: - const: syscon - items: - - const: mediatek,mt8195-vdosys0 + - enum: + - mediatek,mt8195-vdosys0 + - mediatek,mt8195-vdosys1 - const: mediatek,mt8195-mmsys - const: syscon I think we had that several times already: https://lore.kernel.org/all/6bbe9527-ae48-30e0-fb45-519223a74...@linaro.org/ We will something like this, but please check that this does not give any errors/warnings: diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index eb451bec23d3d..8e9c4f4d7c389 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -32,13 +32,22 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8192-mmsys - - mediatek,mt8195-mmsys - mediatek,mt8365-mmsys - const: syscon - items: - const: mediatek,mt7623-mmsys - const: mediatek,mt2701-mmsys - const: syscon + - items: + - const: mediatek,mt8195-vdosys0 + - const: syscon + - items: + - const: mediatek,mt8195-vdosys1 + - const: syscon + - items: + - const: mediatek,mt8195-mmsys + - const: syscon + deprecated: true reg: maxItems: 1
Re: [PATCH v28 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
On 07/11/2022 08:22, Nancy.Lin wrote:
Add mt8195 vdosys1 routing table to the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Rex-BC Chen
Reviewed-by: CK Hu
Tested-by: AngeloGioacchino Del Regno
Tested-by: Bo-Chen Chen
---
drivers/soc/mediatek/mt8195-mmsys.h | 139
drivers/soc/mediatek/mtk-mmsys.c| 10 ++
2 files changed, 149 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
b/drivers/soc/mediatek/mt8195-mmsys.h
index abfe94a30248..fd7b455bd675 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -75,6 +75,70 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0(2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE(3 <<
16)
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL0xf18
+#define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2
+#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define MT8195_SOUT_TO_MIXER_IN1_SEL 1
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define MT8195_SOUT_TO_MIXER_IN2_SEL 1
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define MT8195_SOUT_TO_MIXER_IN3_SEL 1
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define MT8195_SOUT_TO_MIXER_IN4_SEL 1
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN0xf50
+#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER0
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER0
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER0
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER0
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -367,4 +431,79 @@ static const struct mtk_mmsys_routes
mmsys_mt8195_routing_table[] = {
}
};
+static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
+ {
+ DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ }, {
+ DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ }, {
+ DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ }, {
+ DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+
Re: [PATCH v28 06/11] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
On 07/11/2022 08:22, Nancy.Lin wrote:
Add four mmsys config APIs. The config APIs are used for config
mmsys reg. Some mmsys regs need to be set according to the
HW engine binding to the mmsys simultaneously.
1. mtk_mmsys_merge_async_config: config merge async width/height.
async is used for cross-clock domain synchronization.
2. mtk_mmsys_hdr_confing: config hdr backend async width/height.
3. mtk_mmsys_mixer_in_config and mtk_mmsys_mixer_in_config:
config mixer related settings.
Signed-off-by: Nancy.Lin
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: CK Hu
Tested-by: AngeloGioacchino Del Regno
Tested-by: Bo-Chen Chen
Not something we need to fix in this series, but it would make sense instead of
adding all the EXPORTS to pass the functions as callbacks in the
platform_device_register_data. But I realize you don't pass the VDOSYS number to
the DRM driver to distinguish between the different MMSYS devices that created
the platform device. I hadn't had a deep look on the DRM implementation but I
suppose it will be challenge...
Regards,
Matthias
---
drivers/soc/mediatek/mt8195-mmsys.h| 6 +
drivers/soc/mediatek/mtk-mmsys.c | 35 ++
include/linux/soc/mediatek/mtk-mmsys.h | 9 +++
3 files changed, 50 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
b/drivers/soc/mediatek/mt8195-mmsys.h
index fd7b455bd675..454944a9409c 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -75,6 +75,12 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0(2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE(3 <<
16)
+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD0xe30
+#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8195_VDO1_HDR_TOP_CFG0xd00
+#define MT8195_VDO1_MIXER_IN1_ALPHA0xd30
+#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
+
#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA01
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 73c8bd27e6ae..6040a3cff6f8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -137,6 +137,41 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height)
+{
+ mtk_mmsys_update_bits(dev_get_drvdata(dev),
MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
+ ~0, height << 16 | width);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
+
+void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height)
+{
+ mtk_mmsys_update_bits(dev_get_drvdata(dev),
MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
+ be_height << 16 | be_width);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config);
+
+void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel,
u16 alpha,
+ u8 mode, u32 biwidth)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+
+ mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) *
4, ~0,
+ alpha << 16 | alpha);
+ mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx),
+ alpha_sel << (19 + idx));
+ mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
+ GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 |
mode);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
+
+void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool
channel_swap)
+{
+ mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD +
(idx - 1) * 4,
+ BIT(4), channel_swap << 4);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
+
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
{
if (val)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
b/include/linux/soc/mediatek/mtk-mmsys.h
index 127f1b888ace..a4708859c188 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -75,4 +75,13 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
+void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height);
+
+void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height);
+
+void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel,
u16 alpha,
+ u8 mode, u32 biwidth);
+
+void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool
channel_swap);
+
#endif /* __MTK_MMSYS_H */
Re: [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API
On 07/11/2022 08:22, Nancy.Lin wrote:
Simplify code for update mmsys reg.
Signed-off-by: Nancy.Lin
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: CK Hu
Tested-by: AngeloGioacchino Del Regno
Tested-by: Bo-Chen Chen
Reviewed-by: Nícolas F. R. A. Prado
---
drivers/soc/mediatek/mtk-mmsys.c | 45
1 file changed, 16 insertions(+), 29 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9a327eb5d9d7..73c8bd27e6ae 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -99,22 +99,27 @@ struct mtk_mmsys {
struct reset_controller_dev rcdev;
};
+static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ tmp = readl_relaxed(mmsys->regs + offset);
+ tmp = (tmp & ~mask) | (val & mask);
I'm not sure about the change in the implementation of mtk_mmsys_update_bits().
Nicolas tried to explain it to me on IRC but I wasn't totally convincing. As we
have to go for at least another round of this patches, I'd like to get a clear
understanding while it is needed that val bits are set to 1 in the mask.
Regards,
Matthias
+ writel_relaxed(tmp, mmsys->regs + offset);
+}
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_routes *routes = mmsys->data->routes;
- u32 reg;
int i;
for (i = 0; i < mmsys->data->num_routes; i++)
- if (cur == routes[i].from_comp && next == routes[i].to_comp) {
- reg = readl_relaxed(mmsys->regs + routes[i].addr);
- reg &= ~routes[i].mask;
- reg |= routes[i].val;
- writel_relaxed(reg, mmsys->regs + routes[i].addr);
- }
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ mtk_mmsys_update_bits(mmsys, routes[i].addr,
routes[i].mask,
+ routes[i].val);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -124,27 +129,14 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_routes *routes = mmsys->data->routes;
- u32 reg;
int i;
for (i = 0; i < mmsys->data->num_routes; i++)
- if (cur == routes[i].from_comp && next == routes[i].to_comp) {
- reg = readl_relaxed(mmsys->regs + routes[i].addr);
- reg &= ~routes[i].mask;
- writel_relaxed(reg, mmsys->regs + routes[i].addr);
- }
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ mtk_mmsys_update_bits(mmsys, routes[i].addr,
routes[i].mask, 0);
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
-static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
-{
- u32 tmp;
-
- tmp = readl_relaxed(mmsys->regs + offset);
- tmp = (tmp & ~mask) | val;
- writel_relaxed(tmp, mmsys->regs + offset);
-}
-
void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
{
if (val)
@@ -161,18 +153,13 @@ static int mtk_mmsys_reset_update(struct
reset_controller_dev *rcdev, unsigned l
{
struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
unsigned long flags;
- u32 reg;
spin_lock_irqsave(>lock, flags);
- reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
-
if (assert)
- reg &= ~BIT(id);
+ mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset,
BIT(id), 0);
else
- reg |= BIT(id);
-
- writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
+ mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset,
BIT(id), BIT(id));
spin_unlock_irqrestore(>lock, flags);
Re: [PATCH v2 1/6] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195
On 15/09/2022 18:18, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
and they makes VDOSYS0 supports PQ function while they are not
including in VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component). It makes VDOSYS1 supports the HDR function while it's not
including in VDOSYS0.
To summarize0:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.
Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.
Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC
binding")
Signed-off-by: Jason-JH.Lin
Signed-off-by: Bo-Chen Chen
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 6ad023eec193..0e267428eaa6 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,7 +31,7 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
- - mediatek,mt8195-mmsys
+ - mediatek,mt8195-vdosys0
Nack, we miss the fallback compatible, as I already said twice.
Regards,
Matthias
- mediatek,mt8365-mmsys
- const: syscon
- items:
Re: [PATCH 1/5] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195
Hi Jason,
On 15/09/2022 03:24, Jason-JH Lin wrote:
Hi Matthias,
Thanks for the reviews.
On Wed, 2022-09-14 at 23:24 +0200, Matthias Brugger wrote:
On 14/09/2022 20:23, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding
to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture
Quality)
and they makes VDOSYS0 supports PQ function while they are not
including in VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component). It makes VDOSYS1 supports the HDR function while it's
not
including in VDOSYS0.
To summarize0:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.
Therefore, we need to separate these two different mmsys hardwares
to
2 different compatibles for MT8195.
Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195
SoC binding")
Signed-off-by: Jason-JH.Lin
Signed-off-by: Bo-Chen Chen
Acked-by: Krzysztof Kozlowski
I'm not sure Krzysztof gave his Acked-by tag.
I'll remove this tag.
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml|
2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
l
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
l
index 6ad023eec193..a53b32c0a608 100644
---
a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
l
+++
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
l
@@ -32,6 +32,8 @@ properties:
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
- mediatek,mt8195-mmsys
+ - mediatek,mt8195-vdosys0
As I said in the last submission, we should make mediatek,mt8195-
mmsys as a
fallback of vdosys0. Actually mediatek,mt8195-mmsys is only used for
the
fallback of vdosys0.
I think adding both vdosys0 and vdosys1 can make the description of
this patch clearer.
It's find to me to only add "mediatek,mt8195-vdosys0" in this patch.
So I'll remove the "mediatek,mt8195-vdosys1" at the next version.
That's not what I wanted to suggest. Up to now in upstream kernel compatible
mediatek,mt8195-mmsys enables support fro vdosys0. The vdosys1 is not yet
upstream, so no support.
If we change the compatible, we should keep mediatek,mt8195-mmsys as fallback of
"mediatek,mt8195-vdosys0" so that older device tree blobs won't break with a
newer kernel.
For "mediatek,mt8195-vdosys1" we do not need a fallback compatible as the code
never reached upstream, so no breakage expected.
Hope I explain myself now.
Regards,
Matthias
Regards,
Jason-JH.Lin
Regards,
Matthias
+ - mediatek,mt8195-vdosys1
- mediatek,mt8365-mmsys
- const: syscon
- items:
Re: [PATCH v6,1/3] soc: mediatek: Add mmsys func to adapt to dpi output for MT8186
On 14/09/2022 15:21, xinlei@mediatek.com wrote:
From: Xinlei Lee
Add mmsys func to manipulate dpi output format config for MT8186.
Co-developed-by: Jitao Shi
Signed-off-by: Jitao Shi
Signed-off-by: Xinlei Lee
Reviewed-by: Nís F. R. A. Prado
Applied, thanks!
---
drivers/soc/mediatek/mt8186-mmsys.h| 6 ++
drivers/soc/mediatek/mtk-mmsys.c | 20
include/linux/soc/mediatek/mtk-mmsys.h | 2 ++
3 files changed, 28 insertions(+)
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h
b/drivers/soc/mediatek/mt8186-mmsys.h
index eb1ad9c37a9c..09b1ccbc0093 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -3,6 +3,12 @@
#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H
#define __SOC_MEDIATEK_MT8186_MMSYS_H
+/* Values for DPI configuration in MMSYS address space */
+#define MT8186_MMSYS_DPI_OUTPUT_FORMAT 0x400
+#define DPI_FORMAT_MASK0x1
+#define DPI_RGB888_DDR_CON BIT(0)
+#define DPI_RGB565_SDR_CON BIT(1)
+
#define MT8186_MMSYS_OVL_CON 0xF04
#define MT8186_MMSYS_OVL0_CON_MASK0x3
#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 06d8e83a2cb5..2e20b24da363 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -227,6 +227,26 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ tmp = readl_relaxed(mmsys->regs + offset);
+ tmp = (tmp & ~mask) | val;
+ writel_relaxed(tmp, mmsys->regs + offset);
+}
+
+void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
+{
+ if (val)
+ mtk_mmsys_update_bits(dev_get_drvdata(dev),
MT8186_MMSYS_DPI_OUTPUT_FORMAT,
+ DPI_RGB888_DDR_CON, DPI_FORMAT_MASK);
+ else
+ mtk_mmsys_update_bits(dev_get_drvdata(dev),
MT8186_MMSYS_DPI_OUTPUT_FORMAT,
+ DPI_RGB565_SDR_CON, DPI_FORMAT_MASK);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);
+
static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev,
unsigned long id,
bool assert)
{
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
b/include/linux/soc/mediatek/mtk-mmsys.h
index 59117d970daf..d2b02bb43768 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -65,4 +65,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
+
#endif /* __MTK_MMSYS_H */
Re: [PATCH 4/5] arm64: dts: change compatible of vdosys0 and vdosys1 for mt8195
On 14/09/2022 20:23, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
and they makes VDOSYS0 supports PQ function while they are not
including in VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component). It makes VDOSYS1 supports the HDR function while it's not
including in VDOSYS0.
To summarize0:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.
Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.
Fixes: b852ee68fd72 ("arm64: dts: mt8195: Add display node for vdosys0")
No fixes tag needed, there is no runtime bug.
Regards,
Matthias
Signed-off-by: Jason-JH.Lin
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..6ec6d59a16ec 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1966,7 +1966,7 @@
};
vdosys0: syscon@1c01a000 {
- compatible = "mediatek,mt8195-mmsys", "syscon";
+ compatible = "mediatek,mt8195-vdosys0", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
mboxes = < 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
@@ -2101,7 +2101,7 @@
};
vdosys1: syscon@1c10 {
- compatible = "mediatek,mt8195-mmsys", "syscon";
+ compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c10 0 0x1000>;
#clock-cells = <1>;
};
Re: [PATCH 3/3] drm/mediatek: dp: Fix warning in mtk_dp_video_mute()
On 15/09/2022 09:50, Bo-Chen Chen wrote: Warning: ../drivers/gpu/drm/mediatek/mtk_dp.c: In function ‘mtk_dp_video_mute’: ../drivers/gpu/drm/mediatek/mtk_dp.c:947:23: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 4 has type ‘long unsigned int’ [-Wformat=] 947 | dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: 0x%x, ret: 0x%lx-0x%lx\n", | ^ ../include/linux/dev_printk.h:129:27: note: in definition of macro ‘dev_printk’ 129 | _dev_printk(level, dev, fmt, ##__VA_ARGS__); \ | ^~~ ../include/linux/dev_printk.h:163:31: note: in expansion of macro ‘dev_fmt’ 163 | dev_printk(KERN_DEBUG, dev, dev_fmt(fmt), ##__VA_ARGS__); \ | ^~~ ../drivers/gpu/drm/mediatek/mtk_dp.c:947:2: note: in expansion of macro ‘dev_dbg’ 947 | dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: 0x%x, ret: 0x%lx-0x%lx\n", | ^~~ ../drivers/gpu/drm/mediatek/mtk_dp.c:947:36: note: format string is defined here 947 | dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: 0x%x, ret: 0x%lx-0x%lx\n", | ~^ || |unsigned int | %lx To fix this issue, we use %s to replace 0x%x. Reported-by: Chun-Kuang Hu Signed-off-by: Bo-Chen Chen Reviewed-by: Matthias Brugger --- drivers/gpu/drm/mediatek/mtk_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index c72c646e25e9..d58e98b2f83a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -1222,8 +1222,8 @@ static void mtk_dp_video_mute(struct mtk_dp *mtk_dp, bool enable) mtk_dp->data->smc_cmd, enable, 0, 0, 0, 0, 0, ); - dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: 0x%x, ret: 0x%lx-0x%lx\n", - mtk_dp->data->smc_cmd, enable, res.a0, res.a1); + dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: %s, ret: 0x%lx-0x%lx\n", + mtk_dp->data->smc_cmd, enable ? "enable" : "disable", res.a0, res.a1); } static void mtk_dp_audio_mute(struct mtk_dp *mtk_dp, bool mute)
Re: [PATCH 2/3] drm/mediatek: dp: Remove unused register definitions
On 15/09/2022 09:50, Bo-Chen Chen wrote: Some definitions in mtk_dp_reg.h are not used, so remove these redundant codes. Signed-off-by: Bo-Chen Chen Reviewed-by: Matthias Brugger --- drivers/gpu/drm/mediatek/mtk_dp_reg.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h index 096ad6572a5e..84e38cef03c2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h @@ -153,8 +153,6 @@ #define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0) #define MTK_DP_ENC0_P0_3094 0x3094 #define CH_STATUS_2_DP_ENC0_P0_MASK GENMASK(7, 0) -#define MTK_DP_ENC0_P0_30A00x30a0 -#define DP_ENC0_30A0_MASK (BIT(7) | BIT(8) | BIT(12)) #define MTK_DP_ENC0_P0_30A4 0x30a4 #define AU_TS_CFG_DP_ENC0_P0_MASK GENMASK(7, 0) #define MTK_DP_ENC0_P0_30A8 0x30a8 @@ -171,8 +169,6 @@ #define MTK_DP_ENC0_P0_312C 0x312c #define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0) #define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8) -#define MTK_DP_ENC0_P0_31300x3130 -#define MTK_DP_ENC0_P0_31380x3138 #define MTK_DP_ENC0_P0_3154 0x3154 #define PGEN_HTOTAL_DP_ENC0_P0_MASK GENMASK(13, 0) #define MTK_DP_ENC0_P0_3158 0x3158 @@ -206,8 +202,6 @@ #define SDP_PACKET_TYPE_DP_ENC1_P0_MASK GENMASK(4, 0) #define SDP_PACKET_W_DP_ENC1_P0 BIT(5) #define SDP_PACKET_W_DP_ENC1_P0_MASK BIT(5) -#define MTK_DP_ENC1_P0_328C0x328c -#define VSC_DATA_RDY_VESA_DP_ENC1_P0_MASK BIT(7) #define MTK_DP_ENC1_P0_3300 0x3300 #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_VAL2 #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK GENMASK(9, 8)
Re: [PATCH 1/5] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195
On 14/09/2022 20:23, Jason-JH.Lin wrote:
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.
Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
and they makes VDOSYS0 supports PQ function while they are not
including in VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component). It makes VDOSYS1 supports the HDR function while it's not
including in VDOSYS0.
To summarize0:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.
Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.
Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC
binding")
Signed-off-by: Jason-JH.Lin
Signed-off-by: Bo-Chen Chen
Acked-by: Krzysztof Kozlowski
I'm not sure Krzysztof gave his Acked-by tag.
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml| 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 6ad023eec193..a53b32c0a608 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -32,6 +32,8 @@ properties:
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
- mediatek,mt8195-mmsys
+ - mediatek,mt8195-vdosys0
As I said in the last submission, we should make mediatek,mt8195-mmsys as a
fallback of vdosys0. Actually mediatek,mt8195-mmsys is only used for the
fallback of vdosys0.
Regards,
Matthias
+ - mediatek,mt8195-vdosys1
- mediatek,mt8365-mmsys
- const: syscon
- items:
Re: [PATCH 5/5] dt-bindings: arm: mediatek: mmsys: remove the unused compatible for mt8195
On 14/09/2022 20:23, Jason-JH.Lin wrote:
The compatible properties of mt8195 have changed to mediatek,mt8195-vdosys0
and mediatek,mt8195-vdosys1 from mediatek,mt895-mmsys, so remove the unused
compatible.
Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC
binding")
Signed-off-by: Jason-JH.Lin
Signed-off-by: Bo-Chen Chen
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index a53b32c0a608..bfbdd30d2092 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,7 +31,6 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys
- - mediatek,mt8195-mmsys
Should be part of the first patch. As described in the review.
Regards,
Matthias
- mediatek,mt8195-vdosys0
- mediatek,mt8195-vdosys1
- mediatek,mt8365-mmsys
Re: [PATCH 2/5] soc: mediatek: change compatible name for mt8195
On 14/09/2022 20:23, Jason-JH.Lin wrote:
In mt8195, vdosys0 and vdosys1 are 2 different function blocks
for mediatek-drm, so using 2 compatible instead of identifying
multiple mmsys by io_start.
Fixes: b804923b7ccb ("soc: mediatek: add mtk-mmsys support for mt8195 vdosys0")
Signed-off-by: Jason-JH.Lin
From what I have seen we can just revert the commit. No fixes tag needed, it
does not fix any (runtime) bug.
Regards,
Matthias
---
drivers/soc/mediatek/mtk-mmsys.c | 141 +--
drivers/soc/mediatek/mtk-mmsys.h | 6 --
2 files changed, 21 insertions(+), 126 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 06d8e83a2cb5..e1c653f3abc0 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -26,61 +26,26 @@ static const struct mtk_mmsys_driver_data
mt2701_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
};
-static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.clk_driver = "clk-mt2712-mm",
.routes = mmsys_default_routing_table,
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
};
-static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
.clk_driver = "clk-mt6779-mm",
};
-static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
.clk_driver = "clk-mt6797-mm",
};
-static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
.clk_driver = "clk-mt8167-mm",
.routes = mt8167_mmsys_routing_table,
.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
};
-static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
.routes = mmsys_default_routing_table,
@@ -88,13 +53,6 @@ static const struct mtk_mmsys_driver_data
mt8173_mmsys_driver_data = {
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
-static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
@@ -102,13 +60,6 @@ static const struct mtk_mmsys_driver_data
mt8183_mmsys_driver_data = {
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
-static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
.clk_driver = "clk-mt8186-mm",
.routes = mmsys_mt8186_routing_table,
@@ -116,13 +67,6 @@ static const struct mtk_mmsys_driver_data
mt8186_mmsys_driver_data = {
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
};
-static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.clk_driver = "clk-mt8192-mm",
.routes = mmsys_mt8192_routing_table,
@@ -130,66 +74,29 @@ static const struct mtk_mmsys_driver_data
mt8192_mmsys_driver_data = {
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
};
-static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
- _mmsys_driver_data,
- },
-};
-
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
- .io_start = 0x1c01a000,
.clk_driver = "clk-mt8195-vdo0",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
- .io_start = 0x1c10,
.clk_driver = "clk-mt8195-vdo1",
};
-static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
- .num_drv_data = 2,
-
Re: [PATCH] drm/mediatek: Fix wrong dither settings
On 08/09/2022 16:12, Allen-KH Cheng wrote:
The width and height arguments in the cmdq packet for mtk_dither_config()
are inverted. We fix the incorrect width and height for dither settings
in mtk_dither_config().
Fixes: 73d3724745db ("drm/mediatek: Adjust to the alphabetic order for
mediatek-drm")
Co-developed-by: Yongqiang Niu
Signed-off-by: Yongqiang Niu
Signed-off-by: Allen-KH Cheng
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 2d72cc5ddaba..6b6d5335c834 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -157,7 +157,7 @@ static void mtk_dither_config(struct device *dev, unsigned
int w,
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, priv->regs,
DISP_REG_DITHER_SIZE);
mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg, priv->regs,
DISP_REG_DITHER_CFG);
mtk_dither_set_common(priv->regs, >cmdq_reg, bpc,
DISP_REG_DITHER_CFG,
Re: [PATCH v3,1/2] soc: mediatek: Add mmsys func to adapt to dpi output for MT8186
On 23/08/2022 22:17, Nícolas F. R. A. Prado wrote: On Tue, Aug 23, 2022 at 02:38:22PM +0800, xinlei@mediatek.com wrote: From: Xinlei Lee Add mmsys function to manipulate dpi output format configuration for MT8186. Co-developed-by: Jitao Shi Signed-off-by: Jitao Shi Signed-off-by: Xinlei Lee Reviewed-by: Nícolas F. R. A. Prado Patch looks fine, I'll wait for v4 as there is still some discussion on the DRM part. Please try to fix the threading problem you had in sending this series. Thanks, Matthias
Re: [PATCH linux-next v2] drm/mediatek: Remove the unneeded result
On 25/08/2022 09:23, cgel@gmail.com wrote:
From: ye xingchen
Return the value drm_mode_config_helper_suspend() directly instead of
storing it in another redundant variable.
Reported-by: Zeal Robot
Signed-off-by: ye xingchen
I thought I already did this in v1, anyway here we go again:
Reviewed-by: Matthias Brugger
---
v1 -> v2
Add all the mailinglists that get_maintainers.pl give.
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 5f02f8d0e4fc..91f58db5915f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -833,11 +833,8 @@ static int mtk_drm_sys_prepare(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
struct drm_device *drm = private->drm;
- int ret;
-
- ret = drm_mode_config_helper_suspend(drm);
- return ret;
+ return drm_mode_config_helper_suspend(drm);
}
static void mtk_drm_sys_complete(struct device *dev)
