[DO NOT MERGE v8 23/36] mfd: sm501: Convert platform_data to OF property
Various parameters of SM501 can be set using platform_data,
so parameters cannot be passed in the DeviceTree target.
Expands the parameters set in platform_data so that they can be
specified using DeviceTree properties.
Signed-off-by: Yoshinori Sato
---
drivers/mfd/sm501.c | 238 ++
drivers/video/fbdev/sm501fb.c | 87 +
2 files changed, 325 insertions(+)
diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c
index b3592982a83b..d373aded0c3b 100644
--- a/drivers/mfd/sm501.c
+++ b/drivers/mfd/sm501.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
@@ -82,6 +83,16 @@ struct sm501_devdata {
unsigned int rev;
};
+struct sm501_config_props_uint {
+ char *name;
+ u32 shift;
+};
+
+struct sm501_config_props_flag {
+ char *clr_name;
+ char *set_name;
+ u32 bit;
+};
#define MHZ (1000 * 1000)
@@ -1370,6 +1381,227 @@ static int sm501_init_dev(struct sm501_devdata *sm)
return 0;
}
+#define FIELD_WIDTH 4
+struct dt_values {
+ char *name;
+ unsigned int offset;
+ unsigned int width;
+ char *val[(1 << FIELD_WIDTH) + 1];
+};
+
+#define fld(_name, _offset, _width, ...) \
+ { \
+ .name = _name, \
+ .offset = _offset, \
+ .width = _width,\
+ .val = { __VA_ARGS__, NULL},\
+ }
+
+static const struct dt_values misc_timing[] = {
+ fld("ex", 28, 4,
+ "none", "16", "32", "48", "64", "80", "96", "112",
+ "128", "144", "160", "176", "192", "208", "224", "240"),
+ fld("xc", 24, 2, "internal-pll", "hclk", "gpio30"),
+ fld("us", 23, 1, "disable", "enable"),
+ fld("ssm1", 20, 1, "288", "divider"),
+ fld("sm1", 16, 4,
+ "1", "2", "4", "8", "16", "32", "64", "128",
+ "3", "6", "12", "24", "48", "96", "192", "384"),
+ fld("ssm0", 12, 1, "288", "divider"),
+ fld("sm0", 8, 4,
+ "1", "2", "4", "8", "16", "32", "64", "128",
+ "3", "6", "12", "24", "48", "96", "192", "384"),
+ fld("deb", 7, 1, "input-reference", "output"),
+ fld("a", 6, 1, "no-acpi", "acpi"),
+ fld("divider", 4, 2, "336", "288", "240", "192"),
+ fld("u", 3, 1, "normal", "simulation"),
+ fld("delay", 0, 3, "none", "0.5", "1.0", "1.5", "2.0", "2.5"),
+ { .name = NULL },
+};
+
+static const struct dt_values misc_control[] = {
+ fld("pad", 30, 2, "24", "12", "8"),
+ fld("usbclk", 28, 2, "xtal", "96", "48"),
+ fld("ssp", 27, 1, "uart1", "ssp1"),
+ fld("lat", 26, 1, "disable", "enable"),
+ fld("fp", 25, 1, "18", "24"),
+ fld("freq", 24, 1, "24", "12"),
+ fld("refresh", 21, 2, "8", "16", "32", "64"),
+ fld("hold", 18, 3, "fifo-empty", "8", "16", "24", "32"),
+ fld("sh", 17, 1, "active-low", "active-high"),
+ fld("ii", 16, 1, "normal", "inverted"),
+ fld("pll", 15, 1, "disable", "enable"),
+ fld("gap", 13, 2, "0"),
+ fld("dac", 12, 1, "enable", "disable"),
+ fld("mc", 11, 1, "cpu", "8051"),
+ fld("bl", 10, 8, "1"),
+ fld("usb", 9, 1, "master", "slave"),
+ fld("vr", 4, 1, "0x1e0", "0x3e0"),
+ { .name = NULL },
+};
+
+/* Read configuration values */
+static void sm501_of_read_config(struct device *dev, struct device_node *np,
+const char *prefix,
+const struct dt_values *values,
+
[DO NOT MERGE v8 12/36] dt-bindings: pci: pci-sh7751: Add SH7751 PCI
Renesas SH7751 PCI Controller json-schema.
Signed-off-by: Yoshinori Sato
---
.../bindings/pci/renesas,sh7751-pci.yaml | 75 +++
1 file changed, 75 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
diff --git a/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
new file mode 100644
index ..3c3e8f9253c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/renesas,sh7751-pci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 PCI Host controller
+
+maintainers:
+ - Yoshinori Sato
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+const: renesas,sh7751-pci
+
+ reg:
+minItems: 2
+maxItems: 2
+
+ reg-names:
+items:
+ - const: PCI Controller
+ - const: Bus State Controller
+
+ interrupt-controller: true
+
+ renesas,bus-arbit-round-robin:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+ Set DMA bus arbitration to round robin.
+
+required:
+ - compatible
+ - reg
+ - "#interrupt-cells"
+ - interrupt-map
+ - interrupt-map-mask
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+pci@fe20 {
+compatible = "renesas,sh7751-pci";
+#address-cells = <3>;
+#size-cells = <2>;
+#interrupt-cells = <1>;
+interrupt-controller;
+device_type = "pci";
+bus-range = <0 0>;
+ranges = <0x0200 0 0xfd00 0xfd00 0 0x0100>,
+ <0x0100 0 0x 0xfe24 0 0x0004>;
+dma-ranges = <0x0300 0 0xab00 0xab00 0 0x0001>,
+ <0x0200 0 0x0c00 0x0c00 0 0x0400>,
+ <0x0200 0 0xd000 0xd000 0 0x0001>;
+reg = <0xfe20 0x0400>,
+ <0xff80 0x0100>;
+interrupt-map = <0x 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+<0x 0 0 2 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+<0x 0 0 3 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+<0x 0 0 4 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 1 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 2 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 3 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 4 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 1 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 2 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 3 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 4 &julianintc 6 IRQ_TYPE_LEVEL_LOW>;
+interrupt-map-mask = <0x1800 0 0 7>;
+};
--
2.39.2
[DO NOT MERGE v8 31/36] sh: Add IO DATA USL-5P dts
IO DATA DEVICE Inc. USL-5P devicetree.
Signed-off-by: Yoshinori Sato
---
arch/sh/boot/dts/usl-5p.dts | 85 +
1 file changed, 85 insertions(+)
create mode 100644 arch/sh/boot/dts/usl-5p.dts
diff --git a/arch/sh/boot/dts/usl-5p.dts b/arch/sh/boot/dts/usl-5p.dts
new file mode 100644
index ..bfbcb9e466bc
--- /dev/null
+++ b/arch/sh/boot/dts/usl-5p.dts
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the IO DATA DEVICE USL-5P
+ */
+
+/dts-v1/;
+
+#include "sh7751r.dtsi"
+
+/ {
+ model = "IO-DATA Device USL-5P";
+ compatible = "iodata,usl-5p", "renesas,sh7751r";
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ stdout-path = "serial0:9600n8";
+ };
+
+ memory@c00 {
+ device_type = "memory";
+ reg = <0x0c00 0x400>;
+ };
+
+ julianintc: interrupt-controller@b005 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xb005 0x01>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ /*
+* b7: Button
+* b6: Power switch
+* b5: Compact Flash
+* b4: ATA
+* b3: PCI-INTD
+* b2: PCI-INTC
+* b1: PCI-INTB
+* b0: PCI-INTA
+*/
+ renesas,enable-reg = <12 11 10 9 8 7 6 5>;
+ };
+
+ compact-flash@b440 {
+ compatible = "iodata,usl-5p-ata", "ata-generic";
+ reg = <0xb440 0x0e>, <0xb42c 2>;
+ reg-shift = <1>;
+ interrupt-parent = <&julianintc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&extal {
+ clock-frequency = <>;
+};
+
+&cpg {
+ renesas,mode = <5>;
+};
+
+&scif1 {
+ status = "okay";
+};
+
+&pcic {
+ ranges = <0x0200 0 0xfd00 0xfd00 0 0x0100>,
+<0x0100 0 0x 0xfe24 0 0x0004>;
+ dma-ranges = <0x0200 0 0x0c00 0x0c00 0 0x0400>,
+<0x0200 0 0xd000 0xd000 0 0x0004>;
+ interrupt-map = <0x 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 2 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 3 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 4 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 1 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 2 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 3 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 4 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 1 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 2 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 3 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 4 &julianintc 6 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map-mask = <0x1800 0 0 7>;
+ status = "okay";
+};
--
2.39.2
[DO NOT MERGE v8 21/36] dt-bindings: serial: renesas, scif: Add scif-sh7751.
Add Renesas SH7751 SCIF. Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index f3a3eb2831e9..7034594751bc 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -18,6 +18,7 @@ properties: - items: - enum: - renesas,scif-r7s72100 # RZ/A1H + - renesas,scif-sh7751 # SH7751 - const: renesas,scif # generic SCIF compatible UART - items: -- 2.39.2
[DO NOT MERGE v8 36/36] sh: j2_defconfig: update
I've changed some symbols related to DeviceTree, so let's take care of those changes. Signed-off-by: Yoshinori Sato --- arch/sh/configs/j2_defconfig | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/sh/configs/j2_defconfig b/arch/sh/configs/j2_defconfig index 2eb81ebe3888..cdc8ed244618 100644 --- a/arch/sh/configs/j2_defconfig +++ b/arch/sh/configs/j2_defconfig @@ -1,18 +1,15 @@ -CONFIG_SMP=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_CPU_SUBTYPE_J2=y CONFIG_MEMORY_START=0x1000 -CONFIG_MEMORY_SIZE=0x0400 CONFIG_CPU_BIG_ENDIAN=y -CONFIG_SH_DEVICE_TREE=y -CONFIG_SH_JCORE_SOC=y +CONFIG_SH_OF_BOARD=y CONFIG_HZ_100=y +CONFIG_SMP=y CONFIG_CMDLINE_OVERWRITE=y CONFIG_CMDLINE="console=ttyUL0 earlycon" -CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_NET=y CONFIG_PACKET=y @@ -21,7 +18,6 @@ CONFIG_INET=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_NETDEVICES=y -CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_UARTLITE=y CONFIG_SERIAL_UARTLITE_CONSOLE=y CONFIG_I2C=y @@ -30,8 +26,6 @@ CONFIG_SPI_JCORE=y CONFIG_WATCHDOG=y CONFIG_MMC=y CONFIG_MMC_SPI=y -CONFIG_CLKSRC_JCORE_PIT=y -CONFIG_JCORE_AIC=y CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_IOCHARSET="ascii" @@ -40,3 +34,4 @@ CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_UTF8=y +CONFIG_INIT_STACK_NONE=y -- 2.39.2
[DO NOT MERGE v8 15/36] clk: renesas: Add SH7750/7751 CPG Driver
Renesas SH7750 and SH7751 series CPG driver.
This driver supported frequency control and clock gating.
Signed-off-by: Yoshinori Sato
---
drivers/clk/renesas/Kconfig | 13 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/clk-sh7750.c | 480 +++
3 files changed, 491 insertions(+), 3 deletions(-)
create mode 100644 drivers/clk/renesas/clk-sh7750.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index d252150402e8..482efcb6e76e 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
config CLK_RENESAS
- bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
- default y if ARCH_RENESAS
+ bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS &&
!SUPERH
+ default y if ARCH_RENESAS || SUPERH
select CLK_EMEV2 if ARCH_EMEV2
select CLK_RZA1 if ARCH_R7S72100
select CLK_R7S9210 if ARCH_R7S9210
@@ -41,6 +41,9 @@ config CLK_RENESAS
select CLK_R9A08G045 if ARCH_R9A08G045
select CLK_R9A09G011 if ARCH_R9A09G011
select CLK_SH73A0 if ARCH_SH73A0
+ select CLK_SH7750 if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
+CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751 || \
+CPU_SUBTYPE_SH7751R
if CLK_RENESAS
@@ -198,7 +201,6 @@ config CLK_SH73A0
select CLK_RENESAS_CPG_MSTP
select CLK_RENESAS_DIV6
-
# Family
config CLK_RCAR_CPG_LIB
bool "CPG/MSSR library functions" if COMPILE_TEST
@@ -228,6 +230,11 @@ config CLK_RZG2L
bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if
COMPILE_TEST
select RESET_CONTROLLER
+config CLK_SH7750
+ bool "Renesas SH7750/7751 family clock support" if COMPILE_TEST
+ help
+ This is a driver for SH7750 / SH7751 CPG.
+
# Generic
config CLK_RENESAS_CPG_MSSR
bool "CPG/MSSR clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index f7e18679c3b8..ea0ffa8d59c4 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A08G045)+= r9a08g045-cpg.o
obj-$(CONFIG_CLK_R9A09G011)+= r9a09g011-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
+obj-$(CONFIG_CLK_SH7750) += clk-sh7750.o
# Family
obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
diff --git a/drivers/clk/renesas/clk-sh7750.c b/drivers/clk/renesas/clk-sh7750.c
new file mode 100644
index ..6f1580ce96c5
--- /dev/null
+++ b/drivers/clk/renesas/clk-sh7750.c
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7750/51 CPG driver
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* PCLK divide rate selector */
+static const struct clk_div_table pdiv_table[] = {
+ { .val = 0, .div = 2, },
+ { .val = 1, .div = 3, },
+ { .val = 2, .div = 4, },
+ { .val = 3, .div = 6, },
+ { .val = 4, .div = 8, },
+ { }
+};
+
+/* ICLK and BCLK divide rate selector */
+static const struct clk_div_table div_table[] = {
+ { .val = 0, .div = 1, },
+ { .val = 1, .div = 2, },
+ { .val = 2, .div = 3, },
+ { .val = 3, .div = 4, },
+ { .val = 4, .div = 6, },
+ { .val = 5, .div = 8, },
+ { }
+};
+
+struct cpg_priv {
+ struct clk_hw hw;
+ spinlock_t clklock;
+ void __iomem *frqcr;
+ void __iomem *clkstp00;
+ u32 mode;
+ u32 feat;
+};
+
+/* CPG feature flag */
+#define CPG_DIV1 BIT(0) /* 7750, 7750S, 7751 */
+#define MSTP_CR2 BIT(1) /* 7750S, 7750R, 7751, 7751R */
+#define MSTP_CLKSTPBIT(2) /* 7750R, 7751, 7751R */
+#define MSTP_CSTP2 BIT(3) /* 7751, 7751R */
+
+enum {
+ CPG_SH7750,
+ CPG_SH7750S,
+ CPG_SH7750R,
+ CPG_SH7751,
+ CPG_SH7751R,
+};
+
+static const u32 cpg_feature[] = {
+ [CPG_SH7750] = CPG_DIV1,
+ [CPG_SH7750S] = CPG_DIV1 | MSTP_CR2,
+ [CPG_SH7750R] = MSTP_CR2 | MSTP_CLKSTP,
+ [CPG_SH7751] = CPG_DIV1 | MSTP_CR2 | MSTP_CLKSTP | MSTP_CSTP2,
+ [CPG_SH7751R] = MSTP_CR2 | MSTP_CLKSTP | MSTP_CSTP2,
+};
+
+enum clk_type {CLK_DIV, CLK_STBCR, CLK_STBCR2, CLK_CLKSTP00};
+
+enum {
+ FRQCR = 0,
+ STBCR = 4,
+ WTCNT = 8,
+ WTCSR = 12,
+ STBCR2 = 16,
+ CLKSTP00 = 0,
+ CLKSTPCLR00 = 8,
+};
+
+static struct cpg_priv *cpg_data;
+
+#define to_priv(_hw) container_of(_hw, struct cpg_priv, hw)
+
+#define FRQCR_PLL1EN BIT(10)
+static const unsigned int pll1mult[] = { 12, 12, 6, 12, 6, 12, 1};
+
+static unsigned long pll_recalc_rate(struct clk_hw *hw,
+
[DO NOT MERGE v8 02/36] sh: Kconfig unified OF supported targets.
Targets that support OF should be treated as one board. Signed-off-by: Yoshinori Sato --- arch/sh/Kconfig| 1 + arch/sh/boards/Kconfig | 23 +-- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 5e6a3ead51fb..d6704c57f9dc 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -711,6 +711,7 @@ config ROMIMAGE_MMCIF choice prompt "Kernel command line" default CMDLINE_OVERWRITE + depends on !OF || USE_BUILTIN_DTB help Setting this option allows the kernel command line arguments to be set. diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 109bec4dad94..46387fd040ad 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -19,16 +19,9 @@ config SH_DEVICE_TREE select TIMER_OF select COMMON_CLK select GENERIC_CALIBRATE_DELAY - -config SH_JCORE_SOC - bool "J-Core SoC" - select SH_DEVICE_TREE - select CLKSRC_JCORE_PIT - select JCORE_AIC - depends on CPU_J2 - help - Select this option to include drivers core components of the - J-Core SoC, including interrupt controllers and timers. + select GENERIC_IRQ_CHIP + select SYS_SUPPORTS_PCI + select GENERIC_PCI_IOMAP if PCI config SH_SOLUTION_ENGINE bool "SolutionEngine" @@ -293,6 +286,7 @@ config SH_LANDISK bool "LANDISK" depends on CPU_SUBTYPE_SH7751R select HAVE_PCI + select SYS_SUPPORTS_PCI help I-O DATA DEVICE, INC. "LANDISK Series" support. @@ -369,6 +363,15 @@ config SH_APSH4AD0A help Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. +config SH_OF_BOARD + bool "General Open Firmware boards" + select SH_DEVICE_TREE + select CLKSRC_JCORE_PIT if CPU_J2 + select JCORE_AIC if CPU_J2 + select HAVE_PCI if CPU_SUBTYPE_SH7751R + help + This board means general OF supported targets. + source "arch/sh/boards/mach-r2d/Kconfig" source "arch/sh/boards/mach-highlander/Kconfig" source "arch/sh/boards/mach-sdk7780/Kconfig" -- 2.39.2
[DO NOT MERGE v8 11/36] pci: pci-sh7751: Add SH7751 PCI driver
Renesas SH7751 CPU Internal PCI Controller driver. Signed-off-by: Yoshinori Sato --- drivers/pci/controller/Kconfig | 9 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pci-sh7751.c | 335 3 files changed, 345 insertions(+) create mode 100644 drivers/pci/controller/pci-sh7751.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index e534c02ee34f..a2fd917a2e03 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -353,6 +353,15 @@ config PCIE_XILINX_CPM Say 'Y' here if you want kernel support for the Xilinx Versal CPM host bridge. +config PCI_SH7751 + bool "Renesas SH7751 PCI controller" + depends on OF + depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST + select PCI_HOST_COMMON + help + Say 'Y' here if you want kernel to support the Renesas SH7751 PCI + Host Bridge driver. + source "drivers/pci/controller/cadence/Kconfig" source "drivers/pci/controller/dwc/Kconfig" source "drivers/pci/controller/mobiveil/Kconfig" diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index f2b19e6174af..aa97e5d74e58 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o +obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ diff --git a/drivers/pci/controller/pci-sh7751.c b/drivers/pci/controller/pci-sh7751.c new file mode 100644 index ..73ccc14800f7 --- /dev/null +++ b/drivers/pci/controller/pci-sh7751.c @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SH7751 PCI driver + * Copyright (C) 2023 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PCICR and PCICLKCR write enable magic key */ +#define PCIC_WE_KEY(0xa5 << 24) + +/* PCIC registers */ +/* 0x - 0x00ff mapped to PCI device configuration space */ +#define PCIC_PCICR 0x100 /* PCI Control Register */ +#define PCIC_PCICR_TRSBBIT(9) /* Target Read Single */ +#define PCIC_PCICR_BSWPBIT(8) /* Target Byte Swap */ +#define PCIC_PCICR_PLUPBIT(7) /* Enable PCI Pullup */ +#define PCIC_PCICR_ARBMBIT(6) /* PCI Arbitration Mode */ +#define PCIC_PCICR_MD10BIT(5) /* MD10 status */ +#define PCIC_PCICR_MD9 BIT(4) /* MD9 status */ +#define PCIC_PCICR_SERRBIT(3) /* SERR output assert */ +#define PCIC_PCICR_INTABIT(2) /* INTA output assert */ +#define PCIC_PCICR_PRSTBIT(1) /* PCI Reset Assert */ +#define PCIC_PCICR_CFINBIT(0) /* Central Fun. Init Done */ + +#define PCIC_PCILSR0 0x104 /* PCI Local Space Register0 */ +#define PCIC_PCILSR1 0x108 /* PCI Local Space Register1 */ +#define PCIC_PCILAR0 0x10c /* PCI Local Addr Register1 */ +#define PCIC_PCILAR1 0x110 /* PCI Local Addr Register1 */ +#define PCIC_PCIINT0x114 /* PCI Interrupt Register */ +#define PCIC_PCIINTM 0x118 /* PCI Interrupt Mask */ +#define PCIC_PCIALR0x11c /* Error Address Register */ +#define PCIC_PCICLR0x120 /* Error Command/Data */ +#define PCIC_PCIAINT 0x130 /* Arbiter Interrupt Register */ +#define PCIC_PCIAINTM 0x134 /* Arbiter Int. Mask Register */ +#define PCIC_PCIBMLR 0x138 /* Error Bus Master Register */ +#define PCIC_PCIDMABT 0x140 /* DMA Transfer Arb. Register */ +#define PCIC_PCIPAR0x1c0 /* PIO Address Register */ +#define PCIC_PCIMBR0x1c4 /* Memory Base Address */ +#define PCIC_PCIIOBR 0x1c8 /* I/O Base Address Register */ + +#define PCIC_PCIPINT 0x1cc /* Power Mgmnt Int. Register */ +#define PCIC_PCIPINT_D3BIT(1) /* D3 Pwr Mgmt. Interrupt */ +#define PCIC_PCIPINT_D0BIT(0) /* D0 Pwr Mgmt. Interrupt */ + +#define PCIC_PCIPINTM 0x1d0 /* Power Mgmnt Mask Register */ +#define PCIC_PCICLKR 0x1d4 /* Clock Ctrl. Register */ +#define PCIC_PCIBCR1 0x1e0 /* Memory BCR1 Register */ +#define PCIC_PCIBCR2 0x1e4 /* Memory BCR2 Register */ +#define PCIC_PCIWCR1 0x1e8 /* Wait Control 1 Register */ +#define PCIC_PCIWCR2 0x1ec /* Wait Control 2 Register */ +#define PCIC_PCIWCR3 0x1f0 /* Wait Control 3 Register */ +#define PCIC_PCIMCR0x1f4 /* Memory Control Register */ +#define
[DO NOT MERGE v8 34/36] sh: RTS7751R2D Plus OF defconfig
Signed-off-by: Yoshinori Sato --- arch/sh/configs/rts7751r2dplus-of_defconfig | 77 + 1 file changed, 77 insertions(+) create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig diff --git a/arch/sh/configs/rts7751r2dplus-of_defconfig b/arch/sh/configs/rts7751r2dplus-of_defconfig new file mode 100644 index ..e85523a3c821 --- /dev/null +++ b/arch/sh/configs/rts7751r2dplus-of_defconfig @@ -0,0 +1,77 @@ +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_PROFILING=y +CONFIG_CPU_SUBTYPE_SH7751R=y +CONFIG_MEMORY_START=0x0c00 +CONFIG_SH_OF_BOARD=y +CONFIG_HEARTBEAT=y +CONFIG_ZERO_PAGE_OFFSET=0x0001 +CONFIG_CMDLINE_BOOTLOADER=y +CONFIG_MODULES=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IPV6 is not set +CONFIG_PCI=y +CONFIG_HOTPLUG_PCI=y +CONFIG_PCI_SH7751=y +CONFIG_UEVENT_HELPER=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ATA=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_NETDEVICES=y +CONFIG_8139TOO=y +# CONFIG_8139TOO_PIO is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SH_SCI=y +CONFIG_HW_RANDOM=y +CONFIG_SPI=y +CONFIG_SPI_SH_SCI=y +CONFIG_MFD_SM501=y +CONFIG_FB=y +CONFIG_FB_SH_MOBILE_LCDC=m +CONFIG_FB_SM501=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_SUPERH_MONO is not set +# CONFIG_LOGO_SUPERH_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_YMFPCI=m +CONFIG_HID_GYRATION=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_R9701=y +CONFIG_RENESAS_SH7751_INTC=y +CONFIG_RENESAS_SH7751IRL_INTC=y +CONFIG_EXT2_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_MINIX_FS=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_CRC_T10DIF=y +CONFIG_DEBUG_FS=y -- 2.39.2
[DO NOT MERGE v8 07/36] sh: Fix COMMON_CLK support in CONFIG_OF=y.
Initialize the clock and timer using the COMMON_CLK procedure.
sh's earlytimer mechanism doesn't work properly in OF,
so timer initialization is delayed.
If CONFIG_OF=y, perform the general timer initialization procedure.
Signed-off-by: Yoshinori Sato
---
arch/sh/boards/of-generic.c | 28
arch/sh/kernel/time.c | 12
2 files changed, 16 insertions(+), 24 deletions(-)
diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
index cc88cb8908cc..64f80d2878b1 100644
--- a/arch/sh/boards/of-generic.c
+++ b/arch/sh/boards/of-generic.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
@@ -100,16 +101,7 @@ static void sh_of_smp_probe(void)
#endif
-static void noop(void)
-{
-}
-
-static int noopi(void)
-{
- return 0;
-}
-
-static void __init sh_of_mem_reserve(void)
+static void __init sh_of_mem_init(void)
{
early_init_fdt_reserve_self();
early_init_fdt_scan_reserved_mem();
@@ -142,25 +134,13 @@ static void __init sh_of_init_irq(void)
irqchip_init();
}
-static int __init sh_of_clk_init(void)
-{
-#ifdef CONFIG_COMMON_CLK
- /* Disabled pending move to COMMON_CLK framework. */
- pr_info("SH generic board support: scanning for clk providers\n");
- of_clk_init(NULL);
-#endif
- return 0;
-}
-
static struct sh_machine_vector __initmv sh_of_generic_mv = {
.mv_setup = sh_of_setup,
.mv_name= "devicetree", /* replaced by DT root's model */
.mv_irq_demux = sh_of_irq_demux,
.mv_init_irq= sh_of_init_irq,
- .mv_clk_init= sh_of_clk_init,
- .mv_mode_pins = noopi,
- .mv_mem_init= noop,
- .mv_mem_reserve = sh_of_mem_reserve,
+ .mv_mode_pins = generic_mode_pins,
+ .mv_mem_init= sh_of_mem_init,
};
struct sh_clk_ops;
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
index 821a09cbd605..ce5b7c2f8628 100644
--- a/arch/sh/kernel/time.c
+++ b/arch/sh/kernel/time.c
@@ -19,7 +19,9 @@
#include
#include
#include
+#include
+#ifndef CONFIG_SH_DEVICE_TREE
static void __init sh_late_time_init(void)
{
/*
@@ -43,3 +45,13 @@ void __init time_init(void)
late_time_init = sh_late_time_init;
}
+#else
+/* CONFIG_SH_DEVICE_TREE */
+void __init time_init(void)
+{
+ pr_info("SH generic board support: scanning for clk providers\n");
+
+ of_clk_init(NULL);
+ timer_probe();
+}
+#endif
--
2.39.2
[DO NOT MERGE v8 30/36] sh: Add IO DATA LANDISK dts
IO DATA DEVICE Inc. LANDISK HDL-U devicetree.
Signed-off-by: Yoshinori Sato
---
arch/sh/boot/dts/landisk.dts | 77
1 file changed, 77 insertions(+)
create mode 100644 arch/sh/boot/dts/landisk.dts
diff --git a/arch/sh/boot/dts/landisk.dts b/arch/sh/boot/dts/landisk.dts
new file mode 100644
index ..1ac1f532947b
--- /dev/null
+++ b/arch/sh/boot/dts/landisk.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the IO DATA DEVICE LANDISK
+ */
+
+/dts-v1/;
+
+#include "sh7751r.dtsi"
+
+/ {
+ model = "IO DATA Device LANDISK";
+ compatible = "iodata,landisk", "renesas,sh7751r";
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ stdout-path = "serial0:9600n8";
+ };
+
+ memory@c00 {
+ device_type = "memory";
+ reg = <0x0c00 0x400>;
+ };
+
+ julianintc: interrupt-controller@b005 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xb005 0x01>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ /*
+* b7: Not assigned
+* b6: Power switch
+* b5: Not assigned
+* b4: Not assigned
+* b3: PCI-INTD
+* b2: PCI-INTC
+* b1: PCI-INTB
+* b0: PCI-INTA
+*/
+ renesas,enable-reg = <15 11 15 15 8 7 6 5>;
+ };
+};
+
+&extal {
+ clock-frequency = <>;
+};
+
+&cpg {
+ renesas,mode = <5>;
+};
+
+&scif1 {
+ status = "okay";
+};
+
+&pcic {
+ ranges = <0x0200 0 0xfd00 0xfd00 0 0x0100>,
+<0x0100 0 0x 0xfe24 0 0x0004>;
+ dma-ranges = <0x0200 0 0x0c00 0x0c00 0 0x0400>,
+<0x0200 0 0xd000 0xd000 0 0x0004>;
+ interrupt-map = <0x 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 2 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 3 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 4 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 1 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 2 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 3 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 4 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 1 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 2 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 3 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 4 &julianintc 6 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map-mask = <0x1800 0 0 7>;
+ status = "okay";
+};
--
2.39.2
[DO NOT MERGE v8 28/36] sh: SH7751R SoC Internal peripheral definition dtsi.
SH7751R internal peripherals device tree.
Signed-off-by: Yoshinori Sato
---
arch/sh/boot/dts/sh7751r.dtsi | 105 ++
1 file changed, 105 insertions(+)
create mode 100644 arch/sh/boot/dts/sh7751r.dtsi
diff --git a/arch/sh/boot/dts/sh7751r.dtsi b/arch/sh/boot/dts/sh7751r.dtsi
new file mode 100644
index ..61b2af5bebde
--- /dev/null
+++ b/arch/sh/boot/dts/sh7751r.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the SH7751R SoC
+ */
+
+#include
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "renesas,sh4", "renesas,sh2";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&cpg SH7750_CPG_ICK>;
+ clock-names = "ick";
+ icache-size = <16384>;
+ icache-line-size = <32>;
+ dcache-size = <32768>;
+ dcache-line-size = <32>;
+ };
+ };
+
+ extal: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "extal";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&shintc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cpg: clock-controller@ffc0 {
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+ compatible = "renesas,sh7751r-cpg";
+ clocks = <&extal>;
+ clock-names = "extal";
+ reg = <0xffc0 20>, <0xfe0a 16>;
+ reg-names = "FRQCR", "CLKSTP00";
+ renesas,mode = <0>;
+ };
+
+ shintc: interrupt-controller@ffd0 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <0xffd0 20>, <0xfe08 128>;
+ reg-names = "ICR", "INTPRI00";
+ };
+
+ /* sci0 is rarely used, so it is not defined here. */
+ scif1: serial@ffe8 {
+ compatible = "renesas,scif-sh7751", "renesas,scif";
+ reg = <0xffe8 0x100>;
+ interrupts = <0x700>,
+<0x720>,
+<0x760>,
+<0x740>;
+ interrupt-names = "eri", "rxi", "txi", "bri";
+ clocks = <&cpg SH7750_MSTP_SCIF>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ /* Normally ch0 and ch1 are used, so we will define ch0 to ch2
here. */
+ tmu0: timer@ffd8 {
+ compatible = "renesas,tmu-sh7750", "renesas,tmu";
+ reg = <0xffd8 12>;
+ interrupts = <0x400>,
+<0x420>,
+<0x440>,
+<0x460>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
+ clocks = <&cpg SH7750_MSTP_TMU012>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ #renesas,channels = <3>;
+ };
+
+ pcic: pci@fe20 {
+ compatible = "renesas,sh7751-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ bus-range = <0 0>;
+ reg = <0xfe20 0x0400>,
+ <0xff80 0x0100>;
+ status = "disabled";
+ };
+ };
+};
--
2.39.2
[DO NOT MERGE v8 33/36] sh: Add dtbs target support.
Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven --- arch/sh/boot/dts/Makefile | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/sh/boot/dts/Makefile b/arch/sh/boot/dts/Makefile index 4a6dec9714a9..e6b93360c213 100644 --- a/arch/sh/boot/dts/Makefile +++ b/arch/sh/boot/dts/Makefile @@ -1,2 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_USE_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOURCE)) + +dtb-$(CONFIG_CPU_J2) += j2_mimas_v2.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += landisk.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += rts7751r2dplus.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += usl-5p.dtb -- 2.39.2
[DO NOT MERGE v8 26/36] dt-bindings: ata: ata-generic: Add new targets
Added new ata-generic target. - iodata,usl-5p-ata - renesas,rts7751r2d-ata Each boards have simple IDE Interface. Use ATA generic driver. Signed-off-by: Yoshinori Sato --- Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/ata-generic.yaml b/Documentation/devicetree/bindings/ata/ata-generic.yaml index 0697927f3d7e..1025b3b351d0 100644 --- a/Documentation/devicetree/bindings/ata/ata-generic.yaml +++ b/Documentation/devicetree/bindings/ata/ata-generic.yaml @@ -18,6 +18,8 @@ properties: - enum: - arm,vexpress-cf - fsl,mpc8349emitx-pata + - iodata,usl-5p-ata + - renesas,rts7751r2d-ata - const: ata-generic reg: -- 2.39.2
[DO NOT MERGE v8 35/36] sh: LANDISK OF defconfig
Signed-off-by: Yoshinori Sato --- arch/sh/configs/landisk-of_defconfig | 102 +++ 1 file changed, 102 insertions(+) create mode 100644 arch/sh/configs/landisk-of_defconfig diff --git a/arch/sh/configs/landisk-of_defconfig b/arch/sh/configs/landisk-of_defconfig new file mode 100644 index ..580fbaabc557 --- /dev/null +++ b/arch/sh/configs/landisk-of_defconfig @@ -0,0 +1,102 @@ +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_KEXEC=y +CONFIG_CPU_SUBTYPE_SH7751R=y +CONFIG_MEMORY_START=0x0c00 +CONFIG_SH_OF_BOARD=y +CONFIG_HEARTBEAT=y +CONFIG_CMDLINE_BOOTLOADER=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +CONFIG_ATALK=m +CONFIG_PCI=y +CONFIG_PCI_SH7751=y +CONFIG_PCCARD=y +CONFIG_YENTA=y +CONFIG_UEVENT_HELPER=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ATA=y +CONFIG_PATA_ARTOP=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_ATA_GENERIC=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_NETDEVICES=y +CONFIG_TUN=m +CONFIG_8139CP=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_HW_RANDOM=y +CONFIG_SOUND=m +CONFIG_HID_A4TECH=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GYRATION=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SUNPLUS=m +CONFIG_USB_HID=m +CONFIG_USB=y +CONFIG_USB_MON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_SISUSBVGA=m +CONFIG_RENESAS_SH7751_INTC=y +CONFIG_RENESAS_SH7751IRL_INTC=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_REISERFS_FS=y +CONFIG_ISO9660_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_ROMFS_FS=y +CONFIG_UFS_FS=m +CONFIG_NFS_FS=m +CONFIG_NFSD=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_INIT_STACK_NONE=y +CONFIG_CRC_T10DIF=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_FTRACE is not set +CONFIG_SH_STANDARD_BIOS=y -- 2.39.2
[DO NOT MERGE v8 22/36] dt-bindings: display: smi, sm501: SMI SM501 binding json-schema
Signed-off-by: Yoshinori Sato --- .../bindings/display/smi,sm501.yaml | 443 ++ 1 file changed, 443 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/smi,sm501.yaml diff --git a/Documentation/devicetree/bindings/display/smi,sm501.yaml b/Documentation/devicetree/bindings/display/smi,sm501.yaml new file mode 100644 index ..c3ab0f08a894 --- /dev/null +++ b/Documentation/devicetree/bindings/display/smi,sm501.yaml @@ -0,0 +1,443 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/smi,sm501.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Motion SM501 Mobile Multimedia Companion Chip + +maintainers: + - Yoshinori Sato + +description: + Silicon Motion Inc, SM501 Companion Chip. + +definitions: + fb-flag: +$ref: /schemas/types.yaml#/definitions/string-array +description: Display initialize flags. +items: + anyOf: +- const: use-init-done +- const: disable-at-exit +- const: use-hwcursor +- const: use-hwaccel +- const: panel-no-fpen +- const: panel-no-vbiasen +- const: panel-inv-fpen +- const: panel-inv-vbiasen +maxItems: 8 + +properties: + compatible: +const: + smi,sm501 + + reg: +maxItems: 2 +description: + First entry - System Configuration registers + Second entry - IO space (Display Controller register) + + interrupts: +description: SM501 interrupt to the cpu should be described here. + + clocks: +minItems: 2 + + clock-names: +items: + - const: mclk + - const: m1xclk + + mode: +$ref: /schemas/types.yaml#/definitions/string +description: Select a video mode + + edid: +$ref: /schemas/types.yaml#/definitions/uint8-array +description: + Verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + smi,little-endian: +$ref: /schemas/types.yaml#/definitions/flag +description: available on big endian systems, to set different foreign endian. + smi,big-endian: +$ref: /schemas/types.yaml#/definitions/flag +description: available on little endian systems, to set different foreign endian. + + smi,swap-fb-endian: +$ref: /schemas/types.yaml#/definitions/flag +description: swap framebuffer byteorder. + + route-crt-panel: +$ref: /schemas/types.yaml#/definitions/flag +description: Panel output merge to CRT. + + crt: +type: object +description: CRT output control +properties: + smi,flags: +$ref: "#/definitions/fb-flag" + + bpp: +$ref: /schemas/types.yaml#/definitions/uint32 +description: Color depth + + panel: +type: object +description: Panel output control +properties: + smi,flags: +$ref: "#/definitions/fb-flag" + + bpp: +$ref: /schemas/types.yaml#/definitions/uint32 +description: Color depth + + smi,devices: +$ref: /schemas/types.yaml#/definitions/string-array +description: Select SM501 device functions. +items: + anyOf: +- const: usb-host +- const: usb-slave +- const: ssp0 +- const: ssp1 +- const: uart0 +- const: uart1 +- const: fbaccel +- const: ac97 +- const: i2s +minItems: 1 +maxItems: 9 + + smi,misc-timing-ex: +$ref: /schemas/types.yaml#/definitions/string +description: Miscellaneous Timing - Extend bus holding time. +enum: + - none + - "16" + - "32" + - "48" + - "64" + - "80" + - "96" + - "112" + - "128" + - "144" + - "160" + - "176" + - "192" + - "208" + - "224" + - "240" + + smi,misc-timing-xc: +$ref: /schemas/types.yaml#/definitions/string +description: Miscellaneous Timing - Xscale clock input select. +enum: + - internal-pll + - hclk + - gpio30 + + smi,misc-timing-usb-current: +$ref: /schemas/types.yaml#/definitions/string +description: Miscellaneous Timing - USB host current detection. +enum: + - disable + - enable + + smi,misc-timing-ssm1: +$ref: /schemas/types.yaml#/definitions/string +description: Miscellaneous Timing - System SDRAM Clock Select for PW Mode 1. +enum: + - "288" + - divider + + smi,misc-timing-sm1: +$ref: /schemas/types.yaml#/definitions/string +description: Miscellaneous Timing - SDRAM clock divider for PW mode 1. +enum: + - "1" + - "2" + - "3" + - "4" + - "6" + - "8" + - "12" + - &
[DO NOT MERGE v8 16/36] irqchip: Add SH7751 INTC driver
Renesas SH7751 Internal interrupt controller driver.
Signed-off-by: Yoshinori Sato
---
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-renesas-sh7751.c | 282 +++
3 files changed, 291 insertions(+)
create mode 100644 drivers/irqchip/irq-renesas-sh7751.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 14464716bacb..f45a229963d4 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -715,4 +715,12 @@ config SUNPLUS_SP7021_INTC
chained controller, routing all interrupt source in P-Chip to
the primary controller on C-Chip.
+config RENESAS_SH7751_INTC
+ bool "Renesas SH7751 Interrupt Controller"
+ depends on SH_DEVICE_TREE || COMPILE_TEST
+ select IRQ_DOMAIN_HIERARCHY
+ help
+ Support for the Renesas SH7751 On-chip interrupt controller.
+ And external interrupt encoder for some targets.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d9dc3d99aaa8..7bde45f05a1e 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -124,3 +124,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o
obj-$(CONFIG_APPLE_AIC)+= irq-apple-aic.o
obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
+obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
diff --git a/drivers/irqchip/irq-renesas-sh7751.c
b/drivers/irqchip/irq-renesas-sh7751.c
new file mode 100644
index ..91d6dc3ed04c
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-sh7751.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7751 interrupt controller driver
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct ipr {
+ u16 off;
+ u16 idx;
+};
+
+struct sh7751_intc_priv {
+ const struct ipr *iprmap;
+ void __iomem *base;
+ void __iomem *intpri00;
+ bool irlm;
+};
+
+enum {
+ R_ICR = 0x00,
+ R_IPR = 0x04,
+ R_INTPRI00= 0x00,
+ R_INTREQ00= 0x20,
+ R_INTMSK00= 0x40,
+ R_INTMSKCLR00 = 0x60,
+};
+
+#define ICR_IRLM BIT(7)
+
+/*
+ * SH7751 IRQ mapping
+ * IRQ16 - 63: Group0 - IPRA to IPRD
+ * IRQ16 - 31: external IRL input (ICR.IRLM is 0)
+ * IRQ80 - 92: Group1 - INTPRI00
+ */
+#define IRQ_START 16
+#define MAX_IRL(IRQ_START + NR_IRL)
+#define GRP0_IRQ_END 63
+#define GRP1_IRQ_START 80
+#define IRQ_END92
+
+#define NR_IPRMAP0 (GRP0_IRQ_END - IRQ_START + 1)
+#define NR_IPRMAP1 (IRQ_END - GRP1_IRQ_START)
+#define IPR_PRI_MASK 0x000f
+
+#define IPRA 0
+#define IPRB 4
+#define IPRC 8
+#define IPRD 12
+#define INTPRI00 256
+#define IPR_B1212
+#define IPR_B8 8
+#define IPR_B4 4
+#define IPR_B0 0
+
+/* SH7751 EVT to IPR mapping table */
+static const struct ipr sh7751_iprmap[] = {
+ [evt2irq(0x240)] = {IPRD, IPR_B12}, /* IRL0 (ICR.IRLM=1) */
+ [evt2irq(0x2a0)] = {IPRD, IPR_B8}, /* IRL1 (ICR.IRLM=1) */
+ [evt2irq(0x300)] = {IPRD, IPR_B4}, /* IRL2 (ICR.IRLM=1) */
+ [evt2irq(0x360)] = {IPRD, IPR_B0}, /* IRL3 (ICR.IRLM=1) */
+ [evt2irq(0x400)] = {IPRA, IPR_B12}, /* TMU0 */
+ [evt2irq(0x420)] = {IPRA, IPR_B8}, /* TMU1 */
+ [evt2irq(0x440)] = {IPRA, IPR_B4}, /* TMU2 TNUI */
+ [evt2irq(0x460)] = {IPRA, IPR_B4}, /* TMU2 TICPI */
+ [evt2irq(0x480)] = {IPRA, IPR_B0}, /* RTC ATI */
+ [evt2irq(0x4a0)] = {IPRA, IPR_B0}, /* RTC PRI */
+ [evt2irq(0x4c0)] = {IPRA, IPR_B0}, /* RTC CUI */
+ [evt2irq(0x4e0)] = {IPRB, IPR_B4}, /* SCI ERI */
+ [evt2irq(0x500)] = {IPRB, IPR_B4}, /* SCI RXI */
+ [evt2irq(0x520)] = {IPRB, IPR_B4}, /* SCI TXI */
+ [evt2irq(0x540)] = {IPRB, IPR_B4}, /* SCI TEI */
+ [evt2irq(0x560)] = {IPRB, IPR_B12}, /* WDT */
+ [evt2irq(0x580)] = {IPRB, IPR_B8}, /* REF RCMI */
+ [evt2irq(0x5a0)] = {IPRB, IPR_B4}, /* REF ROVI */
+ [evt2irq(0x600)] = {IPRC, IPR_B0}, /* H-UDI */
+ [evt2irq(0x620)] = {IPRC, IPR_B12}, /* GPIO */
+ [evt2irq(0x640)] = {IPRC, IPR_B8}, /* DMAC DMTE0 */
+ [evt2irq(0x660)] = {IPRC, IPR_B8}, /* DMAC DMTE1 */
+ [evt2irq(0x680)] = {IPRC, IPR_B8}, /* DMAC DMTE2 */
+ [evt2irq(0x6a0)] = {IPRC, IPR_B8}, /* DMAC DMTE3 */
+ [evt2irq(0x6c0)] = {IPRC, IPR_B8}, /* DMAC DMAE */
+ [evt2irq(0x700)] = {IPRC, IPR_B4}, /* SCIF ERI */
+ [evt2irq(0x720)] = {IPRC, IPR_B4}, /* SCIF RXI */
+ [evt2irq(0x740)] = {IPRC, IPR_B4},
[DO NOT MERGE v8 20/36] serial: sh-sci: fix SH4 OF support.
- Separated RZ's earlycon initialization from normal SCIF.
- fix earlyprintk hung (NULL pointer reference).
- fix SERIAL_SH_SCI_EARLYCON enablement
Signed-off-by: Yoshinori Sato
Reviewed-by: Geert Uytterhoeven
---
drivers/tty/serial/Kconfig | 2 +-
drivers/tty/serial/sh-sci.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 4fdd7857ef4d..eeb22b582470 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -664,7 +664,7 @@ config SERIAL_SH_SCI_EARLYCON
depends on SERIAL_SH_SCI=y
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
- default ARCH_RENESAS
+ default ARCH_RENESAS || SUPERH
config SERIAL_SH_SCI_DMA
bool "DMA support" if EXPERT
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index f738980a8b2c..068f483401e3 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2723,7 +2723,7 @@ static int sci_remap_port(struct uart_port *port)
if (port->membase)
return 0;
- if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
+ if (dev_of_node(port->dev) || (port->flags & UPF_IOREMAP)) {
port->membase = ioremap(port->mapbase, sport->reg_size);
if (unlikely(!port->membase)) {
dev_err(port->dev, "can't remap port#%d\n", port->line);
@@ -3551,8 +3551,8 @@ static int __init hscif_early_console_setup(struct
earlycon_device *device,
OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044",
rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r7s9210",
rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r9a07g044",
rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
--
2.39.2
[DO NOT MERGE v8 27/36] dt-bindings: soc: renesas: sh: Add SH7751 based target
Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/renesas/sh.yaml | 27 +++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/sh.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/sh.yaml b/Documentation/devicetree/bindings/soc/renesas/sh.yaml new file mode 100644 index ..9e0f69a8ee6a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH Platform + +maintainers: + - Yoshinori Sato + +properties: + $nodename: +const: '/' + compatible: +oneOf: + - description: SH7751R based platform +items: + - enum: + - renesas,rts7751r2d # Renesas SH4 2D graphics board + - iodata,landisk # LANDISK HDL-U + - iodata,usl-5p # USL-5P + - const: renesas,sh7751r + +additionalProperties: true + +... -- 2.39.2
[DO NOT MERGE v8 13/36] dt-bindings: clock: sh7750-cpg: Add renesas, sh7750-cpg header.
SH7750 CPG Clock output define.
Signed-off-by: Yoshinori Sato
---
.../bindings/clock/renesas,sh7750-cpg.yaml| 107 ++
include/dt-bindings/clock/sh7750-cpg.h| 26 +
2 files changed, 133 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
create mode 100644 include/dt-bindings/clock/sh7750-cpg.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
new file mode 100644
index ..0cdcab6fb4bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7750/7751 Clock Pulse Generator (CPG)
+
+maintainers:
+ - Yoshinori Sato
+
+description:
+ The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
+ includes PLLs, and variable ratio dividers.
+
+ The CPG may also provide a Clock Domain for SoC devices, in combination with
+ the CPG Module Stop (MSTP) Clocks.
+
+properties:
+ compatible:
+enum:
+ - renesas,sh7750-cpg # SH7750
+ - renesas,sh7750s-cpg# SH775S
+ - renesas,sh7750r-cpg# SH7750R
+ - renesas,sh7751-cpg # SH7751
+ - renesas,sh7751r-cpg# SH7751R
+
+ reg:
+minItems: 1
+maxItems: 2
+
+ reg-names: true
+
+ clocks:
+maxItems: 1
+
+ clock-names:
+const: extal
+
+ '#clock-cells':
+const: 1
+
+ renesas,mode:
+description: Board-specific settings of the MD[0-2] pins on SoC
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 0
+maximum: 6
+
+ '#power-domain-cells':
+const: 0
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - renesas,sh7750-cpg
+ - renesas,sh7750s-cpg
+then:
+ properties:
+reg:
+ maxItems: 1
+reg-names:
+ items:
+- const: FRQCR
+
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - renesas,sh7750r-cpg
+ - renesas,sh7751-cpg
+ - renesas,sh7751r-cpg
+then:
+ properties:
+reg:
+ minItems: 2
+reg-names:
+ items:
+- const: FRQCR
+- const: CLKSTP00
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+cpg: clock-controller@ffc0 {
+compatible = "renesas,sh7751r-cpg";
+reg = <0xffc0 20>, <0xfe0a 16>;
+reg-names = "FRQCR", "CLKSTP00";
+clocks = <&extal>;
+clock-names = "extal";
+renesas,mode = <0>;
+#clock-cells = <1>;
+#power-domain-cells = <0>;
+};
diff --git a/include/dt-bindings/clock/sh7750-cpg.h
b/include/dt-bindings/clock/sh7750-cpg.h
new file mode 100644
index ..ec267be91adf
--- /dev/null
+++ b/include/dt-bindings/clock/sh7750-cpg.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SH7750_H__
+#define __DT_BINDINGS_CLOCK_SH7750_H__
+
+#define SH7750_CPG_PLLOUT 0
+
+#define SH7750_CPG_PCK 1
+#define SH7750_CPG_BCK 2
+#define SH7750_CPG_ICK 3
+
+#define SH7750_MSTP_SCI4
+#define SH7750_MSTP_RTC5
+#define SH7750_MSTP_TMU012 6
+#define SH7750_MSTP_SCIF 7
+#define SH7750_MSTP_DMAC 8
+#define SH7750_MSTP_UBC9
+#define SH7750_MSTP_SQ 10
+#define SH7750_CSTP_INTC 11
+#define SH7750_CSTP_TMU34 12
+#define SH7750_CSTP_PCIC 13
+
+#endif
--
2.39.2
[DO NOT MERGE v8 24/36] dt-binding: sh: cpus: Add SH CPUs json-schema
Renesas SH series and compatible ISA CPUs.
Signed-off-by: Yoshinori Sato
---
.../devicetree/bindings/sh/cpus.yaml | 63 +++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml
diff --git a/Documentation/devicetree/bindings/sh/cpus.yaml
b/Documentation/devicetree/bindings/sh/cpus.yaml
new file mode 100644
index ..e652b8414ae8
--- /dev/null
+++ b/Documentation/devicetree/bindings/sh/cpus.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sh/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SuperH CPUs
+
+maintainers:
+ - Yoshinori Sato
+
+description: |+
+ Definition of CPU core with Renesas SuperH and compatible instruction set.
+
+properties:
+ compatible:
+oneOf:
+ - items:
+ - enum:
+ - renesas,sh2a
+ - renesas,sh3
+ - renesas,sh4
+ - renesas,sh4a
+ - jcore,j2
+ - const: renesas,sh2
+ - const: renesas,sh2
+
+ clocks:
+maxItems: 1
+
+ reg:
+maxItems: 1
+
+ device_type:
+const: cpu
+
+required:
+ - compatible
+ - reg
+ - device_type
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+cpus {
+#address-cells = <1>;
+#size-cells = <0>;
+
+cpu: cpu@0 {
+compatible = "renesas,sh4", "renesas,sh2";
+device_type = "cpu";
+reg = <0>;
+clocks = <&cpg SH7750_CPG_ICK>;
+clock-names = "ick";
+icache-size = <16384>;
+icache-line-size = <32>;
+dcache-size = <32768>;
+dcache-line-size = <32>;
+};
+};
+...
--
2.39.2
[DO NOT MERGE v8 19/36] dt-bindings: interrupt-controller: renesas, sh7751-irl-ext: Add json-schema
Renesas SH7751 external interrupt encoder json-schema.
Signed-off-by: Yoshinori Sato
---
.../renesas,sh7751-irl-ext.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
new file mode 100644
index ..ff70d57b86cd
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id:
http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 external interrupt encoder with enable regs.
+
+maintainers:
+ - Yoshinori Sato
+
+description:
+ This is the generally used external interrupt encoder on SH7751 based boards.
+
+properties:
+ compatible:
+items:
+ - const: renesas,sh7751-irl-ext
+
+ reg: true
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+const: 2
+
+ '#address-cells':
+const: 0
+
+ renesas,set-to-disable:
+$ref: /schemas/types.yaml#/definitions/flag
+description: Invert enable registers. Setting the bit to 0 enables
interrupts.
+
+ renesas,enable-reg:
+$ref: /schemas/types.yaml#/definitions/uint32-array
+description: |
+ IRQ enable register bit mapping
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+ - renesas,enable-reg
+
+additionalProperties: false
+
+examples:
+ - |
+r2dintc: interrupt-controller@a400 {
+compatible = "renesas,sh7751-irl-ext";
+reg = <0xa400 0x02>;
+interrupt-controller;
+#address-cells = <0>;
+#interrupt-cells = <2>;
+renesas,enable-reg = <12 9 10 3 0 4 1 2 8 5 6 7 15 15 15 11>;
+};
--
2.39.2
[DO NOT MERGE v8 14/36] clk: Compatible with narrow registers
divider and gate only support 32-bit registers.
Older hardware uses narrower registers, so I want to be able to handle
8-bit and 16-bit wide registers.
Seven clk_divider flags are used, and if I add flags for 8bit access and
16bit access, 8bit will not be enough, so I expanded it to u16.
Signed-off-by: Yoshinori Sato
---
drivers/clk/clk-divider.c| 41 +-
drivers/clk/clk-gate.c | 49
include/linux/clk-provider.h | 20 ---
3 files changed, 89 insertions(+), 21 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index a2c2b5203b0a..abafcbbb6578 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -26,17 +26,34 @@
* parent - fixed parent. No clk_set_parent support
*/
-static inline u32 clk_div_readl(struct clk_divider *divider)
-{
+static inline u32 clk_div_read(struct clk_divider *divider)
+{
+ if (divider->flags & CLK_DIVIDER_REG_8BIT)
+ return readb(divider->reg);
+ if (divider->flags & CLK_DIVIDER_REG_16BIT) {
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) {
+ return ioread16be(divider->reg);
+ } else {
+ return readw(divider->reg);
+ }
+ }
if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
return ioread32be(divider->reg);
return readl(divider->reg);
}
-static inline void clk_div_writel(struct clk_divider *divider, u32 val)
+static inline void clk_div_write(struct clk_divider *divider, u32 val)
{
- if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
+ if (divider->flags & CLK_DIVIDER_REG_8BIT)
+ writeb(val, divider->reg);
+ else if (divider->flags & CLK_DIVIDER_REG_16BIT) {
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) {
+ iowrite16be(val, divider->reg);
+ } else {
+ writew(val, divider->reg);
+ }
+ } else if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
iowrite32be(val, divider->reg);
else
writel(val, divider->reg);
@@ -152,7 +169,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw
*hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int val;
- val = clk_div_readl(divider) >> divider->shift;
+ val = clk_div_read(divider) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_recalc_rate(hw, parent_rate, val, divider->table,
@@ -434,7 +451,7 @@ static long clk_divider_round_rate(struct clk_hw *hw,
unsigned long rate,
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
u32 val;
- val = clk_div_readl(divider) >> divider->shift;
+ val = clk_div_read(divider) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_ro_round_rate(hw, rate, prate, divider->table,
@@ -455,7 +472,7 @@ static int clk_divider_determine_rate(struct clk_hw *hw,
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
u32 val;
- val = clk_div_readl(divider) >> divider->shift;
+ val = clk_div_read(divider) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_ro_determine_rate(hw, req, divider->table,
@@ -505,11 +522,11 @@ static int clk_divider_set_rate(struct clk_hw *hw,
unsigned long rate,
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = clk_div_mask(divider->width) << (divider->shift + 16);
} else {
- val = clk_div_readl(divider);
+ val = clk_div_read(divider);
val &= ~(clk_div_mask(divider->width) << divider->shift);
}
val |= (u32)value << divider->shift;
- clk_div_writel(divider, val);
+ clk_div_write(divider, val);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
@@ -538,7 +555,7 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,
struct device_node *np, const char *name,
const char *parent_name, const struct clk_hw *parent_hw,
const struct clk_parent_data *parent_data, unsigned long flags,
- void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
+ void __iomem *reg, u8 shift, u8 width, u16 clk_divider_flags,
const struct clk_div_table *table, spinlock_t *lock)
{
struct clk_divider *div;
@@ -610,7 +627,7 @@ EXPORT_SYMBOL_GPL(__clk_hw_register_divider);
struct clk *clk_register_divider_table(struct
[DO NOT MERGE v8 29/36] sh: add RTS7751R2D Plus DTS
Renesas RTS7751R2D Plus devicetree.
Signed-off-by: Yoshinori Sato
---
arch/sh/boot/dts/rts7751r2dplus.dts | 172
1 file changed, 172 insertions(+)
create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts
diff --git a/arch/sh/boot/dts/rts7751r2dplus.dts
b/arch/sh/boot/dts/rts7751r2dplus.dts
new file mode 100644
index ..a67bd50cc80a
--- /dev/null
+++ b/arch/sh/boot/dts/rts7751r2dplus.dts
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Renesas RTS7751R2D Plus
+ */
+
+/dts-v1/;
+
+#include
+#include "sh7751r.dtsi"
+
+/ {
+ model = "Renesas RTS7715R2D Plus";
+ compatible = "renesas,rts7751r2d", "renesas,sh7751r";
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@c00 {
+ device_type = "memory";
+ reg = <0x0c00 0x400>;
+ };
+
+ r2dintc: interrupt-controller@a400 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xa400 0x02>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ /*
+* b15: 12 - TP
+* b14: 9 - PCI INTA
+* b13: 10 - PCI INTB
+* b12: 3 - PCI INTC
+* b11: 0 - PCI INTD
+* b10: 4 - SM501
+* b9: 1 - CF IDE
+* b8: 2 - CF CD
+* b7: 8 - SDCARD
+* b6: 5 - KEY
+* b5: 6 - RTC ALARM
+* b4: 7 - RTC T
+* b3: unassigned
+* b2: unassigned
+* b1: unassigned
+* b0: 11 -EXT
+*/
+ renesas,enable-reg = <12 9 10 3 0 4 1 2 8 5 6 7 15 15 15 11>;
+ };
+
+ sm501: display@1000 {
+ compatible = "smi,sm501";
+ reg = <0x1000 0x03e0
+ 0x13e0 0x0020>;
+ interrupt-parent = <&r2dintc>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ mode = "640x480-16@60";
+ smi,little-endian;
+ smi,devices = "usb-host", "uart0";
+ smi,swap-fb-endian;
+ #gpio-cells = <2>;
+ edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00
+ 00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60
+ 02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd];
+
+ smi,misc-timing-ex = "16";
+ smi,misc-timing-xc = "internal-pll";
+ smi,misc-timing-usb-current = "disable";
+ smi,misc-control-pad = "24";
+ smi,misc-control-usbclk = "xtal";
+ smi,misc-control-sh = "active-low";
+
+ gpio {
+ pin-0 = "ioport";
+ pin-1 = "function";
+ };
+
+ crt {
+ smi,flags = "use-init-done",
+ "disable-at-exit",
+ "use-hwcursor",
+ "use-hwaccel";
+ };
+
+ panel {
+ bpp = <16>;
+ smi,flags = "use-init-done",
+ "disable-at-exit",
+ "use-hwcursor",
+ "use-hwaccel";
+ };
+ };
+
+ compact-flash@b4001000 {
+ compatible = "renesas,rts7751r2d-ata", "ata-generic";
+ reg = <0xb4001000 0x0e>, <0xb400080c 2>;
+ reg-shift = <1>;
+ interrupt-parent = <&r2dintc>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ flash@0 {
+ compatible = "cfi-flash";
+ reg = <0x 0x0200>;
+ device-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+
[DO NOT MERGE v8 32/36] sh: j2_mimas_v2.dts update
Signed-off-by: Yoshinori Sato
---
arch/sh/boot/dts/j2_mimas_v2.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/sh/boot/dts/j2_mimas_v2.dts b/arch/sh/boot/dts/j2_mimas_v2.dts
index faf884f53804..b6ee682c5737 100644
--- a/arch/sh/boot/dts/j2_mimas_v2.dts
+++ b/arch/sh/boot/dts/j2_mimas_v2.dts
@@ -16,7 +16,7 @@ cpus {
cpu@0 {
device_type = "cpu";
- compatible = "jcore,j2";
+ compatible = "jcore,j2", "renesas,sh2";
reg = <0>;
clock-frequency = <5000>;
d-cache-size = <8192>;
--
2.39.2
[DO NOT MERGE v8 18/36] irqchip: SH7751 external interrupt encoder with enable gate.
SH7751 have 15 level external interrupt.
It is typically connected to the CPU through a priority encoder
that can suppress requests.
This driver provides a way to control those hardware with irqchip.
Signed-off-by: Yoshinori Sato
---
drivers/irqchip/Kconfig | 7 +
drivers/irqchip/Makefile| 2 +
drivers/irqchip/irq-renesas-sh7751irl.c | 221
3 files changed, 230 insertions(+)
create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f45a229963d4..50b2bdf157f1 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -723,4 +723,11 @@ config RENESAS_SH7751_INTC
Support for the Renesas SH7751 On-chip interrupt controller.
And external interrupt encoder for some targets.
+config RENESAS_SH7751IRL_INTC
+ bool "Renesas SH7751 based target IRL encoder support."
+ depends on RENESAS_SH7751_INTC
+ help
+ Support for External Interrupt encoder
+ on the some Renesas SH7751 based target.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 7bde45f05a1e..f99fa24927bc 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -125,3 +125,5 @@ obj-$(CONFIG_APPLE_AIC) +=
irq-apple-aic.o
obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
+obj-$(CONFIG_RENESAS_SH7751IRL_INTC) += irq-renesas-sh7751irl.o
+
diff --git a/drivers/irqchip/irq-renesas-sh7751irl.c
b/drivers/irqchip/irq-renesas-sh7751irl.c
new file mode 100644
index ..5990f2cd9a3d
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-sh7751irl.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SH7751 based board external interrupt level encoder driver
+ * (Renesas RTS7751R2D / IO DATA DEVICE LANDISK, USL-5P)
+ *
+ * Copyright (C) 2023 Yoshinori Sato
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct sh7751irl_intc_priv {
+ struct irq_domain *irq_domain;
+ void __iomem *base;
+ unsigned int width;
+ bool invert;
+ u32 enable_bit[NR_IRL];
+};
+
+static inline unsigned long get_reg(void __iomem *addr, unsigned int w)
+{
+ switch (w) {
+ case 8:
+ return __raw_readb(addr);
+ case 16:
+ return __raw_readw(addr);
+ case 32:
+ return __raw_readl(addr);
+ default:
+ /* The size is checked when reading the properties. */
+ pr_err("%s: Invalid width %d", __FILE__, w);
+ return 0;
+ }
+}
+
+static inline void set_reg(void __iomem *addr, unsigned int w, unsigned long
val)
+{
+ switch (w) {
+ case 8:
+ __raw_writeb(val, addr);
+ break;
+ case 16:
+ __raw_writew(val, addr);
+ break;
+ case 32:
+ __raw_writel(val, addr);
+ break;
+ default:
+ pr_err("%s: Invalid width %d", __FILE__, w);
+ }
+}
+
+static inline struct sh7751irl_intc_priv *irq_data_to_priv(struct irq_data
*data)
+{
+ return data->domain->host_data;
+}
+
+static void irl_endisable(struct irq_data *data, unsigned int enable)
+{
+ struct sh7751irl_intc_priv *priv;
+ unsigned long val;
+ unsigned int irl;
+
+ priv = irq_data_to_priv(data);
+ irl = irqd_to_hwirq(data) - IRL_BASE_IRQ;
+
+ if (irl < NR_IRL && priv->enable_bit[irl] < priv->width) {
+ if (priv->invert)
+ enable = !enable;
+
+ val = get_reg(priv->base, priv->width);
+ if (enable)
+ set_bit(priv->enable_bit[irl], &val);
+ else
+ clear_bit(priv->enable_bit[irl], &val);
+ set_reg(priv->base, priv->width, val);
+ } else {
+ pr_err("%s: Invalid register define in IRL %u", __FILE__, irl);
+ }
+}
+
+static void sh7751irl_intc_disable_irq(struct irq_data *data)
+{
+ irl_endisable(data, 0);
+}
+
+static void sh7751irl_intc_enable_irq(struct irq_data *data)
+{
+ irl_endisable(data, 1);
+}
+
+static struct irq_chip sh7751irl_intc_chip = {
+ .name = "SH7751IRL-INTC",
+ .irq_enable = sh7751irl_intc_enable_irq,
+ .irq_disable= sh7751irl_intc_disable_irq,
+};
+
+static int sh7751irl_intc_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &sh7751irl_intc_chip, handle_level_irq);
+
[DO NOT MERGE v8 25/36] dt-bindings: vendor-prefixes: Add iodata
Add IO DATA DEVICE INC. https://www.iodata.com/ Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index fbf47f0bacf1..66cf68139f07 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -716,6 +716,8 @@ patternProperties: description: Inventec "^inversepath,.*": description: Inverse Path + "^iodata,.*": +description: IO DATA DEVICE Inc. "^iom,.*": description: Iomega Corporation "^irondevice,.*": -- 2.39.2
[DO NOT MERGE v8 17/36] dt-bindings: interrupt-controller: renesas, sh7751-intc: Add json-schema
Renesas SH7751 INTC json-schema.
Signed-off-by: Yoshinori Sato
Reviewed-by: Rob Herring
---
.../renesas,sh7751-intc.yaml | 53 +++
1 file changed, 53 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
new file mode 100644
index ..fb924eff465d
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id:
http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 Interrupt Controller
+
+maintainers:
+ - Yoshinori Sato
+
+properties:
+ compatible:
+items:
+ - const: renesas,sh7751-intc
+
+ '#interrupt-cells':
+const: 1
+
+ interrupt-controller: true
+
+ reg:
+maxItems: 2
+
+ reg-names:
+items:
+ - const: ICR
+ - const: INTPRI00
+
+ renesas,icr-irlm:
+$ref: /schemas/types.yaml#/definitions/flag
+description: If true four independent interrupt requests mode (ICR.IRLM is
1).
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - '#interrupt-cells'
+ - interrupt-controller
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+shintc: interrupt-controller@ffd0 {
+compatible = "renesas,sh7751-intc";
+reg = <0xffd0 14>, <0xfe08 128>;
+reg-names = "ICR", "INTPRI00";
+#interrupt-cells = <1>;
+interrupt-controller;
+};
+...
--
2.39.2
[DO NOT MERGE v8 09/36] dt-binding: Add compatible SH7750 SoC
Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring --- Documentation/devicetree/bindings/timer/renesas,tmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml index 360a5cf1ae9c..4864fcd66bfd 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml @@ -40,6 +40,7 @@ properties: - renesas,tmu-r8a779f0 # R-Car S4-8 - renesas,tmu-r8a779g0 # R-Car V4H - renesas,tmu-r8a779h0 # R-Car V4M + - renesas,tmu-sh7750 # SH7750 - const: renesas,tmu reg: @@ -97,6 +98,7 @@ if: - renesas,tmu-r8a7740 - renesas,tmu-r8a7778 - renesas,tmu-r8a7779 +- renesas,tmu-sh7750 then: required: - resets -- 2.39.2
[DO NOT MERGE v8 08/36] clocksource: sh_tmu: CLOCKSOURCE support.
Allows initialization as CLOCKSOURCE.
Signed-off-by: Yoshinori Sato
---
drivers/clocksource/sh_tmu.c | 198 +++
1 file changed, 132 insertions(+), 66 deletions(-)
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index be81c00f..ce3004a73dcb 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -17,6 +17,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -51,6 +53,7 @@ struct sh_tmu_channel {
struct sh_tmu_device {
struct platform_device *pdev;
+ struct device_node *np;
void __iomem *mapbase;
struct clk *clk;
@@ -65,6 +68,7 @@ struct sh_tmu_device {
bool has_clockevent;
bool has_clocksource;
+ const char *name;
};
#define TSTR -1 /* shared register */
@@ -148,8 +152,8 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch)
/* enable clock */
ret = clk_enable(ch->tmu->clk);
if (ret) {
- dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
- ch->index);
+ pr_err("%s ch%u: cannot enable clock\n",
+ ch->tmu->name, ch->index);
return ret;
}
@@ -174,9 +178,10 @@ static int sh_tmu_enable(struct sh_tmu_channel *ch)
if (ch->enable_count++ > 0)
return 0;
- pm_runtime_get_sync(&ch->tmu->pdev->dev);
- dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
-
+ if (ch->tmu->pdev) {
+ pm_runtime_get_sync(&ch->tmu->pdev->dev);
+ dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
+ }
return __sh_tmu_enable(ch);
}
@@ -202,8 +207,10 @@ static void sh_tmu_disable(struct sh_tmu_channel *ch)
__sh_tmu_disable(ch);
- dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
- pm_runtime_put(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev) {
+ dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
+ pm_runtime_put(&ch->tmu->pdev->dev);
+ }
}
static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
@@ -245,7 +252,7 @@ static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
+static inline struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
{
return container_of(cs, struct sh_tmu_channel, cs);
}
@@ -292,7 +299,8 @@ static void sh_tmu_clocksource_suspend(struct clocksource
*cs)
if (--ch->enable_count == 0) {
__sh_tmu_disable(ch);
- dev_pm_genpd_suspend(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev)
+ dev_pm_genpd_suspend(&ch->tmu->pdev->dev);
}
}
@@ -304,7 +312,8 @@ static void sh_tmu_clocksource_resume(struct clocksource
*cs)
return;
if (ch->enable_count++ == 0) {
- dev_pm_genpd_resume(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev)
+ dev_pm_genpd_resume(&ch->tmu->pdev->dev);
__sh_tmu_enable(ch);
}
}
@@ -324,14 +333,14 @@ static int sh_tmu_register_clocksource(struct
sh_tmu_channel *ch,
cs->mask = CLOCKSOURCE_MASK(32);
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
- dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
-ch->index);
+ pr_info("%s ch%u: used as clock source\n",
+ ch->tmu->name, ch->index);
clocksource_register_hz(cs, ch->tmu->rate);
return 0;
}
-static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
+static inline struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device
*ced)
{
return container_of(ced, struct sh_tmu_channel, ced);
}
@@ -364,8 +373,8 @@ static int sh_tmu_clock_event_set_state(struct
clock_event_device *ced,
if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
sh_tmu_disable(ch);
- dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n",
-ch->index, periodic ? "periodic" : "oneshot");
+ pr_info("%s ch%u: used for %s clock events\n",
+ ch->tmu->name, ch->index, periodic ? "periodic" : "oneshot");
sh_tmu_clock_event_start(ch, periodic);
return 0;
}
@@ -417,20 +426,22 @@ static void sh_tmu_register_clockevent(struct
sh_tmu_channel *ch,
ced->set_state_shutdown = sh_tmu_clock_event_shutdown;
ced->set_state_period
[DO NOT MERGE v8 05/36] sh: GENERIC_IRQ_CHIP support for CONFIG_OF=y
Remove unused function prototype.
Add helper update_sr_imask. use for SH7751 irq driver.
Add stub intc_finalize.
Signed-off-by: Yoshinori Sato
---
arch/sh/include/asm/io.h | 2 ++
arch/sh/include/asm/irq.h | 10 --
arch/sh/kernel/cpu/Makefile| 5 +
arch/sh/kernel/cpu/irq/imask.c | 17 +
include/linux/sh_intc.h| 7 ++-
5 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index cf5eab840d57..5c544cf5201b 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -121,7 +121,9 @@ __BUILD_MEMORY_STRING(__raw_, q, u64)
#define ioport_map ioport_map
#define ioport_unmap ioport_unmap
+#ifndef CONFIG_SH_DEVICE_TREE
#define pci_iounmap pci_iounmap
+#endif
#define ioread8 ioread8
#define ioread16 ioread16
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
index 0f384b1f45ca..3d897229dcc4 100644
--- a/arch/sh/include/asm/irq.h
+++ b/arch/sh/include/asm/irq.h
@@ -16,8 +16,8 @@
/*
* Simple Mask Register Support
*/
-extern void make_maskreg_irq(unsigned int irq);
-extern unsigned short *irq_mask_register;
+
+void update_sr_imask(unsigned int irq, bool enable);
/*
* PINT IRQs
@@ -54,4 +54,10 @@ extern void irq_finish(unsigned int irq);
#include
+/* SH3/4 INTC stuff */
+/* IRL level 0 - 15 */
+#define NR_IRL 15
+/* IRL0 -> IRQ16 */
+#define IRL_BASE_IRQ 16
+
#endif /* __ASM_SH_IRQ_H */
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index e00ebf134985..ad12807fae9c 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -20,7 +20,4 @@ ifndef CONFIG_COMMON_CLK
obj-y += clock.o
obj-$(CONFIG_SH_CLK_CPG_LEGACY)+= clock-cpg.o
endif
-ifndef CONFIG_GENERIC_IRQ_CHIP
-obj-y += irq/
-endif
-obj-y += init.o fpu.o pfc.o proc.o
+obj-y += init.o fpu.o pfc.o proc.o irq/
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
index 572585c3f2fd..7589ca7c506c 100644
--- a/arch/sh/kernel/cpu/irq/imask.c
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -51,6 +51,7 @@ static inline void set_interrupt_registers(int ip)
: "t");
}
+#ifndef CONFIG_GENERIC_IRQ_CHIP
static void mask_imask_irq(struct irq_data *data)
{
unsigned int irq = data->irq;
@@ -83,3 +84,19 @@ void make_imask_irq(unsigned int irq)
irq_set_chip_and_handler_name(irq, &imask_irq_chip, handle_level_irq,
"level");
}
+#else
+void update_sr_imask(unsigned int irq, bool enable)
+{
+ if (enable) {
+ set_bit(irq, imask_mask);
+ interrupt_priority = IMASK_PRIORITY -
+ find_first_bit(imask_mask, IMASK_PRIORITY);
+ } else {
+ clear_bit(irq, imask_mask);
+ if (interrupt_priority < IMASK_PRIORITY - irq)
+ interrupt_priority = IMASK_PRIORITY - irq;
+ }
+ set_interrupt_registers(interrupt_priority);
+}
+EXPORT_SYMBOL(update_sr_imask);
+#endif
diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h
index 27ae79191bdc..994b5b05a0d7 100644
--- a/include/linux/sh_intc.h
+++ b/include/linux/sh_intc.h
@@ -139,8 +139,13 @@ struct intc_desc symbol __initdata = {
\
int register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);
int intc_irq_lookup(const char *chipname, intc_enum enum_id);
+#ifndef CONFIG_SH_DEVICE_TREE
void intc_finalize(void);
-
+#else
+static inline void intc_finalize(void)
+{
+}
+#endif
#ifdef CONFIG_INTC_USERIMASK
int register_intc_userimask(unsigned long addr);
#else
--
2.39.2
[DO NOT MERGE v8 10/36] sh: Common PCI Framework driver support.
Add New OF based PCI Host driver.
This driver conflicts some point in legacy PCI driver.
To resolve the conflict, I made some changes to the legacy driver.
Signed-off-by: Yoshinori Sato
---
arch/sh/include/asm/io.h | 6 ++
arch/sh/include/asm/pci.h | 4
arch/sh/kernel/iomap.c| 18 ++
3 files changed, 28 insertions(+)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 5c544cf5201b..29b5f996cde3 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#define __IO_PREFIX generic
#include
@@ -310,4 +311,9 @@ unsigned long long poke_real_address_q(unsigned long long
addr,
int valid_phys_addr_range(phys_addr_t addr, size_t size);
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+#if defined(CONFIG_PCI) && !defined(CONFIG_GENERIC_IOMAP)
+#define pci_remap_iospace pci_remap_iospace
+int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
+#endif
+
#endif /* __ASM_SH_IO_H */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index 54c30126ea17..92b3bd604319 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -2,6 +2,7 @@
#ifndef __ASM_SH_PCI_H
#define __ASM_SH_PCI_H
+#ifndef CONFIG_SH_DEVICE_TREE
/* Can be used to override the logic in pci_scan_bus for skipping
already-configured bus numbers - to be used for buggy BIOSes
or architectures with incomplete PCI setup by the loader */
@@ -88,4 +89,7 @@ static inline int pci_proc_domain(struct pci_bus *bus)
return hose->need_domain_info;
}
+#else /* CONFIG_SH_DEVICE_TREE */
+#include
+#endif
#endif /* __ASM_SH_PCI_H */
diff --git a/arch/sh/kernel/iomap.c b/arch/sh/kernel/iomap.c
index 0a0dff4e66de..d1b8e496ca23 100644
--- a/arch/sh/kernel/iomap.c
+++ b/arch/sh/kernel/iomap.c
@@ -160,3 +160,21 @@ void iowrite32_rep(void __iomem *addr, const void *src,
unsigned long count)
mmio_outsl(addr, src, count);
}
EXPORT_SYMBOL(iowrite32_rep);
+
+#if defined(pci_remap_iospace)
+int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
+{
+ unsigned long vaddr = res->start;
+
+ if (!(res->flags & IORESOURCE_IO))
+ return -EINVAL;
+
+ if (res->end > IO_SPACE_LIMIT)
+ return -EINVAL;
+
+ __set_io_port_base(phys_addr);
+ return vmap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
+ pgprot_device(PAGE_KERNEL));
+}
+EXPORT_SYMBOL(pci_remap_iospace);
+#endif
--
2.39.2
[DO NOT MERGE v8 06/36] sh: kernel/setup Update DT support.
Fix extrnal fdt initialize and bootargs.
Signed-off-by: Yoshinori Sato
---
arch/sh/Kconfig| 1 -
arch/sh/kernel/setup.c | 31 ---
2 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 91c7c72bc0db..5c9b50884995 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -712,7 +712,6 @@ config ROMIMAGE_MMCIF
choice
prompt "Kernel command line"
default CMDLINE_OVERWRITE
- depends on !OF || USE_BUILTIN_DTB
help
Setting this option allows the kernel command line arguments
to be set.
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 620e5cf8ae1e..03ec6f7a1153 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -269,8 +270,22 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
void __init setup_arch(char **cmdline_p)
{
+#if defined(CONFIG_OF) && defined(CONFIG_OF_EARLY_FLATTREE)
+ if (IS_ENABLED(CONFIG_USE_BUILTIN_DTB)) {
+ /* Relocate Embedded DTB */
+ unflatten_and_copy_device_tree();
+ } else if (initial_boot_params) {
+ /* Reserve external DTB area */
+ memblock_reserve(__pa(initial_boot_params),
+fdt_totalsize(initial_boot_params));
+ unflatten_device_tree();
+ }
+ /* copy from /chosen/bootargs */
+ strscpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
+#endif
enable_mmu();
+#ifndef CONFIG_OF
ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
printk(KERN_NOTICE "Boot params:\n"
@@ -299,14 +314,16 @@ void __init setup_arch(char **cmdline_p)
bss_resource.start = virt_to_phys(__bss_start);
bss_resource.end = virt_to_phys(__bss_stop)-1;
+#endif
#ifdef CONFIG_CMDLINE_OVERWRITE
strscpy(command_line, CONFIG_CMDLINE, sizeof(command_line));
-#else
- strscpy(command_line, COMMAND_LINE, sizeof(command_line));
+#elif !defined(CONFIG_OF) || defined(CONFIG_USE_BUILTIN_DTB)
+ if (*COMMAND_LINE)
+ strscpy(command_line, COMMAND_LINE, sizeof(command_line));
+#endif
#ifdef CONFIG_CMDLINE_EXTEND
strlcat(command_line, " ", sizeof(command_line));
strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line));
-#endif
#endif
/* Save unparsed command line copy for /proc/cmdline */
@@ -322,14 +339,6 @@ void __init setup_arch(char **cmdline_p)
/* Let earlyprintk output early console messages */
sh_early_platform_driver_probe("earlyprintk", 1, 1);
-#ifdef CONFIG_OF_EARLY_FLATTREE
-#ifdef CONFIG_USE_BUILTIN_DTB
- unflatten_and_copy_device_tree();
-#else
- unflatten_device_tree();
-#endif
-#endif
-
paging_init();
/* Perform the machine specific initialisation */
--
2.39.2
[DO NOT MERGE v8 04/36] dt-bindings: interrupt-controller: Add header for Renesas SH3/4 INTC.
Renesas SH7751 Interrupt controller priority register define. Signed-off-by: Yoshinori Sato --- .../renesas,sh7751-intc.h | 19 +++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h diff --git a/include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h b/include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h new file mode 100644 index ..0543bd1b895e --- /dev/null +++ b/include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * SH3/4 INTC IPR register offsets (Address / bits) + */ + +#ifndef __DT_BINDINGS_RENESAS_SH7751_INTC +#define __DT_BINDINGS_RENESAS_SH7751_INTC + +#define IPRA 0 +#define IPRB 4 +#define IPRC 8 +#define IPRD 12 +#define INTPRI00 256 +#define IPR_B1212 +#define IPR_B8 8 +#define IPR_B4 4 +#define IPR_B0 0 + +#endif -- 2.39.2
[DO NOT MERGE v8 03/36] sh: Enable OF support for build and configuration.
IRQ, CLK and PCI will be migrated to a common driver framework. So if OF, disable the SH specific drivers. Signed-off-by: Yoshinori Sato --- arch/sh/Kconfig | 11 ++- arch/sh/drivers/Makefile| 2 ++ arch/sh/kernel/cpu/Makefile | 9 +++-- arch/sh/kernel/cpu/sh4/Makefile | 3 +++ 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index d6704c57f9dc..91c7c72bc0db 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -66,10 +66,10 @@ config SUPERH select MODULES_USE_ELF_RELA select NEED_SG_DMA_LENGTH select NO_DMA if !MMU && !DMA_COHERENT - select NO_GENERIC_PCI_IOPORT_MAP if PCI + select NO_GENERIC_PCI_IOPORT_MAP if !SH_DEVICE_TREE select OLD_SIGACTION select OLD_SIGSUSPEND - select PCI_DOMAINS if PCI + select PCI_DOMAINS if PCI && !SH_DEVICE_TREE select PERF_EVENTS select PERF_USE_VMALLOC select RTC_LIB @@ -154,7 +154,7 @@ menu "System type" # config CPU_SH2 bool - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE config CPU_SH2A bool @@ -180,7 +180,7 @@ config CPU_SH4 select CPU_HAS_INTEVT select CPU_HAS_SR_RB select CPU_HAS_FPU if !CPU_SH4AL_DSP - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE select SYS_SUPPORTS_SH_TMU config CPU_SH4A @@ -523,6 +523,7 @@ config SH_PCLK_FREQ config SH_CLK_CPG def_bool y + depends on !COMMON_CLK config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG @@ -667,7 +668,7 @@ config BUILTIN_DTB_SOURCE kernel. config ZERO_PAGE_OFFSET - hex + hex "Zero page offset" default "0x0001" if PAGE_SIZE_64KB || SH_RTS7751R2D || \ SH_7751_SOLUTION_ENGINE default "0x4000" if PAGE_SIZE_16KB || SH_SH03 diff --git a/arch/sh/drivers/Makefile b/arch/sh/drivers/Makefile index 8bd10b904bf9..83f609ca1eb4 100644 --- a/arch/sh/drivers/Makefile +++ b/arch/sh/drivers/Makefile @@ -5,6 +5,8 @@ obj-y += dma/ platform_early.o +ifndef CONFIG_SH_DEVICE_TREE obj-$(CONFIG_PCI) += pci/ +endif obj-$(CONFIG_PUSH_SWITCH) += push-switch.o obj-$(CONFIG_HEARTBEAT)+= heartbeat.o diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile index 46118236bf04..e00ebf134985 100644 --- a/arch/sh/kernel/cpu/Makefile +++ b/arch/sh/kernel/cpu/Makefile @@ -16,6 +16,11 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/ # Common interfaces. obj-$(CONFIG_SH_ADC) += adc.o +ifndef CONFIG_COMMON_CLK +obj-y += clock.o obj-$(CONFIG_SH_CLK_CPG_LEGACY)+= clock-cpg.o - -obj-y += irq/ init.o clock.o fpu.o pfc.o proc.o +endif +ifndef CONFIG_GENERIC_IRQ_CHIP +obj-y += irq/ +endif +obj-y += init.o fpu.o pfc.o proc.o diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile index 02e3ee16e15c..33da4c86feff 100644 --- a/arch/sh/kernel/cpu/sh4/Makefile +++ b/arch/sh/kernel/cpu/sh4/Makefile @@ -15,6 +15,7 @@ perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o +ifndef CONFIG_SH_DEVICE_TREE # CPU subtype setup obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o @@ -29,5 +30,7 @@ ifndef CONFIG_CPU_SH4A clock-$(CONFIG_CPU_SH4):= clock-sh4.o endif +endif # CONFIG_SH_DEVICE_TREE + obj-y += $(clock-y) obj-$(CONFIG_PERF_EVENTS) += $(perf-y) -- 2.39.2
[DO NOT MERGE v8 01/36] sh: passing FDT address to kernel startup.
R4 is caller saved in SH ABI. Save it so it doesn't get corrupted until it's needed for initialization. Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven --- arch/sh/boot/compressed/head_32.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S index 7bb168133dbb..6be59851122e 100644 --- a/arch/sh/boot/compressed/head_32.S +++ b/arch/sh/boot/compressed/head_32.S @@ -15,7 +15,8 @@ startup: /* Load initial status register */ mov.l init_sr, r1 ldc r1, sr - + /* Save FDT address */ + mov r4, r13 /* Move myself to proper location if necessary */ mova1f, r0 mov.l 1f, r2 @@ -84,7 +85,7 @@ l1: /* Jump to the start of the decompressed kernel */ mov.l kernel_start_addr, r0 jmp @r0 - nop +movr13, r4 .align 2 bss_start_addr: -- 2.39.2
[DO NOT MERGE v8 00/36] Device Tree support for SH7751 based board
This is an updated version of something I wrote about 7 years ago. Minimum support for R2D-plus and LANDISK. I think R2D-1 will work if you add AX88796 to dts. And board-specific functions and SCI's SPI functions are not supported. You can get it working with qemu found here. https://gitlab.com/yoshinori.sato/qemu/-/tree/landisk v8 changes. - rebase v6.10-rc1 - sh/Konfig: Keep compatibility for non-DT. - renesas,sh7750-cpg.yaml: cleanup. - smi,sm501.yaml: rewrite register definition. - sm501.c: remove unneeded changes. - renesas,sh7751-irl-ext.yaml: fix intetrupt-cells. - renesas,sh7751-pci.yaml: remove duplicate. - clk-divider.c: cleanup. - clk-gate.c: cleanup. - sh_tmu.c: cleanup. - pci-sh7751.c: cleanup. v7 changes. - sh/kernel/setup.c: fix kernel parameter handling. - clk-sh7750.c: cleanup. - sh_tmu.c: cleanup. - irq-renesas-sh7751.c: IPR definition move to code. - irq-renesas-sh7751irl.c: update register definition. - pci-sh7751.c: Register initialization fix. - sm501 and sm501fb: Re-design Device Tree properties. v6 changes. - pci-sh7751: merge register define. - pci-sh7751: use 'dma-ranges' property. - pci-sh7751: rename general PCI properties. - sm501 and sm501fb: Re-design Device Tree properties. - sh/kernel/setup: cleanup command line setup. - irq-sh7751.c: some cleanup. v5 changes. - pci-sh7751: revert header changes. and some fix in previuous driver. - sh/kernel/iomap.c: Use SH io functions. - sm501 and sm501fb: re-write DT support. v4 changes. - cpg-sh7750: use clk-divider and clk-gate. - pci-sh7751: unified header files to old PCI driver. - irq-renesas-sh7751: IPR registers direct mapping. - irq-renesas-sh7751irl: useful register bit mapping. - sm501 and sm501fb: re-write dt parser. - j2_minus: fix build error. - dt-binding schema: fix some errors. - *.dts: cleanup. v3 changes. - Rewrite clk drivers. - Added sh_tmu to OF support. - Cleanup PCI stuff. - Update sm501 and sm501fb OF support. - Update devicetree and documents. v2 changes. - Rebasing v6,6-rc1 - re-write irqchip driver. - Add binding documents. - Cleanup review comment. Yoshinori Sato (36): sh: passing FDT address to kernel startup. sh: Kconfig unified OF supported targets. sh: Enable OF support for build and configuration. dt-bindings: interrupt-controller: Add header for Renesas SH3/4 INTC. sh: GENERIC_IRQ_CHIP support for CONFIG_OF=y sh: kernel/setup Update DT support. sh: Fix COMMON_CLK support in CONFIG_OF=y. clocksource: sh_tmu: CLOCKSOURCE support. dt-binding: Add compatible SH7750 SoC sh: Common PCI Framework driver support. pci: pci-sh7751: Add SH7751 PCI driver dt-bindings: pci: pci-sh7751: Add SH7751 PCI dt-bindings: clock: sh7750-cpg: Add renesas,sh7750-cpg header. clk: Compatible with narrow registers clk: renesas: Add SH7750/7751 CPG Driver irqchip: Add SH7751 INTC driver dt-bindings: interrupt-controller: renesas,sh7751-intc: Add json-schema irqchip: SH7751 external interrupt encoder with enable gate. dt-bindings: interrupt-controller: renesas,sh7751-irl-ext: Add json-schema serial: sh-sci: fix SH4 OF support. dt-bindings: serial: renesas,scif: Add scif-sh7751. dt-bindings: display: smi,sm501: SMI SM501 binding json-schema mfd: sm501: Convert platform_data to OF property dt-binding: sh: cpus: Add SH CPUs json-schema dt-bindings: vendor-prefixes: Add iodata dt-bindings: ata: ata-generic: Add new targets dt-bindings: soc: renesas: sh: Add SH7751 based target sh: SH7751R SoC Internal peripheral definition dtsi. sh: add RTS7751R2D Plus DTS sh: Add IO DATA LANDISK dts sh: Add IO DATA USL-5P dts sh: j2_mimas_v2.dts update sh: Add dtbs target support. sh: RTS7751R2D Plus OF defconfig sh: LANDISK OF defconfig sh: j2_defconfig: update .../devicetree/bindings/ata/ata-generic.yaml | 2 + .../bindings/clock/renesas,sh7750-cpg.yaml| 107 .../bindings/display/smi,sm501.yaml | 443 .../renesas,sh7751-intc.yaml | 53 ++ .../renesas,sh7751-irl-ext.yaml | 57 +++ .../bindings/pci/renesas,sh7751-pci.yaml | 75 +++ .../bindings/serial/renesas,scif.yaml | 1 + .../devicetree/bindings/sh/cpus.yaml | 63 +++ .../devicetree/bindings/soc/renesas/sh.yaml | 27 + .../bindings/timer/renesas,tmu.yaml | 2 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/sh/Kconfig | 11 +- arch/sh/boards/Kconfig| 23 +- arch/sh/boards/of-generic.c | 28 +- arch/sh/boot/compressed/head_32.S | 5 +- arch/sh/boot/dts/Makefile | 5 + arch/sh/boot/dts/j2_mimas_v2.dts | 2 +- arch/sh/boot/dts/landisk.dts | 77 +++ arch/sh/boot/dts/rts7751r2dplus.dts | 172 +++ arch/sh/boot/dts/sh7751r.dtsi | 105 arch/sh/boot/dts/usl-5p.dts | 85
Re: [RESEND v7 00/37] Device Tree support for SH7751 based board
On Sat, 18 May 2024 18:08:30 +0900, John Paul Adrian Glaubitz wrote: > > Hi Yoshinori, > > On Thu, 2024-04-04 at 14:14 +0900, Yoshinori Sato wrote: > > Sorry. previus mail is thread broken. > > > > This is an updated version of something I wrote about 7 years ago. > > Minimum support for R2D-plus and LANDISK. > > I think R2D-1 will work if you add AX88796 to dts. > > And board-specific functions and SCI's SPI functions are not supported. > > > > You can get it working with qemu found here. > > https://gitlab.com/yoshinori.sato/qemu/-/tree/landisk > > > > v7 changes. > > - sh/kernel/setup.c: fix kernel parameter handling. > > - clk-sh7750.c: cleanup. > > - sh_tmu.c: cleanup. > > - irq-renesas-sh7751.c: IPR definition move to code. > > - irq-renesas-sh7751irl.c: update register definition. > > - pci-sh7751.c: Register initialization fix. > > - sm501 and sm501fb: Re-design Device Tree properties. > > Could you push your v7 version to your Gitlab [1] repository so I can fetch > it from there? updated it. I'll be posting v8 soon. > Thanks, > Adrian > > > [1] https://gitlab.com/yoshinori.sato/linux > > -- > .''`. John Paul Adrian Glaubitz > : :' : Debian Developer > `. `' Physicist > `-GPG: 62FF 8A75 84E0 2956 9546 0006 7426 3B37 F5B5 F913 > -- Yosinori Sato
[RESEND v7 36/37] sh: LANDISK OF defconfig
Signed-off-by: Yoshinori Sato --- arch/sh/configs/landisk-of_defconfig | 104 +++ 1 file changed, 104 insertions(+) create mode 100644 arch/sh/configs/landisk-of_defconfig diff --git a/arch/sh/configs/landisk-of_defconfig b/arch/sh/configs/landisk-of_defconfig new file mode 100644 index ..1a70884c675b --- /dev/null +++ b/arch/sh/configs/landisk-of_defconfig @@ -0,0 +1,104 @@ +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_KEXEC=y +CONFIG_CPU_SUBTYPE_SH7751R=y +CONFIG_MEMORY_START=0x0c00 +CONFIG_SH_OF_BOARD=y +CONFIG_HEARTBEAT=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +CONFIG_ATALK=m +CONFIG_PCI=y +CONFIG_PCI_SH7751=y +CONFIG_PCCARD=y +CONFIG_YENTA=y +CONFIG_UEVENT_HELPER=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ATA=y +CONFIG_PATA_ARTOP=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_ATA_GENERIC=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_NETDEVICES=y +CONFIG_TUN=m +CONFIG_8139CP=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_HW_RANDOM=y +CONFIG_SOUND=m +CONFIG_HID_A4TECH=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GYRATION=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SUNPLUS=m +CONFIG_USB_HID=m +CONFIG_USB=y +CONFIG_USB_MON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_SISUSBVGA=m +CONFIG_RENESAS_SH7751_INTC=y +CONFIG_RENESAS_SH7751IRL_INTC=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_REISERFS_FS=y +CONFIG_ISO9660_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_ROMFS_FS=y +CONFIG_UFS_FS=m +CONFIG_NFS_FS=m +CONFIG_NFSD=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_INIT_STACK_NONE=y +CONFIG_CRC_T10DIF=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_FTRACE is not set +CONFIG_SH_STANDARD_BIOS=y -- 2.39.2
[RESEND v7 35/37] sh: RTS7751R2D Plus OF defconfig
Signed-off-by: Yoshinori Sato --- arch/sh/configs/rts7751r2dplus-of_defconfig | 75 + 1 file changed, 75 insertions(+) create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig diff --git a/arch/sh/configs/rts7751r2dplus-of_defconfig b/arch/sh/configs/rts7751r2dplus-of_defconfig new file mode 100644 index ..75f3fc4fc5e6 --- /dev/null +++ b/arch/sh/configs/rts7751r2dplus-of_defconfig @@ -0,0 +1,75 @@ +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_PROFILING=y +CONFIG_CPU_SUBTYPE_SH7751R=y +CONFIG_MEMORY_START=0x0c00 +CONFIG_SH_RTS7751R2D=y +CONFIG_RTS7751R2D_PLUS=y +CONFIG_HEARTBEAT=y +CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 root=/dev/sda1" +CONFIG_CMDLINE_OVERWRITE=y +CONFIG_MODULES=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IPV6 is not set +CONFIG_PCI=y +CONFIG_HOTPLUG_PCI=y +CONFIG_UEVENT_HELPER=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ATA=y +CONFIG_PATA_PLATFORM=y +CONFIG_NETDEVICES=y +CONFIG_8139TOO=y +# CONFIG_8139TOO_PIO is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SH_SCI=y +CONFIG_HW_RANDOM=y +CONFIG_SPI=y +CONFIG_SPI_SH_SCI=y +CONFIG_MFD_SM501=y +CONFIG_FB=y +CONFIG_FB_SH_MOBILE_LCDC=m +CONFIG_FB_SM501=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_SUPERH_MONO is not set +# CONFIG_LOGO_SUPERH_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_YMFPCI=m +CONFIG_HID_GYRATION=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_R9701=y +CONFIG_EXT2_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_MINIX_FS=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_CRC_T10DIF=y +CONFIG_DEBUG_FS=y -- 2.39.2
[RESEND v7 32/37] sh: Add IO DATA USL-5P dts
IO DATA DEVICE Inc. USL-5P devicetree.
Signed-off-by: Yoshinori Sato
---
arch/sh/boot/dts/usl-5p.dts | 85 +
1 file changed, 85 insertions(+)
create mode 100644 arch/sh/boot/dts/usl-5p.dts
diff --git a/arch/sh/boot/dts/usl-5p.dts b/arch/sh/boot/dts/usl-5p.dts
new file mode 100644
index ..b90bff50b29a
--- /dev/null
+++ b/arch/sh/boot/dts/usl-5p.dts
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the IO DATA DEVICE USL-5P
+ */
+
+/dts-v1/;
+
+#include "sh7751r.dtsi"
+
+/ {
+ model = "IO-DATA Device USL-5P";
+ compatible = "iodata,usl-5p", "renesas,sh7751r";
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ stdout-path = "serial0:9600n8";
+ };
+
+ memory@c00 {
+ device_type = "memory";
+ reg = <0x0c00 0x400>;
+ };
+
+ julianintc: interrupt-controller@b005 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xb005 0x01>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ /*
+* b7: Button
+* b6: Power switch
+* b5: Compact Flash
+* b4: ATA
+* b3: PCI-INTD
+* b2: PCI-INTC
+* b1: PCI-INTB
+* b0: PCI-INTA
+*/
+ renesas,enable-reg = <12 11 10 9 8 7 6 5>;
+ };
+
+ compact-flash@b440 {
+ compatible = "iodata,usl-5p-ata", "ata-generic";
+ reg = <0xb440 0x0e>, <0xb42c 2>;
+ reg-shift = <1>;
+ interrupt-parent = <&julianintc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&extal {
+ clock-frequency = <>;
+};
+
+&cpg {
+ renesas,mode = <5>;
+};
+
+&scif1 {
+ status = "okay";
+};
+
+&pcic {
+ ranges = <0x0200 0 0xfd00 0xfd00 0 0x0100>,
+<0x0100 0 0x 0xfe24 0 0x0004>;
+ dma-ranges = <0x0200 0 0x0c00 0x0c00 0 0x0400>,
+<0x0200 0 0xd000 0xd000 0 0x0001>;
+ interrupt-map = <0x 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 2 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 3 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 4 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 1 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 2 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 3 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 4 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 1 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 2 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 3 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 4 &julianintc 6 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map-mask = <0x1800 0 0 7>;
+ status = "okay";
+};
--
2.39.2
[RESEND v7 34/37] sh: Add dtbs target support.
Signed-off-by: Yoshinori Sato --- arch/sh/boot/dts/Makefile | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/sh/boot/dts/Makefile b/arch/sh/boot/dts/Makefile index 4a6dec9714a9..e6b93360c213 100644 --- a/arch/sh/boot/dts/Makefile +++ b/arch/sh/boot/dts/Makefile @@ -1,2 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_USE_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOURCE)) + +dtb-$(CONFIG_CPU_J2) += j2_mimas_v2.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += landisk.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += rts7751r2dplus.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += usl-5p.dtb -- 2.39.2
[RESEND v7 33/37] sh: j2_mimas_v2.dts update
Signed-off-by: Yoshinori Sato
---
arch/sh/boot/dts/j2_mimas_v2.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/sh/boot/dts/j2_mimas_v2.dts b/arch/sh/boot/dts/j2_mimas_v2.dts
index fa9562f78d53..5dfe20866a1c 100644
--- a/arch/sh/boot/dts/j2_mimas_v2.dts
+++ b/arch/sh/boot/dts/j2_mimas_v2.dts
@@ -16,7 +16,7 @@ cpus {
cpu@0 {
device_type = "cpu";
- compatible = "jcore,j2";
+ compatible = "jcore,j2", "renesas,sh2";
reg = <0>;
clock-frequency = <5000>;
d-cache-size = <8192>;
--
2.39.2
[RESEND v7 30/37] sh: add RTS7751R2D Plus DTS
Renesas RTS7751R2D Plus devicetree.
Signed-off-by: Yoshinori Sato
---
arch/sh/boot/dts/rts7751r2dplus.dts | 169
1 file changed, 169 insertions(+)
create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts
diff --git a/arch/sh/boot/dts/rts7751r2dplus.dts
b/arch/sh/boot/dts/rts7751r2dplus.dts
new file mode 100644
index ..c3aca9316c76
--- /dev/null
+++ b/arch/sh/boot/dts/rts7751r2dplus.dts
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Renesas RTS7751R2D Plus
+ */
+
+/dts-v1/;
+
+#include "sh7751r.dtsi"
+#include
+
+/ {
+ model = "Renesas RTS7715R2D Plus";
+ compatible = "renesas,rts7751r2d", "renesas,sh7751r";
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@c00 {
+ device_type = "memory";
+ reg = <0x0c00 0x400>;
+ };
+
+ r2dintc: interrupt-controller@a400 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xa400 0x02>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ /*
+* b15: 12 - TP
+* b14: 9 - PCI INTA
+* b13: 10 - PCI INTB
+* b12: 3 - PCI INTC
+* b11: 0 - PCI INTD
+* b10: 4 - SM501
+* b9: 1 - CF IDE
+* b8: 2 - CF CD
+* b7: 8 - SDCARD
+* b6: 5 - KEY
+* b5: 6 - RTC ALARM
+* b4: 7 - RTC T
+* b3: unassigned
+* b2: unassigned
+* b1: unassigned
+* b0: 11 -EXT
+*/
+ renesas,enable-reg = <12 9 10 3 0 4 1 2 8 5 6 7 15 15 15 11>;
+ };
+
+ display@0 {
+ compatible = "smi,sm501";
+ reg = <0x1000 0x03e0
+ 0x13e0 0x0020>;
+ interrupt-parent = <&r2dintc>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ mode = "640x480-16@60";
+ little-endian;
+ smi,devices = "usb-host", "uart0";
+ swap-fb-endian;
+
+ crt {
+ smi,flags = "use-init-done",
+ "disable-at-exit",
+ "use-hwcursor",
+ "use-hwaccel";
+ };
+
+ panel {
+ bpp = <16>;
+ edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00
+ 00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60
+ 02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
bd];
+ smi,flags = "use-init-done",
+ "disable-at-exit",
+ "use-hwcursor",
+ "use-hwaccel";
+ };
+ misc-timing {
+ ex = ;
+ xc = ;
+ usb-over-current-detect-disable;
+ };
+ misc-control {
+ pad = ;
+ usbclk = ;
+ sh-ready-low;
+ };
+ };
+
+ compact-flash@b4001000 {
+ compatible = "renesas,rts7751r2d-ata", "ata-generic";
+ reg = <0xb4001000 0x0e>, <0xb400080c 2>;
+ reg-shift = <1>;
+ interrupt-parent = <&r2dintc>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ flash@0 {
+ compatible = "cfi-flash";
+ reg = <0x 0x0200>;
+ device-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x 0x0004>;
+ };
+
+ partition@1 {
+ label = "En
[RESEND v7 29/37] sh: SH7751R SoC Internal peripheral definition dtsi.
SH7751R internal peripherals device tree.
Signed-off-by: Yoshinori Sato
---
arch/sh/boot/dts/sh7751r.dtsi | 105 ++
1 file changed, 105 insertions(+)
create mode 100644 arch/sh/boot/dts/sh7751r.dtsi
diff --git a/arch/sh/boot/dts/sh7751r.dtsi b/arch/sh/boot/dts/sh7751r.dtsi
new file mode 100644
index ..61b2af5bebde
--- /dev/null
+++ b/arch/sh/boot/dts/sh7751r.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the SH7751R SoC
+ */
+
+#include
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "renesas,sh4", "renesas,sh2";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&cpg SH7750_CPG_ICK>;
+ clock-names = "ick";
+ icache-size = <16384>;
+ icache-line-size = <32>;
+ dcache-size = <32768>;
+ dcache-line-size = <32>;
+ };
+ };
+
+ extal: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "extal";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&shintc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cpg: clock-controller@ffc0 {
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+ compatible = "renesas,sh7751r-cpg";
+ clocks = <&extal>;
+ clock-names = "extal";
+ reg = <0xffc0 20>, <0xfe0a 16>;
+ reg-names = "FRQCR", "CLKSTP00";
+ renesas,mode = <0>;
+ };
+
+ shintc: interrupt-controller@ffd0 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <0xffd0 20>, <0xfe08 128>;
+ reg-names = "ICR", "INTPRI00";
+ };
+
+ /* sci0 is rarely used, so it is not defined here. */
+ scif1: serial@ffe8 {
+ compatible = "renesas,scif-sh7751", "renesas,scif";
+ reg = <0xffe8 0x100>;
+ interrupts = <0x700>,
+<0x720>,
+<0x760>,
+<0x740>;
+ interrupt-names = "eri", "rxi", "txi", "bri";
+ clocks = <&cpg SH7750_MSTP_SCIF>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ /* Normally ch0 and ch1 are used, so we will define ch0 to ch2
here. */
+ tmu0: timer@ffd8 {
+ compatible = "renesas,tmu-sh7750", "renesas,tmu";
+ reg = <0xffd8 12>;
+ interrupts = <0x400>,
+<0x420>,
+<0x440>,
+<0x460>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
+ clocks = <&cpg SH7750_MSTP_TMU012>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ #renesas,channels = <3>;
+ };
+
+ pcic: pci@fe20 {
+ compatible = "renesas,sh7751-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ bus-range = <0 0>;
+ reg = <0xfe20 0x0400>,
+ <0xff80 0x0100>;
+ status = "disabled";
+ };
+ };
+};
--
2.39.2
[RESEND v7 14/37] clk: Compatible with narrow registers
divider and gate only support 32-bit registers.
Older hardware uses narrower registers, so I want to be able to handle
8-bit and 16-bit wide registers.
Seven clk_divider flags are used, and if I add flags for 8bit access and
16bit access, 8bit will not be enough, so I expanded it to u16.
Signed-off-by: Yoshinori Sato
---
drivers/clk/clk-divider.c| 56 +---
drivers/clk/clk-gate.c | 62
include/linux/clk-provider.h | 22 ++---
3 files changed, 103 insertions(+), 37 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index a2c2b5203b0a..a1b5187cd63d 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -26,20 +26,38 @@
* parent - fixed parent. No clk_set_parent support
*/
-static inline u32 clk_div_readl(struct clk_divider *divider)
-{
- if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
- return ioread32be(divider->reg);
-
- return readl(divider->reg);
+static inline u32 clk_div_read(struct clk_divider *divider)
+{
+ if (divider->flags & CLK_DIVIDER_REG_8BIT)
+ return readb(divider->reg);
+ else if (divider->flags & CLK_DIVIDER_REG_16BIT) {
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
+ return ioread16be(divider->reg);
+ else
+ return readw(divider->reg);
+ } else {
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
+ return ioread32be(divider->reg);
+ else
+ return readl(divider->reg);
+ }
}
-static inline void clk_div_writel(struct clk_divider *divider, u32 val)
+static inline void clk_div_write(struct clk_divider *divider, u32 val)
{
- if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
- iowrite32be(val, divider->reg);
- else
- writel(val, divider->reg);
+ if (divider->flags & CLK_DIVIDER_REG_8BIT)
+ writeb(val, divider->reg);
+ else if (divider->flags & CLK_DIVIDER_REG_16BIT) {
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
+ iowrite16be(val, divider->reg);
+ else
+ writew(val, divider->reg);
+ } else {
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
+ iowrite32be(val, divider->reg);
+ else
+ writel(val, divider->reg);
+ }
}
static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
@@ -152,7 +170,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw
*hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int val;
- val = clk_div_readl(divider) >> divider->shift;
+ val = clk_div_read(divider) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_recalc_rate(hw, parent_rate, val, divider->table,
@@ -434,7 +452,7 @@ static long clk_divider_round_rate(struct clk_hw *hw,
unsigned long rate,
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
u32 val;
- val = clk_div_readl(divider) >> divider->shift;
+ val = clk_div_read(divider) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_ro_round_rate(hw, rate, prate, divider->table,
@@ -455,7 +473,7 @@ static int clk_divider_determine_rate(struct clk_hw *hw,
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
u32 val;
- val = clk_div_readl(divider) >> divider->shift;
+ val = clk_div_read(divider) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_ro_determine_rate(hw, req, divider->table,
@@ -505,11 +523,11 @@ static int clk_divider_set_rate(struct clk_hw *hw,
unsigned long rate,
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = clk_div_mask(divider->width) << (divider->shift + 16);
} else {
- val = clk_div_readl(divider);
+ val = clk_div_read(divider);
val &= ~(clk_div_mask(divider->width) << divider->shift);
}
val |= (u32)value << divider->shift;
- clk_div_writel(divider, val);
+ clk_div_write(divider, val);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
@@ -538,7 +556,7 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,
struct device_node *np, const char *name,
const char *parent_name, const struct clk_hw *parent_hw,
const struct clk_parent_da
[RESEND v7 28/37] dt-bindings: soc: renesas: sh: Add SH7751 based target
Signed-off-by: Yoshinori Sato --- .../devicetree/bindings/soc/renesas/sh.yaml | 27 +++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/sh.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/sh.yaml b/Documentation/devicetree/bindings/soc/renesas/sh.yaml new file mode 100644 index ..9e0f69a8ee6a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH Platform + +maintainers: + - Yoshinori Sato + +properties: + $nodename: +const: '/' + compatible: +oneOf: + - description: SH7751R based platform +items: + - enum: + - renesas,rts7751r2d # Renesas SH4 2D graphics board + - iodata,landisk # LANDISK HDL-U + - iodata,usl-5p # USL-5P + - const: renesas,sh7751r + +additionalProperties: true + +... -- 2.39.2
[RESEND v7 37/37] sh: j2_defconfig: update
I've changed some symbols related to DeviceTree, so let's take care of those changes. Signed-off-by: Yoshinori Sato --- arch/sh/configs/j2_defconfig | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/sh/configs/j2_defconfig b/arch/sh/configs/j2_defconfig index 2eb81ebe3888..cdc8ed244618 100644 --- a/arch/sh/configs/j2_defconfig +++ b/arch/sh/configs/j2_defconfig @@ -1,18 +1,15 @@ -CONFIG_SMP=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_CPU_SUBTYPE_J2=y CONFIG_MEMORY_START=0x1000 -CONFIG_MEMORY_SIZE=0x0400 CONFIG_CPU_BIG_ENDIAN=y -CONFIG_SH_DEVICE_TREE=y -CONFIG_SH_JCORE_SOC=y +CONFIG_SH_OF_BOARD=y CONFIG_HZ_100=y +CONFIG_SMP=y CONFIG_CMDLINE_OVERWRITE=y CONFIG_CMDLINE="console=ttyUL0 earlycon" -CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_NET=y CONFIG_PACKET=y @@ -21,7 +18,6 @@ CONFIG_INET=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_NETDEVICES=y -CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_UARTLITE=y CONFIG_SERIAL_UARTLITE_CONSOLE=y CONFIG_I2C=y @@ -30,8 +26,6 @@ CONFIG_SPI_JCORE=y CONFIG_WATCHDOG=y CONFIG_MMC=y CONFIG_MMC_SPI=y -CONFIG_CLKSRC_JCORE_PIT=y -CONFIG_JCORE_AIC=y CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_IOCHARSET="ascii" @@ -40,3 +34,4 @@ CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_UTF8=y +CONFIG_INIT_STACK_NONE=y -- 2.39.2
[RESEND v7 31/37] sh: Add IO DATA LANDISK dts
IO DATA DEVICE Inc. LANDISK HDL-U devicetree.
Signed-off-by: Yoshinori Sato
---
arch/sh/boot/dts/landisk.dts | 77
1 file changed, 77 insertions(+)
create mode 100644 arch/sh/boot/dts/landisk.dts
diff --git a/arch/sh/boot/dts/landisk.dts b/arch/sh/boot/dts/landisk.dts
new file mode 100644
index ..d3dc52295114
--- /dev/null
+++ b/arch/sh/boot/dts/landisk.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the IO DATA DEVICE LANDISK
+ */
+
+/dts-v1/;
+
+#include "sh7751r.dtsi"
+
+/ {
+ model = "IO DATA Device LANDISK";
+ compatible = "iodata,landisk", "renesas,sh7751r";
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ stdout-path = "serial0:9600n8";
+ };
+
+ memory@c00 {
+ device_type = "memory";
+ reg = <0x0c00 0x400>;
+ };
+
+ julianintc: interrupt-controller@b005 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xb005 0x01>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ /*
+* b7: Not assigned
+* b6: Power switch
+* b5: Not assigned
+* b4: Not assigned
+* b3: PCI-INTD
+* b2: PCI-INTC
+* b1: PCI-INTB
+* b0: PCI-INTA
+*/
+ renesas,enable-reg = <15 11 15 15 8 7 6 5>;
+ };
+};
+
+&extal {
+ clock-frequency = <>;
+};
+
+&cpg {
+ renesas,mode = <5>;
+};
+
+&scif1 {
+ status = "okay";
+};
+
+&pcic {
+ ranges = <0x0200 0 0xfd00 0xfd00 0 0x0100>,
+<0x0100 0 0x 0xfe24 0 0x0004>;
+ dma-ranges = <0x0200 0 0x0c00 0x0c00 0 0x0400>,
+<0x0200 0 0xd000 0xd000 0 0x0001>;
+ interrupt-map = <0x 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 2 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 3 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x 0 0 4 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 1 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 2 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 3 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 4 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 1 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 2 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 3 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 4 &julianintc 6 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map-mask = <0x1800 0 0 7>;
+ status = "okay";
+};
--
2.39.2
[RESEND v7 25/37] dt-binding: sh: cpus: Add SH CPUs json-schema
Renesas SH series and compatible ISA CPUs.
Signed-off-by: Yoshinori Sato
---
.../devicetree/bindings/sh/cpus.yaml | 63 +++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml
diff --git a/Documentation/devicetree/bindings/sh/cpus.yaml
b/Documentation/devicetree/bindings/sh/cpus.yaml
new file mode 100644
index ..9e5640793d76
--- /dev/null
+++ b/Documentation/devicetree/bindings/sh/cpus.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sh/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SuperH CPUs
+
+maintainers:
+ - Yoshinori Sato
+
+description: |+
+ Definition of CPU core with Renesas SuperH and compatible instruction set.
+
+properties:
+ compatible:
+anyOf:
+ - items:
+ - enum:
+ - renesas,sh2a
+ - renesas,sh3
+ - renesas,sh4
+ - renesas,sh4a
+ - jcore,j2
+ - const: renesas,sh2
+ - const: renesas,sh2
+
+ clocks:
+maxItems: 1
+
+ reg:
+maxItems: 1
+
+ device_type:
+const: cpu
+
+required:
+ - compatible
+ - reg
+ - device_type
+
+additionalProperties: true
+
+examples:
+ - |
+#include
+cpus {
+#address-cells = <1>;
+#size-cells = <0>;
+
+cpu: cpu@0 {
+compatible = "renesas,sh4", "renesas,sh2";
+device_type = "cpu";
+reg = <0>;
+clocks = <&cpg SH7750_CPG_ICK>;
+clock-names = "ick";
+icache-size = <16384>;
+icache-line-size = <32>;
+dcache-size = <32768>;
+dcache-line-size = <32>;
+};
+};
+...
--
2.39.2
[RESEND v7 22/37] dt-bindings: display: smi, sm501: SMI SM501 binding json-schema
Signed-off-by: Yoshinori Sato --- .../bindings/display/smi,sm501.yaml | 398 ++ 1 file changed, 398 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/smi,sm501.yaml diff --git a/Documentation/devicetree/bindings/display/smi,sm501.yaml b/Documentation/devicetree/bindings/display/smi,sm501.yaml new file mode 100644 index ..06c6af4fa4a9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/smi,sm501.yaml @@ -0,0 +1,398 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/smi,sm501.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Motion SM501 Mobile Multimedia Companion Chip + +maintainers: + - Yoshinori Sato + +description: | + These DT bindings describe the SM501. + +properties: + compatible: +const: + smi,sm501 + + reg: +maxItems: 2 +description: | + First entry: System Configuration register + Second entry: IO space (Display Controller register) + + interrupts: +description: SM501 interrupt to the cpu should be described here. + + mode: +$ref: /schemas/types.yaml#/definitions/string +description: select a video mode + + edid: +description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + little-endian: +$ref: /schemas/types.yaml#/definitions/flag +description: available on big endian systems, to set different foreign endian. + big-endian: +$ref: /schemas/types.yaml#/definitions/flag +description: available on little endian systems, to set different foreign endian. + + swap-fb-endian: +$ref: /schemas/types.yaml#/definitions/flag +description: swap framebuffer byteorder. + + route-crt-panel: +$ref: /schemas/types.yaml#/definitions/flag +description: Panel output merge to CRT. + + crt: +type: object +description: CRT output control +properties: + edid: +$ref: /schemas/types.yaml#/definitions/uint8-array +description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + smi,flags: +$ref: /schemas/types.yaml#/definitions/string-array +description: Display control flags. +items: + anyOf: +- const: use-init-done +- const: disable-at-exit +- const: use-hwcursor +- const: use-hwaccel +- const: panel-no-fpen +- const: panel-no-vbiasen +- const: panel-inv-fpen +- const: panel-inv-vbiasen +maxItems: 8 + + bpp: +$ref: /schemas/types.yaml#/definitions/uint32 +description: Color depth + + panel: +type: object +description: Panel output control +properties: + edid: +$ref: /schemas/types.yaml#/definitions/uint8-array +description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + smi,flags: +$ref: /schemas/types.yaml#/definitions/string-array +description: Display control flags. +items: + anyOf: +- const: use-init-done +- const: disable-at-exit +- const: use-hwcursor +- const: use-hwaccel +- const: panel-no-fpen +- const: panel-no-vbiasen +- const: panel-inv-fpen +- const: panel-inv-vbiasen +maxItems: 8 + + bpp: +$ref: /schemas/types.yaml#/definitions/uint32 +description: Color depth + + smi,devices: +$ref: /schemas/types.yaml#/definitions/string-array +description: Select SM501 device functions. +items: + anyOf: +- const: usb-host +- const: usb-slave +- const: ssp0 +- const: ssp1 +- const: uart0 +- const: uart1 +- const: fbaccel +- const: ac97 +- const: i2s +- const: gpio +minItems: 1 +maxItems: 10 + + smi,mclk: +$ref: /schemas/types.yaml#/definitions/uint32 +description: mclk frequency. + + smi,m1xclk: +$ref: /schemas/types.yaml#/definitions/uint32 +description: m1xclk frequency. + + misc-timing: +type: object +description: Miscellaneous Timing register values. +properties: + ex: +$ref: /schemas/types.yaml#/definitions/uint32 +description: Extend bus holding time. + + xc: +$ref: /schemas/types.yaml#/definitions/uint32 +description: Xscale clock input select. + + usb-over-current-detect-disable: +$ref: /schemas/types.yaml#/definitions/flag +description: USB host current detection disable (Us=0
[RESEND v7 11/37] pci: pci-sh7751: Add SH7751 PCI driver
Renesas SH7751 CPU Internal PCI Controller driver. Signed-off-by: Yoshinori Sato --- drivers/pci/controller/Kconfig | 9 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pci-sh7751.c | 342 3 files changed, 352 insertions(+) create mode 100644 drivers/pci/controller/pci-sh7751.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index e534c02ee34f..a2fd917a2e03 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -353,6 +353,15 @@ config PCIE_XILINX_CPM Say 'Y' here if you want kernel support for the Xilinx Versal CPM host bridge. +config PCI_SH7751 + bool "Renesas SH7751 PCI controller" + depends on OF + depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST + select PCI_HOST_COMMON + help + Say 'Y' here if you want kernel to support the Renesas SH7751 PCI + Host Bridge driver. + source "drivers/pci/controller/cadence/Kconfig" source "drivers/pci/controller/dwc/Kconfig" source "drivers/pci/controller/mobiveil/Kconfig" diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index f2b19e6174af..aa97e5d74e58 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o +obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ diff --git a/drivers/pci/controller/pci-sh7751.c b/drivers/pci/controller/pci-sh7751.c new file mode 100644 index ..a5340689f737 --- /dev/null +++ b/drivers/pci/controller/pci-sh7751.c @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SH7751 PCI driver + * Copyright (C) 2023 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PCICR and PCICLKCR write enable magic key */ +#define PCIC_WE_KEY(0xa5 << 24) + +/* PCIC registers */ +/* 0x - 0x00ff mapped to PCI device configuration space */ +#define PCIC_PCICR 0x100 /* PCI Control Register */ +#define PCIC_PCICR_TRSBBIT(9) /* Target Read Single */ +#define PCIC_PCICR_BSWPBIT(8) /* Target Byte Swap */ +#define PCIC_PCICR_PLUPBIT(7) /* Enable PCI Pullup */ +#define PCIC_PCICR_ARBMBIT(6) /* PCI Arbitration Mode */ +#define PCIC_PCICR_MD10BIT(5) /* MD10 status */ +#define PCIC_PCICR_MD9 BIT(4) /* MD9 status */ +#define PCIC_PCICR_SERRBIT(3) /* SERR output assert */ +#define PCIC_PCICR_INTABIT(2) /* INTA output assert */ +#define PCIC_PCICR_PRSTBIT(1) /* PCI Reset Assert */ +#define PCIC_PCICR_CFINBIT(0) /* Central Fun. Init Done */ + +#define PCIC_PCILSR0 0x104 /* PCI Local Space Register0 */ +#define PCIC_PCILSR1 0x108 /* PCI Local Space Register1 */ +#define PCIC_PCILAR0 0x10c /* PCI Local Addr Register1 */ +#define PCIC_PCILAR1 0x110 /* PCI Local Addr Register1 */ +#define PCIC_PCIINT0x114 /* PCI Interrupt Register */ +#define PCIC_PCIINTM 0x118 /* PCI Interrupt Mask */ +#define PCIC_PCIALR0x11c /* Error Address Register */ +#define PCIC_PCICLR0x120 /* Error Command/Data */ +#define PCIC_PCIAINT 0x130 /* Arbiter Interrupt Register */ +#define PCIC_PCIAINTM 0x134 /* Arbiter Int. Mask Register */ +#define PCIC_PCIBMLR 0x138 /* Error Bus Master Register */ +#define PCIC_PCIDMABT 0x140 /* DMA Transfer Arb. Register */ +#define PCIC_PCIPAR0x1c0 /* PIO Address Register */ +#define PCIC_PCIMBR0x1c4 /* Memory Base Address */ +#define PCIC_PCIIOBR 0x1c8 /* I/O Base Address Register */ + +#define PCIC_PCIPINT 0x1cc /* Power Mgmnt Int. Register */ +#define PCIC_PCIPINT_D3BIT(1) /* D3 Pwr Mgmt. Interrupt */ +#define PCIC_PCIPINT_D0BIT(0) /* D0 Pwr Mgmt. Interrupt */ + +#define PCIC_PCIPINTM 0x1d0 /* Power Mgmnt Mask Register */ +#define PCIC_PCICLKR 0x1d4 /* Clock Ctrl. Register */ +#define PCIC_PCIBCR1 0x1e0 /* Memory BCR1 Register */ +#define PCIC_PCIBCR2 0x1e4 /* Memory BCR2 Register */ +#define PCIC_PCIWCR1 0x1e8 /* Wait Control 1 Register */ +#define PCIC_PCIWCR2 0x1ec /* Wait Control 2 Register */ +#define PCIC_PCIWCR3 0x1f0 /* Wait Control 3 Register */ +#define PCIC_PCIMCR0x1f4 /* Memory Control Register */ +#define
[RESEND v7 23/37] dt-bindings: display: sm501 register definition helper
Miscellaneous Timing and Miscellaneous Control registers definition. Signed-off-by: Yoshinori Sato --- include/dt-bindings/display/sm501.h | 76 + 1 file changed, 76 insertions(+) create mode 100644 include/dt-bindings/display/sm501.h diff --git a/include/dt-bindings/display/sm501.h b/include/dt-bindings/display/sm501.h new file mode 100644 index ..a6c6943642e4 --- /dev/null +++ b/include/dt-bindings/display/sm501.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef __DT_BINDING_DISPALY_SM501__ +#define __DT_BINDING_DISPALY_SM501__ + +/* Miscellaneous Conntrol */ +#define SM501_MISC_CONTROL_PAD_24 0 +#define SM501_MISC_CONTROL_PAD_12 1 +#define SM501_MISC_CONTROL_PAD_8 2 + +#define SM501_MISC_CONTROL_USBCLK_XTAL 0 +#define SM501_MISC_CONTROL_USBCLK_96MHZ1 +#define SM501_MISC_CONTROL_USBCLK_48MHZ2 + +#define SM501_MISC_CONTROL_RFSH_8US0 +#define SM501_MISC_CONTROL_RFSH_16US 1 +#define SM501_MISC_CONTROL_RFSH_32US 2 +#define SM501_MISC_CONTROL_RFSH_64US 3 + +#define SM501_MISC_CONTROL_HOLD_EMPTY 0 +#define SM501_MISC_CONTROL_HOLD_8TR1 +#define SM501_MISC_CONTROL_HOLD_16TR 2 +#define SM501_MISC_CONTROL_HOLD_24TR 3 +#define SM501_MISC_CONTROL_HOLD_32TR 4 + +/* Miscellaneous timing */ +#define SM501_MISC_TIMING_EX_HOLD_00 +#define SM501_MISC_TIMING_EX_HOLD_16 1 +#define SM501_MISC_TIMING_EX_HOLD_32 2 +#define SM501_MISC_TIMING_EX_HOLD_48 3 +#define SM501_MISC_TIMING_EX_HOLD_64 4 +#define SM501_MISC_TIMING_EX_HOLD_80 5 +#define SM501_MISC_TIMING_EX_HOLD_96 6 +#define SM501_MISC_TIMING_EX_HOLD_112 7 +#define SM501_MISC_TIMING_EX_HOLD_128 8 +#define SM501_MISC_TIMING_EX_HOLD_144 9 +#define SM501_MISC_TIMING_EX_HOLD_160 10 +#define SM501_MISC_TIMING_EX_HOLD_176 11 +#define SM501_MISC_TIMING_EX_HOLD_192 12 +#define SM501_MISC_TIMING_EX_HOLD_208 13 +#define SM501_MISC_TIMING_EX_HOLD_224 14 +#define SM501_MISC_TIMING_EX_HOLD_240 15 + +#define SM501_MISC_TIMING_XC_INTERNAL 0 +#define SM501_MISC_TIMING_XC_HCLK 1 +#define SM501_MISC_TIMING_XC_GPIO 2 + +#define SM501_MISC_TIMING_SM_DIV1 0 +#define SM501_MISC_TIMING_SM_DIV2 1 +#define SM501_MISC_TIMING_SM_DIV4 2 +#define SM501_MISC_TIMING_SM_DIV8 3 +#define SM501_MISC_TIMING_SM_DIV16 4 +#define SM501_MISC_TIMING_SM_DIV32 5 +#define SM501_MISC_TIMING_SM_DIV64 6 +#define SM501_MISC_TIMING_SM_DIV1287 +#define SM501_MISC_TIMING_SM_DIV3 8 +#define SM501_MISC_TIMING_SM_DIV6 9 +#define SM501_MISC_TIMING_SM_DIV12 10 +#define SM501_MISC_TIMING_SM_DIV24 11 +#define SM501_MISC_TIMING_SM_DIV48 12 +#define SM501_MISC_TIMING_SM_DIV96 13 +#define SM501_MISC_TIMING_SM_DIV19214 +#define SM501_MISC_TIMING_SM_DIV38415 + +#define SM501_MISC_TIMING_DIV336MHZ0 +#define SM501_MISC_TIMING_DIV288MHZ1 +#define SM501_MISC_TIMING_DIV240MHZ2 +#define SM501_MISC_TIMING_DIV192MHZ3 + +#define SM501_MISC_TIMING_DELAY_NONE 0 +#define SM501_MISC_TIMING_DELAY_0_51 +#define SM501_MISC_TIMING_DELAY_1_02 +#define SM501_MISC_TIMING_DELAY_1_53 +#define SM501_MISC_TIMING_DELAY_2_04 +#define SM501_MISC_TIMING_DELAY_2_55 + +#endif -- 2.39.2
[RESEND v7 27/37] dt-bindings: ata: ata-generic: Add new targets
Added new ata-generic target. - iodata,usl-5p-ata - renesas,rts7751r2d-ata Each boards have simple IDE Interface. Use ATA generic driver. Signed-off-by: Yoshinori Sato --- Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/ata-generic.yaml b/Documentation/devicetree/bindings/ata/ata-generic.yaml index 0697927f3d7e..1025b3b351d0 100644 --- a/Documentation/devicetree/bindings/ata/ata-generic.yaml +++ b/Documentation/devicetree/bindings/ata/ata-generic.yaml @@ -18,6 +18,8 @@ properties: - enum: - arm,vexpress-cf - fsl,mpc8349emitx-pata + - iodata,usl-5p-ata + - renesas,rts7751r2d-ata - const: ata-generic reg: -- 2.39.2
[RESEND v7 26/37] dt-bindings: vendor-prefixes: Add iodata
Add IO DATA DEVICE INC. https://www.iodata.com/ Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b97d298b3eb6..769f9b8c9bd3 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -708,6 +708,8 @@ patternProperties: description: Inventec "^inversepath,.*": description: Inverse Path + "^iodata,.*": +description: IO DATA DEVICE Inc. "^iom,.*": description: Iomega Corporation "^irondevice,.*": -- 2.39.2
[RESEND v7 24/37] mfd: sm501: Convert platform_data to OF property
Various parameters of SM501 can be set using platform_data,
so parameters cannot be passed in the DeviceTree target.
Expands the parameters set in platform_data so that they can be
specified using DeviceTree properties.
Signed-off-by: Yoshinori Sato
---
drivers/mfd/sm501.c | 315 ++
drivers/video/fbdev/sm501fb.c | 106
2 files changed, 421 insertions(+)
diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c
index b3592982a83b..98a69e254f5f 100644
--- a/drivers/mfd/sm501.c
+++ b/drivers/mfd/sm501.c
@@ -82,6 +82,16 @@ struct sm501_devdata {
unsigned int rev;
};
+struct sm501_config_props_uint {
+ char *name;
+ u32 shift;
+};
+
+struct sm501_config_props_flag {
+ char *clr_name;
+ char *set_name;
+ u32 bit;
+};
#define MHZ (1000 * 1000)
@@ -1370,6 +1380,305 @@ static int sm501_init_dev(struct sm501_devdata *sm)
return 0;
}
+static const struct sm501_config_props_uint misc_timing[] = {
+ {"delay",0},
+ {"-",3},
+ {"divider", 4},
+ {"-",6},
+ {"sm0", 8},
+ {"-", 12},
+ {"sm1", 16},
+ {"-", 20},
+ {"xc", 24},
+ {"-", 26},
+ {"ex", 28},
+ {NULL, 32},
+};
+
+static const struct sm501_config_props_flag misc_timing_flag[] = {
+ {"usb-host-normal", "usb-host-simulation",3},
+ {"no-acpi-control", "acpi-control", 6},
+ {"pll-debug-input", "pll-debug-output", 7},
+ {"sdram-clock-mode0-288mhz", "sdram-clock-mode0-div", 12},
+ {"sdram-clock-mode1-288mhz", "sdram-clock-mode1-div", 20},
+ {"usb-over-current-detect-disable",
+"usb-over-current-detect-enable", 23},
+ {},
+};
+
+static const struct sm501_config_props_uint misc_control[] = {
+ {"hold", 18},
+ {"refresh", 21},
+ {"-",23},
+ {"usbclk", 28},
+ {"pad", 30},
+ {NULL, 32},
+};
+
+static const struct sm501_config_props_flag misc_control_flag[] = {
+ {"vr-mmio-30mb","vr-mmio-62mb", 4},
+ {"usb-port-master", "usb-port-slave", 9},
+ {"burst-length-8", "burst-length-1", 10},
+ {"usb-slave-cpu", "usb-slave-8051", 11},
+ {"dac-power-enable","dac-power-disable", 12},
+ {"pll-clock-count-disable", "pll-clock-count-enable", 15},
+ {"interrupt-normal","interrupt-invarted", 16},
+ {"sh-ready-low","sh-ready-high", 17},
+ {"xtal-freq-24mhz", "xtal-freq-12mhz", 24},
+ {"panel-data-18bit","panel-dtat-24bit",25},
+ {"latch-address-disable", "latch-address-enable",26},
+ {"uart1", "ssp1",27},
+ {},
+};
+
+/* Read configuration values */
+static void sm501_of_read_config(struct device *dev, struct device_node *np,
+const char *prefix,
+const struct sm501_config_props_uint *props,
+const struct sm501_config_props_flag
*props_flag,
+struct sm501_reg_init *ret)
+{
+ struct device_node *child;
+ char *name;
+ u32 shift;
+ u32 width;
+ u32 mask;
+ u32 val;
+
+ ret->mask = ~0;
+ ret->set = 0;
+
+ child = of_get_child_by_name(np, prefix);
+ if (!child)
+ return;
+
+ while (props->name) {
+ name = props->name;
+ shift = props->shift;
+ props++;
+
+ if (name[0] == '-' ||
+ of_property_read_u32(child, name, &val))
+ continue;
+
+ width = props->shift - shift;
+ mask = (1 << width) - 1;
+ if (mask < val) {
+ dev_warn(dev, "%s invalid value %d", name, val);
+ continue;
+ }
+ mask = ~(mask << shift);
+ ret->mask &= mask;
+ ret->set |= val << shift;
+ }
+ while (props_flag->clr_name) {
+ val = ~0;
+ if (of_property_read_b
[RESEND v7 17/37] dt-bindings: interrupt-controller: renesas, sh7751-intc: Add json-schema
Renesas SH7751 INTC json-schema.
Signed-off-by: Yoshinori Sato
---
.../renesas,sh7751-intc.yaml | 53 +++
1 file changed, 53 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
new file mode 100644
index ..fb924eff465d
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id:
http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 Interrupt Controller
+
+maintainers:
+ - Yoshinori Sato
+
+properties:
+ compatible:
+items:
+ - const: renesas,sh7751-intc
+
+ '#interrupt-cells':
+const: 1
+
+ interrupt-controller: true
+
+ reg:
+maxItems: 2
+
+ reg-names:
+items:
+ - const: ICR
+ - const: INTPRI00
+
+ renesas,icr-irlm:
+$ref: /schemas/types.yaml#/definitions/flag
+description: If true four independent interrupt requests mode (ICR.IRLM is
1).
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - '#interrupt-cells'
+ - interrupt-controller
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+shintc: interrupt-controller@ffd0 {
+compatible = "renesas,sh7751-intc";
+reg = <0xffd0 14>, <0xfe08 128>;
+reg-names = "ICR", "INTPRI00";
+#interrupt-cells = <1>;
+interrupt-controller;
+};
+...
--
2.39.2
[RESEND v7 12/37] dt-bindings: pci: pci-sh7751: Add SH7751 PCI
Renesas SH7751 PCI Controller json-schema.
Signed-off-by: Yoshinori Sato
---
.../bindings/pci/renesas,sh7751-pci.yaml | 89 +++
1 file changed, 89 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
diff --git a/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
new file mode 100644
index ..115c2bb67339
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/renesas,sh7751-pci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 PCI Host controller
+
+maintainers:
+ - Yoshinori Sato
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+const: renesas,sh7751-pci
+
+ reg:
+minItems: 2
+maxItems: 2
+
+ reg-names:
+items:
+ - const: PCI Controller
+ - const: Bus State Controller
+
+ "#interrupt-cells":
+const: 1
+
+ "#address-cells":
+const: 3
+
+ "#size-cells":
+const: 2
+
+ ranges: true
+
+ dma-ranges: true
+
+ interrupt-controller: true
+
+ renesas,bus-arbit-round-robin:
+$ref: /schemas/types.yaml#/definitions/flag
+description: |
+ Set DMA bus arbitration to round robin.
+
+required:
+ - compatible
+ - reg
+ - "#interrupt-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - interrupt-map
+ - interrupt-map-mask
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+pci@fe20 {
+compatible = "renesas,sh7751-pci";
+#address-cells = <3>;
+#size-cells = <2>;
+#interrupt-cells = <1>;
+interrupt-controller;
+device_type = "pci";
+bus-range = <0 0>;
+ranges = <0x0200 0 0xfd00 0xfd00 0 0x0100>,
+ <0x0100 0 0x 0xfe24 0 0x0004>;
+dma-ranges = <0x0200 0 0xc00 0x0c00 0 0x0400>;
+reg = <0xfe20 0x0400>,
+ <0xff80 0x0100>;
+interrupt-map = <0x 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+<0x 0 0 2 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+<0x 0 0 3 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+<0x 0 0 4 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 1 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 2 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 3 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 4 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 1 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 2 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 3 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 4 &julianintc 6 IRQ_TYPE_LEVEL_LOW>;
+interrupt-map-mask = <0x1800 0 0 7>;
+};
--
2.39.2
[RESEND v7 08/37] clocksource: sh_tmu: CLOCKSOURCE support.
Allows initialization as CLOCKSOURCE.
Signed-off-by: Yoshinori Sato
---
drivers/clocksource/sh_tmu.c | 198 ---
1 file changed, 134 insertions(+), 64 deletions(-)
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index be81c00f..59f9da7fd987 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -17,6 +17,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -51,6 +53,7 @@ struct sh_tmu_channel {
struct sh_tmu_device {
struct platform_device *pdev;
+ struct device_node *np;
void __iomem *mapbase;
struct clk *clk;
@@ -65,6 +68,7 @@ struct sh_tmu_device {
bool has_clockevent;
bool has_clocksource;
+ const char *name;
};
#define TSTR -1 /* shared register */
@@ -148,8 +152,8 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch)
/* enable clock */
ret = clk_enable(ch->tmu->clk);
if (ret) {
- dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
- ch->index);
+ pr_err("%s ch%u: cannot enable clock\n",
+ ch->tmu->name, ch->index);
return ret;
}
@@ -174,9 +178,10 @@ static int sh_tmu_enable(struct sh_tmu_channel *ch)
if (ch->enable_count++ > 0)
return 0;
- pm_runtime_get_sync(&ch->tmu->pdev->dev);
- dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
-
+ if (ch->tmu->pdev) {
+ pm_runtime_get_sync(&ch->tmu->pdev->dev);
+ dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
+ }
return __sh_tmu_enable(ch);
}
@@ -202,8 +207,10 @@ static void sh_tmu_disable(struct sh_tmu_channel *ch)
__sh_tmu_disable(ch);
- dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
- pm_runtime_put(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev) {
+ dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
+ pm_runtime_put(&ch->tmu->pdev->dev);
+ }
}
static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
@@ -245,7 +252,7 @@ static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
+static inline struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
{
return container_of(cs, struct sh_tmu_channel, cs);
}
@@ -292,7 +299,8 @@ static void sh_tmu_clocksource_suspend(struct clocksource
*cs)
if (--ch->enable_count == 0) {
__sh_tmu_disable(ch);
- dev_pm_genpd_suspend(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev)
+ dev_pm_genpd_suspend(&ch->tmu->pdev->dev);
}
}
@@ -304,7 +312,8 @@ static void sh_tmu_clocksource_resume(struct clocksource
*cs)
return;
if (ch->enable_count++ == 0) {
- dev_pm_genpd_resume(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev)
+ dev_pm_genpd_resume(&ch->tmu->pdev->dev);
__sh_tmu_enable(ch);
}
}
@@ -324,14 +333,14 @@ static int sh_tmu_register_clocksource(struct
sh_tmu_channel *ch,
cs->mask = CLOCKSOURCE_MASK(32);
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
- dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
-ch->index);
+ pr_info("%s ch%u: used as clock source\n",
+ ch->tmu->name, ch->index);
clocksource_register_hz(cs, ch->tmu->rate);
return 0;
}
-static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
+static inline struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device
*ced)
{
return container_of(ced, struct sh_tmu_channel, ced);
}
@@ -364,8 +373,8 @@ static int sh_tmu_clock_event_set_state(struct
clock_event_device *ced,
if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
sh_tmu_disable(ch);
- dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n",
-ch->index, periodic ? "periodic" : "oneshot");
+ pr_info("%s ch%u: used for %s clock events\n",
+ ch->tmu->name, ch->index, periodic ? "periodic" : "oneshot");
sh_tmu_clock_event_start(ch, periodic);
return 0;
}
@@ -417,20 +426,22 @@ static void sh_tmu_register_clockevent(struct
sh_tmu_channel *ch,
ced->set_state_shutdown = sh_tmu_clock_event_shutdown;
ced->set_state_period
[RESEND v7 21/37] dt-bindings: serial: renesas, scif: Add scif-sh7751.
Add Renesas SH7751 SCIF. Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 4610a5bd580c..590f88e2ced9 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -18,6 +18,7 @@ properties: - items: - enum: - renesas,scif-r7s72100 # RZ/A1H + - renesas,scif-sh7751 # SH7751 - const: renesas,scif # generic SCIF compatible UART - items: -- 2.39.2
[RESEND v7 19/37] dt-bindings: interrupt-controller: renesas, sh7751-irl-ext: Add json-schema
Renesas SH7751 external interrupt encoder json-schema.
Signed-off-by: Yoshinori Sato
---
.../renesas,sh7751-irl-ext.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
new file mode 100644
index ..fc174c0467e7
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id:
http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 external interrupt encoder with enable regs.
+
+maintainers:
+ - Yoshinori Sato
+
+description:
+ This is the generally used external interrupt encoder on SH7751 based boards.
+
+properties:
+ compatible:
+items:
+ - const: renesas,sh7751-irl-ext
+
+ reg: true
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+const: 2
+
+ '#address-cells':
+const: 0
+
+ renesas,set-to-disable:
+$ref: /schemas/types.yaml#/definitions/flag
+description: Invert enable registers. Setting the bit to 0 enables
interrupts.
+
+ renesas,enable-reg:
+$ref: /schemas/types.yaml#/definitions/uint32-array
+description: |
+ IRQ enable register bit mapping
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+ - renesas,enable-reg
+
+additionalProperties: false
+
+examples:
+ - |
+r2dintc: interrupt-controller@a400 {
+compatible = "renesas,sh7751-irl-ext";
+reg = <0xa400 0x02>;
+interrupt-controller;
+#address-cells = <0>;
+#interrupt-cells = <1>;
+renesas,enable-reg = <12 9 10 3 0 4 1 2 8 5 6 7 15 15 15 11>;
+};
--
2.39.2
[RESEND v7 05/37] sh: GENERIC_IRQ_CHIP support for CONFIG_OF=y
Remove unused function prototype.
Add helper update_sr_imask. use for SH7751 irq driver.
Add stub intc_finalize.
Signed-off-by: Yoshinori Sato
---
arch/sh/include/asm/io.h | 2 ++
arch/sh/include/asm/irq.h | 10 --
arch/sh/kernel/cpu/Makefile| 5 +
arch/sh/kernel/cpu/irq/imask.c | 17 +
include/linux/sh_intc.h| 7 ++-
5 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index cf5eab840d57..5c544cf5201b 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -121,7 +121,9 @@ __BUILD_MEMORY_STRING(__raw_, q, u64)
#define ioport_map ioport_map
#define ioport_unmap ioport_unmap
+#ifndef CONFIG_SH_DEVICE_TREE
#define pci_iounmap pci_iounmap
+#endif
#define ioread8 ioread8
#define ioread16 ioread16
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
index 0f384b1f45ca..3d897229dcc4 100644
--- a/arch/sh/include/asm/irq.h
+++ b/arch/sh/include/asm/irq.h
@@ -16,8 +16,8 @@
/*
* Simple Mask Register Support
*/
-extern void make_maskreg_irq(unsigned int irq);
-extern unsigned short *irq_mask_register;
+
+void update_sr_imask(unsigned int irq, bool enable);
/*
* PINT IRQs
@@ -54,4 +54,10 @@ extern void irq_finish(unsigned int irq);
#include
+/* SH3/4 INTC stuff */
+/* IRL level 0 - 15 */
+#define NR_IRL 15
+/* IRL0 -> IRQ16 */
+#define IRL_BASE_IRQ 16
+
#endif /* __ASM_SH_IRQ_H */
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index e00ebf134985..ad12807fae9c 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -20,7 +20,4 @@ ifndef CONFIG_COMMON_CLK
obj-y += clock.o
obj-$(CONFIG_SH_CLK_CPG_LEGACY)+= clock-cpg.o
endif
-ifndef CONFIG_GENERIC_IRQ_CHIP
-obj-y += irq/
-endif
-obj-y += init.o fpu.o pfc.o proc.o
+obj-y += init.o fpu.o pfc.o proc.o irq/
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
index 572585c3f2fd..7589ca7c506c 100644
--- a/arch/sh/kernel/cpu/irq/imask.c
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -51,6 +51,7 @@ static inline void set_interrupt_registers(int ip)
: "t");
}
+#ifndef CONFIG_GENERIC_IRQ_CHIP
static void mask_imask_irq(struct irq_data *data)
{
unsigned int irq = data->irq;
@@ -83,3 +84,19 @@ void make_imask_irq(unsigned int irq)
irq_set_chip_and_handler_name(irq, &imask_irq_chip, handle_level_irq,
"level");
}
+#else
+void update_sr_imask(unsigned int irq, bool enable)
+{
+ if (enable) {
+ set_bit(irq, imask_mask);
+ interrupt_priority = IMASK_PRIORITY -
+ find_first_bit(imask_mask, IMASK_PRIORITY);
+ } else {
+ clear_bit(irq, imask_mask);
+ if (interrupt_priority < IMASK_PRIORITY - irq)
+ interrupt_priority = IMASK_PRIORITY - irq;
+ }
+ set_interrupt_registers(interrupt_priority);
+}
+EXPORT_SYMBOL(update_sr_imask);
+#endif
diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h
index 27ae79191bdc..994b5b05a0d7 100644
--- a/include/linux/sh_intc.h
+++ b/include/linux/sh_intc.h
@@ -139,8 +139,13 @@ struct intc_desc symbol __initdata = {
\
int register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);
int intc_irq_lookup(const char *chipname, intc_enum enum_id);
+#ifndef CONFIG_SH_DEVICE_TREE
void intc_finalize(void);
-
+#else
+static inline void intc_finalize(void)
+{
+}
+#endif
#ifdef CONFIG_INTC_USERIMASK
int register_intc_userimask(unsigned long addr);
#else
--
2.39.2
[RESEND v7 18/37] irqchip: SH7751 external interrupt encoder with enable gate.
SH7751 have 15 level external interrupt.
It is typically connected to the CPU through a priority encoder
that can suppress requests.
This driver provides a way to control those hardware with irqchip.
Signed-off-by: Yoshinori Sato
---
drivers/irqchip/Kconfig | 7 +
drivers/irqchip/Makefile| 2 +
drivers/irqchip/irq-renesas-sh7751irl.c | 221
3 files changed, 230 insertions(+)
create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 33badb5b4f00..7670fcd6757d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -698,4 +698,11 @@ config RENESAS_SH7751_INTC
Support for the Renesas SH7751 On-chip interrupt controller.
And external interrupt encoder for some targets.
+config RENESAS_SH7751IRL_INTC
+ bool "Renesas SH7751 based target IRL encoder support."
+ depends on RENESAS_SH7751_INTC
+ help
+ Support for External Interrupt encoder
+ on the some Renesas SH7751 based target.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 51855034a895..bc21d65441f2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -122,3 +122,5 @@ obj-$(CONFIG_APPLE_AIC) +=
irq-apple-aic.o
obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
+obj-$(CONFIG_RENESAS_SH7751IRL_INTC) += irq-renesas-sh7751irl.o
+
diff --git a/drivers/irqchip/irq-renesas-sh7751irl.c
b/drivers/irqchip/irq-renesas-sh7751irl.c
new file mode 100644
index ..5990f2cd9a3d
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-sh7751irl.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SH7751 based board external interrupt level encoder driver
+ * (Renesas RTS7751R2D / IO DATA DEVICE LANDISK, USL-5P)
+ *
+ * Copyright (C) 2023 Yoshinori Sato
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct sh7751irl_intc_priv {
+ struct irq_domain *irq_domain;
+ void __iomem *base;
+ unsigned int width;
+ bool invert;
+ u32 enable_bit[NR_IRL];
+};
+
+static inline unsigned long get_reg(void __iomem *addr, unsigned int w)
+{
+ switch (w) {
+ case 8:
+ return __raw_readb(addr);
+ case 16:
+ return __raw_readw(addr);
+ case 32:
+ return __raw_readl(addr);
+ default:
+ /* The size is checked when reading the properties. */
+ pr_err("%s: Invalid width %d", __FILE__, w);
+ return 0;
+ }
+}
+
+static inline void set_reg(void __iomem *addr, unsigned int w, unsigned long
val)
+{
+ switch (w) {
+ case 8:
+ __raw_writeb(val, addr);
+ break;
+ case 16:
+ __raw_writew(val, addr);
+ break;
+ case 32:
+ __raw_writel(val, addr);
+ break;
+ default:
+ pr_err("%s: Invalid width %d", __FILE__, w);
+ }
+}
+
+static inline struct sh7751irl_intc_priv *irq_data_to_priv(struct irq_data
*data)
+{
+ return data->domain->host_data;
+}
+
+static void irl_endisable(struct irq_data *data, unsigned int enable)
+{
+ struct sh7751irl_intc_priv *priv;
+ unsigned long val;
+ unsigned int irl;
+
+ priv = irq_data_to_priv(data);
+ irl = irqd_to_hwirq(data) - IRL_BASE_IRQ;
+
+ if (irl < NR_IRL && priv->enable_bit[irl] < priv->width) {
+ if (priv->invert)
+ enable = !enable;
+
+ val = get_reg(priv->base, priv->width);
+ if (enable)
+ set_bit(priv->enable_bit[irl], &val);
+ else
+ clear_bit(priv->enable_bit[irl], &val);
+ set_reg(priv->base, priv->width, val);
+ } else {
+ pr_err("%s: Invalid register define in IRL %u", __FILE__, irl);
+ }
+}
+
+static void sh7751irl_intc_disable_irq(struct irq_data *data)
+{
+ irl_endisable(data, 0);
+}
+
+static void sh7751irl_intc_enable_irq(struct irq_data *data)
+{
+ irl_endisable(data, 1);
+}
+
+static struct irq_chip sh7751irl_intc_chip = {
+ .name = "SH7751IRL-INTC",
+ .irq_enable = sh7751irl_intc_enable_irq,
+ .irq_disable= sh7751irl_intc_disable_irq,
+};
+
+static int sh7751irl_intc_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &sh7751irl_intc_chip, handle_level_irq);
+
[RESEND v7 20/37] serial: sh-sci: fix SH4 OF support.
- fix earlycon name.
- fix earlyprintk hung (NULL pointer reference).
- fix SERIAL_SH_SCI_EARLYCON enablement
Signed-off-by: Yoshinori Sato
Reviewed-by: Geert Uytterhoeven
---
drivers/tty/serial/Kconfig | 2 +-
drivers/tty/serial/sh-sci.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index ffcf4882b25f..dfe5fd436816 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -661,7 +661,7 @@ config SERIAL_SH_SCI_EARLYCON
depends on SERIAL_SH_SCI=y
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
- default ARCH_RENESAS
+ default ARCH_RENESAS || SUPERH
config SERIAL_SH_SCI_DMA
bool "DMA support" if EXPERT
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index e512eaa57ed5..46466fb5a637 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2717,7 +2717,7 @@ static int sci_remap_port(struct uart_port *port)
if (port->membase)
return 0;
- if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
+ if ((port->dev && port->dev->of_node) || (port->flags & UPF_IOREMAP)) {
port->membase = ioremap(port->mapbase, sport->reg_size);
if (unlikely(!port->membase)) {
dev_err(port->dev, "can't remap port#%d\n", port->line);
@@ -3545,8 +3545,8 @@ static int __init hscif_early_console_setup(struct
earlycon_device *device,
OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044",
rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r7s9210",
rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r9a07g044",
rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
--
2.39.2
[RESEND v7 16/37] irqchip: Add SH7751 INTC driver
Renesas SH7751 Internal interrupt controller driver.
Signed-off-by: Yoshinori Sato
---
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-renesas-sh7751.c | 282 +++
3 files changed, 291 insertions(+)
create mode 100644 drivers/irqchip/irq-renesas-sh7751.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 72c07a12f5e1..33badb5b4f00 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -690,4 +690,12 @@ config SUNPLUS_SP7021_INTC
chained controller, routing all interrupt source in P-Chip to
the primary controller on C-Chip.
+config RENESAS_SH7751_INTC
+ bool "Renesas SH7751 Interrupt Controller"
+ depends on SH_DEVICE_TREE || COMPILE_TEST
+ select IRQ_DOMAIN_HIERARCHY
+ help
+ Support for the Renesas SH7751 On-chip interrupt controller.
+ And external interrupt encoder for some targets.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index ec4a18380998..51855034a895 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -121,3 +121,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o
obj-$(CONFIG_APPLE_AIC)+= irq-apple-aic.o
obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
+obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
diff --git a/drivers/irqchip/irq-renesas-sh7751.c
b/drivers/irqchip/irq-renesas-sh7751.c
new file mode 100644
index ..91d6dc3ed04c
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-sh7751.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7751 interrupt controller driver
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct ipr {
+ u16 off;
+ u16 idx;
+};
+
+struct sh7751_intc_priv {
+ const struct ipr *iprmap;
+ void __iomem *base;
+ void __iomem *intpri00;
+ bool irlm;
+};
+
+enum {
+ R_ICR = 0x00,
+ R_IPR = 0x04,
+ R_INTPRI00= 0x00,
+ R_INTREQ00= 0x20,
+ R_INTMSK00= 0x40,
+ R_INTMSKCLR00 = 0x60,
+};
+
+#define ICR_IRLM BIT(7)
+
+/*
+ * SH7751 IRQ mapping
+ * IRQ16 - 63: Group0 - IPRA to IPRD
+ * IRQ16 - 31: external IRL input (ICR.IRLM is 0)
+ * IRQ80 - 92: Group1 - INTPRI00
+ */
+#define IRQ_START 16
+#define MAX_IRL(IRQ_START + NR_IRL)
+#define GRP0_IRQ_END 63
+#define GRP1_IRQ_START 80
+#define IRQ_END92
+
+#define NR_IPRMAP0 (GRP0_IRQ_END - IRQ_START + 1)
+#define NR_IPRMAP1 (IRQ_END - GRP1_IRQ_START)
+#define IPR_PRI_MASK 0x000f
+
+#define IPRA 0
+#define IPRB 4
+#define IPRC 8
+#define IPRD 12
+#define INTPRI00 256
+#define IPR_B1212
+#define IPR_B8 8
+#define IPR_B4 4
+#define IPR_B0 0
+
+/* SH7751 EVT to IPR mapping table */
+static const struct ipr sh7751_iprmap[] = {
+ [evt2irq(0x240)] = {IPRD, IPR_B12}, /* IRL0 (ICR.IRLM=1) */
+ [evt2irq(0x2a0)] = {IPRD, IPR_B8}, /* IRL1 (ICR.IRLM=1) */
+ [evt2irq(0x300)] = {IPRD, IPR_B4}, /* IRL2 (ICR.IRLM=1) */
+ [evt2irq(0x360)] = {IPRD, IPR_B0}, /* IRL3 (ICR.IRLM=1) */
+ [evt2irq(0x400)] = {IPRA, IPR_B12}, /* TMU0 */
+ [evt2irq(0x420)] = {IPRA, IPR_B8}, /* TMU1 */
+ [evt2irq(0x440)] = {IPRA, IPR_B4}, /* TMU2 TNUI */
+ [evt2irq(0x460)] = {IPRA, IPR_B4}, /* TMU2 TICPI */
+ [evt2irq(0x480)] = {IPRA, IPR_B0}, /* RTC ATI */
+ [evt2irq(0x4a0)] = {IPRA, IPR_B0}, /* RTC PRI */
+ [evt2irq(0x4c0)] = {IPRA, IPR_B0}, /* RTC CUI */
+ [evt2irq(0x4e0)] = {IPRB, IPR_B4}, /* SCI ERI */
+ [evt2irq(0x500)] = {IPRB, IPR_B4}, /* SCI RXI */
+ [evt2irq(0x520)] = {IPRB, IPR_B4}, /* SCI TXI */
+ [evt2irq(0x540)] = {IPRB, IPR_B4}, /* SCI TEI */
+ [evt2irq(0x560)] = {IPRB, IPR_B12}, /* WDT */
+ [evt2irq(0x580)] = {IPRB, IPR_B8}, /* REF RCMI */
+ [evt2irq(0x5a0)] = {IPRB, IPR_B4}, /* REF ROVI */
+ [evt2irq(0x600)] = {IPRC, IPR_B0}, /* H-UDI */
+ [evt2irq(0x620)] = {IPRC, IPR_B12}, /* GPIO */
+ [evt2irq(0x640)] = {IPRC, IPR_B8}, /* DMAC DMTE0 */
+ [evt2irq(0x660)] = {IPRC, IPR_B8}, /* DMAC DMTE1 */
+ [evt2irq(0x680)] = {IPRC, IPR_B8}, /* DMAC DMTE2 */
+ [evt2irq(0x6a0)] = {IPRC, IPR_B8}, /* DMAC DMTE3 */
+ [evt2irq(0x6c0)] = {IPRC, IPR_B8}, /* DMAC DMAE */
+ [evt2irq(0x700)] = {IPRC, IPR_B4}, /* SCIF ERI */
+ [evt2irq(0x720)] = {IPRC, IPR_B4}, /* SCIF RXI */
+ [evt2irq(0x740)] = {IPRC, IPR_B4},
[RESEND v7 09/37] dt-binding: Add compatible SH7750 SoC
Signed-off-by: Yoshinori Sato --- Documentation/devicetree/bindings/timer/renesas,tmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml index 84bbe15028a1..265d286ffb2f 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml @@ -39,6 +39,7 @@ properties: - renesas,tmu-r8a779a0 # R-Car V3U - renesas,tmu-r8a779f0 # R-Car S4-8 - renesas,tmu-r8a779g0 # R-Car V4H + - renesas,tmu-sh7750 # SH7750 - const: renesas,tmu reg: @@ -96,6 +97,7 @@ if: - renesas,tmu-r8a7740 - renesas,tmu-r8a7778 - renesas,tmu-r8a7779 +- renesas,tmu-sh7750 then: required: - resets -- 2.39.2
[RESEND v7 15/37] clk: renesas: Add SH7750/7751 CPG Driver
Renesas SH7750 and SH7751 series CPG driver.
This driver supported frequency control and clock gating.
Signed-off-by: Yoshinori Sato
---
drivers/clk/renesas/Kconfig | 13 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/clk-sh7750.c | 480 +++
3 files changed, 491 insertions(+), 3 deletions(-)
create mode 100644 drivers/clk/renesas/clk-sh7750.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index d252150402e8..482efcb6e76e 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
config CLK_RENESAS
- bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
- default y if ARCH_RENESAS
+ bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS &&
!SUPERH
+ default y if ARCH_RENESAS || SUPERH
select CLK_EMEV2 if ARCH_EMEV2
select CLK_RZA1 if ARCH_R7S72100
select CLK_R7S9210 if ARCH_R7S9210
@@ -41,6 +41,9 @@ config CLK_RENESAS
select CLK_R9A08G045 if ARCH_R9A08G045
select CLK_R9A09G011 if ARCH_R9A09G011
select CLK_SH73A0 if ARCH_SH73A0
+ select CLK_SH7750 if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
+CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751 || \
+CPU_SUBTYPE_SH7751R
if CLK_RENESAS
@@ -198,7 +201,6 @@ config CLK_SH73A0
select CLK_RENESAS_CPG_MSTP
select CLK_RENESAS_DIV6
-
# Family
config CLK_RCAR_CPG_LIB
bool "CPG/MSSR library functions" if COMPILE_TEST
@@ -228,6 +230,11 @@ config CLK_RZG2L
bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if
COMPILE_TEST
select RESET_CONTROLLER
+config CLK_SH7750
+ bool "Renesas SH7750/7751 family clock support" if COMPILE_TEST
+ help
+ This is a driver for SH7750 / SH7751 CPG.
+
# Generic
config CLK_RENESAS_CPG_MSSR
bool "CPG/MSSR clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index f7e18679c3b8..ea0ffa8d59c4 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A08G045)+= r9a08g045-cpg.o
obj-$(CONFIG_CLK_R9A09G011)+= r9a09g011-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
+obj-$(CONFIG_CLK_SH7750) += clk-sh7750.o
# Family
obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
diff --git a/drivers/clk/renesas/clk-sh7750.c b/drivers/clk/renesas/clk-sh7750.c
new file mode 100644
index ..043269d31200
--- /dev/null
+++ b/drivers/clk/renesas/clk-sh7750.c
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7750/51 CPG driver
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* PCLK divide rate selector */
+static const struct clk_div_table pdiv_table[] = {
+ { .val = 0, .div = 2, },
+ { .val = 1, .div = 3, },
+ { .val = 2, .div = 4, },
+ { .val = 3, .div = 6, },
+ { .val = 4, .div = 8, },
+ { }
+};
+
+/* ICLK and BCLK divide rate selector */
+static const struct clk_div_table div_table[] = {
+ { .val = 0, .div = 1, },
+ { .val = 1, .div = 2, },
+ { .val = 2, .div = 3, },
+ { .val = 3, .div = 4, },
+ { .val = 4, .div = 6, },
+ { .val = 5, .div = 8, },
+ { }
+};
+
+struct cpg_priv {
+ struct clk_hw hw;
+ spinlock_t clklock;
+ void __iomem *frqcr;
+ void __iomem *clkstp00;
+ u32 mode;
+ u32 feat;
+};
+
+/* CPG feature flag */
+#define CPG_DIV1 BIT(0) /* 7750, 7750S, 7751 */
+#define MSTP_CR2 BIT(1) /* 7750S, 7750R, 7751, 7751R */
+#define MSTP_CLKSTPBIT(2) /* 7750R, 7751, 7751R */
+#define MSTP_CSTP2 BIT(3) /* 7751, 7751R */
+
+enum {
+ CPG_SH7750,
+ CPG_SH7750S,
+ CPG_SH7750R,
+ CPG_SH7751,
+ CPG_SH7751R,
+};
+
+static const u32 cpg_feature[] = {
+ [CPG_SH7750] = CPG_DIV1,
+ [CPG_SH7750S] = CPG_DIV1 | MSTP_CR2,
+ [CPG_SH7750R] = MSTP_CR2 | MSTP_CLKSTP,
+ [CPG_SH7751] = CPG_DIV1 | MSTP_CR2 | MSTP_CLKSTP | MSTP_CSTP2,
+ [CPG_SH7751R] = MSTP_CR2 | MSTP_CLKSTP | MSTP_CSTP2,
+};
+
+enum clk_type {CLK_DIV, CLK_STBCR, CLK_STBCR2, CLK_CLKSTP00};
+
+enum {
+ FRQCR = 0,
+ STBCR = 4,
+ WTCNT = 8,
+ WTCSR = 12,
+ STBCR2 = 16,
+ CLKSTP00 = 0,
+ CLKSTPCLR00 = 8,
+};
+
+static struct cpg_priv *cpg_data;
+
+#define to_priv(_hw) container_of(_hw, struct cpg_priv, hw)
+
+#define FRQCR_PLL1EN BIT(10)
+static const unsigned int pll1mult[] = { 12, 12, 6, 12, 6, 12, 1};
+
+static unsigned long pll_recalc_rate(struct clk_hw *hw,
+
[RESEND v7 13/37] dt-bindings: clock: sh7750-cpg: Add renesas, sh7750-cpg header.
SH7750 CPG Clock output define.
Signed-off-by: Yoshinori Sato
---
.../bindings/clock/renesas,sh7750-cpg.yaml| 105 ++
include/dt-bindings/clock/sh7750-cpg.h| 26 +
2 files changed, 131 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
create mode 100644 include/dt-bindings/clock/sh7750-cpg.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
new file mode 100644
index ..04c10b0834ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7750/7751 Clock Pulse Generator (CPG)
+
+maintainers:
+ - Yoshinori Sato
+
+description:
+ The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
+ includes PLLs, and variable ratio dividers.
+
+ The CPG may also provide a Clock Domain for SoC devices, in combination with
+ the CPG Module Stop (MSTP) Clocks.
+
+properties:
+ compatible:
+enum:
+ - renesas,sh7750-cpg # SH7750
+ - renesas,sh7750s-cpg# SH775S
+ - renesas,sh7750r-cpg# SH7750R
+ - renesas,sh7751-cpg # SH7751
+ - renesas,sh7751r-cpg# SH7751R
+
+ reg: true
+
+ reg-names: true
+
+ clocks:
+maxItems: 1
+
+ clock-names:
+const: extal
+
+ '#clock-cells':
+const: 1
+
+ renesas,mode:
+description: Board-specific settings of the MD[0-2] pins on SoC
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 0
+maximum: 6
+
+ '#power-domain-cells':
+const: 0
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - renesas,sh7750-cpg
+ - renesas,sh7750s-cpg
+then:
+ properties:
+reg:
+ maxItems: 1
+reg-names:
+ items:
+- const: FRQCR
+
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - renesas,sh7750r-cpg
+ - renesas,sh7751-cpg
+ - renesas,sh7751r-cpg
+then:
+ properties:
+reg:
+ maxItems: 2
+reg-names:
+ items:
+- const: FRQCR
+- const: CLKSTP00
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+cpg: clock-controller@ffc0 {
+#clock-cells = <1>;
+#power-domain-cells = <0>;
+compatible = "renesas,sh7751r-cpg";
+clocks = <&extal>;
+clock-names = "extal";
+reg = <0xffc0 20>, <0xfe0a 16>;
+reg-names = "FRQCR", "CLKSTP00";
+renesas,mode = <0>;
+};
diff --git a/include/dt-bindings/clock/sh7750-cpg.h
b/include/dt-bindings/clock/sh7750-cpg.h
new file mode 100644
index ..ec267be91adf
--- /dev/null
+++ b/include/dt-bindings/clock/sh7750-cpg.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SH7750_H__
+#define __DT_BINDINGS_CLOCK_SH7750_H__
+
+#define SH7750_CPG_PLLOUT 0
+
+#define SH7750_CPG_PCK 1
+#define SH7750_CPG_BCK 2
+#define SH7750_CPG_ICK 3
+
+#define SH7750_MSTP_SCI4
+#define SH7750_MSTP_RTC5
+#define SH7750_MSTP_TMU012 6
+#define SH7750_MSTP_SCIF 7
+#define SH7750_MSTP_DMAC 8
+#define SH7750_MSTP_UBC9
+#define SH7750_MSTP_SQ 10
+#define SH7750_CSTP_INTC 11
+#define SH7750_CSTP_TMU34 12
+#define SH7750_CSTP_PCIC 13
+
+#endif
--
2.39.2
[RESEND v7 10/37] sh: Common PCI Framework driver support.
Add New OF based PCI Host driver.
This driver conflicts some point in legacy PCI driver.
To resolve the conflict, I made some changes to the legacy driver.
Signed-off-by: Yoshinori Sato
---
arch/sh/include/asm/io.h | 6 ++
arch/sh/include/asm/pci.h | 4
arch/sh/kernel/iomap.c| 18 ++
3 files changed, 28 insertions(+)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 5c544cf5201b..29b5f996cde3 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#define __IO_PREFIX generic
#include
@@ -310,4 +311,9 @@ unsigned long long poke_real_address_q(unsigned long long
addr,
int valid_phys_addr_range(phys_addr_t addr, size_t size);
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+#if defined(CONFIG_PCI) && !defined(CONFIG_GENERIC_IOMAP)
+#define pci_remap_iospace pci_remap_iospace
+int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
+#endif
+
#endif /* __ASM_SH_IO_H */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index 54c30126ea17..92b3bd604319 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -2,6 +2,7 @@
#ifndef __ASM_SH_PCI_H
#define __ASM_SH_PCI_H
+#ifndef CONFIG_SH_DEVICE_TREE
/* Can be used to override the logic in pci_scan_bus for skipping
already-configured bus numbers - to be used for buggy BIOSes
or architectures with incomplete PCI setup by the loader */
@@ -88,4 +89,7 @@ static inline int pci_proc_domain(struct pci_bus *bus)
return hose->need_domain_info;
}
+#else /* CONFIG_SH_DEVICE_TREE */
+#include
+#endif
#endif /* __ASM_SH_PCI_H */
diff --git a/arch/sh/kernel/iomap.c b/arch/sh/kernel/iomap.c
index 0a0dff4e66de..d1b8e496ca23 100644
--- a/arch/sh/kernel/iomap.c
+++ b/arch/sh/kernel/iomap.c
@@ -160,3 +160,21 @@ void iowrite32_rep(void __iomem *addr, const void *src,
unsigned long count)
mmio_outsl(addr, src, count);
}
EXPORT_SYMBOL(iowrite32_rep);
+
+#if defined(pci_remap_iospace)
+int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
+{
+ unsigned long vaddr = res->start;
+
+ if (!(res->flags & IORESOURCE_IO))
+ return -EINVAL;
+
+ if (res->end > IO_SPACE_LIMIT)
+ return -EINVAL;
+
+ __set_io_port_base(phys_addr);
+ return vmap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
+ pgprot_device(PAGE_KERNEL));
+}
+EXPORT_SYMBOL(pci_remap_iospace);
+#endif
--
2.39.2
[RESEND v7 06/37] sh: kernel/setup Update DT support.
Fix extrnal fdt initialize and bootargs.
Signed-off-by: Yoshinori Sato
---
arch/sh/Kconfig | 23 +++
arch/sh/include/asm/setup.h | 1 +
arch/sh/kernel/setup.c | 36 +++-
3 files changed, 35 insertions(+), 25 deletions(-)
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 6711cde0d973..242cf30e704d 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -708,17 +708,22 @@ config ROMIMAGE_MMCIF
first part of the romImage which in turn loads the rest the kernel
image to RAM using the MMCIF hardware block.
+config CMDLINE
+ string "Kernel command line arguments string"
+ default "console=ttySC1,115200"
+
choice
prompt "Kernel command line"
- optional
- default CMDLINE_OVERWRITE
- depends on !OF || USE_BUILTIN_DTB
+ default CMDLINE_BOOTLOADER
+
+config CMDLINE_BOOTLOADER
+ bool "Use bootloader kernel arguments"
help
- Setting this option allows the kernel command line arguments
- to be set.
+ Uses the command-line options passed by the boot loader.
+ If boot loader dosen't provide kernel argments, Use built-in argments.
config CMDLINE_OVERWRITE
- bool "Overwrite bootloader kernel arguments"
+ bool "Overwrite built-in kernel arguments"
help
Given string will overwrite any arguments passed in by
a bootloader.
@@ -730,12 +735,6 @@ config CMDLINE_EXTEND
by a bootloader.
endchoice
-
-config CMDLINE
- string "Kernel command line arguments string"
- depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND
- default "console=ttySC1,115200"
-
endmenu
menu "Bus options"
diff --git a/arch/sh/include/asm/setup.h b/arch/sh/include/asm/setup.h
index fc807011187f..84bb23a771f3 100644
--- a/arch/sh/include/asm/setup.h
+++ b/arch/sh/include/asm/setup.h
@@ -21,5 +21,6 @@
void sh_mv_setup(void);
void check_for_initrd(void);
void per_cpu_trap_init(void);
+void sh_fdt_init(phys_addr_t dt_phys);
#endif /* _SH_SETUP_H */
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 620e5cf8ae1e..42e6292a40cf 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -269,8 +270,22 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
void __init setup_arch(char **cmdline_p)
{
+#if defined(CONFIG_OF) && defined(CONFIG_OF_EARLY_FLATTREE)
+ if (IS_ENABLED(CONFIG_USE_BUILTIN_DTB)) {
+ /* Relocate Embedded DTB */
+ unflatten_and_copy_device_tree();
+ } else if (initial_boot_params) {
+ /* Reserve external DTB area */
+ memblock_reserve(__pa(initial_boot_params),
+fdt_totalsize(initial_boot_params));
+ unflatten_device_tree();
+ }
+ /* copy from /chosen/bootargs */
+ strscpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
+#endif
enable_mmu();
+#ifndef CONFIG_OF
ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
printk(KERN_NOTICE "Boot params:\n"
@@ -299,14 +314,17 @@ void __init setup_arch(char **cmdline_p)
bss_resource.start = virt_to_phys(__bss_start);
bss_resource.end = virt_to_phys(__bss_stop)-1;
-#ifdef CONFIG_CMDLINE_OVERWRITE
- strscpy(command_line, CONFIG_CMDLINE, sizeof(command_line));
-#else
- strscpy(command_line, COMMAND_LINE, sizeof(command_line));
+#endif
+#if !defined(CONFIG_OF) || defined(CONFIG_USE_BUILTIN_DTB)
+ if (*COMMAND_LINE)
+ strscpy(command_line, COMMAND_LINE, sizeof(command_line));
+#endif
+ if (*command_line == '\0' || IS_ENABLED(CONFIG_CMDLINE_OVERWRITE))
+ /* Use built-in parameter */
+ strscpy(command_line, CONFIG_CMDLINE, sizeof(command_line));
#ifdef CONFIG_CMDLINE_EXTEND
strlcat(command_line, " ", sizeof(command_line));
strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line));
-#endif
#endif
/* Save unparsed command line copy for /proc/cmdline */
@@ -322,14 +340,6 @@ void __init setup_arch(char **cmdline_p)
/* Let earlyprintk output early console messages */
sh_early_platform_driver_probe("earlyprintk", 1, 1);
-#ifdef CONFIG_OF_EARLY_FLATTREE
-#ifdef CONFIG_USE_BUILTIN_DTB
- unflatten_and_copy_device_tree();
-#else
- unflatten_device_tree();
-#endif
-#endif
-
paging_init();
/* Perform the machine specific initialisation */
--
2.39.2
[RESEND v7 07/37] sh: Fix COMMON_CLK support in CONFIG_OF=y.
Initialize the clock and timer using the COMMON_CLK procedure.
sh's earlytimer mechanism doesn't work properly in OF,
so timer initialization is delayed.
If CONFIG_OF=y, perform the general timer initialization procedure.
Signed-off-by: Yoshinori Sato
---
arch/sh/boards/of-generic.c | 28
arch/sh/kernel/time.c | 12
2 files changed, 16 insertions(+), 24 deletions(-)
diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
index f7f3e618e85b..f1ca5a914c11 100644
--- a/arch/sh/boards/of-generic.c
+++ b/arch/sh/boards/of-generic.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -98,16 +99,7 @@ static void sh_of_smp_probe(void)
#endif
-static void noop(void)
-{
-}
-
-static int noopi(void)
-{
- return 0;
-}
-
-static void __init sh_of_mem_reserve(void)
+static void __init sh_of_mem_init(void)
{
early_init_fdt_reserve_self();
early_init_fdt_scan_reserved_mem();
@@ -140,25 +132,13 @@ static void __init sh_of_init_irq(void)
irqchip_init();
}
-static int __init sh_of_clk_init(void)
-{
-#ifdef CONFIG_COMMON_CLK
- /* Disabled pending move to COMMON_CLK framework. */
- pr_info("SH generic board support: scanning for clk providers\n");
- of_clk_init(NULL);
-#endif
- return 0;
-}
-
static struct sh_machine_vector __initmv sh_of_generic_mv = {
.mv_setup = sh_of_setup,
.mv_name= "devicetree", /* replaced by DT root's model */
.mv_irq_demux = sh_of_irq_demux,
.mv_init_irq= sh_of_init_irq,
- .mv_clk_init= sh_of_clk_init,
- .mv_mode_pins = noopi,
- .mv_mem_init= noop,
- .mv_mem_reserve = sh_of_mem_reserve,
+ .mv_mode_pins = generic_mode_pins,
+ .mv_mem_init= sh_of_mem_init,
};
struct sh_clk_ops;
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
index 821a09cbd605..ce5b7c2f8628 100644
--- a/arch/sh/kernel/time.c
+++ b/arch/sh/kernel/time.c
@@ -19,7 +19,9 @@
#include
#include
#include
+#include
+#ifndef CONFIG_SH_DEVICE_TREE
static void __init sh_late_time_init(void)
{
/*
@@ -43,3 +45,13 @@ void __init time_init(void)
late_time_init = sh_late_time_init;
}
+#else
+/* CONFIG_SH_DEVICE_TREE */
+void __init time_init(void)
+{
+ pr_info("SH generic board support: scanning for clk providers\n");
+
+ of_clk_init(NULL);
+ timer_probe();
+}
+#endif
--
2.39.2
[RESEND v7 02/37] sh: Kconfig unified OF supported targets.
Targets that support OF should be treated as one board. Signed-off-by: Yoshinori Sato --- arch/sh/Kconfig| 1 + arch/sh/boards/Kconfig | 23 +-- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 2ad3e29f0ebe..cbf48e69ad74 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -711,6 +711,7 @@ choice prompt "Kernel command line" optional default CMDLINE_OVERWRITE + depends on !OF || USE_BUILTIN_DTB help Setting this option allows the kernel command line arguments to be set. diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 109bec4dad94..46387fd040ad 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -19,16 +19,9 @@ config SH_DEVICE_TREE select TIMER_OF select COMMON_CLK select GENERIC_CALIBRATE_DELAY - -config SH_JCORE_SOC - bool "J-Core SoC" - select SH_DEVICE_TREE - select CLKSRC_JCORE_PIT - select JCORE_AIC - depends on CPU_J2 - help - Select this option to include drivers core components of the - J-Core SoC, including interrupt controllers and timers. + select GENERIC_IRQ_CHIP + select SYS_SUPPORTS_PCI + select GENERIC_PCI_IOMAP if PCI config SH_SOLUTION_ENGINE bool "SolutionEngine" @@ -293,6 +286,7 @@ config SH_LANDISK bool "LANDISK" depends on CPU_SUBTYPE_SH7751R select HAVE_PCI + select SYS_SUPPORTS_PCI help I-O DATA DEVICE, INC. "LANDISK Series" support. @@ -369,6 +363,15 @@ config SH_APSH4AD0A help Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. +config SH_OF_BOARD + bool "General Open Firmware boards" + select SH_DEVICE_TREE + select CLKSRC_JCORE_PIT if CPU_J2 + select JCORE_AIC if CPU_J2 + select HAVE_PCI if CPU_SUBTYPE_SH7751R + help + This board means general OF supported targets. + source "arch/sh/boards/mach-r2d/Kconfig" source "arch/sh/boards/mach-highlander/Kconfig" source "arch/sh/boards/mach-sdk7780/Kconfig" -- 2.39.2
[RESEND v7 04/37] dt-bindings: interrupt-controller: Add header for Renesas SH3/4 INTC.
Renesas SH7751 Interrupt controller priority register define. Signed-off-by: Yoshinori Sato --- .../renesas,sh7751-intc.h | 19 +++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h diff --git a/include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h b/include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h new file mode 100644 index ..0543bd1b895e --- /dev/null +++ b/include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * SH3/4 INTC IPR register offsets (Address / bits) + */ + +#ifndef __DT_BINDINGS_RENESAS_SH7751_INTC +#define __DT_BINDINGS_RENESAS_SH7751_INTC + +#define IPRA 0 +#define IPRB 4 +#define IPRC 8 +#define IPRD 12 +#define INTPRI00 256 +#define IPR_B1212 +#define IPR_B8 8 +#define IPR_B4 4 +#define IPR_B0 0 + +#endif -- 2.39.2
[RESEND v7 03/37] sh: Enable OF support for build and configuration.
IRQ, CLK and PCI will be migrated to a common driver framework. So if OF, disable the SH specific drivers. Signed-off-by: Yoshinori Sato --- arch/sh/Kconfig | 11 ++- arch/sh/drivers/Makefile| 2 ++ arch/sh/kernel/cpu/Makefile | 9 +++-- arch/sh/kernel/cpu/sh4/Makefile | 3 +++ 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index cbf48e69ad74..6711cde0d973 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -66,10 +66,10 @@ config SUPERH select MODULES_USE_ELF_RELA select NEED_SG_DMA_LENGTH select NO_DMA if !MMU && !DMA_COHERENT - select NO_GENERIC_PCI_IOPORT_MAP if PCI + select NO_GENERIC_PCI_IOPORT_MAP if !SH_DEVICE_TREE select OLD_SIGACTION select OLD_SIGSUSPEND - select PCI_DOMAINS if PCI + select PCI_DOMAINS if PCI && !SH_DEVICE_TREE select PERF_EVENTS select PERF_USE_VMALLOC select RTC_LIB @@ -153,7 +153,7 @@ menu "System type" # config CPU_SH2 bool - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE config CPU_SH2A bool @@ -179,7 +179,7 @@ config CPU_SH4 select CPU_HAS_INTEVT select CPU_HAS_SR_RB select CPU_HAS_FPU if !CPU_SH4AL_DSP - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE select SYS_SUPPORTS_SH_TMU config CPU_SH4A @@ -522,6 +522,7 @@ config SH_PCLK_FREQ config SH_CLK_CPG def_bool y + depends on !COMMON_CLK config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG @@ -666,7 +667,7 @@ config BUILTIN_DTB_SOURCE kernel. config ZERO_PAGE_OFFSET - hex + hex "Zero page offset" default "0x0001" if PAGE_SIZE_64KB || SH_RTS7751R2D || \ SH_7751_SOLUTION_ENGINE default "0x4000" if PAGE_SIZE_16KB || SH_SH03 diff --git a/arch/sh/drivers/Makefile b/arch/sh/drivers/Makefile index 8bd10b904bf9..83f609ca1eb4 100644 --- a/arch/sh/drivers/Makefile +++ b/arch/sh/drivers/Makefile @@ -5,6 +5,8 @@ obj-y += dma/ platform_early.o +ifndef CONFIG_SH_DEVICE_TREE obj-$(CONFIG_PCI) += pci/ +endif obj-$(CONFIG_PUSH_SWITCH) += push-switch.o obj-$(CONFIG_HEARTBEAT)+= heartbeat.o diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile index 46118236bf04..e00ebf134985 100644 --- a/arch/sh/kernel/cpu/Makefile +++ b/arch/sh/kernel/cpu/Makefile @@ -16,6 +16,11 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/ # Common interfaces. obj-$(CONFIG_SH_ADC) += adc.o +ifndef CONFIG_COMMON_CLK +obj-y += clock.o obj-$(CONFIG_SH_CLK_CPG_LEGACY)+= clock-cpg.o - -obj-y += irq/ init.o clock.o fpu.o pfc.o proc.o +endif +ifndef CONFIG_GENERIC_IRQ_CHIP +obj-y += irq/ +endif +obj-y += init.o fpu.o pfc.o proc.o diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile index 02e3ee16e15c..33da4c86feff 100644 --- a/arch/sh/kernel/cpu/sh4/Makefile +++ b/arch/sh/kernel/cpu/sh4/Makefile @@ -15,6 +15,7 @@ perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o +ifndef CONFIG_SH_DEVICE_TREE # CPU subtype setup obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o @@ -29,5 +30,7 @@ ifndef CONFIG_CPU_SH4A clock-$(CONFIG_CPU_SH4):= clock-sh4.o endif +endif # CONFIG_SH_DEVICE_TREE + obj-y += $(clock-y) obj-$(CONFIG_PERF_EVENTS) += $(perf-y) -- 2.39.2
[RESEND v7 01/37] sh: passing FDT address to kernel startup.
R4 is caller saved in SH ABI. Save it so it doesn't get corrupted until it's needed for initialization. Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven --- arch/sh/boot/compressed/head_32.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S index 7bb168133dbb..6be59851122e 100644 --- a/arch/sh/boot/compressed/head_32.S +++ b/arch/sh/boot/compressed/head_32.S @@ -15,7 +15,8 @@ startup: /* Load initial status register */ mov.l init_sr, r1 ldc r1, sr - + /* Save FDT address */ + mov r4, r13 /* Move myself to proper location if necessary */ mova1f, r0 mov.l 1f, r2 @@ -84,7 +85,7 @@ l1: /* Jump to the start of the decompressed kernel */ mov.l kernel_start_addr, r0 jmp @r0 - nop +movr13, r4 .align 2 bss_start_addr: -- 2.39.2
[PATCH v7 02/37] sh: Kconfig unified OF supported targets.
Targets that support OF should be treated as one board. Signed-off-by: Yoshinori Sato --- arch/sh/Kconfig| 1 + arch/sh/boards/Kconfig | 23 +-- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 2ad3e29f0ebe..cbf48e69ad74 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -711,6 +711,7 @@ choice prompt "Kernel command line" optional default CMDLINE_OVERWRITE + depends on !OF || USE_BUILTIN_DTB help Setting this option allows the kernel command line arguments to be set. diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 109bec4dad94..46387fd040ad 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -19,16 +19,9 @@ config SH_DEVICE_TREE select TIMER_OF select COMMON_CLK select GENERIC_CALIBRATE_DELAY - -config SH_JCORE_SOC - bool "J-Core SoC" - select SH_DEVICE_TREE - select CLKSRC_JCORE_PIT - select JCORE_AIC - depends on CPU_J2 - help - Select this option to include drivers core components of the - J-Core SoC, including interrupt controllers and timers. + select GENERIC_IRQ_CHIP + select SYS_SUPPORTS_PCI + select GENERIC_PCI_IOMAP if PCI config SH_SOLUTION_ENGINE bool "SolutionEngine" @@ -293,6 +286,7 @@ config SH_LANDISK bool "LANDISK" depends on CPU_SUBTYPE_SH7751R select HAVE_PCI + select SYS_SUPPORTS_PCI help I-O DATA DEVICE, INC. "LANDISK Series" support. @@ -369,6 +363,15 @@ config SH_APSH4AD0A help Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. +config SH_OF_BOARD + bool "General Open Firmware boards" + select SH_DEVICE_TREE + select CLKSRC_JCORE_PIT if CPU_J2 + select JCORE_AIC if CPU_J2 + select HAVE_PCI if CPU_SUBTYPE_SH7751R + help + This board means general OF supported targets. + source "arch/sh/boards/mach-r2d/Kconfig" source "arch/sh/boards/mach-highlander/Kconfig" source "arch/sh/boards/mach-sdk7780/Kconfig" -- 2.39.2
[PATCH v7 13/37] dt-bindings: clock: sh7750-cpg: Add renesas, sh7750-cpg header.
SH7750 CPG Clock output define.
Signed-off-by: Yoshinori Sato
---
.../bindings/clock/renesas,sh7750-cpg.yaml| 105 ++
include/dt-bindings/clock/sh7750-cpg.h| 26 +
2 files changed, 131 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
create mode 100644 include/dt-bindings/clock/sh7750-cpg.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
new file mode 100644
index ..04c10b0834ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7750/7751 Clock Pulse Generator (CPG)
+
+maintainers:
+ - Yoshinori Sato
+
+description:
+ The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
+ includes PLLs, and variable ratio dividers.
+
+ The CPG may also provide a Clock Domain for SoC devices, in combination with
+ the CPG Module Stop (MSTP) Clocks.
+
+properties:
+ compatible:
+enum:
+ - renesas,sh7750-cpg # SH7750
+ - renesas,sh7750s-cpg# SH775S
+ - renesas,sh7750r-cpg# SH7750R
+ - renesas,sh7751-cpg # SH7751
+ - renesas,sh7751r-cpg# SH7751R
+
+ reg: true
+
+ reg-names: true
+
+ clocks:
+maxItems: 1
+
+ clock-names:
+const: extal
+
+ '#clock-cells':
+const: 1
+
+ renesas,mode:
+description: Board-specific settings of the MD[0-2] pins on SoC
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 0
+maximum: 6
+
+ '#power-domain-cells':
+const: 0
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - renesas,sh7750-cpg
+ - renesas,sh7750s-cpg
+then:
+ properties:
+reg:
+ maxItems: 1
+reg-names:
+ items:
+- const: FRQCR
+
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - renesas,sh7750r-cpg
+ - renesas,sh7751-cpg
+ - renesas,sh7751r-cpg
+then:
+ properties:
+reg:
+ maxItems: 2
+reg-names:
+ items:
+- const: FRQCR
+- const: CLKSTP00
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+cpg: clock-controller@ffc0 {
+#clock-cells = <1>;
+#power-domain-cells = <0>;
+compatible = "renesas,sh7751r-cpg";
+clocks = <&extal>;
+clock-names = "extal";
+reg = <0xffc0 20>, <0xfe0a 16>;
+reg-names = "FRQCR", "CLKSTP00";
+renesas,mode = <0>;
+};
diff --git a/include/dt-bindings/clock/sh7750-cpg.h
b/include/dt-bindings/clock/sh7750-cpg.h
new file mode 100644
index ..ec267be91adf
--- /dev/null
+++ b/include/dt-bindings/clock/sh7750-cpg.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SH7750_H__
+#define __DT_BINDINGS_CLOCK_SH7750_H__
+
+#define SH7750_CPG_PLLOUT 0
+
+#define SH7750_CPG_PCK 1
+#define SH7750_CPG_BCK 2
+#define SH7750_CPG_ICK 3
+
+#define SH7750_MSTP_SCI4
+#define SH7750_MSTP_RTC5
+#define SH7750_MSTP_TMU012 6
+#define SH7750_MSTP_SCIF 7
+#define SH7750_MSTP_DMAC 8
+#define SH7750_MSTP_UBC9
+#define SH7750_MSTP_SQ 10
+#define SH7750_CSTP_INTC 11
+#define SH7750_CSTP_TMU34 12
+#define SH7750_CSTP_PCIC 13
+
+#endif
--
2.39.2
[PATCH v7 03/37] sh: Enable OF support for build and configuration.
IRQ, CLK and PCI will be migrated to a common driver framework. So if OF, disable the SH specific drivers. Signed-off-by: Yoshinori Sato --- arch/sh/Kconfig | 11 ++- arch/sh/drivers/Makefile| 2 ++ arch/sh/kernel/cpu/Makefile | 9 +++-- arch/sh/kernel/cpu/sh4/Makefile | 3 +++ 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index cbf48e69ad74..6711cde0d973 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -66,10 +66,10 @@ config SUPERH select MODULES_USE_ELF_RELA select NEED_SG_DMA_LENGTH select NO_DMA if !MMU && !DMA_COHERENT - select NO_GENERIC_PCI_IOPORT_MAP if PCI + select NO_GENERIC_PCI_IOPORT_MAP if !SH_DEVICE_TREE select OLD_SIGACTION select OLD_SIGSUSPEND - select PCI_DOMAINS if PCI + select PCI_DOMAINS if PCI && !SH_DEVICE_TREE select PERF_EVENTS select PERF_USE_VMALLOC select RTC_LIB @@ -153,7 +153,7 @@ menu "System type" # config CPU_SH2 bool - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE config CPU_SH2A bool @@ -179,7 +179,7 @@ config CPU_SH4 select CPU_HAS_INTEVT select CPU_HAS_SR_RB select CPU_HAS_FPU if !CPU_SH4AL_DSP - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE select SYS_SUPPORTS_SH_TMU config CPU_SH4A @@ -522,6 +522,7 @@ config SH_PCLK_FREQ config SH_CLK_CPG def_bool y + depends on !COMMON_CLK config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG @@ -666,7 +667,7 @@ config BUILTIN_DTB_SOURCE kernel. config ZERO_PAGE_OFFSET - hex + hex "Zero page offset" default "0x0001" if PAGE_SIZE_64KB || SH_RTS7751R2D || \ SH_7751_SOLUTION_ENGINE default "0x4000" if PAGE_SIZE_16KB || SH_SH03 diff --git a/arch/sh/drivers/Makefile b/arch/sh/drivers/Makefile index 8bd10b904bf9..83f609ca1eb4 100644 --- a/arch/sh/drivers/Makefile +++ b/arch/sh/drivers/Makefile @@ -5,6 +5,8 @@ obj-y += dma/ platform_early.o +ifndef CONFIG_SH_DEVICE_TREE obj-$(CONFIG_PCI) += pci/ +endif obj-$(CONFIG_PUSH_SWITCH) += push-switch.o obj-$(CONFIG_HEARTBEAT)+= heartbeat.o diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile index 46118236bf04..e00ebf134985 100644 --- a/arch/sh/kernel/cpu/Makefile +++ b/arch/sh/kernel/cpu/Makefile @@ -16,6 +16,11 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/ # Common interfaces. obj-$(CONFIG_SH_ADC) += adc.o +ifndef CONFIG_COMMON_CLK +obj-y += clock.o obj-$(CONFIG_SH_CLK_CPG_LEGACY)+= clock-cpg.o - -obj-y += irq/ init.o clock.o fpu.o pfc.o proc.o +endif +ifndef CONFIG_GENERIC_IRQ_CHIP +obj-y += irq/ +endif +obj-y += init.o fpu.o pfc.o proc.o diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile index 02e3ee16e15c..33da4c86feff 100644 --- a/arch/sh/kernel/cpu/sh4/Makefile +++ b/arch/sh/kernel/cpu/sh4/Makefile @@ -15,6 +15,7 @@ perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o +ifndef CONFIG_SH_DEVICE_TREE # CPU subtype setup obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o @@ -29,5 +30,7 @@ ifndef CONFIG_CPU_SH4A clock-$(CONFIG_CPU_SH4):= clock-sh4.o endif +endif # CONFIG_SH_DEVICE_TREE + obj-y += $(clock-y) obj-$(CONFIG_PERF_EVENTS) += $(perf-y) -- 2.39.2
[PATCH v7 05/37] sh: GENERIC_IRQ_CHIP support for CONFIG_OF=y
Remove unused function prototype.
Add helper update_sr_imask. use for SH7751 irq driver.
Add stub intc_finalize.
Signed-off-by: Yoshinori Sato
---
arch/sh/include/asm/io.h | 2 ++
arch/sh/include/asm/irq.h | 10 --
arch/sh/kernel/cpu/Makefile| 5 +
arch/sh/kernel/cpu/irq/imask.c | 17 +
include/linux/sh_intc.h| 7 ++-
5 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index cf5eab840d57..5c544cf5201b 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -121,7 +121,9 @@ __BUILD_MEMORY_STRING(__raw_, q, u64)
#define ioport_map ioport_map
#define ioport_unmap ioport_unmap
+#ifndef CONFIG_SH_DEVICE_TREE
#define pci_iounmap pci_iounmap
+#endif
#define ioread8 ioread8
#define ioread16 ioread16
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
index 0f384b1f45ca..3d897229dcc4 100644
--- a/arch/sh/include/asm/irq.h
+++ b/arch/sh/include/asm/irq.h
@@ -16,8 +16,8 @@
/*
* Simple Mask Register Support
*/
-extern void make_maskreg_irq(unsigned int irq);
-extern unsigned short *irq_mask_register;
+
+void update_sr_imask(unsigned int irq, bool enable);
/*
* PINT IRQs
@@ -54,4 +54,10 @@ extern void irq_finish(unsigned int irq);
#include
+/* SH3/4 INTC stuff */
+/* IRL level 0 - 15 */
+#define NR_IRL 15
+/* IRL0 -> IRQ16 */
+#define IRL_BASE_IRQ 16
+
#endif /* __ASM_SH_IRQ_H */
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index e00ebf134985..ad12807fae9c 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -20,7 +20,4 @@ ifndef CONFIG_COMMON_CLK
obj-y += clock.o
obj-$(CONFIG_SH_CLK_CPG_LEGACY)+= clock-cpg.o
endif
-ifndef CONFIG_GENERIC_IRQ_CHIP
-obj-y += irq/
-endif
-obj-y += init.o fpu.o pfc.o proc.o
+obj-y += init.o fpu.o pfc.o proc.o irq/
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
index 572585c3f2fd..7589ca7c506c 100644
--- a/arch/sh/kernel/cpu/irq/imask.c
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -51,6 +51,7 @@ static inline void set_interrupt_registers(int ip)
: "t");
}
+#ifndef CONFIG_GENERIC_IRQ_CHIP
static void mask_imask_irq(struct irq_data *data)
{
unsigned int irq = data->irq;
@@ -83,3 +84,19 @@ void make_imask_irq(unsigned int irq)
irq_set_chip_and_handler_name(irq, &imask_irq_chip, handle_level_irq,
"level");
}
+#else
+void update_sr_imask(unsigned int irq, bool enable)
+{
+ if (enable) {
+ set_bit(irq, imask_mask);
+ interrupt_priority = IMASK_PRIORITY -
+ find_first_bit(imask_mask, IMASK_PRIORITY);
+ } else {
+ clear_bit(irq, imask_mask);
+ if (interrupt_priority < IMASK_PRIORITY - irq)
+ interrupt_priority = IMASK_PRIORITY - irq;
+ }
+ set_interrupt_registers(interrupt_priority);
+}
+EXPORT_SYMBOL(update_sr_imask);
+#endif
diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h
index 27ae79191bdc..994b5b05a0d7 100644
--- a/include/linux/sh_intc.h
+++ b/include/linux/sh_intc.h
@@ -139,8 +139,13 @@ struct intc_desc symbol __initdata = {
\
int register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);
int intc_irq_lookup(const char *chipname, intc_enum enum_id);
+#ifndef CONFIG_SH_DEVICE_TREE
void intc_finalize(void);
-
+#else
+static inline void intc_finalize(void)
+{
+}
+#endif
#ifdef CONFIG_INTC_USERIMASK
int register_intc_userimask(unsigned long addr);
#else
--
2.39.2
[PATCH v7 01/37] sh: passing FDT address to kernel startup.
R4 is caller saved in SH ABI. Save it so it doesn't get corrupted until it's needed for initialization. Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven --- arch/sh/boot/compressed/head_32.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S index 7bb168133dbb..6be59851122e 100644 --- a/arch/sh/boot/compressed/head_32.S +++ b/arch/sh/boot/compressed/head_32.S @@ -15,7 +15,8 @@ startup: /* Load initial status register */ mov.l init_sr, r1 ldc r1, sr - + /* Save FDT address */ + mov r4, r13 /* Move myself to proper location if necessary */ mova1f, r0 mov.l 1f, r2 @@ -84,7 +85,7 @@ l1: /* Jump to the start of the decompressed kernel */ mov.l kernel_start_addr, r0 jmp @r0 - nop +movr13, r4 .align 2 bss_start_addr: -- 2.39.2
[PATCH v7 12/37] dt-bindings: pci: pci-sh7751: Add SH7751 PCI
Renesas SH7751 PCI Controller json-schema.
Signed-off-by: Yoshinori Sato
---
.../bindings/pci/renesas,sh7751-pci.yaml | 89 +++
1 file changed, 89 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
diff --git a/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
new file mode 100644
index ..115c2bb67339
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/renesas,sh7751-pci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 PCI Host controller
+
+maintainers:
+ - Yoshinori Sato
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+const: renesas,sh7751-pci
+
+ reg:
+minItems: 2
+maxItems: 2
+
+ reg-names:
+items:
+ - const: PCI Controller
+ - const: Bus State Controller
+
+ "#interrupt-cells":
+const: 1
+
+ "#address-cells":
+const: 3
+
+ "#size-cells":
+const: 2
+
+ ranges: true
+
+ dma-ranges: true
+
+ interrupt-controller: true
+
+ renesas,bus-arbit-round-robin:
+$ref: /schemas/types.yaml#/definitions/flag
+description: |
+ Set DMA bus arbitration to round robin.
+
+required:
+ - compatible
+ - reg
+ - "#interrupt-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - interrupt-map
+ - interrupt-map-mask
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+pci@fe20 {
+compatible = "renesas,sh7751-pci";
+#address-cells = <3>;
+#size-cells = <2>;
+#interrupt-cells = <1>;
+interrupt-controller;
+device_type = "pci";
+bus-range = <0 0>;
+ranges = <0x0200 0 0xfd00 0xfd00 0 0x0100>,
+ <0x0100 0 0x 0xfe24 0 0x0004>;
+dma-ranges = <0x0200 0 0xc00 0x0c00 0 0x0400>;
+reg = <0xfe20 0x0400>,
+ <0xff80 0x0100>;
+interrupt-map = <0x 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+<0x 0 0 2 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+<0x 0 0 3 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+<0x 0 0 4 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 1 &julianintc 6 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 2 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 3 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+<0x0800 0 0 4 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 1 &julianintc 7 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 2 &julianintc 8 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 3 &julianintc 5 IRQ_TYPE_LEVEL_LOW>,
+<0x1000 0 0 4 &julianintc 6 IRQ_TYPE_LEVEL_LOW>;
+interrupt-map-mask = <0x1800 0 0 7>;
+};
--
2.39.2
[PATCH v7 21/37] dt-bindings: serial: renesas,scif: Add scif-sh7751.
Add Renesas SH7751 SCIF. Signed-off-by: Yoshinori Sato Reviewed-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 4610a5bd580c..590f88e2ced9 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -18,6 +18,7 @@ properties: - items: - enum: - renesas,scif-r7s72100 # RZ/A1H + - renesas,scif-sh7751 # SH7751 - const: renesas,scif # generic SCIF compatible UART - items: -- 2.39.2
[PATCH v7 14/37] clk: Compatible with narrow registers
divider and gate only support 32-bit registers.
Older hardware uses narrower registers, so I want to be able to handle
8-bit and 16-bit wide registers.
Seven clk_divider flags are used, and if I add flags for 8bit access and
16bit access, 8bit will not be enough, so I expanded it to u16.
Signed-off-by: Yoshinori Sato
---
drivers/clk/clk-divider.c| 56 +---
drivers/clk/clk-gate.c | 62
include/linux/clk-provider.h | 22 ++---
3 files changed, 103 insertions(+), 37 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index a2c2b5203b0a..a1b5187cd63d 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -26,20 +26,38 @@
* parent - fixed parent. No clk_set_parent support
*/
-static inline u32 clk_div_readl(struct clk_divider *divider)
-{
- if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
- return ioread32be(divider->reg);
-
- return readl(divider->reg);
+static inline u32 clk_div_read(struct clk_divider *divider)
+{
+ if (divider->flags & CLK_DIVIDER_REG_8BIT)
+ return readb(divider->reg);
+ else if (divider->flags & CLK_DIVIDER_REG_16BIT) {
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
+ return ioread16be(divider->reg);
+ else
+ return readw(divider->reg);
+ } else {
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
+ return ioread32be(divider->reg);
+ else
+ return readl(divider->reg);
+ }
}
-static inline void clk_div_writel(struct clk_divider *divider, u32 val)
+static inline void clk_div_write(struct clk_divider *divider, u32 val)
{
- if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
- iowrite32be(val, divider->reg);
- else
- writel(val, divider->reg);
+ if (divider->flags & CLK_DIVIDER_REG_8BIT)
+ writeb(val, divider->reg);
+ else if (divider->flags & CLK_DIVIDER_REG_16BIT) {
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
+ iowrite16be(val, divider->reg);
+ else
+ writew(val, divider->reg);
+ } else {
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
+ iowrite32be(val, divider->reg);
+ else
+ writel(val, divider->reg);
+ }
}
static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
@@ -152,7 +170,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw
*hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int val;
- val = clk_div_readl(divider) >> divider->shift;
+ val = clk_div_read(divider) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_recalc_rate(hw, parent_rate, val, divider->table,
@@ -434,7 +452,7 @@ static long clk_divider_round_rate(struct clk_hw *hw,
unsigned long rate,
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
u32 val;
- val = clk_div_readl(divider) >> divider->shift;
+ val = clk_div_read(divider) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_ro_round_rate(hw, rate, prate, divider->table,
@@ -455,7 +473,7 @@ static int clk_divider_determine_rate(struct clk_hw *hw,
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
u32 val;
- val = clk_div_readl(divider) >> divider->shift;
+ val = clk_div_read(divider) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_ro_determine_rate(hw, req, divider->table,
@@ -505,11 +523,11 @@ static int clk_divider_set_rate(struct clk_hw *hw,
unsigned long rate,
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = clk_div_mask(divider->width) << (divider->shift + 16);
} else {
- val = clk_div_readl(divider);
+ val = clk_div_read(divider);
val &= ~(clk_div_mask(divider->width) << divider->shift);
}
val |= (u32)value << divider->shift;
- clk_div_writel(divider, val);
+ clk_div_write(divider, val);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
@@ -538,7 +556,7 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,
struct device_node *np, const char *name,
const char *parent_name, const struct clk_hw *parent_hw,
const struct clk_parent_da
[PATCH v7 09/37] dt-binding: Add compatible SH7750 SoC
Signed-off-by: Yoshinori Sato --- Documentation/devicetree/bindings/timer/renesas,tmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml index 84bbe15028a1..265d286ffb2f 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml @@ -39,6 +39,7 @@ properties: - renesas,tmu-r8a779a0 # R-Car V3U - renesas,tmu-r8a779f0 # R-Car S4-8 - renesas,tmu-r8a779g0 # R-Car V4H + - renesas,tmu-sh7750 # SH7750 - const: renesas,tmu reg: @@ -96,6 +97,7 @@ if: - renesas,tmu-r8a7740 - renesas,tmu-r8a7778 - renesas,tmu-r8a7779 +- renesas,tmu-sh7750 then: required: - resets -- 2.39.2
[PATCH v7 08/37] clocksource: sh_tmu: CLOCKSOURCE support.
Allows initialization as CLOCKSOURCE.
Signed-off-by: Yoshinori Sato
---
drivers/clocksource/sh_tmu.c | 198 ---
1 file changed, 134 insertions(+), 64 deletions(-)
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index be81c00f..59f9da7fd987 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -17,6 +17,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -51,6 +53,7 @@ struct sh_tmu_channel {
struct sh_tmu_device {
struct platform_device *pdev;
+ struct device_node *np;
void __iomem *mapbase;
struct clk *clk;
@@ -65,6 +68,7 @@ struct sh_tmu_device {
bool has_clockevent;
bool has_clocksource;
+ const char *name;
};
#define TSTR -1 /* shared register */
@@ -148,8 +152,8 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch)
/* enable clock */
ret = clk_enable(ch->tmu->clk);
if (ret) {
- dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
- ch->index);
+ pr_err("%s ch%u: cannot enable clock\n",
+ ch->tmu->name, ch->index);
return ret;
}
@@ -174,9 +178,10 @@ static int sh_tmu_enable(struct sh_tmu_channel *ch)
if (ch->enable_count++ > 0)
return 0;
- pm_runtime_get_sync(&ch->tmu->pdev->dev);
- dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
-
+ if (ch->tmu->pdev) {
+ pm_runtime_get_sync(&ch->tmu->pdev->dev);
+ dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
+ }
return __sh_tmu_enable(ch);
}
@@ -202,8 +207,10 @@ static void sh_tmu_disable(struct sh_tmu_channel *ch)
__sh_tmu_disable(ch);
- dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
- pm_runtime_put(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev) {
+ dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
+ pm_runtime_put(&ch->tmu->pdev->dev);
+ }
}
static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
@@ -245,7 +252,7 @@ static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
+static inline struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
{
return container_of(cs, struct sh_tmu_channel, cs);
}
@@ -292,7 +299,8 @@ static void sh_tmu_clocksource_suspend(struct clocksource
*cs)
if (--ch->enable_count == 0) {
__sh_tmu_disable(ch);
- dev_pm_genpd_suspend(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev)
+ dev_pm_genpd_suspend(&ch->tmu->pdev->dev);
}
}
@@ -304,7 +312,8 @@ static void sh_tmu_clocksource_resume(struct clocksource
*cs)
return;
if (ch->enable_count++ == 0) {
- dev_pm_genpd_resume(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev)
+ dev_pm_genpd_resume(&ch->tmu->pdev->dev);
__sh_tmu_enable(ch);
}
}
@@ -324,14 +333,14 @@ static int sh_tmu_register_clocksource(struct
sh_tmu_channel *ch,
cs->mask = CLOCKSOURCE_MASK(32);
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
- dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
-ch->index);
+ pr_info("%s ch%u: used as clock source\n",
+ ch->tmu->name, ch->index);
clocksource_register_hz(cs, ch->tmu->rate);
return 0;
}
-static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
+static inline struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device
*ced)
{
return container_of(ced, struct sh_tmu_channel, ced);
}
@@ -364,8 +373,8 @@ static int sh_tmu_clock_event_set_state(struct
clock_event_device *ced,
if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
sh_tmu_disable(ch);
- dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n",
-ch->index, periodic ? "periodic" : "oneshot");
+ pr_info("%s ch%u: used for %s clock events\n",
+ ch->tmu->name, ch->index, periodic ? "periodic" : "oneshot");
sh_tmu_clock_event_start(ch, periodic);
return 0;
}
@@ -417,20 +426,22 @@ static void sh_tmu_register_clockevent(struct
sh_tmu_channel *ch,
ced->set_state_shutdown = sh_tmu_clock_event_shutdown;
ced->set_state_period
[PATCH v7 23/37] dt-bindings: display: sm501 register definition helper
Miscellaneous Timing and Miscellaneous Control registers definition. Signed-off-by: Yoshinori Sato --- include/dt-bindings/display/sm501.h | 76 + 1 file changed, 76 insertions(+) create mode 100644 include/dt-bindings/display/sm501.h diff --git a/include/dt-bindings/display/sm501.h b/include/dt-bindings/display/sm501.h new file mode 100644 index ..a6c6943642e4 --- /dev/null +++ b/include/dt-bindings/display/sm501.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef __DT_BINDING_DISPALY_SM501__ +#define __DT_BINDING_DISPALY_SM501__ + +/* Miscellaneous Conntrol */ +#define SM501_MISC_CONTROL_PAD_24 0 +#define SM501_MISC_CONTROL_PAD_12 1 +#define SM501_MISC_CONTROL_PAD_8 2 + +#define SM501_MISC_CONTROL_USBCLK_XTAL 0 +#define SM501_MISC_CONTROL_USBCLK_96MHZ1 +#define SM501_MISC_CONTROL_USBCLK_48MHZ2 + +#define SM501_MISC_CONTROL_RFSH_8US0 +#define SM501_MISC_CONTROL_RFSH_16US 1 +#define SM501_MISC_CONTROL_RFSH_32US 2 +#define SM501_MISC_CONTROL_RFSH_64US 3 + +#define SM501_MISC_CONTROL_HOLD_EMPTY 0 +#define SM501_MISC_CONTROL_HOLD_8TR1 +#define SM501_MISC_CONTROL_HOLD_16TR 2 +#define SM501_MISC_CONTROL_HOLD_24TR 3 +#define SM501_MISC_CONTROL_HOLD_32TR 4 + +/* Miscellaneous timing */ +#define SM501_MISC_TIMING_EX_HOLD_00 +#define SM501_MISC_TIMING_EX_HOLD_16 1 +#define SM501_MISC_TIMING_EX_HOLD_32 2 +#define SM501_MISC_TIMING_EX_HOLD_48 3 +#define SM501_MISC_TIMING_EX_HOLD_64 4 +#define SM501_MISC_TIMING_EX_HOLD_80 5 +#define SM501_MISC_TIMING_EX_HOLD_96 6 +#define SM501_MISC_TIMING_EX_HOLD_112 7 +#define SM501_MISC_TIMING_EX_HOLD_128 8 +#define SM501_MISC_TIMING_EX_HOLD_144 9 +#define SM501_MISC_TIMING_EX_HOLD_160 10 +#define SM501_MISC_TIMING_EX_HOLD_176 11 +#define SM501_MISC_TIMING_EX_HOLD_192 12 +#define SM501_MISC_TIMING_EX_HOLD_208 13 +#define SM501_MISC_TIMING_EX_HOLD_224 14 +#define SM501_MISC_TIMING_EX_HOLD_240 15 + +#define SM501_MISC_TIMING_XC_INTERNAL 0 +#define SM501_MISC_TIMING_XC_HCLK 1 +#define SM501_MISC_TIMING_XC_GPIO 2 + +#define SM501_MISC_TIMING_SM_DIV1 0 +#define SM501_MISC_TIMING_SM_DIV2 1 +#define SM501_MISC_TIMING_SM_DIV4 2 +#define SM501_MISC_TIMING_SM_DIV8 3 +#define SM501_MISC_TIMING_SM_DIV16 4 +#define SM501_MISC_TIMING_SM_DIV32 5 +#define SM501_MISC_TIMING_SM_DIV64 6 +#define SM501_MISC_TIMING_SM_DIV1287 +#define SM501_MISC_TIMING_SM_DIV3 8 +#define SM501_MISC_TIMING_SM_DIV6 9 +#define SM501_MISC_TIMING_SM_DIV12 10 +#define SM501_MISC_TIMING_SM_DIV24 11 +#define SM501_MISC_TIMING_SM_DIV48 12 +#define SM501_MISC_TIMING_SM_DIV96 13 +#define SM501_MISC_TIMING_SM_DIV19214 +#define SM501_MISC_TIMING_SM_DIV38415 + +#define SM501_MISC_TIMING_DIV336MHZ0 +#define SM501_MISC_TIMING_DIV288MHZ1 +#define SM501_MISC_TIMING_DIV240MHZ2 +#define SM501_MISC_TIMING_DIV192MHZ3 + +#define SM501_MISC_TIMING_DELAY_NONE 0 +#define SM501_MISC_TIMING_DELAY_0_51 +#define SM501_MISC_TIMING_DELAY_1_02 +#define SM501_MISC_TIMING_DELAY_1_53 +#define SM501_MISC_TIMING_DELAY_2_04 +#define SM501_MISC_TIMING_DELAY_2_55 + +#endif -- 2.39.2
[PATCH v7 16/37] irqchip: Add SH7751 INTC driver
Renesas SH7751 Internal interrupt controller driver.
Signed-off-by: Yoshinori Sato
---
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-renesas-sh7751.c | 282 +++
3 files changed, 291 insertions(+)
create mode 100644 drivers/irqchip/irq-renesas-sh7751.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 72c07a12f5e1..33badb5b4f00 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -690,4 +690,12 @@ config SUNPLUS_SP7021_INTC
chained controller, routing all interrupt source in P-Chip to
the primary controller on C-Chip.
+config RENESAS_SH7751_INTC
+ bool "Renesas SH7751 Interrupt Controller"
+ depends on SH_DEVICE_TREE || COMPILE_TEST
+ select IRQ_DOMAIN_HIERARCHY
+ help
+ Support for the Renesas SH7751 On-chip interrupt controller.
+ And external interrupt encoder for some targets.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index ec4a18380998..51855034a895 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -121,3 +121,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o
obj-$(CONFIG_APPLE_AIC)+= irq-apple-aic.o
obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
+obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
diff --git a/drivers/irqchip/irq-renesas-sh7751.c
b/drivers/irqchip/irq-renesas-sh7751.c
new file mode 100644
index ..91d6dc3ed04c
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-sh7751.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7751 interrupt controller driver
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct ipr {
+ u16 off;
+ u16 idx;
+};
+
+struct sh7751_intc_priv {
+ const struct ipr *iprmap;
+ void __iomem *base;
+ void __iomem *intpri00;
+ bool irlm;
+};
+
+enum {
+ R_ICR = 0x00,
+ R_IPR = 0x04,
+ R_INTPRI00= 0x00,
+ R_INTREQ00= 0x20,
+ R_INTMSK00= 0x40,
+ R_INTMSKCLR00 = 0x60,
+};
+
+#define ICR_IRLM BIT(7)
+
+/*
+ * SH7751 IRQ mapping
+ * IRQ16 - 63: Group0 - IPRA to IPRD
+ * IRQ16 - 31: external IRL input (ICR.IRLM is 0)
+ * IRQ80 - 92: Group1 - INTPRI00
+ */
+#define IRQ_START 16
+#define MAX_IRL(IRQ_START + NR_IRL)
+#define GRP0_IRQ_END 63
+#define GRP1_IRQ_START 80
+#define IRQ_END92
+
+#define NR_IPRMAP0 (GRP0_IRQ_END - IRQ_START + 1)
+#define NR_IPRMAP1 (IRQ_END - GRP1_IRQ_START)
+#define IPR_PRI_MASK 0x000f
+
+#define IPRA 0
+#define IPRB 4
+#define IPRC 8
+#define IPRD 12
+#define INTPRI00 256
+#define IPR_B1212
+#define IPR_B8 8
+#define IPR_B4 4
+#define IPR_B0 0
+
+/* SH7751 EVT to IPR mapping table */
+static const struct ipr sh7751_iprmap[] = {
+ [evt2irq(0x240)] = {IPRD, IPR_B12}, /* IRL0 (ICR.IRLM=1) */
+ [evt2irq(0x2a0)] = {IPRD, IPR_B8}, /* IRL1 (ICR.IRLM=1) */
+ [evt2irq(0x300)] = {IPRD, IPR_B4}, /* IRL2 (ICR.IRLM=1) */
+ [evt2irq(0x360)] = {IPRD, IPR_B0}, /* IRL3 (ICR.IRLM=1) */
+ [evt2irq(0x400)] = {IPRA, IPR_B12}, /* TMU0 */
+ [evt2irq(0x420)] = {IPRA, IPR_B8}, /* TMU1 */
+ [evt2irq(0x440)] = {IPRA, IPR_B4}, /* TMU2 TNUI */
+ [evt2irq(0x460)] = {IPRA, IPR_B4}, /* TMU2 TICPI */
+ [evt2irq(0x480)] = {IPRA, IPR_B0}, /* RTC ATI */
+ [evt2irq(0x4a0)] = {IPRA, IPR_B0}, /* RTC PRI */
+ [evt2irq(0x4c0)] = {IPRA, IPR_B0}, /* RTC CUI */
+ [evt2irq(0x4e0)] = {IPRB, IPR_B4}, /* SCI ERI */
+ [evt2irq(0x500)] = {IPRB, IPR_B4}, /* SCI RXI */
+ [evt2irq(0x520)] = {IPRB, IPR_B4}, /* SCI TXI */
+ [evt2irq(0x540)] = {IPRB, IPR_B4}, /* SCI TEI */
+ [evt2irq(0x560)] = {IPRB, IPR_B12}, /* WDT */
+ [evt2irq(0x580)] = {IPRB, IPR_B8}, /* REF RCMI */
+ [evt2irq(0x5a0)] = {IPRB, IPR_B4}, /* REF ROVI */
+ [evt2irq(0x600)] = {IPRC, IPR_B0}, /* H-UDI */
+ [evt2irq(0x620)] = {IPRC, IPR_B12}, /* GPIO */
+ [evt2irq(0x640)] = {IPRC, IPR_B8}, /* DMAC DMTE0 */
+ [evt2irq(0x660)] = {IPRC, IPR_B8}, /* DMAC DMTE1 */
+ [evt2irq(0x680)] = {IPRC, IPR_B8}, /* DMAC DMTE2 */
+ [evt2irq(0x6a0)] = {IPRC, IPR_B8}, /* DMAC DMTE3 */
+ [evt2irq(0x6c0)] = {IPRC, IPR_B8}, /* DMAC DMAE */
+ [evt2irq(0x700)] = {IPRC, IPR_B4}, /* SCIF ERI */
+ [evt2irq(0x720)] = {IPRC, IPR_B4}, /* SCIF RXI */
+ [evt2irq(0x740)] = {IPRC, IPR_B4},
[PATCH v7 00/37] Device Tree support for SH7751 based board
This is an updated version of something I wrote about 7 years ago. Minimum support for R2D-plus and LANDISK. I think R2D-1 will work if you add AX88796 to dts. And board-specific functions and SCI's SPI functions are not supported. You can get it working with qemu found here. https://gitlab.com/yoshinori.sato/qemu/-/tree/landisk v7 changes. - sh/kernel/setup.c: fix kernel parameter handling. - clk-sh7750.c: cleanup. - sh_tmu.c: cleanup. - irq-renesas-sh7751.c: IPR definition move to code. - irq-renesas-sh7751irl.c: update register definition. - pci-sh7751.c: Register initialization fix. - sm501 and sm501fb: Re-design Device Tree properties. v6 changes. - pci-sh7751: merge register define. - pci-sh7751: use 'dma-ranges' property. - pci-sh7751: rename general PCI properties. - sm501 and sm501fb: Re-design Device Tree properties. - sh/kernel/setup: cleanup command line setup. - irq-sh7751.c: some cleanup. v5 changes. - pci-sh7751: revert header changes. and some fix in previuous driver. - sh/kernel/iomap.c: Use SH io functions. - sm501 and sm501fb: re-write DT support. v4 changes. - cpg-sh7750: use clk-divider and clk-gate. - pci-sh7751: unified header files to old PCI driver. - irq-renesas-sh7751: IPR registers direct mapping. - irq-renesas-sh7751irl: useful register bit mapping. - sm501 and sm501fb: re-write dt parser. - j2_minus: fix build error. - dt-binding schema: fix some errors. - *.dts: cleanup. v3 changes. - Rewrite clk drivers. - Added sh_tmu to OF support. - Cleanup PCI stuff. - Update sm501 and sm501fb OF support. - Update devicetree and documents. v2 changes. - Rebasing v6,6-rc1 - re-write irqchip driver. - Add binding documents. - Cleanup review comment. Yoshinori Sato (37): sh: passing FDT address to kernel startup. sh: Kconfig unified OF supported targets. sh: Enable OF support for build and configuration. dt-bindings: interrupt-controller: Add header for Renesas SH3/4 INTC. sh: GENERIC_IRQ_CHIP support for CONFIG_OF=y sh: kernel/setup Update DT support. sh: Fix COMMON_CLK support in CONFIG_OF=y. clocksource: sh_tmu: CLOCKSOURCE support. dt-binding: Add compatible SH7750 SoC sh: Common PCI Framework driver support. pci: pci-sh7751: Add SH7751 PCI driver dt-bindings: pci: pci-sh7751: Add SH7751 PCI dt-bindings: clock: sh7750-cpg: Add renesas,sh7750-cpg header. clk: Compatible with narrow registers clk: renesas: Add SH7750/7751 CPG Driver irqchip: Add SH7751 INTC driver dt-bindings: interrupt-controller: renesas,sh7751-intc: Add json-schema irqchip: SH7751 external interrupt encoder with enable gate. dt-bindings: interrupt-controller: renesas,sh7751-irl-ext: Add json-schema serial: sh-sci: fix SH4 OF support. dt-bindings: serial: renesas,scif: Add scif-sh7751. dt-bindings: display: smi,sm501: SMI SM501 binding json-schema dt-bindings: display: sm501 register definition helper mfd: sm501: Convert platform_data to OF property dt-binding: sh: cpus: Add SH CPUs json-schema dt-bindings: vendor-prefixes: Add iodata dt-bindings: ata: ata-generic: Add new targets dt-bindings: soc: renesas: sh: Add SH7751 based target sh: SH7751R SoC Internal peripheral definition dtsi. sh: add RTS7751R2D Plus DTS sh: Add IO DATA LANDISK dts sh: Add IO DATA USL-5P dts sh: j2_mimas_v2.dts update sh: Add dtbs target support. sh: RTS7751R2D Plus OF defconfig sh: LANDISK OF defconfig sh: j2_defconfig: update .../devicetree/bindings/ata/ata-generic.yaml | 2 + .../bindings/clock/renesas,sh7750-cpg.yaml| 105 .../bindings/display/smi,sm501.yaml | 398 +++ .../renesas,sh7751-intc.yaml | 53 ++ .../renesas,sh7751-irl-ext.yaml | 57 +++ .../bindings/pci/renesas,sh7751-pci.yaml | 89 .../bindings/serial/renesas,scif.yaml | 1 + .../devicetree/bindings/sh/cpus.yaml | 63 +++ .../devicetree/bindings/soc/renesas/sh.yaml | 27 + .../bindings/timer/renesas,tmu.yaml | 2 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/sh/Kconfig | 33 +- arch/sh/boards/Kconfig| 23 +- arch/sh/boards/of-generic.c | 28 +- arch/sh/boot/compressed/head_32.S | 5 +- arch/sh/boot/dts/Makefile | 5 + arch/sh/boot/dts/j2_mimas_v2.dts | 2 +- arch/sh/boot/dts/landisk.dts | 77 +++ arch/sh/boot/dts/rts7751r2dplus.dts | 169 ++ arch/sh/boot/dts/sh7751r.dtsi | 105 arch/sh/boot/dts/usl-5p.dts | 85 arch/sh/configs/j2_defconfig | 11 +- arch/sh/configs/landisk-of_defconfig | 104 arch/sh/configs/rts7751r2dplus-of_defconfig | 75 +++ arch/sh/drivers/Makefile | 2 + arch/sh/include/asm/io.h | 8 + arch/sh/include/asm/irq.h | 10 +-
[PATCH v7 07/37] sh: Fix COMMON_CLK support in CONFIG_OF=y.
Initialize the clock and timer using the COMMON_CLK procedure.
sh's earlytimer mechanism doesn't work properly in OF,
so timer initialization is delayed.
If CONFIG_OF=y, perform the general timer initialization procedure.
Signed-off-by: Yoshinori Sato
---
arch/sh/boards/of-generic.c | 28
arch/sh/kernel/time.c | 12
2 files changed, 16 insertions(+), 24 deletions(-)
diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
index f7f3e618e85b..f1ca5a914c11 100644
--- a/arch/sh/boards/of-generic.c
+++ b/arch/sh/boards/of-generic.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -98,16 +99,7 @@ static void sh_of_smp_probe(void)
#endif
-static void noop(void)
-{
-}
-
-static int noopi(void)
-{
- return 0;
-}
-
-static void __init sh_of_mem_reserve(void)
+static void __init sh_of_mem_init(void)
{
early_init_fdt_reserve_self();
early_init_fdt_scan_reserved_mem();
@@ -140,25 +132,13 @@ static void __init sh_of_init_irq(void)
irqchip_init();
}
-static int __init sh_of_clk_init(void)
-{
-#ifdef CONFIG_COMMON_CLK
- /* Disabled pending move to COMMON_CLK framework. */
- pr_info("SH generic board support: scanning for clk providers\n");
- of_clk_init(NULL);
-#endif
- return 0;
-}
-
static struct sh_machine_vector __initmv sh_of_generic_mv = {
.mv_setup = sh_of_setup,
.mv_name= "devicetree", /* replaced by DT root's model */
.mv_irq_demux = sh_of_irq_demux,
.mv_init_irq= sh_of_init_irq,
- .mv_clk_init= sh_of_clk_init,
- .mv_mode_pins = noopi,
- .mv_mem_init= noop,
- .mv_mem_reserve = sh_of_mem_reserve,
+ .mv_mode_pins = generic_mode_pins,
+ .mv_mem_init= sh_of_mem_init,
};
struct sh_clk_ops;
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
index 821a09cbd605..ce5b7c2f8628 100644
--- a/arch/sh/kernel/time.c
+++ b/arch/sh/kernel/time.c
@@ -19,7 +19,9 @@
#include
#include
#include
+#include
+#ifndef CONFIG_SH_DEVICE_TREE
static void __init sh_late_time_init(void)
{
/*
@@ -43,3 +45,13 @@ void __init time_init(void)
late_time_init = sh_late_time_init;
}
+#else
+/* CONFIG_SH_DEVICE_TREE */
+void __init time_init(void)
+{
+ pr_info("SH generic board support: scanning for clk providers\n");
+
+ of_clk_init(NULL);
+ timer_probe();
+}
+#endif
--
2.39.2
[PATCH v7 17/37] dt-bindings: interrupt-controller: renesas, sh7751-intc: Add json-schema
Renesas SH7751 INTC json-schema.
Signed-off-by: Yoshinori Sato
---
.../renesas,sh7751-intc.yaml | 53 +++
1 file changed, 53 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
new file mode 100644
index ..fb924eff465d
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id:
http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 Interrupt Controller
+
+maintainers:
+ - Yoshinori Sato
+
+properties:
+ compatible:
+items:
+ - const: renesas,sh7751-intc
+
+ '#interrupt-cells':
+const: 1
+
+ interrupt-controller: true
+
+ reg:
+maxItems: 2
+
+ reg-names:
+items:
+ - const: ICR
+ - const: INTPRI00
+
+ renesas,icr-irlm:
+$ref: /schemas/types.yaml#/definitions/flag
+description: If true four independent interrupt requests mode (ICR.IRLM is
1).
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - '#interrupt-cells'
+ - interrupt-controller
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+shintc: interrupt-controller@ffd0 {
+compatible = "renesas,sh7751-intc";
+reg = <0xffd0 14>, <0xfe08 128>;
+reg-names = "ICR", "INTPRI00";
+#interrupt-cells = <1>;
+interrupt-controller;
+};
+...
--
2.39.2
[PATCH v7 04/37] dt-bindings: interrupt-controller: Add header for Renesas SH3/4 INTC.
Renesas SH7751 Interrupt controller priority register define. Signed-off-by: Yoshinori Sato --- .../renesas,sh7751-intc.h | 19 +++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h diff --git a/include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h b/include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h new file mode 100644 index ..0543bd1b895e --- /dev/null +++ b/include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * SH3/4 INTC IPR register offsets (Address / bits) + */ + +#ifndef __DT_BINDINGS_RENESAS_SH7751_INTC +#define __DT_BINDINGS_RENESAS_SH7751_INTC + +#define IPRA 0 +#define IPRB 4 +#define IPRC 8 +#define IPRD 12 +#define INTPRI00 256 +#define IPR_B1212 +#define IPR_B8 8 +#define IPR_B4 4 +#define IPR_B0 0 + +#endif -- 2.39.2
[PATCH v7 20/37] serial: sh-sci: fix SH4 OF support.
- fix earlycon name.
- fix earlyprintk hung (NULL pointer reference).
- fix SERIAL_SH_SCI_EARLYCON enablement
Signed-off-by: Yoshinori Sato
Reviewed-by: Geert Uytterhoeven
---
drivers/tty/serial/Kconfig | 2 +-
drivers/tty/serial/sh-sci.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index ffcf4882b25f..dfe5fd436816 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -661,7 +661,7 @@ config SERIAL_SH_SCI_EARLYCON
depends on SERIAL_SH_SCI=y
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
- default ARCH_RENESAS
+ default ARCH_RENESAS || SUPERH
config SERIAL_SH_SCI_DMA
bool "DMA support" if EXPERT
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index e512eaa57ed5..46466fb5a637 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2717,7 +2717,7 @@ static int sci_remap_port(struct uart_port *port)
if (port->membase)
return 0;
- if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
+ if ((port->dev && port->dev->of_node) || (port->flags & UPF_IOREMAP)) {
port->membase = ioremap(port->mapbase, sport->reg_size);
if (unlikely(!port->membase)) {
dev_err(port->dev, "can't remap port#%d\n", port->line);
@@ -3545,8 +3545,8 @@ static int __init hscif_early_console_setup(struct
earlycon_device *device,
OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044",
rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r7s9210",
rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r9a07g044",
rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
--
2.39.2
[PATCH v7 06/37] sh: kernel/setup Update DT support.
Fix extrnal fdt initialize and bootargs.
Signed-off-by: Yoshinori Sato
---
arch/sh/Kconfig | 23 +++
arch/sh/include/asm/setup.h | 1 +
arch/sh/kernel/setup.c | 36 +++-
3 files changed, 35 insertions(+), 25 deletions(-)
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 6711cde0d973..242cf30e704d 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -708,17 +708,22 @@ config ROMIMAGE_MMCIF
first part of the romImage which in turn loads the rest the kernel
image to RAM using the MMCIF hardware block.
+config CMDLINE
+ string "Kernel command line arguments string"
+ default "console=ttySC1,115200"
+
choice
prompt "Kernel command line"
- optional
- default CMDLINE_OVERWRITE
- depends on !OF || USE_BUILTIN_DTB
+ default CMDLINE_BOOTLOADER
+
+config CMDLINE_BOOTLOADER
+ bool "Use bootloader kernel arguments"
help
- Setting this option allows the kernel command line arguments
- to be set.
+ Uses the command-line options passed by the boot loader.
+ If boot loader dosen't provide kernel argments, Use built-in argments.
config CMDLINE_OVERWRITE
- bool "Overwrite bootloader kernel arguments"
+ bool "Overwrite built-in kernel arguments"
help
Given string will overwrite any arguments passed in by
a bootloader.
@@ -730,12 +735,6 @@ config CMDLINE_EXTEND
by a bootloader.
endchoice
-
-config CMDLINE
- string "Kernel command line arguments string"
- depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND
- default "console=ttySC1,115200"
-
endmenu
menu "Bus options"
diff --git a/arch/sh/include/asm/setup.h b/arch/sh/include/asm/setup.h
index fc807011187f..84bb23a771f3 100644
--- a/arch/sh/include/asm/setup.h
+++ b/arch/sh/include/asm/setup.h
@@ -21,5 +21,6 @@
void sh_mv_setup(void);
void check_for_initrd(void);
void per_cpu_trap_init(void);
+void sh_fdt_init(phys_addr_t dt_phys);
#endif /* _SH_SETUP_H */
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 620e5cf8ae1e..42e6292a40cf 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -269,8 +270,22 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
void __init setup_arch(char **cmdline_p)
{
+#if defined(CONFIG_OF) && defined(CONFIG_OF_EARLY_FLATTREE)
+ if (IS_ENABLED(CONFIG_USE_BUILTIN_DTB)) {
+ /* Relocate Embedded DTB */
+ unflatten_and_copy_device_tree();
+ } else if (initial_boot_params) {
+ /* Reserve external DTB area */
+ memblock_reserve(__pa(initial_boot_params),
+fdt_totalsize(initial_boot_params));
+ unflatten_device_tree();
+ }
+ /* copy from /chosen/bootargs */
+ strscpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
+#endif
enable_mmu();
+#ifndef CONFIG_OF
ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
printk(KERN_NOTICE "Boot params:\n"
@@ -299,14 +314,17 @@ void __init setup_arch(char **cmdline_p)
bss_resource.start = virt_to_phys(__bss_start);
bss_resource.end = virt_to_phys(__bss_stop)-1;
-#ifdef CONFIG_CMDLINE_OVERWRITE
- strscpy(command_line, CONFIG_CMDLINE, sizeof(command_line));
-#else
- strscpy(command_line, COMMAND_LINE, sizeof(command_line));
+#endif
+#if !defined(CONFIG_OF) || defined(CONFIG_USE_BUILTIN_DTB)
+ if (*COMMAND_LINE)
+ strscpy(command_line, COMMAND_LINE, sizeof(command_line));
+#endif
+ if (*command_line == '\0' || IS_ENABLED(CONFIG_CMDLINE_OVERWRITE))
+ /* Use built-in parameter */
+ strscpy(command_line, CONFIG_CMDLINE, sizeof(command_line));
#ifdef CONFIG_CMDLINE_EXTEND
strlcat(command_line, " ", sizeof(command_line));
strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line));
-#endif
#endif
/* Save unparsed command line copy for /proc/cmdline */
@@ -322,14 +340,6 @@ void __init setup_arch(char **cmdline_p)
/* Let earlyprintk output early console messages */
sh_early_platform_driver_probe("earlyprintk", 1, 1);
-#ifdef CONFIG_OF_EARLY_FLATTREE
-#ifdef CONFIG_USE_BUILTIN_DTB
- unflatten_and_copy_device_tree();
-#else
- unflatten_device_tree();
-#endif
-#endif
-
paging_init();
/* Perform the machine specific initialisation */
--
2.39.2
[PATCH v7 11/37] pci: pci-sh7751: Add SH7751 PCI driver
Renesas SH7751 CPU Internal PCI Controller driver. Signed-off-by: Yoshinori Sato --- drivers/pci/controller/Kconfig | 9 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pci-sh7751.c | 342 3 files changed, 352 insertions(+) create mode 100644 drivers/pci/controller/pci-sh7751.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index e534c02ee34f..a2fd917a2e03 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -353,6 +353,15 @@ config PCIE_XILINX_CPM Say 'Y' here if you want kernel support for the Xilinx Versal CPM host bridge. +config PCI_SH7751 + bool "Renesas SH7751 PCI controller" + depends on OF + depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST + select PCI_HOST_COMMON + help + Say 'Y' here if you want kernel to support the Renesas SH7751 PCI + Host Bridge driver. + source "drivers/pci/controller/cadence/Kconfig" source "drivers/pci/controller/dwc/Kconfig" source "drivers/pci/controller/mobiveil/Kconfig" diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index f2b19e6174af..aa97e5d74e58 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o +obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ diff --git a/drivers/pci/controller/pci-sh7751.c b/drivers/pci/controller/pci-sh7751.c new file mode 100644 index ..a5340689f737 --- /dev/null +++ b/drivers/pci/controller/pci-sh7751.c @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SH7751 PCI driver + * Copyright (C) 2023 Yoshinori Sato + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PCICR and PCICLKCR write enable magic key */ +#define PCIC_WE_KEY(0xa5 << 24) + +/* PCIC registers */ +/* 0x - 0x00ff mapped to PCI device configuration space */ +#define PCIC_PCICR 0x100 /* PCI Control Register */ +#define PCIC_PCICR_TRSBBIT(9) /* Target Read Single */ +#define PCIC_PCICR_BSWPBIT(8) /* Target Byte Swap */ +#define PCIC_PCICR_PLUPBIT(7) /* Enable PCI Pullup */ +#define PCIC_PCICR_ARBMBIT(6) /* PCI Arbitration Mode */ +#define PCIC_PCICR_MD10BIT(5) /* MD10 status */ +#define PCIC_PCICR_MD9 BIT(4) /* MD9 status */ +#define PCIC_PCICR_SERRBIT(3) /* SERR output assert */ +#define PCIC_PCICR_INTABIT(2) /* INTA output assert */ +#define PCIC_PCICR_PRSTBIT(1) /* PCI Reset Assert */ +#define PCIC_PCICR_CFINBIT(0) /* Central Fun. Init Done */ + +#define PCIC_PCILSR0 0x104 /* PCI Local Space Register0 */ +#define PCIC_PCILSR1 0x108 /* PCI Local Space Register1 */ +#define PCIC_PCILAR0 0x10c /* PCI Local Addr Register1 */ +#define PCIC_PCILAR1 0x110 /* PCI Local Addr Register1 */ +#define PCIC_PCIINT0x114 /* PCI Interrupt Register */ +#define PCIC_PCIINTM 0x118 /* PCI Interrupt Mask */ +#define PCIC_PCIALR0x11c /* Error Address Register */ +#define PCIC_PCICLR0x120 /* Error Command/Data */ +#define PCIC_PCIAINT 0x130 /* Arbiter Interrupt Register */ +#define PCIC_PCIAINTM 0x134 /* Arbiter Int. Mask Register */ +#define PCIC_PCIBMLR 0x138 /* Error Bus Master Register */ +#define PCIC_PCIDMABT 0x140 /* DMA Transfer Arb. Register */ +#define PCIC_PCIPAR0x1c0 /* PIO Address Register */ +#define PCIC_PCIMBR0x1c4 /* Memory Base Address */ +#define PCIC_PCIIOBR 0x1c8 /* I/O Base Address Register */ + +#define PCIC_PCIPINT 0x1cc /* Power Mgmnt Int. Register */ +#define PCIC_PCIPINT_D3BIT(1) /* D3 Pwr Mgmt. Interrupt */ +#define PCIC_PCIPINT_D0BIT(0) /* D0 Pwr Mgmt. Interrupt */ + +#define PCIC_PCIPINTM 0x1d0 /* Power Mgmnt Mask Register */ +#define PCIC_PCICLKR 0x1d4 /* Clock Ctrl. Register */ +#define PCIC_PCIBCR1 0x1e0 /* Memory BCR1 Register */ +#define PCIC_PCIBCR2 0x1e4 /* Memory BCR2 Register */ +#define PCIC_PCIWCR1 0x1e8 /* Wait Control 1 Register */ +#define PCIC_PCIWCR2 0x1ec /* Wait Control 2 Register */ +#define PCIC_PCIWCR3 0x1f0 /* Wait Control 3 Register */ +#define PCIC_PCIMCR0x1f4 /* Memory Control Register */ +#define
[PATCH v7 10/37] sh: Common PCI Framework driver support.
Add New OF based PCI Host driver.
This driver conflicts some point in legacy PCI driver.
To resolve the conflict, I made some changes to the legacy driver.
Signed-off-by: Yoshinori Sato
---
arch/sh/include/asm/io.h | 6 ++
arch/sh/include/asm/pci.h | 4
arch/sh/kernel/iomap.c| 18 ++
3 files changed, 28 insertions(+)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 5c544cf5201b..29b5f996cde3 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#define __IO_PREFIX generic
#include
@@ -310,4 +311,9 @@ unsigned long long poke_real_address_q(unsigned long long
addr,
int valid_phys_addr_range(phys_addr_t addr, size_t size);
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+#if defined(CONFIG_PCI) && !defined(CONFIG_GENERIC_IOMAP)
+#define pci_remap_iospace pci_remap_iospace
+int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
+#endif
+
#endif /* __ASM_SH_IO_H */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index 54c30126ea17..92b3bd604319 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -2,6 +2,7 @@
#ifndef __ASM_SH_PCI_H
#define __ASM_SH_PCI_H
+#ifndef CONFIG_SH_DEVICE_TREE
/* Can be used to override the logic in pci_scan_bus for skipping
already-configured bus numbers - to be used for buggy BIOSes
or architectures with incomplete PCI setup by the loader */
@@ -88,4 +89,7 @@ static inline int pci_proc_domain(struct pci_bus *bus)
return hose->need_domain_info;
}
+#else /* CONFIG_SH_DEVICE_TREE */
+#include
+#endif
#endif /* __ASM_SH_PCI_H */
diff --git a/arch/sh/kernel/iomap.c b/arch/sh/kernel/iomap.c
index 0a0dff4e66de..d1b8e496ca23 100644
--- a/arch/sh/kernel/iomap.c
+++ b/arch/sh/kernel/iomap.c
@@ -160,3 +160,21 @@ void iowrite32_rep(void __iomem *addr, const void *src,
unsigned long count)
mmio_outsl(addr, src, count);
}
EXPORT_SYMBOL(iowrite32_rep);
+
+#if defined(pci_remap_iospace)
+int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
+{
+ unsigned long vaddr = res->start;
+
+ if (!(res->flags & IORESOURCE_IO))
+ return -EINVAL;
+
+ if (res->end > IO_SPACE_LIMIT)
+ return -EINVAL;
+
+ __set_io_port_base(phys_addr);
+ return vmap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
+ pgprot_device(PAGE_KERNEL));
+}
+EXPORT_SYMBOL(pci_remap_iospace);
+#endif
--
2.39.2
[PATCH v7 22/37] dt-bindings: display: smi, sm501: SMI SM501 binding json-schema
Signed-off-by: Yoshinori Sato --- .../bindings/display/smi,sm501.yaml | 398 ++ 1 file changed, 398 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/smi,sm501.yaml diff --git a/Documentation/devicetree/bindings/display/smi,sm501.yaml b/Documentation/devicetree/bindings/display/smi,sm501.yaml new file mode 100644 index ..06c6af4fa4a9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/smi,sm501.yaml @@ -0,0 +1,398 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/smi,sm501.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Motion SM501 Mobile Multimedia Companion Chip + +maintainers: + - Yoshinori Sato + +description: | + These DT bindings describe the SM501. + +properties: + compatible: +const: + smi,sm501 + + reg: +maxItems: 2 +description: | + First entry: System Configuration register + Second entry: IO space (Display Controller register) + + interrupts: +description: SM501 interrupt to the cpu should be described here. + + mode: +$ref: /schemas/types.yaml#/definitions/string +description: select a video mode + + edid: +description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + little-endian: +$ref: /schemas/types.yaml#/definitions/flag +description: available on big endian systems, to set different foreign endian. + big-endian: +$ref: /schemas/types.yaml#/definitions/flag +description: available on little endian systems, to set different foreign endian. + + swap-fb-endian: +$ref: /schemas/types.yaml#/definitions/flag +description: swap framebuffer byteorder. + + route-crt-panel: +$ref: /schemas/types.yaml#/definitions/flag +description: Panel output merge to CRT. + + crt: +type: object +description: CRT output control +properties: + edid: +$ref: /schemas/types.yaml#/definitions/uint8-array +description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + smi,flags: +$ref: /schemas/types.yaml#/definitions/string-array +description: Display control flags. +items: + anyOf: +- const: use-init-done +- const: disable-at-exit +- const: use-hwcursor +- const: use-hwaccel +- const: panel-no-fpen +- const: panel-no-vbiasen +- const: panel-inv-fpen +- const: panel-inv-vbiasen +maxItems: 8 + + bpp: +$ref: /schemas/types.yaml#/definitions/uint32 +description: Color depth + + panel: +type: object +description: Panel output control +properties: + edid: +$ref: /schemas/types.yaml#/definitions/uint8-array +description: | + verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + smi,flags: +$ref: /schemas/types.yaml#/definitions/string-array +description: Display control flags. +items: + anyOf: +- const: use-init-done +- const: disable-at-exit +- const: use-hwcursor +- const: use-hwaccel +- const: panel-no-fpen +- const: panel-no-vbiasen +- const: panel-inv-fpen +- const: panel-inv-vbiasen +maxItems: 8 + + bpp: +$ref: /schemas/types.yaml#/definitions/uint32 +description: Color depth + + smi,devices: +$ref: /schemas/types.yaml#/definitions/string-array +description: Select SM501 device functions. +items: + anyOf: +- const: usb-host +- const: usb-slave +- const: ssp0 +- const: ssp1 +- const: uart0 +- const: uart1 +- const: fbaccel +- const: ac97 +- const: i2s +- const: gpio +minItems: 1 +maxItems: 10 + + smi,mclk: +$ref: /schemas/types.yaml#/definitions/uint32 +description: mclk frequency. + + smi,m1xclk: +$ref: /schemas/types.yaml#/definitions/uint32 +description: m1xclk frequency. + + misc-timing: +type: object +description: Miscellaneous Timing register values. +properties: + ex: +$ref: /schemas/types.yaml#/definitions/uint32 +description: Extend bus holding time. + + xc: +$ref: /schemas/types.yaml#/definitions/uint32 +description: Xscale clock input select. + + usb-over-current-detect-disable: +$ref: /schemas/types.yaml#/definitions/flag +description: USB host current detection disable (Us=0
[PATCH v7 19/37] dt-bindings: interrupt-controller: renesas, sh7751-irl-ext: Add json-schema
Renesas SH7751 external interrupt encoder json-schema.
Signed-off-by: Yoshinori Sato
---
.../renesas,sh7751-irl-ext.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
new file mode 100644
index ..fc174c0467e7
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id:
http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 external interrupt encoder with enable regs.
+
+maintainers:
+ - Yoshinori Sato
+
+description:
+ This is the generally used external interrupt encoder on SH7751 based boards.
+
+properties:
+ compatible:
+items:
+ - const: renesas,sh7751-irl-ext
+
+ reg: true
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+const: 2
+
+ '#address-cells':
+const: 0
+
+ renesas,set-to-disable:
+$ref: /schemas/types.yaml#/definitions/flag
+description: Invert enable registers. Setting the bit to 0 enables
interrupts.
+
+ renesas,enable-reg:
+$ref: /schemas/types.yaml#/definitions/uint32-array
+description: |
+ IRQ enable register bit mapping
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+ - renesas,enable-reg
+
+additionalProperties: false
+
+examples:
+ - |
+r2dintc: interrupt-controller@a400 {
+compatible = "renesas,sh7751-irl-ext";
+reg = <0xa400 0x02>;
+interrupt-controller;
+#address-cells = <0>;
+#interrupt-cells = <1>;
+renesas,enable-reg = <12 9 10 3 0 4 1 2 8 5 6 7 15 15 15 11>;
+};
--
2.39.2
[PATCH v7 15/37] clk: renesas: Add SH7750/7751 CPG Driver
Renesas SH7750 and SH7751 series CPG driver.
This driver supported frequency control and clock gating.
Signed-off-by: Yoshinori Sato
---
drivers/clk/renesas/Kconfig | 13 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/clk-sh7750.c | 480 +++
3 files changed, 491 insertions(+), 3 deletions(-)
create mode 100644 drivers/clk/renesas/clk-sh7750.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index d252150402e8..482efcb6e76e 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
config CLK_RENESAS
- bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
- default y if ARCH_RENESAS
+ bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS &&
!SUPERH
+ default y if ARCH_RENESAS || SUPERH
select CLK_EMEV2 if ARCH_EMEV2
select CLK_RZA1 if ARCH_R7S72100
select CLK_R7S9210 if ARCH_R7S9210
@@ -41,6 +41,9 @@ config CLK_RENESAS
select CLK_R9A08G045 if ARCH_R9A08G045
select CLK_R9A09G011 if ARCH_R9A09G011
select CLK_SH73A0 if ARCH_SH73A0
+ select CLK_SH7750 if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
+CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751 || \
+CPU_SUBTYPE_SH7751R
if CLK_RENESAS
@@ -198,7 +201,6 @@ config CLK_SH73A0
select CLK_RENESAS_CPG_MSTP
select CLK_RENESAS_DIV6
-
# Family
config CLK_RCAR_CPG_LIB
bool "CPG/MSSR library functions" if COMPILE_TEST
@@ -228,6 +230,11 @@ config CLK_RZG2L
bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if
COMPILE_TEST
select RESET_CONTROLLER
+config CLK_SH7750
+ bool "Renesas SH7750/7751 family clock support" if COMPILE_TEST
+ help
+ This is a driver for SH7750 / SH7751 CPG.
+
# Generic
config CLK_RENESAS_CPG_MSSR
bool "CPG/MSSR clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index f7e18679c3b8..ea0ffa8d59c4 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A08G045)+= r9a08g045-cpg.o
obj-$(CONFIG_CLK_R9A09G011)+= r9a09g011-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
+obj-$(CONFIG_CLK_SH7750) += clk-sh7750.o
# Family
obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
diff --git a/drivers/clk/renesas/clk-sh7750.c b/drivers/clk/renesas/clk-sh7750.c
new file mode 100644
index ..043269d31200
--- /dev/null
+++ b/drivers/clk/renesas/clk-sh7750.c
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7750/51 CPG driver
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* PCLK divide rate selector */
+static const struct clk_div_table pdiv_table[] = {
+ { .val = 0, .div = 2, },
+ { .val = 1, .div = 3, },
+ { .val = 2, .div = 4, },
+ { .val = 3, .div = 6, },
+ { .val = 4, .div = 8, },
+ { }
+};
+
+/* ICLK and BCLK divide rate selector */
+static const struct clk_div_table div_table[] = {
+ { .val = 0, .div = 1, },
+ { .val = 1, .div = 2, },
+ { .val = 2, .div = 3, },
+ { .val = 3, .div = 4, },
+ { .val = 4, .div = 6, },
+ { .val = 5, .div = 8, },
+ { }
+};
+
+struct cpg_priv {
+ struct clk_hw hw;
+ spinlock_t clklock;
+ void __iomem *frqcr;
+ void __iomem *clkstp00;
+ u32 mode;
+ u32 feat;
+};
+
+/* CPG feature flag */
+#define CPG_DIV1 BIT(0) /* 7750, 7750S, 7751 */
+#define MSTP_CR2 BIT(1) /* 7750S, 7750R, 7751, 7751R */
+#define MSTP_CLKSTPBIT(2) /* 7750R, 7751, 7751R */
+#define MSTP_CSTP2 BIT(3) /* 7751, 7751R */
+
+enum {
+ CPG_SH7750,
+ CPG_SH7750S,
+ CPG_SH7750R,
+ CPG_SH7751,
+ CPG_SH7751R,
+};
+
+static const u32 cpg_feature[] = {
+ [CPG_SH7750] = CPG_DIV1,
+ [CPG_SH7750S] = CPG_DIV1 | MSTP_CR2,
+ [CPG_SH7750R] = MSTP_CR2 | MSTP_CLKSTP,
+ [CPG_SH7751] = CPG_DIV1 | MSTP_CR2 | MSTP_CLKSTP | MSTP_CSTP2,
+ [CPG_SH7751R] = MSTP_CR2 | MSTP_CLKSTP | MSTP_CSTP2,
+};
+
+enum clk_type {CLK_DIV, CLK_STBCR, CLK_STBCR2, CLK_CLKSTP00};
+
+enum {
+ FRQCR = 0,
+ STBCR = 4,
+ WTCNT = 8,
+ WTCSR = 12,
+ STBCR2 = 16,
+ CLKSTP00 = 0,
+ CLKSTPCLR00 = 8,
+};
+
+static struct cpg_priv *cpg_data;
+
+#define to_priv(_hw) container_of(_hw, struct cpg_priv, hw)
+
+#define FRQCR_PLL1EN BIT(10)
+static const unsigned int pll1mult[] = { 12, 12, 6, 12, 6, 12, 1};
+
+static unsigned long pll_recalc_rate(struct clk_hw *hw,
+
[PATCH v7 18/37] irqchip: SH7751 external interrupt encoder with enable gate.
SH7751 have 15 level external interrupt.
It is typically connected to the CPU through a priority encoder
that can suppress requests.
This driver provides a way to control those hardware with irqchip.
Signed-off-by: Yoshinori Sato
---
drivers/irqchip/Kconfig | 7 +
drivers/irqchip/Makefile| 2 +
drivers/irqchip/irq-renesas-sh7751irl.c | 221
3 files changed, 230 insertions(+)
create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 33badb5b4f00..7670fcd6757d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -698,4 +698,11 @@ config RENESAS_SH7751_INTC
Support for the Renesas SH7751 On-chip interrupt controller.
And external interrupt encoder for some targets.
+config RENESAS_SH7751IRL_INTC
+ bool "Renesas SH7751 based target IRL encoder support."
+ depends on RENESAS_SH7751_INTC
+ help
+ Support for External Interrupt encoder
+ on the some Renesas SH7751 based target.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 51855034a895..bc21d65441f2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -122,3 +122,5 @@ obj-$(CONFIG_APPLE_AIC) +=
irq-apple-aic.o
obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
+obj-$(CONFIG_RENESAS_SH7751IRL_INTC) += irq-renesas-sh7751irl.o
+
diff --git a/drivers/irqchip/irq-renesas-sh7751irl.c
b/drivers/irqchip/irq-renesas-sh7751irl.c
new file mode 100644
index ..5990f2cd9a3d
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-sh7751irl.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SH7751 based board external interrupt level encoder driver
+ * (Renesas RTS7751R2D / IO DATA DEVICE LANDISK, USL-5P)
+ *
+ * Copyright (C) 2023 Yoshinori Sato
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct sh7751irl_intc_priv {
+ struct irq_domain *irq_domain;
+ void __iomem *base;
+ unsigned int width;
+ bool invert;
+ u32 enable_bit[NR_IRL];
+};
+
+static inline unsigned long get_reg(void __iomem *addr, unsigned int w)
+{
+ switch (w) {
+ case 8:
+ return __raw_readb(addr);
+ case 16:
+ return __raw_readw(addr);
+ case 32:
+ return __raw_readl(addr);
+ default:
+ /* The size is checked when reading the properties. */
+ pr_err("%s: Invalid width %d", __FILE__, w);
+ return 0;
+ }
+}
+
+static inline void set_reg(void __iomem *addr, unsigned int w, unsigned long
val)
+{
+ switch (w) {
+ case 8:
+ __raw_writeb(val, addr);
+ break;
+ case 16:
+ __raw_writew(val, addr);
+ break;
+ case 32:
+ __raw_writel(val, addr);
+ break;
+ default:
+ pr_err("%s: Invalid width %d", __FILE__, w);
+ }
+}
+
+static inline struct sh7751irl_intc_priv *irq_data_to_priv(struct irq_data
*data)
+{
+ return data->domain->host_data;
+}
+
+static void irl_endisable(struct irq_data *data, unsigned int enable)
+{
+ struct sh7751irl_intc_priv *priv;
+ unsigned long val;
+ unsigned int irl;
+
+ priv = irq_data_to_priv(data);
+ irl = irqd_to_hwirq(data) - IRL_BASE_IRQ;
+
+ if (irl < NR_IRL && priv->enable_bit[irl] < priv->width) {
+ if (priv->invert)
+ enable = !enable;
+
+ val = get_reg(priv->base, priv->width);
+ if (enable)
+ set_bit(priv->enable_bit[irl], &val);
+ else
+ clear_bit(priv->enable_bit[irl], &val);
+ set_reg(priv->base, priv->width, val);
+ } else {
+ pr_err("%s: Invalid register define in IRL %u", __FILE__, irl);
+ }
+}
+
+static void sh7751irl_intc_disable_irq(struct irq_data *data)
+{
+ irl_endisable(data, 0);
+}
+
+static void sh7751irl_intc_enable_irq(struct irq_data *data)
+{
+ irl_endisable(data, 1);
+}
+
+static struct irq_chip sh7751irl_intc_chip = {
+ .name = "SH7751IRL-INTC",
+ .irq_enable = sh7751irl_intc_enable_irq,
+ .irq_disable= sh7751irl_intc_disable_irq,
+};
+
+static int sh7751irl_intc_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &sh7751irl_intc_chip, handle_level_irq);
+
Re: [DO NOT MERGE v6 17/37] dt-bindings: interrupt-controller: renesas, sh7751-intc: Add json-schema
On Tue, 09 Jan 2024 21:30:34 +0900, Linus Walleij wrote: > > Hi Yoshinori, > > thanks for your patch! > > On Tue, Jan 9, 2024 at 9:24 AM Yoshinori Sato > wrote: > > > + renesas,icr-irlm: > > +$ref: /schemas/types.yaml#/definitions/flag > > +description: If true four independent interrupt requests mode > > (ICR.IRLM is 1). > > + > > + renesas,ipr-map: > > +$ref: /schemas/types.yaml#/definitions/uint32-array > > +description: | > > + IRQ to IPR mapping definition. > > + 1st - INTEVT code > > + 2nd - Register > > + 3rd - bit index > > (...) > > > +renesas,ipr-map = <0x240 IPRD IPR_B12>, /* IRL0 */ > > + <0x2a0 IPRD IPR_B8>, /* IRL1 */ > > + <0x300 IPRD IPR_B4>, /* IRL2 */ > > + <0x360 IPRD IPR_B0>, /* IRL3 */ > (...) > > Is it really necessary to have all this in the device tree? > > You know from the compatible that this is "renesas,sh7751-intc" > and I bet this table will be the same for any sh7751 right? > > Then just put it in a table in the driver instead and skip this from > the device tree and bindings. If more interrupt controllers need > to be supported by the driver, you can simply look up the table from > the compatible string. The SH interrupt controller has the same structure, only this part is different for each SoC. Currently, we are targeting only the 7751, but in the future we plan to handle all SoCs. Is it better to differentiate SoC only by compatible? > Yours, > Linus Walleij > -- Yosinori Sato
