[PATCH v10 09/24] soc: mediatek: Support reset bit mapping in mmsys driver

[Hsiao Chien Sung]

- Reset ID must starts from 0 and be consecutive, but
  the reset bits in our hardware design is not continuous,
  some bits are left unused, we need a map to solve the problem
- Use old style 1-to-1 mapping if .rst_tb is not defined

Reviewed-by: AngeloGioacchino Del Regno 
<angelogioacchino.delre...@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.s...@mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++
 drivers/soc/mediatek/mtk-mmsys.h | 3 +++
 2 files changed, 12 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index b1db09e19905..3a7108eefe9d 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -314,6 +314,15 @@ static int mtk_mmsys_reset_update(struct 
reset_controller_dev *rcdev, unsigned l
        u32 offset;
        u32 reg;
 
+       if (mmsys->data->rst_tb) {
+               if (id >= mmsys->data->num_resets) {
+                       dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n",
+                               id, mmsys->data->num_resets);
+                       return -EINVAL;
+               }
+               id = mmsys->data->rst_tb[id];
+       }
+
        offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
        id = id % MMSYS_SW_RESET_PER_REG;
        reg = mmsys->data->sw0_rst_offset + offset;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 9d8507f98b7a..d370192737ca 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -78,6 +78,8 @@
 #define DSI_SEL_IN_RDMA                                0x1
 #define DSI_SEL_IN_MASK                                0x1
 
+#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit))
+
 struct mtk_mmsys_routes {
        u32 from_comp;
        u32 to_comp;
@@ -119,6 +121,7 @@ struct mtk_mmsys_driver_data {
        const struct mtk_mmsys_routes *routes;
        const unsigned int num_routes;
        const u16 sw0_rst_offset;
+       const u8 *rst_tb;
        const u32 num_resets;
        const bool is_vppsys;
        const u8 vsync_len;
-- 
2.18.0