[PATCH v2 21/27] drm/sun4i: DW HDMI PHY: Add support for second PLL

[Jernej Skrabec]

Some DW HDMI PHYs, like those found in A64 and R40 SoCs, can select
between two clock parents.

Add code which reads second PLL from DT.

Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h  |  2 ++
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 20 +++++++++++++++-----
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h 
b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index 3ba71aff92fc..46a3aa6a53a9 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -147,6 +147,7 @@ struct sun8i_hdmi_phy;
 
 struct sun8i_hdmi_phy_variant {
        bool has_phy_clk;
+       bool has_second_pll;
        void (*phy_init)(struct sun8i_hdmi_phy *phy);
        void (*phy_disable)(struct dw_hdmi *hdmi,
                            struct sun8i_hdmi_phy *phy);
@@ -160,6 +161,7 @@ struct sun8i_hdmi_phy {
        struct clk                      *clk_mod;
        struct clk                      *clk_phy;
        struct clk                      *clk_pll0;
+       struct clk                      *clk_pll1;
        unsigned int                    rcal;
        struct regmap                   *regs;
        struct reset_control            *rst_phy;
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c 
b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index cd07ceb71601..f50072ae054a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -482,10 +482,19 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, 
struct device_node *node)
                        goto err_put_clk_mod;
                }
 
+               if (phy->variant->has_second_pll) {
+                       phy->clk_pll1 = of_clk_get_by_name(node, "pll-1");
+                       if (IS_ERR(phy->clk_pll1)) {
+                               dev_err(dev, "Could not get pll-1 clock\n");
+                               ret = PTR_ERR(phy->clk_pll1);
+                               goto err_put_clk_pll0;
+                       }
+               }
+
                ret = sun8i_phy_clk_create(phy, dev);
                if (ret) {
                        dev_err(dev, "Couldn't create the PHY clock\n");
-                       goto err_put_clk_pll0;
+                       goto err_put_clk_pll1;
                }
 
                clk_prepare_enable(phy->clk_phy);
@@ -528,9 +537,10 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, 
struct device_node *node)
        reset_control_put(phy->rst_phy);
 err_disable_clk_phy:
        clk_disable_unprepare(phy->clk_phy);
+err_put_clk_pll1:
+       clk_put(phy->clk_pll1);
 err_put_clk_pll0:
-       if (phy->variant->has_phy_clk)
-               clk_put(phy->clk_pll0);
+       clk_put(phy->clk_pll0);
 err_put_clk_mod:
        clk_put(phy->clk_mod);
 err_put_clk_bus:
@@ -551,8 +561,8 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
 
        reset_control_put(phy->rst_phy);
 
-       if (phy->variant->has_phy_clk)
-               clk_put(phy->clk_pll0);
+       clk_put(phy->clk_pll0);
+       clk_put(phy->clk_pll1);
        clk_put(phy->clk_mod);
        clk_put(phy->clk_bus);
 }
-- 
2.17.1

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