Re: [PATCH v3 2/2] drm/panel: Add support for Raydium RM67191 panel driver
Hi Robert,
On Thu, Jun 20, 2019 at 10:31 AM Robert Chiras wrote:
> +fail:
> + if (rad->reset)
> + gpiod_set_value_cansleep(rad->reset, 1);
gpiod_set_value_cansleep() can handle NULL, so no need for the if() check.
> +static const struct display_timing rad_default_timing = {
> + .pixelclock = { 13200, 13200, 13200 },
Having the same information listed three times does not seem useful.
You could use a drm_display_mode structure with a single entry instead.
> + videomode_from_timing(&rad_default_timing, &panel->vm);
> +
> + of_property_read_u32(np, "width-mm", &panel->width_mm);
> + of_property_read_u32(np, "height-mm", &panel->height_mm);
> +
> + panel->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
Since this is optional it would be better to use
devm_gpiod_get_optional() instead.
> +
> + if (IS_ERR(panel->reset))
> + panel->reset = NULL;
> + else
> + gpiod_set_value_cansleep(panel->reset, 1);
This is not handling defer probing, so it would be better to do like this:
panel->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(panel->reset))
return PTR_ERR(panel->reset);
> + memset(&bl_props, 0, sizeof(bl_props));
> + bl_props.type = BACKLIGHT_RAW;
> + bl_props.brightness = 255;
> + bl_props.max_brightness = 255;
> +
> + panel->backlight = devm_backlight_device_register(dev, dev_name(dev),
> + dev, dsi,
> + &rad_bl_ops,
> + &bl_props);
Could you put more parameters into the same line?
Using 4 lines seems excessive.
> + if (IS_ERR(panel->backlight)) {
> + ret = PTR_ERR(panel->backlight);
> + dev_err(dev, "Failed to register backlight (%d)\n", ret);
> + return ret;
> + }
> +
> + drm_panel_init(&panel->panel);
> + panel->panel.funcs = &rad_panel_funcs;
> + panel->panel.dev = dev;
> + dev_set_drvdata(dev, panel);
> +
> + ret = drm_panel_add(&panel->panel);
> +
Unneeded blank line
> + if (ret < 0)
> + return ret;
> +
> + ret = mipi_dsi_attach(dsi);
> + if (ret < 0)
> + drm_panel_remove(&panel->panel);
> +
> + return ret;
You did not handle the "power" regulator.
> +static int __maybe_unused rad_panel_suspend(struct device *dev)
> +{
> + struct rad_panel *rad = dev_get_drvdata(dev);
> +
> + if (!rad->reset)
> + return 0;
> +
> + devm_gpiod_put(dev, rad->reset);
> + rad->reset = NULL;
> +
> + return 0;
> +}
> +
> +static int __maybe_unused rad_panel_resume(struct device *dev)
> +{
> + struct rad_panel *rad = dev_get_drvdata(dev);
> +
> + if (rad->reset)
> + return 0;
> +
> + rad->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
Why do you call devm_gpiod_get() once again?
I am having a hard time to understand the need for this suspend/resume hooks.
Can't you simply remove them?
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Re: [PATCH v3 1/2] dt-bindings: display: panel: Add support for Raydium RM67191 panel
Hi Robert, On Thu, Jun 20, 2019 at 10:32 AM Robert Chiras wrote: > > Add dt-bindings documentation for Raydium RM67191 DSI panel. > > Signed-off-by: Robert Chiras > Reviewed-by: Sam Ravnborg > --- > .../bindings/display/panel/raydium,rm67191.txt | 39 > ++ > 1 file changed, 39 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt > > diff --git > a/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt > b/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt > new file mode 100644 > index 000..52af272 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt > @@ -0,0 +1,39 @@ > +Raydium RM67171 OLED LCD panel with MIPI-DSI protocol > + > +Required properties: > +- compatible: "raydium,rm67191" > +- reg: virtual channel for MIPI-DSI protocol > + must be <0> > +- dsi-lanes: number of DSI lanes to be used > + must be <3> or <4> > +- port:input port node with endpoint definition as > + defined in > Documentation/devicetree/bindings/graph.txt; > + the input port should be connected to a MIPI-DSI > device > + driver > + > +Optional properties: > +- reset-gpios: a GPIO spec for the RST_B GPIO pin > +- width-mm:see panel-common.txt > +- height-mm: see panel-common.txt > +- video-mode: 0 - burst-mode > + 1 - non-burst with sync event > + 2 - non-burst with sync po ulse No power-supply property?
Re: [EXT] Re: [PATCH v3 1/2] dt-bindings: display: panel: Add support for Raydium RM67191 panel
Hi Robert, On Fri, Jun 21, 2019 at 11:16 AM Robert Chiras wrote: > From what I've seen in the schematics, the power lines on the DSI port > on all the i.MX8 cores are coming from a PMIC providing power for all > the peripherals. Since I didn't find a way to cut the power on a single > peripheral (like DSI, for example) it doesn't make sense for power- > supply property. For now, at least. This panel driver is not supposed to only work with i.MX8 NXP reference boards. The dt-bindings should be as accurate as possible from day one, so describing the power-supply is important. Please look at the panel datasheet and describe the required power supplies accordingly. Thanks
Re: [EXT] Re: [PATCH v3 2/2] drm/panel: Add support for Raydium RM67191 panel driver
Hi Robert, On Mon, Jun 24, 2019 at 4:44 AM Robert Chiras wrote: > > You did not handle the "power" regulator. > There is no need for a power regulator. I am sure the panel requires power to be applied so that it can work :-) > > Can't you simply remove them? > The reset gpio pin is shared between the DSI display controller and Looking at the imx8mq-evk schematics it is not clear for me what pin in shared between the OLED display and touch screen. Could you please clarify which pin you are referring to? > touch controller, both found on the same panel. Since, the touch driver > also acceses this gpio pin, in some cases the display can be put to > sleep, but the touch is still active. This is why, during suspend I > release the gpio resource, and I have to take it back in resume. > Without this release/acquire mechanism during suspend/resume, stress- > tests showed some failures: the resume freezes completly. Looking at the imx8mq-evk dts from the vendor tree I see that the touchscreen is not supported in mainline yet. Maybe there is a better way to solve this, so what if you don't introduce the suspend/resume hooks for now and then we revisit this after the touchscreen driver is added?
Re: [PATCH v4 2/2] drm/panel: Add support for Raydium RM67191 panel driver
Hi Robert,
On Tue, Jun 25, 2019 at 4:28 AM Robert Chiras wrote:
> +static int rad_bl_get_brightness(struct backlight_device *bl)
> +{
> + struct mipi_dsi_device *dsi = bl_get_data(bl);
> + struct rad_panel *rad = mipi_dsi_get_drvdata(dsi);
> + struct device *dev = &dsi->dev;
> + u16 brightness;
> + int ret;
> +
> + if (!rad->prepared)
> + return 0;
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "\n");
Please remove this debug line.
> + if (!rad->prepared)
> + return 0;
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "New brightness: %d\n",
> bl->props.brightness);
Please remove it.
> + ret = of_property_read_u32(np, "dsi-lanes", &dsi->lanes);
> + if (ret) {
> + dev_err(dev, "Failed to get dsi-lanes property (%d)\n", ret);
> + return ret;
> + }
> +
> + panel->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
Even it is optional, you still need to check for error and propagate
it in the case of error.
Otherwise defer probe will not work.
> + ret = drm_panel_add(&panel->panel);
> + if (ret)
> + return ret;
> +
> +
One blank line is enough.
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Re: [PATCH v5 1/2] dt-bindings: display: panel: Add support for Raydium RM67191 panel
On Wed, Jun 26, 2019 at 7:21 AM Robert Chiras wrote: > > Add dt-bindings documentation for Raydium RM67191 DSI panel. > > Signed-off-by: Robert Chiras > Reviewed-by: Sam Ravnborg Reviewed-by: Fabio Estevam ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v5 2/2] drm/panel: Add support for Raydium RM67191 panel driver
Hi Robert, On Wed, Jun 26, 2019 at 7:21 AM Robert Chiras wrote: > > This patch adds Raydium RM67191 TFT LCD panel driver (MIPI-DSI > protocol). > > Signed-off-by: Robert Chiras > Reviewed-by: Sam Ravnborg Looks good to me: Reviewed-by: Fabio Estevam Thanks
Re: [PATCH] drm/etnaviv: add missing failure path to destroy suballoc
Hi Lucas, On Thu, Jun 27, 2019 at 11:44 AM Lucas Stach wrote: > > When something goes wrong in the GPU init after the cmdbuf suballocator > has been constructed, we fail to destory it properly. This causes havok s/destory/destroy > later when the GPU is unbound due to a module unload or similar. Should this one have a Fixes tag? Thanks ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 2/3] dt-bindings: Add Rocktech jh057n00900 panel bindings
On Mon, Mar 25, 2019 at 11:06 AM Guido Günther wrote:
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.txt
> @@ -0,0 +1,18 @@
> +Rocktech jh057n00900 5.5" 720x1440 TFT LCD panel
> +
> +Required properties:
> +- compatible: should be "rocktech,jh057n00900"
> +- reg: DSI virtual channel of the peripheral
> +- reset-gpios: panel reset gpio
> +- backlight: phandle of the backlight device attached to the panel
> +
> +Example:
> +
> + &mipi_dsi {
> + panel {
> + compatible = "rocktech,jh057n00900";
> + reg = <0>;
Passing the reg property without its corresponding @0 would cause a
dtc warning when building with W=1.
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Re: [PATCH v2 3/3] drm/panel: simple: Add support for VXT VL050-8048NT-C01 panel
Hi Thierry, On Mon, Feb 18, 2019 at 9:27 PM Fabio Estevam wrote: > > Add support for the VXT VL050-8048NT-C01 800x480 panel to the > panel-simple driver. > > This panel is used on some boards manufactured by TechNexion, such as > imx7d-pico. > > Reviewed-by: Otavio Salvador > Reviewed-by: Sam Ravnborg > Signed-off-by: Fabio Estevam Any feedback, please? Trying to get this one upstreamed for four months already and hope to get it to 5.2. Thanks ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/bridge: Improve the help text for DRM_ANALOGIX_ANX78XX
Improve the help text for DRM_ANALOGIX_ANX78XX by adding the missing "power" word. After this change the help text matches with the ANX7814 product description from the Analogix website: https://www.analogix.com/en/products/convertersbridges/anx7814 Signed-off-by: Fabio Estevam --- drivers/gpu/drm/bridge/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index ee777469293a..a6eec908c43e 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -21,7 +21,7 @@ config DRM_ANALOGIX_ANX78XX select DRM_KMS_HELPER select REGMAP_I2C ---help--- - ANX78XX is an ultra-low Full-HD SlimPort transmitter + ANX78XX is an ultra-low power Full-HD SlimPort transmitter designed for portable devices. The ANX78XX transforms the HDMI output of an application processor to MyDP or DisplayPort. -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 3/3] drm/bridge: Add NWL MIPI DSI host controller support
Hi Guido,
Thanks for your work on this driver!
On Wed, Jul 24, 2019 at 12:52 PM Guido Günther wrote:
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/imx-nwl/Kconfig
> @@ -0,0 +1,15 @@
> +config DRM_IMX_NWL_DSI
> + tristate "Support for Northwest Logic MIPI DSI Host controller"
> + depends on DRM && (ARCH_MXC || ARCH_MULTIPLATFORM || COMPILE_TEST)
This IP could potentially be found on other SoCs, so no need to make
it depend on ARCH_MXC.
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
I did not find gpio AP used in this driver.
> +static void imx_nwl_dsi_set_clocks(struct imx_nwl_dsi *dsi, bool enable)
Better make it to return 'int' instead...
> +{
> + struct device *dev = dsi->dev;
> + const char *id;
> + struct clk *clk;
> + unsigned long new_rate, cur_rate;
> + bool enabled;
> + size_t i;
> + int ret;
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "%sabling platform clocks",
Please remove the letter 's' from 'sabling'.
> +enable ? "en" : "dis");
> + ret = clk_prepare_enable(clk);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "Failed to enable clock
> %s",
> + id);
and propagate the error in case of clk_prepare_enable() failure.
> + }
> + dsi->clk_config[i].enabled = true;
> + cur_rate = clk_get_rate(clk);
> + DRM_DEV_DEBUG_DRIVER(
> + dev, "Enabled %s clk (rate: req=%lu
> act=%lu)\n",
> + id, new_rate, cur_rate);
> + } else if (enabled) {
> + clk_disable_unprepare(clk);
> + dsi->clk_config[i].enabled = false;
> + DRM_DEV_DEBUG_DRIVER(dev, "Disabled %s clk\n", id);
> + }
> + }
> +}
> +
> +static void imx_nwl_dsi_enable(struct imx_nwl_dsi *dsi)
Same here. Please return 'int' instead.
> +{
> + struct device *dev = dsi->dev;
> + int ret;
> +
> + imx_nwl_dsi_set_clocks(dsi, true);
> +
> + ret = dsi->pdata->poweron(dsi);
> + if (ret < 0)
> + DRM_DEV_ERROR(dev, "Failed to power on DSI (%d)\n", ret);
If the power domain failed to turn on, it is better to propagate the error.
> + phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
> + DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate);
> + if (ret < 0) {
This check looks wrong. At this point ret is always 0.
> + DRM_DEV_ERROR(dsi->dev,
> + "Cannot setup PHY for mode: %ux%u @%d Hz\n",
> + adjusted_mode->hdisplay,
> adjusted_mode->vdisplay,
> + adjusted_mode->clock);
> + DRM_DEV_ERROR(dsi->dev, "PHY ref clk: %lu, bit clk: %lu\n",
> + phy_ref_rate, new_cfg.mipi_dphy.hs_clk_rate);
> + } else {
> + /* Save the new desired phy config */
> + memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));
> + }
> +
> + /* LCDIF + NWL needs active high sync */
Would this still work if DCSS is used instead?
> + adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> + adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC |
> DRM_MODE_FLAG_NVSYNC);
> +
> + drm_display_mode_to_videomode(adjusted_mode, &dsi->vm);
> + drm_mode_debug_printmodeline(adjusted_mode);
> +
> + return ret == 0;
At this point ret is always 0.
> +static void imx_nwl_dsi_bridge_pre_enable(struct drm_bridge *bridge)
> +{
> + struct imx_nwl_dsi *dsi = bridge_to_dsi(bridge);
> +
> + if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
> + return;
> +
> + imx_nwl_select_input_source(dsi);
This function is i.MX8M specific, so better protect it to run only for
the i.MX8M variant.
> + pm_runtime_get_sync(dsi->dev);
> + imx_nwl_dsi_enable(dsi);
> + nwl_dsi_enable(dsi);
Please check the error and propagate in the case of failure.
> + dsi->dpms_mode = DRM_MODE_DPMS_ON;
> +}
> +
> + dsi->csr = syscon_regmap_lookup_by_phandle(np, "csr");
> + if (IS_ERR(dsi->csr) && dsi->pdata->ext_regs & IMX_REG_CSR) {
> + ret = PTR_ERR(dsi->csr);
> + DRM_DEV_ERROR(dsi->dev, "Failed to get CSR regmap: %d\n",
In this function (and globally in the driver) there is a mix of
DRM_DEV_ERROR() and dev_err().
Can we just pick one of the two and use it consistently?
Not sure what is the norm in drm code, but IMHO dev_err() looks prettier :-)
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dsi->dev, res);
Could use devm_platform_ioremap_resource(), which makes it simpler.
> +err_cleanup:
>
Re: [PATCH 1/1] drm: mxsfb: add i.MX6UL in Kconfig
Hi Sébastien, On Mon, Jul 29, 2019 at 11:14 AM Sébastien Szymanski wrote: > config DRM_MXSFB > - tristate "i.MX23/i.MX28/i.MX6SX MXSFB LCD controller" > + tristate "i.MX23/i.MX28/i.MX6SX/i.MX6UL MXSFB LCD controller" This IP is also found on i.MX6SL, i.MX7D, i.MX7S, i.MX8M, i.MX8QXP, etc I think it would be better if we do not keep increasing the list of supported SoCs in the Kconfig text. What about just having the text like this instead? tristate "MXSFB LCD controller" > depends on DRM && OF > depends on COMMON_CLK > select DRM_MXS > @@ -14,7 +14,7 @@ config DRM_MXSFB > select DRM_KMS_CMA_HELPER > select DRM_PANEL > help > - Choose this option if you have an i.MX23/i.MX28/i.MX6SX MXSFB > + Choose this option if you have an i.MX23/i.MX28/i.MX6SX/i.MX6UL > MXSFB > LCD controller. and here it would become: Choose this option if you want to support the MXSFB LCD controller. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 1/1] drm: mxsfb: add i.MX6UL in Kconfig
Hi Sam, On Mon, Jul 29, 2019 at 11:37 AM Sam Ravnborg wrote: > Could we throw a COMPILE_TEST in the mix so we get better build > coverage too? There is no architecture dependency to build this driver, so we already have build coverage for it. Regards, Fabio Estevam ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 3/3] drm/bridge: Add NWL MIPI DSI host controller support
Hi Guido, On Wed, Jul 31, 2019 at 11:35 AM Guido Günther wrote: > The idea is to have > > "%sabling platform clocks", enable ? "en" : "dis"); > > depending whether clocks are enabled/disabled. Yes, I understood the idea, but this would print: ensabling or dissabling :-) > > Same here. Please return 'int' instead. > > This is from drm_bridge_funcs so the prototype is fixed. I'm not sure > how what's the best way to bubble up fatal errors through the drm layer? Ok, so let's not change this one. > I went for DRM_DEV_ERROR() since that what i used in the rest of the > driver and these ones were omission. Hope that's o.k. No strong preferences here. I just think dev_err() easier to type and shorter. Thanks for this work! ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 3/3] drm/bridge: Add NWL MIPI DSI host controller support
On Wed, Jul 31, 2019 at 1:40 PM Jernej Škrabec wrote: > > Yes, I understood the idea, but this would print: > > > > ensabling or dissabling :-) > > No, it wouldn't. That extra "s" is part of "%s", e.g. part of format > specifier. Ops, you are right. Sorry about that! ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/imx: Drop unused imx-ipuv3-crtc.o build
Hi Guido,
Good catch!
On Fri, Aug 2, 2019 at 7:55 AM Guido Günther wrote:
>
> Since
>
> commit 3d1df96ad468 ("drm/imx: merge imx-drm-core and ipuv3-crtc in one
> module")
>
> imx-ipuv3-crtc.o is built via imxdrm-objs. So there's no need to keep an
Actually, it is ipuv3-crtc.o that is built via imxdrm-objs, not
imx-ipuv3-crtc.o.
Apart from that:
Reviewed-by: Fabio Estevam
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[PATCH 1/2] dt-bindings: display: simple: Add Startek KD070WVFPA043-C069A panel
From: Fabio Estevam Add Startek KD070WVFPA043-C069A 7" TFT LCD panel compatible string. Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 1eb9dd4f8f58..e190eef66872 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -294,6 +294,8 @@ properties: - starry,kr070pe2t # Starry 12.2" (1920x1200 pixels) TFT LCD panel - starry,kr122ea0sra +# Startek KD070WVFPA043-C069A 7" TFT LCD panel + - startek,kd070wvfpa # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel - team-source-display,tst043015cmhx # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel -- 2.25.1
[PATCH 2/2] drm/panel: simple: Add Startek KD070WVFPA043-C069A panel support
From: Heiko Schocher
Add Startek KD070WVFPA043-C069A 7" TFT LCD panel support.
Signed-off-by: Heiko Schocher
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/panel/panel-simple.c | 33
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index a34f4198a534..ca8cd017821d 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3311,6 +3311,36 @@ static const struct panel_desc tsd_tst043015cmhx = {
.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
};
+static const struct display_timing startek_kd070wvfpa_mode = {
+ .pixelclock = { 2520, 2720, 3050 },
+ .hactive = { 800, 800, 800 },
+ .hfront_porch = { 19, 44, 115 },
+ .hback_porch = { 5, 16, 101 },
+ .hsync_len = { 1, 2, 100 },
+ .vactive = { 480, 480, 480 },
+ .vfront_porch = { 5, 43, 67 },
+ .vback_porch = { 5, 5, 67 },
+ .vsync_len = { 1, 2, 66 },
+};
+
+static const struct panel_desc startek_kd070wvfpa = {
+ .timings = &startek_kd070wvfpa_mode,
+ .num_timings = 1,
+ .bpc = 8,
+ .size = {
+ .width = 152,
+ .height = 91,
+ },
+ .delay = {
+ .prepare = 20,
+ .enable = 200,
+ .disable = 200,
+ },
+ .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+};
+
static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
.clock = 3,
.hdisplay = 800,
@@ -3990,6 +4020,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "starry,kr070pe2t",
.data = &starry_kr070pe2t,
+ }, {
+ .compatible = "startek,kd070wvfpa",
+ .data = &startek_kd070wvfpa,
}, {
.compatible = "team-source-display,tst043015cmhx",
.data = &tsd_tst043015cmhx,
--
2.25.1
[PATCH v2 1/2] dt-bindings: display: simple: Add Startek KD070WVFPA043-C069A panel
From: Fabio Estevam Add Startek KD070WVFPA043-C069A 7" TFT LCD panel compatible string. Signed-off-by: Fabio Estevam Acked-by: Sam Ravnborg --- Changes since v1: - None. Only added Sam's ack. .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 1eb9dd4f8f58..e190eef66872 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -294,6 +294,8 @@ properties: - starry,kr070pe2t # Starry 12.2" (1920x1200 pixels) TFT LCD panel - starry,kr122ea0sra +# Startek KD070WVFPA043-C069A 7" TFT LCD panel + - startek,kd070wvfpa # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel - team-source-display,tst043015cmhx # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel -- 2.25.1
[PATCH v2 2/2] drm/panel: simple: Add Startek KD070WVFPA043-C069A panel support
From: Heiko Schocher
Add Startek KD070WVFPA043-C069A 7" TFT LCD panel support.
Signed-off-by: Heiko Schocher
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Put the panel entry in the correct order (Sam).
drivers/gpu/drm/panel/panel-simple.c | 33
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index a34f4198a534..61d82d7be1ba 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3284,6 +3284,36 @@ static const struct panel_desc starry_kr070pe2t = {
.connector_type = DRM_MODE_CONNECTOR_DPI,
};
+static const struct display_timing startek_kd070wvfpa_mode = {
+ .pixelclock = { 2520, 2720, 3050 },
+ .hactive = { 800, 800, 800 },
+ .hfront_porch = { 19, 44, 115 },
+ .hback_porch = { 5, 16, 101 },
+ .hsync_len = { 1, 2, 100 },
+ .vactive = { 480, 480, 480 },
+ .vfront_porch = { 5, 43, 67 },
+ .vback_porch = { 5, 5, 67 },
+ .vsync_len = { 1, 2, 66 },
+};
+
+static const struct panel_desc startek_kd070wvfpa = {
+ .timings = &startek_kd070wvfpa_mode,
+ .num_timings = 1,
+ .bpc = 8,
+ .size = {
+ .width = 152,
+ .height = 91,
+ },
+ .delay = {
+ .prepare = 20,
+ .enable = 200,
+ .disable = 200,
+ },
+ .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+};
+
static const struct display_timing tsd_tst043015cmhx_timing = {
.pixelclock = { 500, 900, 1200 },
.hactive = { 480, 480, 480 },
@@ -3990,6 +4020,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "starry,kr070pe2t",
.data = &starry_kr070pe2t,
+ }, {
+ .compatible = "startek,kd070wvfpa",
+ .data = &startek_kd070wvfpa,
}, {
.compatible = "team-source-display,tst043015cmhx",
.data = &tsd_tst043015cmhx,
--
2.25.1
[PATCH v3 2/2] drm/panel: simple: Add Startek KD070WVFPA043-C069A panel support
From: Heiko Schocher
Add Startek KD070WVFPA043-C069A 7" TFT LCD panel support.
Signed-off-by: Heiko Schocher
[fabio: passed .flags and .bus_flags]
Signed-off-by: Fabio Estevam
Acked-by: Sam Ravnborg
---
Changes since v2:
- Pass the full flags and bus_flags.
drivers/gpu/drm/panel/panel-simple.c | 38
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 595396f57632..8c9fae298d9b 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3310,6 +3310,41 @@ static const struct panel_desc starry_kr070pe2t = {
.connector_type = DRM_MODE_CONNECTOR_DPI,
};
+static const struct display_timing startek_kd070wvfpa_mode = {
+ .pixelclock = { 2520, 2720, 3050 },
+ .hactive = { 800, 800, 800 },
+ .hfront_porch = { 19, 44, 115 },
+ .hback_porch = { 5, 16, 101 },
+ .hsync_len = { 1, 2, 100 },
+ .vactive = { 480, 480, 480 },
+ .vfront_porch = { 5, 43, 67 },
+ .vback_porch = { 5, 5, 67 },
+ .vsync_len = { 1, 2, 66 },
+ .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
+DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
+DISPLAY_FLAGS_SYNC_POSEDGE,
+};
+
+static const struct panel_desc startek_kd070wvfpa = {
+ .timings = &startek_kd070wvfpa_mode,
+ .num_timings = 1,
+ .bpc = 8,
+ .size = {
+ .width = 152,
+ .height = 91,
+ },
+ .delay = {
+ .prepare = 20,
+ .enable = 200,
+ .disable = 200,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH |
+DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
+DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
+};
+
static const struct display_timing tsd_tst043015cmhx_timing = {
.pixelclock = { 500, 900, 1200 },
.hactive = { 480, 480, 480 },
@@ -4019,6 +4054,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "starry,kr070pe2t",
.data = &starry_kr070pe2t,
+ }, {
+ .compatible = "startek,kd070wvfpa",
+ .data = &startek_kd070wvfpa,
}, {
.compatible = "team-source-display,tst043015cmhx",
.data = &tsd_tst043015cmhx,
--
2.25.1
[PATCH v3 1/2] dt-bindings: display: simple: Add Startek KD070WVFPA043-C069A panel
From: Fabio Estevam Add Startek KD070WVFPA043-C069A 7" TFT LCD panel compatible string. Signed-off-by: Fabio Estevam Acked-by: Sam Ravnborg --- Changes since v2: - None .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 1eb9dd4f8f58..e190eef66872 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -294,6 +294,8 @@ properties: - starry,kr070pe2t # Starry 12.2" (1920x1200 pixels) TFT LCD panel - starry,kr122ea0sra +# Startek KD070WVFPA043-C069A 7" TFT LCD panel + - startek,kd070wvfpa # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel - team-source-display,tst043015cmhx # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel -- 2.25.1
Re: imx8mm lcdif->dsi->adv7535 no video, no errors
Hi Adam, On Sat, Jul 30, 2022 at 12:16 PM Adam Ford wrote: > > Hey all, > > I am trying to test Jagan's patch series [1] to add support for the > samsung dsim bridge which is used on the imx8mm to output DSI video. > The DSIM gets the video from the mxsfb, and in my case, the DSI is > sent to the adv7535 for connecting to HDMI. I had to add some extra patches on top of Jagan's imx8mm-dsi-v3 to get HDMI output functional on a imx8mm-evk via ADV7535: https://github.com/fabioestevam/kernel/commits/imx8mm-dsi-v3 Does it work on your board?
Re: imx8mm lcdif->dsi->adv7535 no video, no errors
Hi Marco, On Mon, Aug 1, 2022 at 7:55 PM Marco Felsch wrote: > Question is, does your setup work for all modes after applying your > patches and without using the NXP-downstream porches settings? We also Without Frieder's patch: "drm/exynos: Fix horizontal timing settings in MHPORCH/MSYNC registers", I get no HDMI output. Regards, Fabio Estevam
Re: imx8mm lcdif->dsi->adv7535 no video, no errors
On Mon, Aug 1, 2022 at 10:39 PM Adam Ford wrote: > I managed to get my HDMI output working. I had the lanes set to 2 > instead of 4. Once I switched to 4-lanes, the monitor came up in > 1080p. I haven't yet been able to get other modes to work. Ok, good. On another thread, you mentioned that you were also trying to get LVDS to work via SN65DSI83. Does LVDS work for you on this branch?
[PATCH] drm: bridge: adv7511: Move CEC definitions to adv7511_cec.c
ADV7511_REG_CEC_RX_FRAME_HDR[] and ADV7511_REG_CEC_RX_FRAME_LEN[]
are only used inside adv7511_cec.c.
Move their definitions to this file to avoid the following build
warnings when CONFIG_DRM_I2C_ADV7511_CEC is not selected:
drivers/gpu/drm/bridge/adv7511/adv7511.h:229:17: warning:
'ADV7511_REG_CEC_RX_FRAME_HDR' defined but not used [-Wunused-const-variable=]
drivers/gpu/drm/bridge/adv7511/adv7511.h:235:17: warning:
'ADV7511_REG_CEC_RX_FRAME_LEN' defined but not used [-Wunused-const-variable=]
Reported-by: kernel test robot
Fixes: ab0af093bf90 ("drm: bridge: adv7511: use non-legacy mode for CEC RX")
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/adv7511/adv7511.h | 12
drivers/gpu/drm/bridge/adv7511/adv7511_cec.c | 12
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h
b/drivers/gpu/drm/bridge/adv7511/adv7511.h
index 9e3bb8a8ee40..a031a0cd1f18 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
@@ -226,18 +226,6 @@
#define ADV7511_REG_CEC_CLK_DIV0x4e
#define ADV7511_REG_CEC_SOFT_RESET 0x50
-static const u8 ADV7511_REG_CEC_RX_FRAME_HDR[] = {
- ADV7511_REG_CEC_RX1_FRAME_HDR,
- ADV7511_REG_CEC_RX2_FRAME_HDR,
- ADV7511_REG_CEC_RX3_FRAME_HDR,
-};
-
-static const u8 ADV7511_REG_CEC_RX_FRAME_LEN[] = {
- ADV7511_REG_CEC_RX1_FRAME_LEN,
- ADV7511_REG_CEC_RX2_FRAME_LEN,
- ADV7511_REG_CEC_RX3_FRAME_LEN,
-};
-
#define ADV7533_REG_CEC_OFFSET 0x70
enum adv7511_input_clock {
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
index 399f625a50c8..0b266f28f150 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
@@ -15,6 +15,18 @@
#include "adv7511.h"
+static const u8 ADV7511_REG_CEC_RX_FRAME_HDR[] = {
+ ADV7511_REG_CEC_RX1_FRAME_HDR,
+ ADV7511_REG_CEC_RX2_FRAME_HDR,
+ ADV7511_REG_CEC_RX3_FRAME_HDR,
+};
+
+static const u8 ADV7511_REG_CEC_RX_FRAME_LEN[] = {
+ ADV7511_REG_CEC_RX1_FRAME_LEN,
+ ADV7511_REG_CEC_RX2_FRAME_LEN,
+ ADV7511_REG_CEC_RX3_FRAME_LEN,
+};
+
#define ADV7511_INT1_CEC_MASK \
(ADV7511_INT1_CEC_TX_READY | ADV7511_INT1_CEC_TX_ARBIT_LOST | \
ADV7511_INT1_CEC_TX_RETRY_TIMEOUT | ADV7511_INT1_CEC_RX_READY1 | \
--
2.25.1
[PATCH] drm/bridge: ti-sn65dsi83: Add a sysfs entry for the pattern generator
From: Fabio Estevam
The sn65dsi83 chip has a test pattern generator capability.
Add a sysfs entry to allow enabling and disabling it in runtime.
This is helpful during the MIPI DSI/LVDS bringup.
To enable the test pattern generator:
echo 1 > /sys/bus/i2c/devices/0-002c/pattern_generator
To disable the test pattern generator:
echo 0 > /sys/bus/i2c/devices/0-002c/pattern_generator
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/ti-sn65dsi83.c | 42 +++
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
index 14e7aa77e758..bb94b3fe9b17 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
@@ -731,6 +731,47 @@ static const struct of_device_id sn65dsi83_match_table[] =
{
};
MODULE_DEVICE_TABLE(of, sn65dsi83_match_table);
+static ssize_t pattern_generator_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ struct sn65dsi83 *ctx = dev_get_drvdata(dev);
+ bool arg;
+ int ret;
+
+ ret = kstrtobool(buf, &arg);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, arg ? 0x10 :
0x00);
+ if (ret < 0)
+ return ret;
+
+ return len;
+}
+
+static ssize_t pattern_generator_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sn65dsi83 *ctx = dev_get_drvdata(dev);
+ int ret, test_pattern;
+
+ ret = regmap_read(ctx->regmap, REG_VID_CHA_TEST_PATTERN, &test_pattern);
+ if (ret < 0)
+ return ret;
+
+ return sprintf(buf, "%d\n", !!test_pattern);
+}
+
+static DEVICE_ATTR_RW(pattern_generator);
+
+static struct attribute *sn65dsi83_attrs[] = {
+ &dev_attr_pattern_generator.attr,
+ NULL,
+};
+
+ATTRIBUTE_GROUPS(sn65dsi83);
+
static struct i2c_driver sn65dsi83_driver = {
.probe = sn65dsi83_probe,
.remove = sn65dsi83_remove,
@@ -738,6 +779,7 @@ static struct i2c_driver sn65dsi83_driver = {
.driver = {
.name = "sn65dsi83",
.of_match_table = sn65dsi83_match_table,
+ .dev_groups = sn65dsi83_groups,
},
};
module_i2c_driver(sn65dsi83_driver);
--
2.25.1
Re: [PATCH v3 01/17] fbcon: delete a few unneeded forward decl
On Tue, Apr 5, 2022 at 6:04 PM Daniel Vetter wrote: > > I didn't bother with any code movement to fix the others, these just > got a bit in the way. > > v2: Rebase on top of Helge's reverts. > > Acked-by: Thomas Zimmermann > Acked-by: Sam Ravnborg (v1) > Reviewed-by: Geert Uytterhoeven (v1) > Signed-off-by: Daniel Vetter > Cc: Helge Deller > Cc: Daniel Vetter > Cc: Thomas Zimmermann > Cc: Du Cheng > Cc: Tetsuo Handa > Cc: Claudio Suarez >From checkpatch: WARNING: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter '
[PATCH] drm/panel: simple: Fix innolux_g121i1_l01 bus_format
From: Heiko Schocher
innolux_g121i1_l01 sets bpc to 6, so use the corresponding bus format:
MEDIA_BUS_FMT_RGB666_1X7X3_SPWG.
Fixes: 4ae13e486866 ("drm/panel: simple: Add more properties to Innolux
G121I1-L01")
Signed-off-by: Heiko Schocher
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/panel/panel-simple.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index edd5a0c35437..0cb3be26e2e6 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -2255,7 +2255,7 @@ static const struct panel_desc innolux_g121i1_l01 = {
.enable = 200,
.disable = 20,
},
- .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
--
2.25.1
Re: [PATCH] drm/imx: imx-tve: Fix return type of imx_tve_connector_mode_valid
Hi Nathan, On Tue, Sep 13, 2022 at 5:55 PM Nathan Huckleberry wrote: > > The mode_valid field in drm_connector_helper_funcs is expected to be of > type: > enum drm_mode_status (* mode_valid) (struct drm_connector *connector, > struct drm_display_mode *mode); > > The mismatched return type breaks forward edge kCFI since the underlying > function definition does not match the function hook definition. > > The return type of imx_tve_connector_mode_valid should be changed from > int to enum drm_mode_status. > > Reported-by: Dan Carpenter > Link: https://github.com/ClangBuiltLinux/linux/issues/1703 > Cc: l...@lists.linux.dev > Signed-off-by: Nathan Huckleberry Reviewed-by: Fabio Estevam
Re: [PATCH v6 00/10] drm: bridge: Add Samsung MIPI DSIM bridge
Hi Jagan, On Sat, Oct 1, 2022 at 5:07 AM Jagan Teki wrote: > Repo: > https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v6 This URL returns an error. Please double-check.
Re: [PATCH v1] 2c: imx: fix typo in comment
Hi Flavio, On Fri, Jul 15, 2022 at 10:28 AM Flavio Suligoi wrote: > > to provid --> to provide There is also a typo in the Subject line: 2c ---> i2c :-)
Re: [Freedreno] [PATCH RESEND] drm/msm/adreno: Do not print error on "qcom, gpu-pwrlevels" absence
Hi Rob, On Tue, Oct 15, 2019 at 11:19 AM Jeffrey Hugo wrote: > > On Tue, Oct 15, 2019 at 7:40 AM Fabio Estevam wrote: > > > > Booting the adreno driver on a imx53 board leads to the following > > error message: > > > > adreno 3000.gpu: [drm:adreno_gpu_init] *ERROR* Could not find the GPU > > powerlevels > > > > As the "qcom,gpu-pwrlevels" property is optional and never present on > > i.MX5, turn the message into debug level instead. > > > > Signed-off-by: Fabio Estevam > > Seems reasonable. Reviewed-by: Jeffrey Hugo Any comments, please? Just wanted to get rid of this misleading error message on i.MX5. Thanks ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/mxsfb: Remove brackets for single line if block
There is no need for brackets when for a single line inside
the 'if' block, so remove the unneeded brackets.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index b69ace8bf526..bacd1f2b2fb3 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -326,11 +326,10 @@ void mxsfb_plane_atomic_update(struct mxsfb_drm_private
*mxsfb,
if (event) {
crtc->state->event = NULL;
- if (drm_crtc_vblank_get(crtc) == 0) {
+ if (drm_crtc_vblank_get(crtc) == 0)
drm_crtc_arm_vblank_event(crtc, event);
- } else {
+ else
drm_crtc_send_vblank_event(crtc, event);
- }
}
spin_unlock_irq(&crtc->dev->event_lock);
--
2.17.1
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[PATCH v2] drm/mxsfb: Remove brackets for single line if block
There is no need for brackets for a single line inside the 'if' block,
so remove the unneeded brackets.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Fix typo in commit log
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index b69ace8bf526..bacd1f2b2fb3 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -326,11 +326,10 @@ void mxsfb_plane_atomic_update(struct mxsfb_drm_private
*mxsfb,
if (event) {
crtc->state->event = NULL;
- if (drm_crtc_vblank_get(crtc) == 0) {
+ if (drm_crtc_vblank_get(crtc) == 0)
drm_crtc_arm_vblank_event(crtc, event);
- } else {
+ else
drm_crtc_send_vblank_event(crtc, event);
- }
}
spin_unlock_irq(&crtc->dev->event_lock);
--
2.17.1
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Re: [Freedreno] [PATCH RESEND] drm/msm/adreno: Do not print error on "qcom, gpu-pwrlevels" absence
Hi Jordan, On Fri, Nov 1, 2019 at 11:52 AM Jordan Crouse wrote: > I'm good with this. This really should only be around for > compatibility with downstream device tree files which should mean nothing for > I.MX5. May I resend it with your Reviewed-by tag? Thanks ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH RESEND] drm/msm/adreno: Do not print error on "qcom, gpu-pwrlevels" absence
Booting the adreno driver on a imx53 board leads to the following
error message:
adreno 3000.gpu: [drm:adreno_gpu_init] *ERROR* Could not find the GPU
powerlevels
As the "qcom,gpu-pwrlevels" property is optional and never present on
i.MX5, turn the message into debug level instead.
Signed-off-by: Fabio Estevam
Reviewed-by: Jeffrey Hugo
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 0783e4b5486a..5d7bdb4c83cc 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -826,7 +826,7 @@ static int adreno_get_legacy_pwrlevels(struct device *dev)
node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
if (!node) {
- DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n");
+ DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
return -ENXIO;
}
--
2.17.1
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[PATCH RESEND] drm/msm/adreno: Do not print error on "qcom, gpu-pwrlevels" absence
Booting the adreno driver on a imx53 board leads to the following
error message:
adreno 3000.gpu: [drm:adreno_gpu_init] *ERROR* Could not find the GPU
powerlevels
As the "qcom,gpu-pwrlevels" property is optional and never present on
i.MX5, turn the message into debug level instead.
Signed-off-by: Fabio Estevam
Reviewed-by: Jeffrey Hugo
Reviewed-by: Jordan Crouse
---
Trying once again :-)
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 0783e4b5486a..5d7bdb4c83cc 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -826,7 +826,7 @@ static int adreno_get_legacy_pwrlevels(struct device *dev)
node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
if (!node) {
- DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n");
+ DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
return -ENXIO;
}
--
2.17.1
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Re: [PATCH RESEND] drm/msm/adreno: Do not print error on "qcom,gpu-pwrlevels" absence
Hi Rob,
On Tue, Dec 10, 2019 at 8:12 PM Fabio Estevam wrote:
>
> Booting the adreno driver on a imx53 board leads to the following
> error message:
>
> adreno 3000.gpu: [drm:adreno_gpu_init] *ERROR* Could not find the GPU
> powerlevels
>
> As the "qcom,gpu-pwrlevels" property is optional and never present on
> i.MX5, turn the message into debug level instead.
>
> Signed-off-by: Fabio Estevam
> Reviewed-by: Jeffrey Hugo
> Reviewed-by: Jordan Crouse
> ---
> Trying once again :-)
>
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 0783e4b5486a..5d7bdb4c83cc 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -826,7 +826,7 @@ static int adreno_get_legacy_pwrlevels(struct device *dev)
>
> node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
> if (!node) {
> - DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n");
> + DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
A gentle ping...
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Re: [PATCH] drm/msm: Use the correct dma_sync calls harder
Hi Rob,
On Wed, Sep 4, 2019 at 2:19 PM Rob Clark wrote:
>
> From: Rob Clark
>
> Looks like the dma_sync calls don't do what we want on armv7 either.
> Fixes:
>
> Unable to handle kernel paging request at virtual address 50001000
> pgd = (ptrval)
> [50001000] *pgd=
> Internal error: Oops: 805 [#1] SMP ARM
> Modules linked in:
> CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.3.0-rc6-00271-g9f159ae07f07 #4
> Hardware name: Freescale i.MX53 (Device Tree Support)
> PC is at v7_dma_clean_range+0x20/0x38
> LR is at __dma_page_cpu_to_dev+0x28/0x90
> pc : []lr : []psr: 2013
> sp : d80b5a88 ip : de96c000 fp : d840ce6c
> r10: r9 : 0001 r8 : d843e010
> r7 : r6 : 8000 r5 : ddb6c000 r4 :
> r3 : 003f r2 : 0040 r1 : 50008000 r0 : 50001000
> Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
> Control: 10c5387d Table: 70004019 DAC: 0051
> Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
>
> Signed-off-by: Rob Clark
> Fixes: 3de433c5b38a ("drm/msm: Use the correct dma_sync calls in msm_gem")
> Tested-by: Fabio Estevam
I see this one got applied in linux-next already.
Could it be sent to 5.4-rc, please?
mx53 boards cannot boot in mainline because of this.
Thanks
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Re: [PATCH] drm/msm: Use the correct dma_sync calls harder
Hi Rob, On Tue, Oct 8, 2019 at 8:08 PM Rob Clark wrote: > afaict this should be at least in v5.4-rc2.. am I missing something? You are right, it is in 5.4-rc indeed, sorry. It is 5.3.x stable that has this commit missing, but I guess it will be backported at some point. Thanks!
[PATCH RESEND] drm/msm/adreno: Do not print error on "qcom, gpu-pwrlevels" absence
Booting the adreno driver on a imx53 board leads to the following
error message:
adreno 3000.gpu: [drm:adreno_gpu_init] *ERROR* Could not find the GPU
powerlevels
As the "qcom,gpu-pwrlevels" property is optional and never present on
i.MX5, turn the message into debug level instead.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 0783e4b5486a..5d7bdb4c83cc 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -826,7 +826,7 @@ static int adreno_get_legacy_pwrlevels(struct device *dev)
node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
if (!node) {
- DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n");
+ DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
return -ENXIO;
}
--
2.17.1
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Re: [PATCH] backlight: pwm_bl: configure pwm only once per backlight toggle
On Wed, Oct 23, 2019 at 11:16 AM Adam Ford wrote: > What is the plan to address the regression for 5.4? I wasn't sure if > we're going to apply the i.mx fixes or temporarily revert the > offending patch, or something else. (or maybe nothing at all) Yes, I do see the regression on a imx53 board with 5.4-rc too and also interested on a fix. Thanks ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/bridge: adv7511: Replace hardcoded number
The hardcoded '12' means the number of elements in the
adv7511_csc_ycbcr_to_rgb[] array, so use the ARRAY_SIZE() macro
to let the code less error prone.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 9e13e466e72c..568c6d52cdda 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -132,6 +132,13 @@ static const struct regmap_config adv7511_regmap_config = {
* Hardware configuration
*/
+/* Coefficients for adv7511 color space conversion */
+static const uint16_t adv7511_csc_ycbcr_to_rgb[] = {
+ 0x0734, 0x04ad, 0x, 0x1c1b,
+ 0x1ddc, 0x04ad, 0x1f24, 0x0135,
+ 0x, 0x04ad, 0x087c, 0x1b77,
+};
+
static void adv7511_set_colormap(struct adv7511 *adv7511, bool enable,
const uint16_t *coeff,
unsigned int scaling_factor)
@@ -142,7 +149,7 @@ static void adv7511_set_colormap(struct adv7511 *adv7511,
bool enable,
ADV7511_CSC_UPDATE_MODE, ADV7511_CSC_UPDATE_MODE);
if (enable) {
- for (i = 0; i < 12; ++i) {
+ for (i = 0; i < ARRAY_SIZE(adv7511_csc_ycbcr_to_rgb); ++i) {
regmap_update_bits(adv7511->regmap,
ADV7511_REG_CSC_UPPER(i),
0x1f, coeff[i] >> 8);
@@ -193,13 +200,6 @@ static int adv7511_packet_disable(struct adv7511 *adv7511,
unsigned int packet)
return 0;
}
-/* Coefficients for adv7511 color space conversion */
-static const uint16_t adv7511_csc_ycbcr_to_rgb[] = {
- 0x0734, 0x04ad, 0x, 0x1c1b,
- 0x1ddc, 0x04ad, 0x1f24, 0x0135,
- 0x, 0x04ad, 0x087c, 0x1b77,
-};
-
static void adv7511_set_config_csc(struct adv7511 *adv7511,
struct drm_connector *connector,
bool rgb, bool hdmi_mode)
--
2.17.1
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Re: [PATCH 16/21] drm: mxsfb: Add i.MX7 to the list of supported SoCs in Kconfig
Hi Laurent, On Mon, Mar 9, 2020 at 4:53 PM Laurent Pinchart wrote: > config DRM_MXSFB > - tristate "i.MX23/i.MX28/i.MX6SX MXSFB LCD controller" > + tristate "i.MX23/i.MX28/i.MX6SX/i.MX7 MXSFB LCD controller" Can't we just make it simpler and write: tristate "i.MX eLCDIF controller" instead? Otherwise this list will get longer each time a new SoC is supported: tristate "i.MX23/i.MX28/i.MX6SX/i.MX6SL/i.MX7/i.MX7ULP/i.MX8M/i.MX8MM/i.MX8QXP/i.MX8M MXSFB LCD controller" and probably more :-) ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 31/33] drm/panel-simple: Fix dotclock for XT VL050-8048NT-C01
Hi Ville,
On Mon, Mar 2, 2020 at 5:36 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> The currently listed dotclock disagrees with the currently
> listed vrefresh rate. Change the dotclock to match the vrefresh.
>
> Someone tell me which (if either) of the dotclock or vreresh is
> correct?
>
> Cc: Fabio Estevam
> Cc: Sam Ravnborg
> Cc: Thierry Reding
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/panel/panel-simple.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c
> b/drivers/gpu/drm/panel/panel-simple.c
> index 5ce1328fd7dc..6b48c02af112 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -3368,7 +3368,7 @@ static const struct panel_desc urt_umsh_8596md_parallel
> = {
> };
>
> static const struct drm_display_mode vl050_8048nt_c01_mode = {
> - .clock = 3,
> + .clock = 34540,
I don't have access to hardware to test this change at the moment, but
looking at the panel datasheet I see that 34.54MHz is still inside the
valid range:
Reviewed-by: Fabio Estevam
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Re: [PATCH] drm/panel: simple: Add Innolux N133HSE panel support
Hi Marek, On Mon, Jan 27, 2020 at 5:16 AM Marek Vasut wrote: > > From: Sean Cross > > The Innolux N133HSE panel is a 13.3" 1920x1080 panel that contains an > integrated backlight, and connects via eDP. > > It is used in the Kosagi Novena. > > Signed-off-by: Sean Cross > Cc: Shawn Guo > Cc: Fabio Estevam The freescale.com domain is gone for quite some time. Please use nxp.com instead or feste...@gmail.com. Otherwise the patch looks good. Thanks ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 3/4] drm: imx: Add i.MX 6 MIPI DSI host driver
Hi Adrian,
On Mon, Nov 18, 2019 at 12:25 PM Adrian Ratiu
wrote:
Some nitpicks:
> +
> +config DRM_IMX_MIPI_DSI
> + tristate "Freescale i.MX DRM MIPI DSI"
This text seems too generic as there are i.MX SoCs that use different
MIPI DSI IP.
Maybe "Freescale i.MX6 DRM MIPI DSI" instead?
> +module_platform_driver(imx_mipi_dsi_driver);
> +
> +MODULE_DESCRIPTION("i.MX MIPI DSI host controller driver");
i.MX6 MIPI DSI, please.
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Adreno crash on i.MX53 running 5.3-rc6
Hi, I am getting the following crash when booting the adreno driver on i.MX53 running a 5.3-rc6 kernel. Such error does not happen with 5.2 though. Before I start running a bisect, I am wondering if anyone has any ideas about this issue. Thanks, Fabio Estevam [2.083249] 8<--- cut here --- [2.086460] Unable to handle kernel paging request at virtual address 50001000 [2.094174] pgd = (ptrval) [2.096911] [50001000] *pgd= [2.100606] Internal error: Oops: 805 [#1] SMP ARM [2.105412] Modules linked in: [2.108487] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.3.0-rc6-00271-g9f159ae07f07 #4 [2.116411] Hardware name: Freescale i.MX53 (Device Tree Support) [2.122538] PC is at v7_dma_clean_range+0x20/0x38 [2.127254] LR is at __dma_page_cpu_to_dev+0x28/0x90 [2.132226] pc : []lr : []psr: 2013 [2.138500] sp : d80b5a88 ip : de96c000 fp : d840ce6c [2.143732] r10: r9 : 0001 r8 : d843e010 [2.148964] r7 : r6 : 8000 r5 : ddb6c000 r4 : [2.155500] r3 : 003f r2 : 0040 r1 : 50008000 r0 : 50001000 [2.162037] Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none [2.169180] Control: 10c5387d Table: 70004019 DAC: 0051 [2.174934] Process swapper/0 (pid: 1, stack limit = 0x(ptrval)) [2.180949] Stack: (0xd80b5a88 to 0xd80b6000) [2.185319] 5a80: c011c7bc d8491780 d840ce6c d849b380 c011822c [2.193509] 5aa0: c0d01a18 c0118abc c0118a78 d84a0200 0008 c1308908 d838e800 d849a4a8 [2.201697] 5ac0: d8491780 c06699b4 d8491600 d80b5b20 d84a0200 [2.209886] 5ae0: d8491780 d8491600 d80b5b20 d8491600 d849a4a8 d84a0200 0003 d84a0358 [2.218077] 5b00: c1308908 d8491600 d849a4a8 d8491780 d840ce6c c066a55c c1308908 c066a104 [2.226266] 5b20: 01001000 d84a0200 10700ac6 d849a480 d84a0200 d8491600 [2.234455] 5b40: e0845000 c1308908 c066a72c d849a480 d840ce6c d840ce00 c1308908 [2.242643] 5b60: c066b584 d849a488 d849a4a8 c1308908 d840ce6c c066ff40 [2.250832] 5b80: d849a488 d849a4a8 c1308908 d81b4000 e0845000 [2.259021] 5ba0: d838e800 c1308908 d8491600 10700ac6 d80b5bc8 d840ce00 d840ce6c 0001 [2.267210] 5bc0: e0845000 d838e800 c066ece4 0100 10ff [2.275399] 5be0: c1308908 0001 d81b4000 0100 0001 10700ac6 [2.283587] 5c00: c0d6d564 d840ce00 d81b4010 0001 d81b4000 c0d6d564 c1308908 d80b5c48 [2.291777] 5c20: d838e800 c061f9cc c1029dec d80b5c48 d838e800 c13e8788 [2.299965] 5c40: c1308928 c102a234 0100 10ff [2.308154] 5c60: 0001 a013 10700ac6 c13b7658 d840ce00 d838e800 d81b4000 [2.316343] 5c80: d840ce00 c1308908 0002 d838f800 c0620514 0001 10700ac6 [2.324531] 5ca0: d8496440 d81b4010 c1aa1c00 d838e800 c061e070 [2.332720] 5cc0: c0d6c534 df56cf34 00c8 10700ac6 d81b4010 [2.340909] 5ce0: d8496440 d838e800 c103acd0 d8496280 c1380488 c06a3e10 [2.349097] 5d00: d838f800 d838e800 d843e010 d8496440 c1308908 [2.357286] 5d20: d83f9640 c1380488 c0668554 0006 0007 c13804d4 d83f9640 [2.365475] 5d40: c1380488 c017ec18 d80c c0c43e40 d843e010 d8496440 0001 c0182a94 [2.373665] 5d60: 6013 10700ac6 d843e010 d8496280 d8496400 0018 d8496440 0001 [2.381854] 5d80: c13804d4 d83f9640 c1380488 c06a4280 c1380488 c0d764f8 d8496440 [2.390044] 5da0: c1380488 d843e010 c0d764f8 c1308908 c13ef300 c06a44f0 [2.398232] 5dc0: c0d8a0dc dffcc6f0 d843e010 dffcc6f0 d843e010 c06680b8 [2.406421] 5de0: d84988c0 d83f9640 d84988c0 d84989a0 d8498230 10700ac6 0001 d843e010 [2.414610] 5e00: c137eec0 c137eec0 c13ef300 c06ac1a0 [2.422799] 5e20: d843e010 c1aa40dc c1aa40e0 c137eec0 c06aa014 d843e010 c137eec0 [2.430988] 5e40: c137eec0 c1308908 c13e9880 c13e85d4 c06aa368 c1308908 c13e9880 [2.439178] 5e60: c13e85d4 d843e010 c137eec0 c1308908 c13e9880 c13e85d4 c06aa618 [2.447367] 5e80: c137eec0 d843e010 c06aa6a4 c137eec0 c06aa620 c06a844c [2.46] 5ea0: d80888d4 d80888a4 d84914d0 10700ac6 d80888d4 c137eec0 d8494f00 c1380d28 [2.463745] 5ec0: c06a946c c105f3d4 c1308908 c137eec0 c1308908 [2.471934] 5ee0: c125fdd0 c06ab304 c1308928 c1308908 c0103178 0109 [2.480123] 5f00: dc6e dc00 c1126860 0109 0109 c014dc88 c11253ac c10607a0 [2.488312] 5f20: 0006 0006 c12adeec dc6e 10700ac6 [2.496501] 5f40: c1308f18 10700ac6 0007 c13e9880 c13ef300 c1294
Re: Adreno crash on i.MX53 running 5.3-rc6
Hi Robin, On Mon, Sep 2, 2019 at 11:45 AM Robin Murphy wrote: > Try 0036bc73ccbe - that looks like something that CONFIG_DMA_API_DEBUG > should have been screaming about anyway. Thanks for your suggestion. I can successfully boot after reverting the following commits: commit 141db5703c887f46957615cd6616ca28fe4691e0 (HEAD) Author: Fabio Estevam Date: Mon Sep 2 14:58:18 2019 -0300 Revert "drm/msm: stop abusing dma_map/unmap for cache" This reverts commit 0036bc73ccbe7e600a3468bf8e8879b122252274. commit fa5b1f620f2984c254877d6049214c39c24c8207 Author: Fabio Estevam Date: Mon Sep 2 14:56:01 2019 -0300 Revert "drm/msm: Use the correct dma_sync calls in msm_gem" This reverts commit 3de433c5b38af49a5fc7602721e2ab5d39f1e69c. Rob, What would be the recommended approach for fixing this? Thanks ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Adreno crash on i.MX53 running 5.3-rc6
Hi Jonathan, On Tue, Sep 3, 2019 at 4:25 PM Jonathan Marek wrote: > > Hi, > > I tried this and it works with patches 4+5 from Rob's series and > changing gpummu to use sg_phys(sg) instead of sg->dma_address > (dma_address isn't set now that dma_map_sg isn't used). Thanks for testing it. I haven't had a chance to test it yet. Rob, I assume your series is targeted to 5.4, correct? If this is the case, what we should do about the i.MX5 regression on 5.3? Would a revert of the two commits be acceptable in 5.3 in order to avoid the regression? Please advise. Thanks ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Adreno crash on i.MX53 running 5.3-rc6
Hi Rob, On Tue, Sep 3, 2019 at 9:12 PM Rob Clark wrote: > In the mean time, it is a bit ugly, but I guess something like this should > work: Yes, this works on a i.MX53 board, thanks: Tested-by: Fabio Estevam Is this something you could submit for 5.3? Thanks ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/msm/adreno: Do not print error on "qcom, gpu-pwrlevels" absence
Booting the adreno driver on a imx53 board leads to the following
error message:
adreno 3000.gpu: [drm:adreno_gpu_init] *ERROR* Could not find the GPU
powerlevels
As the "qcom,gpu-pwrlevels" property is optional and never present on
i.MX5, turn the message into debug level instead.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 048c8be426f3..73c79f1614c1 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -825,7 +825,7 @@ static int adreno_get_legacy_pwrlevels(struct device *dev)
node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
if (!node) {
- DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n");
+ DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
return -ENXIO;
}
--
2.17.1
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Re: [RFC PATCH 2/9] drm: bridge: Add Samsung SEC MIPI DSIM bridge driver
Hi Jagan/Laurent, On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart wrote: > Looking at the register set, it seems to match the Exynos 5433, > supported by drivers/gpu/drm/exynos/exynos_drm_dsi.c. Can we leverage > that driver instead of adding a new one for the same IP core ? Yes. there was an attempt from Michael in this direction: https://patchwork.kernel.org/project/dri-devel/cover/20200911135413.3654800-1-m.tret...@pengutronix.de/ Cheers
Re: [RFC PATCH 2/9] drm: bridge: Add Samsung SEC MIPI DSIM bridge driver
Hi Jagan, On Thu, Jun 24, 2021 at 9:32 AM Jagan Teki wrote: > > I had a brief look at the exynos driver, and I think it should be turned > > into a DRM bridge as part of this rework to be used with the i.MX8MM. > > > > Is there someone from Samsung who could assist, at least to test the > > changes ? > > I have hardware to verify it on i.MX8MM but from exynos I don't have > any contact from Samsung to suggest or test. Maybe I can add Tomasz > Figa while sending the changes? Adding Inki Dae and Marek Szyprowski from Samsung who helped to review Michael's series. > I understand that there are 2 key implementations. > > 1. Adjust the exynos_drm_dsi.c by dropping component_ops as i.MX8MM > flow with LCDIF doesn't have component_ops (make sure it works with > exynos platform first) > 2. Sec DSIM Bridge driver common cross Exynos and i.MX8MM platform > drivers or only one Sec DSIM bridge driver to handle both the > platforms by differentiating compatible and driver data > > Any more suggestions would be appreciated? > > Jagan.
Re: [PATCH v12 00/18] drm: Add Samsung MIPI DSIM bridge
Hi Rasmus, On Tue, Feb 14, 2023 at 7:55 AM Rasmus Villemoes wrote: > Well, the data sheet for the dsi86 says up to 750MHz DSI HS clock, and > if the value specified in samsung,burst-clock-frequency is twice the DSI > HS clk, I suppose I should be good up to 1.5GHz? I have tried many > different values, but I never seem to get anything through; I think I'm > missing some piece. > > So now I've tried to use these patches on the imx8mp-evk with the > mipi->hdmi accessory from NXP, just to see if I can ever get any > graphics through the mipi interface. And there the story is the same: > the adv7535 bridge gets probed, and can read out the edid from the > monitor over hdmi. And while the mipi block and the bridge seem to > attach to each other, I still don't get any output. > > Do any of you happen to have this working on the imx8mp-evk, and if so, > can you share the .dts updates you've done and how exactly you test the > graphics? I don't have access to an imx8mp-evk, but I tested the ADV7535 MIPI to HDMI daughter card on an imx8mm-evk. Some extra ADV7535 patches were needed. Please check patches 0020-0023 and see if they help.
Re: [PATCH v12 00/18] drm: Add Samsung MIPI DSIM bridge
On Tue, Feb 14, 2023 at 8:09 AM Fabio Estevam wrote: > Some extra ADV7535 patches were needed. Please check patches 0020-0023 > and see if they help. Sorry, forgot to put the repo URL: https://github.com/fabioestevam/meta-imx8mmevk-bsp/tree/kirkstone/recipes-kernel/linux/linux-stable/6.1/imx8mmevk
Re: [PATCH] drm/msm: fix PM_DEVFREQ kconfig dependency warning
On Tue, Mar 7, 2023 at 2:46 PM Randy Dunlap wrote:
>
> Since DEVFREQ_GOV_SIMPLE_ONDEMAND depends on PM_DEVFREQ, the latter
> should either be selected or DRM_MSM should depend on PM_DEVFREQ.
> Since most drivers select PM_DEVFREQ instead of depending on it,
> add a select here to satisfy kconfig.
>
> WARNING: unmet direct dependencies detected for DEVFREQ_GOV_SIMPLE_ONDEMAND
> Depends on [n]: PM_DEVFREQ [=n]
> Selected by [y]:
> - DRM_MSM [=y] && HAS_IOMEM [=y] && DRM [=y] && (ARCH_QCOM || SOC_IMX5 ||
> COMPILE_TEST [=y]) && COMMON_CLK [=y] && IOMMU_SUPPORT [=y] && (QCOM_OCMEM
> [=n] || QCOM_OCMEM [=n]=n) && (QCOM_LLCC [=n] || QCOM_LLCC [=n]=n) &&
> (QCOM_COMMAND_DB [=y] || QCOM_COMMAND_DB [=y]=n)
>
> Fixes: 6563f60f14cb ("drm/msm/gpu: Add devfreq tuning debugfs")
> Signed-off-by: Randy Dunlap
> Reported-by: kernel test robot
> Link: lore.kernel.org/r/202303071922.wjqdwqpe-...@intel.com
> Cc: Rob Clark
> Cc: Paul Gazzillo
> Cc: Necip Fazil Yildiran
> Cc: Chia-I Wu
> Cc: Abhinav Kumar
> Cc: Dmitry Baryshkov
> Cc: linux-arm-...@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: freedr...@lists.freedesktop.org
This fixes the warning after running 'make imx_v6_v7_defconfig', thanks:
Tested-by: Fabio Estevam
Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge
Hi Jagan, On Thu, Jan 5, 2023 at 7:24 AM Jagan Teki wrote: > Does anyone have any other comments on this? I would like to send v11 > with a few nits on v10. Please let me know. What is blocking this series to be applied?
Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge
Hi Jagan, On Thu, Jan 19, 2023 at 2:59 PM Jagan Teki wrote: > There are two patch series prior to this need to apply. > > https://patchwork.kernel.org/project/dri-devel/patch/20221212145745.15387-1-ja...@amarulasolutions.com/ > https://patchwork.kernel.org/project/dri-devel/cover/20221212182923.29155-1-ja...@amarulasolutions.com/ Would it make sense to re-submit these two patches as part of your series?
Re: [PATCH v2 1/2] drivers: gpu: drm: add driver for samsung s6e3fc2x01 cmd mode panel
Hi Nia,
On Fri, Oct 7, 2022 at 8:16 AM Nia Espera wrote:
> +static int samsung_s6e3fc2x01_prepare(struct drm_panel *panel)
> +{
> + struct samsung_s6e3fc2x01 *ctx = to_samsung_s6e3fc2x01(panel);
> + struct device *dev = &ctx->dsi->dev;
> + int ret;
> +
> + if (ctx->prepared)
> + return 0;
> +
> + ret = regulator_enable(ctx->supply);
> + if (ret < 0) {
> + dev_err(dev, "Failed to enable regulator: %d\n", ret);
> + return ret;
> + }
> +
> + samsung_s6e3fc2x01_reset(ctx);
> +
> + ret = samsung_s6e3fc2x01_on(ctx);
> + if (ret < 0) {
> + dev_err(dev, "Failed to initialize panel: %d\n", ret);
> + gpiod_set_value_cansleep(ctx->reset_gpio, 1);
You should also call regulator_disable() here in the case of failure.
> +static int samsung_s6e3fc2x01_unprepare(struct drm_panel *panel)
> +{
> + struct samsung_s6e3fc2x01 *ctx = to_samsung_s6e3fc2x01(panel);
> + struct device *dev = &ctx->dsi->dev;
> + int ret;
> +
> + if (!ctx->prepared)
> + return 0;
> +
> + ret = samsung_s6e3fc2x01_off(ctx);
> + if (ret < 0)
> + dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
> +
> + gpiod_set_value_cansleep(ctx->reset_gpio, 1);
regulator_disable() should be called here as well.
Re: [PATCH v2 2/4] usb: gadget: hid: Convert to use list_count()
On Mon, Nov 14, 2022 at 1:22 PM Andy Shevchenko wrote: > > The list API now provides the list_count() to help with counting > existing nodes in the list. Uilise it. s/Uilise/Utilise
Re: [PATCH v4 01/10] drm: bridge: cadence: convert mailbox functions to macro functions
Hi Sandor, On Mon, Nov 21, 2022 at 4:27 AM Sandor Yu wrote: > > Mailbox access functions could be share to other mhdp driver and > HDP-TX HDMI/DP PHY drivers, move those functions to head file > include/drm/bridge/cdns-mhdp-mailbox.h and convert them to > macro functions. What is the reason for converting the functions to macro?
Re: [PATCH v7 00/10] drm: bridge: Add Samsung MIPI DSIM bridge
Hi, On Mon, Nov 7, 2022 at 1:34 PM Frieder Schrempf wrote: > I tested this on the Kontron DL i.MX8MM which uses a TI SN65DSI84 bridge > and a Jenson 7" LVDS Display. > > Thanks for your work, Jagan! > > Tested-by: Frieder Schrempf # Kontron DL > i.MX8MM As this series has been successfully tested on multiple devices, is it possible to apply it so people can make further adjustments? Thanks
Re: [PATCH] drm/etnaviv: Remove redundant dev_err()
On Sun, Dec 11, 2022 at 3:02 PM Kang Minchul wrote:
>
> Function dev_err() is redundant because platform_get_irq()
> already prints an error.
>
> Signed-off-by: Kang Minchul
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> index a31eeff2b297..097fa9034ee8 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> @@ -1771,7 +1771,6 @@ static int etnaviv_gpu_platform_probe(struct
> platform_device *pdev)
> /* Get Interrupt: */
> gpu->irq = platform_get_irq(pdev, 0);
> if (gpu->irq < 0) {
> - dev_err(dev, "failed to get irq: %d\n", gpu->irq);
> return gpu->irq;
> }
If the dev_err() line is removed, then the { and } should be removed as well.
Re: [PATCH v9 10/18] drm: bridge: samsung-dsim: Init exynos host for first DSI transfer
Hi Jagan, On Tue, Dec 13, 2022 at 7:40 AM Jagan Teki wrote: > https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v10 Please preserve the authorship of the patches. This one is from Marek Vasut: https://gitlab.com/openedev/kernel/-/commit/e244fa552402caebcf48cd6710fd387429f7f680 but in your tree, it appears as if you were the original author. Please double-check globally.
Driver for CFAF240320X0-020T display
Hi, Does anyone know if the Crystalfontz CFAF240320X0-020T display is supported in Linux? https://www.crystalfontz.com/product/cfaf240320x0020t-2inch-240x320-color-tft It uses a Sitronix ST7789V controller. For the ST7789V, there is a drm driver: drivers/gpu/drm/panel/panel-sitronix-st7789v.c and also an fbtft one: drivers/staging/fbtft/fb_st7789v.c Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml shows a remote-endpoint property, so I assume this only works when st7789v is connected via RGB parallel, correct? On my board, the CFAF240320X0-020T is connected via SPI only, so I guess I should try the fbtdt driver? The arch/riscv/boot/dts/canaan/sipeed_maix_* boards use compatible = "sitronix,st7789v" Do these boards have st7789v functional? Are they using the fbtft or drm driver? Appreciate any suggestions. Thanks, Fabio Estevam
Re: [PATCH] drm/msm/a2xx: support loading legacy (iMX) firmware
Hi Dmitry, On Sun, Jan 1, 2023 at 12:58 PM Dmitry Baryshkov wrote: > > Support loading A200 firmware generated from the iMX firmware header > files. The firmware lacks protection support, however it allows GPU to > function properly while using the firmware files with clear license > which allows redistribution. Could you please share more details as to what firmware you are using with the i.MX53? Is it available on the linux-firmare repository? Please advise.
Re: Driver for CFAF240320X0-020T display
Hi Noralf, On Fri, Dec 16, 2022 at 9:30 AM Noralf Trønnes wrote: > There is a DRM driver that can be used with all of these controllers: > drivers/gpu/drm/tiny/panel-mipi-dbi.c. It uses a firmware file for the > init commands. > > Binding: > Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml > Wiki: https://github.com/notro/panel-mipi-dbi/wiki Thanks for your suggestion. I was able to get the CFAF240320X0-020T display to work with the panel-mipi-dbi.c driver. You did a great job on this driver and wiki! Cheers
Re: [PATCH v10 00/18] drm: Add Samsung MIPI DSIM bridge
On Fri, Jan 6, 2023 at 11:34 AM Adam Ford wrote: > I got it working on an LVDS display that I have, but I didn't get it > working on the HDMI bridge. Since we have a few tested-by people, > it'd be nice to see this integrated so we can work on ading more > functionality Agreed. Hopefully, this series can be applied soon so we don't miss another cycle.
[PATCH v2 1/2] dt-bindings: display: bridge: ldb: Add i.MX6SX support
From: Fabio Estevam i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout with i.MX8MP and i.MX93. Signed-off-by: Fabio Estevam --- Changes since v1: - Do not duplicate the entire if. (Krzysztof) .../devicetree/bindings/display/bridge/fsl,ldb.yaml | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml index 6e0e3ba9b49e..07388bf2b90d 100644 --- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml +++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: enum: + - fsl,imx6sx-ldb - fsl,imx8mp-ldb - fsl,imx93-ldb @@ -64,7 +65,9 @@ allOf: properties: compatible: contains: -const: fsl,imx93-ldb +enum: + - fsl,imx6sx-ldb + - fsl,imx93-ldb then: properties: ports: -- 2.34.1
[PATCH v2 2/2] drm/bridge: fsl-ldb: Add i.MX6SX support
From: Fabio Estevam
i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout
with i.MX8MP and i.MX93.
There is no LVDS CTRL register on the i.MX6SX, so only write to
this register on the appropriate SoCs.
Add support for the i.MX6SX LDB.
Tested on a imx6sx-sdb board with a Hannstar HSD100PXN1 LVDS panel
and also on a custom i.MX6SX-based board.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- None
drivers/gpu/drm/bridge/fsl-ldb.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index 450b352914f4..f8e5d8ab98e3 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -56,6 +56,7 @@
#define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)
enum fsl_ldb_devtype {
+ IMX6SX_LDB,
IMX8MP_LDB,
IMX93_LDB,
};
@@ -64,9 +65,14 @@ struct fsl_ldb_devdata {
u32 ldb_ctrl;
u32 lvds_ctrl;
bool lvds_en_bit;
+ bool not_lvds_ctrl;
};
static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
+ [IMX6SX_LDB] = {
+ .ldb_ctrl = 0x18,
+ .not_lvds_ctrl = true,
+ },
[IMX8MP_LDB] = {
.ldb_ctrl = 0x5c,
.lvds_ctrl = 0x128,
@@ -202,6 +208,9 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg);
+ if (fsl_ldb->devdata->not_lvds_ctrl)
+ return;
+
/* Program LVDS_CTRL */
reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
@@ -228,7 +237,8 @@ static void fsl_ldb_atomic_disable(struct drm_bridge
*bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl,
LVDS_CTRL_LVDS_EN);
else
- regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
+ if (!fsl_ldb->devdata->not_lvds_ctrl)
+ regmap_write(fsl_ldb->regmap,
fsl_ldb->devdata->lvds_ctrl, 0);
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0);
clk_disable_unprepare(fsl_ldb->clk);
@@ -355,6 +365,8 @@ static void fsl_ldb_remove(struct platform_device *pdev)
}
static const struct of_device_id fsl_ldb_match[] = {
+ { .compatible = "fsl,imx6sx-ldb",
+ .data = &fsl_ldb_devdata[IMX6SX_LDB], },
{ .compatible = "fsl,imx8mp-ldb",
.data = &fsl_ldb_devdata[IMX8MP_LDB], },
{ .compatible = "fsl,imx93-ldb",
--
2.34.1
Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'
Hi Jagan, On Thu, Mar 30, 2023 at 4:55 AM Jagan Teki wrote: > I have a previous iteration of this conversion. Can I resend it on top > of drm-misc-next? > https://lore.kernel.org/all/20210704090230.26489-9-ja...@amarulasolutions.com/ I tried applying your patch against linux-next, but I get the following error: $ make dt_binding_check DT_SCHEMA_FILES=samsung,mipi-dsim.yaml LINTDocumentation/devicetree/bindings CHKDT Documentation/devicetree/bindings/processed-schema.json /home/fabio/linux-next/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml: properties:samsung,power-domain:maxItems: False schema does not allow 1 hint: Scalar properties should not have array keywords from schema $id: http://devicetree.org/meta-schemas/keywords.yaml# DTEX Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dts DTC_CHK Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dtb Could you please take a look? Thanks
[PATCH] dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to yaml
From: Jagan Teki Samsung MIPI DSIM bridge can be found on Exynos and NXP's i.MX8M Mini and Nano SoC's. Convert exynos_dsim.txt to yaml. Used the example node from latest Exynos SoC instead of the one used in legacy exynos_dsim.txt. Signed-off-by: Jagan Teki Signed-off-by: Fabio Estevam --- .../display/bridge/samsung,mipi-dsim.yaml | 275 ++ .../bindings/display/exynos/exynos_dsim.txt | 92 -- 2 files changed, 275 insertions(+), 92 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml delete mode 100644 Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml new file mode 100644 index ..c131bd879caf --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -0,0 +1,275 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung MIPI DSIM bridge controller + +maintainers: + - Inki Dae + - Jagan Teki + +description: | + Samsung MIPI DSIM bridge controller can be found it on Exynos + and i.MX8M Mini and Nano SoC's. + +properties: + compatible: +enum: + - samsung,exynos3250-mipi-dsi + - samsung,exynos4210-mipi-dsi + - samsung,exynos5410-mipi-dsi + - samsung,exynos5422-mipi-dsi + - samsung,exynos5433-mipi-dsi + - fsl,imx8mm-mipi-dsim + - fsl,imx8mp-mipi-dsim + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + '#address-cells': +const: 1 + + '#size-cells': +const: 0 + + clocks: +minItems: 2 +maxItems: 5 + + clock-names: +minItems: 2 +maxItems: 5 + + phys: +maxItems: 1 +description: phandle to the phy module representing the DPHY + + phy-names: +items: + - const: dsim + + samsung,phy-type: +$ref: /schemas/types.yaml#/definitions/uint32 +description: phandle to the samsung phy-type + + power-domains: +description: phandle to the associated power domain +maxItems: 1 + + samsung,power-domain: +$ref: /schemas/types.yaml#/definitions/phandle +description: phandle to the associated samsung power domain + + vddcore-supply: +description: MIPI DSIM Core voltage supply (e.g. 1.1V) + + vddio-supply: +description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) + + samsung,burst-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM high speed burst mode frequency. + + samsung,esc-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM escape mode frequency. + + samsung,pll-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM oscillator clock frequency. + + ports: +$ref: /schemas/graph.yaml#/properties/ports + +properties: + port@0: +$ref: /schemas/graph.yaml#/$defs/port-base +description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. +properties: + endpoint@0: +$ref: /schemas/graph.yaml#/properties/endpoint +description: sub-node describing the input from MIC + +unevaluatedProperties: false + + port@1: +$ref: /schemas/graph.yaml#/properties/port +description: + DSI output port node to the panel or the next bridge + in the chain + +required: + - '#address-cells' + - '#size-cells' + - clock-names + - clocks + - compatible + - interrupts + - phy-names + - phys + - reg + - samsung,burst-clock-frequency + - samsung,esc-clock-frequency + - samsung,pll-clock-frequency + +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: samsung,exynos5433-mipi-dsi + +then: + properties: +clocks: + minItems: 5 + +clock-names: + items: +- const: bus_clk +- const: phyclk_mipidphy0_bitclkdiv8 +- const: phyclk_mipidphy0_rxclkesc0 +- const: sclk_rgb_vclk_to_dsim0 +- const: sclk_mipi + +ports: + required: +- port@0 + + required: +- ports +- vddcore-supply +- vddio-supply + + - if: + properties: +compatible: + contains: +const: samsung,exynos5410-mipi-dsi + +then: + properties: +clocks: + minItems: 2 + +clock-names: + items: +- const: bus_clk +- const: pll_clk + + required: +- vddcore-supp
[PATCH v2] dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to yaml
From: Jagan Teki Samsung MIPI DSIM bridge can be found on Exynos and NXP's i.MX8M Mini/Nano/Plus SoCs. Convert exynos_dsim.txt to yaml. Used the example node from latest Exynos SoC instead of the one used in legacy exynos_dsim.txt. Signed-off-by: Jagan Teki Signed-off-by: Fabio Estevam --- Changes since v1: - Added samsung,mipi-dsim.yaml entry to MAINTAINERS file (Jagan) - Added Marek Szyprowski entry to the samsung,mipi-dsim.yaml maintainers section (Jagan) - Mention that i.MX8M Plus is also supported (Marek) - Remove endpoint@0 description as it only has one endpoint (Marek) .../display/bridge/samsung,mipi-dsim.yaml | 271 ++ .../bindings/display/exynos/exynos_dsim.txt | 92 -- MAINTAINERS | 1 + 3 files changed, 272 insertions(+), 92 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml delete mode 100644 Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml new file mode 100644 index ..2698752dc6ed --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -0,0 +1,271 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung MIPI DSIM bridge controller + +maintainers: + - Inki Dae + - Jagan Teki + +description: | + Samsung MIPI DSIM bridge controller can be found it on Exynos + and i.MX8M Mini/Nano/Plus SoC's. + +properties: + compatible: +enum: + - samsung,exynos3250-mipi-dsi + - samsung,exynos4210-mipi-dsi + - samsung,exynos5410-mipi-dsi + - samsung,exynos5422-mipi-dsi + - samsung,exynos5433-mipi-dsi + - fsl,imx8mm-mipi-dsim + - fsl,imx8mp-mipi-dsim + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + '#address-cells': +const: 1 + + '#size-cells': +const: 0 + + clocks: +minItems: 2 +maxItems: 5 + + clock-names: +minItems: 2 +maxItems: 5 + + phys: +maxItems: 1 +description: phandle to the phy module representing the DPHY + + phy-names: +items: + - const: dsim + + samsung,phy-type: +$ref: /schemas/types.yaml#/definitions/uint32 +description: phandle to the samsung phy-type + + power-domains: +description: phandle to the associated power domain +maxItems: 1 + + samsung,power-domain: +$ref: /schemas/types.yaml#/definitions/phandle +description: phandle to the associated samsung power domain + + vddcore-supply: +description: MIPI DSIM Core voltage supply (e.g. 1.1V) + + vddio-supply: +description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) + + samsung,burst-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM high speed burst mode frequency. + + samsung,esc-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM escape mode frequency. + + samsung,pll-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM oscillator clock frequency. + + ports: +$ref: /schemas/graph.yaml#/properties/ports + +properties: + port@0: +$ref: /schemas/graph.yaml#/$defs/port-base +description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. + +unevaluatedProperties: false + + port@1: +$ref: /schemas/graph.yaml#/properties/port +description: + DSI output port node to the panel or the next bridge + in the chain + +required: + - '#address-cells' + - '#size-cells' + - clock-names + - clocks + - compatible + - interrupts + - phy-names + - phys + - reg + - samsung,burst-clock-frequency + - samsung,esc-clock-frequency + - samsung,pll-clock-frequency + +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: samsung,exynos5433-mipi-dsi + +then: + properties: +clocks: + minItems: 5 + +clock-names: + items: +- const: bus_clk +- const: phyclk_mipidphy0_bitclkdiv8 +- const: phyclk_mipidphy0_rxclkesc0 +- const: sclk_rgb_vclk_to_dsim0 +- const: sclk_mipi + +ports: + required: +- port@0 + + required: +- ports +- vddcore-supply +- vddio-supply + + - if: + properties: +compatible: + contains: +const: samsung,exynos5410-mipi-dsi + +then: + properties: +
Re: [PATCH v2] dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to yaml
Hi Krzysztof, On 03/04/2023 09:49, Krzysztof Kozlowski wrote: Signed-off-by: Jagan Teki Signed-off-by: Fabio Estevam --- Changes since v1: - Added samsung,mipi-dsim.yaml entry to MAINTAINERS file (Jagan) - Added Marek Szyprowski entry to the samsung,mipi-dsim.yaml maintainers section (Jagan) - Mention that i.MX8M Plus is also supported (Marek) - Remove endpoint@0 description as it only has one endpoint (Marek) Where is the changelog from original submission? How your v1 differs form it? Or did you just ignore all the feedback? I'm sorry, but it was not my intention to ignore any feedback. Which feedback are you referring to specifically? Some more context: last week I sent a patch adding a new property for exynos_dsim.txt and you asked me to convert it to yaml first: https://lore.kernel.org/all/ff66c8b9-c7f7-1eb2-c730-4812b7ff6...@linaro.org/#t Jagan pointed out an earlier submission he did in 2021: https://lore.kernel.org/all/20210704090230.26489-9-ja...@amarulasolutions.com/ That was my starting point. + phys: +maxItems: 1 +description: phandle to the phy module representing the DPHY OK, so you did ignore the feedback. Not intentionally. NAK, go through the feedback and implement it. Just found this feedback from Rob about Jagan's initial submission: https://lore.kernel.org/all/20210712151322.ga1931...@robh.at.kernel.org/ I can send a new version that takes Rob's feedback into account. Were there any further versions/feedback that were submitted? Can't find them on lore. In another reply, you mention that this should be v13. I could not find previous versions of the yaml submission. Please advise. Thanks, Fabio Estevam
[PATCH v3] dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to yaml
From: Jagan Teki Samsung MIPI DSIM bridge can be found on Exynos and NXP's i.MX8M Mini/Nano/Plus SoCs. Convert exynos_dsim.txt to yaml. Used the example node from exynos5433.dtsi instead of the one used in the legacy exynos_dsim.txt. Signed-off-by: Jagan Teki Signed-off-by: Fabio Estevam --- Changes since v2: - Took previous Rob Herring's feedback into account: https://lore.kernel.org/all/20210712151322.ga1931...@robh.at.kernel.org/ - Handled imx8mn and imx8mp - Remove unnecessary #address-cells/size-cells. .../display/bridge/samsung,mipi-dsim.yaml | 255 ++ .../bindings/display/exynos/exynos_dsim.txt | 92 --- MAINTAINERS | 1 + 3 files changed, 256 insertions(+), 92 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml delete mode 100644 Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml new file mode 100644 index ..55dbec178ea8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -0,0 +1,255 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung MIPI DSIM bridge controller + +maintainers: + - Inki Dae + - Jagan Teki + - Marek Szyprowski + +description: | + Samsung MIPI DSIM bridge controller can be found it on Exynos + and i.MX8M Mini/Nano/Plus SoC's. + +properties: + compatible: +oneOf: + - enum: + - samsung,exynos3250-mipi-dsi + - samsung,exynos4210-mipi-dsi + - samsung,exynos5410-mipi-dsi + - samsung,exynos5422-mipi-dsi + - samsung,exynos5433-mipi-dsi + - fsl,imx8mm-mipi-dsim + - fsl,imx8mp-mipi-dsim + - items: + - const: fsl,imx8mn-mipi-dsim + - const: fsl,imx8mm-mipi-dsim + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + '#address-cells': +const: 1 + + '#size-cells': +const: 0 + + clocks: +minItems: 2 +maxItems: 5 + + clock-names: +minItems: 2 +maxItems: 5 + + samsung,phy-type: +$ref: /schemas/types.yaml#/definitions/uint32 +description: phandle to the samsung phy-type + + power-domains: +maxItems: 1 + + samsung,power-domain: +$ref: /schemas/types.yaml#/definitions/phandle +description: phandle to the associated samsung power domain + + vddcore-supply: +description: MIPI DSIM Core voltage supply (e.g. 1.1V) + + vddio-supply: +description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) + + samsung,burst-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM high speed burst mode frequency. + + samsung,esc-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM escape mode frequency. + + samsung,pll-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM oscillator clock frequency. + + phys: +maxItems: 1 + + phy-names: +const: dsim + + ports: +$ref: /schemas/graph.yaml#/properties/ports + +properties: + port@0: +$ref: /schemas/graph.yaml#/properties/port +description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. + + port@1: +$ref: /schemas/graph.yaml#/properties/port +description: + DSI output port node to the panel or the next bridge + in the chain + +required: + - clock-names + - clocks + - compatible + - interrupts + - reg + - samsung,burst-clock-frequency + - samsung,esc-clock-frequency + - samsung,pll-clock-frequency + +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: samsung,exynos5433-mipi-dsi + +then: + properties: +clocks: + minItems: 5 + +clock-names: + items: +- const: bus_clk +- const: phyclk_mipidphy0_bitclkdiv8 +- const: phyclk_mipidphy0_rxclkesc0 +- const: sclk_rgb_vclk_to_dsim0 +- const: sclk_mipi + +ports: + required: +- port@0 + + required: +- ports +- vddcore-supply +- vddio-supply + + - if: + properties: +compatible: + contains: +const: samsung,exynos5410-mipi-dsi + +then: + properties: +clocks: + minItems: 2 + +clock-names: + items: +- const: bus_clk +- const: pll_clk + + required: +- vdd
[PATCH v3 1/2] dt-bindings: display: bridge: ldb: Add an i.MX6SX entry
From: Fabio Estevam i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout with i.MX8MP and i.MX93. Signed-off-by: Fabio Estevam Reviewed-by: Krzysztof Kozlowski Reviewed-by: Marek Vasut --- Changes since v2: - Collected Reviewed-by tags. - Improved the Subject by not stating support. (Marek). Changes since v1: - Do not duplicate the entire if. (Krzysztof) .../devicetree/bindings/display/bridge/fsl,ldb.yaml | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml index 6e0e3ba9b49e..07388bf2b90d 100644 --- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml +++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: enum: + - fsl,imx6sx-ldb - fsl,imx8mp-ldb - fsl,imx93-ldb @@ -64,7 +65,9 @@ allOf: properties: compatible: contains: -const: fsl,imx93-ldb +enum: + - fsl,imx6sx-ldb + - fsl,imx93-ldb then: properties: ports: -- 2.34.1
[PATCH v3 2/2] drm/bridge: fsl-ldb: Add i.MX6SX support
From: Fabio Estevam
i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout
with i.MX8MP and i.MX93.
There is no LVDS CTRL register on the i.MX6SX, so only write to
this register on the appropriate SoCs.
Add support for the i.MX6SX LDB.
Tested on a imx6sx-sdb board with a Hannstar HSD100PXN1 LVDS panel
and also on a custom i.MX6SX-based board.
Signed-off-by: Fabio Estevam
Reviewed-by: Neil Armstrong
Reviewed-by: Marek Vasut
---
Changes since v2:
- Rename it to 'single_ctrl_reg' to make it clearer that on i.MX6X, there
is a single ctrl register. On the newer SoCs there are two ctrl registers.
Changes since v1:
- None
drivers/gpu/drm/bridge/fsl-ldb.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index 450b352914f4..f8e5d8ab98e3 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -56,6 +56,7 @@
#define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)
enum fsl_ldb_devtype {
+ IMX6SX_LDB,
IMX8MP_LDB,
IMX93_LDB,
};
@@ -64,9 +65,14 @@ struct fsl_ldb_devdata {
u32 ldb_ctrl;
u32 lvds_ctrl;
bool lvds_en_bit;
+ bool single_ctrl_reg;
};
static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
+ [IMX6SX_LDB] = {
+ .ldb_ctrl = 0x18,
+ .single_ctrl_reg = true,
+ },
[IMX8MP_LDB] = {
.ldb_ctrl = 0x5c,
.lvds_ctrl = 0x128,
@@ -202,6 +208,9 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg);
+ if (fsl_ldb->devdata->single_ctrl_reg)
+ return;
+
/* Program LVDS_CTRL */
reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
@@ -228,7 +237,8 @@ static void fsl_ldb_atomic_disable(struct drm_bridge
*bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl,
LVDS_CTRL_LVDS_EN);
else
- regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
+ if (!fsl_ldb->devdata->single_ctrl_reg)
+ regmap_write(fsl_ldb->regmap,
fsl_ldb->devdata->lvds_ctrl, 0);
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0);
clk_disable_unprepare(fsl_ldb->clk);
@@ -355,6 +365,8 @@ static void fsl_ldb_remove(struct platform_device *pdev)
}
static const struct of_device_id fsl_ldb_match[] = {
+ { .compatible = "fsl,imx6sx-ldb",
+ .data = &fsl_ldb_devdata[IMX6SX_LDB], },
{ .compatible = "fsl,imx8mp-ldb",
.data = &fsl_ldb_devdata[IMX8MP_LDB], },
{ .compatible = "fsl,imx93-ldb",
--
2.34.1
[PATCH v3] dt-bindings: bridge: Convert Samsung MIPI DSIM bridge to yaml
From: Jagan Teki Samsung MIPI DSIM bridge can be found on Exynos and NXP's i.MX8M Mini/Nano/Plus SoCs. Convert exynos_dsim.txt to yaml. Used the example node from exynos5433.dtsi instead of the one used in the legacy exynos_dsim.txt. Signed-off-by: Jagan Teki Signed-off-by: Fabio Estevam --- Changes since v2: - Took previous Rob Herring's feedback into account: https://lore.kernel.org/all/20210712151322.ga1931...@robh.at.kernel.org/ - Handled imx8mn and imx8mp. - Remove unnecessary #address-cells/size-cells. .../display/bridge/samsung,mipi-dsim.yaml | 255 ++ .../bindings/display/exynos/exynos_dsim.txt | 92 --- MAINTAINERS | 1 + 3 files changed, 256 insertions(+), 92 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml delete mode 100644 Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml new file mode 100644 index ..55dbec178ea8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -0,0 +1,255 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung MIPI DSIM bridge controller + +maintainers: + - Inki Dae + - Jagan Teki + - Marek Szyprowski + +description: | + Samsung MIPI DSIM bridge controller can be found it on Exynos + and i.MX8M Mini/Nano/Plus SoC's. + +properties: + compatible: +oneOf: + - enum: + - samsung,exynos3250-mipi-dsi + - samsung,exynos4210-mipi-dsi + - samsung,exynos5410-mipi-dsi + - samsung,exynos5422-mipi-dsi + - samsung,exynos5433-mipi-dsi + - fsl,imx8mm-mipi-dsim + - fsl,imx8mp-mipi-dsim + - items: + - const: fsl,imx8mn-mipi-dsim + - const: fsl,imx8mm-mipi-dsim + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + '#address-cells': +const: 1 + + '#size-cells': +const: 0 + + clocks: +minItems: 2 +maxItems: 5 + + clock-names: +minItems: 2 +maxItems: 5 + + samsung,phy-type: +$ref: /schemas/types.yaml#/definitions/uint32 +description: phandle to the samsung phy-type + + power-domains: +maxItems: 1 + + samsung,power-domain: +$ref: /schemas/types.yaml#/definitions/phandle +description: phandle to the associated samsung power domain + + vddcore-supply: +description: MIPI DSIM Core voltage supply (e.g. 1.1V) + + vddio-supply: +description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) + + samsung,burst-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM high speed burst mode frequency. + + samsung,esc-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM escape mode frequency. + + samsung,pll-clock-frequency: +$ref: /schemas/types.yaml#/definitions/uint32 +description: + DSIM oscillator clock frequency. + + phys: +maxItems: 1 + + phy-names: +const: dsim + + ports: +$ref: /schemas/graph.yaml#/properties/ports + +properties: + port@0: +$ref: /schemas/graph.yaml#/properties/port +description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. + + port@1: +$ref: /schemas/graph.yaml#/properties/port +description: + DSI output port node to the panel or the next bridge + in the chain. + +required: + - clock-names + - clocks + - compatible + - interrupts + - reg + - samsung,burst-clock-frequency + - samsung,esc-clock-frequency + - samsung,pll-clock-frequency + +allOf: + - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: samsung,exynos5433-mipi-dsi + +then: + properties: +clocks: + minItems: 5 + +clock-names: + items: +- const: bus_clk +- const: phyclk_mipidphy0_bitclkdiv8 +- const: phyclk_mipidphy0_rxclkesc0 +- const: sclk_rgb_vclk_to_dsim0 +- const: sclk_mipi + +ports: + required: +- port@0 + + required: +- ports +- vddcore-supply +- vddio-supply + + - if: + properties: +compatible: + contains: +const: samsung,exynos5410-mipi-dsi + +then: + properties: +clocks: + minItems: 2 + +clock-names: + items: +- const: bus_clk +- const: pll_clk + + required: +
[PATCH v2 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'
From: Fabio Estevam The Samsung DSIM IP block allows the inversion of the clock and data lanes. Add an optional property called 'lane-polarities' that describes the polarities of the MIPI DSI clock and data lanes. This property is useful for properly describing the hardware when the board designer decided to switch the polarities of the MIPI DSI clock and/or data lanes. Signed-off-by: Fabio Estevam --- Changes since v1: - Rebased against drm-misc-next that has samsung,mipi-dsim.yaml. .../display/bridge/samsung,mipi-dsim.yaml | 29 +++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml index e841659e20cd..04eb440ade72 100644 --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -105,6 +105,35 @@ properties: DSI output port node to the panel or the next bridge in the chain. +properties: + endpoint: +$ref: /schemas/graph.yaml#/$defs/endpoint-base +unevaluatedProperties: false + +properties: + data-lanes: +oneOf: + - minItems: 1 +maxItems: 4 +uniqueItems: true +items: + enum: [ 1, 2, 3, 4 ] +description: + See ../../media/video-interfaces.yaml for details. + + lane-polarities: +minItems: 1 +maxItems: 5 +items: + enum: [ 0, 1 ] +description: + See ../../media/video-interfaces.yaml for details. + The Samsung MIPI DSI IP requires that all the data lanes have + the same polarity. + +dependencies: + lane-polarities: [data-lanes] + required: - clock-names - clocks -- 2.34.1
[PATCH v2 2/2] drm: bridge: samsung-dsim: Implement support for clock/data polarity swap
From: Marek Vasut
Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.
This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.
Signed-off-by: Marek Vasut
Signed-off-by: Fabio Estevam
Reviewed-by: Jagan Teki
---
Changes since v1:
- Use 'drm: bridge: samsung-dsim:' as prefix (Jagan).
- Collected Jagan's Reviewed-by tag.
drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++-
include/drm/bridge/samsung-dsim.h | 2 ++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c
b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..5791148e2da2 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -183,6 +183,8 @@
#define DSIM_AFC_CTL(x)(((x) & 0x7) << 5)
/* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
#define DSIM_FREQ_BAND(x) ((x) << 24)
#define DSIM_PLL_ENBIT(23)
#define DSIM_PLL_P(x, offset) ((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct
samsung_dsim *dsi,
reg |= DSIM_FREQ_BAND(band);
}
+ if (dsi->swap_dn_dp_clk)
+ reg |= DSIM_PLL_DPDNSWAP_CLK;
+ if (dsi->swap_dn_dp_data)
+ reg |= DSIM_PLL_DPDNSWAP_DAT;
+
samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
{
struct device *dev = dsi->dev;
struct device_node *node = dev->of_node;
- int ret;
+ u32 lane_polarities[5] = { 0 };
+ struct device_node *endpoint;
+ int i, nr_lanes, ret;
ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
&dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim
*dsi)
if (ret < 0)
return ret;
+ endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+ nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+ if (nr_lanes > 0 && nr_lanes <= 4) {
+ /* Polarity 0 is clock lane, 1..4 are data lanes. */
+ of_property_read_u32_array(endpoint, "lane-polarities",
+ lane_polarities, nr_lanes + 1);
+ for (i = 1; i <= nr_lanes; i++) {
+ if (lane_polarities[1] != lane_polarities[i])
+ DRM_DEV_ERROR(dsi->dev, "Data lanes polarities
do not match");
+ }
+ if (lane_polarities[0])
+ dsi->swap_dn_dp_clk = true;
+ if (lane_polarities[1])
+ dsi->swap_dn_dp_data = true;
+ }
+
return 0;
}
diff --git a/include/drm/bridge/samsung-dsim.h
b/include/drm/bridge/samsung-dsim.h
index ba5484de2b30..6a37d1e079bf 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -95,6 +95,8 @@ struct samsung_dsim {
u32 mode_flags;
u32 format;
+ bool swap_dn_dp_clk;
+ bool swap_dn_dp_data;
int state;
struct drm_property *brightness;
struct completion completed;
--
2.34.1
[PATCH] dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references
From: Fabio Estevam video-interface.txt does not exist anymore, as it has been converted to video-interfaces.yaml. Update the references to the new file name. Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/bridge/ti,sn65dsi86.yaml | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml index 911564468c5e..967b1deb4936 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml @@ -106,7 +106,7 @@ properties: description: If you have 1 logical lane the bridge supports routing to either port 0 or port 1. Port 0 is suggested. - See ../../media/video-interface.txt for details. + See ../../media/video-interfaces.yaml for details. - minItems: 2 maxItems: 2 @@ -118,7 +118,7 @@ properties: description: If you have 2 logical lanes the bridge supports reordering but only on physical ports 0 and 1. - See ../../media/video-interface.txt for details. + See ../../media/video-interfaces.yaml for details. - minItems: 4 maxItems: 4 @@ -132,7 +132,7 @@ properties: description: If you have 4 logical lanes the bridge supports reordering in any way. - See ../../media/video-interface.txt for details. + See ../../media/video-interfaces.yaml for details. lane-polarities: minItems: 1 @@ -141,7 +141,7 @@ properties: enum: - 0 - 1 -description: See ../../media/video-interface.txt +description: See ../../media/video-interfaces.yaml dependencies: lane-polarities: [data-lanes] -- 2.34.1
[PATCH] dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references
From: Fabio Estevam video-interface.txt does not exist anymore, as it has been converted to video-interfaces.yaml. Instead of referencing video-interfaces.yaml multiple times, pass it as a $ref to the schema. Signed-off-by: Fabio Estevam --- Changes since v1: - Pass video-interfaces.yaml as a $ref to the schema. (Rob) .../devicetree/bindings/display/bridge/ti,sn65dsi86.yaml| 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml index 911564468c5e..6ec6d287bff4 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml @@ -90,7 +90,7 @@ properties: properties: endpoint: -$ref: /schemas/graph.yaml#/$defs/endpoint-base +$ref: /schemas/media/video-interfaces.yaml# unevaluatedProperties: false properties: @@ -106,7 +106,6 @@ properties: description: If you have 1 logical lane the bridge supports routing to either port 0 or port 1. Port 0 is suggested. - See ../../media/video-interface.txt for details. - minItems: 2 maxItems: 2 @@ -118,7 +117,6 @@ properties: description: If you have 2 logical lanes the bridge supports reordering but only on physical ports 0 and 1. - See ../../media/video-interface.txt for details. - minItems: 4 maxItems: 4 @@ -132,7 +130,6 @@ properties: description: If you have 4 logical lanes the bridge supports reordering in any way. - See ../../media/video-interface.txt for details. lane-polarities: minItems: 1 @@ -141,7 +138,6 @@ properties: enum: - 0 - 1 -description: See ../../media/video-interface.txt dependencies: lane-polarities: [data-lanes] -- 2.34.1
Re: [PATCH v2 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'
Hi Rob, On 12/04/2023 11:43, Rob Herring wrote: No, this should be video-interfaces.yaml since you use properties from it. Ok, will change it. +unevaluatedProperties: false + +properties: + data-lanes: +oneOf: + - minItems: 1 +maxItems: 4 +uniqueItems: true +items: + enum: [ 1, 2, 3, 4 ] The h/w really supports any combination of lanes to be used? The MIPI DSIM IP supports the usage of 1, 2, 3, or 4 data lanes. The following cases are possible: data-lanes = <1>; data-lanes = <1 2>; data-lanes = <1 2 3>; data-lanes = <1 2 3 4>; Lane reordering is not supported. +description: + See ../../media/video-interfaces.yaml for details. + + lane-polarities: +minItems: 1 +maxItems: 5 +items: + enum: [ 0, 1 ] +description: + See ../../media/video-interfaces.yaml for details. + The Samsung MIPI DSI IP requires that all the data lanes have + the same polarity. Sounds like a constraint: oneOf: - items: const: 0 - items: const: 1 Imagine a board that has 4 data lanes and only the clock lane is inverted. The representation is (the first entry is the clock lane, followed by the 4 data lanes): lane-polarities = <1 0 0 0 0>; If the board has no inversion on the clock lane, and has the data lanes inverted: lane-polarities = <0 1 1 1 1>; Should I keep the data-lanes and lane-polarities description as in this patch? Please advise. Thanks, Fabio Estevam
Re: [PATCH v15 00/16] drm: Add Samsung MIPI DSIM bridge
Hi Inki, On Mon, Mar 6, 2023 at 2:24 AM 대인기/Tizen Platform Lab(SR)/삼성전자 wrote: > Seems some issue Marek found on testing. If fixed then I will try to pick this > patch series up. Marek has successfully tested v16. Could you please apply v16? Thanks
[PATCH 2/2] drm/panel: seiko-43wvf1g: Add the 'enable-gpios' property
Sometimes a GPIO is needed to turn on/off the display.
Add support for this usecase by introducing the optional 'enable-gpios'
property.
Tested on a imx53qsb board.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/panel/panel-seiko-43wvf1g.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
b/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
index 76160e5d43bd..c250ca36a5b3 100644
--- a/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
+++ b/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
@@ -7,6 +7,7 @@
*/
#include
+#include
#include
#include
#include
@@ -48,6 +49,7 @@ struct seiko_panel {
const struct seiko_panel_desc *desc;
struct regulator *dvdd;
struct regulator *avdd;
+ struct gpio_desc *enable_gpio;
};
static inline struct seiko_panel *to_seiko_panel(struct drm_panel *panel)
@@ -139,6 +141,8 @@ static int seiko_panel_unprepare(struct drm_panel *panel)
if (!p->prepared)
return 0;
+ gpiod_set_value_cansleep(p->enable_gpio, 0);
+
regulator_disable(p->avdd);
/* Add a 100ms delay as per the panel datasheet */
@@ -174,6 +178,8 @@ static int seiko_panel_prepare(struct drm_panel *panel)
goto disable_dvdd;
}
+ gpiod_set_value_cansleep(p->enable_gpio, 1);
+
p->prepared = true;
return 0;
@@ -252,6 +258,12 @@ static int seiko_panel_probe(struct device *dev,
if (IS_ERR(panel->avdd))
return PTR_ERR(panel->avdd);
+ panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
+GPIOD_OUT_LOW);
+ if (IS_ERR(panel->enable_gpio))
+ return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
+"failed to request GPIO\n");
+
drm_panel_init(&panel->base, dev, &seiko_panel_funcs,
DRM_MODE_CONNECTOR_DPI);
--
2.34.1
[PATCH 1/2] dt-bindings: display: seiko, 43wvf1g: Add the 'enable-gpios' property
Add an optional 'enable-gpios' property that can be used to turn on/off the display. Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/panel/seiko,43wvf1g.yaml| 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml index cfaa50cf5f5d..496a39561db0 100644 --- a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml +++ b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml @@ -25,6 +25,8 @@ properties: avdd-supply: description: 5v analog regulator + enable-gpios: true + required: - compatible - dvdd-supply -- 2.34.1
[PATCH] dt-bindings: display: seiko, 43wvf1g: Change the maintainer's email
From: Fabio Estevam Marco's NXP email is no longer valid. Change it to his Gmail account. Signed-off-by: Fabio Estevam --- Marco, If you are no longer interested in being listed as the maintainer contact for the seiko,43wvf1g.yaml, please let me know. .../devicetree/bindings/display/panel/seiko,43wvf1g.yaml| 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml index a5426586b473..7977e07e2f48 100644 --- a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml +++ b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel maintainers: - - Marco Franchi + - Marco Franchi allOf: - $ref: panel-common.yaml# -- 2.34.1
Re: [PATCH v15 00/16] drm: Add Samsung MIPI DSIM bridge
Hi Inki, On Mon, Mar 13, 2023 at 9:51 PM Inki Dae wrote: >> Could you please apply v16? > > > I am planning to merge this patch series soon, but I will be proceeding with > the pull-request next week. As the DSIM driver is being moved to the bridge > folder, I would like to wait for acknowledgment from the bridge maintainers. > However, if there are no further comments until next week, I will proceed > with the pull-request. A friendly reminder: do you think you can proceed with the pull-request now? Thanks
[PATCH 1/2] dt-bindings: display: bridge: ldb: Add i.MX6SX support
From: Fabio Estevam i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout with i.MX8MP and i.MX93. Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/bridge/fsl,ldb.yaml | 11 +++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml index 6e0e3ba9b49e..4f842bcfba1a 100644 --- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml +++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: enum: + - fsl,imx6sx-ldb - fsl,imx8mp-ldb - fsl,imx93-ldb @@ -60,6 +61,16 @@ required: - ports allOf: + - if: + properties: +compatible: + contains: +const: fsl,imx6sx-ldb +then: + properties: +ports: + properties: +port@2: false - if: properties: compatible: -- 2.34.1
[PATCH 2/2] drm/bridge: fsl-ldb: Add i.MX6SX support
From: Fabio Estevam
i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout
with i.MX8MP and i.MX93.
There is no LVDS CTRL register on the i.MX6SX, so only write to
this register on the appropriate SoCs.
Add support for the i.MX6SX LDB.
Tested on a imx6sx-sdb board with a Hannstar HSD100PXN1 LVDS panel
and also on a custom i.MX6SX-based board.
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/fsl-ldb.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index 450b352914f4..f8e5d8ab98e3 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -56,6 +56,7 @@
#define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)
enum fsl_ldb_devtype {
+ IMX6SX_LDB,
IMX8MP_LDB,
IMX93_LDB,
};
@@ -64,9 +65,14 @@ struct fsl_ldb_devdata {
u32 ldb_ctrl;
u32 lvds_ctrl;
bool lvds_en_bit;
+ bool not_lvds_ctrl;
};
static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
+ [IMX6SX_LDB] = {
+ .ldb_ctrl = 0x18,
+ .not_lvds_ctrl = true,
+ },
[IMX8MP_LDB] = {
.ldb_ctrl = 0x5c,
.lvds_ctrl = 0x128,
@@ -202,6 +208,9 @@ static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg);
+ if (fsl_ldb->devdata->not_lvds_ctrl)
+ return;
+
/* Program LVDS_CTRL */
reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
@@ -228,7 +237,8 @@ static void fsl_ldb_atomic_disable(struct drm_bridge
*bridge,
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl,
LVDS_CTRL_LVDS_EN);
else
- regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
+ if (!fsl_ldb->devdata->not_lvds_ctrl)
+ regmap_write(fsl_ldb->regmap,
fsl_ldb->devdata->lvds_ctrl, 0);
regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0);
clk_disable_unprepare(fsl_ldb->clk);
@@ -355,6 +365,8 @@ static void fsl_ldb_remove(struct platform_device *pdev)
}
static const struct of_device_id fsl_ldb_match[] = {
+ { .compatible = "fsl,imx6sx-ldb",
+ .data = &fsl_ldb_devdata[IMX6SX_LDB], },
{ .compatible = "fsl,imx8mp-ldb",
.data = &fsl_ldb_devdata[IMX8MP_LDB], },
{ .compatible = "fsl,imx93-ldb",
--
2.34.1
[PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'
From: Fabio Estevam The Samsung DSIM IP block allows the inversion of the clock and data lanes. Add an optional property called 'lane-polarities' that describes the polarities of the MIPI DSI clock and data lanes. This is property is useful for properly describing the hardware when the board designer decided to switch the polarities of the MIPI DSI clock and/or data lanes. Signed-off-by: Fabio Estevam --- .../devicetree/bindings/display/exynos/exynos_dsim.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt index 2a5f0889ec32..65ed8ef7aed7 100644 --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt @@ -29,6 +29,12 @@ Required properties: Optional properties: - power-domains: a phandle to DSIM power domain node + - lane-polarities: Array that describes the polarities of the clock and data lanes. +1: inverted polarity +0: normal polarity +The first entry corresponds to the clock lanes. Subsequent entries correspond to the data lanes. +Example of a 4-lane system with only the clock lanes inverted: +lane-polarities = <1 0 0 0 0>; Child nodes: Should contain DSI peripheral nodes (see MIPI DSI bindings [1]). -- 2.34.1
[PATCH 2/2] drm/exynos: Implement support for DSI clock and data lane polarity swap
From: Marek Vasut
Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.
This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.
Signed-off-by: Marek Vasut
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++-
include/drm/bridge/samsung-dsim.h | 2 ++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c
b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..5791148e2da2 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -183,6 +183,8 @@
#define DSIM_AFC_CTL(x)(((x) & 0x7) << 5)
/* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
#define DSIM_FREQ_BAND(x) ((x) << 24)
#define DSIM_PLL_ENBIT(23)
#define DSIM_PLL_P(x, offset) ((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct
samsung_dsim *dsi,
reg |= DSIM_FREQ_BAND(band);
}
+ if (dsi->swap_dn_dp_clk)
+ reg |= DSIM_PLL_DPDNSWAP_CLK;
+ if (dsi->swap_dn_dp_data)
+ reg |= DSIM_PLL_DPDNSWAP_DAT;
+
samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
{
struct device *dev = dsi->dev;
struct device_node *node = dev->of_node;
- int ret;
+ u32 lane_polarities[5] = { 0 };
+ struct device_node *endpoint;
+ int i, nr_lanes, ret;
ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
&dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim
*dsi)
if (ret < 0)
return ret;
+ endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+ nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+ if (nr_lanes > 0 && nr_lanes <= 4) {
+ /* Polarity 0 is clock lane, 1..4 are data lanes. */
+ of_property_read_u32_array(endpoint, "lane-polarities",
+ lane_polarities, nr_lanes + 1);
+ for (i = 1; i <= nr_lanes; i++) {
+ if (lane_polarities[1] != lane_polarities[i])
+ DRM_DEV_ERROR(dsi->dev, "Data lanes polarities
do not match");
+ }
+ if (lane_polarities[0])
+ dsi->swap_dn_dp_clk = true;
+ if (lane_polarities[1])
+ dsi->swap_dn_dp_data = true;
+ }
+
return 0;
}
diff --git a/include/drm/bridge/samsung-dsim.h
b/include/drm/bridge/samsung-dsim.h
index ba5484de2b30..6a37d1e079bf 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -95,6 +95,8 @@ struct samsung_dsim {
u32 mode_flags;
u32 format;
+ bool swap_dn_dp_clk;
+ bool swap_dn_dp_data;
int state;
struct drm_property *brightness;
struct completion completed;
--
2.34.1
[PATCH v2] dt-bindings: display: seiko, 43wvf1g: Change the maintainer's contact
From: Fabio Estevam Marco's NXP email is no longer valid. Marco told me offline that he has no interest to be listed as the maintainer contact for this binding, so add my contact. Signed-off-by: Fabio Estevam --- Changes since v1: - Use my contact instead of Marco's personal email. .../devicetree/bindings/display/panel/seiko,43wvf1g.yaml| 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml index a5426586b473..1df3cbb51ff9 100644 --- a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml +++ b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel maintainers: - - Marco Franchi + - Fabio Estevam allOf: - $ref: panel-common.yaml# -- 2.34.1
[PATCH] drm/panel: simple: Add connector_type for innolux_at043tn24
From: Fabio Estevam
The innolux at043tn24 display is a parallel LCD. Pass the 'connector_type'
information to avoid the following warning:
panel-simple panel: Specify missing connector_type
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/panel/panel-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index a247a0e7c799..7c80528d571e 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -2178,6 +2178,7 @@ static const struct panel_desc innolux_at043tn24 = {
.height = 54,
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
};
--
2.34.1
[PATCH v2] drm/panel: simple: Add connector_type for innolux_at043tn24
From: Fabio Estevam
The innolux at043tn24 display is a parallel LCD. Pass the 'connector_type'
information to avoid the following warning:
panel-simple panel: Specify missing connector_type
Signed-off-by: Fabio Estevam
Fixes: 41bcceb4de9c ("drm/panel: simple: Add support for Innolux AT043TN24")
---
Changes since v1:
- Pass Fixes tag (Neil).
drivers/gpu/drm/panel/panel-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index a247a0e7c799..7c80528d571e 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -2178,6 +2178,7 @@ static const struct panel_desc innolux_at043tn24 = {
.height = 54,
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
};
--
2.34.1
[PATCH] drm/msm/a2xx: Pass the revision information
From: Fabio Estevam
Since commit cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified
before being set") the following run-time warning is observed:
[ cut here ]
WARNING: CPU: 0 PID: 1 at drivers/gpu/drm/msm/adreno/adreno_gpu.h:171
a2xx_gpu_init+0x138/0x184
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.4.0-rc7-next-20230620 #993
Fix the problem by assigning the GPU revision fields like it is
done in a6xx_gpu.
Fixes: cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified before
being set")
Signed-off-by: Fabio Estevam
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
index c67089a7ebc1..4e1218462a23 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
@@ -520,6 +520,8 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
struct msm_gpu *gpu;
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
+ struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
int ret;
if (!pdev) {
@@ -540,6 +542,23 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
gpu->perfcntrs = perfcntrs;
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
+ /*
+* We need to know the platform type before calling into adreno_gpu_init
+* so that the hw_apriv flag can be correctly set. Snoop into the info
+* and grab the revision number
+*/
+ info = adreno_info(config->rev);
+ if (!info)
+ return ERR_PTR(-EINVAL);
+
+ /* Assign these early so that we can use the is_aXYZ helpers */
+ /* Numeric revision IDs (e.g. 630) */
+ adreno_gpu->revn = info->revn;
+ /* New-style ADRENO_REV()-only */
+ adreno_gpu->rev = info->rev;
+ /* Quirk data */
+ adreno_gpu->info = info;
+
if (adreno_is_a20x(adreno_gpu))
adreno_gpu->registers = a200_registers;
else if (adreno_is_a225(adreno_gpu))
--
2.34.1
[PATCH 1/3] drm/msm/a3xx: Pass the revision information
From: Fabio Estevam
Commit cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified
before being set") exposes the need of setting the GPU revision fields
prior to using the adreno_is_xxx() functions.
Pass the GPU revision information to avoid run-time warning.
Signed-off-by: Fabio Estevam
---
Build-tested only.
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index c86b377f6f0d..fc23810d7684 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -530,6 +530,8 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
struct msm_gpu *gpu;
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
+ struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
struct icc_path *ocmem_icc_path;
struct icc_path *icc_path;
int ret;
@@ -558,6 +560,25 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
if (ret)
goto fail;
+ /*
+* We need to know the platform type before calling into adreno_gpu_init
+* so that the hw_apriv flag can be correctly set. Snoop into the info
+* and grab the revision number
+*/
+ info = adreno_info(config->rev);
+ if (!info) {
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ /* Assign these early so that we can use the is_aXYZ helpers */
+ /* Numeric revision IDs (e.g. 630) */
+ adreno_gpu->revn = info->revn;
+ /* New-style ADRENO_REV()-only */
+ adreno_gpu->rev = info->rev;
+ /* Quirk data */
+ adreno_gpu->info = info;
+
/* if needed, allocate gmem: */
if (adreno_is_a330(adreno_gpu)) {
ret = adreno_gpu_ocmem_init(&adreno_gpu->base.pdev->dev,
--
2.34.1
