Re: radeon syncronization
Jerome Glisse wrote: Hi, So while playing with buffer move i am facing a problem and would like to know if anyone ever faced it. I emitting a bitblt multi to move data from ttm to vram just after the bitblt multi there is a WAIT_UNTIL packet emitted with WAIT_2D_IDLECLEAN, WAIT_HOST_IDLECLEAN set however if i add a blit from the destination memory to the framebuffer (to see what gets copied) just after this wait packet i see garbage and the end of the copied data so it's like while doing the second blit the first blit isn't yet finished or even started. If i add long enough udelay before emitting the wait packet i see data fine. My guess is that wait idle doesn't work :( i have tried with setting many others (allmost all) wait flags but results stay the them i need a udelay. Anyone got though/information on that ? I'm assuming you're doing both blits and the wait using cp mode? Maybe you need an explicit cache flush after the first blit? (Though I wouldn't know why, should be the same cache for read and write I think, unless you're switching from 3d to 2d commands or something). Or maybe you'd need an explicit WAIT_FOR_IDLE packet3 (or the respective reg write), if this doesn't help (I guess that's bad for performance, should likely avoid it unless really necessary.) Roland - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2005. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ -- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
Re: radeon syncronization
Roland Scheidegger wrote: Jerome Glisse wrote: Hi, So while playing with buffer move i am facing a problem and would like to know if anyone ever faced it. I emitting a bitblt multi to move data from ttm to vram just after the bitblt multi there is a WAIT_UNTIL packet emitted with WAIT_2D_IDLECLEAN, WAIT_HOST_IDLECLEAN set however if i add a blit from the destination memory to the framebuffer (to see what gets copied) just after this wait packet i see garbage and the end of the copied data so it's like while doing the second blit the first blit isn't yet finished or even started. If i add long enough udelay before emitting the wait packet i see data fine. My guess is that wait idle doesn't work :( i have tried with setting many others (allmost all) wait flags but results stay the them i need a udelay. Anyone got though/information on that ? I'm assuming you're doing both blits and the wait using cp mode? Maybe you need an explicit cache flush after the first blit? (Though I wouldn't know why, should be the same cache for read and write I think, unless you're switching from 3d to 2d commands or something). Or maybe you'd need an explicit WAIT_FOR_IDLE packet3 (or the respective reg write), if this doesn't help (I guess that's bad for performance, should likely avoid it unless really necessary.) Roland This was a lot simpler want i first did the code i faced the dead lock i mention in another mail so to avoid it and keep working on others things i set the evict flag on buffer. So before the blit started the memory manager started to evict the buffer and i ended up blitting wrong things. Of course in the mean time i did forget that i was forcing to evict :( shame on me So now that i don't evict anymore every things seems to work smoothly :) to this regard. I might add a flush to the RB2D cache reg to be extra cautious on this. Cheers, Jerome Glisse - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2005. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ -- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
radeon syncronization
Hi, So while playing with buffer move i am facing a problem and would like to know if anyone ever faced it. I emitting a bitblt multi to move data from ttm to vram just after the bitblt multi there is a WAIT_UNTIL packet emitted with WAIT_2D_IDLECLEAN, WAIT_HOST_IDLECLEAN set however if i add a blit from the destination memory to the framebuffer (to see what gets copied) just after this wait packet i see garbage and the end of the copied data so it's like while doing the second blit the first blit isn't yet finished or even started. If i add long enough udelay before emitting the wait packet i see data fine. My guess is that wait idle doesn't work :( i have tried with setting many others (allmost all) wait flags but results stay the them i need a udelay. Anyone got though/information on that ? Cheers, Jerome Glisse - This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2005. http://clk.atdmt.com/MRT/go/vse012070mrt/direct/01/ -- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
