Re: [edk2] _gUefiDriverRevision definition?

2017-06-22 Thread Kinney, Michael D 
David,

The value comes from the UEFI_SPECIFICATION_VERSION define in the [Defines] 
section of a modules INF file.

If this is not defined, then the default value is 0.

Mike

-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of David F.
Sent: Thursday, June 22, 2017 8:27 PM
To: edk2-devel@lists.01.org
Subject: [edk2] _gUefiDriverRevision definition?

Just for information in general, where does one define the value for 
_gUefiDriverRevision ?

TIA!!
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[edk2] _gUefiDriverRevision definition?

2017-06-22 Thread David F. 
Just for information in general, where does one define the value for
_gUefiDriverRevision ?

TIA!!
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Re: [edk2] [PATCH v3 01/10] BaseTools: Tools change to support PI v1.5 Specification.

2017-06-22 Thread Gao, Liming 
Supreeth:
  I just realize MM_STANDALONE and MM_CORE_STANDALONE are new feature. They 
have no compatibility issue. We can directly define them with MM prefix instead 
of SMM prefix. So, for new added FV file type MM_STANDALONE and 
MM_CORE_STANDALONE, I prefer to use the same definition with PI spec. For new 
module type MM_STANDALONE and MM_CORE_STANDALONE, I suggest to update BaseTools 
to support them only. 

  For the existing SMM_CORE, DXE_SMM_DRIVER, they will still be kept for 
compatibility. 

Thanks
Liming
>-Original Message-
>From: Supreeth Venkatesh [mailto:supreeth.venkat...@arm.com]
>Sent: Friday, June 23, 2017 3:54 AM
>To: edk2-devel@lists.01.org
>Cc: leif.lindh...@linaro.org; Kinney, Michael D
>; Gao, Liming ;
>achin.gu...@arm.com; supreeth.venkat...@arm.com; fel...@ami.com;
>jbra...@qti.qualcomm.com; jonathan.zh...@cavium.com; Yao, Jiewen
>
>Subject: [PATCH v3 01/10] BaseTools: Tools change to support PI v1.5
>Specification.
>
>PI specification v1.5 defines new firmware volume file types.
>
>This patch adds the new file type EFI_FV_FILETYPE_SMM_STANDALONE and
>EFI_FV_FILETYPE_SMM_CORE_STANDALONE in GenFfs tool.
>*_SMM_* regex instead of *_MM_* is used to preserve
>backwards compatibility.
>
>Contributed-under: TianoCore Contribution Agreement 1.0
>Signed-off-by: Jiewen Yao 
>Signed-off-by: Supreeth Venkatesh 
>---
> BaseTools/Source/C/GenFfs/GenFfs.c | 8 ++--
> BaseTools/Source/C/Include/Common/PiFirmwareFile.h | 2 ++
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
>diff --git a/BaseTools/Source/C/GenFfs/GenFfs.c
>b/BaseTools/Source/C/GenFfs/GenFfs.c
>index c5d657b..c394b8b 100644
>--- a/BaseTools/Source/C/GenFfs/GenFfs.c
>+++ b/BaseTools/Source/C/GenFfs/GenFfs.c
>@@ -43,8 +43,10 @@ STATIC CHAR8 *mFfsFileType[] = {
>   "EFI_FV_FILETYPE_SMM",  // 0x0A
>   "EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE",// 0x0B
>   "EFI_FV_FILETYPE_COMBINED_SMM_DXE", // 0x0C
>-  "EFI_FV_FILETYPE_SMM_CORE"  // 0x0D
>- };
>+  "EFI_FV_FILETYPE_SMM_CORE", // 0x0D
>+  "EFI_FV_FILETYPE_SMM_STANDALONE",   // 0x0E
>+  "EFI_FV_FILETYPE_SMM_CORE_STANDALONE"   // 0x0F
>+};
>
> STATIC CHAR8 *mAlignName[] = {
>   "1", "2", "4", "8", "16", "32", "64", "128", "256", "512",
>@@ -130,6 +132,8 @@ Returns:
> EFI_FV_FILETYPE_DRIVER, 
> EFI_FV_FILETYPE_APPLICATION,\n\
> EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER,\n\
> EFI_FV_FILETYPE_SMM, EFI_FV_FILETYPE_SMM_CORE,\n\
>+EFI_FV_FILETYPE_SMM_STANDALONE,\n\
>+EFI_FV_FILETYPE_SMM_CORE_STANDALONE,\n\
> EFI_FV_FILETYPE_COMBINED_SMM_DXE, \n\
> EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE.\n");
>   fprintf (stdout, "  -g FileGuid, --fileguid FileGuid\n\
>diff --git a/BaseTools/Source/C/Include/Common/PiFirmwareFile.h
>b/BaseTools/Source/C/Include/Common/PiFirmwareFile.h
>index 2984860..8b40ec2 100644
>--- a/BaseTools/Source/C/Include/Common/PiFirmwareFile.h
>+++ b/BaseTools/Source/C/Include/Common/PiFirmwareFile.h
>@@ -52,6 +52,8 @@ typedef UINT8 EFI_FFS_FILE_STATE;
> #define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B
> #define EFI_FV_FILETYPE_COMBINED_SMM_DXE  0x0C
> #define EFI_FV_FILETYPE_SMM_CORE  0x0D
>+#define EFI_FV_FILETYPE_SMM_STANDALONE0x0E
>+#define EFI_FV_FILETYPE_SMM_CORE_STANDALONE   0x0F
> #define EFI_FV_FILETYPE_OEM_MIN   0xc0
> #define EFI_FV_FILETYPE_OEM_MAX   0xdf
> #define EFI_FV_FILETYPE_DEBUG_MIN 0xe0
>--
>2.7.4

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Re: [edk2] Constructor Order

2017-06-22 Thread Kinney, Michael D 
David,

Constructor order is determined by the build tool through evaluation of each of 
the library instance dependencies as declared in the [LibraryClasses] section 
of the INF.  This is a recursive algorithm to collect all the library instances 
because a module uses libs and each lib can use additional libs.

This process is described in the EDK II Build Specification in Section 8.2.5 
Post processing.

https://edk2-docs.gitbooks.io/edk-ii-build-specification/content/8_pre-build_autogen_stage/82_auto-generation_process.html#82-auto-generation-process

If you want a different order, then likely one or more of the lib instances 
being linked to a module does not have correct information about its lib 
dependencies in the [LibraryClasses] section of the INF.  If the dependencies 
are specified correctly, then the order generated by the build tool should be a 
valid order based on dependencies.  There are some cases where there could be 
ties, such that the order could be different and still correct, but there is no 
way to influence the order between ties.

Mike

-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of David F.
Sent: Thursday, June 22, 2017 3:05 PM
To: edk2-devel@lists.01.org
Subject: [edk2] Constructor Order

So I'm back from years ago trying to work out the constructor order.
It doesn't seem any change I make causes autogen.c to change the order to what 
I want to happen.  At least if someone could indicate which file I need to use 
to check the order, that would help.  I presume it's the .inf file of items 
being built in the [libraryclasses] section ?

I don't think [Packages] should matter?

TIA!!
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Re: [edk2] [Patch] NetworkPkg: Fix GCC build issue.

2017-06-22 Thread Ye, Ting 
Reviewed-by: Ye Ting  

-Original Message-
From: Fu, Siyuan 
Sent: Friday, June 23, 2017 9:00 AM
To: edk2-devel@lists.01.org
Cc: Ye, Ting ; Wu, Jiaxin 
Subject: [Patch] NetworkPkg: Fix GCC build issue.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Fu Siyuan 
Cc: Ye Ting 
Cc: Wu Jiaxin 
---
 NetworkPkg/HttpBootDxe/HttpBootImpl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/NetworkPkg/HttpBootDxe/HttpBootImpl.c 
b/NetworkPkg/HttpBootDxe/HttpBootImpl.c
index 56f5babeb4..63cf3960a9 100644
--- a/NetworkPkg/HttpBootDxe/HttpBootImpl.c
+++ b/NetworkPkg/HttpBootDxe/HttpBootImpl.c
@@ -630,6 +630,7 @@ EFI_LOAD_FILE_PROTOCOL  gHttpBootDxeLoadFile = {
   @retval EFI_ABORTED Tells the HTTP Boot driver to abort the 
current HTTP Boot process.
 **/
 EFI_STATUS
+EFIAPI
 HttpBootCallback (
   IN EFI_HTTP_BOOT_CALLBACK_PROTOCOL *This,
   IN EFI_HTTP_BOOT_CALLBACK_DATA_TYPEDataType,
-- 
2.13.0.windows.1

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Re: [edk2] [Patch] NetworkPkg: Fix GCC build issue.

2017-06-22 Thread Wu, Jiaxin 
Reviewed-by: Wu Jiaxin 


> -Original Message-
> From: Fu, Siyuan
> Sent: Friday, June 23, 2017 9:00 AM
> To: edk2-devel@lists.01.org
> Cc: Ye, Ting ; Wu, Jiaxin 
> Subject: [Patch] NetworkPkg: Fix GCC build issue.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Fu Siyuan 
> Cc: Ye Ting 
> Cc: Wu Jiaxin 
> ---
>  NetworkPkg/HttpBootDxe/HttpBootImpl.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/NetworkPkg/HttpBootDxe/HttpBootImpl.c
> b/NetworkPkg/HttpBootDxe/HttpBootImpl.c
> index 56f5babeb4..63cf3960a9 100644
> --- a/NetworkPkg/HttpBootDxe/HttpBootImpl.c
> +++ b/NetworkPkg/HttpBootDxe/HttpBootImpl.c
> @@ -630,6 +630,7 @@ EFI_LOAD_FILE_PROTOCOL  gHttpBootDxeLoadFile = {
>@retval EFI_ABORTED Tells the HTTP Boot driver to abort the 
> current
> HTTP Boot process.
>  **/
>  EFI_STATUS
> +EFIAPI
>  HttpBootCallback (
>IN EFI_HTTP_BOOT_CALLBACK_PROTOCOL *This,
>IN EFI_HTTP_BOOT_CALLBACK_DATA_TYPEDataType,
> --
> 2.13.0.windows.1

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[edk2] [Patch] NetworkPkg: Fix GCC build issue.

2017-06-22 Thread Fu Siyuan 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Fu Siyuan 
Cc: Ye Ting 
Cc: Wu Jiaxin 
---
 NetworkPkg/HttpBootDxe/HttpBootImpl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/NetworkPkg/HttpBootDxe/HttpBootImpl.c 
b/NetworkPkg/HttpBootDxe/HttpBootImpl.c
index 56f5babeb4..63cf3960a9 100644
--- a/NetworkPkg/HttpBootDxe/HttpBootImpl.c
+++ b/NetworkPkg/HttpBootDxe/HttpBootImpl.c
@@ -630,6 +630,7 @@ EFI_LOAD_FILE_PROTOCOL  gHttpBootDxeLoadFile = {
   @retval EFI_ABORTED Tells the HTTP Boot driver to abort the 
current HTTP Boot process.
 **/
 EFI_STATUS
+EFIAPI
 HttpBootCallback (
   IN EFI_HTTP_BOOT_CALLBACK_PROTOCOL *This,
   IN EFI_HTTP_BOOT_CALLBACK_DATA_TYPEDataType,
-- 
2.13.0.windows.1

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[edk2] Constructor Order

2017-06-22 Thread David F. 
So I'm back from years ago trying to work out the constructor order.
It doesn't seem any change I make causes autogen.c to change the order
to what I want to happen.  At least if someone could indicate which
file I need to use to check the order, that would help.  I presume
it's the .inf file of items being built in the [libraryclasses]
section ?

I don't think [Packages] should matter?

TIA!!
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[edk2] [PATCH v7 11/17] OvmfPkg/QemuFwCfgLib: Prepare for SEV support

2017-06-22 Thread Brijesh Singh 
Add SEV specific internal functions which will be used while intergrating
the SEV support into QemuFwCfgLib.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Jordan Justen 
---
 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h | 37 
 1 file changed, 37 insertions(+)

diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h
index 6e87c625102e..8cfa7913ffae 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h
@@ -2,6 +2,7 @@
   Internal interfaces specific to the QemuFwCfgLib instances in OvmfPkg.
 
   Copyright (C) 2016, Red Hat, Inc.
+  Copyright (C) 2017, Advanced Micro Devices. All rights reserved
 
   This program and the accompanying materials are licensed and made available
   under the terms and conditions of the BSD License which accompanies this
@@ -43,4 +44,40 @@ InternalQemuFwCfgDmaIsAvailable (
   VOID
   );
 
+/**
+ Returns a boolean indicating whether SEV support is enabled
+
+ @retvalTRUESEV is enabled
+ @retvalFALSE   SEV is disabled
+**/
+BOOLEAN
+InternalQemuFwCfgSevIsEnabled (
+  VOID
+  );
+
+/**
+ Allocate a bounce buffer for SEV DMA.
+
+  @param[out]Buffer   Allocated DMA Buffer pointer
+  @param[in] NumPage  Number of pages.
+
+**/
+VOID
+InternalQemuFwCfgSevDmaAllocateBuffer (
+  OUTVOID **Buffer,
+  IN UINT32   NumPages
+  );
+
+/**
+ Free the DMA buffer allocated using InternalQemuFwCfgSevDmaAllocateBuffer
+
+  @param[in] NumPage  Number of pages.
+  @param[in] Buffer   DMA Buffer pointer
+
+**/
+VOID
+InternalQemuFwCfgSevDmaFreeBuffer (
+  IN VOID *Buffer,
+  IN UINT32   NumPages
+  );
 #endif
-- 
2.7.4

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[edk2] [PATCH v7 13/17] OvmfPkg/QemuFwCfgLib: Implement SEV internal functions for PEI phase

2017-06-22 Thread Brijesh Singh 
Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Jordan Justen 
---
 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf |  1 +
 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c  | 72 +++-
 2 files changed, 71 insertions(+), 2 deletions(-)

diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf
index 47e23b97eccf..7e51c3f160ac 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf
@@ -47,4 +47,5 @@ [LibraryClasses]
   DebugLib
   IoLib
   MemoryAllocationLib
+  MemEncryptSevLib
 
diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c
index ac05f4c347f3..40f89c3b53e2 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c
@@ -4,6 +4,7 @@
 
   Copyright (C) 2013, Red Hat, Inc.
   Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.
+  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
 
   This program and the accompanying materials are licensed and made available
   under the terms and conditions of the BSD License which accompanies this
@@ -14,8 +15,10 @@
   WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
+#include 
 #include 
 #include 
+#include 
 
 #include "QemuFwCfgLibInternal.h"
 
@@ -76,8 +79,18 @@ QemuFwCfgInitialize (
   if ((Revision & FW_CFG_F_DMA) == 0) {
 DEBUG ((DEBUG_INFO, "QemuFwCfg interface (IO Port) is supported.\n"));
   } else {
-mQemuFwCfgDmaSupported = TRUE;
-DEBUG ((DEBUG_INFO, "QemuFwCfg interface (DMA) is supported.\n"));
+//
+// If SEV is enabled then we do not support DMA operations in PEI phase.
+// This is mainly because DMA in SEV guest requires using bounce buffer
+// (which need to allocate dynamic memory and allocating a PAGE size'd
+// buffer can be challenge in PEI phase)
+//
+if (InternalQemuFwCfgSevIsEnabled ()) {
+  DEBUG ((DEBUG_INFO, "SEV: QemuFwCfg fallback to IO Port interface.\n"));
+} else {
+  mQemuFwCfgDmaSupported = TRUE;
+  DEBUG ((DEBUG_INFO, "QemuFwCfg interface (DMA) is supported.\n"));
+}
   }
   return RETURN_SUCCESS;
 }
@@ -114,3 +127,58 @@ InternalQemuFwCfgDmaIsAvailable (
 {
   return mQemuFwCfgDmaSupported;
 }
+
+/**
+
+ Returns a boolean indicating whether SEV is enabled
+
+ @retvalTRUESEV is enabled
+ @retvalFALSE   SEV is disabled
+**/
+BOOLEAN
+InternalQemuFwCfgSevIsEnabled (
+  VOID
+  )
+{
+  return MemEncryptSevIsEnabled ();
+}
+
+/**
+ Allocate a bounce buffer for SEV DMA.
+
+  @param[in] NumPage  Number of pages.
+  @param[out]Buffer   Allocated DMA Buffer pointer
+
+**/
+VOID
+InternalQemuFwCfgSevDmaAllocateBuffer (
+  OUTVOID **Buffer,
+  IN UINT32   NumPages
+  )
+{
+  //
+  // We should never reach here
+  //
+  ASSERT (FALSE);
+  CpuDeadLoop ();
+}
+
+/**
+ Free the DMA buffer allocated using InternalQemuFwCfgSevDmaAllocateBuffer
+
+  @param[in] NumPage  Number of pages.
+  @param[in] Buffer   DMA Buffer pointer
+
+**/
+VOID
+InternalQemuFwCfgSevDmaFreeBuffer (
+  IN VOID *Buffer,
+  IN UINT32   NumPages
+  )
+{
+  //
+  // We should never reach here
+  //
+  ASSERT (FALSE);
+  CpuDeadLoop ();
+}
-- 
2.7.4

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[edk2] [PATCH v7 14/17] OvmfPkg/QemuFwCfgLib: Implement SEV internal function for Dxe phase

2017-06-22 Thread Brijesh Singh 
When SEV is enabled, the DMA must be performed on unencrypted pages.
So when get asked to perfom FWCFG DMA read or write, we allocate a
intermediate (bounce buffer) unencrypted buffer and use this buffer
for DMA read or write.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Jordan Justen 
Reviewed-by: Laszlo Ersek 
---
 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf |   7 ++
 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c  | 114 
 2 files changed, 121 insertions(+)

diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf
index d7e368e5435d..11cbb3c4f393 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf
@@ -39,6 +39,7 @@ [Sources]
 
 [Packages]
   MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
   OvmfPkg/OvmfPkg.dec
 
 [LibraryClasses]
@@ -47,4 +48,10 @@ [LibraryClasses]
   DebugLib
   IoLib
   MemoryAllocationLib
+  MemEncryptSevLib
 
+[Protocols]
+  gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES
+
+[Depex]
+  gEdkiiIoMmuProtocolGuid OR gIoMmuAbsentProtocolGuid
diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c
index ac05f4c347f3..f8eb03bc3a9a 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c
@@ -4,6 +4,7 @@
 
   Copyright (C) 2013, Red Hat, Inc.
   Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.
+  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
 
   This program and the accompanying materials are licensed and made available
   under the terms and conditions of the BSD License which accompanies this
@@ -14,14 +15,36 @@
   WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
+#include 
+
+#include 
+
+#include 
 #include 
 #include 
+#include 
+#include 
 
 #include "QemuFwCfgLibInternal.h"
 
 STATIC BOOLEAN mQemuFwCfgSupported = FALSE;
 STATIC BOOLEAN mQemuFwCfgDmaSupported;
 
+STATIC EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;
+/**
+
+ Returns a boolean indicating whether SEV is enabled
+
+ @retvalTRUESEV is enabled
+ @retvalFALSE   SEV is disabled
+**/
+BOOLEAN
+InternalQemuFwCfgSevIsEnabled (
+  VOID
+  )
+{
+  return MemEncryptSevIsEnabled ();
+}
 
 /**
   Returns a boolean indicating if the firmware configuration interface
@@ -79,6 +102,24 @@ QemuFwCfgInitialize (
 mQemuFwCfgDmaSupported = TRUE;
 DEBUG ((DEBUG_INFO, "QemuFwCfg interface (DMA) is supported.\n"));
   }
+
+  if (mQemuFwCfgDmaSupported && MemEncryptSevIsEnabled ()) {
+EFI_STATUS   Status;
+
+//
+// IoMmuDxe driver must have installed the IOMMU protocol. If we are not
+// able to locate the protocol then something must have gone wrong.
+//
+Status = gBS->LocateProtocol (, NULL, (VOID 
**));
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR,
+"QemuFwCfgSevDma %a:%a Failed to locate IOMMU protocol.\n",
+gEfiCallerBaseName, __FUNCTION__));
+  ASSERT (FALSE);
+  CpuDeadLoop ();
+}
+  }
+
   return RETURN_SUCCESS;
 }
 
@@ -114,3 +155,76 @@ InternalQemuFwCfgDmaIsAvailable (
 {
   return mQemuFwCfgDmaSupported;
 }
+
+/**
+ Allocate a bounce buffer for SEV DMA.
+
+  @param[in] NumPage  Number of pages.
+  @param[out]Buffer   Allocated DMA Buffer pointer
+
+**/
+VOID
+InternalQemuFwCfgSevDmaAllocateBuffer (
+  OUTVOID **Buffer,
+  IN UINT32   NumPages
+  )
+{
+  EFI_STATUSStatus;
+
+  ASSERT (mIoMmuProtocol != NULL);
+
+  Status = mIoMmuProtocol->AllocateBuffer (
+mIoMmuProtocol,
+0,
+EfiBootServicesData,
+NumPages,
+Buffer,
+EDKII_IOMMU_ATTRIBUTE_MEMORY_CACHED
+  );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR,
+  "%a:%a failed to allocate %u pages\n", gEfiCallerBaseName, __FUNCTION__,
+  NumPages));
+ASSERT (FALSE);
+CpuDeadLoop ();
+  }
+
+  DEBUG ((DEBUG_VERBOSE,
+"%a:%a buffer 0x%Lx Pages %u\n", gEfiCallerBaseName, __FUNCTION__,
+(UINT64)(UINTN)Buffer, NumPages));
+}
+
+/**
+ Free the DMA buffer allocated using InternalQemuFwCfgSevDmaAllocateBuffer
+
+  @param[in] NumPage  Number of pages.
+  @param[in] Buffer   DMA Buffer pointer
+
+**/
+VOID
+InternalQemuFwCfgSevDmaFreeBuffer (
+  IN VOID *Buffer,
+  IN UINT32   NumPages
+  )
+{
+  EFI_STATUSStatus;
+
+  ASSERT (mIoMmuProtocol != NULL);
+
+  Status = mIoMmuProtocol->FreeBuffer (
+mIoMmuProtocol,
+NumPages,
+Buffer
+

[edk2] [PATCH v7 17/17] OvmfPkg: update PciHostBridgeDxe to use PlatformHasIoMmuLib

2017-06-22 Thread Brijesh Singh 
This patch enables PciHostBridgeDxe driver to use Platform IoMMU detection
library to ensure that PciHostBridgeDxe is run after platform IoMmuDxe
driver has checked whether platform need to install IOMMU protocol provider.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Suggested-by: Laszlo Ersek 
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
---
 OvmfPkg/OvmfPkgIa32.dsc| 1 +
 OvmfPkg/OvmfPkgIa32X64.dsc | 1 +
 OvmfPkg/OvmfPkgX64.dsc | 1 +
 3 files changed, 3 insertions(+)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index fffee6b0610b..7bc2404ca84a 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -626,6 +626,7 @@ [Components]
   MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
 
   PciHostBridgeLib|OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  NULL|OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.inf
   }
   MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {
 
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index a7a6c4694bca..e6773084a0f5 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -635,6 +635,7 @@ [Components.X64]
   MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
 
   PciHostBridgeLib|OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  NULL|OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.inf
   }
   MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {
 
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 31145b4bcfad..905ed30232ef 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -633,6 +633,7 @@ [Components]
   MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
 
   PciHostBridgeLib|OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  NULL|OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.inf
   }
   MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {
 
-- 
2.7.4

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[edk2] [PATCH v7 15/17] OvmfPkg/QemuFwCfgLib: Add option to dynamic alloc FW_CFG_DMA Access

2017-06-22 Thread Brijesh Singh 
Update InternalQemuFwCfgDmaBytes() to work with DMA Access pointer.
The change provides the flexibility to dynamically allocate the "Access"
when SEV is enabled.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Jordan Justen 
---
 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c
index 1bf725d8b7ae..73a19772bee1 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c
@@ -68,7 +68,8 @@ InternalQemuFwCfgDmaBytes (
   IN UINT32   Control
   )
 {
-  volatile FW_CFG_DMA_ACCESS Access;
+  volatile FW_CFG_DMA_ACCESS LocalAccess;
+  volatile FW_CFG_DMA_ACCESS *Access;
   UINT32 AccessHigh, AccessLow;
   UINT32 Status;
 
@@ -79,9 +80,11 @@ InternalQemuFwCfgDmaBytes (
 return;
   }
 
-  Access.Control = SwapBytes32 (Control);
-  Access.Length  = SwapBytes32 (Size);
-  Access.Address = SwapBytes64 ((UINTN)Buffer);
+  Access = 
+
+  Access->Control = SwapBytes32 (Control);
+  Access->Length  = SwapBytes32 (Size);
+  Access->Address = SwapBytes64 ((UINTN)Buffer);
 
   //
   // Delimit the transfer from (a) modifications to Access, (b) in case of a
@@ -92,8 +95,8 @@ InternalQemuFwCfgDmaBytes (
   //
   // Start the transfer.
   //
-  AccessHigh = (UINT32)RShiftU64 ((UINTN), 32);
-  AccessLow  = (UINT32)(UINTN)
+  AccessHigh = (UINT32)RShiftU64 ((UINTN)Access, 32);
+  AccessLow  = (UINT32)(UINTN)Access;
   IoWrite32 (FW_CFG_IO_DMA_ADDRESS, SwapBytes32 (AccessHigh));
   IoWrite32 (FW_CFG_IO_DMA_ADDRESS + 4, SwapBytes32 (AccessLow));
 
@@ -106,7 +109,7 @@ InternalQemuFwCfgDmaBytes (
   // Wait for the transfer to complete.
   //
   do {
-Status = SwapBytes32 (Access.Control);
+Status = SwapBytes32 (Access->Control);
 ASSERT ((Status & FW_CFG_DMA_CTL_ERROR) == 0);
   } while (Status != 0);
 
-- 
2.7.4

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[edk2] [PATCH v7 12/17] OvmfPkg/QemuFwCfgLib: Implement SEV internal function for SEC phase

2017-06-22 Thread Brijesh Singh 
Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Jordan Justen 
---
 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c | 57 
 1 file changed, 57 insertions(+)

diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c
index 465ccbe90dad..071b8d9b91d4 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c
@@ -6,6 +6,7 @@
 
   Copyright (C) 2013, Red Hat, Inc.
   Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.
+  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
 
   This program and the accompanying materials are licensed and made available
   under the terms and conditions of the BSD License which accompanies this
@@ -94,3 +95,59 @@ InternalQemuFwCfgDmaIsAvailable (
 {
   return FALSE;
 }
+
+/**
+
+ Returns a boolean indicating whether SEV is enabled
+
+ @retvalTRUESEV is enabled
+ @retvalFALSE   SEV is disabled
+**/
+BOOLEAN
+InternalQemuFwCfgSevIsEnabled (
+  VOID
+  )
+{
+  //
+  // DMA is not supported in SEC phase hence SEV support is irrelevant
+  //
+  return FALSE;
+}
+
+/**
+ Allocate a bounce buffer for SEV DMA.
+
+  @param[in] NumPage  Number of pages.
+  @param[out]Buffer   Allocated DMA Buffer pointer
+
+**/
+VOID
+InternalQemuFwCfgSevDmaAllocateBuffer (
+  OUTVOID **Buffer,
+  IN UINT32   NumPages
+  )
+{
+  //
+  // We should never reach here
+  //
+  ASSERT (FALSE);
+}
+
+/**
+ Free the DMA buffer allocated using InternalQemuFwCfgSevDmaAllocateBuffer
+
+  @param[in] NumPage  Number of pages.
+  @param[in] Buffer   DMA Buffer pointer
+
+**/
+VOID
+InternalQemuFwCfgSevDmaFreeBuffer (
+  IN VOID *Buffer,
+  IN UINT32   NumPages
+  )
+{
+  //
+  // We should never reach here
+  //
+  ASSERT (FALSE);
+}
-- 
2.7.4

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[edk2] [PATCH v7 16/17] OvmfPkg/QemuFwCfgLib: Add SEV support

2017-06-22 Thread Brijesh Singh 
When SEV is enabled, use a bounce buffer to perform the DMA operation.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Jordan Justen 
---
 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c | 54 +++-
 1 file changed, 52 insertions(+), 2 deletions(-)

diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c
index 73a19772bee1..dbebd36b1853 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c
@@ -72,6 +72,8 @@ InternalQemuFwCfgDmaBytes (
   volatile FW_CFG_DMA_ACCESS *Access;
   UINT32 AccessHigh, AccessLow;
   UINT32 Status;
+  UINT32 NumPages;
+  VOID   *DmaBuffer, *BounceBuffer;
 
   ASSERT (Control == FW_CFG_DMA_CTL_WRITE || Control == FW_CFG_DMA_CTL_READ ||
 Control == FW_CFG_DMA_CTL_SKIP);
@@ -80,11 +82,44 @@ InternalQemuFwCfgDmaBytes (
 return;
   }
 
-  Access = 
+  //
+  // When SEV is enabled then allocate DMA bounce buffer
+  //
+  if (InternalQemuFwCfgSevIsEnabled ()) {
+UINTN  TotalSize;
+
+TotalSize = sizeof (*Access);
+//
+// Skip operation does not need buffer
+//
+if (Control != FW_CFG_DMA_CTL_SKIP) {
+  TotalSize += Size;
+}
+
+//
+// Allocate SEV DMA buffer
+//
+NumPages = (UINT32)EFI_SIZE_TO_PAGES (TotalSize);
+InternalQemuFwCfgSevDmaAllocateBuffer (, NumPages);
+
+Access = BounceBuffer;
+DmaBuffer = (UINT8*)BounceBuffer + sizeof (*Access);
+
+//
+//  Decrypt data from encrypted guest buffer into DMA buffer
+//
+if (Control == FW_CFG_DMA_CTL_WRITE) {
+  CopyMem (DmaBuffer, Buffer, Size);
+}
+  } else {
+Access = 
+DmaBuffer = Buffer;
+BounceBuffer = NULL;
+  }
 
   Access->Control = SwapBytes32 (Control);
   Access->Length  = SwapBytes32 (Size);
-  Access->Address = SwapBytes64 ((UINTN)Buffer);
+  Access->Address = SwapBytes64 ((UINTN)DmaBuffer);
 
   //
   // Delimit the transfer from (a) modifications to Access, (b) in case of a
@@ -117,6 +152,21 @@ InternalQemuFwCfgDmaBytes (
   // After a read, the caller will want to use Buffer.
   //
   MemoryFence ();
+
+  //
+  // If Bounce buffer was allocated then copy the data into guest buffer and
+  // free the bounce buffer
+  //
+  if (BounceBuffer != NULL) {
+//
+//  Encrypt the data from DMA buffer into guest buffer
+//
+if (Control == FW_CFG_DMA_CTL_READ) {
+  CopyMem (Buffer, DmaBuffer, Size);
+}
+
+InternalQemuFwCfgSevDmaFreeBuffer (BounceBuffer, NumPages);
+  }
 }
 
 
-- 
2.7.4

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[edk2] [PATCH v7 10/17] OvmfPkg/QemuFwCfgLib: Provide Pei and Dxe specific library

2017-06-22 Thread Brijesh Singh 
Current QemuFwCfgLib.inf is used in both Pei and Dxe phases. Add Pei
and Dxe inf file to provide a seperate QemuFwCfgLib instances for Pei
and Dxe phases.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Jordan Justen 
---
 OvmfPkg/OvmfPkgIa32.dsc| 3 ++-
 OvmfPkg/OvmfPkgIa32X64.dsc | 3 ++-
 OvmfPkg/OvmfPkgX64.dsc | 3 ++-
 OvmfPkg/Library/QemuFwCfgLib/{QemuFwCfgLib.inf => QemuFwCfgDxeLib.inf} | 8 

 OvmfPkg/Library/QemuFwCfgLib/{QemuFwCfgLib.inf => QemuFwCfgPeiLib.inf} | 8 

 OvmfPkg/Library/QemuFwCfgLib/{QemuFwCfgPeiDxe.c => QemuFwCfgDxe.c} | 0
 OvmfPkg/Library/QemuFwCfgLib/{QemuFwCfgPeiDxe.c => QemuFwCfgPei.c} | 0
 7 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 18544d7cfd73..fffee6b0610b 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -142,7 +142,7 @@ [LibraryClasses]
   DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
   UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
   
SerializeVariablesLib|OvmfPkg/Library/SerializeVariablesLib/SerializeVariablesLib.inf
-  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
+  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf
   VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
   LoadLinuxLib|OvmfPkg/Library/LoadLinuxLib/LoadLinuxLib.inf
   
MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf
@@ -260,6 +260,7 @@ [LibraryClasses.common.PEIM]
   MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
   QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf
   PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf
 
 [LibraryClasses.common.DXE_CORE]
   HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 1b3bf3517a9f..a7a6c4694bca 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -147,7 +147,7 @@ [LibraryClasses]
   DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
   UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
   
SerializeVariablesLib|OvmfPkg/Library/SerializeVariablesLib/SerializeVariablesLib.inf
-  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
+  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf
   VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
   LoadLinuxLib|OvmfPkg/Library/LoadLinuxLib/LoadLinuxLib.inf
   
MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf
@@ -265,6 +265,7 @@ [LibraryClasses.common.PEIM]
   MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
   QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf
   PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf
 
 [LibraryClasses.common.DXE_CORE]
   HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 9fdabaf0eac4..31145b4bcfad 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -147,7 +147,7 @@ [LibraryClasses]
   DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
   UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
   
SerializeVariablesLib|OvmfPkg/Library/SerializeVariablesLib/SerializeVariablesLib.inf
-  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
+  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf
   VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
   LoadLinuxLib|OvmfPkg/Library/LoadLinuxLib/LoadLinuxLib.inf
   
MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf
@@ -265,6 +265,7 @@ [LibraryClasses.common.PEIM]
   MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
   QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf
   PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf
 
 [LibraryClasses.common.DXE_CORE]
   HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf
similarity index 80%
copy from OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
copy to OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf
index 689476032d39..d7e368e5435d 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf
@@ -18,11 +18,11 @@
 
 [Defines]
   INF_VERSION= 0x00010005
-  BASE_NAME  = QemuFwCfgLib
-  FILE_GUID  =

[edk2] [PATCH v7 07/17] OvmfPkg: Introduce IoMmuAbsent Protocol GUID

2017-06-22 Thread Brijesh Singh 
Platforms that optionally provide an IOMMU protocol should do so by
including a DXE driver (usually called IoMmuDxe) that produces either
the IOMMU protocol -- if the underlying capabilities are available --,
or gIoMmuAbsentProtocolGuid, to signal that the IOMMU capability
detection completed with negative result (i.e., no IOMMU will be
available in the system).

In turn, DXE drivers (and library instances) that are supposed to use
the IOMMU protocol if it is available should add the following to
their DEPEX:

gEdkiiIoMmuProtocolGuid OR gIoMmuAbsentProtocolGuid

This ensures these client modules will only be dispatched after IOMMU
detection completes (with positive or negative result).

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Cc: Leo Duran 
Contributed-under: TianoCore Contribution Agreement 1.0
Suggested-by: Jordan Justen 
Suggested-by: Laszlo Ersek 
Signed-off-by: Brijesh Singh 
---
 OvmfPkg/OvmfPkg.dec | 1 +
 1 file changed, 1 insertion(+)

diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 5627be0bab0a..4241af10c3d0 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -69,6 +69,7 @@ [Protocols]
   gBlockMmioProtocolGuid  = {0x6b558ce3, 0x69e5, 0x4c67, {0xa6, 
0x34, 0xf7, 0xfe, 0x72, 0xad, 0xbe, 0x84}}
   gXenBusProtocolGuid = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 
0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}
   gXenIoProtocolGuid  = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 
0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}
+  gIoMmuAbsentProtocolGuid= {0xf8775d50, 0x8abd, 0x4adf, {0x92, 
0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}
 
 [PcdsFixedAtBuild]
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0
-- 
2.7.4

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[edk2] [PATCH v7 09/17] OvmfPkg: Add IoMmuDxe driver

2017-06-22 Thread Brijesh Singh 
The IOMMU protocol driver provides capabilities to set a DMA access
attribute and methods to allocate, free, map and unmap the DMA memory
for the PCI Bus devices.

Due to security reasons all DMA operations inside the SEV guest must
be performed on shared (i.e unencrypted) pages. The IOMMU protocol
driver for the SEV guest uses a bounce buffer to map guest DMA buffer
to shared pages inorder to provide the support for DMA operations inside
SEV guest.

IoMmuDxe driver looks for SEV capabilities, if present then it installs
the real IOMMU protocol otherwise it installs placeholder protocol.
Currently, PciHostBridgeDxe and QemuFWCfgLib need to know the existance
of IOMMU protocol. The modules needing to know the existance of IOMMU
support should add

  gEdkiiIoMmuProtocolGuid OR gIoMmuAbsentProtocolGuid

in their depex to ensure that platform IOMMU detection has been performed.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Cc: Leo Duran 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Suggested-by: Jiewen Yao 
Signed-off-by: Brijesh Singh 
Reviewed-by: Jiewen Yao 
Acked-by: Laszlo Ersek 
---
 OvmfPkg/OvmfPkgIa32.dsc|   1 +
 OvmfPkg/OvmfPkgIa32X64.dsc |   1 +
 OvmfPkg/OvmfPkgX64.dsc |   1 +
 OvmfPkg/OvmfPkgIa32.fdf|   1 +
 OvmfPkg/OvmfPkgIa32X64.fdf |   1 +
 OvmfPkg/OvmfPkgX64.fdf |   1 +
 OvmfPkg/IoMmuDxe/IoMmuDxe.inf  |  49 +++
 OvmfPkg/IoMmuDxe/AmdSevIoMmu.h |  43 ++
 OvmfPkg/IoMmuDxe/AmdSevIoMmu.c | 459 
 OvmfPkg/IoMmuDxe/IoMmuDxe.c|  53 +++
 10 files changed, 610 insertions(+)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 55f7e4269938..18544d7cfd73 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -815,6 +815,7 @@ [Components]
 !endif
 
   OvmfPkg/PlatformDxe/Platform.inf
+  OvmfPkg/IoMmuDxe/IoMmuDxe.inf
 
 !if $(SMM_REQUIRE) == TRUE
   OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 8dd6179893a9..1b3bf3517a9f 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -825,6 +825,7 @@ [Components.X64]
 
   OvmfPkg/PlatformDxe/Platform.inf
   OvmfPkg/AmdSevDxe/AmdSevDxe.inf
+  OvmfPkg/IoMmuDxe/IoMmuDxe.inf
 
 !if $(SMM_REQUIRE) == TRUE
   OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 6324941ca2ab..9fdabaf0eac4 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -823,6 +823,7 @@ [Components]
 
   OvmfPkg/PlatformDxe/Platform.inf
   OvmfPkg/AmdSevDxe/AmdSevDxe.inf
+  OvmfPkg/IoMmuDxe/IoMmuDxe.inf
 
 !if $(SMM_REQUIRE) == TRUE
   OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
diff --git a/OvmfPkg/OvmfPkgIa32.fdf b/OvmfPkg/OvmfPkgIa32.fdf
index 09c165882c3f..c6c60bf81413 100644
--- a/OvmfPkg/OvmfPkgIa32.fdf
+++ b/OvmfPkg/OvmfPkgIa32.fdf
@@ -351,6 +351,7 @@ [FV.DXEFV]
 INF  OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
 INF  OvmfPkg/VirtioGpuDxe/VirtioGpu.inf
 INF  OvmfPkg/PlatformDxe/Platform.inf
+INF  OvmfPkg/IoMmuDxe/IoMmuDxe.inf
 
 !if $(SMM_REQUIRE) == TRUE
 INF  OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.fdf b/OvmfPkg/OvmfPkgIa32X64.fdf
index 12871860d001..6bd574459bd0 100644
--- a/OvmfPkg/OvmfPkgIa32X64.fdf
+++ b/OvmfPkg/OvmfPkgIa32X64.fdf
@@ -353,6 +353,7 @@ [FV.DXEFV]
 INF  OvmfPkg/VirtioGpuDxe/VirtioGpu.inf
 INF  OvmfPkg/PlatformDxe/Platform.inf
 INF  OvmfPkg/AmdSevDxe/AmdSevDxe.inf
+INF  OvmfPkg/IoMmuDxe/IoMmuDxe.inf
 
 !if $(SMM_REQUIRE) == TRUE
 INF  OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf
index ae6e66a1c08d..c3d75ca9d72f 100644
--- a/OvmfPkg/OvmfPkgX64.fdf
+++ b/OvmfPkg/OvmfPkgX64.fdf
@@ -353,6 +353,7 @@ [FV.DXEFV]
 INF  OvmfPkg/VirtioGpuDxe/VirtioGpu.inf
 INF  OvmfPkg/PlatformDxe/Platform.inf
 INF  OvmfPkg/AmdSevDxe/AmdSevDxe.inf
+INF  OvmfPkg/IoMmuDxe/IoMmuDxe.inf
 
 !if $(SMM_REQUIRE) == TRUE
 INF  OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
diff --git a/OvmfPkg/IoMmuDxe/IoMmuDxe.inf b/OvmfPkg/IoMmuDxe/IoMmuDxe.inf
new file mode 100644
index ..b90dc80dfd37
--- /dev/null
+++ b/OvmfPkg/IoMmuDxe/IoMmuDxe.inf
@@ -0,0 +1,49 @@
+#/** @file
+#
+#  Driver provides the IOMMU protcol support for PciHostBridgeIo and others
+#  drivers.
+#
+#  Copyright (c) 2017, AMD Inc. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD
+#  License which accompanies this distribution.  The full text of the license 
may
+#  be found at http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION= 1.25
+  BASE_NAME

[edk2] [PATCH v7 02/17] OvmfPkg/ResetVector: Set C-bit when building initial page table

2017-06-22 Thread Brijesh Singh 
SEV guest VMs have the concept of private and shared memory. Private
memory is encrypted with the guest-specific key, while shared memory
may be encrypted with hypervisor key. Certain types of memory (namely
instruction pages and guest page tables) are always treated as private
memory by the hardware. The C-bit in PTE indicate whether the page is
private or shared. The C-bit position for the PTE can be obtained from
CPUID Fn8000_001F[EBX].

When SEV is active, the BIOS is encrypted by the Qemu launch sequence,
we must set the C-bit when building the page table.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Cc: Tom Lendacky 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
---
 OvmfPkg/ResetVector/Ia32/PageTables64.asm | 62 +++-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm 
b/OvmfPkg/ResetVector/Ia32/PageTables64.asm
index 6201cad1f5dc..db1590aedd42 100644
--- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm
+++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm
@@ -37,12 +37,66 @@ BITS32
PAGE_READ_WRITE + \
PAGE_PRESENT)
 
+; Check if Secure Encrypted Virtualization (SEV) feature is enabled
+;
+; If SEV is enabled then EAX will be at least 32
+; If SEV is disabled then EAX will be zero.
+;
+CheckSevFeature:
+; Check if we have a valid (0x8000_001F) CPUID leaf
+mov   eax, 0x8000
+cpuid
+
+; This check should fail on Intel or Non SEV AMD CPUs. In future if
+; Intel CPUs supports this CPUID leaf then we are guranteed to have exact
+; same bit definition.
+cmp   eax, 0x801f
+jlNoSev
+
+; Check for memory encryption feature:
+;  CPUID  Fn8000_001F[EAX] - Bit 1
+;
+mov   eax,  0x801f
+cpuid
+bteax, 1
+jnc   NoSev
+
+; Check if memory encryption is enabled
+;  MSR_0xC0010131 - Bit 0 (SEV enabled)
+mov   ecx, 0xc0010131
+rdmsr
+bteax, 0
+jnc   NoSev
+
+; Get pte bit position to enable memory encryption
+; CPUID Fn8000_001F[EBX] - Bits 5:0
+;
+mov   eax, ebx
+and   eax, 0x3f
+jmp   SevExit
+
+NoSev:
+xor   eax, eax
+
+SevExit:
+OneTimeCallRet CheckSevFeature
 
 ;
-; Modified:  EAX, ECX
+; Modified:  EAX, EBX, ECX, EDX
 ;
 SetCr3ForPageTables64:
 
+OneTimeCall   CheckSevFeature
+xor edx, edx
+testeax, eax
+jz  SevNotActive
+
+; If SEV is enabled, C-bit is always above 31
+sub eax, 32
+bts edx, eax
+
+SevNotActive:
+
 ;
 ; For OVMF, build some initial page tables at
 ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).
@@ -64,14 +118,19 @@ clearPageTablesMemoryLoop:
 ; Top level Page Directory Pointers (1 * 512GB entry)
 ;
 mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR
+mov dword[PT_ADDR (4)], edx
 
 ;
 ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
 ;
 mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR
+mov dword[PT_ADDR (0x1004)], edx
 mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR
+mov dword[PT_ADDR (0x100C)], edx
 mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR
+mov dword[PT_ADDR (0x1014)], edx
 mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR
+mov dword[PT_ADDR (0x101C)], edx
 
 ;
 ; Page Table Entries (2048 * 2MB entries => 4GB)
@@ -83,6 +142,7 @@ pageTableEntriesLoop:
 shl eax, 21
 add eax, PAGE_2M_PDE_ATTR
 mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax
+mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx
 looppageTableEntriesLoop
 
 ;
-- 
2.7.4

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[edk2] [PATCH v7 05/17] OvmfPkg/PlatformPei: Set memory encryption PCD when SEV is enabled

2017-06-22 Thread Brijesh Singh 
Secure Encrypted Virtualization (SEV) guest VMs have the concept of
private and shared memory. Private memory is encrypted with the
guest-specific key, while shared memory may be encrypted with hypervisor
key.  Certain types of memory (namely instruction pages and guest page
tables) are always treated as private memory by the hardware.
For data memory, SEV guest VMs can choose which pages they would like
to be private. The choice is done using the standard CPU page tables
using the C-bit. When building the initial page table we mark all the
memory as private.

The patch sets the memory encryption PCD. The PCD is consumed by the
following edk2 modules, which manipulate page tables:

- PEI phase modules: CapsulePei, DxeIplPeim, S3Resume2Pei.

CapsulePei is not used by OVMF. DxeIplPeim consumes the PCD at the
end of the PEI phase, when it builds the initial page tables for the
DXE core / DXE phase. S3Resume2Pei does not consume the PCD in its
entry point function, only when DxeIplPeim branches to the S3 resume
path at the end of the PEI phase, and calls S3Resume2Pei's
EFI_PEI_S3_RESUME2_PPI.S3RestoreConfig2() member function.

Therefore it is safe to set the PCD for these modules in PlatformPei.

- DXE phase modules: BootScriptExecutorDxe, CpuDxe, PiSmmCpuDxeSmm.

They are all dispatched after the PEI phase, so setting the PCD for
them in PlatformPei is safe. (BootScriptExecutorDxe is launched "for
real" in the PEI phase during S3 resume, but it caches the PCD into a
static variable when its entry point is originally invoked in DXE.)

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
---
 OvmfPkg/OvmfPkgIa32.dsc |  3 +
 OvmfPkg/OvmfPkgIa32X64.dsc  |  3 +
 OvmfPkg/OvmfPkgX64.dsc  |  3 +
 OvmfPkg/PlatformPei/PlatformPei.inf |  3 +
 OvmfPkg/PlatformPei/Platform.h  |  5 ++
 OvmfPkg/PlatformPei/AmdSev.c| 62 
 OvmfPkg/PlatformPei/Platform.c  |  1 +
 7 files changed, 80 insertions(+)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 98691c0a6d99..55f7e4269938 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -534,6 +534,9 @@ [PcdsDynamicDefault]
   gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|5
 
+  # Set memory encryption mask
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0
+
 !if $(SMM_REQUIRE) == TRUE
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x01
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 3b51513a4d95..dfc2534fc998 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -542,6 +542,9 @@ [PcdsDynamicDefault]
   gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|5
 
+  # Set memory encryption mask
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0
+
 !if $(SMM_REQUIRE) == TRUE
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x01
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index ebf07cd585dd..60e42794483b 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -541,6 +541,9 @@ [PcdsDynamicDefault]
   gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|5
 
+  # Set memory encryption mask
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0
+
 !if $(SMM_REQUIRE) == TRUE
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x01
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10
diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf 
b/OvmfPkg/PlatformPei/PlatformPei.inf
index a1e12c1fc7e2..16a8db7b0bd2 100644
--- a/OvmfPkg/PlatformPei/PlatformPei.inf
+++ b/OvmfPkg/PlatformPei/PlatformPei.inf
@@ -29,6 +29,7 @@ [Defines]
 #
 
 [Sources]
+  AmdSev.c
   Cmos.c
   FeatureControl.c
   Fv.c
@@ -60,6 +61,7 @@ [LibraryClasses]
   QemuFwCfgLib
   QemuFwCfgS3Lib
   MtrrLib
+  MemEncryptSevLib
   PcdLib
 
 [Pcd]
@@ -93,6 +95,7 @@ [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack
   gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask
   gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress
   gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds
diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h
index 18f42c3f0ea8..a7729b9df44b 100644
--- a/OvmfPkg/PlatformPei/Platform.h
+++ b/OvmfPkg/PlatformPei/Platform.h
@@ -88,6 +88,11 @@

[edk2] [PATCH v7 03/17] OvmfPkg: Update dsc to use IoLib from BaseIoLibIntrinsicSev.inf

2017-06-22 Thread Brijesh Singh 
When SEV is enabled then we must unroll the rep String I/O instructions.

The patch updates dsc file to use SEV version of IoLib inf. The main
difference between BaseIoLibIntrinsic.inf and BaseIoLibIntrinsicSev.inf
is, SEV version checks if its running under SEV enabled guest, If so
then it unroll the String I/O (REP INS/OUTS) otherwise fallbacks to
rep ins/outs.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
---
 OvmfPkg/OvmfPkgIa32.dsc| 2 +-
 OvmfPkg/OvmfPkgIa32X64.dsc | 2 +-
 OvmfPkg/OvmfPkgX64.dsc | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 0647f346257a..b5c874b65afc 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -122,7 +122,7 @@ [LibraryClasses]
   PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
   PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
   PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
-  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
   
OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
   SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf
   MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 1182b1858a7d..1d071cac2bef 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -127,7 +127,7 @@ [LibraryClasses]
   PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
   PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
   PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
-  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
   
OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
   SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf
   MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 636dfb1b5638..2bea75437788 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -127,7 +127,7 @@ [LibraryClasses]
   PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
   PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
   PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
-  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
   
OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
   SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf
   MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
-- 
2.7.4

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[edk2] [PATCH v7 08/17] OvmfPkg: Add PlatformHasIoMmuLib

2017-06-22 Thread Brijesh Singh 
Add the shorter-term library instance outlined in the previous patch to
OvmfPkg, so that we can imbue PciHostBridgeDxe with a protocol dependency
on gEdkiiIoMmuProtocolGuid OR gIoMmuAbsentProtocolGuid.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Suggested-by: Laszlo Ersek 
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
---
 OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.inf | 38 

 OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.c   | 33 
+
 2 files changed, 71 insertions(+)

diff --git a/OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.inf 
b/OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.inf
new file mode 100644
index ..f8151cfe2594
--- /dev/null
+++ b/OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.inf
@@ -0,0 +1,38 @@
+## @file
+# A hook-in library for MdeModulePkg/Bus/Pci/PciHostBridgeDxe.
+#
+#  Plugging this library instance into PciHostBridgeDxe makes
+#  PciHostBridgeDxe depend on the platform's dynamic decision whether
+#  to provide IOMMU implementation (usually through IoMmuDxe driver).
+#
+# Copyright (C) 2017, Red Hat, Inc.
+# Copyright (C) 2017, AMD, Inc.
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+##
+
+[Defines]
+  INF_VERSION= 1.25
+  BASE_NAME  = PlatformHasIoMmuLib
+  FILE_GUID  = 49b4b018-0558-448b-1e1a-12226342877d
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PlatformHasIoMmuLib|DXE_DRIVER
+  CONSTRUCTOR= PlatformHasIoMmuInitialize
+
+[Sources]
+  PlatformHasIoMmuLib.c
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OvmfPkg/OvmfPkg.dec
+
+[Depex]
+  gEdkiiIoMmuProtocolGuid OR gIoMmuAbsentProtocolGuid
diff --git a/OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.c 
b/OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.c
new file mode 100644
index ..a271be3e8aa3
--- /dev/null
+++ b/OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.c
@@ -0,0 +1,33 @@
+/** @file
+  A hook-in library for MdeModulePkg/Bus/Pci/PciHostBridgeDxe.
+
+  Plugging this library instance into PciHostBridgeDxe makes
+  PciHostBridgeDxe depend on the platform's dynamic decision whether
+  to provide IOMMU implementation (usually through IoMmuDxe driver).
+
+  Copyright (C) 2017, Red Hat, Inc.
+  Copyright (C) 2017, AMD, Inc.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include 
+
+RETURN_STATUS
+EFIAPI
+PlatformHasIoMmuInitialize (
+  VOID
+  )
+{
+  //
+  // Do nothing, just imbue PciHostBridgeDxe with a protocol dependency on
+  // gIoMmuAbsentProtocolGuid OR gEdkiiIoMmuProtocolGuid.
+  //
+  return RETURN_SUCCESS;
+}
-- 
2.7.4

___
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edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v7 04/17] OvmfPkg/BaseMemcryptSevLib: Add SEV helper library

2017-06-22 Thread Brijesh Singh 
Add Secure Encrypted Virtualization (SEV) helper library.
The library provides the routines to:
-  set or clear memory encryption bit for a given memory region.
-  query whether SEV is enabled.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Laszlo Ersek 
---
 OvmfPkg/OvmfPkgIa32.dsc |   1 +
 OvmfPkg/OvmfPkgIa32X64.dsc  |   1 +
 OvmfPkg/OvmfPkgX64.dsc  |   1 +
 OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf   |  50 +++
 OvmfPkg/Include/Library/MemEncryptSevLib.h  |  81 
 OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h| 184 
 OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c|  84 
 OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c |  90 
 OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c |  84 
 OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c| 439 

 10 files changed, 1015 insertions(+)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index b5c874b65afc..98691c0a6d99 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -145,6 +145,7 @@ [LibraryClasses]
   QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
   VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
   LoadLinuxLib|OvmfPkg/Library/LoadLinuxLib/LoadLinuxLib.inf
+  
MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf
 !if $(SMM_REQUIRE) == FALSE
   LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf
 !endif
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 1d071cac2bef..3b51513a4d95 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -150,6 +150,7 @@ [LibraryClasses]
   QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
   VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
   LoadLinuxLib|OvmfPkg/Library/LoadLinuxLib/LoadLinuxLib.inf
+  
MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf
 !if $(SMM_REQUIRE) == FALSE
   LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf
 !endif
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 2bea75437788..ebf07cd585dd 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -150,6 +150,7 @@ [LibraryClasses]
   QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
   VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
   LoadLinuxLib|OvmfPkg/Library/LoadLinuxLib/LoadLinuxLib.inf
+  
MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf
 !if $(SMM_REQUIRE) == FALSE
   LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf
 !endif
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf 
b/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf
new file mode 100644
index ..3cfd80a28c1d
--- /dev/null
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf
@@ -0,0 +1,50 @@
+## @file
+#  Library provides the helper functions for SEV guest
+#
+# Copyright (c) 2017 Advanced Micro Devices. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD
+#  License which accompanies this distribution. The full text of the license
+#  may be found at http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION= 1.25
+  BASE_NAME  = MemEncryptSevLib
+  FILE_GUID  = c1594631-3888-4be4-949f-9c630dbc842b
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = MemEncryptSevLib|PEIM DXE_DRIVER 
DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+# VALID_ARCHITECTURES   = IA32 X64
+#
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OvmfPkg/OvmfPkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[Sources.X64]
+  MemEncryptSevLibInternal.c
+  X64/MemEncryptSevLib.c
+  X64/VirtualMemory.c
+
+[Sources.IA32]
+  MemEncryptSevLibInternal.c
+  Ia32/MemEncryptSevLib.c
+
+[LibraryClasses]
+  BaseLib
+  CpuLib
+  CacheMaintenanceLib
+  DebugLib
+  MemoryAllocationLib
diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h 
b/OvmfPkg/Include/Library/MemEncryptSevLib.h
new file mode 100644
index ..b6753762423e
--- /dev/null
+++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h
@@ -0,0 +1,81 @@
+/** @file
+
+  Define Secure Encrypted Virtualization

[edk2] [PATCH v7 01/17] UefiCpuPkg: Define AMD Memory Encryption specific CPUID and MSR

2017-06-22 Thread Brijesh Singh 
The patch defines AMD's Memory Encryption Information CPUID leaf and SEV
status MSR. The complete description for CPUID leaf is available in APM
volume 2, Section 15.34.

Cc: Jordan Justen 
Cc: Laszlo Ersek 
Cc: Jeff Fan 
Cc: Liming Gao 
Cc: Leo Duran 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh 
Reviewed-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Amd/Cpuid.h| 162 
 UefiCpuPkg/Include/Register/Amd/Fam17Msr.h |  62 
 UefiCpuPkg/Include/Register/Amd/Msr.h  |  29 
 3 files changed, 253 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Amd/Cpuid.h 
b/UefiCpuPkg/Include/Register/Amd/Cpuid.h
new file mode 100644
index ..5cd42667dc46
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Amd/Cpuid.h
@@ -0,0 +1,162 @@
+/** @file
+  CPUID leaf definitions.
+
+  Provides defines for CPUID leaf indexes.  Data structures are provided for
+  registers returned by a CPUID leaf that contain one or more bit fields.
+  If a register returned is a single 32-bit value, then a data structure is
+  not provided for that register.
+
+  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
+
+**/
+
+#ifndef __AMD_CPUID_H__
+#define __AMD_CPUID_H__
+
+/**
+
+  Memory Encryption Information
+
+  @param   EAX  CPUID_MEMORY_ENCRYPTION_INFO (0x801F)
+
+  @retval  EAX  Returns the memory encryption feature support status.
+  @retval  EBX  If memory encryption feature is present then return
+the page table bit number used to enable memory encryption 
support
+and reducing of physical address space in bits.
+  @retval  ECX  Returns number of encrypted guest supported simultaneosuly.
+  @retval  EDX  Returns minimum SEV enabled and SEV disbled ASID..
+
+  Example usage
+  @code
+  UINT32 Eax;
+  UINT32 Ebx;
+  UINT32 Ecx;
+  UINT32 Edx;
+
+  AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, , , , );
+  @endcode
+**/
+
+#define CPUID_MEMORY_ENCRYPTION_INFO 0x801F
+
+/**
+  CPUID Memory Encryption support information EAX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0] Secure Memory Encryption (Sme) Support
+///
+UINT32  SmeBit:1;
+
+///
+/// [Bit 1] Secure Encrypted Virtualization (Sev) Support
+///
+UINT32  SevBit:1;
+
+///
+/// [Bit 2] Page flush MSR support
+///
+UINT32  PageFlushMsrBit:1;
+
+///
+/// [Bit 3] Encrypted state support
+///
+UINT32  SevEsBit:1;
+
+///
+/// [Bit 4:31] Reserved
+///
+UINT32  ReservedBits:28;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EAX;
+
+/**
+  CPUID Memory Encryption support information EBX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0:5] Page table bit number used to enable memory encryption
+///
+UINT32  PtePosBits:6;
+
+///
+/// [Bit 6:11] Reduction of system physical address space bits when memory 
encryption is enabled
+///
+UINT32  ReducedPhysBits:5;
+
+///
+/// [Bit 12:31] Reserved
+///
+UINT32  ReservedBits:21;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EBX;
+
+/**
+  CPUID Memory Encryption support information ECX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0:31] Number of encrypted guest supported simultaneously
+///
+UINT32  NumGuests;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_ECX;
+
+/**
+  CPUID Memory Encryption support information EDX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0:31] Minimum SEV enabled, SEV-ES disabled ASID
+///
+UINT32  MinAsid;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EDX;
+
+#endif
diff --git

[edk2] [PATCH v7 00/17] x86: Secure Encrypted Virtualization (AMD)

2017-06-22 Thread Brijesh Singh 
The patch series provides support for AMD's new Secure Encrypted
Virtualization (SEV) feature.

SEV is an extension to the AMD-V architecture which supports running
multiple VMs under the control of a hypervisor. The SEV feature allows
the memory contents of a virtual machine (VM) to be transparently encrypted
with a key unique to the guest VM. The memory controller contains a
high performance encryption engine which can be programmed with multiple
keys for use by a different VMs in the system. The programming and
management of these keys is handled by the AMD Secure Processor firmware
which exposes a commands for these tasks.

SEV guest VMs have the concept of private and shared memory.  Private memory is
encrypted with the guest-specific key, while shared memory may be encrypted
with hypervisor key.  Certain types of memory (namely instruction pages and
guest page tables) are always treated as private memory by the hardware.
For data memory, SEV guest VMs can choose which pages they would like to be
private. The choice is done using the standard CPU page tables using the C-bit,
and is fully controlled by the guest. Due to security reasons all the DMA
operations inside the  guest must be performed on shared pages (C-bit clear).
Note that since C-bit is only controllable by the guest OS when it is operating
in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware forces the
C-bit to a 1.

The following links provide additional details:

AMD Memory Encryption whitepaper:
http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_Memory_Encryption_Whitepaper_v7-Public.pdf

AMD64 Architecture Programmer's Manual:
http://support.amd.com/TechDocs/24593.pdf
SME is section 7.10
SEV is section 15.34

Secure Encrypted Virutualization Key Management:
http://support.amd.com/TechDocs/55766_SEV-KM API_Specification.pdf

KVM Forum Presentation:
http://www.linux-kvm.org/images/7/74/02x08A-Thomas_Lendacky-AMDs_Virtualizatoin_Memory_Encryption_Technology.pdf

[1] http://marc.info/?l=linux-mm=148846752931115=2

---

Patch series is based on commit 9ba8baae15ca (BaseTools/tools_def: AARCH64: 
disable LTO type mismatch warnings)

https://github.com/codomania/edk2/tree/v7

The patch series is tested with OvmfIa32.dsc, OvmfIa32X64.dsc and OvmfX64.dsc.
Since memory encryption bit is not accessiable when processor is in 32-bit mode
hence any DMA access in this mode would cause assert. I have also tested the
suspend and resume path, it seems to be working fine. I still need to work to
finish adding the SEV Dma support in QemuFwCfgS3Lib package (see TODO).

Changes since v6:
 - Keep Red Hat copright in PlatformHasIoMmuLib
 - PageTable64.asm: Do not use stack operations (push and pop instruction)

Changes since v5:
 - add placeholder gIoMmuAbsentProtocolGuid
 - add PlatformHasIoMmuLib
 - fix indentation

Changes since v4:
 - decouple IoMmu protocol implementation from AmdSevDxe into a seperate
   IoMmuDxe driver. And introduce a placeholder protocol to provide the
   dependency support for the dependent modules.
 - update debug messages to use gEfiCallerBaseName where applicable.
 - fix QemuFwCfgSecLib build errors and simplify SEV support
 - update QemuFwCfgDxeLib to assert when failed to locate IOMMU
 - update comments "host buffer" to " host buffer"

Changes since v3:
 - update AmdSevDxe driver to produce IOMMU protocol
 - remove BmDmaLib dependency
 - update QemuFwCfgLib to use IOMMU protocol to allocate SEV DMA buffer

Changes since v2:
 - move memory encryption CPUID and MSR definition into UefiCpuPkg
 - fix the argument order for SUB instruction in ResetVector and add more
   comments
 - update PlatformPei to use BaseMemEncryptSevLib
 - break the overlong comment lines to 79 chars
 - variable aligment and other formating fixes
 - split the SEV DMA support patch for QemuFwCfgLib into multiple patches as
   recommended by Laszlo
 - add AmdSevDxe driver which runs very early in DXE phase and clear the C-bit
   from MMIO memory region
 - drop 'QemuVideoDxe: Clear C-bit from framebuffer' patch since AmdSevDxe
   driver takes care of clearing the C-bit from MMIO region
 - Verified that Qemu PFLASH works fine with SEV guest, Found a KVM driver issue
   which was causing #PF when PFLASH was enabled. I have submitted patch to
   fix it in upstream http://marc.info/?l=kvm=149304930814202=2

Changes since v1:
 - bug fixes in OvmfPkg/ResetVector (pointed by Tom Lendacky)
 - add SEV CPUID and MSR register definition in standard include file
 - remove the MemEncryptLib dependency from PlatformPei. Move AmdSevInitialize()
   implementation in local file inside the PlatformPei package
 - rename MemCryptSevLib to MemEncryptSevLib and add functions to set or
   clear memory encryption attribute on memory region
 - integerate SEV support in BmDmaLib
 - split QemuFwCfgDxePei.c into QemuFwCfgDxe.c and QemuFwCfgPei.c to
   allow building seperate QemuFwCfgLib for Dxe and Pei phase
   (recommended by Laszlo Ersek)
 -

[edk2] [PATCH v3 07/10] BaseTools: Tools change to support PI v1.5 Specification.

2017-06-22 Thread Supreeth Venkatesh 
This patch verifies SMM_CORE_STANDALONE module compatibility with PI
specification version.
Also, it registers SMM_STANDALONE/SMM_CORE_STANDALONE modules with
FdfParser class and provides mapping between SMM_STANDALONE and
SMM_CORE_STANDALONE module type in FDF with
EFI_FV_FILETYPE_SMM_STANDALONE and EFI_FV_FILETYPE_SMM_CORE_STANDALONE file 
types
in GenFfs.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
Signed-off-by: Supreeth Venkatesh 
---
 BaseTools/Source/Python/GenFds/FdfParser.py   | 4 ++--
 BaseTools/Source/Python/GenFds/Ffs.py | 8 ++--
 BaseTools/Source/Python/GenFds/FfsInfStatement.py | 3 +++
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/BaseTools/Source/Python/GenFds/FdfParser.py 
b/BaseTools/Source/Python/GenFds/FdfParser.py
index a1825ba..4f1efc1 100644
--- a/BaseTools/Source/Python/GenFds/FdfParser.py
+++ b/BaseTools/Source/Python/GenFds/FdfParser.py
@@ -3672,7 +3672,7 @@ class FdfParser:
  "DXE_SMM_DRIVER", "DXE_RUNTIME_DRIVER", \
  "UEFI_DRIVER", "UEFI_APPLICATION", 
"USER_DEFINED", "DEFAULT", "BASE", \
  "SECURITY_CORE", "COMBINED_PEIM_DRIVER", 
"PIC_PEIM", "RELOCATABLE_PEIM", \
- "PE32_PEIM", "BS_DRIVER", "RT_DRIVER", 
"SAL_RT_DRIVER", "APPLICATION", "ACPITABLE", "SMM_CORE"):
+"PE32_PEIM", "BS_DRIVER", "RT_DRIVER", 
"SAL_RT_DRIVER", "APPLICATION", "ACPITABLE", "SMM_CORE", "SMM_STANDALONE", 
"SMM_CORE_STANDALONE"):
 raise Warning("Unknown Module type '%s'" % self.__Token, 
self.FileName, self.CurrentLineNumber)
 return self.__Token
 
@@ -3716,7 +3716,7 @@ class FdfParser:
 
 Type = self.__Token.strip().upper()
 if Type not in ("RAW", "FREEFORM", "SEC", "PEI_CORE", "PEIM",\
- "PEI_DXE_COMBO", "DRIVER", "DXE_CORE", 
"APPLICATION", "FV_IMAGE", "SMM", "SMM_CORE"):
+ "PEI_DXE_COMBO", "DRIVER", "DXE_CORE", 
"APPLICATION", "FV_IMAGE", "SMM", "SMM_CORE", "SMM_STANDALONE", 
"SMM_CORE_STANDALONE"):
 raise Warning("Unknown FV type '%s'" % self.__Token, 
self.FileName, self.CurrentLineNumber)
 
 if not self.__IsToken("="):
diff --git a/BaseTools/Source/Python/GenFds/Ffs.py 
b/BaseTools/Source/Python/GenFds/Ffs.py
index c8c5a6e..b20804f 100644
--- a/BaseTools/Source/Python/GenFds/Ffs.py
+++ b/BaseTools/Source/Python/GenFds/Ffs.py
@@ -34,7 +34,9 @@ class Ffs(FDClassObject):
 'DXE_RUNTIME_DRIVER': 'EFI_FV_FILETYPE_DRIVER',
 'UEFI_DRIVER'   : 'EFI_FV_FILETYPE_DRIVER',
 'UEFI_APPLICATION'  : 'EFI_FV_FILETYPE_APPLICATION',
-'SMM_CORE'  : 'EFI_FV_FILETYPE_SMM_CORE'
+'SMM_CORE'  : 'EFI_FV_FILETYPE_SMM_CORE',
+'SMM_STANDALONE': 'EFI_FV_FILETYPE_SMM_STANDALONE',
+'SMM_CORE_STANDALONE' : 'EFI_FV_FILETYPE_SMM_CORE_STANDALONE'
 }
 
 # mapping between FILE type in FDF and file type for GenFfs
@@ -50,7 +52,9 @@ class Ffs(FDClassObject):
 'RAW'   : 'EFI_FV_FILETYPE_RAW',
 'PEI_DXE_COMBO' : 'EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER',
 'SMM'   : 'EFI_FV_FILETYPE_SMM',
-'SMM_CORE'  : 'EFI_FV_FILETYPE_SMM_CORE'
+'SMM_CORE'  : 'EFI_FV_FILETYPE_SMM_CORE',
+'SMM_STANDALONE': 'EFI_FV_FILETYPE_SMM_STANDALONE',
+'SMM_CORE_STANDALONE' : 'EFI_FV_FILETYPE_SMM_CORE_STANDALONE'
 }
 
 # mapping between section type in FDF and file suffix
diff --git a/BaseTools/Source/Python/GenFds/FfsInfStatement.py 
b/BaseTools/Source/Python/GenFds/FfsInfStatement.py
index e9517a4..1f0250f 100644
--- a/BaseTools/Source/Python/GenFds/FfsInfStatement.py
+++ b/BaseTools/Source/Python/GenFds/FfsInfStatement.py
@@ -224,6 +224,9 @@ class FfsInfStatement(FfsInfStatementClassObject):
 if self.ModuleType == 'SMM_CORE' and int(self.PiSpecVersion, 16) < 
0x0001000A:
 EdkLogger.error("GenFds", FORMAT_NOT_SUPPORTED, "SMM_CORE module 
type can't be used in the module with PI_SPECIFICATION_VERSION less than 
0x0001000A", File=self.InfFileName)  
 
+if self.ModuleType == 'SMM_CORE_STANDALONE' and 
int(self.PiSpecVersion, 16) < 0x00010032:
+EdkLogger.error("GenFds", FORMAT_NOT_SUPPORTED, 
"SMM_CORE_STANDALONE module type can't be used in the module with 
PI_SPECIFICATION_VERSION less than 0x00010032", File=self.InfFileName)
+
 if Inf._Defs != None and len(Inf._Defs) > 0:
 self.OptRomDefs.update(Inf._Defs)
 
-- 
2.7.4

___
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edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v3 09/10] BaseTools: Tools change to support PI v1.5 Specification.

2017-06-22 Thread Supreeth Venkatesh 
This patch checks SUP_MODULE_SMM_CORE_STANDALONE and
SUP_MODULE_SMM_STANDALONE module compatibility with PI specification
version.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
Signed-off-by: Supreeth Venkatesh 
---
 BaseTools/Source/Python/Workspace/WorkspaceDatabase.py | 5 +
 1 file changed, 5 insertions(+)

diff --git a/BaseTools/Source/Python/Workspace/WorkspaceDatabase.py 
b/BaseTools/Source/Python/Workspace/WorkspaceDatabase.py
index c1af5c7..599c6df 100644
--- a/BaseTools/Source/Python/Workspace/WorkspaceDatabase.py
+++ b/BaseTools/Source/Python/Workspace/WorkspaceDatabase.py
@@ -1977,6 +1977,11 @@ class InfBuildData(ModuleBuildClassObject):
 if (self._Specification == None) or (not 
'PI_SPECIFICATION_VERSION' in self._Specification) or 
(int(self._Specification['PI_SPECIFICATION_VERSION'], 16) < 0x0001000A):
 if self._ModuleType == SUP_MODULE_SMM_CORE:
 EdkLogger.error("build", FORMAT_NOT_SUPPORTED, "SMM_CORE 
module type can't be used in the module with PI_SPECIFICATION_VERSION less than 
0x0001000A", File=self.MetaFile)
+if (self._Specification == None) or (not 
'PI_SPECIFICATION_VERSION' in self._Specification) or 
(int(self._Specification['PI_SPECIFICATION_VERSION'], 16) < 0x00010032):
+if self._ModuleType == SUP_MODULE_SMM_CORE_STANDALONE:
+EdkLogger.error("build", FORMAT_NOT_SUPPORTED, 
"SMM_CORE_STANDALONE module type can't be used in the module with 
PI_SPECIFICATION_VERSION less than 0x00010032", File=self.MetaFile)
+if self._ModuleType == SUP_MODULE_SMM_STANDALONE:
+EdkLogger.error("build", FORMAT_NOT_SUPPORTED, 
"SMM_STANDALONE module type can't be used in the module with 
PI_SPECIFICATION_VERSION less than 0x00010032", File=self.MetaFile)
 if self._Defs and 'PCI_DEVICE_ID' in self._Defs and 
'PCI_VENDOR_ID' in self._Defs \
and 'PCI_CLASS_CODE' in self._Defs and 'PCI_REVISION' in 
self._Defs:
 self._BuildType = 'UEFI_OPTIONROM'
-- 
2.7.4

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[edk2] [PATCH v3 10/10] BaseTools: Tools change to support PI v1.5 Specification.

2017-06-22 Thread Supreeth Venkatesh 
This patch registers SMM_STANDALONE and SMM_CORE_STANDALONE with Ffs class.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
Signed-off-by: Supreeth Venkatesh 
---
 BaseTools/Source/Python/Eot/FvImage.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/BaseTools/Source/Python/Eot/FvImage.py 
b/BaseTools/Source/Python/Eot/FvImage.py
index f2a9bc6..32eabfe 100644
--- a/BaseTools/Source/Python/Eot/FvImage.py
+++ b/BaseTools/Source/Python/Eot/FvImage.py
@@ -999,6 +999,8 @@ class Ffs(Image):
 0x0B:   "FIRMWARE_VOLUME_IMAGE",
 0x0C:   "COMBINED_SMM_DXE",
 0x0D:   "SMM_CORE",
+0x0E:   "SMM_STANDALONE",
+0x0F:   "SMM_CORE_STANDALONE",
 0xc0:   "OEM_MIN",
 0xdf:   "OEM_MAX",
 0xe0:   "DEBUG_MIN",
-- 
2.7.4

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[edk2] [PATCH v3 05/10] BaseTools: Tools change to support PI v1.5 Specification.

2017-06-22 Thread Supreeth Venkatesh 
This patch adds support for FdfParser tool to parse SMM_STANDALONE and
SMM_CORE_STANDALONE modules.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
Signed-off-by: Supreeth Venkatesh 
---
 BaseTools/Source/Python/Common/FdfParserLite.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/BaseTools/Source/Python/Common/FdfParserLite.py 
b/BaseTools/Source/Python/Common/FdfParserLite.py
index a8cce26..4f3b159 100644
--- a/BaseTools/Source/Python/Common/FdfParserLite.py
+++ b/BaseTools/Source/Python/Common/FdfParserLite.py
@@ -2823,7 +2823,7 @@ class FdfParser(object):
  "DXE_SMM_DRIVER", "DXE_RUNTIME_DRIVER", \
  "UEFI_DRIVER", "UEFI_APPLICATION", 
"USER_DEFINED", "DEFAULT", "BASE", \
  "SECURITY_CORE", "COMBINED_PEIM_DRIVER", 
"PIC_PEIM", "RELOCATABLE_PEIM", \
- "PE32_PEIM", "BS_DRIVER", "RT_DRIVER", 
"SAL_RT_DRIVER", "APPLICATION", "ACPITABLE", "SMM_CORE"):
+ "PE32_PEIM", "BS_DRIVER", "RT_DRIVER", 
"SAL_RT_DRIVER", "APPLICATION", "ACPITABLE", "SMM_CORE", "SMM_STANDALONE", 
"SMM_CORE_STANDALONE"):
 raise Warning("Unknown Module type At line ", self.FileName, 
self.CurrentLineNumber)
 return self.__Token
 
@@ -2867,7 +2867,7 @@ class FdfParser(object):
 
 Type = self.__Token.strip().upper()
 if Type not in ("RAW", "FREEFORM", "SEC", "PEI_CORE", "PEIM",\
- "PEI_DXE_COMBO", "DRIVER", "DXE_CORE", 
"APPLICATION", "FV_IMAGE", "SMM", "SMM_CORE"):
+ "PEI_DXE_COMBO", "DRIVER", "DXE_CORE", 
"APPLICATION", "FV_IMAGE", "SMM", "SMM_CORE", "SMM_STANDALONE"):
 raise Warning("Unknown FV type At line ", self.FileName, 
self.CurrentLineNumber)
 
 if not self.__IsToken("="):
-- 
2.7.4

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[edk2] [PATCH v3 01/10] BaseTools: Tools change to support PI v1.5 Specification.

2017-06-22 Thread Supreeth Venkatesh 
PI specification v1.5 defines new firmware volume file types.

This patch adds the new file type EFI_FV_FILETYPE_SMM_STANDALONE and
EFI_FV_FILETYPE_SMM_CORE_STANDALONE in GenFfs tool.
*_SMM_* regex instead of *_MM_* is used to preserve
backwards compatibility.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
Signed-off-by: Supreeth Venkatesh 
---
 BaseTools/Source/C/GenFfs/GenFfs.c | 8 ++--
 BaseTools/Source/C/Include/Common/PiFirmwareFile.h | 2 ++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/BaseTools/Source/C/GenFfs/GenFfs.c 
b/BaseTools/Source/C/GenFfs/GenFfs.c
index c5d657b..c394b8b 100644
--- a/BaseTools/Source/C/GenFfs/GenFfs.c
+++ b/BaseTools/Source/C/GenFfs/GenFfs.c
@@ -43,8 +43,10 @@ STATIC CHAR8 *mFfsFileType[] = {
   "EFI_FV_FILETYPE_SMM",  // 0x0A
   "EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE",// 0x0B
   "EFI_FV_FILETYPE_COMBINED_SMM_DXE", // 0x0C
-  "EFI_FV_FILETYPE_SMM_CORE"  // 0x0D
- };
+  "EFI_FV_FILETYPE_SMM_CORE", // 0x0D
+  "EFI_FV_FILETYPE_SMM_STANDALONE",   // 0x0E
+  "EFI_FV_FILETYPE_SMM_CORE_STANDALONE"   // 0x0F
+};
 
 STATIC CHAR8 *mAlignName[] = {
   "1", "2", "4", "8", "16", "32", "64", "128", "256", "512",
@@ -130,6 +132,8 @@ Returns:
 EFI_FV_FILETYPE_DRIVER, EFI_FV_FILETYPE_APPLICATION,\n\
 EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER,\n\
 EFI_FV_FILETYPE_SMM, EFI_FV_FILETYPE_SMM_CORE,\n\
+EFI_FV_FILETYPE_SMM_STANDALONE,\n\
+EFI_FV_FILETYPE_SMM_CORE_STANDALONE,\n\
 EFI_FV_FILETYPE_COMBINED_SMM_DXE, \n\
 EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE.\n");
   fprintf (stdout, "  -g FileGuid, --fileguid FileGuid\n\
diff --git a/BaseTools/Source/C/Include/Common/PiFirmwareFile.h 
b/BaseTools/Source/C/Include/Common/PiFirmwareFile.h
index 2984860..8b40ec2 100644
--- a/BaseTools/Source/C/Include/Common/PiFirmwareFile.h
+++ b/BaseTools/Source/C/Include/Common/PiFirmwareFile.h
@@ -52,6 +52,8 @@ typedef UINT8 EFI_FFS_FILE_STATE;
 #define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B
 #define EFI_FV_FILETYPE_COMBINED_SMM_DXE  0x0C
 #define EFI_FV_FILETYPE_SMM_CORE  0x0D
+#define EFI_FV_FILETYPE_SMM_STANDALONE0x0E
+#define EFI_FV_FILETYPE_SMM_CORE_STANDALONE   0x0F
 #define EFI_FV_FILETYPE_OEM_MIN   0xc0
 #define EFI_FV_FILETYPE_OEM_MAX   0xdf
 #define EFI_FV_FILETYPE_DEBUG_MIN 0xe0
-- 
2.7.4

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[edk2] [PATCH v3 08/10] BaseTools: Tools change to support PI v1.5 Specification.

2017-06-22 Thread Supreeth Venkatesh 
This patch registers SMM_STANDALONE and SMM_CORE_STANDALONE module type
with python build tools.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
Signed-off-by: Supreeth Venkatesh 
---
 BaseTools/Source/Python/build/BuildReport.py | 4 +++-
 BaseTools/Source/Python/build/build.py   | 2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/BaseTools/Source/Python/build/BuildReport.py 
b/BaseTools/Source/Python/build/BuildReport.py
index 91d1e93..409aa54 100644
--- a/BaseTools/Source/Python/build/BuildReport.py
+++ b/BaseTools/Source/Python/build/BuildReport.py
@@ -123,6 +123,8 @@ gDriverTypeMap = {
   'UEFI_APPLICATION'  : '0x9 (APPLICATION)',
   'SMM_CORE'  : '0xD (SMM_CORE)',
   'SMM_DRIVER': '0xA (SMM)', # Extension of module type to support PI 
1.1 SMM drivers
+  'SMM_STANDALONE': '0xE (SMM_STANDALONE)',
+  'SMM_CORE_STANDALONE' : '0xF (SMM_CORE_STANDALONE)',
   }
 
 ## The look up table of the supported opcode in the dependency expression 
binaries
@@ -374,7 +376,7 @@ class DepexReport(object):
 if not ModuleType:
 ModuleType = gComponentType2ModuleType.get(M.ComponentType, "")
 
-if ModuleType in ["SEC", "PEI_CORE", "DXE_CORE", "SMM_CORE", 
"UEFI_APPLICATION"]:
+if ModuleType in ["SEC", "PEI_CORE", "DXE_CORE", "SMM_CORE", 
"SMM_CORE_STANDALONE", "UEFI_APPLICATION"]:
 return
   
 for Source in M.SourceFileList:
diff --git a/BaseTools/Source/Python/build/build.py 
b/BaseTools/Source/Python/build/build.py
index fd94ae6..c67ccb7 100644
--- a/BaseTools/Source/Python/build/build.py
+++ b/BaseTools/Source/Python/build/build.py
@@ -1499,7 +1499,7 @@ class Build():
 if IsIpfPlatform and ImageInfo.Image.Size % 0x2000 != 
0:
 ImageInfo.Image.Size = (ImageInfo.Image.Size / 
0x2000 + 1) * 0x2000
 RtSize += ImageInfo.Image.Size
-elif Module.ModuleType in ['SMM_CORE', 'DXE_SMM_DRIVER']:
+elif Module.ModuleType in ['SMM_CORE', 'DXE_SMM_DRIVER', 
'SMM_STANDALONE', 'SMM_CORE_STANDALONE']:
 SmmModuleList[Module.MetaFile] = ImageInfo
 SmmSize += ImageInfo.Image.Size
 if Module.ModuleType == 'DXE_SMM_DRIVER':
-- 
2.7.4

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[edk2] [PATCH v3 06/10] BaseTools: Tools change to support PI v1.5 Specification.

2017-06-22 Thread Supreeth Venkatesh 
This patch registers SMM_STANDALONE and SMM_CORE_STANDALONE module types
with CommonClass and PackageIncludePkgHeaderClass in CommonDataClass.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
Signed-off-by: Supreeth Venkatesh 
---
 BaseTools/Source/Python/CommonDataClass/CommonClass.py  | 6 +++---
 BaseTools/Source/Python/CommonDataClass/PackageClass.py | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/BaseTools/Source/Python/CommonDataClass/CommonClass.py 
b/BaseTools/Source/Python/CommonDataClass/CommonClass.py
index 5e908a6..c520799 100644
--- a/BaseTools/Source/Python/CommonDataClass/CommonClass.py
+++ b/BaseTools/Source/Python/CommonDataClass/CommonClass.py
@@ -174,7 +174,7 @@ class IncludeStatementClass(object):
 # @var GuidTypeList:   To store value for GuidTypeList, selection scope is in 
below list
 #  DATA_HUB_RECORD | EFI_EVENT | 
EFI_SYSTEM_CONFIGURATION_TABLE | EFI_VARIABLE | GUID | HII_PACKAGE_LIST | HOB | 
TOKEN_SPACE_GUID
 # @var SupModuleList:  To store value for SupModuleList, selection scope is in 
below list
-#  BASE | SEC | PEI_CORE | PEIM | DXE_CORE | DXE_DRIVER | 
DXE_RUNTIME_DRIVER | DXE_SAL_DRIVER | DXE_SMM_DRIVER | UEFI_DRIVER | 
UEFI_APPLICATION | USER_DEFINED | SMM_CORE
+#  BASE | SEC | PEI_CORE | PEIM | DXE_CORE | DXE_DRIVER | 
DXE_RUNTIME_DRIVER | DXE_SAL_DRIVER | DXE_SMM_DRIVER | UEFI_DRIVER | 
UEFI_APPLICATION | USER_DEFINED | SMM_CORE | SMM_STANDALONE | 
SMM_CORE_STANDALONE
 #
 class GuidProtocolPpiCommonClass(CommonClass):
 def __init__(self):
@@ -202,7 +202,7 @@ class GuidProtocolPpiCommonClass(CommonClass):
 # @var RecommendedInstance: To store value for RecommendedInstance, 
selection scope is in below list
 #   DATA_HUB_RECORD | EFI_EVENT | 
EFI_SYSTEM_CONFIGURATION_TABLE | EFI_VARIABLE | GUID | HII_PACKAGE_LIST | HOB | 
TOKEN_SPACE_GUID
 # @var SupModuleList:   To store value for SupModuleList, 
selection scope is in below list
-#   BASE | SEC | PEI_CORE | PEIM | DXE_CORE | 
DXE_DRIVER | DXE_RUNTIME_DRIVER | DXE_SAL_DRIVER | DXE_SMM_DRIVER | UEFI_DRIVER 
| UEFI_APPLICATION | USER_DEFINED | SMM_CORE
+#   BASE | SEC | PEI_CORE | PEIM | DXE_CORE | 
DXE_DRIVER | DXE_RUNTIME_DRIVER | DXE_SAL_DRIVER | DXE_SMM_DRIVER | UEFI_DRIVER 
| UEFI_APPLICATION | USER_DEFINED | SMM_CORE | SMM_STANDALONE | 
SMM_CORE_STANDALONE
 #
 class LibraryClassClass(CommonClass, DefineClass):
 def __init__(self):
@@ -354,7 +354,7 @@ class PcdErrorClass(object):
 # @var SkuInfoList:To store value for SkuInfoList
 #  It is a set structure as { [SkuIdName] : 
SkuInfoClass } 
 # @var SupModuleList:  To store value for SupModuleList, selection 
scope is in below list
-#  BASE | SEC | PEI_CORE | PEIM | DXE_CORE | 
DXE_DRIVER | DXE_RUNTIME_DRIVER | DXE_SAL_DRIVER | DXE_SMM_DRIVER | UEFI_DRIVER 
| UEFI_APPLICATION | USER_DEFINED | SMM_CORE
+#  BASE | SEC | PEI_CORE | PEIM | DXE_CORE | 
DXE_DRIVER | DXE_RUNTIME_DRIVER | DXE_SAL_DRIVER | DXE_SMM_DRIVER | UEFI_DRIVER 
| UEFI_APPLICATION | USER_DEFINED | SMM_CORE | SMM_STANDALONE | 
SMM_CORE_STANDALONE
 #
 class PcdClass(CommonClass):
 def __init__(self, CName = '', Token = '', TokenSpaceGuidCName = '', 
DatumType = '', MaxDatumSize = '', DefaultValue = '', ItemType = '', ValidUsage 
= None, SkuInfoList = None, SupModuleList = None):
diff --git a/BaseTools/Source/Python/CommonDataClass/PackageClass.py 
b/BaseTools/Source/Python/CommonDataClass/PackageClass.py
index 82e7394..b63e05d 100644
--- a/BaseTools/Source/Python/CommonDataClass/PackageClass.py
+++ b/BaseTools/Source/Python/CommonDataClass/PackageClass.py
@@ -62,7 +62,7 @@ class PackageIndustryStdHeaderClass(CommonClass):
 #
 # @var IncludeHeader:  To store value for IncludeHeader
 # @var ModuleType: To store value for ModuleType, it is a set structure as
-#  BASE | SEC | PEI_CORE | PEIM | DXE_CORE | DXE_DRIVER | 
DXE_RUNTIME_DRIVER | DXE_SAL_DRIVER | DXE_SMM_DRIVER | TOOL | UEFI_DRIVER | 
UEFI_APPLICATION | USER_DEFINED | SMM_CORE
+#  BASE | SEC | PEI_CORE | PEIM | DXE_CORE | DXE_DRIVER | 
DXE_RUNTIME_DRIVER | DXE_SAL_DRIVER | DXE_SMM_DRIVER | TOOL | UEFI_DRIVER | 
UEFI_APPLICATION | USER_DEFINED | SMM_CORE | SMM_STANDALONE | 
SMM_CORE_STANDALONE
 #
 class PackageIncludePkgHeaderClass(object):
 def __init__(self):
-- 
2.7.4

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[edk2] [PATCH v3 04/10] BaseTools: Tools change to support PI v1.5 Specification.

2017-06-22 Thread Supreeth Venkatesh 
This patch adds SUP_MODULE_SMM_STANDALONE and
SUP_MODULE_SMM_CORE_STANDALONE data types and includes it in
SUP_MODULE_LIST.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
Signed-off-by: Supreeth Venkatesh 
---
 BaseTools/Source/Python/Common/DataType.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/BaseTools/Source/Python/Common/DataType.py 
b/BaseTools/Source/Python/Common/DataType.py
index 6edc0c0..ab64553 100644
--- a/BaseTools/Source/Python/Common/DataType.py
+++ b/BaseTools/Source/Python/Common/DataType.py
@@ -70,10 +70,12 @@ SUP_MODULE_UEFI_DRIVER = 'UEFI_DRIVER'
 SUP_MODULE_UEFI_APPLICATION = 'UEFI_APPLICATION'
 SUP_MODULE_USER_DEFINED = 'USER_DEFINED'
 SUP_MODULE_SMM_CORE = 'SMM_CORE'
+SUP_MODULE_SMM_STANDALONE = 'SMM_STANDALONE'
+SUP_MODULE_SMM_CORE_STANDALONE = 'SMM_CORE_STANDALONE'
 
 SUP_MODULE_LIST = [SUP_MODULE_BASE, SUP_MODULE_SEC, SUP_MODULE_PEI_CORE, 
SUP_MODULE_PEIM, SUP_MODULE_DXE_CORE, SUP_MODULE_DXE_DRIVER, \
SUP_MODULE_DXE_RUNTIME_DRIVER, SUP_MODULE_DXE_SAL_DRIVER, 
SUP_MODULE_DXE_SMM_DRIVER, SUP_MODULE_UEFI_DRIVER, \
-   SUP_MODULE_UEFI_APPLICATION, SUP_MODULE_USER_DEFINED, 
SUP_MODULE_SMM_CORE]
+   SUP_MODULE_UEFI_APPLICATION, SUP_MODULE_USER_DEFINED, 
SUP_MODULE_SMM_CORE, SUP_MODULE_SMM_STANDALONE, SUP_MODULE_SMM_CORE_STANDALONE]
 SUP_MODULE_LIST_STRING = TAB_VALUE_SPLIT.join(l for l in SUP_MODULE_LIST)
 
 EDK_COMPONENT_TYPE_LIBRARY = 'LIBRARY'
-- 
2.7.4

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[edk2] [PATCH v3 00/10] *** BaseTools: Tools change to support MM Interface in PI v1.5 Specification ***

2017-06-22 Thread Supreeth Venkatesh 
*** 
PI v1.5 Specification Volume 4 defines Management Mode Core Interface.
In order to support Management Mode Core Interface, Module Types MM_STANDALONE, 
MM_CORE_STANDALONE are needed. 
PI specification v1.5 defines the following new file types:
#define EFI_FV_FILETYPE_MM 0x0A
#define EFI_FV_FILETYPE_COMBINED_MM_DXE 0x0C
#define EFI_FV_FILETYPE_MM_STANDALONE 0x0E
#define EFI_FV_FILETYPE_MM_CORE_STANDALONE 0x0F
The following changes are necessitated in order to support the above changes to 
the specification. 

Changes Since v2:
Add missing EFI_FV_FILETYPE_MM_CORE_STANDALONE defined in PI Specification v1.5 
VOL3, 
but not defined in VOL4.

Changes Since v1:
Corrected Version check HEX Value "0x00010032" (1 and 50), not 0x0001000A (1 
and 10) 
***

Supreeth Venkatesh (10):
  BaseTools: Tools change to support PI v1.5 Specification.
  BaseTools: Tools change to support PI v1.5 Specification.
  BaseTools: Tools change to support PI v1.5 Specification.
  BaseTools: Tools change to support PI v1.5 Specification.
  BaseTools: Tools change to support PI v1.5 Specification.
  BaseTools: Tools change to support PI v1.5 Specification.
  BaseTools: Tools change to support PI v1.5 Specification.
  BaseTools: Tools change to support PI v1.5 Specification.
  BaseTools: Tools change to support PI v1.5 Specification.
  BaseTools: Tools change to support PI v1.5 Specification.

 BaseTools/Source/C/GenFfs/GenFfs.c |   8 +-
 BaseTools/Source/C/GenFw/GenFw.c   |   5 +-
 BaseTools/Source/C/Include/Common/PiFirmwareFile.h |   2 +
 BaseTools/Source/Python/AutoGen/GenC.py| 148 -
 BaseTools/Source/Python/AutoGen/GenDepex.py|  17 ++-
 BaseTools/Source/Python/Common/DataType.py |   4 +-
 BaseTools/Source/Python/Common/FdfParserLite.py|   4 +-
 .../Source/Python/CommonDataClass/CommonClass.py   |   6 +-
 .../Source/Python/CommonDataClass/PackageClass.py  |   2 +-
 BaseTools/Source/Python/Eot/FvImage.py |   2 +
 BaseTools/Source/Python/GenFds/FdfParser.py|   4 +-
 BaseTools/Source/Python/GenFds/Ffs.py  |   8 +-
 BaseTools/Source/Python/GenFds/FfsInfStatement.py  |   3 +
 .../Source/Python/Workspace/WorkspaceDatabase.py   |   5 +
 BaseTools/Source/Python/build/BuildReport.py   |   4 +-
 BaseTools/Source/Python/build/build.py |   2 +-
 16 files changed, 205 insertions(+), 19 deletions(-)

-- 
2.7.4

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[edk2] [PATCH v3 03/10] BaseTools: Tools change to support PI v1.5 Specification.

2017-06-22 Thread Supreeth Venkatesh 
This patch adds changes to auto generate SMM_CORE_STANDALONE and
SMM_STANDALONE Entry Point templates.
Also, it adds changes to help auto generate dependency expressions for
SMM_STANDALONE modules.

PI Specification v1.5 specifies Management Mode System Table (MMST)
which is  a collection of common services for managing
MMRAM allocation and providing basic I/O services. MMST is similar to
the UEFI System Table.

Some of auto generated SMM_CORE_STANDALONE and SMM_STANDALONE template
APIs use MMST as parameter.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
Signed-off-by: Supreeth Venkatesh 
---
 BaseTools/Source/Python/AutoGen/GenC.py | 148 +++-
 BaseTools/Source/Python/AutoGen/GenDepex.py |  17 +++-
 2 files changed, 162 insertions(+), 3 deletions(-)

diff --git a/BaseTools/Source/Python/AutoGen/GenC.py 
b/BaseTools/Source/Python/AutoGen/GenC.py
index 67aaef7..d42dd45 100644
--- a/BaseTools/Source/Python/AutoGen/GenC.py
+++ b/BaseTools/Source/Python/AutoGen/GenC.py
@@ -237,6 +237,100 @@ ProcessModuleEntryPointList (
 ${END}
 """)
 
+## SMM_CORE_STANDALONE Entry Point Templates
+gSmmCoreStandaloneEntryPointPrototype = TemplateString("""
+${BEGIN}
+EFI_STATUS
+EFIAPI
+${Function} (
+  IN VOID *HobStart
+  );
+${END}
+""")
+
+gSmmCoreStandaloneEntryPointString = TemplateString("""
+${BEGIN}
+const UINT32 _gSmmRevision = ${PiSpecVersion};
+
+VOID
+EFIAPI
+ProcessModuleEntryPointList (
+  IN VOID *HobStart
+  )
+{
+  ${Function} (HobStart);
+}
+${END}
+""")
+
+## SMM_STANDALONE Entry Point Templates
+gSmmStandaloneEntryPointPrototype = TemplateString("""
+${BEGIN}
+EFI_STATUS
+EFIAPI
+${Function} (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SMM_SYSTEM_TABLE2 *SmmSystemTable
+  );
+${END}
+""")
+
+gSmmStandaloneEntryPointString = [
+TemplateString("""
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT32 _gSmmRevision = ${PiSpecVersion};
+
+EFI_STATUS
+EFIAPI
+ProcessModuleEntryPointList (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SMM_SYSTEM_TABLE2 *SmmSystemTable
+  )
+
+{
+  return EFI_SUCCESS;
+}
+"""),
+TemplateString("""
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT32 _gSmmRevision = ${PiSpecVersion};
+${BEGIN}
+EFI_STATUS
+EFIAPI
+ProcessModuleEntryPointList (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SMM_SYSTEM_TABLE2 *SmmSystemTable
+  )
+
+{
+  return ${Function} (ImageHandle, SmmSystemTable);
+}
+${END}
+"""),
+TemplateString("""
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT32 _gSmmRevision = ${PiSpecVersion};
+
+EFI_STATUS
+EFIAPI
+ProcessModuleEntryPointList (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SMM_SYSTEM_TABLE2 *SmmSystemTable
+  )
+
+{
+  EFI_STATUS  Status;
+  EFI_STATUS  CombinedStatus;
+
+  CombinedStatus = EFI_LOAD_ERROR;
+${BEGIN}
+  Status = ${Function} (ImageHandle, SmmSystemTable);
+  if (!EFI_ERROR (Status) || EFI_ERROR (CombinedStatus)) {
+CombinedStatus = Status;
+  }
+${END}
+  return CombinedStatus;
+}
+""")
+]
+
 ## DXE SMM Entry Point Templates
 gDxeSmmEntryPointPrototype = TemplateString("""
 ${BEGIN}
@@ -580,6 +674,15 @@ ${Function} (
   IN EFI_SYSTEM_TABLE  *SystemTable
   );${END}
 """),
+
+'SMM'   : TemplateString("""${BEGIN}
+EFI_STATUS
+EFIAPI
+${Function} (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SMM_SYSTEM_TABLE2 *SmmSystemTable
+  );${END}
+"""),
 }
 
 gLibraryStructorCall = {
@@ -597,6 +700,11 @@ gLibraryStructorCall = {
   Status = ${Function} (ImageHandle, SystemTable);
   ASSERT_EFI_ERROR (Status);${END}
 """),
+
+'SMM'   : TemplateString("""${BEGIN}
+  Status = ${Function} (ImageHandle, SmmSystemTable);
+  ASSERT_EFI_ERROR (Status);${END}
+"""),
 }
 
 ## Library Constructor and Destructor Templates
@@ -644,6 +752,21 @@ ${BEGIN}  EFI_STATUS  Status;
 ${FunctionCall}${END}
 }
 """),
+
+'SMM'   :   TemplateString("""
+${BEGIN}${FunctionPrototype}${END}
+
+VOID
+EFIAPI
+ProcessLibrary${Type}List (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SMM_SYSTEM_TABLE2 *SmmSystemTable
+  )
+{
+${BEGIN}  EFI_STATUS  Status;
+${FunctionCall}${END}
+}
+"""),
 }
 
 gBasicHeaderFile = "Base.h"
@@ -661,6 +784,8 @@ gModuleTypeHeaderFile = {
 "UEFI_DRIVER"   :   ["Uefi.h",  "Library/BaseLib.h", 
"Library/DebugLib.h", "Library/UefiBootServicesTableLib.h", 
"Library/UefiDriverEntryPoint.h"],
 "UEFI_APPLICATION"  :   ["Uefi.h",  "Library/BaseLib.h", 
"Library/DebugLib.h", "Library/UefiBootServicesTableLib.h", 
"Library/UefiApplicationEntryPoint.h"],
 "SMM_CORE"  :   ["PiDxe.h", "Library/BaseLib.h", 
"Library/DebugLib.h", "Library/UefiDriverEntryPoint.h"],
+"SMM_STANDALONE":   ["PiSmm.h", "Library/BaseLib.h", 
"Library/DebugLib.h", "Library/SmmDriverStandaloneEntryPoint.h"],
+"SMM_CORE_STANDALONE" : ["PiSmm.h", "Library/BaseLib.h", 
"Library/DebugLib.h", "Library/SmmCoreStandaloneEntryPoint.h"],
 "USER_DEFINED"  :   [gBasicHeaderFile]
 }
 
@@ -1266,6 +1391,9 @@ def

Re: [edk2] [PATCH 1/5] OvmfPkg: introduce Q35TsegSizeLib (class header and sole lib instance)

2017-06-22 Thread Laszlo Ersek 
On 06/21/17 02:52, Yao, Jiewen wrote:
> As far as I know, the real platform SmmAccessPeim may depend on
> gEfiPeiMemoryDiscoveredPpiGuid, because the SmramHob is produced in
> MRC wrapper.

Thanks for the info, Jiewen!

- I don't know what "MRC wrapper" is.

  I found "QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c",
  with the comment "Framework PEIM to initialize memory on a Quark
  Memory Controller".

- I don't know what "SmramHob" is.

  I see some hits in QuarkPlatformPkg and Vlv2TbltDevicePkg. The type
  seems to be "EFI_SMRAM_HOB_DESCRIPTOR_BLOCK", in
  "IntelFrameworkPkg/Include/Guid/SmramMemoryReserve.h", with the
  comment "GUID specific data structure of HOB for reserving SMRAM
  regions".

  I think the comment is inaccurate. From the data structure itself, it
  looks like the HOB is used to expose the possible SMRAM regions to
  "other" modules, and not to reserve regions from SMRAM. Anyway, I
  guess the HOB is consumed by modules such as:

  - QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe
  - QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei

So apparently, on Quark, the PEIM that initializes physical RAM produces
the SmramHob (which is an Intel Framework concept, apparently), and
SmmAccessPei consumes the SmramHob. In order to serialize these
operations, the two PEIMs reuse / repurpose
gEfiPeiMemoryDiscoveredPpiGuid, as a PEIM dispatch barrier. The
availability of SmramHob is parallel to the availability of
gEfiPeiMemoryDiscoveredPpiGuid.

This doesn't match OVMF for two reasons:

- In OVMF / on QEMU, we don't initialize RAM (we don't have to).

- In OVMF, we have a separate SmmAccessPei implementation, which does
  not rely on such a HOB.

Rebasing the SMM platform code in OVMF to SmramHob is out of scope, in
my opinion. The current layout of drivers works fine; we just need a new
bit pattern (11 binary) in the ESMRAMC.TSEG_SZ bitfield, and OVMF should
be able to query QEMU as to what that bit pattern translates to,
size-wise. That's all.

> At same time, I also saw a solution to use library to produce
> SmmAccessPpi. In such case, there is no dependency expression, because
> one module does 2 things: 1) init memory, 2) produce SmmAccessPpi.

I agree that this is a technical possiblity, but for OVMF it is again
out of scope. One reason is separation of concepts. Another reason is
that OVMF can be built without SMM support (that's the default
actually), and for such a build the library approach would require a
Null instance of whatever new library class we would invent. Too much
churn.

Jordan, can we please go ahead with the posted approach? If you strongly
prefer dynamic PCDs (which I *slightly* dislike), I can do that --
hacking a spurious gEfiPeiMemoryDiscoveredPpiGuid dependency into
SmmAccessPei.inf, as a serialization barrier between PCD setting and PCD
consumption --, for the sake of making progress on this series.

Thanks,
Laszlo
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Re: [edk2] [RFC] migration of OpenPlatformPkg to tianocore

2017-06-22 Thread Leif Lindholm 
On Thu, Jun 22, 2017 at 03:57:10PM +, Ard Biesheuvel wrote:
> >> Build/Cello/DEBUG_GCC5/AARCH64/edk2-platforms/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT/Dsdt.hex
> >>
> >> but the include is defined as
> >>
> >>   GCC:*_*_AARCH64_PLATFORM_FLAGS =
> >> -I$(BIN_DIR)/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT
> >
> > You're not reading the documentation ;)  (Have a glance at Readme.md.)
> >
> > Yes, this is the behaviour I had before this latest reshuffle.
> > Mike's proposed (and functional) workaround is to not have "edk2" as
> > your WORKSPACE, but a common superdirectory of edk2, edk2-platforms
> > and edk2-non-osi.
> >
> > Hopefully at some point we can get rid of this restriction, but for
> > now it's sort of necessary.
> 
> Thanks for clearing that up. And as it turns out, WORKSPACE is not
> required to be a parent directory to the core EDK2 checkout or any of
> the alternative sources listed in PACKAGES_PATH, which is actually
> quite convenient.

*cough* yes, apparently that works when you actually set WORKSPACE in
the same terminal as you then run edksetup.sh from...

/
Leif
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Re: [edk2] [RFC] migration of OpenPlatformPkg to tianocore

2017-06-22 Thread Ard Biesheuvel 
On 22 June 2017 at 12:49, Leif Lindholm  wrote:
> On Thu, Jun 22, 2017 at 11:46:16AM +, Ard Biesheuvel wrote:
>> On 22 June 2017 at 11:39, Ard Biesheuvel  wrote:
>> > On 21 June 2017 at 17:44, Leif Lindholm  wrote:
>> >> Hi all,
>> >>
>> >> I have now pushed updated versions of devel-OpenPlatformPkg branches
>> >> to edk2-platforms and edk2-non-osi. I now also have a Readme.md at the
>> >> top-level of edk2-platforms describing
>> >>
>> >> All the silly hacks are gone, and all platforms now build.
>> >>
>> >> I would really appreciate if people could have a look (and a play).
>> >>
>> >
>> > Cello does not build atm in the new arrangement:
>> >
>> > build.py...
>> >  : error 000E: File/directory not found in workspace
>> > OpenPlatformPkg/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf
>> > is not found in packages path:
>> > /home/ard/build/edk2/../edk2-platforms
>> > /home/ard/build/edk2/../edk2-non-osi
>>
>> I also think the new PACKAGES_PATH breaks the inclusion of Dsdt.hex:
>>
>> /home/ard/build/edk2-platforms/Silicon/AMD/Styx/AcpiTables/Dsdt.c:22:20:
>> fatal error: Dsdt.hex: No such file or directory
>>  #include 
>> ^
>> compilation terminated.
>>
>> which resides at
>>
>> Build/Cello/DEBUG_GCC5/AARCH64/edk2-platforms/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT/Dsdt.hex
>>
>> but the include is defined as
>>
>>   GCC:*_*_AARCH64_PLATFORM_FLAGS =
>> -I$(BIN_DIR)/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT
>
> You're not reading the documentation ;)  (Have a glance at Readme.md.)
>
> Yes, this is the behaviour I had before this latest reshuffle.
> Mike's proposed (and functional) workaround is to not have "edk2" as
> your WORKSPACE, but a common superdirectory of edk2, edk2-platforms
> and edk2-non-osi.
>
> Hopefully at some point we can get rid of this restriction, but for
> now it's sort of necessary.
>

Thanks for clearing that up. And as it turns out, WORKSPACE is not
required to be a parent directory to the core EDK2 checkout or any of
the alternative sources listed in PACKAGES_PATH, which is actually
quite convenient.
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Re: [edk2] [staging/cadence-aarch64 PATCH v3 4/6] CadencePkg: Add SEC phase implementation for Cadence CSP platform.

2017-06-22 Thread Leif Lindholm 
On Thu, Jun 22, 2017 at 10:31:59AM +0100, Scott Telford wrote:
> Add SEC phase implementation for Cadence CSP platform configured with
> a single Cortex-A53 processor and GIC-500.
> 
> Based on ArmPlatformPkg/Sec, with required parts of
> ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib integrated (both now deleted
> from edk2 master).
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Scott Telford 

Reviewed-by: Leif Lindholm 

> ---
>  CadencePkg/Sec/AArch64/Arch.c   |  25 +++
>  CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S |  27 +++
>  CadencePkg/Sec/AArch64/Helper.S |  93 
>  CadencePkg/Sec/AArch64/SecEntryPoint.S  | 139 
>  CadencePkg/Sec/Sec.c| 335 
> 
>  CadencePkg/Sec/Sec.inf  |  85 +++
>  CadencePkg/Sec/SecInternal.h| 105 +
>  7 files changed, 809 insertions(+)
>  create mode 100644 CadencePkg/Sec/AArch64/Arch.c
>  create mode 100644 CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
>  create mode 100644 CadencePkg/Sec/AArch64/Helper.S
>  create mode 100644 CadencePkg/Sec/AArch64/SecEntryPoint.S
>  create mode 100644 CadencePkg/Sec/Sec.c
>  create mode 100644 CadencePkg/Sec/Sec.inf
>  create mode 100644 CadencePkg/Sec/SecInternal.h
> 
> diff --git a/CadencePkg/Sec/AArch64/Arch.c b/CadencePkg/Sec/AArch64/Arch.c
> new file mode 100644
> index 000..6e7d58e
> --- /dev/null
> +++ b/CadencePkg/Sec/AArch64/Arch.c
> @@ -0,0 +1,25 @@
> +/** @file
> +*
> +*  Copyright (c) 2013, ARM Limited. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD 
> License
> +*  which accompanies this distribution.  The full text of the license may be 
> found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +*
> +**/
> +
> +#include 
> +
> +VOID
> +EFIAPI
> +ArmSecArchTrustzoneInit (
> +  VOID
> +  )
> +{
> +  // Do not trap any access to Floating Point and Advanced SIMD in EL3.
> +  ArmWriteCptr (0);
> +}
> diff --git a/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S 
> b/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
> new file mode 100644
> index 000..531de63
> --- /dev/null
> +++ b/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
> @@ -0,0 +1,27 @@
> +#--
> +#
> +# Copyright (c) 2013 - 2014, ARM Limited. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD 
> Licese
> +# which accompanies this distribution.  The full text of the license may be 
> foun at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +#
> +#--
> +
> +#include 
> +
> +ASM_FUNC(ArmReadCpuExCr)
> +  mrs   x0, S3_1_c15_c2_1
> +  ret
> +
> +ASM_FUNC(ArmWriteCpuExCr)
> +  msr   S3_1_c15_c2_1, x0
> +  dsb   sy
> +  isb
> +  ret
> +
> +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
> diff --git a/CadencePkg/Sec/AArch64/Helper.S b/CadencePkg/Sec/AArch64/Helper.S
> new file mode 100644
> index 000..3b58e12
> --- /dev/null
> +++ b/CadencePkg/Sec/AArch64/Helper.S
> @@ -0,0 +1,93 @@
> +#
> +#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD 
> License
> +#  which accompanies this distribution.  The full text of the license may be 
> found at
> +#  http:#opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +#
> +#===
> +
> +#include 
> +#include 
> +
> +#start of the code section
> +.text
> +.align 3
> +
> +GCC_ASM_EXPORT(SwitchToNSExceptionLevel1)
> +GCC_ASM_EXPORT(enter_monitor_mode)
> +GCC_ASM_EXPORT(return_from_exception)
> +GCC_ASM_EXPORT(copy_cpsr_into_spsr)
> +GCC_ASM_EXPORT(set_non_secure_mode)
> +
> +// Switch from EL3 to NS-EL1
> +ASM_PFX(SwitchToNSExceptionLevel1):
> +   // Now setup our EL1. Controlled by EL2 config on Model
> +   mrs x0, hcr_el2// Read EL2 Hypervisor configuration 
> Register
> +   orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
> +
> +   // Send all interrupts to

Re: [edk2] [staging/cadence-aarch64 PATCH v3 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex.

2017-06-22 Thread Leif Lindholm 
On Thu, Jun 22, 2017 at 10:31:58AM +0100, Scott Telford wrote:
> Add PciHostBridgeLib implementation for the Cadence PCIe Root Complex.
> This library is derived from
> Platforms/ARM/Juno/Library/JunoPciHostBridgeLib in OpenPlatformPkg.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Scott Telford 
> ---
>  .../Library/CadencePciHostBridgeLib/CdnsPci.c  | 149 
>  .../Library/CadencePciHostBridgeLib/CdnsPci.h  |  88 ++
>  .../CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c | 188 
> +
>  .../CdnsPciHostBridgeLib.inf   |  73 
>  4 files changed, 498 insertions(+)
>  create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
>  create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
>  create mode 100644 
> CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
>  create mode 100644 
> CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf
> 
> diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c 
> b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
> new file mode 100644
> index 000..3114843
> --- /dev/null
> +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
> @@ -0,0 +1,149 @@
> +/** @file
> +*  Initialize the Cadence PCIe Root complex
> +*
> +*  Copyright (c) 2017, Cadence Design Systems. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD 
> License
> +*  which accompanies this distribution.  The full text of the license may be 
> found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +*
> +**/
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#include "CdnsPci.h"
> +
> +STATIC
> +VOID
> +CdnsPciConfigRegion (
> +  EFI_CPU_IO2_PROTOCOL *CpuIo,
> +  IN UINT32 Region,
> +  IN UINT32 Descriptor,
> +  IN UINT32 TransAddr,
> +  IN UINT32 TransAddrBits,
> +  IN UINT32 BaseAddr,
> +  IN UINT32 BaseAddrBits
> +  )
> +{
> +  UINTN RegionBaseAddr = PCIE_AXI + (Region * PCIE_AXI_REGION_OFF);
> +
> +  PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_TRANS0_OFF,
> + TransAddr | TransAddrBits);
> +  PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_DESC_OFF,
> + Descriptor);
> +  PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_BASE0_OFF,
> + BaseAddr | BaseAddrBits);
> +}
> +
> +STATIC
> +VOID
> +CdnsPciRegInit(
> +  EFI_CPU_IO2_PROTOCOL*CpuIo
> +)
> +{
> +  UINT32  Value;
> +
> +  // Setup the class code as PCIe Host Bridge.
> +  PCIE_ROOTPORT_WRITE32 (PCIE_RP + PCIE_PCI_CLASSCODE, 
> PCIE_BRIDGE_CLASSCODE);
> +
> +  // Set up the BARs via the Root Port registers
> +  PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value);
> +  PCIE_ROOTPORT_WRITE32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value | (1 << 
> PCIE_RCBARPIE));
> +
> +  // Allow incoming writes
> +  PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR0_IB, PCIE_AXI_BITS_32);
> +  PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR1_IB, PCIE_AXI_BITS_32);
> +  PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_NO_BAR_IB, PCIE_AXI_BITS_32);
> +
> +  // Set up region 0 for Type 0 write (bus 0 and 1), size 2MB
> +  CdnsPciConfigRegion (
> +  CpuIo,
> +  0,
> +  PCIE_AXI_DESC_TYPE0,
> +  PCIE_ECAM_BASE,
> +  PCIE_AXI_BITS_25,
> +  0,
> +  PCIE_AXI_BITS_21
> +  );
> +
> +  // Set up region 1 for Type 1 writes (bus 2 upwards), size (32-2)MB
> +  CdnsPciConfigRegion(
> +  CpuIo,
> +  1,
> +  PCIE_AXI_DESC_TYPE1,
> +  PCIE_ECAM_BASE + (2*PCIE_BUS_SIZE),
> +  PCIE_AXI_BITS_25,
> +  2*PCIE_BUS_SIZE,
> +  PCIE_AXI_BITS_25
> +  );
> +
> +  // Set up region 2 for memory write, size 16MB
> +  CdnsPciConfigRegion(
> +  CpuIo,
> +  2,
> +  PCIE_AXI_DESC_MEM,
> +  PCIE_MEM32_BASE,
> +  PCIE_AXI_BITS_25,
> +  (PCIE_MEM32_BASE - PCIE_ECAM_BASE),
> +  PCIE_AXI_BITS_24
> +  );
> +
> +  // Set up region 3 for IO write, size 16MB
> +  CdnsPciConfigRegion(
> +  CpuIo,
> +  3,
> +  PCIE_AXI_DESC_IO,
> +  PCIE_IO_BASE,
> +  PCIE_AXI_BITS_25,
> +  (PCIE_IO_BASE - PCIE_ECAM_BASE),
> +  PCIE_AXI_BITS_24
> +  );

Thanks - this is exactly what I was hoping for!
I'll leave for Ard to comment on hos bits, but:
Reviewed-by: Leif Lindholm 

> +}
> +
> +EFI_STATUS
> +HWPciRbInit (
> +  IN EFI_HANDLEImageHandle,
> +  IN EFI_SYSTEM_TABLE  *SystemTable
> +  )
> +{
> +  UINT32

Re: [edk2] [staging/cadence-aarch64 PATCH v3 2/6] CadencePkg: Add library for Cadence UART.

2017-06-22 Thread Leif Lindholm 
On Thu, Jun 22, 2017 at 10:31:57AM +0100, Scott Telford wrote:
> Add serial port library to support the Cadence IP6528 UART used in the
> Cadence CSP platform.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Scott Telford 

Reviewed-by: Leif Lindholm 

> ---
>  CadencePkg/Include/Library/CspSerialPortLib.h  |  86 
>  .../CadenceCspSerialPortLib/CspSerialPortLib.c | 523 
> +
>  .../CadenceCspSerialPortLib/CspSerialPortLib.inf   |  52 ++
>  .../CadenceCspSerialPortLib/CspSerialPortLib.uni   | Bin 0 -> 1622 bytes
>  4 files changed, 661 insertions(+)
>  create mode 100644 CadencePkg/Include/Library/CspSerialPortLib.h
>  create mode 100644 
> CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
>  create mode 100644 
> CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
>  create mode 100644 
> CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni
> 
> diff --git a/CadencePkg/Include/Library/CspSerialPortLib.h 
> b/CadencePkg/Include/Library/CspSerialPortLib.h
> new file mode 100644
> index 000..46fa0d8
> --- /dev/null
> +++ b/CadencePkg/Include/Library/CspSerialPortLib.h
> @@ -0,0 +1,86 @@
> +/** @file
> +*  Serial Port Library for Cadence IP6528 UART.
> +*  Copyright (c) 2017, Cadence Design Systems. All rights reserved.
> +*
> +*  This program and the accompanying materials are licensed and made
> +*  available under the terms and conditions of the BSD License which
> +*  accompanies this distribution.  The full text of the license may be
> +*  found at http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +*
> +**/
> +
> +#ifndef __CSP_SERIAL_PORT_LIB_H__
> +#define __CSP_SERIAL_PORT_LIB_H__
> +
> +// Cadence UART register offsets
> +#define CSP_UART_CR 0x00  // Control
> +#define CSP_UART_MR 0x04  // Mode
> +#define CSP_UART_IER0x08  // Interrupt enable
> +#define CSP_UART_IDR0x0C  // Interrupt disable
> +#define CSP_UART_IMR0x10  // Interrupt mask
> +#define CSP_UART_CISR   0x14  // Channel interrupt status
> +#define CSP_UART_BRGR   0x18  // Baud rate generator
> +#define CSP_UART_RTOR   0x1C  // Rx Timeout
> +#define CSP_UART_RTRIG  0x20  // Rx FIFO trigger level
> +#define CSP_UART_MCR0x24  // Modem control
> +#define CSP_UART_MSR0x28  // Modem status
> +#define CSP_UART_CSR0x2C  // Channel status
> +#define CSP_UART_FIFO   0x30  // FIFO (Tx/Rx)
> +#define CSP_UART_BDIV   0x34  // Baud rate divider
> +#define CSP_UART_FDEL   0x38  // Flow delay
> +#define CSP_UART_PMIN   0x3C  // IR min received pulse width
> +#define CSP_UART_PWID   0x40  // IR transmitted pulse Width
> +#define CSP_UART_TTRIG  0x44  // Tx FIFO trigger level
> +
> +
> +// Control Register Bit Definitions
> +#define CSP_UART_CR_STPBRK  0x0100  // Stop Tx break
> +#define CSP_UART_CR_STTBRK  0x0080  // Start Tx break
> +#define CSP_UART_CR_RSTTO   0x0040  // Restart Rx timeout Counter
> +#define CSP_UART_CR_TXDIS   0x0020  // Tx disable
> +#define CSP_UART_CR_TXEN0x0010  // Tx enable
> +#define CSP_UART_CR_RXDIS   0x0008  // Rx disable
> +#define CSP_UART_CR_RXEN0x0004  // Rx enable
> +#define CSP_UART_CR_TXRES   0x0002  // Tx reset
> +#define CSP_UART_CR_RXRES   0x0001  // Rx reset
> +
> +
> +// Mode register bit definitions
> +#define CSP_UART_MR_CLKS0x0001  // Baud rate /8 
> pre-scalar
> +#define CSP_UART_MR_CHMODE_LLB  0x0200  // Local loopback mode
> +#define CSP_UART_MR_CHMODE_NML  0x  // Normal mode
> +
> +#define CSP_UART_MR_CHRL_6  0x0006  // 6 databits
> +#define CSP_UART_MR_CHRL_7  0x0004  // 7 databits
> +#define CSP_UART_MR_CHRL_8  0x  // 8 databits
> +
> +#define CSP_UART_MR_PAR_NONE0x0020  // No parity mode
> +#define CSP_UART_MR_PAR_MARK0x0018  // Mark parity mode
> +#define CSP_UART_MR_PAR_SPACE   0x0010  // Space parity mode
> +#define CSP_UART_MR_PAR_ODD 0x0008  // Odd parity mode
> +#define CSP_UART_MR_PAR_EVEN0x  // Even parity mode
> +
> +#define CSP_UART_MR_NBSTOP_10x  // 1 stop bit
> +#define CSP_UART_MR_NBSTOP_20x0080  // 2 stop bits
> +
> +// Modem control register bit definitions
> +#define CSP_UART_MCR_DTR0x0001  // DTR control
> +#define CSP_UART_MCR_RTS0x0002  // RTS control
> +#define CSP_UART_MCR_FCM0x0020  // Auto flow control
> +
> +// Modem status register bit definitions
>

Re: [edk2] [staging/cadence-aarch64 PATCH v3 1/6] CadencePkg: Add libraries for Cadence CSP platform.

2017-06-22 Thread Leif Lindholm 
On Thu, Jun 22, 2017 at 10:31:56AM +0100, Scott Telford wrote:
> Add libraries (CadenceCspLib, CadenceCspSecLib,
> CadenceCspResetSystemLib) to support the Cadence Configurable System
> Platform (CSP) configured with a single ARM Cortex-A53, GIC-500,
> Cadence UART and Cadence PCIe Root Complex.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Scott Telford 

I'd like for Ard to comment on the bits he raised last time, but from
my point of view:
Reviewed-by: Leif Lindholm 

/
Leif

> ---
>  CadencePkg/Include/Library/CspSysReg.h |  37 ++
>  .../CadenceCspLib/AArch64/ArmPlatformHelper.S  |  55 +
>  CadencePkg/Library/CadenceCspLib/CadenceCspLib.c   | 133 
> +
>  CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf |  68 +++
>  .../Library/CadenceCspLib/CadenceCspLibMem.c   | 116 ++
>  .../Library/CadenceCspLib/CadenceCspLibSec.inf |  52 
>  .../CadenceCspResetSystemLib.c |  82 +
>  .../CadenceCspResetSystemLib.inf   |  40 +++
>  .../Library/CadenceCspSecLib/AArch64/CspBoot.S |  49 
>  .../Library/CadenceCspSecLib/AArch64/GicV3.S   |  67 +++
>  .../Library/CadenceCspSecLib/CadenceCspSecLib.inf  |  44 +++
>  CadencePkg/Library/CadenceCspSecLib/CspSec.c   |  79 
>  12 files changed, 822 insertions(+)
>  create mode 100644 CadencePkg/Include/Library/CspSysReg.h
>  create mode 100644 
> CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
>  create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
>  create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
>  create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
>  create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
>  create mode 100644 
> CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
>  create mode 100644 
> CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
>  create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
>  create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
>  create mode 100644 CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
>  create mode 100644 CadencePkg/Library/CadenceCspSecLib/CspSec.c
> 
> diff --git a/CadencePkg/Include/Library/CspSysReg.h 
> b/CadencePkg/Include/Library/CspSysReg.h
> new file mode 100644
> index 000..4d3ac925
> --- /dev/null
> +++ b/CadencePkg/Include/Library/CspSysReg.h
> @@ -0,0 +1,37 @@
> +/** @file
> +*  Cadence CSP system register offsets.
> +*  Copyright (c) 2017, Cadence Design Systems. All rights reserved.
> +*
> +*  This program and the accompanying materials are licensed and made
> +*  available under the terms and conditions of the BSD License which
> +*  accompanies this distribution.  The full text of the license may be
> +*  found at http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +*
> +**/
> +
> +#ifndef __CSP_SYS_REG_H__
> +#define __CSP_SYS_REG_H__
> +
> +// Cadence CSP system register offsets
> +#define CSP_SYSREG_VERSION  0x00
> +#define CSP_SYSREG_CPU_FREQ 0x04
> +#define CSP_SYSREG_STATUS   0x08
> +#define CSP_SYSREG_RUN_STALL0x0C
> +#define CSP_SYSREG_SW_RESET 0x10
> +#define CSP_SYSREG_CORE1_RESET  0x14
> +#define CSP_SYSREG_SCRATCH_REG_00x18
> +#define CSP_SYSREG_PROC_INTERRUPT   0x1C
> +#define CSP_SYSREG_SCRATCH_REG_10x20
> +#define CSP_SYSREG_SCRATCH_REG_20x24
> +#define CSP_SYSREG_SCRATCH_REG_30x28
> +#define CSP_SYSREG_SCRATCH_REG_40x2C
> +#define CSP_SYSREG_SCRATCH_REG_50x30
> +#define CSP_SYSREG_SCRATCH_REG_60x34
> +#define CSP_SYSREG_SET_INTERRUPT0x38
> +#define CSP_SYSREG_CLR_INTERRUPT0x3C
> +#define CSP_SYSREG_DIP_SWITCHES 0x40
> +
> +#endif
> diff --git a/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S 
> b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
> new file mode 100644
> index 000..8832673
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
> @@ -0,0 +1,55 @@
> +#
> +#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD 
> License
> +#  which accompanies this distribution.  The full text of the license may be 
> found at
> +#  http://opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +#
> +#
> +
> +#include 
> +#include 
> +
>

[edk2] [PATCH 2/2] MdeModulePkg Variable: Update GetNextVariableName to follow UEFI 2.7

2017-06-22 Thread Star Zeng 
"The size must be large enough to fit input string supplied in
VariableName buffer" is added in the description for VariableNameSize.
And two cases of EFI_INVALID_PARAMETER are added.
1. The input values of VariableName and VendorGuid are not a name and
   GUID of an existing variable.
2. Null-terminator is not found in the first VariableNameSize bytes of
   the input VariableName buffer.

This patch is to update code to follow them.

Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng 
---
 MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c 
b/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
index 0a325de1659d..d8f41d799238 100644
--- a/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
+++ b/MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c
@@ -2926,6 +2926,12 @@ VariableServiceGetNextVariableInternal (
 
   Status = FindVariable (VariableName, VendorGuid, , 
>VariableGlobal, FALSE);
   if (Variable.CurrPtr == NULL || EFI_ERROR (Status)) {
+if (VariableName[0] != 0) {
+  //
+  // The input values of VariableName and VendorGuid are not a name and 
GUID of an existing variable.
+  //
+  Status = EFI_INVALID_PARAMETER;
+}
 goto Done;
   }
 
@@ -3065,6 +3071,7 @@ VariableServiceGetNextVariableName (
   )
 {
   EFI_STATUS  Status;
+  UINTN   MaxLen;
   UINTN   VarNameSize;
   VARIABLE_HEADER *VariablePtr;
 
@@ -3072,6 +3079,18 @@ VariableServiceGetNextVariableName (
 return EFI_INVALID_PARAMETER;
   }
 
+  //
+  // Calculate the possible maximum length of name string, including the Null 
terminator.
+  //
+  MaxLen = *VariableNameSize / sizeof (CHAR16);
+  if ((MaxLen == 0) ||
+  ((VariableName[MaxLen - 1] != 0) && (StrnLenS (VariableName, MaxLen) >= 
MaxLen))) {
+//
+// Null-terminator is not found in the first VariableNameSize bytes of the 
input VariableName buffer.
+//
+return EFI_INVALID_PARAMETER;
+  }
+
   
AcquireLockOnlyAtBootTime(>VariableGlobal.VariableServicesLock);
 
   Status = VariableServiceGetNextVariableInternal (VariableName, VendorGuid, 
);
-- 
2.7.0.windows.1

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[edk2] [PATCH 0/2] Update comments and code for GetNextVariableName to follow UEFI 2.7

2017-06-22 Thread Star Zeng 
"The size must be large enough to fit input string supplied in
VariableName buffer" is added in the description for VariableNameSize.
And two cases of EFI_INVALID_PARAMETER are added.
1. The input values of VariableName and VendorGuid are not a name and
   GUID of an existing variable.
2. Null-terminator is not found in the first VariableNameSize bytes of
   the input VariableName buffer.

Star Zeng (2):
  MdePkg: Update comments for GetNextVariableName to follow UEFI 2.7
  MdeModulePkg Variable: Update GetNextVariableName to follow UEFI 2.7

 MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c | 19 +++
 MdePkg/Include/Uefi/UefiSpec.h|  7 ++-
 2 files changed, 25 insertions(+), 1 deletion(-)

-- 
2.7.0.windows.1

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[edk2] [PATCH 1/2] MdePkg: Update comments for GetNextVariableName to follow UEFI 2.7

2017-06-22 Thread Star Zeng 
"The size must be large enough to fit input string supplied in
VariableName buffer" is added in the description for VariableNameSize.
And two cases of EFI_INVALID_PARAMETER are added.
1. The input values of VariableName and VendorGuid are not a name and
   GUID of an existing variable.
2. Null-terminator is not found in the first VariableNameSize bytes of
   the input VariableName buffer.

This patch is to update comments for GetNextVariableName to follow them.

Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng 
---
 MdePkg/Include/Uefi/UefiSpec.h | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h
index eb662a35503c..0b84f4829749 100644
--- a/MdePkg/Include/Uefi/UefiSpec.h
+++ b/MdePkg/Include/Uefi/UefiSpec.h
@@ -661,7 +661,8 @@ EFI_STATUS
 /**
   Enumerates the current variable names.
 
-  @param[in, out]  VariableNameSize The size of the VariableName buffer.
+  @param[in, out]  VariableNameSize The size of the VariableName buffer. The 
size must be large
+enough to fit input string supplied in 
VariableName buffer.
   @param[in, out]  VariableName On input, supplies the last VariableName 
that was returned
 by GetNextVariableName(). On output, 
returns the Nullterminated
 string of the current variable.
@@ -675,6 +676,10 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETER VariableNameSize is NULL.
   @retval EFI_INVALID_PARAMETER VariableName is NULL.
   @retval EFI_INVALID_PARAMETER VendorGuid is NULL.
+  @retval EFI_INVALID_PARAMETER The input values of VariableName and 
VendorGuid are not a name and
+GUID of an existing variable.
+  @retval EFI_INVALID_PARAMETER Null-terminator is not found in the first 
VariableNameSize bytes of
+the input VariableName buffer.
   @retval EFI_DEVICE_ERROR  The variable could not be retrieved due to a 
hardware error.
 
 **/
-- 
2.7.0.windows.1

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Re: [edk2] [PATCH V3] MdeModulePkg/DxeCore: Fixed Interface returned by CoreOpenProtocol

2017-06-22 Thread Zeng, Star 
Amit,

If consumer calls OpenProtocol with Attributes = 
EFI_OPEN_PROTOCOL_TEST_PROTOCOL and Interface = NULL, and the protocol could 
not be found, how could the code with the patch work to assign *Interface = 
NULL?

And also UEFI spec has words Interface will be ignored if Attributes is 
EFI_OPEN_PROTOCOL_TEST_PROTOCOL.
“InterfaceSupplies the address where a pointer to the corresponding Protocol 
Interface is returned. NULL will be returned in *Interface if a structure is 
not associated with Protocol. This parameter is optional, and will be ignored 
if Attributes is EFI_OPEN_PROTOCOL_TEST_PROTOCOL.”

Thanks,
Star
From: Amit Kumar [mailto:amit...@samsung.com]
Sent: Thursday, June 22, 2017 8:54 PM
To: edk2-devel@lists.01.org; Gao, Liming ; Zeng, Star 
; Kinney, Michael D 
Cc: Tian, Feng 
Subject: RE: RE: [edk2] [PATCH V3] MdeModulePkg/DxeCore: Fixed Interface 
returned by CoreOpenProtocol


>>Should the code
>>
>>+// Return NULL Interface if Unsupported Protocol
>>+*Interface = NULL;
>>
>>be
>>
>>+if (Attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL) {
>>+  // Return NULL Interface if Unsupported Protocol
>>+  *Interface = NULL;
>>+}
>>
>>to cover the case Attributes = EFI_OPEN_PROTOCOL_TEST_PROTOCOL and Interface 
>>= NULL?
>>
>>
>>Thanks,
>>Star



Hello Star,



It looks like and you suggestion is apt and satisfies the use case scenarios of 
EFI_OPEN_PROTOCOL_TEST_PROTOCOL.

But if we talk of UEFI Spec 2.7, I think the patch is good enough .

I would like to have some suggestion here from all the concerned people, if 
agreed I would add these changes to the patch.



Thanks And Regards

Amit





- Original Message -

Sender : Zeng, Star >

Date : 2017-06-20 15:28 (GMT+5:30)

Title : RE: [edk2] [PATCH V3] MdeModulePkg/DxeCore: Fixed Interface returned by 
CoreOpenProtocol

To : Amit Kumar>, 
null>

CC : null>, 
null>



Should the code



+// Return NULL Interface if Unsupported Protocol

+*Interface = NULL;



be



+if (Attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL) {

+  // Return NULL Interface if Unsupported Protocol

+  *Interface = NULL;

+}



to cover the case Attributes = EFI_OPEN_PROTOCOL_TEST_PROTOCOL and Interface = 
NULL?





Thanks,

Star

-Original Message-

From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Amit 
Kumar

Sent: Monday, June 19, 2017 8:24 PM

To: edk2-devel@lists.01.org

Cc: Tian, Feng >

Subject: [edk2] [PATCH V3] MdeModulePkg/DxeCore: Fixed Interface returned by 
CoreOpenProtocol



Change Since v2:

1) Modified to use EFI_ERROR to get status code



Change since v1:

1) Fixed typo protocal to protocol

2) Fixed coding style



Modified source code to update Interface as per spec.

1) In case of Protocol is un-supported, interface should be returned NULL.

2) In case of any error, interface should not be modified.

3) In case of Test Protocol, interface is optional.



Contributed-under: TianoCore Contribution Agreement 1.0

Signed-off-by: Amit Kumar >

---

 MdeModulePkg/Core/Dxe/Hand/Handle.c | 24 

 1 file changed, 12 insertions(+), 12 deletions(-)



diff --git a/MdeModulePkg/Core/Dxe/Hand/Handle.c 
b/MdeModulePkg/Core/Dxe/Hand/Handle.c

index 1c25521..6de300f 100644

--- a/MdeModulePkg/Core/Dxe/Hand/Handle.c

+++ b/MdeModulePkg/Core/Dxe/Hand/Handle.c

@@ -1004,12 +1004,8 @@ CoreOpenProtocol (

   //

   // Check for invalid Interface

   //

-  if (Attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL) {

-if (Interface == NULL) {

-  return EFI_INVALID_PARAMETER;

-} else {

-  *Interface = NULL;

-}

+  if ((Attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL) && (Interface == NULL)) {

+return EFI_INVALID_PARAMETER;

   }



   //

@@ -1073,15 +1069,11 @@ CoreOpenProtocol (

   Prot = CoreGetProtocolInterface (UserHandle, Protocol);

   if (Prot == NULL) {

 Status = EFI_UNSUPPORTED;

+// Return NULL Interface if Unsupported Protocol

+*Interface = NULL;

 goto Done;

   }



-  //

-  // This is the protocol interface entry for this protocol

-  //

-  if (Attributes != EFI_OPEN_PROTOCOL_TEST_PROTOCOL) {

-*Interface = Prot->Interface;

-  }

   Status = EFI_SUCCESS;



   ByDriver= FALSE;

@@ -1175,6 +1167,14 @@ CoreOpenProtocol (

   }



 Done:

+

+  //

+  // This is the protocol interface entry for this protocol.

+  // In case of any Error, Interface should not be updated as per spec.

+  //

+  if (!EFI_ERROR (Status) && Attributes !=

Re: [edk2] [RFC] migration of OpenPlatformPkg to tianocore

2017-06-22 Thread Leif Lindholm 
On Thu, Jun 22, 2017 at 11:46:16AM +, Ard Biesheuvel wrote:
> On 22 June 2017 at 11:39, Ard Biesheuvel  wrote:
> > On 21 June 2017 at 17:44, Leif Lindholm  wrote:
> >> Hi all,
> >>
> >> I have now pushed updated versions of devel-OpenPlatformPkg branches
> >> to edk2-platforms and edk2-non-osi. I now also have a Readme.md at the
> >> top-level of edk2-platforms describing
> >>
> >> All the silly hacks are gone, and all platforms now build.
> >>
> >> I would really appreciate if people could have a look (and a play).
> >>
> >
> > Cello does not build atm in the new arrangement:
> >
> > build.py...
> >  : error 000E: File/directory not found in workspace
> > OpenPlatformPkg/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf
> > is not found in packages path:
> > /home/ard/build/edk2/../edk2-platforms
> > /home/ard/build/edk2/../edk2-non-osi
> 
> I also think the new PACKAGES_PATH breaks the inclusion of Dsdt.hex:
> 
> /home/ard/build/edk2-platforms/Silicon/AMD/Styx/AcpiTables/Dsdt.c:22:20:
> fatal error: Dsdt.hex: No such file or directory
>  #include 
> ^
> compilation terminated.
> 
> which resides at
> 
> Build/Cello/DEBUG_GCC5/AARCH64/edk2-platforms/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT/Dsdt.hex
> 
> but the include is defined as
> 
>   GCC:*_*_AARCH64_PLATFORM_FLAGS =
> -I$(BIN_DIR)/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT

You're not reading the documentation ;)  (Have a glance at Readme.md.)

Yes, this is the behaviour I had before this latest reshuffle. 
Mike's proposed (and functional) workaround is to not have "edk2" as
your WORKSPACE, but a common superdirectory of edk2, edk2-platforms
and edk2-non-osi.

Hopefully at some point we can get rid of this restriction, but for
now it's sort of necessary.

/
Leif
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Re: [edk2] [RFC] migration of OpenPlatformPkg to tianocore

2017-06-22 Thread Leif Lindholm 
On Thu, Jun 22, 2017 at 11:39:53AM +, Ard Biesheuvel wrote:
> On 21 June 2017 at 17:44, Leif Lindholm  wrote:
> > Hi all,
> >
> > I have now pushed updated versions of devel-OpenPlatformPkg branches
> > to edk2-platforms and edk2-non-osi. I now also have a Readme.md at the
> > top-level of edk2-platforms describing
> >
> > All the silly hacks are gone, and all platforms now build.
> >
> > I would really appreciate if people could have a look (and a play).
> >
> 
> Cello does not build atm in the new arrangement:
> 
> build.py...
>  : error 000E: File/directory not found in workspace
> OpenPlatformPkg/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf
> is not found in packages path:
> /home/ard/build/edk2/../edk2-platforms
> /home/ard/build/edk2/../edk2-non-osi

Yes, it will fail when you build with RENESAS_XHCI_FW_DIR set, until
such a point as that driver appears somewhere. (And since it doesn't
live anywhere right now, I didn't have anything to replace the path
with.)

Ray - could you respond to Ard's reply from 19 April please?
Subject:
"[PATCH] OptionRomPkg: add firmware loader driver for Renesas PD72020x"

I would prefer to keep generic device drivers out of EDK2 platforms,
but they need somewhere else to live.

Regards,

Leif
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Re: [edk2] [Patch V3] NetworkPkg/HttpBootDxe: Add HTTP Boot Callback protocol support.

2017-06-22 Thread Laszlo Ersek 
Hi,

On 06/20/17 03:23, Fu Siyuan wrote:
> V3 update:
> Fix X64 build error.
> 
> V2 update:
> Correct the file size print for IA32.
> 
> This patch updates the HTTP Boot driver to install a default HTTP Callback 
> protocol
> if the platform doesn't provide one. This callback implementation will print 
> the
> boot file download progress in percentage format.

This patch breaks the GCC build, because:

> diff --git a/NetworkPkg/HttpBootDxe/HttpBootImpl.c 
> b/NetworkPkg/HttpBootDxe/HttpBootImpl.c
> index cf6de80..56f5bab 100644
> --- a/NetworkPkg/HttpBootDxe/HttpBootImpl.c
> +++ b/NetworkPkg/HttpBootDxe/HttpBootImpl.c

> +**/
> +EFI_STATUS
> +HttpBootCallback (
> +  IN EFI_HTTP_BOOT_CALLBACK_PROTOCOL *This,
> +  IN EFI_HTTP_BOOT_CALLBACK_DATA_TYPEDataType,
> +  IN BOOLEAN Received,
> +  IN UINT32  DataLength,
> +  IN VOID*Data OPTIONAL
> +  )

the EFIAPI calling convention wasn't specified here, but

> +///
> +/// HTTP Boot Callback Protocol instance
> +///
> +GLOBAL_REMOVE_IF_UNREFERENCED 
> +EFI_HTTP_BOOT_CALLBACK_PROTOCOL  gHttpBootDxeHttpBootCallback = {
> +  HttpBootCallback
> +};

it is required here, for the EFI_HTTP_BOOT_CALLBACK function pointer type.

(Reported by Gerd's Jenkins CI.)

Thanks,
Laszlo
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Re: [edk2] [RFC] migration of OpenPlatformPkg to tianocore

2017-06-22 Thread Ard Biesheuvel 
On 22 June 2017 at 11:39, Ard Biesheuvel  wrote:
> On 21 June 2017 at 17:44, Leif Lindholm  wrote:
>> Hi all,
>>
>> I have now pushed updated versions of devel-OpenPlatformPkg branches
>> to edk2-platforms and edk2-non-osi. I now also have a Readme.md at the
>> top-level of edk2-platforms describing
>>
>> All the silly hacks are gone, and all platforms now build.
>>
>> I would really appreciate if people could have a look (and a play).
>>
>
> Cello does not build atm in the new arrangement:
>
> build.py...
>  : error 000E: File/directory not found in workspace
> OpenPlatformPkg/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf
> is not found in packages path:
> /home/ard/build/edk2/../edk2-platforms
> /home/ard/build/edk2/../edk2-non-osi

I also think the new PACKAGES_PATH breaks the inclusion of Dsdt.hex:

/home/ard/build/edk2-platforms/Silicon/AMD/Styx/AcpiTables/Dsdt.c:22:20:
fatal error: Dsdt.hex: No such file or directory
 #include 
^
compilation terminated.

which resides at

Build/Cello/DEBUG_GCC5/AARCH64/edk2-platforms/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT/Dsdt.hex

but the include is defined as

  GCC:*_*_AARCH64_PLATFORM_FLAGS =
-I$(BIN_DIR)/Silicon/AMD/Styx/AcpiTables/AcpiAml/OUTPUT
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Re: [edk2] [RFC] migration of OpenPlatformPkg to tianocore

2017-06-22 Thread Ard Biesheuvel 
On 21 June 2017 at 17:44, Leif Lindholm  wrote:
> Hi all,
>
> I have now pushed updated versions of devel-OpenPlatformPkg branches
> to edk2-platforms and edk2-non-osi. I now also have a Readme.md at the
> top-level of edk2-platforms describing
>
> All the silly hacks are gone, and all platforms now build.
>
> I would really appreciate if people could have a look (and a play).
>

Cello does not build atm in the new arrangement:

build.py...
 : error 000E: File/directory not found in workspace
OpenPlatformPkg/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf
is not found in packages path:
/home/ard/build/edk2/../edk2-platforms
/home/ard/build/edk2/../edk2-non-osi
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Re: [edk2] [PATCH 2/2] BaseTools/tools_def: AARCH64: disable LTO type mismatch warnings

2017-06-22 Thread Ard Biesheuvel 
On 21 June 2017 at 02:11, Gao, Liming  wrote:
> Reviewed-by: Liming Gao 
>

Thanks, pushed as 9ba8baae15ca


>>-Original Message-
>>From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
>>Sent: Wednesday, June 21, 2017 4:00 AM
>>To: Ard Biesheuvel 
>>Cc: edk2-devel@lists.01.org; Gao, Liming ; Zhu,
>>Yonghong ; ler...@redhat.com
>>Subject: Re: [PATCH 2/2] BaseTools/tools_def: AARCH64: disable LTO type
>>mismatch warnings
>>
>>On Tue, Jun 20, 2017 at 08:43:54PM +0200, Ard Biesheuvel wrote:
>>> On AARCH64, any code that may execute with the MMU off needs to be
>>built
>>> with -mstrict-align, given that unaligned accesses are not allowed unless
>>> the MMU is enabled. This does not only affect SEC and PEI modules, but
>>> also static libraries of the BASE type, which may be linked into such
>>> modules, as well as into modules of other types. As it turns out, the
>>> presence of -mstrict-align is reflected in the internal representations
>>> of the types defined in those libraries.
>>>
>>> When -fstrict-aliasing is passed to GCC, it assumes that pointers to
>>> objects of different types cannot refer to the same memory location, and
>>> attempts to exploit this fact when optimizing the code. Since such
>>> assumptions are only valid under very strict conditions which are not
>>> guaranteed to be met in EDK2, we disable this optimization by passing
>>> -fno-strict-aliasing by default.
>>
>>Just a comment - you don't necessarily have to update this excellent
>>commit mesage, but:
>>-fstrict-aliasing is GCC default, because it is a restriction in the C
>>language. Because it's a bit non-obvious, things can go hilariously
>>wrong in very non-obvious ways, and the potential optimization gains
>>are ulikely to be generally relevant, -fno-strict-aliasing is a
>>sensible thing to always have set (like we do).
>>
>>> When LTO is in effect, this applies equally to the code generation that
>>> may occur at link time, which is why the linker warns about unexpected
>>> differences in type definitions between the intermediate representations
>>> that are present in the object files being linked. This may result in
>>> warnings such as the one below, even if -fno-strict-aliasing is used:
>>>
>>>   MdePkg/Include/Library/BaseLib.h:1712:1:
>>>   warning: type of 'StrToGuid' does not match original declaration
>>>   [-Wlto-type-mismatch]
>>>StrToGuid (
>>>^
>>>   MdePkg/Library/BaseLib/SafeString.c:1506:1:
>>>   note: 'StrToGuid' was previously declared here
>>>StrToGuid (
>>>^
>>>   MdePkg/Library/BaseLib/SafeString.c:1506:1:
>>>   note: code may be misoptimized unless -fno-strict-aliasing is used
>>>
>>> This warning is inadvertently triggered when linking BASE libraries built
>>> with -mstrict-align into modules of types other than SEC or PEI, since the
>>> types are subtly different, even though the use of code that maintains
>>> strict alignment in a module that does not care about this is unlikely to
>>> cause problems. And even if it did, it would still only affect code built
>>> with -fstrict-aliasing enabled, which we disable unconditionally. So let's
>>> just silence the warning by passing -Wno-lto-type-mismatch.
>>>
>>> Contributed-under: TianoCore Contribution Agreement 1.0
>>> Signed-off-by: Ard Biesheuvel 
>>
>>Reviewed-by: Leif Lindholm 
>>
>>> ---
>>>  BaseTools/Conf/tools_def.template | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/BaseTools/Conf/tools_def.template
>>b/BaseTools/Conf/tools_def.template
>>> index 7a58ce365ed2..9a3ba9defb12 100755
>>> --- a/BaseTools/Conf/tools_def.template
>>> +++ b/BaseTools/Conf/tools_def.template
>>> @@ -5407,7 +5407,7 @@ RELEASE_GCC5_ARM_DLINK_FLAGS =
>>DEF(GCC5_ARM_DLINK_FLAGS) -flto -Os -L$(WORKS
>>>DEBUG_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
>>>
>>>  RELEASE_GCC5_AARCH64_CC_FLAGS= DEF(GCC5_AARCH64_CC_FLAGS) -
>>flto -Wno-unused-but-set-variable -mcmodel=tiny -fomit-frame-pointer
>>> -RELEASE_GCC5_AARCH64_DLINK_FLAGS =
>>DEF(GCC5_AARCH64_DLINK_FLAGS) -flto -Os -
>>L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-
>>through=-llto-aarch64
>>> +RELEASE_GCC5_AARCH64_DLINK_FLAGS =
>>DEF(GCC5_AARCH64_DLINK_FLAGS) -flto -Os -
>>L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-
>>through=-llto-aarch64 -Wno-lto-type-mismatch
>>>
>>>NOOPT_GCC5_AARCH64_CC_FLAGS= DEF(GCC5_AARCH64_CC_FLAGS) -
>>O0 -mcmodel=small
>>>NOOPT_GCC5_AARCH64_DLINK_FLAGS =
>>DEF(GCC5_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 -O0
>>> --
>>> 2.7.4
>>>
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Re: [edk2] [PATCH 1/2] BaseTools/tools_def GCC: ARM/AARCH64: replace -save-temps with -pipe

2017-06-22 Thread Ard Biesheuvel 
On 21 June 2017 at 12:42, Leif Lindholm  wrote:
> On Wed, Jun 21, 2017 at 01:31:15PM +0200, Ard Biesheuvel wrote:
>> > "-pipe" isn't used anywhere else in "tools_def.template". Can we imagine
>> > a platform where cross-compiling to aarch64 with gcc works otherwise,
>> > but "-pipe" might break that? Cygwin perhaps? (No clue, honestly.)
>> >
>> > For consistency with the rest of "tools_def.template", I'd suggest
>> > simply dropping "-save-temps", and thinking about "-pipe" separately
>> > (and then for all the GCC toolchains and for all arches). But, I don't
>> > feel particularly strongly about this.
>> >
>>
>> Yeah, that's a fair point. The fact that -save-temps is specific to
>> ARM does not mean we should perpetuate that with -pipe.
>>
>> Leif, if you agree, I will drop the addition of -pipe from this patch,
>> and we can revisit it later for all GCC flavors.
>
> Much as I would like to find out if there really are any platforms
> that still have issues with -pipe (in which case, why wouldn't GCC
> just use temp files anyway?), I guess that is a sensible approach.
>
> Reviewed-by: Leif Lindholm 
> for the dropping of -save-temps.
>

Thanks, pushed as fa6080138c08
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[edk2] [PATCH] MdePkg/IndustryStandard: update ACPI/IORT definitions to revision C

2017-06-22 Thread Ard Biesheuvel 
This updates the IORT header to include the definitions that were added
in revision C of the IORT spec that was made public recently.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel 
---
 MdePkg/Include/IndustryStandard/IoRemappingTable.h | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/IoRemappingTable.h 
b/MdePkg/Include/IndustryStandard/IoRemappingTable.h
index 430df3b956bb..c113afdd2784 100644
--- a/MdePkg/Include/IndustryStandard/IoRemappingTable.h
+++ b/MdePkg/Include/IndustryStandard/IoRemappingTable.h
@@ -1,7 +1,7 @@
 /** @file
-  ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049B
+  ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049C
 
-  
http://infocenter.arm.com/help/topic/com.arm.doc.den0049b/DEN0049B_IO_Remapping_Table.pdf
+  
http://infocenter.arm.com/help/topic/com.arm.doc.den0049c/DEN0049C_IO_Remapping_Table.pdf
 
   Copyright (c) 2017, Linaro Limited. All rights reserved.
 
@@ -26,6 +26,7 @@
 #define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2
 #define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3
 #define EFI_ACPI_IORT_TYPE_SMMUv3   0x4
+#define EFI_ACPI_IORT_TYPE_PMCG 0x5
 
 #define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA   BIT0
 
@@ -41,6 +42,8 @@
 #define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1
 #define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400 0x2
 #define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500 0x3
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2  0x5
 
 #define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0
 #define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALKBIT1
@@ -178,6 +181,18 @@ typedef struct {
   UINT32  Sync;
 } EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
 
+///
+/// Node type 5: PMCG node
+///
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE  Node;
+
+  UINT64  Base;
+  UINT32  OverflowInterruptGsiv;
+  UINT32  NodeReference;
+//EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE  OverflowInterruptMsiMapping[1];
+} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;
+
 #pragma pack()
 
 #endif
-- 
2.9.3

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[edk2] [staging/cadence-aarch64 PATCH v3 0/6] CadencePkg: Add package for Cadence hardware IP support.

2017-06-22 Thread Scott Telford 
Revised patchset following comments from Leif and Ard.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford 

Scott Telford (6):
  CadencePkg: Add libraries for Cadence CSP platform.
  CadencePkg: Add library for Cadence UART.
  CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex.
  CadencePkg: Add SEC phase implementation for Cadence CSP platform.
  CadencePkg: Add ACPI tables for Cadence CSP platform.
  CadencePkg: Add .dsc, .fdf and .dec files for Cadence CSP platform.

 CadencePkg/AcpiTables/AcpiTables.inf   |  50 ++
 CadencePkg/AcpiTables/CspPlatform.h|  46 ++
 CadencePkg/AcpiTables/Dsdt.asl | 307 ++
 CadencePkg/AcpiTables/Fadt.aslc|  87 +++
 CadencePkg/AcpiTables/Gtdt.aslc|  80 +++
 CadencePkg/AcpiTables/Madt.aslc|  71 +++
 CadencePkg/AcpiTables/Mcfg.aslc|  76 +++
 CadencePkg/CadenceCsp.dsc  | 672 +
 CadencePkg/CadenceCsp.fdf  | 412 +
 CadencePkg/CadenceCspPkg.dec   |  55 ++
 CadencePkg/Include/Library/CspSerialPortLib.h  |  86 +++
 CadencePkg/Include/Library/CspSysReg.h |  37 ++
 .../CadenceCspLib/AArch64/ArmPlatformHelper.S  |  55 ++
 CadencePkg/Library/CadenceCspLib/CadenceCspLib.c   | 133 
 CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf |  68 +++
 .../Library/CadenceCspLib/CadenceCspLibMem.c   | 116 
 .../Library/CadenceCspLib/CadenceCspLibSec.inf |  52 ++
 .../CadenceCspResetSystemLib.c |  82 +++
 .../CadenceCspResetSystemLib.inf   |  40 ++
 .../Library/CadenceCspSecLib/AArch64/CspBoot.S |  49 ++
 .../Library/CadenceCspSecLib/AArch64/GicV3.S   |  67 ++
 .../Library/CadenceCspSecLib/CadenceCspSecLib.inf  |  44 ++
 CadencePkg/Library/CadenceCspSecLib/CspSec.c   |  79 +++
 .../CadenceCspSerialPortLib/CspSerialPortLib.c | 523 
 .../CadenceCspSerialPortLib/CspSerialPortLib.inf   |  52 ++
 .../CadenceCspSerialPortLib/CspSerialPortLib.uni   | Bin 0 -> 1622 bytes
 .../Library/CadencePciHostBridgeLib/CdnsPci.c  | 149 +
 .../Library/CadencePciHostBridgeLib/CdnsPci.h  |  88 +++
 .../CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c | 188 ++
 .../CdnsPciHostBridgeLib.inf   |  73 +++
 CadencePkg/Sec/AArch64/Arch.c  |  25 +
 CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S|  27 +
 CadencePkg/Sec/AArch64/Helper.S|  93 +++
 CadencePkg/Sec/AArch64/SecEntryPoint.S | 139 +
 CadencePkg/Sec/Sec.c   | 335 ++
 CadencePkg/Sec/Sec.inf |  85 +++
 CadencePkg/Sec/SecInternal.h   | 105 
 37 files changed, 4646 insertions(+)
 create mode 100644 CadencePkg/AcpiTables/AcpiTables.inf
 create mode 100644 CadencePkg/AcpiTables/CspPlatform.h
 create mode 100644 CadencePkg/AcpiTables/Dsdt.asl
 create mode 100644 CadencePkg/AcpiTables/Fadt.aslc
 create mode 100644 CadencePkg/AcpiTables/Gtdt.aslc
 create mode 100644 CadencePkg/AcpiTables/Madt.aslc
 create mode 100644 CadencePkg/AcpiTables/Mcfg.aslc
 create mode 100644 CadencePkg/CadenceCsp.dsc
 create mode 100644 CadencePkg/CadenceCsp.fdf
 create mode 100644 CadencePkg/CadenceCspPkg.dec
 create mode 100644 CadencePkg/Include/Library/CspSerialPortLib.h
 create mode 100644 CadencePkg/Include/Library/CspSysReg.h
 create mode 100644 CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
 create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
 create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
 create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
 create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
 create mode 100644 
CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
 create mode 100644 
CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
 create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
 create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
 create mode 100644 CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
 create mode 100644 CadencePkg/Library/CadenceCspSecLib/CspSec.c
 create mode 100644 
CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
 create mode 100644 
CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
 create mode 100644 
CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni
 create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
 create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
 create mode 100644 
CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
 create mode 100644 
CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf

[edk2] [staging/cadence-aarch64 PATCH v3 2/6] CadencePkg: Add library for Cadence UART.

2017-06-22 Thread Scott Telford 
Add serial port library to support the Cadence IP6528 UART used in the
Cadence CSP platform.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford 
---
 CadencePkg/Include/Library/CspSerialPortLib.h  |  86 
 .../CadenceCspSerialPortLib/CspSerialPortLib.c | 523 +
 .../CadenceCspSerialPortLib/CspSerialPortLib.inf   |  52 ++
 .../CadenceCspSerialPortLib/CspSerialPortLib.uni   | Bin 0 -> 1622 bytes
 4 files changed, 661 insertions(+)
 create mode 100644 CadencePkg/Include/Library/CspSerialPortLib.h
 create mode 100644 
CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
 create mode 100644 
CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
 create mode 100644 
CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni

diff --git a/CadencePkg/Include/Library/CspSerialPortLib.h 
b/CadencePkg/Include/Library/CspSerialPortLib.h
new file mode 100644
index 000..46fa0d8
--- /dev/null
+++ b/CadencePkg/Include/Library/CspSerialPortLib.h
@@ -0,0 +1,86 @@
+/** @file
+*  Serial Port Library for Cadence IP6528 UART.
+*  Copyright (c) 2017, Cadence Design Systems. All rights reserved.
+*
+*  This program and the accompanying materials are licensed and made
+*  available under the terms and conditions of the BSD License which
+*  accompanies this distribution.  The full text of the license may be
+*  found at http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef __CSP_SERIAL_PORT_LIB_H__
+#define __CSP_SERIAL_PORT_LIB_H__
+
+// Cadence UART register offsets
+#define CSP_UART_CR 0x00  // Control
+#define CSP_UART_MR 0x04  // Mode
+#define CSP_UART_IER0x08  // Interrupt enable
+#define CSP_UART_IDR0x0C  // Interrupt disable
+#define CSP_UART_IMR0x10  // Interrupt mask
+#define CSP_UART_CISR   0x14  // Channel interrupt status
+#define CSP_UART_BRGR   0x18  // Baud rate generator
+#define CSP_UART_RTOR   0x1C  // Rx Timeout
+#define CSP_UART_RTRIG  0x20  // Rx FIFO trigger level
+#define CSP_UART_MCR0x24  // Modem control
+#define CSP_UART_MSR0x28  // Modem status
+#define CSP_UART_CSR0x2C  // Channel status
+#define CSP_UART_FIFO   0x30  // FIFO (Tx/Rx)
+#define CSP_UART_BDIV   0x34  // Baud rate divider
+#define CSP_UART_FDEL   0x38  // Flow delay
+#define CSP_UART_PMIN   0x3C  // IR min received pulse width
+#define CSP_UART_PWID   0x40  // IR transmitted pulse Width
+#define CSP_UART_TTRIG  0x44  // Tx FIFO trigger level
+
+
+// Control Register Bit Definitions
+#define CSP_UART_CR_STPBRK  0x0100  // Stop Tx break
+#define CSP_UART_CR_STTBRK  0x0080  // Start Tx break
+#define CSP_UART_CR_RSTTO   0x0040  // Restart Rx timeout Counter
+#define CSP_UART_CR_TXDIS   0x0020  // Tx disable
+#define CSP_UART_CR_TXEN0x0010  // Tx enable
+#define CSP_UART_CR_RXDIS   0x0008  // Rx disable
+#define CSP_UART_CR_RXEN0x0004  // Rx enable
+#define CSP_UART_CR_TXRES   0x0002  // Tx reset
+#define CSP_UART_CR_RXRES   0x0001  // Rx reset
+
+
+// Mode register bit definitions
+#define CSP_UART_MR_CLKS0x0001  // Baud rate /8 pre-scalar
+#define CSP_UART_MR_CHMODE_LLB  0x0200  // Local loopback mode
+#define CSP_UART_MR_CHMODE_NML  0x  // Normal mode
+
+#define CSP_UART_MR_CHRL_6  0x0006  // 6 databits
+#define CSP_UART_MR_CHRL_7  0x0004  // 7 databits
+#define CSP_UART_MR_CHRL_8  0x  // 8 databits
+
+#define CSP_UART_MR_PAR_NONE0x0020  // No parity mode
+#define CSP_UART_MR_PAR_MARK0x0018  // Mark parity mode
+#define CSP_UART_MR_PAR_SPACE   0x0010  // Space parity mode
+#define CSP_UART_MR_PAR_ODD 0x0008  // Odd parity mode
+#define CSP_UART_MR_PAR_EVEN0x  // Even parity mode
+
+#define CSP_UART_MR_NBSTOP_10x  // 1 stop bit
+#define CSP_UART_MR_NBSTOP_20x0080  // 2 stop bits
+
+// Modem control register bit definitions
+#define CSP_UART_MCR_DTR0x0001  // DTR control
+#define CSP_UART_MCR_RTS0x0002  // RTS control
+#define CSP_UART_MCR_FCM0x0020  // Auto flow control
+
+// Modem status register bit definitions
+#define CSP_UART_MSR_FCMS   0x0100  // Auto flow control status
+#define CSP_UART_MSR_DCD0x0080  // DCD status
+#define CSP_UART_MSR_RI 0x0040  // RI status
+#define CSP_UART_MSR_DSR0x0020  // DSR status
+#define CSP_UART_MSR_CTS

[edk2] [staging/cadence-aarch64 PATCH v3 4/6] CadencePkg: Add SEC phase implementation for Cadence CSP platform.

2017-06-22 Thread Scott Telford 
Add SEC phase implementation for Cadence CSP platform configured with
a single Cortex-A53 processor and GIC-500.

Based on ArmPlatformPkg/Sec, with required parts of
ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib integrated (both now deleted
from edk2 master).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford 
---
 CadencePkg/Sec/AArch64/Arch.c   |  25 +++
 CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S |  27 +++
 CadencePkg/Sec/AArch64/Helper.S |  93 
 CadencePkg/Sec/AArch64/SecEntryPoint.S  | 139 
 CadencePkg/Sec/Sec.c| 335 
 CadencePkg/Sec/Sec.inf  |  85 +++
 CadencePkg/Sec/SecInternal.h| 105 +
 7 files changed, 809 insertions(+)
 create mode 100644 CadencePkg/Sec/AArch64/Arch.c
 create mode 100644 CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
 create mode 100644 CadencePkg/Sec/AArch64/Helper.S
 create mode 100644 CadencePkg/Sec/AArch64/SecEntryPoint.S
 create mode 100644 CadencePkg/Sec/Sec.c
 create mode 100644 CadencePkg/Sec/Sec.inf
 create mode 100644 CadencePkg/Sec/SecInternal.h

diff --git a/CadencePkg/Sec/AArch64/Arch.c b/CadencePkg/Sec/AArch64/Arch.c
new file mode 100644
index 000..6e7d58e
--- /dev/null
+++ b/CadencePkg/Sec/AArch64/Arch.c
@@ -0,0 +1,25 @@
+/** @file
+*
+*  Copyright (c) 2013, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#include 
+
+VOID
+EFIAPI
+ArmSecArchTrustzoneInit (
+  VOID
+  )
+{
+  // Do not trap any access to Floating Point and Advanced SIMD in EL3.
+  ArmWriteCptr (0);
+}
diff --git a/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S 
b/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
new file mode 100644
index 000..531de63
--- /dev/null
+++ b/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
@@ -0,0 +1,27 @@
+#--
+#
+# Copyright (c) 2013 - 2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD 
Licese
+# which accompanies this distribution.  The full text of the license may be 
foun at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#--
+
+#include 
+
+ASM_FUNC(ArmReadCpuExCr)
+  mrs   x0, S3_1_c15_c2_1
+  ret
+
+ASM_FUNC(ArmWriteCpuExCr)
+  msr   S3_1_c15_c2_1, x0
+  dsb   sy
+  isb
+  ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/CadencePkg/Sec/AArch64/Helper.S b/CadencePkg/Sec/AArch64/Helper.S
new file mode 100644
index 000..3b58e12
--- /dev/null
+++ b/CadencePkg/Sec/AArch64/Helper.S
@@ -0,0 +1,93 @@
+#
+#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http:#opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+#===
+
+#include 
+#include 
+
+#start of the code section
+.text
+.align 3
+
+GCC_ASM_EXPORT(SwitchToNSExceptionLevel1)
+GCC_ASM_EXPORT(enter_monitor_mode)
+GCC_ASM_EXPORT(return_from_exception)
+GCC_ASM_EXPORT(copy_cpsr_into_spsr)
+GCC_ASM_EXPORT(set_non_secure_mode)
+
+// Switch from EL3 to NS-EL1
+ASM_PFX(SwitchToNSExceptionLevel1):
+   // Now setup our EL1. Controlled by EL2 config on Model
+   mrs x0, hcr_el2// Read EL2 Hypervisor configuration Register
+   orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
+
+   // Send all interrupts to their respective Exception levels for EL2
+   and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable 
virtual FIQ, IRQ, SError and Abort
+   msr hcr_el2, x0// Write back our settings
+
+   msr cptr_el2, xzr  // Disable copro traps to EL2
+
+   msr sctlr_el2, xzr
+
+   // Enable architected timer access
+   mrs x0, cnthctl_el2
+   orr x0, x0, #3

[edk2] [staging/cadence-aarch64 PATCH v3 6/6] CadencePkg: Add .dsc, .fdf and .dec files for Cadence CSP platform.

2017-06-22 Thread Scott Telford 
Add .dsc, .fdf and .dec files for a Cadence CSP platform configured
with a single Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root
Complex.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford 
---
 CadencePkg/CadenceCsp.dsc| 672 +++
 CadencePkg/CadenceCsp.fdf| 412 ++
 CadencePkg/CadenceCspPkg.dec |  55 
 3 files changed, 1139 insertions(+)
 create mode 100644 CadencePkg/CadenceCsp.dsc
 create mode 100644 CadencePkg/CadenceCsp.fdf
 create mode 100644 CadencePkg/CadenceCspPkg.dec

diff --git a/CadencePkg/CadenceCsp.dsc b/CadencePkg/CadenceCsp.dsc
new file mode 100644
index 000..eb98a29
--- /dev/null
+++ b/CadencePkg/CadenceCsp.dsc
@@ -0,0 +1,672 @@
+#
+#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+#  Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME  = CadenceCsp
+  PLATFORM_GUID  = 262f8c6b-047b-4afe-b317-7c90b795beb8
+  PLATFORM_VERSION   = 0.1
+  DSC_SPECIFICATION  = 1.25
+!ifdef $(EDK2_OUT_DIR)
+  OUTPUT_DIRECTORY   = $(EDK2_OUT_DIR)
+!else
+  OUTPUT_DIRECTORY   = Build/CadenceCsp
+!endif
+  SUPPORTED_ARCHITECTURES= AARCH64
+  BUILD_TARGETS  = DEBUG|RELEASE
+  SKUID_IDENTIFIER   = DEFAULT
+  FLASH_DEFINITION   = CadencePkg/CadenceCsp.fdf
+
+  SECURE_BOOT_ENABLE  = FALSE
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+  # Virtio Support
+  VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
+  
VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+!endif
+
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+  
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  
ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
+  
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+  #
+  # Assume everything is fixed at build
+  #
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+  # Networking

[edk2] [staging/cadence-aarch64 PATCH v3 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex.

2017-06-22 Thread Scott Telford 
Add PciHostBridgeLib implementation for the Cadence PCIe Root Complex.
This library is derived from
Platforms/ARM/Juno/Library/JunoPciHostBridgeLib in OpenPlatformPkg.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford 
---
 .../Library/CadencePciHostBridgeLib/CdnsPci.c  | 149 
 .../Library/CadencePciHostBridgeLib/CdnsPci.h  |  88 ++
 .../CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c | 188 +
 .../CdnsPciHostBridgeLib.inf   |  73 
 4 files changed, 498 insertions(+)
 create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
 create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
 create mode 100644 
CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
 create mode 100644 
CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf

diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c 
b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
new file mode 100644
index 000..3114843
--- /dev/null
+++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
@@ -0,0 +1,149 @@
+/** @file
+*  Initialize the Cadence PCIe Root complex
+*
+*  Copyright (c) 2017, Cadence Design Systems. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "CdnsPci.h"
+
+STATIC
+VOID
+CdnsPciConfigRegion (
+  EFI_CPU_IO2_PROTOCOL *CpuIo,
+  IN UINT32 Region,
+  IN UINT32 Descriptor,
+  IN UINT32 TransAddr,
+  IN UINT32 TransAddrBits,
+  IN UINT32 BaseAddr,
+  IN UINT32 BaseAddrBits
+  )
+{
+  UINTN RegionBaseAddr = PCIE_AXI + (Region * PCIE_AXI_REGION_OFF);
+
+  PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_TRANS0_OFF,
+ TransAddr | TransAddrBits);
+  PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_DESC_OFF,
+ Descriptor);
+  PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_BASE0_OFF,
+ BaseAddr | BaseAddrBits);
+}
+
+STATIC
+VOID
+CdnsPciRegInit(
+  EFI_CPU_IO2_PROTOCOL*CpuIo
+)
+{
+  UINT32  Value;
+
+  // Setup the class code as PCIe Host Bridge.
+  PCIE_ROOTPORT_WRITE32 (PCIE_RP + PCIE_PCI_CLASSCODE, PCIE_BRIDGE_CLASSCODE);
+
+  // Set up the BARs via the Root Port registers
+  PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value);
+  PCIE_ROOTPORT_WRITE32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value | (1 << 
PCIE_RCBARPIE));
+
+  // Allow incoming writes
+  PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR0_IB, PCIE_AXI_BITS_32);
+  PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR1_IB, PCIE_AXI_BITS_32);
+  PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_NO_BAR_IB, PCIE_AXI_BITS_32);
+
+  // Set up region 0 for Type 0 write (bus 0 and 1), size 2MB
+  CdnsPciConfigRegion (
+  CpuIo,
+  0,
+  PCIE_AXI_DESC_TYPE0,
+  PCIE_ECAM_BASE,
+  PCIE_AXI_BITS_25,
+  0,
+  PCIE_AXI_BITS_21
+  );
+
+  // Set up region 1 for Type 1 writes (bus 2 upwards), size (32-2)MB
+  CdnsPciConfigRegion(
+  CpuIo,
+  1,
+  PCIE_AXI_DESC_TYPE1,
+  PCIE_ECAM_BASE + (2*PCIE_BUS_SIZE),
+  PCIE_AXI_BITS_25,
+  2*PCIE_BUS_SIZE,
+  PCIE_AXI_BITS_25
+  );
+
+  // Set up region 2 for memory write, size 16MB
+  CdnsPciConfigRegion(
+  CpuIo,
+  2,
+  PCIE_AXI_DESC_MEM,
+  PCIE_MEM32_BASE,
+  PCIE_AXI_BITS_25,
+  (PCIE_MEM32_BASE - PCIE_ECAM_BASE),
+  PCIE_AXI_BITS_24
+  );
+
+  // Set up region 3 for IO write, size 16MB
+  CdnsPciConfigRegion(
+  CpuIo,
+  3,
+  PCIE_AXI_DESC_IO,
+  PCIE_IO_BASE,
+  PCIE_AXI_BITS_25,
+  (PCIE_IO_BASE - PCIE_ECAM_BASE),
+  PCIE_AXI_BITS_24
+  );
+}
+
+EFI_STATUS
+HWPciRbInit (
+  IN EFI_HANDLEImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  UINT32  Count;
+  EFI_CPU_IO2_PROTOCOL*CpuIo;
+  EFI_STATUS  Status;
+  UINT32  Value;
+
+  PCI_TRACE ("HWPciRbInit()");
+
+  PCI_TRACE ("PCIe Setting up Address Translation");
+
+  Status = gBS->LocateProtocol (, NULL,
+  (VOID **));
+  ASSERT_EFI_ERROR (Status);
+
+  // Check for link up
+  for (Count = 0; Count < PCIE_LINK_TIMEOUT_COUNT; Count++) {
+gBS->Stall (PCIE_LINK_TIMEOUT_WAIT_US);
+PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_LINK_CTRL_STATUS, Value);
+if (Value &

[edk2] [staging/cadence-aarch64 PATCH v3 1/6] CadencePkg: Add libraries for Cadence CSP platform.

2017-06-22 Thread Scott Telford 
Add libraries (CadenceCspLib, CadenceCspSecLib,
CadenceCspResetSystemLib) to support the Cadence Configurable System
Platform (CSP) configured with a single ARM Cortex-A53, GIC-500,
Cadence UART and Cadence PCIe Root Complex.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford 
---
 CadencePkg/Include/Library/CspSysReg.h |  37 ++
 .../CadenceCspLib/AArch64/ArmPlatformHelper.S  |  55 +
 CadencePkg/Library/CadenceCspLib/CadenceCspLib.c   | 133 +
 CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf |  68 +++
 .../Library/CadenceCspLib/CadenceCspLibMem.c   | 116 ++
 .../Library/CadenceCspLib/CadenceCspLibSec.inf |  52 
 .../CadenceCspResetSystemLib.c |  82 +
 .../CadenceCspResetSystemLib.inf   |  40 +++
 .../Library/CadenceCspSecLib/AArch64/CspBoot.S |  49 
 .../Library/CadenceCspSecLib/AArch64/GicV3.S   |  67 +++
 .../Library/CadenceCspSecLib/CadenceCspSecLib.inf  |  44 +++
 CadencePkg/Library/CadenceCspSecLib/CspSec.c   |  79 
 12 files changed, 822 insertions(+)
 create mode 100644 CadencePkg/Include/Library/CspSysReg.h
 create mode 100644 CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
 create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
 create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
 create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
 create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
 create mode 100644 
CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
 create mode 100644 
CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
 create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
 create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
 create mode 100644 CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
 create mode 100644 CadencePkg/Library/CadenceCspSecLib/CspSec.c

diff --git a/CadencePkg/Include/Library/CspSysReg.h 
b/CadencePkg/Include/Library/CspSysReg.h
new file mode 100644
index 000..4d3ac925
--- /dev/null
+++ b/CadencePkg/Include/Library/CspSysReg.h
@@ -0,0 +1,37 @@
+/** @file
+*  Cadence CSP system register offsets.
+*  Copyright (c) 2017, Cadence Design Systems. All rights reserved.
+*
+*  This program and the accompanying materials are licensed and made
+*  available under the terms and conditions of the BSD License which
+*  accompanies this distribution.  The full text of the license may be
+*  found at http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef __CSP_SYS_REG_H__
+#define __CSP_SYS_REG_H__
+
+// Cadence CSP system register offsets
+#define CSP_SYSREG_VERSION  0x00
+#define CSP_SYSREG_CPU_FREQ 0x04
+#define CSP_SYSREG_STATUS   0x08
+#define CSP_SYSREG_RUN_STALL0x0C
+#define CSP_SYSREG_SW_RESET 0x10
+#define CSP_SYSREG_CORE1_RESET  0x14
+#define CSP_SYSREG_SCRATCH_REG_00x18
+#define CSP_SYSREG_PROC_INTERRUPT   0x1C
+#define CSP_SYSREG_SCRATCH_REG_10x20
+#define CSP_SYSREG_SCRATCH_REG_20x24
+#define CSP_SYSREG_SCRATCH_REG_30x28
+#define CSP_SYSREG_SCRATCH_REG_40x2C
+#define CSP_SYSREG_SCRATCH_REG_50x30
+#define CSP_SYSREG_SCRATCH_REG_60x34
+#define CSP_SYSREG_SET_INTERRUPT0x38
+#define CSP_SYSREG_CLR_INTERRUPT0x3C
+#define CSP_SYSREG_DIP_SWITCHES 0x40
+
+#endif
diff --git a/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S 
b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
new file mode 100644
index 000..8832673
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
@@ -0,0 +1,55 @@
+#
+#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+#
+
+#include 
+#include 
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+  ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  MOV32  (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+  ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+  and   x0, x0, x1
+  MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+  cmp   w0, w1
+  b.ne  1f
+  mov

[edk2] [staging/cadence-aarch64 PATCH v3 5/6] CadencePkg: Add ACPI tables for Cadence CSP platform.

2017-06-22 Thread Scott Telford 
Add ACPI tables for Cadence CSP platform configured with a single
Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford 
---
 CadencePkg/AcpiTables/AcpiTables.inf |  50 ++
 CadencePkg/AcpiTables/CspPlatform.h  |  46 ++
 CadencePkg/AcpiTables/Dsdt.asl   | 307 +++
 CadencePkg/AcpiTables/Fadt.aslc  |  87 ++
 CadencePkg/AcpiTables/Gtdt.aslc  |  80 +
 CadencePkg/AcpiTables/Madt.aslc  |  71 
 CadencePkg/AcpiTables/Mcfg.aslc  |  76 +
 7 files changed, 717 insertions(+)
 create mode 100644 CadencePkg/AcpiTables/AcpiTables.inf
 create mode 100644 CadencePkg/AcpiTables/CspPlatform.h
 create mode 100644 CadencePkg/AcpiTables/Dsdt.asl
 create mode 100644 CadencePkg/AcpiTables/Fadt.aslc
 create mode 100644 CadencePkg/AcpiTables/Gtdt.aslc
 create mode 100644 CadencePkg/AcpiTables/Madt.aslc
 create mode 100644 CadencePkg/AcpiTables/Mcfg.aslc

diff --git a/CadencePkg/AcpiTables/AcpiTables.inf 
b/CadencePkg/AcpiTables/AcpiTables.inf
new file mode 100644
index 000..4f79485
--- /dev/null
+++ b/CadencePkg/AcpiTables/AcpiTables.inf
@@ -0,0 +1,50 @@
+## @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
+#  Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = CspAcpiTables
+  FILE_GUID  = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE= USER_DEFINED
+  VERSION_STRING = 1.0
+
+[Sources]
+  Dsdt.asl
+  Fadt.aslc
+  Gtdt.aslc
+  Madt.aslc
+  Mcfg.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  CadencePkg/CadenceCspPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gCadenceCspTokenSpaceGuid.PcdCspSerialBase
+  gCadenceCspTokenSpaceGuid.PcdCspSerialSize
diff --git a/CadencePkg/AcpiTables/CspPlatform.h 
b/CadencePkg/AcpiTables/CspPlatform.h
new file mode 100644
index 000..d3afe9e
--- /dev/null
+++ b/CadencePkg/AcpiTables/CspPlatform.h
@@ -0,0 +1,46 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*  Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+*
+**/
+
+
+#ifndef _CSP_PLATFORM_H_
+#define _CSP_PLATFORM_H_
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_CSP_OEM_ID   'C','D','N','S',' ',' '   // OEMID 6 
bytes long
+#define EFI_ACPI_CSP_OEM_TABLE_ID SIGNATURE_64('C','S','P',' ',' ',' ',' 
',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_CSP_OEM_REVISION 0x0002
+#define EFI_ACPI_CSP_CREATOR_ID   SIGNATURE_32('C','D','N','S')
+#define EFI_ACPI_CSP_CREATOR_REVISION 0x0001
+
+// A macro to initialise the common header part of EFI ACPI tables as defined 
by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) {  \
+Signature,  /* UINT32  Signature */   \
+sizeof (Type),  /* UINT32  Length */  \
+Revision,   /* UINT8   Revision */\
+0,  /* UINT8   Checksum */\
+{ EFI_ACPI_CSP_OEM_ID },/* UINT8   OemId[6] */\
+EFI_ACPI_CSP_OEM_TABLE_ID,  /* UINT64  OemTableId */  \
+EFI_ACPI_CSP_OEM_REVISION,  /* UINT32  OemRevision */ \

Re: [edk2] [staging/cadence-aarch64 PATCH v2 5/6] CadencePkg: Add ACPI tables for Cadence CSP platform.

2017-06-22 Thread Scott Telford 
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: 05 June 2017 16:40
> To: Scott Telford 
> Cc: edk2-devel@lists.01.org ; Leif Lindholm
> ; Graeme Gregory ;
> af...@apple.com; Kinney, Michael D 
> Subject: Re: [staging/cadence-aarch64 PATCH v2 5/6] CadencePkg: Add ACPI
> tables for Cadence CSP platform.
> 

> 
> > +Device (LNKA)
> > +{
> > +  Name (_HID, Eisaid ("PNP0C0F"))
> > +  Name (_UID, 1)
> > +  Name(_PRS, ResourceTemplate(){
> > +Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 
> > 46 }
> > +  })
> > +  Method(_DIS) {}
> > +  Method(_CRS) { Return (_PRS) }
> > +  Method(_SRS, 1) {}
> > +}
> > +Device (LNKB)
> > +{
> > +  Name (_HID, Eisaid ("PNP0C0F"))
> > +  Name (_UID, 1)
> > +  Name(_PRS, ResourceTemplate(){
> > +Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 
> > 46 }
> > +  })
> > +  Method(_DIS) {}
> > +  Method(_CRS) { Return (_PRS) }
> > +  Method(_SRS, 1) {}
> > +}
> > +Device (LNKC)
> > +{
> > +  Name (_HID, Eisaid ("PNP0C0F"))
> > +  Name (_UID, 1)
> > +  Name(_PRS, ResourceTemplate(){
> > +Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 
> > 46 }
> > +  })
> > +  Method(_DIS) {}
> > +  Method(_CRS) { Return (_PRS) }
> > +  Method(_SRS, 1) {}
> > +}
> > +Device (LNKD)
> > +{
> > +  Name (_HID, Eisaid ("PNP0C0F"))
> > +  Name (_UID, 1)
> > +  Name(_PRS, ResourceTemplate(){
> > +Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 
> > 46 }
> > +  })
> > +  Method(_DIS) {}
> > +  Method(_CRS) { Return (_PRS) }
> > +  Method(_SRS, 1) {}
> > +}
> > +
> 
> This looks like a very complicated way (combined with the _PRT below)
> to route all legacy interrupts to GSIV 46. You can fold this into _PRT
> instead AFAIK

This is actually very similar to the example code in section 6.2.13.1 of the 
ACPI 6.0 spec.

Regards,
Scott.

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Re: [edk2] [staging/cadence-aarch64 PATCH v2 6/6] CadencePkg: Add .dsc, .fdf and .dec files for Cadence CSP platform.

2017-06-22 Thread Scott Telford 
> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: 06 June 2017 12:37
> To: Scott Telford 
> Cc: edk2-de...@ml01.01.org; ard.biesheu...@linaro.org;
> graeme.greg...@linaro.org; af...@apple.com; michael.d.kin...@intel.com
> Subject: Re: [staging/cadence-aarch64 PATCH v2 6/6] CadencePkg: Add .dsc,
> .fdf and .dec files for Cadence CSP platform.

> > +
> > +  #
> > +  # Bds
> > +  #
> > +  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > +  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> > +  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> > +  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
> 
> Oh, and unless this causes issues for you, please substitute the above
> line for
> ---
>   MdeModulePkg/Application/UiApp/UiApp.inf {
> 
> 
> NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
>   NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
> 
> NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMainte
> nanceManagerUiLib.inf
>  }
> ---
> 
> (The platform you cloned has not yet migrated over to the generic Bds.)

I tried that, but I just got some debug output saying the BDS was waiting for 
something. The Intel BDS drops me straight into the EFI Shell which is ideal 
for the purpose this platform exists for (i.e. developing and testing the 
Cadence PCIe library).

Regards,
Scott.
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Re: [edk2] [staging/cadence-aarch64 PATCH v2 5/6] CadencePkg: Add ACPI tables for Cadence CSP platform.

2017-06-22 Thread Scott Telford 
> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: 06 June 2017 12:12
> To: Ard Biesheuvel 
> Cc: Scott Telford ; edk2-devel@lists.01.org  de...@ml01.01.org>; Graeme Gregory ;
> af...@apple.com; Kinney, Michael D 
> Subject: Re: [staging/cadence-aarch64 PATCH v2 5/6] CadencePkg: Add ACPI
> tables for Cadence CSP platform.
 
> However, if you want this Cadence UART to be usable as an operating
> system boot console in ACPI systems, you need to get the serial port
> type added to DBG2 (which is explicitly referenced from SPCR):
> https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__msdn.microsoft.com_en-2Dus_library_windows_hardware_dn639131-
> 28v-3Dvs.85-
> 29.aspx=DwIBAg=aUq983L2pue2FqKFoP6PGHMJQyoJ7kl3s3GZ-
> _haXqY=0b2qZ7fqn6FWL0d7Bhx7saDL-
> B7sx3Cxz3HPARO7ozc=SLa8mBFqNKP-
> AkMHpGlWJjZ0wbdukQ9J_HJDF_4Wd7o=1QAszB3f1u_Zpzh4ZD-
> YJzK9rtZJktnrFm9j23oaQeU=
> 
> Is this something you would be interested in doing? I could probably
> dig up the required contacts if that was the case.
> 
> (You would then also need to add some matching code in
> linux/drivers/tty/serial/xilinx_uartps.c, to get it autodetected by
> Linux.)

Thanks for the offer, but we only used a Cadence UART in this platform because 
we didn't have the ARM PL011 IP available to us when we started working on this 
(we do now). I doubt anyone else will want to use this UART in an SBSA or 
similar system, so I'll just drop SPCR.

Regards,
Scott.
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Re: [edk2] [staging/cadence-aarch64 PATCH v2 4/6] CadencePkg: Add SEC phase implementation for Cadence CSP platform.

2017-06-22 Thread Scott Telford 
> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: 06 June 2017 11:52
> To: Scott Telford 
> Cc: edk2-de...@ml01.01.org; ard.biesheu...@linaro.org;
> graeme.greg...@linaro.org; af...@apple.com; michael.d.kin...@intel.com
> Subject: Re: [staging/cadence-aarch64 PATCH v2 4/6] CadencePkg: Add SEC
> phase implementation for Cadence CSP platform.
> 
> On Mon, Jun 05, 2017 at 11:50:26AM +0100, Scott Telford wrote:
> > Add SEC phase implementation for Cadence CSP platform configured with
> > a single Cortex-A53 processor and GIC-500.

> Secondly, is there a strong reason why ArmCortexA5xLib cannot be used
> as is, rather than copied across?

ArmCpuLib was deleted in commit cffa7925a293d991957bc47865eac25516b59e63, hence 
the need to merge the required A5x routines into this code.

> Thirdly, it would be nice if the commit message described explicitly
> where this code came from.

Will do.

Regards,
Scott.
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Re: [edk2] [staging/cadence-aarch64 PATCH v2 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex.

2017-06-22 Thread Scott Telford 
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: 05 June 2017 16:25
> To: Scott Telford 
> Cc: edk2-devel@lists.01.org ; Leif Lindholm
> ; Graeme Gregory ;
> af...@apple.com; Kinney, Michael D 
> Subject: Re: [staging/cadence-aarch64 PATCH v2 3/6] CadencePkg: Add PCI
> host bridge library for Cadence PCIe Root Complex.
> 

> It is not entirely clear to me how these pieces fit together, but a
> couple of things look odd to me:
> - the type 0 region does not use PCI_ECAM_BASE, but the type 1 region does
> - the type 1 region seems to start at bus offset 2 in the ECAM space,
> why is that?

I've now made the use of PCI_ECAM_BASE consistent.

AIUI, the Root Port (bus 0) and the device or switch directly connected to the 
Root Port (bus 1) should be configured for Type 0 configuration cycles. All 
other devices should be configured for Type 1 configuration cycles.

> These appear to assume that the ECAM and MEM32 regions are ordered in
> a certain way in memory. Is that guaranteed? Also, what happened to
> the MMIO64 region?

I've removed this dependency.
I've also decided to omit the MMIO64 region as I'm not sure we can test that 
adequately on the platform configuration we're using.

Regards,
Scott.
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Re: [edk2] [staging/cadence-aarch64 PATCH v2 1/6] CadencePkg: Add libraries for Cadence CSP platform.

2017-06-22 Thread Scott Telford 
Hi Ard, sorry for the delay, got sidetracked by other issues.

> If I am reading the code correctly, this UEFI port may execute under
> ATF or may be booted at EL3 directly, right? In the former case, you
> should really be using PSCI for reset instead of poking the system
> registers directly.

No, as this platform is primarily just a test environment for the Cadence PCIe 
library, we're booting at EL3 directly and not using ATF.

Regards,
Scott.
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Re: [edk2] [staging/cadence-aarch64 PATCH v2 1/6] CadencePkg: Add libraries for Cadence CSP platform.

2017-06-22 Thread Scott Telford 
Hi Leif, sorry for the delay in replying, got sidetracked by other issues.

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: 05 June 2017 18:11
> To: Scott Telford 
> Cc: edk2-de...@ml01.01.org; ard.biesheu...@linaro.org;
> graeme.greg...@linaro.org; af...@apple.com; michael.d.kin...@intel.com
> Subject: Re: [staging/cadence-aarch64 PATCH v2 1/6] CadencePkg: Add
> libraries for Cadence CSP platform.

> > +
> > +  gCadenceCspTokenSpaceGuid.PcdPcie1RootPortBaseAddress
> > +  gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress
> > +  gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
> > +  gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize
> > +  gArmTokenSpaceGuid.PcdPciMmio32Base
> > +  gArmTokenSpaceGuid.PcdPciMmio32Size
> > +  gArmTokenSpaceGuid.PcdPciMmio64Base
> > +  gArmTokenSpaceGuid.PcdPciMmio64Size
> 
> All of my comments from round 1 have been addressed, apart from the
> paragraph of Pcds above probably not being needed.
> That's not actually correct at the moment, but if adjusting the memory
> map setup based on Ard's comments, I think these could go?

Some of these are actually still required as they are used in 
ArmPlatformGetVirtualMemoryMap() in CadenceCspLibMem.c.

Regards,
Scott.
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[edk2] [PATCH 0/2] Add EFI Partition Information Protocol

2017-06-22 Thread Hao Wu 
Add the EFI Partition Information Protocol per the latest UEFI spec.

Test for the series:
A simple application called 'DumpPartInfo' is used to dump the contents of
the Partition Information protocols when the following devices are
attached:
a. MBR Hard disk
b. GPT Hard disk
c. CDROM

The source of the application and the series is available at:
https://github.com/hwu25/edk2 branch:partition_info_test

Cc: Ruiyu Ni 

Hao Wu (2):
  MdePkg: Add EFI Partition Information Protocol definitions
  MdeModulePkg/PartitionDxe: Add impl of Partition Information Protocol

 MdeModulePkg/Universal/Disk/PartitionDxe/ElTorito.c   | 43 ++-
 MdeModulePkg/Universal/Disk/PartitionDxe/Gpt.c| 55 --
 MdeModulePkg/Universal/Disk/PartitionDxe/Mbr.c| 51 -
 MdeModulePkg/Universal/Disk/PartitionDxe/Partition.c  | 23 --
 MdeModulePkg/Universal/Disk/PartitionDxe/Partition.h  | 48 ++--
 MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf |  3 +-
 MdePkg/Include/Protocol/PartitionInfo.h   | 78 

 MdePkg/MdePkg.dec |  3 +
 8 files changed, 216 insertions(+), 88 deletions(-)
 create mode 100644 MdePkg/Include/Protocol/PartitionInfo.h

-- 
2.12.0.windows.1

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[edk2] [PATCH 1/2] MdePkg: Add EFI Partition Information Protocol definitions

2017-06-22 Thread Hao Wu 
Cc: Ruiyu Ni 
Cc: Michael D Kinney 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu 
---
 MdePkg/Include/Protocol/PartitionInfo.h | 78 
 MdePkg/MdePkg.dec   |  3 +
 2 files changed, 81 insertions(+)

diff --git a/MdePkg/Include/Protocol/PartitionInfo.h 
b/MdePkg/Include/Protocol/PartitionInfo.h
new file mode 100644
index 00..60e46456c6
--- /dev/null
+++ b/MdePkg/Include/Protocol/PartitionInfo.h
@@ -0,0 +1,78 @@
+/** @file
+  This file defines the EFI Partition Information Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Revision Reference:
+  This Protocol is introduced in UEFI Specification 2.7
+
+**/
+
+#ifndef __PARTITION_INFO_PROTOCOL_H__
+#define __PARTITION_INFO_PROTOCOL_H__
+
+#include 
+#include 
+
+//
+// EFI Partition Information Protocol GUID value
+//
+#define EFI_PARTITION_INFO_PROTOCOL_GUID \
+  { 0x8cf2f62c, 0xbc9b, 0x4821, { 0x80, 0x8d, 0xec, 0x9e, 0xc4, 0x21, 0xa1, 
0xa0 }};
+
+//
+// Forward reference for pure ANSI compatability
+//
+typedef struct _EFI_PARTITION_INFO_PROTOCOL  EFI_PARTITION_INFO_PROTOCOL;
+
+#define EFI_PARTITION_INFO_PROTOCOL_REVISION 0x0001000
+#define PARTITION_TYPE_OTHER 0x00
+#define PARTITION_TYPE_MBR   0x01
+#define PARTITION_TYPE_GPT   0x02
+
+#pragma pack(1)
+
+///
+/// Partition Information Protocol structure.
+///
+struct _EFI_PARTITION_INFO_PROTOCOL {
+  //
+  // Set to EFI_PARTITION_INFO_PROTOCOL_REVISION.
+  //
+  UINT32 Revision;
+  //
+  // Partition info type (PARTITION_TYPE_MBR, PARTITION_TYPE_GPT, or 
PARTITION_TYPE_OTHER).
+  //
+  UINT32 Type;
+  //
+  // If 1, partition describes an EFI System Partition.
+  //
+  UINT8  System;
+  UINT8  Reserved[7];
+  union {
+///
+/// MBR data
+///
+MBR_PARTITION_RECORD Mbr;
+///
+/// GPT data
+///
+EFI_PARTITION_ENTRY  Gpt;
+  } Info;
+};
+
+#pragma pack()
+
+///
+/// Partition Information Protocol GUID variable.
+///
+extern EFI_GUID gEfiPartitionInfoProtocolGuid;
+
+#endif
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 7a7504b7a3..c48f248526 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -1671,6 +1671,9 @@
   ## Include/Protocol/BluetoothLeConfig.h
   gEfiBluetoothLeConfigProtocolGuid = { 0x8f76da58, 0x1f99, 0x4275, { 
0xa4, 0xec, 0x47, 0x56, 0x51, 0x5b, 0x1c, 0xe8 } }
 
+  ## Include/Protocol/PartitionInfo.h
+  gEfiPartitionInfoProtocolGuid = { 0x8cf2f62c, 0xbc9b, 0x4821, { 
0x80, 0x8d, 0xec, 0x9e, 0xc4, 0x21, 0xa1, 0xa0 }}
+
   #
   # Protocols defined in Shell2.0
   #
-- 
2.12.0.windows.1

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[edk2] [PATCH 2/2] MdeModulePkg/PartitionDxe: Add impl of Partition Information Protocol

2017-06-22 Thread Hao Wu 
Cc: Ruiyu Ni 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bret Barkelew 
Signed-off-by: Hao Wu 
---
 MdeModulePkg/Universal/Disk/PartitionDxe/ElTorito.c   | 43 ---
 MdeModulePkg/Universal/Disk/PartitionDxe/Gpt.c| 55 

 MdeModulePkg/Universal/Disk/PartitionDxe/Mbr.c| 51 
--
 MdeModulePkg/Universal/Disk/PartitionDxe/Partition.c  | 23 ++--
 MdeModulePkg/Universal/Disk/PartitionDxe/Partition.h  | 48 
+
 MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf |  3 +-
 6 files changed, 135 insertions(+), 88 deletions(-)

diff --git a/MdeModulePkg/Universal/Disk/PartitionDxe/ElTorito.c 
b/MdeModulePkg/Universal/Disk/PartitionDxe/ElTorito.c
index 2af38429dd..2084ee5abe 100644
--- a/MdeModulePkg/Universal/Disk/PartitionDxe/ElTorito.c
+++ b/MdeModulePkg/Universal/Disk/PartitionDxe/ElTorito.c
@@ -1,7 +1,7 @@
 /** @file
   Decode an El Torito formatted CD-ROM
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -44,22 +44,23 @@ PartitionInstallElToritoChildHandles (
   IN  EFI_DEVICE_PATH_PROTOCOL *DevicePath
   )
 {
-  EFI_STATUS  Status;
-  UINT64  VolDescriptorOffset;
-  UINT32  Lba2KB;
-  EFI_BLOCK_IO_MEDIA  *Media;
-  CDROM_VOLUME_DESCRIPTOR *VolDescriptor;
-  ELTORITO_CATALOG*Catalog;
-  UINTN   Check;
-  UINTN   Index;
-  UINTN   BootEntry;
-  UINTN   MaxIndex;
-  UINT16  *CheckBuffer;
-  CDROM_DEVICE_PATH   CdDev;
-  UINT32  SubBlockSize;
-  UINT32  SectorCount;
-  EFI_STATUS  Found;
-  UINT32  VolSpaceSize;
+  EFI_STATUS   Status;
+  UINT64   VolDescriptorOffset;
+  UINT32   Lba2KB;
+  EFI_BLOCK_IO_MEDIA   *Media;
+  CDROM_VOLUME_DESCRIPTOR  *VolDescriptor;
+  ELTORITO_CATALOG *Catalog;
+  UINTNCheck;
+  UINTNIndex;
+  UINTNBootEntry;
+  UINTNMaxIndex;
+  UINT16   *CheckBuffer;
+  CDROM_DEVICE_PATHCdDev;
+  UINT32   SubBlockSize;
+  UINT32   SectorCount;
+  EFI_STATUS   Found;
+  UINT32   VolSpaceSize;
+  EFI_PARTITION_INFO_PROTOCOL  PartitionInfo;
 
   Found = EFI_NOT_FOUND;
   Media = BlockIo->Media;
@@ -248,6 +249,10 @@ PartitionInstallElToritoChildHandles (
 );
   }
 
+  ZeroMem (, sizeof (EFI_PARTITION_INFO_PROTOCOL));
+  PartitionInfo.Revision = EFI_PARTITION_INFO_PROTOCOL_REVISION;
+  PartitionInfo.Type = PARTITION_TYPE_OTHER;
+
   Status = PartitionInstallChildHandle (
 This,
 Handle,
@@ -257,10 +262,10 @@ PartitionInstallElToritoChildHandles (
 BlockIo2,
 DevicePath,
 (EFI_DEVICE_PATH_PROTOCOL *) ,
+,
 Catalog->Boot.Lba * (SIZE_2KB / Media->BlockSize),
 Catalog->Boot.Lba * (SIZE_2KB / Media->BlockSize) + 
CdDev.PartitionSize - 1,
-SubBlockSize,
-FALSE
+SubBlockSize
 );
   if (!EFI_ERROR (Status)) {
 Found = EFI_SUCCESS;
diff --git a/MdeModulePkg/Universal/Disk/PartitionDxe/Gpt.c 
b/MdeModulePkg/Universal/Disk/PartitionDxe/Gpt.c
index 35860515c1..2cd3e15e8a 100644
--- a/MdeModulePkg/Universal/Disk/PartitionDxe/Gpt.c
+++ b/MdeModulePkg/Universal/Disk/PartitionDxe/Gpt.c
@@ -13,7 +13,7 @@
   PartitionValidGptTable(), PartitionCheckGptEntry() routine will accept disk
   partition content and validate the GPT table and GPT entry.
 
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -205,19 +205,20 @@ PartitionInstallGptChildHandles (
   IN  EFI_DEVICE_PATH_PROTOCOL *DevicePath
   )
 {
-  EFI_STATUS  Status;
-  UINT32  BlockSize;
-  EFI_LBA LastBlock;
-  MASTER_BOOT_RECORD  *ProtectiveMbr;
-  EFI_PARTITION_TABLE_HEADER  *PrimaryHeader;
-  EFI_PARTITION_TABLE_HEADER  *BackupHeader;
-  EFI_PARTITION_ENTRY

Re: [edk2] [PATCH] ShellPkg DmpStore: Make NameSize to be consistent with name buffer

2017-06-22 Thread Ni, Ruiyu 
Reviewed-by: Ruiyu Ni 

Thanks/Ray

> -Original Message-
> From: Zeng, Star
> Sent: Thursday, June 22, 2017 3:24 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star ; Ni, Ruiyu ;
> Carsey, Jaben 
> Subject: [PATCH] ShellPkg DmpStore: Make NameSize to be consistent with
> name buffer
> 
> Current code will allocate pool to hold the null char for name buffer
> when PrevName==NULL, but the NameSize is still 0.
> 
> For this case, GetNextVariableName will return EFI_INVALID_PARAMETER
> to follow UEFI 2.7 spec.
> 
> UEFI 2.7 spec:
>   The VariableNameSize must not be smaller the size of the variable
>   name string passed to GetNextVariableName() on input in the
>   VariableName buffer.
> 
>   EFI_INVALID_PARAMETER
>   Null-terminator is not found in the first VariableNameSize bytes of
>   the input VariableName buffer.
> 
> This patch is to make NameSize to be consistent with name buffer.
> 
> Cc: Ruiyu Ni 
> Cc: Jaben Carsey 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Star Zeng 
> ---
>  ShellPkg/Library/UefiShellDebug1CommandsLib/DmpStore.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/DmpStore.c
> b/ShellPkg/Library/UefiShellDebug1CommandsLib/DmpStore.c
> index 23db54553f11..aeffc89b1991 100644
> --- a/ShellPkg/Library/UefiShellDebug1CommandsLib/DmpStore.c
> +++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/DmpStore.c
> @@ -436,6 +436,7 @@ CascadeProcessVariables (
>  StrnCatGrow(, , PrevName, 0);
>} else {
>  FoundVarName = AllocateZeroPool(sizeof(CHAR16));
> +NameSize = sizeof(CHAR16);
>}
> 
>Status = gRT->GetNextVariableName (, FoundVarName,
> );
> --
> 2.7.0.windows.1

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[edk2] [Patch] BaseTools: Enhance DEC Defines section format check

2017-06-22 Thread Yonghong Zhu 
From: Yunhua Feng 

1. break if Dec Defines Section is missing
2. break if Dec have more than one Defines Section
3. break if Dec Defines Section have arch attribute
4. break if no section head, like as:
#[Defines]
 DEC_SPECIFICATION  = 0x00010005
 PACKAGE_NAME   = Nt32Pkg

Cc: Liming Gao 
Cc: Yonghong Zhu 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yunhua Feng 
---
 BaseTools/Source/Python/Workspace/MetaFileParser.py | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/BaseTools/Source/Python/Workspace/MetaFileParser.py 
b/BaseTools/Source/Python/Workspace/MetaFileParser.py
index d094403..6e236e6 100644
--- a/BaseTools/Source/Python/Workspace/MetaFileParser.py
+++ b/BaseTools/Source/Python/Workspace/MetaFileParser.py
@@ -1654,10 +1654,11 @@ class DecParser(MetaFileParser):
 try:
 Content = open(str(self.MetaFile), 'r').readlines()
 except:
 EdkLogger.error("Parser", FILE_READ_FAILURE, 
ExtraData=self.MetaFile)
 
+self._DefinesCount = 0
 for Index in range(0, len(Content)):
 Line, Comment = CleanString2(Content[Index])
 self._CurrentLine = Line
 self._LineIndex = Index
 
@@ -1669,12 +1670,19 @@ class DecParser(MetaFileParser):
 continue
 
 # section header
 if Line[0] == TAB_SECTION_START and Line[-1] == TAB_SECTION_END:
 self._SectionHeaderParser()
+if self._SectionName == TAB_DEC_DEFINES.upper():
+self._DefinesCount += 1
 self._Comments = []
 continue
+if self._SectionType == MODEL_UNKNOWN:
+EdkLogger.error("Parser", FORMAT_INVALID,
+""
+"Not able to determine \"%s\" in which 
section."%self._CurrentLine,
+self.MetaFile, self._LineIndex + 1)
 elif len(self._SectionType) == 0:
 self._Comments = []
 continue
 
 # section content
@@ -1718,10 +1726,14 @@ class DecParser(MetaFileParser):
 LineNo,
 - 1,
 0
 )
 self._Comments = []
+if self._DefinesCount > 1:
+EdkLogger.error('Parser', FORMAT_INVALID, 'Multiple [Defines] 
section is exist.', self.MetaFile )
+if self._DefinesCount == 0:
+EdkLogger.error('Parser', FORMAT_INVALID, 'No [Defines] section 
exist.',self.MetaFile)
 self._Done()
 
 
 ## Section header parser
 #
@@ -1743,10 +1755,13 @@ class DecParser(MetaFileParser):
 self.MetaFile, self._LineIndex + 1, 
self._CurrentLine)
 ItemList = Item.split(TAB_SPLIT)
 
 # different types of PCD are permissible in one section
 self._SectionName = ItemList[0].upper()
+if self._SectionName == TAB_DEC_DEFINES.upper() and (len(ItemList) 
> 1 or len(Line.split(TAB_COMMA_SPLIT)) > 1):
+EdkLogger.error("Parser", FORMAT_INVALID, "Defines section 
format is invalid",
+self.MetaFile, self._LineIndex + 1, 
self._CurrentLine)
 if self._SectionName in self.DataType:
 if self.DataType[self._SectionName] not in self._SectionType:
 self._SectionType.append(self.DataType[self._SectionName])
 else:
 EdkLogger.error("Parser", FORMAT_UNKNOWN_ERROR, "%s is not a 
valid section name" % Item,
-- 
2.6.1.windows.1

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[edk2] [PATCH] ShellPkg DmpStore: Make NameSize to be consistent with name buffer

2017-06-22 Thread Star Zeng 
Current code will allocate pool to hold the null char for name buffer
when PrevName==NULL, but the NameSize is still 0.

For this case, GetNextVariableName will return EFI_INVALID_PARAMETER
to follow UEFI 2.7 spec.

UEFI 2.7 spec:
  The VariableNameSize must not be smaller the size of the variable
  name string passed to GetNextVariableName() on input in the
  VariableName buffer.

  EFI_INVALID_PARAMETER
  Null-terminator is not found in the first VariableNameSize bytes of
  the input VariableName buffer.

This patch is to make NameSize to be consistent with name buffer.

Cc: Ruiyu Ni 
Cc: Jaben Carsey 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng 
---
 ShellPkg/Library/UefiShellDebug1CommandsLib/DmpStore.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/DmpStore.c 
b/ShellPkg/Library/UefiShellDebug1CommandsLib/DmpStore.c
index 23db54553f11..aeffc89b1991 100644
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/DmpStore.c
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/DmpStore.c
@@ -436,6 +436,7 @@ CascadeProcessVariables (
 StrnCatGrow(, , PrevName, 0);
   } else {
 FoundVarName = AllocateZeroPool(sizeof(CHAR16));
+NameSize = sizeof(CHAR16);
   }
 
   Status = gRT->GetNextVariableName (, FoundVarName, );
-- 
2.7.0.windows.1

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