Re: [PSES] EMC Puzzle update

2013-12-23 Thread ce-test, qualified testing bv - Gert Gremmen
Good addition John, completely true

I should have written "universal ground"

Gert

-Oorspronkelijk bericht-
Van: John Woodgate [mailto:j...@jmwa.demon.co.uk] 
Verzonden: zondag 22 december 2013 23:19
Aan: EMC-PSTC@LISTSERV.IEEE.ORG
Onderwerp: Re: [PSES] EMC Puzzle update

In message ,
dated Sun, 22 Dec 2013, "ce-test, qualified testing bv - Gert Gremmen" 
 writes:

>Dirty planes do not exist, unless there is a reference to be compared 
>to, ideally universal ground.

While most of what you say is true, there IS no 'universal ground', not
even a conducting sheet, if it's bigger in any dimension than about 0.1
wavelengths, and, at lower frequencies, has a surface resistivity larger
than that necessary to reduce the voltage between any two points to a
negligible value. (What is negligible depends on signal levels, of
course.)

The case in this thread is that there was a separate 'chassis plane' in
the stack. In terms of emissions, it's probably misleading to call it
'dirty', but for immunity, it certainly is dirty, because it introduces
into the internal circuits stuff picked up from incident emissions.

With seasonal greetings to all my readers. (;-)
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Nondum ex silvis sumus John Woodgate, J M Woodgate and Associates,
Rayleigh, Essex UK

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Re: [PSES] EMC Puzzle update

2013-12-22 Thread John Woodgate
In message , 
dated Sun, 22 Dec 2013, "ce-test, qualified testing bv - Gert Gremmen" 
 writes:


Dirty planes do not exist, unless there is a reference to be compared 
to, ideally universal ground.


While most of what you say is true, there IS no 'universal ground', not 
even a conducting sheet, if it's bigger in any dimension than about 0.1 
wavelengths, and, at lower frequencies, has a surface resistivity larger 
than that necessary to reduce the voltage between any two points to a 
negligible value. (What is negligible depends on signal levels, of 
course.)


The case in this thread is that there was a separate 'chassis plane' in 
the stack. In terms of emissions, it's probably misleading to call it 
'dirty', but for immunity, it certainly is dirty, because it introduces 
into the internal circuits stuff picked up from incident emissions.


With seasonal greetings to all my readers. (;-)
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Nondum ex silvis sumus
John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK

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Re: [PSES] EMC Puzzle update

2013-12-22 Thread ce-test, qualified testing bv - Gert Gremmen
A few truths about EMC and grounding

A conductive PLANE is the closest equivalent for RF of the SINGLE POINT
grounding system John recommends.  RF current at a certain point A will
not travel
to a single point S, so the single point comes to point A as a plane.

Dirty planes do not exist, unless there is a reference to be compared
to, ideally universal ground.

The biggest plane in a system automatically behaves as the CLEAN ground
to the outside world, as it has the highest capacitance to the outside
world
 thus the lowest interference potential.

All measures on EMC should be referenced to the largest conductive
surface
in a system. If you have more than one, insulated from each other or not
decently
interconnected for RF, they will compete in RF potential to ground and
none of them
will do their job as clean ground.

A wire is an impregnable  obstacle for EMC problem currents.

An RF conductor ideally should not be longer than wide.
 

Gert 

-Oorspronkelijk bericht-
Van: John Woodgate [mailto:j...@jmwa.demon.co.uk] 
Verzonden: donderdag 19 december 2013 23:46
Aan: EMC-PSTC@LISTSERV.IEEE.ORG
Onderwerp: Re: [PSES] EMC Puzzle update

In message
,
dated Thu, 19 Dec 2013, "McInturff, Gary" 
writes:

>Not really practical above a few KHz or so. Above that parasitic 
>capacitance grounds at lots of points. For audio it works but for high 
>speed electronics not so much

I'm talking about conductive connections, which are usually the source
of this sort of EMI problem. If in the OP's case, the errant layer had
not been connected to chassis, the emissions would not have occurred.

I agree that consecutive layers in a stack have considerable capacitance
between them and that is where the EMI gets from the 'dirty' plane to
the 'clean' one.
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Nondum ex silvis sumus John Woodgate, J M Woodgate and Associates,
Rayleigh, Essex UK

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Re: [PSES] EMC Puzzle update

2013-12-19 Thread John Woodgate
In message 
, 
dated Thu, 19 Dec 2013, "McInturff, Gary"  
writes:


Not really practical above a few KHz or so. Above that parasitic 
capacitance grounds at lots of points. For audio it works but for high 
speed electronics not so much


I'm talking about conductive connections, which are usually the source 
of this sort of EMI problem. If in the OP's case, the errant layer had 
not been connected to chassis, the emissions would not have occurred.


I agree that consecutive layers in a stack have considerable capacitance 
between them and that is where the EMI gets from the 'dirty' plane to 
the 'clean' one.

--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Nondum ex silvis sumus
John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK

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Re: [PSES] EMC Puzzle update

2013-12-19 Thread McInturff, Gary
Not really practical above a few KHz or so. Above that parasitic capacitance 
grounds at lots of points. For audio it works but for high speed electronics 
not so much


Gary

-Original Message-
From: John Woodgate [mailto:j...@jmwa.demon.co.uk] 
Sent: Thursday, December 19, 2013 12:29 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: Re: [PSES] EMC Puzzle update

In message <8d0cb0b733784c8-23b4-27...@webmailstg-m01.sysops.aol.com>, 
dated Thu, 19 Dec 2013, Derek Walton  writes:

>I am not a proponent of having all planes tied together, only ever seen 
>disasters that way. If you allow circuit currents to deliberately on 
>inadvertently flow in the chassis it becomes a nightmare to control 
>them.

Planes that are intended to be at zero-voltage reference potential 
should meet at ONE point only. That way no unwanted sharing or stealing 
of currents occurs. Including in a stack a plane carrying stuff from the 
'chassis' seems most unwise.
-- 
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Nondum ex silvis sumus
John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK

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Re: [PSES] EMC Puzzle update

2013-12-19 Thread John Woodgate
In message <8d0cb0b733784c8-23b4-27...@webmailstg-m01.sysops.aol.com>, 
dated Thu, 19 Dec 2013, Derek Walton  writes:


I am not a proponent of having all planes tied together, only ever seen 
disasters that way. If you allow circuit currents to deliberately on 
inadvertently flow in the chassis it becomes a nightmare to control 
them.


Planes that are intended to be at zero-voltage reference potential 
should meet at ONE point only. That way no unwanted sharing or stealing 
of currents occurs. Including in a stack a plane carrying stuff from the 
'chassis' seems most unwise.

--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Nondum ex silvis sumus
John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK

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Re: [PSES] EMC Puzzle update

2013-12-19 Thread Derek Walton
HI James,


This problem child isn't my design, just one that came in my lab for debugging 
and testing: my life revolves around fixing other peoples problems :-)


I am not a proponent of having all planes tied together, only ever seen 
disasters that way. If you allow circuit currents to deliberately on 
inadvertently flow in the chassis it becomes a nightmare to control them. Much 
better to separate and segregate so you have control over outbound ( usually on 
a trace ) and return current ( usually on a plane ). This technique also allows 
you to keep outside threats like ESD and HIRF restricted to the connector and 
prevents them progressing into your ( metal ) box. If your box is plastic, you 
have to me more careful.

Does this help?


Cheers,


Derek.
L F Research


-Original Message-
From: Pawson, James 
To: EMC-PSTC 
Sent: Thu, Dec 19, 2013 11:00 am
Subject: Re: [PSES] EMC Puzzle update



Hi Derek,
 
I’m glad you managed to find out what had been causing that problem. Why did 
you elect to have a separate “chassis plane” in the first place that 
(presumably) wasn’t tied into the PCB ground planes? My (limited) understanding 
is that it is better to have all ground planes connected together to provide a 
good quality RF return path and minimise the chance of traces crossing plane 
splits.
 
Many thanks
James
 
From: Derek Walton [mailto:lfresea...@aol.com]
Sent: 19 December 2013 16:24
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: [PSES] EMC Puzzle update
 
First off, many thanks to all who replied on and off list.

 

Most of the replies we had already addressed, but here is an update.

 

To re-cap, we had a sealed metal box with just a power cord, and that power 
cord had feed through type caps. In theory this should not radiate.

 

To save the agony that we went through what was finally identified was on a 6 
layer board, 6 traces left the sanctuary of a ground or power plane and were 
routed directly over a thin chassis plane that was incorporated to increase the 
number of chassis connections that we really needed on this board. Even though 
internal, we were able to break that connection and emissions reduced close to 
30 dB. A board re-layout is needed to really fix this issue.

 

As part of the debugging process, we also found that since the board chassis 
layer was "backfeeding" the Ethernet connector housing metal and the "grounding 
tabs" were just not adequate for bonding. The result was current on the outside 
of the case that cause the enclosure to radiate pretty much equally in all 
directions... Can I patent this? :-)

 

The lesson here is that if you do bring chassis onto your PWB, and we do as a 
means to divert ESD and some RF current, that you keep it well away from 
internal high speed or sensitive traces and ideally confined to the region 
around where it's used.

 

After our mods, we now have dropped from 20 dB over class A to about 13 dB 
under Class B.

 

A big thank you once more to everyone that replied!!! Seasons Greatings to all.

 

Sincerely,


Derek.

L F Research

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Re: [PSES] EMC Puzzle update

2013-12-19 Thread Pawson, James
Hi Derek,

I'm glad you managed to find out what had been causing that problem. Why did 
you elect to have a separate "chassis plane" in the first place that 
(presumably) wasn't tied into the PCB ground planes? My (limited) understanding 
is that it is better to have all ground planes connected together to provide a 
good quality RF return path and minimise the chance of traces crossing plane 
splits.

Many thanks
James

From: Derek Walton [mailto:lfresea...@aol.com]
Sent: 19 December 2013 16:24
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: [PSES] EMC Puzzle update

First off, many thanks to all who replied on and off list.

Most of the replies we had already addressed, but here is an update.

To re-cap, we had a sealed metal box with just a power cord, and that power 
cord had feed through type caps. In theory this should not radiate.

To save the agony that we went through what was finally identified was on a 6 
layer board, 6 traces left the sanctuary of a ground or power plane and were 
routed directly over a thin chassis plane that was incorporated to increase the 
number of chassis connections that we really needed on this board. Even though 
internal, we were able to break that connection and emissions reduced close to 
30 dB. A board re-layout is needed to really fix this issue.

As part of the debugging process, we also found that since the board chassis 
layer was "backfeeding" the Ethernet connector housing metal and the "grounding 
tabs" were just not adequate for bonding. The result was current on the outside 
of the case that cause the enclosure to radiate pretty much equally in all 
directions... Can I patent this? :-)

The lesson here is that if you do bring chassis onto your PWB, and we do as a 
means to divert ESD and some RF current, that you keep it well away from 
internal high speed or sensitive traces and ideally confined to the region 
around where it's used.

After our mods, we now have dropped from 20 dB over class A to about 13 dB 
under Class B.

A big thank you once more to everyone that replied!!! Seasons Greatings to all.

Sincerely,

Derek.
L F Research
-


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[PSES] EMC Puzzle update

2013-12-19 Thread Derek Walton
First off, many thanks to all who replied on and off list.


Most of the replies we had already addressed, but here is an update.


To re-cap, we had a sealed metal box with just a power cord, and that power 
cord had feed through type caps. In theory this should not radiate.


To save the agony that we went through what was finally identified was on a 6 
layer board, 6 traces left the sanctuary of a ground or power plane and were 
routed directly over a thin chassis plane that was incorporated to increase the 
number of chassis connections that we really needed on this board. Even though 
internal, we were able to break that connection and emissions reduced close to 
30 dB. A board re-layout is needed to really fix this issue.


As part of the debugging process, we also found that since the board chassis 
layer was "backfeeding" the Ethernet connector housing metal and the "grounding 
tabs" were just not adequate for bonding. The result was current on the outside 
of the case that cause the enclosure to radiate pretty much equally in all 
directions... Can I patent this? :-)


The lesson here is that if you do bring chassis onto your PWB, and we do as a 
means to divert ESD and some RF current, that you keep it well away from 
internal high speed or sensitive traces and ideally confined to the region 
around where it's used.


After our mods, we now have dropped from 20 dB over class A to about 13 dB 
under Class B.


A big thank you once more to everyone that replied!!! Seasons Greatings to all.


Sincerely,

Derek.
L F Research

-

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