RE: FW: [Fwd: [SI-LIST] : Copper balance] {Venting of PCBs}
Larry,
I had no idea there even WAS such a standard.
Interesting, the things it's possible to learn
here; an assemblage of experts, indeed!
Thanks!
Cortland
== Original Message Follows
Date: 24-Jan-01 15:19:07 MsgID: 1078-329 ToID: 72146,373
From: Larry Merchell INTERNET:lmerch...@t-yuden.com
Subj: RE: FW: [Fwd: [SI-LIST] : Copper balance] {Venting of PCBs}
Chrg: $0.00 Imp: Norm Sens: StdReceipt: NoParts: 1
From: Larry Merchell lmerch...@t-yuden.com
Subject: RE: FW: [Fwd: [SI-LIST] : Copper balance] {Venting of PCBs}
List-Post: emc-pstc@listserv.ieee.org
Date: Wed, 24 Jan 2001 15:10:35 -0800
Reply-To: Larry Merchell lmerch...@t-yuden.com
Cortland,
The holes or slots may also be required to
meet the Maximum unpierced conductor area
requirement of UL796 Standard for Printed-
Wiring Boards for your particular PWB supplier.
In the UL Recognized Component Directory (vol.
3, ZPMV2) it is listed as Maximum, Area,
Diameter, Inches.
Regards,
Larry Merchell
Taiyo Yuden (USA), Inc.
San Marcos, CA
== End of Original Message =
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RE: FW: [Fwd: [SI-LIST] : Copper balance] {Venting of PCBs}
Cortland, The holes or slots may also be required to meet the Maximum unpierced conductor area requirement of UL796 Standard for Printed-Wiring Boards for your particular PWB supplier. In the UL Recognized Component Directory (vol. 3, ZPMV2) it is listed as Maximum, Area, Diameter, Inches. Regards, Larry Merchell Taiyo Yuden (USA), Inc. San Marcos, CA -Original Message- From: Cortland Richmond [mailto:72146@compuserve.com] Sent: Wednesday, January 24, 2001 8:38 AM To: Debbie Mallory; ieee pstc list Subject: Re: FW: [Fwd: [SI-LIST] : Copper balance] Debbie, Doug Powell explained it as venting, where slots or holes are added to a plane in order to let vapor out. However, it is my belief that this is also done to keep copper balanced during the etching process. I may well be mistaken, but the EMI and signal integrity concerns we have with the practice are all valid. Cheers, Cortland == Original Message Follows Date: 23-Jan-01 07:25:06 MsgID: 1077-23952 ToID: 72146,373 From: Debbie Mallory INTERNET:debbie.mall...@fibre.com Subj: FW: [Fwd: [SI-LIST] : Copper balance] Chrg: $0.00 Imp: Norm Sens: StdReceipt: NoParts: 1 From: Debbie Mallory debbie.mall...@fibre.com Subject: FW: [Fwd: [SI-LIST] : Copper balance] List-Post: emc-pstc@listserv.ieee.org Date: Tue, 23 Jan 2001 07:21:35 -0800 Cortland, I, too, am having problems passing radiated emissions because of 350Mz originating from a 50MHz processor that uses a 50MHz oscillator. I thought I understood thieving until you said you have to put it on the ground plane also. Can you explain further why and how thieving is applied to the ground plane? Thanks. Regards, Debbie Mallory Advanced Fibre Communications Largo, FL == End of Original Message = --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Jim Bacher: jim_bac...@mail.monarch.com Michael Garretson:pstc_ad...@garretson.org For policy questions, send mail to: Richard Nute: ri...@ieee.org --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Jim Bacher: jim_bac...@mail.monarch.com Michael Garretson:pstc_ad...@garretson.org For policy questions, send mail to: Richard Nute: ri...@ieee.org
Re: FW: [Fwd: [SI-LIST] : Copper balance]
Debbie, Doug Powell explained it as venting, where slots or holes are added to a plane in order to let vapor out. However, it is my belief that this is also done to keep copper balanced during the etching process. I may well be mistaken, but the EMI and signal integrity concerns we have with the practice are all valid. Cheers, Cortland == Original Message Follows Date: 23-Jan-01 07:25:06 MsgID: 1077-23952 ToID: 72146,373 From: Debbie Mallory INTERNET:debbie.mall...@fibre.com Subj: FW: [Fwd: [SI-LIST] : Copper balance] Chrg: $0.00 Imp: Norm Sens: StdReceipt: NoParts: 1 From: Debbie Mallory debbie.mall...@fibre.com Subject: FW: [Fwd: [SI-LIST] : Copper balance] List-Post: emc-pstc@listserv.ieee.org Date: Tue, 23 Jan 2001 07:21:35 -0800 Cortland, I, too, am having problems passing radiated emissions because of 350Mz originating from a 50MHz processor that uses a 50MHz oscillator. I thought I understood thieving until you said you have to put it on the ground plane also. Can you explain further why and how thieving is applied to the ground plane? Thanks. Regards, Debbie Mallory Advanced Fibre Communications Largo, FL == End of Original Message = --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Jim Bacher: jim_bac...@mail.monarch.com Michael Garretson:pstc_ad...@garretson.org For policy questions, send mail to: Richard Nute: ri...@ieee.org
Re: Copper balance
Logically, if it can make emissions worse, it can make them better, too. Suppose your original board exhibited some resonance, and thieving changed it. That would certainly lower emissions due to a resonant board. Anything that resonates will radiate, and this can even be a whole board in its slot. So the answer is yes, it CAN help. But I'd not count on random thieving to cut overall emissions! On the other had, I like the idea of ground-fill, well tied to an underlying plane. This should provide an on-board return path for fields than otherwise would return through more distant conductors. Cortland == Original Message Follows Date: 17-Jan-01 12:18:24 MsgID: 1077-21792 ToID: 72146,373 From: David Gelfand INTERNET:gelf...@memotec.com Subj: Re: Copper balance Chrg: $0.00 Imp: Norm Sens: StdReceipt: NoParts: 1 From: David Gelfand gelf...@memotec.com Subject: Re: Copper balance List-Post: emc-pstc@listserv.ieee.org Date: Wed, 17 Jan 2001 15:18:44 -0500 Can thieving reduce emissions even if they are floating? I have two different versions of a board, the one without thieving is much noisier than the other. Thanks, David. David Gelfand Regulatory Approvals Memotec Communications Inc. Montreal Canada == End of Original Message = --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Jim Bacher: jim_bac...@mail.monarch.com Michael Garretson:pstc_ad...@garretson.org For policy questions, send mail to: Richard Nute: ri...@ieee.org
Re: [Fwd: [SI-LIST] : Copper balance]
Hi! Cortland: Thanks for your comments. In your experience, does the size/spacing of the copper dots or islands matter as long as their dimension is much smaller than the wavelength for the highest possible frequency on the card ? Any special considerations other than that ? Regards Perry Cortland Richmond wrote: Yes indeed. My preference is for thieving to be done with dots or islands small with respect to the shortest wavelength of concern. This is because thieving can be constructed so as to resonate and aggravate an EMI problem. Some years ago, at an employer far away (grin), we had obtained compliance on a computer using a plug-in processor board. On testing the first production items, we found they were some dB over -- at 350 Mhz! It took some time, but I found the PWB manufacturer had added a ring of thieving material around the board. This ring was resonating at 350 Mhz and significantly increasing the shielding required. Chopping it up into strips made the problem go away. (Many devices use so-called ESD traces to protect board-mounted devices from being affected by ESD during maintenance. Unless care is taken with these, they can act the same way as thieving copper above.) Cortland (cortland.richm...@usa.alcatel.com) The post above does not represent my employer's opinions or policies == (some snipped) Date: Tue, 16 Jan 2001 17:10:43 -0500 From: Perry Qu perry...@alcatel.com Organization: Alcatel CID Subject: [Fwd: [SI-LIST] : Copper balance] Reply-To: Perry Qu perry...@alcatel.com Hi! We are looking for some advice on copper thieving on the PCB. The concern is the EMC impact of the floating copper. Anyone is willing to share his/her experience on the best configuration for high percentage of copper coverage and low EMI at the same time ? Refer to the post to SI list by my colleague Dorin on this issue. Any advice on this will be greatly appreciated. Regards Perry Qu --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Jim Bacher: jim_bac...@mail.monarch.com Michael Garretson:pstc_ad...@garretson.org For policy questions, send mail to: Richard Nute: ri...@ieee.org
Re: [Fwd: [SI-LIST] : Copper balance]
Yes indeed. My preference is for thieving to be done with dots or islands small with respect to the shortest wavelength of concern. This is because thieving can be constructed so as to resonate and aggravate an EMI problem. Some years ago, at an employer far away (grin), we had obtained compliance on a computer using a plug-in processor board. On testing the first production items, we found they were some dB over -- at 350 Mhz! It took some time, but I found the PWB manufacturer had added a ring of thieving material around the board. This ring was resonating at 350 Mhz and significantly increasing the shielding required. Chopping it up into strips made the problem go away. (Many devices use so-called ESD traces to protect board-mounted devices from being affected by ESD during maintenance. Unless care is taken with these, they can act the same way as thieving copper above.) Cortland (cortland.richm...@usa.alcatel.com) The post above does not represent my employer's opinions or policies == (some snipped) List-Post: emc-pstc@listserv.ieee.org Date: Tue, 16 Jan 2001 17:10:43 -0500 From: Perry Qu perry...@alcatel.com Organization: Alcatel CID Subject: [Fwd: [SI-LIST] : Copper balance] Reply-To: Perry Qu perry...@alcatel.com Hi! We are looking for some advice on copper thieving on the PCB. The concern is the EMC impact of the floating copper. Anyone is willing to share his/her experience on the best configuration for high percentage of copper coverage and low EMI at the same time ? Refer to the post to SI list by my colleague Dorin on this issue. Any advice on this will be greatly appreciated. Regards Perry Qu --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Jim Bacher: jim_bac...@mail.monarch.com Michael Garretson:pstc_ad...@garretson.org For policy questions, send mail to: Richard Nute: ri...@ieee.org
