RE: RFI/EMI and Susceptibility on PCB for Analog Signal Distribution
I think I can make NEC-2 work for this. It is a wire antenna modeling program but I can make it do much more. Dave From: Robert A. Macy [mailto:m...@california.com] Sent: Monday, October 08, 2007 3:34 PM To: David Cuthbert Cc: emc-p...@ieee.org Subject: Re: RFI/EMI and Susceptibility on PCB for Analog Signal Distribution David, Thank you for your response. It seemed counter intuitive that the second approach would have less crosstalk than the first. That expectation is based upon picturing the fields between the two signal traces as better contained when the traces were side by side on the same layer, than if the traces were on top each other. As in the second structure it seemed that the field of one pair is polarized to better inject into an adjacent pair. Another way to say this, is to think in general of a field from a current loop on axis and off axis. Off axis, like in the first structure there is inherently 6 dB less than when on axis like in the second structure. I agree about modelling to get a better representation of what is going on. Will the modelling show the effect of 3V/m DC to 1GHz fields? Robert On Mon, 8 Oct 2007 14:27:28 -0600 "David Cuthbert" wrote: > Robert, > > The second PCB stack-up will give less channel-to-channel > crosstalk. Imagine > the stack-up with the ground traces on layers 2 and 3 > removed. The coupling > of the layer 2 and layer 3 traces will be almost equal to > the adjacent > channel. The ground stitching will help a lot. But you > need to know if 120 > dB is possible. A 3-D field solver is the tool to use > unless you like doing > tedious calculations (from your EM class). I can run this > in NEC-2 this > evening and see what we get. > > Dave Cuthbert > Linear Technology > > -Original Message- > From: emc-p...@ieee.org [mailto:emc-p...@ieee.org] On > Behalf Of Robert A. > Macy > Sent: Monday, October 08, 2007 1:10 PM > To: emc-p...@ieee.org > Subject: RFI/EMI and Susceptibility on PCB for Analog > Signal Distribution > > Background > > Trying to 'Engineer' the design of transmitting more than > eight balanced analog signals of very high quality over a > length of 30-40 cm using PCB structures that simulate > twinax cabling. > > The signals themselves are energetic with bandwidth > exceeding 50MHz at levels more than 200 Volts. Impedance > of the twinax is 150 ohm to a capacitive load, so only > 150mA spikes occur. > > These high quality analog signals cannot stand more than > 1/4 mV injected back into them. We're talking 120dB > analog > distribution system here. > > > Need Help with E3 > > Anybody have experience, or data, regarding RFI/EMI > generation *and* susceptibility from PCB structures that > are made to simulate twinax? Interested especially in > susceptibility. > > > Here are two possible PCB constructions: > First, use 3 copper layers: > GND layer, > then side by side traces > GND : S+ : S- : GND > GND layer > Second, use 4 copper layers: > GND layer > then single trace per layer > GND : S+ : GND > GND : S- : GND > GND layer > > which is better? It seems that four layers is worse, > because with four layers the adjacent traces are more > likely to 'talk' through to adjacent structures. > > Does anyone know of a better structure? > > > Also, given thickness of the insulation, what should be > spacing? and spacing of 'stitching' vias from the top GND > through guard GND traces through to bottom GND layer? > > Then, after selecting a structure, what is susceptibility > of that structure? How does one predict the amount of > signal corruption that will appear on a pair of lines? > > Robert > > - > > This message is from the IEEE Product Safety Engineering > Society > emc-pstc discussion list.Website: > http://www.ieee-pses.org/ > > To post a message to the list, send your e-mail to > emc-p...@ieee.org > > Instructions: > http://listserv.ieee.org/request/user-guide.html > > List rules: http://www.ieee-pses.org/listrules.html > > For help, send mail to the list administrators: > > Scott Douglas emcp...@ptcnh.net > Mike Cantwell mcantw...@ieee.org > > For policy questions, send mail to: > > Jim Bacher: j.bac...@ieee.org > David Heald:emc-p...@daveheald.com > > All emc-pstc postings are archived and searchable on the > web at: > > http://www.ieeecommunities.org/emc-pstc > > - This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list.Website: h
Re: RFI/EMI and Susceptibility on PCB for Analog Signal Distribution
David, Thank you for your response. It seemed counter intuitive that the second approach would have less crosstalk than the first. That expectation is based upon picturing the fields between the two signal traces as better contained when the traces were side by side on the same layer, than if the traces were on top each other. As in the second structure it seemed that the field of one pair is polarized to better inject into an adjacent pair. Another way to say this, is to think in general of a field from a current loop on axis and off axis. Off axis, like in the first structure there is inherently 6 dB less than when on axis like in the second structure. I agree about modelling to get a better representation of what is going on. Will the modelling show the effect of 3V/m DC to 1GHz fields? Robert On Mon, 8 Oct 2007 14:27:28 -0600 "David Cuthbert" wrote: > Robert, > > The second PCB stack-up will give less channel-to-channel > crosstalk. Imagine > the stack-up with the ground traces on layers 2 and 3 > removed. The coupling > of the layer 2 and layer 3 traces will be almost equal to > the adjacent > channel. The ground stitching will help a lot. But you > need to know if 120 > dB is possible. A 3-D field solver is the tool to use > unless you like doing > tedious calculations (from your EM class). I can run this > in NEC-2 this > evening and see what we get. > > Dave Cuthbert > Linear Technology > > -Original Message- > From: emc-p...@ieee.org [mailto:emc-p...@ieee.org] On > Behalf Of Robert A. > Macy > Sent: Monday, October 08, 2007 1:10 PM > To: emc-p...@ieee.org > Subject: RFI/EMI and Susceptibility on PCB for Analog > Signal Distribution > > Background > > Trying to 'Engineer' the design of transmitting more than > eight balanced analog signals of very high quality over a > length of 30-40 cm using PCB structures that simulate > twinax cabling. > > The signals themselves are energetic with bandwidth > exceeding 50MHz at levels more than 200 Volts. Impedance > of the twinax is 150 ohm to a capacitive load, so only > 150mA spikes occur. > > These high quality analog signals cannot stand more than > 1/4 mV injected back into them. We're talking 120dB > analog > distribution system here. > > > Need Help with E3 > > Anybody have experience, or data, regarding RFI/EMI > generation *and* susceptibility from PCB structures that > are made to simulate twinax? Interested especially in > susceptibility. > > > Here are two possible PCB constructions: > First, use 3 copper layers: > GND layer, > then side by side traces > GND : S+ : S- : GND > GND layer > Second, use 4 copper layers: > GND layer > then single trace per layer > GND : S+ : GND > GND : S- : GND > GND layer > > which is better? It seems that four layers is worse, > because with four layers the adjacent traces are more > likely to 'talk' through to adjacent structures. > > Does anyone know of a better structure? > > > Also, given thickness of the insulation, what should be > spacing? and spacing of 'stitching' vias from the top GND > through guard GND traces through to bottom GND layer? > > Then, after selecting a structure, what is susceptibility > of that structure? How does one predict the amount of > signal corruption that will appear on a pair of lines? > > Robert > > - > > This message is from the IEEE Product Safety Engineering > Society > emc-pstc discussion list.Website: > http://www.ieee-pses.org/ > > To post a message to the list, send your e-mail to > emc-p...@ieee.org > > Instructions: > http://listserv.ieee.org/request/user-guide.html > > List rules: http://www.ieee-pses.org/listrules.html > > For help, send mail to the list administrators: > > Scott Douglas emcp...@ptcnh.net > Mike Cantwell mcantw...@ieee.org > > For policy questions, send mail to: > > Jim Bacher: j.bac...@ieee.org > David Heald:emc-p...@daveheald.com > > All emc-pstc postings are archived and searchable on the > web at: > > http://www.ieeecommunities.org/emc-pstc > > - This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list.Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to emc-p...@ieee.org Instructions: http://listserv.ieee.org/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas emcp...@ptcnh.net Mike Cantwell mcantw...@ieee.org For policy questions, send mail to: Jim Bacher: j.bac...@ieee.org David Heald:emc-p...@daveheald.com All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc __ This e-mail has been scanned by MCI Managed Em
RE: RFI/EMI and Susceptibility on PCB for Analog Signal Distribution
Robert, The second PCB stack-up will give less channel-to-channel crosstalk. Imagine the stack-up with the ground traces on layers 2 and 3 removed. The coupling of the layer 2 and layer 3 traces will be almost equal to the adjacent channel. The ground stitching will help a lot. But you need to know if 120 dB is possible. A 3-D field solver is the tool to use unless you like doing tedious calculations (from your EM class). I can run this in NEC-2 this evening and see what we get. Dave Cuthbert Linear Technology From: emc-p...@ieee.org [mailto:emc-p...@ieee.org] On Behalf Of Robert A. Macy Sent: Monday, October 08, 2007 1:10 PM To: emc-p...@ieee.org Subject: RFI/EMI and Susceptibility on PCB for Analog Signal Distribution Background Trying to 'Engineer' the design of transmitting more than eight balanced analog signals of very high quality over a length of 30-40 cm using PCB structures that simulate twinax cabling. The signals themselves are energetic with bandwidth exceeding 50MHz at levels more than 200 Volts. Impedance of the twinax is 150 ohm to a capacitive load, so only 150mA spikes occur. These high quality analog signals cannot stand more than 1/4 mV injected back into them. We're talking 120dB analog distribution system here. Need Help with E3 Anybody have experience, or data, regarding RFI/EMI generation *and* susceptibility from PCB structures that are made to simulate twinax? Interested especially in susceptibility. Here are two possible PCB constructions: First, use 3 copper layers: GND layer, then side by side traces GND : S+ : S- : GND GND layer Second, use 4 copper layers: GND layer then single trace per layer GND : S+ : GND GND : S- : GND GND layer which is better? It seems that four layers is worse, because with four layers the adjacent traces are more likely to 'talk' through to adjacent structures. Does anyone know of a better structure? Also, given thickness of the insulation, what should be spacing? and spacing of 'stitching' vias from the top GND through guard GND traces through to bottom GND layer? Then, after selecting a structure, what is susceptibility of that structure? How does one predict the amount of signal corruption that will appear on a pair of lines? Robert - This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list.Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to emc-p...@ieee.org Instructions: http://listserv.ieee.org/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas emcp...@ptcnh.net Mike Cantwell mcantw...@ieee.org For policy questions, send mail to: Jim Bacher: j.bac...@ieee.org David Heald:emc-p...@daveheald.com All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc - This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list.Website: http://www.ieee-pses.org/ To post a message to the list, send your e-mail to emc-p...@ieee.org Instructions: http://listserv.ieee.org/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas emcp...@ptcnh.net Mike Cantwell mcantw...@ieee.org For policy questions, send mail to: Jim Bacher: j.bac...@ieee.org David Heald:emc-p...@daveheald.com All emc-pstc postings are archived and searchable on the web at: http://www.ieeecommunities.org/emc-pstc __ This e-mail has been scanned by MCI Managed Email Content Service, using Skeptic(tm) technology powered by MessageLabs. For more information on MCI's Managed Email Content Service, visit http://www.mci.com. __