MTRR stuff

1999-07-08 Thread Stephen Hocking-Senior Programmer PGS Tensor Perth

For some video cards (to wit, the voodoo stuff), the MTRRs should be set up as 
follows

   write-combining
 +--+ 
 +---+
  uncacheable

i.e. the two regions have the same starting area, but the small chunk for the 
registers should be uncacheable. When I try to do this using memconf on my 
K6-2, it spits the dummy. Is there a work around for this?


Stephen
-- 
  The views expressed above are not those of PGS Tensor.

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Re: MTRR stuff

1999-07-09 Thread Brian F. Feldman

On Fri, 9 Jul 1999, Stephen Hocking-Senior Programmer PGS Tensor Perth wrote:

> For some video cards (to wit, the voodoo stuff), the MTRRs should be set up as 
> follows
> 
>write-combining
>  +--+ 
>  +---+
>   uncacheable
> 
> i.e. the two regions have the same starting area, but the small chunk for the 
> registers should be uncacheable. When I try to do this using memconf on my 
> K6-2, it spits the dummy. Is there a work around for this?

Spits the dummy? And do you mean memcontrol?
I have no idea what you mean by that. However, the natural thing to do would
be this:
+---+ write-combine uncacheable
 +--+ uncacheable

> 
> 
>   Stephen
> -- 
>   The views expressed above are not those of PGS Tensor.
> 
> "We've heard that a million monkeys at a million keyboards could produce
>  the Complete Works of Shakespeare; now, thanks to the Internet, we know
>  this is not true."Robert Wilensky, University of California
> 
> 
> 
> 
> To Unsubscribe: send mail to [EMAIL PROTECTED]
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> 

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Re: MTRR stuff

1999-07-09 Thread Stephen Hocking-Senior Programmer PGS Tensor Perth


> 
> Spits the dummy? And do you mean memcontrol?

It (memcontrol, I was typing the name from memory at work) complains. I was 
trying to set up the MTRRs like the Linux voodoo device driver does. I hadn't 
thought of doing it the way you suggest, as the documentation says that the 
size has to be a power of 2.

> I have no idea what you mean by that. However, the natural thing to do would
> be this:
>   +---+ write-combine uncacheable
>+--+ uncacheable
> 

-- 
  The views expressed above are not those of PGS Tensor.

"We've heard that a million monkeys at a million keyboards could produce
 the Complete Works of Shakespeare; now, thanks to the Internet, we know
 this is not true."Robert Wilensky, University of California




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Re: MTRR stuff

1999-07-09 Thread Brian F. Feldman

On Fri, 9 Jul 1999, Stephen Hocking-Senior Programmer PGS Tensor Perth wrote:

> 
> > 
> > Spits the dummy? And do you mean memcontrol?
> 
> It (memcontrol, I was typing the name from memory at work) complains. I was 
> trying to set up the MTRRs like the Linux voodoo device driver does. I hadn't 
> thought of doing it the way you suggest, as the documentation says that the 
> size has to be a power of 2.

What exactly are the ranges? You haven't given me enough info yet. I wrote the
K6-* MTRR driver, so I'd like to help.

> 
> > I have no idea what you mean by that. However, the natural thing to do would
> > be this:
> > +---+ write-combine uncacheable
> >  +--+ uncacheable
> > 
> 
> -- 
>   The views expressed above are not those of PGS Tensor.
> 
> "We've heard that a million monkeys at a million keyboards could produce
>  the Complete Works of Shakespeare; now, thanks to the Internet, we know
>  this is not true."Robert Wilensky, University of California
> 
> 
> 

 Brian Fundakowski Feldman  _ __ ___   ___ ___ ___  
 [EMAIL PROTECTED]   _ __ ___ | _ ) __|   \ 
 FreeBSD: The Power to Serve!_ __ | _ \._ \ |) |
   http://www.FreeBSD.org/  _ |___/___/___/ 



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Re: MTRR stuff

1999-07-09 Thread Stephen Hocking-Senior Programmer PGS Tensor Perth

 
> What exactly are the ranges? You haven't given me enough info yet. I wrote the
> K6-* MTRR driver, so I'd like to help.
> 
OK, the Linux 3dfx driver attempts to set up a write combining range starting 
at the card's base address and 0x40 bytes long. After doing this it then 
sets up a range marked as uncacheable starting at the card's base address of 
length  0x1000.


Stephen

-- 
  The views expressed above are not those of PGS Tensor.

"We've heard that a million monkeys at a million keyboards could produce
 the Complete Works of Shakespeare; now, thanks to the Internet, we know
 this is not true."Robert Wilensky, University of California




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Re: MTRR stuff

1999-07-12 Thread Mike Smith

>  
> > What exactly are the ranges? You haven't given me enough info yet. I wrote the
> > K6-* MTRR driver, so I'd like to help.
> > 
> OK, the Linux 3dfx driver attempts to set up a write combining range starting 
> at the card's base address and 0x40 bytes long. After doing this it then 
> sets up a range marked as uncacheable starting at the card's base address of 
> length  0x1000.

The current i686 MTRR driver doesn't allow overlapping ranges at all; 
this is a defect in its implementation that will be rectified when I 
get to work on it next (hopefully in the next week or so).

-- 
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\\  of the man.   \\  [EMAIL PROTECTED]
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Re: MTRR stuff

1999-07-12 Thread Brian F. Feldman

On Mon, 12 Jul 1999, Mike Smith wrote:

> >  
> > > What exactly are the ranges? You haven't given me enough info yet. I wrote the
> > > K6-* MTRR driver, so I'd like to help.
> > > 
> > OK, the Linux 3dfx driver attempts to set up a write combining range starting 
> > at the card's base address and 0x40 bytes long. After doing this it then 
> > sets up a range marked as uncacheable starting at the card's base address of 
> > length  0x1000.
> 
> The current i686 MTRR driver doesn't allow overlapping ranges at all; 
> this is a defect in its implementation that will be rectified when I 
> get to work on it next (hopefully in the next week or so).

The current K6 MTRR driver does, but I need more information on exactly
what's wrong. If it's returning EINVAL, what EXACTLY did he pass it?
Stephen, you're not giving enough information.

> 
> -- 
> \\  The mind's the standard   \\  Mike Smith
> \\  of the man.   \\  [EMAIL PROTECTED]
> \\-- Joseph Merrick   \\  [EMAIL PROTECTED]
> 
> 
> 
> 
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Re: MTRR stuff

1999-07-30 Thread Mike Smith

> For some video cards (to wit, the voodoo stuff), the MTRRs should be set up as 
> follows
> 
>write-combining
>  +--+ 
>  +---+
>   uncacheable
> 
> i.e. the two regions have the same starting area, but the small chunk for the 
> registers should be uncacheable. When I try to do this using memconf on my 
> K6-2, it spits the dummy. Is there a work around for this?

The i686 MTRR implementation, at least, doesn't allow UC to overlap WC; 
only Write-back and uncached are allowed to overlap.  I don't know what 
the K6's limitations are; you should talk to Brian Feldman about that.

-- 
\\  The mind's the standard   \\  Mike Smith
\\  of the man.   \\  [EMAIL PROTECTED]
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Re: MTRR stuff

1999-07-30 Thread Brian F. Feldman

On Fri, 30 Jul 1999, Mike Smith wrote:

> > For some video cards (to wit, the voodoo stuff), the MTRRs should be set up as 
> > follows
> > 
> >write-combining
> >  +--+ 
> >  +---+
> >   uncacheable
> > 
> > i.e. the two regions have the same starting area, but the small chunk for the 
> > registers should be uncacheable. When I try to do this using memconf on my 
> > K6-2, it spits the dummy. Is there a work around for this?
> 
> The i686 MTRR implementation, at least, doesn't allow UC to overlap WC; 
> only Write-back and uncached are allowed to overlap.  I don't know what 
> the K6's limitations are; you should talk to Brian Feldman about that.

As long as a range isn't exactly the same (base, len being the same), it
allows the change. The question is how does it fail? I let the hardware
decide what to actually do with the registers, but I write them, so...
I need to know where the problem is.

> 
> -- 
> \\  The mind's the standard   \\  Mike Smith
> \\  of the man.   \\  [EMAIL PROTECTED]
> \\-- Joseph Merrick   \\  [EMAIL PROTECTED]
> 
> 
> 
> 
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> 

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 [EMAIL PROTECTED]   _ __ ___ | _ ) __|   \ 
 FreeBSD: The Power to Serve!_ __ | _ \._ \ |) |
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