Re: GSoC'11: DWARF2 call frame information
2011/3/22 Chagin Dmitry dcha...@freebsd.org: On Mon, Mar 21, 2011 at 05:36:13PM +0800, Xingxing Pan wrote: 2011/3/21 Chagin Dmitry dcha...@freebsd.org: powerfull script. Xingxing Pan hmm, which script? I think enough amd64, i386 and amd64/ia32. I suggest to write a example before continuing the conversation about the GSoC. For example (bcopy || bzero) cpu_switch. Is it ok for you? -- Have fun! chd Hi Chargin, Thank you for your reply. The followings shows how I try to add DWARF for bcopy. --- ../8.2.0/sys/i386/include/asm.h 2011-03-21 14:35:56.111973722 +0800 +++ asm.h 2011-03-21 15:25:31.564636162 +0800 @@ -71,7 +71,7 @@ #define _ENTRY(x) _START_ENTRY; \ .globl CNAME(x); .type CNAME(x),@function; CNAME(x): -#define END(x) .size x, . - x +#define END(x) .cfi_endproc; .size x, . - x #ifdef PROF #define ALTENTRY(x) _ENTRY(x); \ @@ -80,9 +80,10 @@ popl %ebp; \ jmp 9f #define ENTRY(x) _ENTRY(x); \ - pushl %ebp; movl %esp,%ebp; \ + .cfi_startproc; \ + pushl %ebp; .cfi_adjust_cfa_offset 4; movl %esp,%ebp; .cfi_def_cfa_register %ebp; \ call PIC_PLT(HIDENAME(mcount)); \ - popl %ebp; \ + popl %ebp; .cfi_def_cfa %esp, 4; \ --- bcopy.S 2011-03-21 15:51:26.804203809 +0800 +++ ../8.2.0/lib/libc/i386/string/bcopy.S 2011-03-21 14:28:15.023069890 +0800 @@ -51,9 +51,7 @@ ENTRY(bcopy) #endif #endif pushl %esi - .cfi_adjust_cfa_offset 4; pushl %edi - .cfi_adjust_cfa_offset 4; #if defined(MEMCOPY) || defined(MEMMOVE) movl 12(%esp),%edi movl 16(%esp),%esi @@ -77,9 +75,7 @@ ENTRY(bcopy) rep movsb popl %edi - .cfi_adjust_cfa_offset -4; popl %esi - .cfi_adjust_cfa_offset -4; ret 1: addl %ecx,%edi /* copy backwards. */ @@ -98,9 +94,7 @@ ENTRY(bcopy) rep movsl popl %edi - .cfi_adjust_cfa_offset -4; popl %esi - .cfi_adjust_cfa_offset -4; cld ret #ifdef MEMCOPY But I don't know how to add DWARF for cpu_switch, because I have no idea about the circumstance when we need to backtrace through this function. Suppose there's a cpu switch like this, threadA-kernel-threadB. Then should the expected backtrace has the following result? threadB's stack kernel's stack threadA's stack hmm, ok. good, avoid cpu_switch. First of all, please, read style(9) man page. In the second, evaluate the proposed plan (discussed with kib@): 1) Annotate libc, msun, rtld, libthr (you) 2) vdso (I'm) 3) Annotate signal trampolines (you, after vdso) And i'm going to understand what I need to do to start GSoC for you. Thanks! -- Have fun! chd I think the plan is ok for me. Thank you. Xingxing Pan ___ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to freebsd-hackers-unsubscr...@freebsd.org
Re: GSoC'11: DWARF2 call frame information
2011/3/22 Kostik Belousov kostik...@gmail.com: On Mon, Mar 21, 2011 at 08:32:04PM +0300, Chagin Dmitry wrote: On Mon, Mar 21, 2011 at 05:36:13PM +0800, Xingxing Pan wrote: 2011/3/21 Chagin Dmitry dcha...@freebsd.org: powerfull script. Xingxing Pan hmm, which script? I think enough amd64, i386 and amd64/ia32. I suggest to write a example before continuing the conversation about the GSoC. For example (bcopy || bzero) cpu_switch. Is it ok for you? -- Have fun! chd Hi Chargin, Thank you for your reply. The followings shows how I try to add DWARF for bcopy. --- ../8.2.0/sys/i386/include/asm.h 2011-03-21 14:35:56.111973722 +0800 +++ asm.h 2011-03-21 15:25:31.564636162 +0800 @@ -71,7 +71,7 @@ #define _ENTRY(x) _START_ENTRY; \ .globl CNAME(x); .type CNAME(x),@function; CNAME(x): -#define END(x) .size x, . - x +#define END(x) .cfi_endproc; .size x, . - x #ifdef PROF #define ALTENTRY(x) _ENTRY(x); \ @@ -80,9 +80,10 @@ popl %ebp; \ jmp 9f #define ENTRY(x) _ENTRY(x); \ - pushl %ebp; movl %esp,%ebp; \ + .cfi_startproc; \ + pushl %ebp; .cfi_adjust_cfa_offset 4; movl %esp,%ebp; .cfi_def_cfa_register %ebp; \ call PIC_PLT(HIDENAME(mcount)); \ - popl %ebp; \ + popl %ebp; .cfi_def_cfa %esp, 4; \ --- bcopy.S 2011-03-21 15:51:26.804203809 +0800 +++ ../8.2.0/lib/libc/i386/string/bcopy.S 2011-03-21 14:28:15.023069890 +0800 @@ -51,9 +51,7 @@ ENTRY(bcopy) #endif #endif pushl %esi - .cfi_adjust_cfa_offset 4; pushl %edi - .cfi_adjust_cfa_offset 4; #if defined(MEMCOPY) || defined(MEMMOVE) movl 12(%esp),%edi movl 16(%esp),%esi @@ -77,9 +75,7 @@ ENTRY(bcopy) rep movsb popl %edi - .cfi_adjust_cfa_offset -4; popl %esi - .cfi_adjust_cfa_offset -4; ret 1: addl %ecx,%edi /* copy backwards. */ @@ -98,9 +94,7 @@ ENTRY(bcopy) rep movsl popl %edi - .cfi_adjust_cfa_offset -4; popl %esi - .cfi_adjust_cfa_offset -4; cld ret #ifdef MEMCOPY But I don't know how to add DWARF for cpu_switch, because I have no idea about the circumstance when we need to backtrace through this function. Suppose there's a cpu switch like this, threadA-kernel-threadB. Then should the expected backtrace has the following result? threadB's stack kernel's stack threadA's stack hmm, ok. good, avoid cpu_switch. First of all, please, read style(9) man page. In the second, evaluate the proposed plan (discussed with kib@): 1) Annotate libc, msun, rtld, libthr (you) 1a) Develop and implement a testing plan to verify the implementation. 1b) consider doing full register tracking for assembler code. 2) vdso (I'm) 3) Annotate signal trampolines (you, after vdso) And i'm going to understand what I need to do to start GSoC for you. Thanks! -- Have fun! chd Hi Kostik, I think the basic testing method can be using GDB to set breakpoint in functions and observing the backtrace result. GDB uses Expect. I can learn something from GDB's testsuite. AFAIK, CFA and return address are enough for unwinding. Dose full register tracking means to emit DWARF for all the registers's saving and restoring in the life time of the function? Thanks. Xingxing Pan ___ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to freebsd-hackers-unsubscr...@freebsd.org
PowerPC e500v2 and IEEE 754
Hello does anyone know if FreeBSD provides the software support for full IEEE 754 conformance on a PowerPC e500v2 core (for example QorIQ series from Freescale)? Have a nice day! -- Sebastian Huber, embedded brains GmbH Address : Obere Lagerstr. 30, D-82178 Puchheim, Germany Phone : +49 89 18 90 80 79-6 Fax : +49 89 18 90 80 79-9 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to freebsd-hackers-unsubscr...@freebsd.org
DMA controller on Northbridge?
How can I tell if the Northbridge on a machine has a built-in DMA controller? And if it does, what device would I use to control it? I ask because I'm working with a PCI card that has a 36-bit physical address limit, and that means bounce buffers when using more than 64GB of memory. I'd prefer not to use bounce buffers, and since the card's memory that I'm using is mapped into the physical space of the FreeBSD host, the entire address space of the card that I care about is available to FreeBSD. So while pio to the card's memory is too slow to be useful, if there was a way to use a DMA controller on the motherboard to get data into and out of the card, that may be preferable to using the card's DMAC with the limited address space. But all that's just theory -- I have no idea how to tell whether the mobo has a DMAC, and if it does, how to control it. Help? :-) Attached is the boot dmesg; I can also run pciconf commands, etc., to help out with figuring out what I have. Thanks, matthew Copyright (c) 2001-2011 Isilon Systems LLC. All rights reserved. Copyright (c) 1992-2011 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. Isilon OneFS vHEAD B_7466(DEBUG): 0x605010E001D2A00: Sat Mar 19 12:02:12 GMT 2011 root@mdf-rnv-1:/data/sb/head/obj/data/sb/head/src/sys/IQ.amd64.debug amd64 WARNING: WITNESS option enabled, expect reduced performance. Isilon: model 44 family 6 stepping 2; highmem enabled. MEMGUARD DEBUGGING ALLOCATOR INITIALIZED: MEMGUARD map base: 0xff800040 MEMGUARD map limit: 0xff87ae548000 MEMGUARD map size: 32212256 KBytes Timecounter i8254 frequency 1193182 Hz quality 0 CPU: Intel(R) Xeon(R) CPU E5620 @ 2.40GHz (2394.02-MHz K8-class CPU) Origin = GenuineIntel Id = 0x206c2 Stepping = 2 Features=0xbfebfbffFPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE Features2=0x29ee3ffSSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,SMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,PCID,DCA,SSE4.1,SSE4.2,POPCNT,AESNI AMD Features=0x2c100800SYSCALL,NX,Page1GB,RDTSCP,LM AMD Features2=0x1LAHF TSC: P-state invariant usable memory = 25647685632 (24459 MB) fix_tunable(): returning 65536 for tunable nbuf, mem = 25769803776 fix_tunable(): returning 65536 for tunable nbuf, mem = 25769803776 avail memory = 24562372608 (23424 MB) fix_tunable(): returning 67108864 for tunable hirunningspace, mem = 25769803776 fix_tunable(): returning 66060288 for tunable lorunningspace, mem = 25769803776 fix_tunable(): returning 1 for tunable lodirtybuffers, mem = 25769803776 fix_tunable(): returning 10250 for tunable hidirtybuffers, mem = 25769803776 fix_tunable(): returning 2562 for tunable dirtybufthresh, mem = 25769803776 ACPI APIC Table: 092110 APIC2013 FreeBSD/SMP: Multiprocessor System Detected: 8 CPUs FreeBSD/SMP: 2 package(s) x 4 core(s) cpu0 (BSP): APIC ID: 0 cpu1 (AP): APIC ID: 2 cpu2 (AP): APIC ID: 18 cpu3 (AP): APIC ID: 20 cpu4 (AP): APIC ID: 32 cpu5 (AP): APIC ID: 34 cpu6 (AP): APIC ID: 50 cpu7 (AP): APIC ID: 52 ioapic0: Changing APIC ID to 1 ioapic1: Changing APIC ID to 3 ioapic0 Version 2.0 irqs 0-23 on motherboard ioapic1 Version 2.0 irqs 24-47 on motherboard registered firmware set isp_1040 registered firmware set isp_1040_it registered firmware set isp_1080 registered firmware set isp_1080_it registered firmware set isp_12160 registered firmware set isp_12160_it registered firmware set isp_2100 registered firmware set isp_2200 registered firmware set isp_2300 registered firmware set isp_2322 registered firmware set isp_2400 imdd0-9: Isilon Mirrored Disk Driver Fibre Channel Device Manager (fcdm) is loaded acpi0: NEC on motherboard acpi0: [ITHREAD] acpi0: Power Button (fixed) acpi0: reservation of 0, a (3) failed acpi0: reservation of 10, bff0 (3) failed Timecounter ACPI-fast frequency 3579545 Hz quality 1000 acpi_timer0: 24-bit timer at 3.579545MHz port 0x808-0x80b on acpi0 acpi_hpet0: High Precision Event Timer iomem 0xfed0-0xfed003ff on acpi0 Timecounter HPET frequency 14318180 Hz quality 2000 pcib0: ACPI Host-PCI bridge port 0xcf8-0xcff on acpi0 pci0: ACPI PCI bus on pcib0 pcib1: ACPI PCI-PCI bridge at device 1.0 on pci0 pci9: ACPI PCI bus on pcib1 pcib2: ACPI PCI-PCI bridge at device 3.0 on pci0 pci8: ACPI PCI bus on pcib2 pci8: serial bus at device 0.0 (no driver attached) pcib3: ACPI PCI-PCI bridge at device 5.0 on pci0 pci7: ACPI PCI bus on pcib3 cxgbc0: Chelsio T320, 2 ports mem 0xfae7e000-0xfae7efff,0xfae7f000-0xfae7 irq 26 at device 0.0 on pci7 cxgbc0: SFP module vendor is FINISAR CORP. cxgbc0: SFP part number is FTLX8571D3BCL cxgbc0: ael2005 phy: modtype:1 cxgbc0: SFP module vendor is FINISAR CORP. cxgbc0: SFP part number is FTLX8571D3BCL cxgbc0: ael2005 phy: modtype:1
Re: PowerPC e500v2 and IEEE 754
On 2011-03-22, at 17:12, Sebastian Huber wrote: Hello does anyone know if FreeBSD provides the software support for full IEEE 754 conformance on a PowerPC e500v2 core (for example QorIQ series from Freescale)? Do you mean using the floating point APU in E500? We basically run with soft floats only, either at GCC level or kernel-side FPU emulation, the floating point APU is not utilised currently. Rafal ___ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to freebsd-hackers-unsubscr...@freebsd.org
Re: GSoC'11: DWARF2 call frame information
Xingxing Pan mprc.pku.edu.cn wrote: Dose full register tracking means to emit DWARF for all the registers's saving and restoring in the life time of the function? Most assembly functions are leaves, so saving/restoring around calls to lower-level functions will be infrequent. I suspect it would be more useful to emit debug records that show how the registers are being used, so that gdb can display meaningful names along with their values. And yes, this requires reading and understanding the comments if the code is well commented, or analyzing the code if it is not well commented. It can't be automated. ___ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to freebsd-hackers-unsubscr...@freebsd.org
Re: DMA controller on Northbridge?
On 3/22/2011 12:11 PM, Matthew Fleming wrote: How can I tell if the Northbridge on a machine has a built-in DMA controller? And if it does, what device would I use to control it? I ask because I'm working with a PCI card that has a 36-bit physical address limit, and that means bounce buffers when using more than 64GB of memory. I'd prefer not to use bounce buffers, and since the card's memory that I'm using is mapped into the physical space of the FreeBSD host, the entire address space of the card that I care about is available to FreeBSD. So while pio to the card's memory is too slow to be useful, if there was a way to use a DMA controller on the motherboard to get data into and out of the card, that may be preferable to using the card's DMAC with the limited address space. But all that's just theory -- I have no idea how to tell whether the mobo has a DMAC, and if it does, how to control it. Help? :-) Attached is the boot dmesg; I can also run pciconf commands, etc., to help out with figuring out what I have. Thanks, matthew ___ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to freebsd-hackers-unsubscr...@freebsd.org Sounds like you are referring to IOMMU: http://software.intel.com/en-us/blogs/2009/03/02/intels-virtualization-for-directed-io-aka-iommu-part-1/ --Mark Tinguely ___ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to freebsd-hackers-unsubscr...@freebsd.org
Re: DMA controller on Northbridge?
On Tue, Mar 22, 2011 at 10:11:04AM -0700, Matthew Fleming wrote: How can I tell if the Northbridge on a machine has a built-in DMA controller? And if it does, what device would I use to control it? I ask because I'm working with a PCI card that has a 36-bit physical address limit, and that means bounce buffers when using more than 64GB of memory. I'd prefer not to use bounce buffers, and since the card's memory that I'm using is mapped into the physical space of the FreeBSD host, the entire address space of the card that I care about is available to FreeBSD. So while pio to the card's memory is too slow to be useful, if there was a way to use a DMA controller on the motherboard to get data into and out of the card, that may be preferable to using the card's DMAC with the limited address space. But all that's just theory -- I have no idea how to tell whether the mobo has a DMAC, and if it does, how to control it. Help? :-) Attached is the boot dmesg; I can also run pciconf commands, etc., to help out with figuring out what I have. I believe what are you looking for is ftp://download.intel.com/technology/.../Intel(r)_VT_for_Direct_IO.pdf On my X58 machine it is shown like this: none6@pci0:0:22:2: class=0x088000 card=0xf38015d9 chip=0x34328086 rev=0x12 hdr=0x00 vendor = 'Intel Corporation' device = 'DMA Engine' class = base peripheral cap 11[80] = MSI-X supports 1 message in map 0x10 cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) cap 01[e0] = powerspec 3 supports D0 D3 current D0 pgpN2wNvBDDeJ.pgp Description: PGP signature
Re: GSoC'11: DWARF2 call frame information
On Tue, Mar 22, 2011 at 11:39:58PM +0800, Xingxing Pan wrote: 2011/3/22 Kostik Belousov kostik...@gmail.com: On Mon, Mar 21, 2011 at 08:32:04PM +0300, Chagin Dmitry wrote: On Mon, Mar 21, 2011 at 05:36:13PM +0800, Xingxing Pan wrote: 2011/3/21 Chagin Dmitry dcha...@freebsd.org: powerfull script. Xingxing Pan hmm, which script? I think enough amd64, i386 and amd64/ia32. I suggest to write a example before continuing the conversation about the GSoC. For example (bcopy || bzero) cpu_switch. Is it ok for you? -- Have fun! chd Hi Chargin, Thank you for your reply. The followings shows how I try to add DWARF for bcopy. --- ../8.2.0/sys/i386/include/asm.h 2011-03-21 14:35:56.111973722 +0800 +++ asm.h 2011-03-21 15:25:31.564636162 +0800 @@ -71,7 +71,7 @@ #define _ENTRY(x) _START_ENTRY; \ .globl CNAME(x); .type CNAME(x),@function; CNAME(x): -#define END(x) .size x, . - x +#define END(x) .cfi_endproc; .size x, . - x #ifdef PROF #define ALTENTRY(x) _ENTRY(x); \ @@ -80,9 +80,10 @@ popl %ebp; \ jmp 9f #define ENTRY(x) _ENTRY(x); \ - pushl %ebp; movl %esp,%ebp; \ + .cfi_startproc; \ + pushl %ebp; .cfi_adjust_cfa_offset 4; movl %esp,%ebp; .cfi_def_cfa_register %ebp; \ call PIC_PLT(HIDENAME(mcount)); \ - popl %ebp; \ + popl %ebp; .cfi_def_cfa %esp, 4; \ --- bcopy.S 2011-03-21 15:51:26.804203809 +0800 +++ ../8.2.0/lib/libc/i386/string/bcopy.S 2011-03-21 14:28:15.023069890 +0800 @@ -51,9 +51,7 @@ ENTRY(bcopy) #endif #endif pushl %esi - .cfi_adjust_cfa_offset 4; pushl %edi - .cfi_adjust_cfa_offset 4; #if defined(MEMCOPY) || defined(MEMMOVE) movl 12(%esp),%edi movl 16(%esp),%esi @@ -77,9 +75,7 @@ ENTRY(bcopy) rep movsb popl %edi - .cfi_adjust_cfa_offset -4; popl %esi - .cfi_adjust_cfa_offset -4; ret 1: addl %ecx,%edi /* copy backwards. */ @@ -98,9 +94,7 @@ ENTRY(bcopy) rep movsl popl %edi - .cfi_adjust_cfa_offset -4; popl %esi - .cfi_adjust_cfa_offset -4; cld ret #ifdef MEMCOPY But I don't know how to add DWARF for cpu_switch, because I have no idea about the circumstance when we need to backtrace through this function. Suppose there's a cpu switch like this, threadA-kernel-threadB. Then should the expected backtrace has the following result? threadB's stack kernel's stack threadA's stack hmm, ok. good, avoid cpu_switch. First of all, please, read style(9) man page. In the second, evaluate the proposed plan (discussed with kib@): 1) Annotate libc, msun, rtld, libthr (you) 1a) Develop and implement a testing plan to verify the implementation. 1b) consider doing full register tracking for assembler code. 2) vdso (I'm) 3) Annotate signal trampolines (you, after vdso) And i'm going to understand what I need to do to start GSoC for you. Thanks! -- Have fun! chd Hi Kostik, I think the basic testing method can be using GDB to set breakpoint in functions and observing the backtrace result. GDB uses Expect. I can learn something from GDB's testsuite. Sounds good. AFAIK, CFA and return address are enough for unwinding. Dose full register tracking means to emit DWARF for all the registers's saving and restoring in the life time of the function? Not only save and restore, but also for move around. I am mostly about the syscall entry sequence on amd64, see the description of the `syscall' instruction and handling of %rcx in libc sources. Rarely used routines could be left aside. pgpyDdqJ4T4Oz.pgp Description: PGP signature
Re: DMA controller on Northbridge?
On Tue, Mar 22, 2011 at 11:12 AM, Kostik Belousov kostik...@gmail.com wrote: On Tue, Mar 22, 2011 at 10:11:04AM -0700, Matthew Fleming wrote: How can I tell if the Northbridge on a machine has a built-in DMA controller? And if it does, what device would I use to control it? I ask because I'm working with a PCI card that has a 36-bit physical address limit, and that means bounce buffers when using more than 64GB of memory. I'd prefer not to use bounce buffers, and since the card's memory that I'm using is mapped into the physical space of the FreeBSD host, the entire address space of the card that I care about is available to FreeBSD. So while pio to the card's memory is too slow to be useful, if there was a way to use a DMA controller on the motherboard to get data into and out of the card, that may be preferable to using the card's DMAC with the limited address space. But all that's just theory -- I have no idea how to tell whether the mobo has a DMAC, and if it does, how to control it. Help? :-) Attached is the boot dmesg; I can also run pciconf commands, etc., to help out with figuring out what I have. I believe what are you looking for is ftp://download.intel.com/technology/.../Intel(r)_VT_for_Direct_IO.pdf This link doesn't work for me. On my X58 machine it is shown like this: none6@pci0:0:22:2: class=0x088000 card=0xf38015d9 chip=0x34328086 rev=0x12 hdr=0x00 vendor = 'Intel Corporation' device = 'DMA Engine' class = base peripheral cap 11[80] = MSI-X supports 1 message in map 0x10 cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) cap 01[e0] = powerspec 3 supports D0 D3 current D0 I do seem to have several DMA Engine entries in pciconf on this hardware. Hopefully the above doc will explain what to do. :-) Thanks, matthew ___ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to freebsd-hackers-unsubscr...@freebsd.org
Re: DMA controller on Northbridge?
On Tue, Mar 22, 2011 at 11:55:59AM -0700, Matthew Fleming wrote: On Tue, Mar 22, 2011 at 11:12 AM, Kostik Belousov kostik...@gmail.com wrote: On Tue, Mar 22, 2011 at 10:11:04AM -0700, Matthew Fleming wrote: How can I tell if the Northbridge on a machine has a built-in DMA controller? And if it does, what device would I use to control it? I ask because I'm working with a PCI card that has a 36-bit physical address limit, and that means bounce buffers when using more than 64GB of memory. I'd prefer not to use bounce buffers, and since the card's memory that I'm using is mapped into the physical space of the FreeBSD host, the entire address space of the card that I care about is available to FreeBSD. So while pio to the card's memory is too slow to be useful, if there was a way to use a DMA controller on the motherboard to get data into and out of the card, that may be preferable to using the card's DMAC with the limited address space. But all that's just theory -- I have no idea how to tell whether the mobo has a DMAC, and if it does, how to control it. Help? :-) Attached is the boot dmesg; I can also run pciconf commands, etc., to help out with figuring out what I have. I believe what are you looking for is ftp://download.intel.com/technology/.../Intel(r)_VT_for_Direct_IO.pdf Oops. ftp://download.intel.com/technology/computing/vptech/Intel(r)_VT_for_Direct_IO.pdf This link doesn't work for me. On my X58 machine it is shown like this: none6@pci0:0:22:2: class=0x088000 card=0xf38015d9 chip=0x34328086 rev=0x12 hdr=0x00 vendor = 'Intel Corporation' device = 'DMA Engine' class = base peripheral cap 11[80] = MSI-X supports 1 message in map 0x10 cap 10[90] = PCI-Express 2 root endpoint max data 128(128) link x0(x0) cap 01[e0] = powerspec 3 supports D0 D3 current D0 I do seem to have several DMA Engine entries in pciconf on this hardware. Hopefully the above doc will explain what to do. :-) Thanks, matthew pgpkII57XvuLo.pgp Description: PGP signature
Re: issues with kern.devstat.all
On Tue, 22 Mar 2011 00:15:06 +0300 Andrey Zonov wrote: AZ Hi, AZ This sysctl contains a binary data. You can see it using -o or -x AZ sysctl's key. AZ Additional information is at devstat(3) manpage. Or try sysutils/devstat :-) -- Mikolaj Golub ___ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to freebsd-hackers-unsubscr...@freebsd.org
Hot-ICE '11 Workshop Is Approaching
We're writing to remind you that the first Workshop on Hot Topics in Management of Internet, Cloud, and Enterprise Networks and Service (Hot-ICE '11) is just a week away. There's still time! Register today and join us in Boston, MA, on March 29, 2011. Hot-ICE '11 will bring together researchers and practitioners working on network and service management in the Internet, cloud, and enterprise domains. The scope of Hot-ICE includes all aspects of network and service management. The program includes sessions on cloud and resource management, service management, network management, and datacenter networking. In addition, a mini-panel will close each session. Check out the full program at: http://www.usenix.org/events/hotice11/tech/ Hot-ICE evolved from earlier Internet Network Management (INM) workshops, which more recently combined with the Workshop on Research on Enterprise Networking (WREN). As such, Hot-ICE, while a new workshop, is serving an established community, but with a broader scope, in recognition of the evolving concerns of the community. Hot-ICE '11 will be co-located with the 8th USENIX Symposium on Networked Systems Design and Implementation (NSDI '11), which will take place March 30-April 1, 2011. Find out more and register today at: http://www.usenix.org/hotice11/progb On behalf of the Hot-ICE '11 Program Committee, Anees Shaikh, IBM Research Kobus Van der Merwe, ATT Labs--Research Hot-ICE '11 Program Co-Chairs hotice11cha...@usenix.org --- Workshop on Hot Topics in Management of Internet, Cloud, and Enterprise Networks and Services (Hot-ICE '11) March 29, 2011 Boston, MA, USA http://www.usenix.org/hotice11/progb Sponsored by USENIX ___ freebsd-hackers@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-hackers To unsubscribe, send any mail to freebsd-hackers-unsubscr...@freebsd.org
