date:20230615

[Freedreno] [PATCH v9 16/20] drm/msm/a6xx: Fix some A619 tunables

2023-06-15 Thread Konrad Dybcio

Adreno 619 expects some tunables to be set differently. Make up for it.

Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support")
Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Akhil P Oommen 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 47aafc9deaf8..97e261d33312 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1306,6 +1306,8 @@ static int hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
+   else if (adreno_is_a619(adreno_gpu))
+   gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000);
else if (adreno_is_a610(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x0008);
else
@@ -1323,7 +1325,9 @@ static int hw_init(struct msm_gpu *gpu)
a6xx_set_ubwc_config(gpu);
 
/* Enable fault detection */
-   if (adreno_is_a610(adreno_gpu))
+   if (adreno_is_a619(adreno_gpu))
+   gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) 
| 0x3f);
+   else if (adreno_is_a610(adreno_gpu))
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) 
| 0x3);
else
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) 
| 0x1f);

-- 
2.41.0

[Freedreno] [PATCH v9 15/20] drm/msm/a6xx: Add A610 support

2023-06-15 Thread Konrad Dybcio

A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
features no GMU, as it's implemented solely on SoCs with SMD_RPM.
What's more interesting is that it does not feature a VDDGX line
either, being powered solely by VDDCX and has an unfortunate hardware
quirk that makes its reset line broken - after a couple of assert/
deassert cycles, it will hang for good and will not wake up again.

This GPU requires mesa changes for proper rendering, and lots of them
at that. The command streams are quite far away from any other A6XX
GPU and hence it needs special care. This patch was validated both
by running an (incomplete) downstream mesa with some hacks (frames
rendered correctly, though some instructions made the GPU hangcheck
which is expected - garbage in, garbage out) and by replaying RD
traces captured with the downstream KGSL driver - no crashes there,
ever.

Add support for this GPU on the kernel side, which comes down to
pretty simply adding A612 HWCG tables, altering a few values and
adding a special case for handling the reset line.

Reviewed-by: Dmitry Baryshkov 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c  | 99 ++
 drivers/gpu/drm/msm/adreno/adreno_device.c | 12 
 drivers/gpu/drm/msm/adreno/adreno_gpu.h|  8 ++-
 3 files changed, 107 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 2ca9e0440396..47aafc9deaf8 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -252,6 +252,56 @@ static void a6xx_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit)
a6xx_flush(gpu, ring);
 }
 
+const struct adreno_reglist a612_hwcg[] = {
+   {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x},
+   {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x0220},
+   {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x0081},
+   {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0xf3cf},
+   {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x},
+   {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x},
+   {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x},
+   {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x0002},
+   {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x},
+   {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x},
+   {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x},
+   {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x0001},
+   {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x},
+   {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x},
+   {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x},
+   {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x0007},
+   {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x},
+   {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x0120},
+   {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x2220},
+   {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
+   {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
+   {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x},
+   {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x0011},
+   {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+   {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x0422},
+   {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x},
+   {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x0222},
+   {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x0002},
+   {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x},
+   {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000},
+   {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x},
+   {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x0200},
+   {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x},
+   {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x},
+   {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x},
+   {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+   {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x},
+   {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x},
+   {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x0004},
+   {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x0002},
+   {REG_A6XX_RBBM_ISDB_CNT, 0x0182},
+   {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x},
+   {REG_A6XX_RBBM_SP_HYST_CNT, 0x},
+   {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x0222},
+   {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x0111},
+   {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x0555},
+   {},
+};
+
 /* For a615 family (a615, a616, a618 and a619) */
 const struct adreno_reglist a615_hwcg[] = {
{REG_A6XX_RBBM_CLOCK_CNTL_SP0,  0x0222},
@@ -659,6 +709,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
 
if (adreno_is_a630(adreno_gpu))
clock_cntl_on = 0x8aa8aa02;
+   else if (adreno_is_a610(adreno_gpu))
+   clock_cntl_on = 0xaaa8aa82;
else
clock_cntl_on = 0x8aa8aa82;
 
@@ -669,13 +721,15 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
return;
 
/* Disable SP clock before programming HWCG registers */
-   gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
+   if (!adreno_is_a610(adreno_gpu))
+

[Freedreno] [PATCH v9 20/20] drm/msm/a6xx: Add A610 speedbin support

2023-06-15 Thread Konrad Dybcio

A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.

Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Akhil P Oommen 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index ff9a8d342c77..b3ada1e7b598 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2204,6 +2204,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct 
msm_ringbuffer *ring)
return progress;
 }
 
+static u32 a610_get_speed_bin(u32 fuse)
+{
+   /*
+* There are (at least) three SoCs implementing A610: SM6125 (trinket),
+* SM6115 (bengal) and SM6225 (khaje). Trinket does not have 
speedbinning,
+* as only a single SKU exists and we don't support khaje upstream yet.
+* Hence, this matching table is only valid for bengal and can be easily
+* expanded if need be.
+*/
+
+   if (fuse == 0)
+   return 0;
+   else if (fuse == 206)
+   return 1;
+   else if (fuse == 200)
+   return 2;
+   else if (fuse == 157)
+   return 3;
+   else if (fuse == 127)
+   return 4;
+
+   return UINT_MAX;
+}
+
 static u32 a618_get_speed_bin(u32 fuse)
 {
if (fuse == 0)
@@ -2301,6 +2325,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct 
adreno_gpu *adreno_gpu, u3
 {
u32 val = UINT_MAX;
 
+   if (adreno_is_a610(adreno_gpu))
+   val = a610_get_speed_bin(fuse);
+
if (adreno_is_a618(adreno_gpu))
val = a618_get_speed_bin(fuse);
 

-- 
2.41.0

[Freedreno] [PATCH v9 18/20] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching

2023-06-15 Thread Konrad Dybcio

Before transitioning to using per-SoC and not per-Adreno speedbin
fuse values (need another patchset to land elsewhere), a good
improvement/stopgap solution is to use adreno_is_aXYZ macros in
place of explicit revision matching. Do so to allow differentiating
between A619 and A619_holi.

Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Akhil P Oommen 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 18 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h | 15 ---
 2 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index d0ba0844079c..d7139eae0f73 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2269,23 +2269,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse)
return UINT_MAX;
 }
 
-static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
+static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, 
u32 fuse)
 {
u32 val = UINT_MAX;
 
-   if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
+   if (adreno_is_a618(adreno_gpu))
val = a618_get_speed_bin(fuse);
 
-   else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev))
+   else if (adreno_is_a619(adreno_gpu))
val = a619_get_speed_bin(fuse);
 
-   else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
+   else if (adreno_is_7c3(adreno_gpu))
val = adreno_7c3_get_speed_bin(fuse);
 
-   else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
+   else if (adreno_is_a640(adreno_gpu))
val = a640_get_speed_bin(fuse);
 
-   else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
+   else if (adreno_is_a650(adreno_gpu))
val = a650_get_speed_bin(fuse);
 
if (val == UINT_MAX) {
@@ -2298,7 +2298,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct 
adreno_rev rev, u32 fuse)
return (1 << val);
 }
 
-static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
+static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu 
*adreno_gpu)
 {
u32 supp_hw;
u32 speedbin;
@@ -2317,7 +2317,7 @@ static int a6xx_set_supported_hw(struct device *dev, 
struct adreno_rev rev)
return ret;
}
 
-   supp_hw = fuse_to_supp_hw(dev, rev, speedbin);
+   supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin);
 
ret = devm_pm_opp_set_supported_hw(dev, _hw, 1);
if (ret)
@@ -2438,7 +2438,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
 
a6xx_llc_slices_init(pdev, a6xx_gpu);
 
-   ret = a6xx_set_supported_hw(>dev, config->rev);
+   ret = a6xx_set_supported_hw(>dev, adreno_gpu);
if (ret) {
a6xx_destroy(&(a6xx_gpu->base.base));
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 3a8af5fdaea8..d8c9e8cc3753 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -279,10 +279,9 @@ static inline int adreno_is_a630(const struct adreno_gpu 
*gpu)
return adreno_is_revn(gpu, 630);
 }
 
-static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
+static inline int adreno_is_a640(const struct adreno_gpu *gpu)
 {
-   return adreno_is_revn(gpu, 640) ||
-   adreno_is_revn(gpu, 680);
+   return adreno_is_revn(gpu, 640);
 }
 
 static inline int adreno_is_a650(const struct adreno_gpu *gpu)
@@ -301,6 +300,11 @@ static inline int adreno_is_a660(const struct adreno_gpu 
*gpu)
return adreno_is_revn(gpu, 660);
 }
 
+static inline int adreno_is_a680(const struct adreno_gpu *gpu)
+{
+   return adreno_is_revn(gpu, 680);
+}
+
 static inline int adreno_is_a690(const struct adreno_gpu *gpu)
 {
return adreno_is_revn(gpu, 690);
@@ -328,6 +332,11 @@ static inline int adreno_is_a650_family(const struct 
adreno_gpu *gpu)
adreno_is_a660_family(gpu);
 }
 
+static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
+{
+   return adreno_is_a640(gpu) || adreno_is_a680(gpu);
+}
+
 u64 adreno_private_address_space_size(struct msm_gpu *gpu);
 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
 uint32_t param, uint64_t *value, uint32_t *len);

-- 
2.41.0

[Freedreno] [PATCH v9 14/20] drm/msm/a6xx: Add support for A619_holi

2023-06-15 Thread Konrad Dybcio

A619_holi is a GMU-less variant of the already-supported A619 GPU.
It's present on at least SM4350 (holi) and SM6375 (blair). No mesa
changes are required. Add the required kernel-side support for it.

Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 27 +--
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  5 +
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index b91fc02eb08c..2ca9e0440396 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -911,6 +911,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
if (adreno_is_a618(adreno_gpu))
return;
 
+   if (adreno_is_a619_holi(adreno_gpu))
+   hbb_lo = 0;
+
if (adreno_is_a640_family(adreno_gpu))
amsbc = 1;
 
@@ -1135,7 +1138,12 @@ static int hw_init(struct msm_gpu *gpu)
}
 
/* Clear GBIF halt in case GX domain was not collapsed */
-   if (a6xx_has_gbif(adreno_gpu)) {
+   if (adreno_is_a619_holi(adreno_gpu)) {
+   gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
+   gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0);
+   /* Let's make extra sure that the GPU can access the memory.. */
+   mb();
+   } else if (a6xx_has_gbif(adreno_gpu)) {
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
/* Let's make extra sure that the GPU can access the memory.. */
@@ -1144,6 +1152,9 @@ static int hw_init(struct msm_gpu *gpu)
 
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
 
+   if (adreno_is_a619_holi(adreno_gpu))
+   a6xx_sptprac_enable(gmu);
+
/*
 * Disable the trusted memory range - we don't actually supported secure
 * memory rendering at this point in time and we don't want to block off
@@ -1760,12 +1771,18 @@ static void a6xx_llc_slices_init(struct platform_device 
*pdev,
 #define GBIF_CLIENT_HALT_MASK  BIT(0)
 #define GBIF_ARB_HALT_MASK BIT(1)
 #define VBIF_XIN_HALT_CTRL0_MASK   GENMASK(3, 0)
+#define VBIF_RESET_ACK_MASK0xF0
+#define GPR0_GBIF_HALT_REQUEST 0x1E0
 
 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool 
gx_off)
 {
struct msm_gpu *gpu = _gpu->base;
 
-   if (!a6xx_has_gbif(adreno_gpu)) {
+   if (adreno_is_a619_holi(adreno_gpu)) {
+   gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST);
+   spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) &
+   (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK);
+   } else if (!a6xx_has_gbif(adreno_gpu)) {
gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 
VBIF_XIN_HALT_CTRL0_MASK);
spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
(VBIF_XIN_HALT_CTRL0_MASK)) == 
VBIF_XIN_HALT_CTRL0_MASK);
@@ -1861,6 +1878,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu)
if (ret)
goto err_bulk_clk;
 
+   if (adreno_is_a619_holi(adreno_gpu))
+   a6xx_sptprac_enable(gmu);
+
/* If anything goes south, tear the GPU down piece by piece.. */
if (ret) {
 err_bulk_clk:
@@ -1920,6 +1940,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
/* Drain the outstanding traffic on memory buses */
a6xx_bus_clear_pending_transactions(adreno_gpu, true);
 
+   if (adreno_is_a619_holi(adreno_gpu))
+   a6xx_sptprac_disable(gmu);
+
clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
 
pm_runtime_put_sync(gmu->gxpd);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index de0b03a4b594..efd35b7bc4cf 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -263,6 +263,11 @@ static inline int adreno_is_a619(const struct adreno_gpu 
*gpu)
return adreno_is_revn(gpu, 619);
 }
 
+static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu)
+{
+   return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu);
+}
+
 static inline int adreno_is_a630(const struct adreno_gpu *gpu)
 {
return adreno_is_revn(gpu, 630);

-- 
2.41.0

[Freedreno] [PATCH v9 13/20] drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations

2023-06-15 Thread Konrad Dybcio

A610 and A619_holi don't support the feature. Disable it to make the GPU stop
crashing after almost each and every submission - the received data on
the GPU end was simply incomplete in garbled, resulting in almost nothing
being executed properly. Extend the disablement to adreno_has_gmu_wrapper,
as none of the GMU wrapper Adrenos that don't support yet seem to feature it.

Reviewed-by: Akhil P Oommen 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/adreno_device.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c 
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index e5a865024e94..6ea24b8ddcf8 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -565,7 +565,6 @@ static int adreno_bind(struct device *dev, struct device 
*master, void *data)
config.rev.minor, config.rev.patchid);
 
priv->is_a2xx = config.rev.core == 2;
-   priv->has_cached_coherent = config.rev.core >= 6;
 
gpu = info->init(drm);
if (IS_ERR(gpu)) {
@@ -577,6 +576,10 @@ static int adreno_bind(struct device *dev, struct device 
*master, void *data)
if (ret)
return ret;
 
+   if (config.rev.core >= 6)
+   if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu)))
+   priv->has_cached_coherent = true;
+
return 0;
 }
 

-- 
2.41.0

[Freedreno] [PATCH v9 19/20] drm/msm/a6xx: Add A619_holi speedbin support

2023-06-15 Thread Konrad Dybcio

A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
(blair). This is what seems to be a first occurrence of this happening,
but it's easy to overcome by guarding the SoC-specific fuse values with
of_machine_is_compatible(). Do just that to enable frequency limiting
on these SoCs.

Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Akhil P Oommen 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index d7139eae0f73..ff9a8d342c77 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2216,6 +2216,34 @@ static u32 a618_get_speed_bin(u32 fuse)
return UINT_MAX;
 }
 
+static u32 a619_holi_get_speed_bin(u32 fuse)
+{
+   /*
+* There are (at least) two SoCs implementing A619_holi: SM4350 (holi)
+* and SM6375 (blair). Limit the fuse matching to the corresponding
+* SoC to prevent bogus frequency setting (as improbable as it may be,
+* given unexpected fuse values are.. unexpected! But still possible.)
+*/
+
+   if (fuse == 0)
+   return 0;
+
+   if (of_machine_is_compatible("qcom,sm4350")) {
+   if (fuse == 138)
+   return 1;
+   else if (fuse == 92)
+   return 2;
+   } else if (of_machine_is_compatible("qcom,sm6375")) {
+   if (fuse == 190)
+   return 1;
+   else if (fuse == 177)
+   return 2;
+   } else
+   pr_warn("Unknown SoC implementing A619_holi!\n");
+
+   return UINT_MAX;
+}
+
 static u32 a619_get_speed_bin(u32 fuse)
 {
if (fuse == 0)
@@ -2276,6 +2304,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct 
adreno_gpu *adreno_gpu, u3
if (adreno_is_a618(adreno_gpu))
val = a618_get_speed_bin(fuse);
 
+   else if (adreno_is_a619_holi(adreno_gpu))
+   val = a619_holi_get_speed_bin(fuse);
+
else if (adreno_is_a619(adreno_gpu))
val = a619_get_speed_bin(fuse);
 

-- 
2.41.0

[Freedreno] [PATCH v9 17/20] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching

2023-06-15 Thread Konrad Dybcio

The GPU can only be one at a time. Turn a series of ifs into if +
elseifs to save some CPU cycles.

Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Akhil P Oommen 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 97e261d33312..d0ba0844079c 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2276,16 +2276,16 @@ static u32 fuse_to_supp_hw(struct device *dev, struct 
adreno_rev rev, u32 fuse)
if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
val = a618_get_speed_bin(fuse);
 
-   if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev))
+   else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev))
val = a619_get_speed_bin(fuse);
 
-   if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
+   else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
val = adreno_7c3_get_speed_bin(fuse);
 
-   if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
+   else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
val = a640_get_speed_bin(fuse);
 
-   if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
+   else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
val = a650_get_speed_bin(fuse);
 
if (val == UINT_MAX) {

-- 
2.41.0

[Freedreno] [PATCH v9 11/20] drm/msm/a6xx: Move CX GMU power counter enablement to hw_init

2023-06-15 Thread Konrad Dybcio

Since the introduction of A6xx support, we've been enabling the CX GMU
power counter 0 in a bit of a weird spot. Move it to hw_init so that
GMU wrapper GPUs can reuse the same code paths. As a bonus, this order
makes it easier to compare mainline and downstream register access traces.

Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 --
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 906bed49f27d..aae7ea651607 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -479,12 +479,6 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
 
gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
 
-   /* Set up CX GMU counter 0 to count busy ticks */
-   gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff00);
-   gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20);
-
-   /* Enable the power counter */
-   gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
return 0;
 }
 
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 8aa4670b4308..0efecde2af1a 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1256,6 +1256,13 @@ static int hw_init(struct msm_gpu *gpu)
0x3f0243f0);
}
 
+   /* Set up the CX GMU counter 0 to count busy ticks */
+   gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff00);
+
+   /* Enable the power counter */
+   gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5));
+   gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
+
/* Protect registers from the CP */
a6xx_set_cp_protect(gpu);
 

-- 
2.41.0

[Freedreno] [PATCH v9 12/20] drm/msm/a6xx: Introduce GMU wrapper support

2023-06-15 Thread Konrad Dybcio

Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
but don't implement the associated GMUs. This is due to the fact that
the GMU directly pokes at RPMh. Sadly, this means we have to take care
of enabling & scaling power rails, clocks and bandwidth ourselves.

Reuse existing Adreno-common code and modify the deeply-GMU-infused
A6XX code to facilitate these GPUs. This involves if-ing out lots
of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's
the actual name that Qualcomm uses in their downstream kernels).

This is essentially a register region which is convenient to model
as a device. We'll use it for managing the GDSCs. The register
layout matches the actual GMU_CX/GX regions on the "real GMU" devices
and lets us reuse quite a bit of gmu_read/write/rmw calls.

Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c   |  72 +-
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 201 
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h   |   1 +
 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c |  14 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.c |   8 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |   6 +
 6 files changed, 266 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index aae7ea651607..5deb79924897 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -1431,6 +1431,7 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct 
platform_device *pdev,
 
 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
 {
+   struct adreno_gpu *adreno_gpu = _gpu->base;
struct a6xx_gmu *gmu = _gpu->gmu;
struct platform_device *pdev = to_platform_device(gmu->dev);
 
@@ -1456,10 +1457,12 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
gmu->mmio = NULL;
gmu->rscc = NULL;
 
-   a6xx_gmu_memory_free(gmu);
+   if (!adreno_has_gmu_wrapper(adreno_gpu)) {
+   a6xx_gmu_memory_free(gmu);
 
-   free_irq(gmu->gmu_irq, gmu);
-   free_irq(gmu->hfi_irq, gmu);
+   free_irq(gmu->gmu_irq, gmu);
+   free_irq(gmu->hfi_irq, gmu);
+   }
 
/* Drop reference taken in of_find_device_by_node */
put_device(gmu->dev);
@@ -1478,6 +1481,69 @@ static int cxpd_notifier_cb(struct notifier_block *nb,
return 0;
 }
 
+int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
+{
+   struct platform_device *pdev = of_find_device_by_node(node);
+   struct a6xx_gmu *gmu = _gpu->gmu;
+   int ret;
+
+   if (!pdev)
+   return -ENODEV;
+
+   gmu->dev = >dev;
+
+   of_dma_configure(gmu->dev, node, true);
+
+   pm_runtime_enable(gmu->dev);
+
+   /* Mark legacy for manual SPTPRAC control */
+   gmu->legacy = true;
+
+   /* Map the GMU registers */
+   gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
+   if (IS_ERR(gmu->mmio)) {
+   ret = PTR_ERR(gmu->mmio);
+   goto err_mmio;
+   }
+
+   gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
+   if (IS_ERR(gmu->cxpd)) {
+   ret = PTR_ERR(gmu->cxpd);
+   goto err_mmio;
+   }
+
+   if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) {
+   ret = -ENODEV;
+   goto detach_cxpd;
+   }
+
+   init_completion(>pd_gate);
+   complete_all(>pd_gate);
+   gmu->pd_nb.notifier_call = cxpd_notifier_cb;
+
+   /* Get a link to the GX power domain to reset the GPU */
+   gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
+   if (IS_ERR(gmu->gxpd)) {
+   ret = PTR_ERR(gmu->gxpd);
+   goto err_mmio;
+   }
+
+   gmu->initialized = true;
+
+   return 0;
+
+detach_cxpd:
+   dev_pm_domain_detach(gmu->cxpd, false);
+
+err_mmio:
+   iounmap(gmu->mmio);
+
+   /* Drop reference taken in of_find_device_by_node */
+   put_device(gmu->dev);
+
+   return ret;
+}
+
 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
 {
struct adreno_gpu *adreno_gpu = _gpu->base;
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 0efecde2af1a..b91fc02eb08c 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -21,7 +21,7 @@ static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 
/* Check that the GMU is idle */
-   if (!a6xx_gmu_isidle(_gpu->gmu))
+   if (!adreno_has_gmu_wrapper(adreno_gpu) && 
!a6xx_gmu_isidle(_gpu->gmu))
return false;
 
/* Check tha the CX master is idle */
@@ -1126,10 +1126,13 @@ static int hw_init(struct msm_gpu *gpu)
 {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+

[Freedreno] [PATCH v9 10/20] drm/msm/a6xx: Extend and explain UBWC config

2023-06-15 Thread Konrad Dybcio

Rename lower_bit to hbb_lo and explain what it signifies.
Add explanations (wherever possible to other tunables).

Port setting min_access_length, ubwc_mode and hbb_hi from downstream.

Reviewed-by: Rob Clark 
Reviewed-by: Akhil P Oommen 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 41 ++-
 1 file changed, 31 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 7e0d1dfcd993..8aa4670b4308 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -887,10 +887,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
 {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-   u32 lower_bit = 2;
-   u32 amsbc = 0;
+   /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */
u32 rgb565_predicator = 0;
+   /* Unknown, introduced with A650 family */
u32 uavflagprd_inv = 0;
+   /* Whether the minimum access length is 64 bits */
+   u32 min_acc_len = 0;
+   /* Entirely magic, per-GPU-gen value */
+   u32 ubwc_mode = 0;
+   /*
+* The Highest Bank Bit value represents the bit of the highest DDR 
bank.
+* We then subtract 13 from it (13 is the minimum value allowed by hw) 
and
+* write the lowest two bits of the remaining value as hbb_lo and the
+* one above it as hbb_hi to the hardware. This should ideally use DRAM
+* type detection.
+*/
+   u32 hbb_hi = 0;
+   u32 hbb_lo = 2;
+   /* Unknown, introduced with A640/680 */
+   u32 amsbc = 0;
 
/* a618 is using the hw default values */
if (adreno_is_a618(adreno_gpu))
@@ -901,32 +916,38 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
 
if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) {
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
-   lower_bit = 3;
+   hbb_lo = 3;
amsbc = 1;
rgb565_predicator = 1;
uavflagprd_inv = 2;
}
 
if (adreno_is_a690(adreno_gpu)) {
-   lower_bit = 2;
+   hbb_lo = 2;
amsbc = 1;
rgb565_predicator = 1;
uavflagprd_inv = 2;
}
 
if (adreno_is_7c3(adreno_gpu)) {
-   lower_bit = 1;
+   hbb_lo = 1;
amsbc = 1;
rgb565_predicator = 1;
uavflagprd_inv = 2;
}
 
gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
-   rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
-   gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
-   gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
-   uavflagprd_inv << 4 | lower_bit << 1);
-   gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
+ rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 |
+ min_acc_len << 3 | hbb_lo << 1 | ubwc_mode);
+
+   gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 |
+ min_acc_len << 3 | hbb_lo << 1 | ubwc_mode);
+
+   gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 |
+ uavflagprd_inv << 4 | min_acc_len << 3 |
+ hbb_lo << 1 | ubwc_mode);
+
+   gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 
21);
 }
 
 static int a6xx_cp_init(struct msm_gpu *gpu)

-- 
2.41.0

[Freedreno] [PATCH v9 06/20] drm/msm/a6xx: Move a6xx_bus_clear_pending_transactions to a6xx_gpu

2023-06-15 Thread Konrad Dybcio

This function is responsible for telling the GPU to halt transactions
on all of its relevant buses, drain them and leave them in a predictable
state, so that the GPU can be e.g. reset cleanly.

Move the function to a6xx_gpu.c, remove the static keyword and add a
prototype in a6xx_gpu.h to accomodate for the move.

Reviewed-by: Akhil P Oommen 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 37 ---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 36 ++
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h |  2 ++
 3 files changed, 38 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 32852c161aab..6402544f6849 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -868,43 +868,6 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
(val & 1), 100, 1000);
 }
 
-#define GBIF_CLIENT_HALT_MASK BIT(0)
-#define GBIF_ARB_HALT_MASKBIT(1)
-
-static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu,
-   bool gx_off)
-{
-   struct msm_gpu *gpu = _gpu->base;
-
-   if (!a6xx_has_gbif(adreno_gpu)) {
-   gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
-   spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
-   0xf) == 0xf);
-   gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
-
-   return;
-   }
-
-   if (gx_off) {
-   /* Halt the gx side of GBIF */
-   gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1);
-   spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1);
-   }
-
-   /* Halt new client requests on GBIF */
-   gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
-   spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
-   (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
-
-   /* Halt all AXI requests on GBIF */
-   gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
-   spin_until((gpu_read(gpu,  REG_A6XX_GBIF_HALT_ACK) &
-   (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
-
-   /* The GBIF halt needs to be explicitly cleared */
-   gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
-}
-
 /* Force the GMU off in case it isn't responsive */
 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
 {
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index eebb4bc7c0f9..a48f4e3a754a 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1705,6 +1705,42 @@ static void a6xx_llc_slices_init(struct platform_device 
*pdev,
a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+#define GBIF_CLIENT_HALT_MASK BIT(0)
+#define GBIF_ARB_HALT_MASKBIT(1)
+
+void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool 
gx_off)
+{
+   struct msm_gpu *gpu = _gpu->base;
+
+   if (!a6xx_has_gbif(adreno_gpu)) {
+   gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
+   spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
+   0xf) == 0xf);
+   gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
+
+   return;
+   }
+
+   if (gx_off) {
+   /* Halt the gx side of GBIF */
+   gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1);
+   spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1);
+   }
+
+   /* Halt new client requests on GBIF */
+   gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
+   spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
+   (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
+
+   /* Halt all AXI requests on GBIF */
+   gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
+   spin_until((gpu_read(gpu,  REG_A6XX_GBIF_HALT_ACK) &
+   (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
+
+   /* The GBIF halt needs to be explicitly cleared */
+   gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
+}
+
 static int a6xx_pm_resume(struct msm_gpu *gpu)
 {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index eea2e60ce3b7..9580def06d45 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -88,4 +88,6 @@ void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state 
*state,
 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
 int a6xx_gpu_state_put(struct msm_gpu_state *state);
 
+void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool 
gx_off);
+
 #endif /* __A6XX_GPU_H__ */

-- 
2.41.0

[Freedreno] [PATCH v9 09/20] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init

2023-06-15 Thread Konrad Dybcio

Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
need REG_A6XX_GBIF_HALT to be set to 0.

This is typically done automatically on successful GX collapse, but in
case that fails, we should take care of it.

Also, add a memory barrier to ensure it's gone through before jumping
to further initialization.

Reviewed-by: Dmitry Baryshkov 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index b627be3f6360..7e0d1dfcd993 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -,8 +,12 @@ static int hw_init(struct msm_gpu *gpu)
a6xx_gmu_set_oob(_gpu->gmu, GMU_OOB_GPU_SET);
 
/* Clear GBIF halt in case GX domain was not collapsed */
-   if (a6xx_has_gbif(adreno_gpu))
+   if (a6xx_has_gbif(adreno_gpu)) {
+   gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
+   /* Let's make extra sure that the GPU can access the memory.. */
+   mb();
+   }
 
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
 

-- 
2.41.0

[Freedreno] [PATCH v9 08/20] drm/msm/a6xx: Add a helper for software-resetting the GPU

2023-06-15 Thread Konrad Dybcio

Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper
GPUs and reuse it in a6xx_gmu_force_off().

This helper, contrary to the original usage in GMU code paths, adds
a readback+delay sequence to ensure that the reset is never deasserted
too quickly due to e.g. OoO execution going crazy.

Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c |  3 +--
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h |  1 +
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 6402544f6849..906bed49f27d 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -899,8 +899,7 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
a6xx_bus_clear_pending_transactions(adreno_gpu, true);
 
/* Reset GPU core blocks */
-   gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1);
-   udelay(100);
+   a6xx_gpu_sw_reset(gpu, true);
 }
 
 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu 
*gmu)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index d5bd008c2947..b627be3f6360 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1742,6 +1742,18 @@ void a6xx_bus_clear_pending_transactions(struct 
adreno_gpu *adreno_gpu, bool gx_
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
 }
 
+void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert)
+{
+   gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert);
+   /* Perform a bogus read and add a brief delay to ensure ordering. */
+   gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD);
+   udelay(1);
+
+   /* The reset line needs to be asserted for at least 100 us */
+   if (assert)
+   udelay(100);
+}
+
 static int a6xx_pm_resume(struct msm_gpu *gpu)
 {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 9580def06d45..aa70390ee1c6 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -89,5 +89,6 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
 int a6xx_gpu_state_put(struct msm_gpu_state *state);
 
 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool 
gx_off);
+void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert);
 
 #endif /* __A6XX_GPU_H__ */

-- 
2.41.0

[Freedreno] [PATCH v9 07/20] drm/msm/a6xx: Improve a6xx_bus_clear_pending_transactions()

2023-06-15 Thread Konrad Dybcio

Unify the indentation and explain the cryptic 0xF value.

Reviewed-by: Akhil P Oommen 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index a48f4e3a754a..d5bd008c2947 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1705,17 +1705,18 @@ static void a6xx_llc_slices_init(struct platform_device 
*pdev,
a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
-#define GBIF_CLIENT_HALT_MASK BIT(0)
-#define GBIF_ARB_HALT_MASKBIT(1)
+#define GBIF_CLIENT_HALT_MASK  BIT(0)
+#define GBIF_ARB_HALT_MASK BIT(1)
+#define VBIF_XIN_HALT_CTRL0_MASK   GENMASK(3, 0)
 
 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool 
gx_off)
 {
struct msm_gpu *gpu = _gpu->base;
 
if (!a6xx_has_gbif(adreno_gpu)) {
-   gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
+   gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 
VBIF_XIN_HALT_CTRL0_MASK);
spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
-   0xf) == 0xf);
+   (VBIF_XIN_HALT_CTRL0_MASK)) == 
VBIF_XIN_HALT_CTRL0_MASK);
gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
 
return;

-- 
2.41.0

[Freedreno] [PATCH v9 03/20] drm/msm/adreno: Use adreno_is_revn for A690

2023-06-15 Thread Konrad Dybcio

The adreno_is_revn rework came at the same time as A690 introduction
and that resulted in it not covering all cases. Fix it.

Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 9a7626c7ac4d..5a26c8a2de7c 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -286,7 +286,7 @@ static inline int adreno_is_a660(const struct adreno_gpu 
*gpu)
 
 static inline int adreno_is_a690(const struct adreno_gpu *gpu)
 {
-   return gpu->revn == 690;
+   return adreno_is_revn(gpu, 690);
 };
 
 /* check for a615, a616, a618, a619 or any derivatives */

-- 
2.41.0

[Freedreno] [PATCH v9 02/20] dt-bindings: display/msm/gmu: Add GMU wrapper

2023-06-15 Thread Konrad Dybcio

The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat these de-facto GMU-less parts in a way that's very similar to their
GMU-equipped cousins, massively saving up on code duplication.

The "wrapper" register space was specifically designed to mimic the layout
of a real GMU, though it rather obviously does not have the M3 core et al.

To sum it all up, the GMU wrapper is essentially a register space within
the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks,
interrupts, multiple reg spaces, iommus and OPP. Document it.

Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Konrad Dybcio 
---
 .../devicetree/bindings/display/msm/gmu.yaml   | 50 --
 1 file changed, 38 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml 
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index f31a26305ca9..5fc4106110ad 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -19,16 +19,18 @@ description: |
 
 properties:
   compatible:
-items:
-  - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
-  - const: qcom,adreno-gmu
+oneOf:
+  - items:
+  - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
+  - const: qcom,adreno-gmu
+  - const: qcom,adreno-gmu-wrapper
 
   reg:
-minItems: 3
+minItems: 1
 maxItems: 4
 
   reg-names:
-minItems: 3
+minItems: 1
 maxItems: 4
 
   clocks:
@@ -44,7 +46,6 @@ properties:
   - description: GMU HFI interrupt
   - description: GMU interrupt
 
-
   interrupt-names:
 items:
   - const: hfi
@@ -72,14 +73,8 @@ required:
   - compatible
   - reg
   - reg-names
-  - clocks
-  - clock-names
-  - interrupts
-  - interrupt-names
   - power-domains
   - power-domain-names
-  - iommus
-  - operating-points-v2
 
 additionalProperties: false
 
@@ -218,6 +213,28 @@ allOf:
 - const: axi
 - const: memnoc
 
+  - if:
+  properties:
+compatible:
+  contains:
+const: qcom,adreno-gmu-wrapper
+then:
+  properties:
+reg:
+  items:
+- description: GMU wrapper register space
+reg-names:
+  items:
+- const: gmu
+else:
+  required:
+- clocks
+- clock-names
+- interrupts
+- interrupt-names
+- iommus
+- operating-points-v2
+
 examples:
   - |
 #include 
@@ -250,3 +267,12 @@ examples:
 iommus = <_smmu 5>;
 operating-points-v2 = <_opp_table>;
 };
+
+gmu_wrapper: gmu@596a000 {
+compatible = "qcom,adreno-gmu-wrapper";
+reg = <0x0596a000 0x3>;
+reg-names = "gmu";
+power-domains = < GPU_CX_GDSC>,
+< GPU_GX_GDSC>;
+power-domain-names = "cx", "gx";
+};

-- 
2.41.0

[Freedreno] [PATCH v9 04/20] drm/msm/a6xx: Remove static keyword from sptprac en/disable functions

2023-06-15 Thread Konrad Dybcio

These two will be reused by at least A619_holi in the non-gmu
paths. Turn them non-static them to make it possible.

Reviewed-by: Dmitry Baryshkov 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++--
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 8914992378f2..a6fa273d700e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -354,7 +354,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum 
a6xx_gmu_oob_state state)
 }
 
 /* Enable CPU control of SPTP power power collapse */
-static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
+int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
 {
int ret;
u32 val;
@@ -376,7 +376,7 @@ static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
 }
 
 /* Disable CPU control of SPTP power power collapse */
-static void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
+void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
 {
u32 val;
int ret;
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h 
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
index 4759a8ce51e4..236f81a43caa 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
@@ -193,5 +193,7 @@ int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index);
 
 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
+void a6xx_sptprac_disable(struct a6xx_gmu *gmu);
+int a6xx_sptprac_enable(struct a6xx_gmu *gmu);
 
 #endif

-- 
2.41.0

[Freedreno] [PATCH v9 05/20] drm/msm/a6xx: Move force keepalive vote removal to a6xx_gmu_force_off()

2023-06-15 Thread Konrad Dybcio

As pointed out by Akhil during the review process of GMU wrapper
introduction [1], it makes sense to move this write into the function
that's responsible for forcibly shutting the GMU off.

It is also very convenient to move this to GMU-specific code, so that
it does not have to be guarded by an if-condition to avoid calling it
on GMU wrapper targets.

Move the write to the aforementioned a6xx_gmu_force_off() to achieve
that. No effective functional change.

[1] 
https://lore.kernel.org/linux-arm-msm/20230501194022.ga18...@akhilpo-linux.qualcomm.com/

Reviewed-by: Akhil P Oommen 
Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 ++
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 --
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index a6fa273d700e..32852c161aab 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -912,6 +912,12 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
struct adreno_gpu *adreno_gpu = _gpu->base;
struct msm_gpu *gpu = _gpu->base;
 
+   /*
+* Turn off keep alive that might have been enabled by the hang
+* interrupt
+*/
+   gmu_write(_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
+
/* Flush all the queues */
a6xx_hfi_stop(gmu);
 
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index ab5c446e4409..eebb4bc7c0f9 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1382,12 +1382,6 @@ static void a6xx_recover(struct msm_gpu *gpu)
/* Halt SQE first */
gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3);
 
-   /*
-* Turn off keep alive that might have been enabled by the hang
-* interrupt
-*/
-   gmu_write(_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
-
pm_runtime_dont_use_autosuspend(>pdev->dev);
 
/* active_submit won't change until we make a submission */

-- 
2.41.0

[Freedreno] [PATCH v9 01/20] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx

2023-06-15 Thread Konrad Dybcio

The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat these de-facto GMU-less parts in a way that's very similar to their
GMU-equipped cousins, massively saving up on code duplication.

The "wrapper" register space was specifically designed to mimic the layout
of a real GMU, though it rather obviously does not have the M3 core et al.

GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be
specified under the GPU node, just like their older cousins. Account
for that.

Acked-by: Rob Herring 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Konrad Dybcio 
---
 .../devicetree/bindings/display/msm/gpu.yaml   | 61 ++
 1 file changed, 52 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml 
b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 5dabe7b6794b..58ca8912a8c3 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -36,10 +36,7 @@ properties:
 
   reg-names:
 minItems: 1
-items:
-  - const: kgsl_3d0_reg_memory
-  - const: cx_mem
-  - const: cx_dbgc
+maxItems: 3
 
   interrupts:
 maxItems: 1
@@ -157,16 +154,62 @@ allOf:
   required:
 - clocks
 - clock-names
+
   - if:
   properties:
 compatible:
   contains:
-pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
-
-then: # Since Adreno 6xx series clocks should be defined in GMU
+enum:
+  - qcom,adreno-610.0
+  - qcom,adreno-619.1
+then:
   properties:
-clocks: false
-clock-names: false
+clocks:
+  minItems: 6
+  maxItems: 6
+
+clock-names:
+  items:
+- const: core
+  description: GPU Core clock
+- const: iface
+  description: GPU Interface clock
+- const: mem_iface
+  description: GPU Memory Interface clock
+- const: alt_mem_iface
+  description: GPU Alternative Memory Interface clock
+- const: gmu
+  description: CX GMU clock
+- const: xo
+  description: GPUCC clocksource clock
+
+reg-names:
+  minItems: 1
+  items:
+- const: kgsl_3d0_reg_memory
+- const: cx_dbgc
+
+  required:
+- clocks
+- clock-names
+else:
+  if:
+properties:
+  compatible:
+contains:
+  pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
+
+  then: # Starting with A6xx, the clocks are usually defined in the GMU 
node
+properties:
+  clocks: false
+  clock-names: false
+
+  reg-names:
+minItems: 1
+items:
+  - const: kgsl_3d0_reg_memory
+  - const: cx_mem
+  - const: cx_dbgc
 
 examples:
   - |

-- 
2.41.0

[Freedreno] [PATCH v9 00/20] GMU-less A6xx support (A610, A619_holi)

2023-06-15 Thread Konrad Dybcio

v8 -> v9:
- Re-pick-up Krzysztof's lost r-b tag (I messed up, sorry)
- Rebase on constifying-adreno_is_aXYZ and A690 changes
- Fix A610 inactive period
- Move the stray A619 register write from A610 patch to the A619 patch
- Add one more commit, cleaning up A690 addition for git context (for adding
  adreno_is_a680 in "Use adreno_is_aXYZ macros in speedbin matching")
- Use a readback+delay combo instead of a memory barrier in sw reset
- Separate out GMU CX power counter moving
- Pick up tags from v8
v8: 
https://lore.kernel.org/r/20230223-topic-gmuwrapper-v8-0-69c682066...@linaro.org

v7 -> v8:
- Fix up resume/suspend (icc now correctly parks to 0, don't abuse
  OPP & genpd throughout system-wide suspend)
- Don't handle ebi1_clk separately, the bulk ops handle it just fine
- Rebase on next-20230525 (no meaningful changes)

v7: 
https://lore.kernel.org/linux-arm-msm/20230223-topic-gmuwrapper-v7-0-ecc7aab83...@linaro.org/

v6 -> v7:
- Rebase on next-20230519 (A640/650 speedbin merged already)

- separate out the .get_timestamp cb for gmu wrapper

- check for gmu presence inside a6xx_llc_slices_(init|destroy) instead
  of before calling them

- use REG_A6XX_RBBM_GPR0_CNTL instead of literal 0x18

- move a6xx_bus_clear_pending_transactions to a6xx_gpu, clean it up
  and reuse it for gmu wrapper gpus

- drop clearing RBBM_GBIF (GBIF from GX's POV) as part of draining the
  buses, it's not necessary

- introduce a helper for gpu softreset

- sw-reset the gmu wrapper GPUS *after* draining GBIF and only reset
  it if it's hung

- reword the commit message in "Remove both GBIF and RBBM GBIF halt
  on hw init" and move it before gmu wrapper-specific changes

- drop set_rate logic from a6xx_pm_suspend as the clock simply gets
  disabled and we don't have to worry about scaling problems as OPP
  and devfreq take care of that, validated with debugcc

- drop a level of indentation in _a6xx_check_idle() to hopefully
  improve readability

- check for !a610 instead of gmu_wrapper||a619_holi in sptprac cc
  toggling in a6xx_set_hwcg()

- pick up krzk's rb on bindings

All external dependencies have been merged since the last revision.

v6: 
https://lore.kernel.org/r/20230223-topic-gmuwrapper-v6-0-2034115bb...@linaro.org

v5 -> v6:
- Rebase on 8ead96783163 ("drm/msm/gpu: Move BO allocation out of hw_init")
  (Add .ucode_load to funcs_gmuwrapper)
- Drop A6[45]0 speedbin deps, merged into msm-next

Dependencies:
- 
https://lore.kernel.org/linux-arm-msm/20230330231517.2747024-1-konrad.dyb...@linaro.org/
 (to work properly)

v5: 
https://lore.kernel.org/linux-arm-msm/20230223-topic-gmuwrapper-v5-0-bf774b9a9...@linaro.org/

v4 -> v5:
- Add a newline before the new allOf:if: [3/15]
- Enforce 6 clocks on A619_holi/A610 [2/15]
- Pick up tags
- Improve error handling in a6xx_pm_resume [6/15]
- Add patch [1/15] (fix an existing issue) which can be picked
  separately and account for it in [6/15]
- Rebase atop Akhil's CX shutdown patches and incorporate analogous logic
- Fix a regression introduced in v3 that made the fw loader expect
  GMU fw on GMU wrapper GPUs

Dependencies:
- 
https://lore.kernel.org/linux-arm-msm/20230120172233.1905761-1-konrad.dyb...@linaro.org/
 (to apply)
- 
https://lore.kernel.org/linux-arm-msm/20230330231517.2747024-1-konrad.dyb...@linaro.org/
 (to work properly)

v4: 
https://lore.kernel.org/r/20230223-topic-gmuwrapper-v4-0-e987eb79d...@linaro.org

v3 -> v4:
- Drop the mistakengly-included and wrong A3xx-A5xx bindings changes
- Improve bindings commit messages to better explain what GMU Wrapper is
- Drop the A680 highest bank bit value adjustment patch
- Sort UBWC config variables in a reverse-Christmass-tree fashion [4/14]
- Don't alter any UBWC config values in [4/14]
  - Do so for a619_holi in [8/14]
- Rebase on next-20230314 (shouldn't matter at all)

v3: 
https://lore.kernel.org/r/20230223-topic-gmuwrapper-v3-0-5be55a336...@linaro.org

v2 -> v3:
New dependencies:
- 
https://lore.kernel.org/linux-arm-msm/20230223-topic-opp-v3-0-5f22163cd...@linaro.org/T/#t
- 
https://lore.kernel.org/linux-arm-msm/20230120172233.1905761-1-konrad.dyb...@linaro.org/

Sidenote: A speedbin rework is in progress, the of_machine_is_compatible
calls in A619_holi are ugly (but well, necessary..) but they'll be
replaced with socid matching in this or the next kernel cycle.

Due to the new way of identifying GMU wrapper GPUs, configuring 6350
to use wrapper would cause the wrong fuse values to be checked, but that
will be solved by the conversion + the ultimate goal is to use the GMU
whenever possible with the wrapper left for GMU-less Adrenos and early
bringup debugging of GMU-equipped ones.

- Ship dt-bindings in this series as we're referencing the compatible now

- "De-staticize" -> "remove static keyword" [3/15]

- Track down all the values in [4/15]

- Add many comments and explanations in [4/15]

- Fix possible return-before-mutex-unlock [5/15]

- Explain the GMU wrapper a bit more in the commit msg [5/15]

- Separate out

Re: [Freedreno] [PATCH v2 00/22]drm/msm/dpu: another catalog rework

2023-06-15 Thread Marijn Suijten

On 2023-06-15 14:31:22, Dmitry Baryshkov wrote:
> 
> On Tue, 13 Jun 2023 03:09:39 +0300, Dmitry Baryshkov wrote:
> > Having a macro with 10 arguments doesn't seem like a good idea. It makes
> > it inherently harder to compare the actual structure values. Also this
> > leads to adding macros covering varieties of the block.
> > 
> > As it was previously discussed, inline all foo_BLK macros in order to
> > ease performing changes to the catalog data.
> > 
> > [...]
> 
> Applied, thanks!
> 
> [01/22] drm/msm/dpu: fix sc7280 and sc7180 PINGPONG done interrupts
> https://gitlab.freedesktop.org/lumag/msm/-/commit/5efc0fec31d8
> [02/22] drm/msm/dpu: correct MERGE_3D length
> https://gitlab.freedesktop.org/lumag/msm/-/commit/f01fb5e211fd
> [03/22] drm/msm/dpu: remove unused INTF_NONE interfaces
> https://gitlab.freedesktop.org/lumag/msm/-/commit/17bf6f8efc50

The first two patches are fixes, the third one is not?

- Marijn

> 
> Best regards,
> -- 
> Dmitry Baryshkov

Re: [Freedreno] [PATCH v2 05/22] drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n

2023-06-15 Thread Marijn Suijten

On 2023-06-13 03:09:44, Dmitry Baryshkov wrote:
> In several catalog entries we did not use existing MSM_DP_CONTROLLER_n
> constants. Fill them in. Also use freshly defined MSM_DSI_CONTROLLER_n
> for DSI interfaces.
> 
> Signed-off-by: Dmitry Baryshkov 
> ---
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h  | 6 +++---
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h   | 8 
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h   | 8 
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h  | 4 ++--
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h   | 8 
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h   | 2 +-
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h   | 2 +-
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h  | 2 +-

6_4_sm6350 and 6_9_sm6375 are missing from this series.

For the rest:

Reviewed-by: Marijn Suijten 

>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h   | 4 ++--
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h   | 2 +-
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++--
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h   | 4 ++--
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h   | 4 ++--
>  13 files changed, 29 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 7d0d0e74c3b0..be0514bf27ec 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -139,13 +139,13 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
>  };
>  
>  static const struct dpu_intf_cfg msm8998_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21, 
> INTF_SDM845_MASK,
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 
> MSM_DP_CONTROLLER_0, 21, INTF_SDM845_MASK,
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21, 
> INTF_SDM845_MASK,
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 
> MSM_DSI_CONTROLLER_0, 21, INTF_SDM845_MASK,
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21, 
> INTF_SDM845_MASK,
> + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 
> MSM_DSI_CONTROLLER_1, 21, INTF_SDM845_MASK,
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
>   INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, 
> INTF_SDM845_MASK,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index b6098141bb9b..b33472625fcb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -143,16 +143,16 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = {
>  };
>  
>  static const struct dpu_intf_cfg sdm845_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, 
> INTF_SDM845_MASK,
> + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 
> MSM_DP_CONTROLLER_0, 24, INTF_SDM845_MASK,
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, 
> INTF_SDM845_MASK,
> + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 
> MSM_DSI_CONTROLLER_0, 24, INTF_SDM845_MASK,
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, 
> INTF_SDM845_MASK,
> + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 
> MSM_DSI_CONTROLLER_1, 24, INTF_SDM845_MASK,
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, 
> INTF_SDM845_MASK,
> + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 
> MSM_DP_CONTROLLER_1, 24, INTF_SDM845_MASK,
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
>  };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index b5f751354267..64ed10da1b73 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -162,18 +162,18 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
>  };
>  
>  static const struct dpu_intf_cfg sm8150_intf[] = {
> - INTF_BLK("intf_0", INTF_0,

Re: [Freedreno] [PATCH v2 04/22] drm/msm: enumerate DSI interfaces

2023-06-15 Thread Marijn Suijten

On 2023-06-13 03:09:43, Dmitry Baryshkov wrote:
> Follow the DP example and define MSM_DSI_CONTROLLER_n enumeration.
> 
> Signed-off-by: Dmitry Baryshkov 

Nice, that'll be cleaner.

Reviewed-by: Marijn Suijten 

> ---
>  drivers/gpu/drm/msm/msm_drv.h | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index e13a8cbd61c9..ad4fad2bcdc8 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -65,6 +65,12 @@ enum msm_dp_controller {
>   MSM_DP_CONTROLLER_COUNT,
>  };
>  
> +enum msm_dsi_controller {
> + MSM_DSI_CONTROLLER_0,
> + MSM_DSI_CONTROLLER_1,
> + MSM_DSI_CONTROLLER_COUNT,
> +};
> +
>  #define MSM_GPU_MAX_RINGS 4
>  #define MAX_H_TILES_PER_DISPLAY 2
>  
> @@ -117,7 +123,7 @@ struct msm_drm_private {
>   struct hdmi *hdmi;
>  
>   /* DSI is shared by mdp4 and mdp5 */
> - struct msm_dsi *dsi[2];
> + struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT];
>  
>   struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT];
>  
> -- 
> 2.39.2
>

Re: [Freedreno] [PATCH v2 03/22] drm/msm/dpu: remove unused INTF_NONE interfaces

2023-06-15 Thread Marijn Suijten

On 2023-06-13 03:09:42, Dmitry Baryshkov wrote:
> sm6115 and qcm2290 do not have INTF_0. Drop corresponding interface
> definitions.

As Abhinav said, add sm6375.

If it wasn't for sc8280xp using INTF_NONE for fake MST, we could have
dropped INTF_NONE and the special-cases in dpu_hw_interrupts.c and
dpu_hw_intf.c entirely!  Is that your plan?

> 
> Signed-off-by: Dmitry Baryshkov 

Reviewed-by: Marijn Suijten 

> ---
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h  | 1 -
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
>  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h  | 1 -
>  3 files changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index ba9de008519b..031fc8dae3c6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -66,7 +66,6 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = {
>  };
>  
>  static const struct dpu_intf_cfg sm6115_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x0, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
>   INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, 
> INTF_SC7180_MASK,
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 92ac348eea6b..f2808098af39 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -63,7 +63,6 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = {
>  };
>  
>  static const struct dpu_intf_cfg qcm2290_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x0, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
>   INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, 
> INTF_SC7180_MASK,
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index d7aae45e3e66..241fa6746674 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -71,7 +71,6 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = {
>  };
>  
>  static const struct dpu_intf_cfg sm6375_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x0, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
>   INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, 
> INTF_SC7180_MASK,
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> -- 
> 2.39.2
>

Re: [Freedreno] [PATCH v2 02/22] drm/msm/dpu: correct MERGE_3D length

2023-06-15 Thread Marijn Suijten

On 2023-06-13 03:09:41, Dmitry Baryshkov wrote:
> Each MERGE_3D block has just two registers. Correct the block length
> accordingly.
> 
> Fixes: 4369c93cf36b ("drm/msm/dpu: initial support for merge3D hardware 
> block")
> Signed-off-by: Dmitry Baryshkov 

Indeed, and that patch wasn't even introducing the register writes -
this only happened in commit 9ffd0e8569937 ("drm/msm/dpu: setup merge
modes in merge_3d block").

Reviewed-by: Marijn Suijten 

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 36ba3f58dcdf..0de507d4d7b7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -508,7 +508,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk 
> = {
>  #define MERGE_3D_BLK(_name, _id, _base) \
>   {\
>   .name = _name, .id = _id, \
> - .base = _base, .len = 0x100, \
> + .base = _base, .len = 0x8, \
>   .features = MERGE_3D_SM8150_MASK, \
>   .sblk = NULL \
>   }
> -- 
> 2.39.2
>

Re: [Freedreno] [PATCH v2 01/22] drm/msm/dpu: fix sc7280 and sc7180 PINGPONG done interrupts

2023-06-15 Thread Marijn Suijten

On 2023-06-13 03:09:40, Dmitry Baryshkov wrote:
> During IRQ conversion we have lost the PP_DONE interrupts for sc7280
> platform. This was left unnoticed, because this interrupt is only used
> for CMD outputs and probably no sc7[12]80 systems use DSI CMD panels.
> 
> Fixes: 667e9985ee24 ("drm/msm/dpu: replace IRQ lookup with the data in hw 
> catalog")
> Signed-off-by: Dmitry Baryshkov 

Agreed.  I never really understood why these were missing, as if there
was no cmd-mode support.  The code prior to the Fixes: commit was indeed
returning interrupts without looking at hardware support at all.

Reviewed-by: Marijn Suijten 

> ---
>  .../drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h   |  8 ++--
>  .../drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h   | 16 
>  2 files changed, 18 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 0b05da2592c0..67566b07195a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -80,8 +80,12 @@ static const struct dpu_dspp_cfg sc7180_dspp[] = {
>  };
>  
>  static const struct dpu_pingpong_cfg sc7180_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x7, PINGPONG_SM8150_MASK, 0, 
> sdm845_pp_sblk, -1, -1),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, 
> sdm845_pp_sblk, -1, -1),
> + PP_BLK("pingpong_0", PINGPONG_0, 0x7, PINGPONG_SM8150_MASK, 0, 
> sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, 
> sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + -1),
>  };
>  
>  static const struct dpu_intf_cfg sc7180_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 9c5a3fe9cfde..6ea1cb551348 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -88,10 +88,18 @@ static const struct dpu_dspp_cfg sc7280_dspp[] = {
>  };
>  
>  static const struct dpu_pingpong_cfg sc7280_pp[] = {
> - PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, 
> -1),
> - PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, 
> -1),
> - PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, 
> -1),
> - PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, 
> -1),
> + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + -1),
> + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + -1),
> + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + -1),
> + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + -1),
>  };
>  
>  static const struct dpu_wb_cfg sc7280_wb[] = {
> -- 
> 2.39.2
>

Re: [Freedreno] [PATCH v2 00/22]drm/msm/dpu: another catalog rework

2023-06-15 Thread Marijn Suijten

On 2023-06-13 03:09:39, Dmitry Baryshkov wrote:
> Having a macro with 10 arguments doesn't seem like a good idea. It makes
> it inherently harder to compare the actual structure values. Also this
> leads to adding macros covering varieties of the block.
> 
> As it was previously discussed, inline all foo_BLK macros in order to
> ease performing changes to the catalog data.
> 
> Major part of the conversion was performed using vim script found at
> [1]. Then some manual cleanups were applied, like dropping fields set to
> 0.
> 
> Dependencies: [2].
> 
> Changes since v1:
>  - Rebased on top of msm-next
>  - Dropped dependency on interrupt rework
> 
> [1] https://pastebin.ubuntu.com/p/26cdW5VpYB/
> [2] https://patchwork.freedesktop.org/patch/542142/?series=119220=1
> 
> Dmitry Baryshkov (22):
>   drm/msm/dpu: fix sc7280 and sc7180 PINGPONG done interrupts
>   drm/msm/dpu: correct MERGE_3D length
>   drm/msm/dpu: remove unused INTF_NONE interfaces
>   drm/msm: enumerate DSI interfaces
>   drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n
>   drm/msm/dpu: simplify peer LM handling
>   drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
>   drm/msm/dpu: drop enum dpu_mdp and MDP_TOP value
>   drm/msm/dpu: expand .clk_ctrls definitions
>   drm/msm/dpu: drop zero features from dpu_mdp_cfg data
>   drm/msm/dpu: drop zero features from dpu_ctl_cfg data
>   drm/msm/dpu: correct indentation for CTL definitions
>   drm/msm/dpu: inline SSPP_BLK macros
>   drm/msm/dpu: inline DSPP_BLK macros
>   drm/msm/dpu: inline LM_BLK macros
>   drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros
>   drm/msm/dpu: inline MERGE_3D_BLK macros
>   drm/msm/dpu: inline various PP_BLK_* macros
>   drm/msm/dpu: inline WB_BLK macros
>   drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros
>   drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK
>   drm/msm/dpu: drop empty features mask INTF_SDM845_MASK

I am not sure how to process this series, seems like something went
wrong during sending.  Besides patch 16 being duplicate albeit with
different content, patch 20, 21 and 22 are duplicate as well and have an
interesting pattern where 21 and 22 are sent in reply to 20?

6587 N T 2023-06-13 02:09:54 Dmitry Baryshko (   0) ├─>[PATCH v2 15/22] 
drm/msm/dpu: inline LM_BLK macros
6588 N T 2023-06-13 02:09:55 Dmitry Baryshko (   0) ├─>[PATCH v2 16/22] 
drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros
6589 N T 2023-06-13 02:09:57 Dmitry Baryshko (   0) ├─>[PATCH v2 17/22] 
drm/msm/dpu: inline MERGE_3D_BLK macros
6590 N T 2023-06-13 02:12:37 Dmitry Baryshko (   0) ├─>[PATCH v2 20/22] 
drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros
6591 N T 2023-06-13 02:12:38 Dmitry Baryshko (   0) │ ├─>[PATCH v2 21/22] 
drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK
6592 N T 2023-06-13 02:12:39 Dmitry Baryshko (   0) │ └─>[PATCH v2 22/22] 
drm/msm/dpu: drop empty features mask INTF_SDM845_MASK

^ Here are 21 and 22 in reply to 20 ^

6593 N T 2023-06-13 02:14:49 Dmitry Baryshko (   0) ├─>[PATCH v2 18/22] 
drm/msm/dpu: inline various PP_BLK_* macros
6594 N T 2023-06-13 02:14:50 Dmitry Baryshko (   0) ├─>[PATCH v2 19/22] 
drm/msm/dpu: inline WB_BLK macros
6595 N T 2023-06-13 02:14:51 Dmitry Baryshko (   0) ├─>[PATCH v2 20/22] 
drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros
6596 N T 2023-06-13 02:14:52 Dmitry Baryshko (   0) ├─>[PATCH v2 21/22] 
drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK
6597 N T 2023-06-13 02:14:53 Dmitry Baryshko (   0) ├─>[PATCH v2 22/22] 
drm/msm/dpu: drop empty features mask INTF_SDM845_MASK

And here they are again.

See the same on Lore: 
https://lore.kernel.org/linux-arm-msm/20230613001004.3426676-1-dmitry.barysh...@linaro.org/

- Marijn

> 
>  .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h   | 329 
>  .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 348 +
>  .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 411 ++-
>  .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h   | 448 +++-
>  .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 430 +++-
>  .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h| 180 +--
>  .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h|  89 +++-
>  .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h| 188 ---
>  .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h   |  89 +++-
>  .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h|  96 ++--
>  .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h| 418 ++-
>  .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h| 236 ++---
>  .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  | 484 +-
>  .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h| 445 +++-
>  .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h| 467 -
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 130 -
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   5 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h   |   5 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c|  34 +-
>

Re: [Freedreno] [PATCH v2 16/21] drm/msm/dpu: inline DSC_BLK macros

2023-06-15 Thread Dmitry Baryshkov


On 16/06/2023 01:05, Marijn Suijten wrote:

On 2023-06-13 03:09:56, Dmitry Baryshkov wrote:

To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.

Signed-off-by: Dmitry Baryshkov 
---
  .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h   | 11 +--
  .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 17 +++---
  .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 21 ++---
  .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h   | 31 +++
  .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 21 ++---
  .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h|  6 +++-
  .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h|  6 +++-
  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 10 --
  8 files changed, 91 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index a07c68744b29..7c3da4033c46 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -200,8 +200,15 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = {
  };
  
  static const struct dpu_dsc_cfg msm8998_dsc[] = {

-   DSC_BLK("dsc_0", DSC_0, 0x8, 0),
-   DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
+   {
+   .name = "dsc_0", .id = DSC_0,
+   .base = 0x8, .len = 0x1800,
+   .features = 0,
+   }, {
+   .name = "dsc_1", .id = DSC_1,
+   .base = 0x80400, .len = 0x1800,
+   .features = 0,
+   },
  };
  
  static const struct dpu_dspp_cfg msm8998_dspp[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 786263ed1ef2..ca3bb6a1a93a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -224,10 +224,19 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = {
  };
  
  static const struct dpu_dsc_cfg sdm845_dsc[] = {

-   DSC_BLK("dsc_0", DSC_0, 0x8, 0),
-   DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
-   DSC_BLK("dsc_2", DSC_2, 0x80800, 0),
-   DSC_BLK("dsc_3", DSC_3, 0x80c00, 0),
+   {
+   .name = "dsc_0", .id = DSC_0,
+   .base = 0x8, .len = 0x1800,
+   }, {
+   .name = "dsc_1", .id = DSC_1,
+   .base = 0x80400, .len = 0x1800,
+   }, {
+   .name = "dsc_2", .id = DSC_2,
+   .base = 0x80800, .len = 0x1800,
+   }, {
+   .name = "dsc_3", .id = DSC_3,
+   .base = 0x80c00, .len = 0x1800,
+   },
  };
  
  static const struct dpu_intf_cfg sdm845_intf[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 6b9bfeac6e0a..5b068521de13 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -245,10 +245,23 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
  };
  
  static const struct dpu_dsc_cfg sm8150_dsc[] = {

-   DSC_BLK("dsc_0", DSC_0, 0x8, BIT(DPU_DSC_OUTPUT_CTRL)),
-   DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
-   DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
-   DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
+   {
+   .name = "dsc_0", .id = DSC_0,
+   .base = 0x8, .len = 0x1800,
+   .features = BIT(DPU_DSC_OUTPUT_CTRL),
+   }, {
+   .name = "dsc_1", .id = DSC_1,
+   .base = 0x80400, .len = 0x1800,
+   .features = BIT(DPU_DSC_OUTPUT_CTRL),
+   }, {
+   .name = "dsc_2", .id = DSC_2,
+   .base = 0x80800, .len = 0x1800,
+   .features = BIT(DPU_DSC_OUTPUT_CTRL),
+   }, {
+   .name = "dsc_3", .id = DSC_3,
+   .base = 0x80c00, .len = 0x1800,
+   .features = BIT(DPU_DSC_OUTPUT_CTRL),
+   },
  };
  
  static const struct dpu_intf_cfg sm8150_intf[] = {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 414f0db3306c..ba5420f334ec 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -244,12 +244,31 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = 
{
  };
  
  static const struct dpu_dsc_cfg sc8180x_dsc[] = {

-   DSC_BLK("dsc_0", DSC_0, 0x8, BIT(DPU_DSC_OUTPUT_CTRL)),
-   DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
-   DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
-   DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
-   DSC_BLK("dsc_4", DSC_4, 0x81000,

Re: [Freedreno] [PATCH v2 16/21] drm/msm/dpu: inline DSC_BLK macros

2023-06-15 Thread Marijn Suijten

On 2023-06-13 03:09:56, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
> 
> Signed-off-by: Dmitry Baryshkov 
> ---
>  .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h   | 11 +--
>  .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 17 +++---
>  .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h| 21 ++---
>  .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h   | 31 +++
>  .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h| 21 ++---
>  .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h|  6 +++-
>  .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h|  6 +++-
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 10 --
>  8 files changed, 91 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index a07c68744b29..7c3da4033c46 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -200,8 +200,15 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = {
>  };
>  
>  static const struct dpu_dsc_cfg msm8998_dsc[] = {
> - DSC_BLK("dsc_0", DSC_0, 0x8, 0),
> - DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
> + {
> + .name = "dsc_0", .id = DSC_0,
> + .base = 0x8, .len = 0x1800,
> + .features = 0,
> + }, {
> + .name = "dsc_1", .id = DSC_1,
> + .base = 0x80400, .len = 0x1800,
> + .features = 0,
> + },
>  };
>  
>  static const struct dpu_dspp_cfg msm8998_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 786263ed1ef2..ca3bb6a1a93a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -224,10 +224,19 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = {
>  };
>  
>  static const struct dpu_dsc_cfg sdm845_dsc[] = {
> - DSC_BLK("dsc_0", DSC_0, 0x8, 0),
> - DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
> - DSC_BLK("dsc_2", DSC_2, 0x80800, 0),
> - DSC_BLK("dsc_3", DSC_3, 0x80c00, 0),
> + {
> + .name = "dsc_0", .id = DSC_0,
> + .base = 0x8, .len = 0x1800,
> + }, {
> + .name = "dsc_1", .id = DSC_1,
> + .base = 0x80400, .len = 0x1800,
> + }, {
> + .name = "dsc_2", .id = DSC_2,
> + .base = 0x80800, .len = 0x1800,
> + }, {
> + .name = "dsc_3", .id = DSC_3,
> + .base = 0x80c00, .len = 0x1800,
> + },
>  };
>  
>  static const struct dpu_intf_cfg sdm845_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 6b9bfeac6e0a..5b068521de13 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -245,10 +245,23 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] 
> = {
>  };
>  
>  static const struct dpu_dsc_cfg sm8150_dsc[] = {
> - DSC_BLK("dsc_0", DSC_0, 0x8, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
> + {
> + .name = "dsc_0", .id = DSC_0,
> + .base = 0x8, .len = 0x1800,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_1", .id = DSC_1,
> + .base = 0x80400, .len = 0x1800,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_2", .id = DSC_2,
> + .base = 0x80800, .len = 0x1800,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_3", .id = DSC_3,
> + .base = 0x80c00, .len = 0x1800,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + },
>  };
>  
>  static const struct dpu_intf_cfg sm8150_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 414f0db3306c..ba5420f334ec 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -244,12 +244,31 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] 
> = {
>  };
>  
>  static const struct dpu_dsc_cfg sc8180x_dsc[] = {
> - DSC_BLK("dsc_0", DSC_0, 0x8, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_3", DSC_3, 0x80c00,

Re: [Freedreno] [PATCH v8 10/18] drm/msm/a6xx: Introduce GMU wrapper support

2023-06-15 Thread Konrad Dybcio

On 10.06.2023 00:06, Akhil P Oommen wrote:
> On Mon, May 29, 2023 at 03:52:29PM +0200, Konrad Dybcio wrote:
>>
>> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
>> but don't implement the associated GMUs. This is due to the fact that
>> the GMU directly pokes at RPMh. Sadly, this means we have to take care
>> of enabling & scaling power rails, clocks and bandwidth ourselves.
>>
>> Reuse existing Adreno-common code and modify the deeply-GMU-infused
>> A6XX code to facilitate these GPUs. This involves if-ing out lots
>> of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's
>> the actual name that Qualcomm uses in their downstream kernels).
>>
>> This is essentially a register region which is convenient to model
>> as a device. We'll use it for managing the GDSCs. The register
>> layout matches the actual GMU_CX/GX regions on the "real GMU" devices
>> and lets us reuse quite a bit of gmu_read/write/rmw calls.
>>
>> Signed-off-by: Konrad Dybcio 
>> ---
>>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c   |  72 +-
>>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 211 
>> 
>>  drivers/gpu/drm/msm/adreno/a6xx_gpu.h   |   1 +
>>  drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c |  14 +-
>>  drivers/gpu/drm/msm/adreno/adreno_gpu.c |   8 +-
>>  drivers/gpu/drm/msm/adreno/adreno_gpu.h |   6 +
>>  6 files changed, 277 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
>> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> index 5ba8cba69383..385ca3a12462 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> @@ -1437,6 +1437,7 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, 
>> struct platform_device *pdev,
>>  
>>  void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
>>  {
>> +struct adreno_gpu *adreno_gpu = _gpu->base;
>>  struct a6xx_gmu *gmu = _gpu->gmu;
>>  struct platform_device *pdev = to_platform_device(gmu->dev);
>>  
>> @@ -1462,10 +1463,12 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
>>  gmu->mmio = NULL;
>>  gmu->rscc = NULL;
>>  
>> -a6xx_gmu_memory_free(gmu);
>> +if (!adreno_has_gmu_wrapper(adreno_gpu)) {
>> +a6xx_gmu_memory_free(gmu);
>>  
>> -free_irq(gmu->gmu_irq, gmu);
>> -free_irq(gmu->hfi_irq, gmu);
>> +free_irq(gmu->gmu_irq, gmu);
>> +free_irq(gmu->hfi_irq, gmu);
>> +}
>>  
>>  /* Drop reference taken in of_find_device_by_node */
>>  put_device(gmu->dev);
>> @@ -1484,6 +1487,69 @@ static int cxpd_notifier_cb(struct notifier_block *nb,
>>  return 0;
>>  }
>>  
>> +int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node 
>> *node)
>> +{
>> +struct platform_device *pdev = of_find_device_by_node(node);
>> +struct a6xx_gmu *gmu = _gpu->gmu;
>> +int ret;
>> +
>> +if (!pdev)
>> +return -ENODEV;
>> +
>> +gmu->dev = >dev;
>> +
>> +of_dma_configure(gmu->dev, node, true);
>> +
>> +pm_runtime_enable(gmu->dev);
>> +
>> +/* Mark legacy for manual SPTPRAC control */
>> +gmu->legacy = true;
>> +
>> +/* Map the GMU registers */
>> +gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
>> +if (IS_ERR(gmu->mmio)) {
>> +ret = PTR_ERR(gmu->mmio);
>> +goto err_mmio;
>> +}
>> +
>> +gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
>> +if (IS_ERR(gmu->cxpd)) {
>> +ret = PTR_ERR(gmu->cxpd);
>> +goto err_mmio;
>> +}
>> +
>> +if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) {
>> +ret = -ENODEV;
>> +goto detach_cxpd;
>> +}
>> +
>> +init_completion(>pd_gate);
>> +complete_all(>pd_gate);
>> +gmu->pd_nb.notifier_call = cxpd_notifier_cb;
>> +
>> +/* Get a link to the GX power domain to reset the GPU */
>> +gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
>> +if (IS_ERR(gmu->gxpd)) {
>> +ret = PTR_ERR(gmu->gxpd);
>> +goto err_mmio;
>> +}
>> +
>> +gmu->initialized = true;
>> +
>> +return 0;
>> +
>> +detach_cxpd:
>> +dev_pm_domain_detach(gmu->cxpd, false);
>> +
>> +err_mmio:
>> +iounmap(gmu->mmio);
>> +
>> +/* Drop reference taken in of_find_device_by_node */
>> +put_device(gmu->dev);
>> +
>> +return ret;
>> +}
>> +
>>  int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
>>  {
>>  struct adreno_gpu *adreno_gpu = _gpu->base;
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
>> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index 58bf405b85d8..0a44762dbb6d 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -21,7 +21,7 @@ static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
>>  struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>>  
>>  /* Check that the GMU is idle */
>> -if (!a6xx_gmu_isidle(_gpu->gmu))
>> +if

Re: [Freedreno] [PATCH v8 07/18] drm/msm/a6xx: Add a helper for software-resetting the GPU

2023-06-15 Thread Akhil P Oommen

On Thu, Jun 15, 2023 at 10:59:23PM +0200, Konrad Dybcio wrote:
> 
> On 15.06.2023 22:11, Akhil P Oommen wrote:
> > On Thu, Jun 15, 2023 at 12:34:06PM +0200, Konrad Dybcio wrote:
> >>
> >> On 6.06.2023 19:18, Akhil P Oommen wrote:
> >>> On Mon, May 29, 2023 at 03:52:26PM +0200, Konrad Dybcio wrote:
> 
>  Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper
>  GPUs and reuse it in a6xx_gmu_force_off().
> 
>  This helper, contrary to the original usage in GMU code paths, adds
>  a write memory barrier which together with the necessary delay should
>  ensure that the reset is never deasserted too quickly due to e.g. OoO
>  execution going crazy.
> 
>  Signed-off-by: Konrad Dybcio 
>  ---
>   drivers/gpu/drm/msm/adreno/a6xx_gmu.c |  3 +--
>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++
>   drivers/gpu/drm/msm/adreno/a6xx_gpu.h |  1 +
>   3 files changed, 13 insertions(+), 2 deletions(-)
> 
>  diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
>  b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>  index b86be123ecd0..5ba8cba69383 100644
>  --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>  +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>  @@ -899,8 +899,7 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
>   a6xx_bus_clear_pending_transactions(adreno_gpu, true);
>   
>   /* Reset GPU core blocks */
>  -gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1);
>  -udelay(100);
>  +a6xx_gpu_sw_reset(gpu, true);
>   }
>   
>   static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct 
>  a6xx_gmu *gmu)
>  diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
>  b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>  index e3ac3f045665..083ccb5bcb4e 100644
>  --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>  +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>  @@ -1634,6 +1634,17 @@ void a6xx_bus_clear_pending_transactions(struct 
>  adreno_gpu *adreno_gpu, bool gx_
>   gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
>   }
>   
>  +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert)
>  +{
>  +gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert);
>  +/* Add a barrier to avoid bad surprises */
> >>> Can you please make this comment a bit more clear? Highlight that we
> >>> should ensure the register is posted at hw before polling.
> >>>
> >>> I think this barrier is required only during assert.
> >> Generally it should not be strictly required at all, but I'm thinking
> >> that it'd be good to keep it in both cases, so that:
> >>
> >> if (assert)
> >>we don't keep writing things to the GPU if it's in reset
> >> else
> >>we don't start writing things to the GPU becomes it comes
> >>out of reset
> >>
> >> Also, if you squint hard enough at the commit message, you'll notice
> >> I intended for this so only be a wmb, but for some reason generalized
> >> it.. Perhaps that's another thing I should fix!
> >> for v9..
> > 
> > wmb() doesn't provide any ordering guarantee with the delay loop.
> Hm, fair.. I'm still not as fluent with memory access knowledge as I'd
> like to be..
> 
> > A common practice is to just read back the same register before
> > the loop because a readl followed by delay() is guaranteed to be ordered.
> So, how should I proceed? Keep the r/w barrier, or add a readback and
> a tiiiny (perhaps even using ndelay instead of udelay?) delay on de-assert?

readback + delay (similar value as downstream). This path is exercised
rarely.

-Akhil.

> 
> Konrad
> > 
> > -Akhil.
> >>
> >> Konrad
> >>>
> >>> -Akhil.
>  +mb();
>  +
>  +/* The reset line needs to be asserted for at least 100 us */
>  +if (assert)
>  +udelay(100);
>  +}
>  +
>   static int a6xx_pm_resume(struct msm_gpu *gpu)
>   {
>   struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>  diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h 
>  b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>  index 9580def06d45..aa70390ee1c6 100644
>  --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>  +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>  @@ -89,5 +89,6 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct 
>  msm_gpu *gpu);
>   int a6xx_gpu_state_put(struct msm_gpu_state *state);
>   
>   void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, 
>  bool gx_off);
>  +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert);
>   
>   #endif /* __A6XX_GPU_H__ */
> 
>  -- 
>  2.40.1
>

Re: [Freedreno] [PATCH v8 07/18] drm/msm/a6xx: Add a helper for software-resetting the GPU

2023-06-15 Thread Konrad Dybcio

On 15.06.2023 22:11, Akhil P Oommen wrote:
> On Thu, Jun 15, 2023 at 12:34:06PM +0200, Konrad Dybcio wrote:
>>
>> On 6.06.2023 19:18, Akhil P Oommen wrote:
>>> On Mon, May 29, 2023 at 03:52:26PM +0200, Konrad Dybcio wrote:

 Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper
 GPUs and reuse it in a6xx_gmu_force_off().

 This helper, contrary to the original usage in GMU code paths, adds
 a write memory barrier which together with the necessary delay should
 ensure that the reset is never deasserted too quickly due to e.g. OoO
 execution going crazy.

 Signed-off-by: Konrad Dybcio 
 ---
  drivers/gpu/drm/msm/adreno/a6xx_gmu.c |  3 +--
  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++
  drivers/gpu/drm/msm/adreno/a6xx_gpu.h |  1 +
  3 files changed, 13 insertions(+), 2 deletions(-)

 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
 b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
 index b86be123ecd0..5ba8cba69383 100644
 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
 +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
 @@ -899,8 +899,7 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
a6xx_bus_clear_pending_transactions(adreno_gpu, true);
  
/* Reset GPU core blocks */
 -  gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1);
 -  udelay(100);
 +  a6xx_gpu_sw_reset(gpu, true);
  }
  
  static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct 
 a6xx_gmu *gmu)
 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
 b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
 index e3ac3f045665..083ccb5bcb4e 100644
 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
 +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
 @@ -1634,6 +1634,17 @@ void a6xx_bus_clear_pending_transactions(struct 
 adreno_gpu *adreno_gpu, bool gx_
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
  }
  
 +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert)
 +{
 +  gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert);
 +  /* Add a barrier to avoid bad surprises */
>>> Can you please make this comment a bit more clear? Highlight that we
>>> should ensure the register is posted at hw before polling.
>>>
>>> I think this barrier is required only during assert.
>> Generally it should not be strictly required at all, but I'm thinking
>> that it'd be good to keep it in both cases, so that:
>>
>> if (assert)
>>  we don't keep writing things to the GPU if it's in reset
>> else
>>  we don't start writing things to the GPU becomes it comes
>>  out of reset
>>
>> Also, if you squint hard enough at the commit message, you'll notice
>> I intended for this so only be a wmb, but for some reason generalized
>> it.. Perhaps that's another thing I should fix!
>> for v9..
> 
> wmb() doesn't provide any ordering guarantee with the delay loop.
Hm, fair.. I'm still not as fluent with memory access knowledge as I'd
like to be..

> A common practice is to just read back the same register before
> the loop because a readl followed by delay() is guaranteed to be ordered.
So, how should I proceed? Keep the r/w barrier, or add a readback and
a tiiiny (perhaps even using ndelay instead of udelay?) delay on de-assert?

Konrad
> 
> -Akhil.
>>
>> Konrad
>>>
>>> -Akhil.
 +  mb();
 +
 +  /* The reset line needs to be asserted for at least 100 us */
 +  if (assert)
 +  udelay(100);
 +}
 +
  static int a6xx_pm_resume(struct msm_gpu *gpu)
  {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h 
 b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
 index 9580def06d45..aa70390ee1c6 100644
 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
 +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
 @@ -89,5 +89,6 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu 
 *gpu);
  int a6xx_gpu_state_put(struct msm_gpu_state *state);
  
  void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, 
 bool gx_off);
 +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert);
  
  #endif /* __A6XX_GPU_H__ */

 -- 
 2.40.1

Re: [Freedreno] [PATCH v8 07/18] drm/msm/a6xx: Add a helper for software-resetting the GPU

2023-06-15 Thread Akhil P Oommen

On Thu, Jun 15, 2023 at 12:34:06PM +0200, Konrad Dybcio wrote:
> 
> On 6.06.2023 19:18, Akhil P Oommen wrote:
> > On Mon, May 29, 2023 at 03:52:26PM +0200, Konrad Dybcio wrote:
> >>
> >> Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper
> >> GPUs and reuse it in a6xx_gmu_force_off().
> >>
> >> This helper, contrary to the original usage in GMU code paths, adds
> >> a write memory barrier which together with the necessary delay should
> >> ensure that the reset is never deasserted too quickly due to e.g. OoO
> >> execution going crazy.
> >>
> >> Signed-off-by: Konrad Dybcio 
> >> ---
> >>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c |  3 +--
> >>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++
> >>  drivers/gpu/drm/msm/adreno/a6xx_gpu.h |  1 +
> >>  3 files changed, 13 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
> >> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >> index b86be123ecd0..5ba8cba69383 100644
> >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >> @@ -899,8 +899,7 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
> >>a6xx_bus_clear_pending_transactions(adreno_gpu, true);
> >>  
> >>/* Reset GPU core blocks */
> >> -  gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1);
> >> -  udelay(100);
> >> +  a6xx_gpu_sw_reset(gpu, true);
> >>  }
> >>  
> >>  static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct 
> >> a6xx_gmu *gmu)
> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
> >> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> index e3ac3f045665..083ccb5bcb4e 100644
> >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> @@ -1634,6 +1634,17 @@ void a6xx_bus_clear_pending_transactions(struct 
> >> adreno_gpu *adreno_gpu, bool gx_
> >>gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
> >>  }
> >>  
> >> +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert)
> >> +{
> >> +  gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert);
> >> +  /* Add a barrier to avoid bad surprises */
> > Can you please make this comment a bit more clear? Highlight that we
> > should ensure the register is posted at hw before polling.
> > 
> > I think this barrier is required only during assert.
> Generally it should not be strictly required at all, but I'm thinking
> that it'd be good to keep it in both cases, so that:
> 
> if (assert)
>   we don't keep writing things to the GPU if it's in reset
> else
>   we don't start writing things to the GPU becomes it comes
>   out of reset
> 
> Also, if you squint hard enough at the commit message, you'll notice
> I intended for this so only be a wmb, but for some reason generalized
> it.. Perhaps that's another thing I should fix!
> for v9..

wmb() doesn't provide any ordering guarantee with the delay loop.
A common practice is to just read back the same register before
the loop because a readl followed by delay() is guaranteed to be ordered.

-Akhil.
> 
> Konrad
> > 
> > -Akhil.
> >> +  mb();
> >> +
> >> +  /* The reset line needs to be asserted for at least 100 us */
> >> +  if (assert)
> >> +  udelay(100);
> >> +}
> >> +
> >>  static int a6xx_pm_resume(struct msm_gpu *gpu)
> >>  {
> >>struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h 
> >> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> >> index 9580def06d45..aa70390ee1c6 100644
> >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> >> @@ -89,5 +89,6 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu 
> >> *gpu);
> >>  int a6xx_gpu_state_put(struct msm_gpu_state *state);
> >>  
> >>  void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, 
> >> bool gx_off);
> >> +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert);
> >>  
> >>  #endif /* __A6XX_GPU_H__ */
> >>
> >> -- 
> >> 2.40.1
> >>

Re: [Freedreno] [PATCH v6 0/6] Add DSC v1.2 Support for DSI

2023-06-15 Thread Marijn Suijten

On 2023-06-15 14:31:26, Dmitry Baryshkov wrote:
> 
> On Fri, 09 Jun 2023 15:57:12 -0700, Jessica Zhang wrote:
> > This is a series of changes for DSI to enable command mode support
> > for DSC v1.2.
> > 
> > This includes:
> > 
> > 1) Rounding up `hdisplay / 3` in dsc_timing_setup()
> > 2) Adjusting pclk_rate to account for compression
> > 3) Fixing incorrect uses of slice_count in DSI DSC calculations
> > 4) Setting the DATA_COMPRESS bit when DSC is enabled
> > 
> > [...]
> 
> Applied, thanks!
> 
> [1/6] msm/drm/dsi: Round up DSC hdisplay calculation
>   https://gitlab.freedesktop.org/lumag/msm/-/commit/21bf617110ba
> [2/6] drm/msm/dsi: Reduce pclk rate for compression
>   https://gitlab.freedesktop.org/lumag/msm/-/commit/7c9e4a554d4a
> [3/6] drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature flag for DPU >= 7.0
>   https://gitlab.freedesktop.org/lumag/msm/-/commit/22598cfc94bb
> [4/6] drm/msm/dpu: Set DATA_COMPRESS on command mode for DCE/DSC 1.2
>   https://gitlab.freedesktop.org/lumag/msm/-/commit/1642b5803473
> [5/6] drm/msm/dsi: Remove incorrect references to slice_count
>   https://gitlab.freedesktop.org/lumag/msm/-/commit/155fa3a91d64
> 
> Note, patch 6 is skipped for now

Note that we also haven't finished discussions on where the ratio in
patch 2/6 comes from and how that should be outlined in patch 6.
Related to the widebus patches which affect the ratio as well.

- Marijn

Re: [Freedreno] [PATCH v14 00/10] add DSC 1.2 dpu supports

2023-06-15 Thread Dmitry Baryshkov



On Thu, 25 May 2023 10:40:48 -0700, Kuogee Hsieh wrote:
> This series adds the DPU side changes to support DSC 1.2 encoder. This
> was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
> The DSI and DP parts will be pushed later on top of this change.
> This seriel is rebase on [1], [2] and catalog fixes from rev-4 of [3].
> 
> [1]: https://patchwork.freedesktop.org/series/116851/
> [2]: https://patchwork.freedesktop.org/series/116615/
> [3]: https://patchwork.freedesktop.org/series/112332/
> 
> [...]

Applied, thanks!

[06/10] drm/msm/dpu: add support for DSC encoder v1.2 engine
https://gitlab.freedesktop.org/lumag/msm/-/commit/8c4094b275f6
[09/10] drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets
https://gitlab.freedesktop.org/lumag/msm/-/commit/0d1b10c63346

Best regards,
-- 
Dmitry Baryshkov

Re: [Freedreno] [PATCH v14 0/9] Introduce MSM-specific DSC helpers

2023-06-15 Thread Dmitry Baryshkov



On Wed, 24 May 2023 10:45:13 -0700, Jessica Zhang wrote:
> There are some overlap in calculations for MSM-specific DSC variables
> between DP and DSI. In addition, the calculations for initial_scale_value
> and det_thresh_flatness that are defined within the DSC 1.2 specifications,
> but aren't yet included in drm_dsc_helper.c.
> 
> This series moves these calculations to a shared msm_dsc_helper.c file and
> defines drm_dsc_helper methods for initial_scale_value and
> det_thresh_flatness.
> 
> [...]

Applied, thanks!

[1/9] drm/display/dsc: Add flatness and initial scale value calculations
  https://gitlab.freedesktop.org/lumag/msm/-/commit/7df1ed6ddf3d
[2/9] drm/display/dsc: add helper to set semi-const parameters
  https://gitlab.freedesktop.org/lumag/msm/-/commit/e871a70d8ccd
[3/9] drm/display/dsc: Add drm_dsc_get_bpp_int helper
  https://gitlab.freedesktop.org/lumag/msm/-/commit/688583281241
[4/9] drm/msm/dsi: use DRM DSC helpers for DSC setup
  https://gitlab.freedesktop.org/lumag/msm/-/commit/49fd30a7153b
[5/9] drm/msm: Add MSM-specific DSC helper methods
  https://gitlab.freedesktop.org/lumag/msm/-/commit/b50f06f83e0e
[6/9] drm/msm/dpu: Use fixed DRM DSC helper for det_thresh_flatness
  https://gitlab.freedesktop.org/lumag/msm/-/commit/44346191a210
[7/9] drm/msm/dpu: Fix slice_last_group_size calculation
  https://gitlab.freedesktop.org/lumag/msm/-/commit/c223059e6f83
[8/9] drm/msm/dsi: Use MSM and DRM DSC helper methods
  https://gitlab.freedesktop.org/lumag/msm/-/commit/ed1498f77419
[9/9] drm/msm/dsi: update hdisplay calculation for dsi_timing_setup
  https://gitlab.freedesktop.org/lumag/msm/-/commit/149419396a92

Best regards,
-- 
Dmitry Baryshkov

Re: [Freedreno] [PATCH] drm/msm/dp: Free resources after unregistering them

2023-06-15 Thread Dmitry Baryshkov



On Mon, 12 Jun 2023 15:02:59 -0700, Bjorn Andersson wrote:
> The DP component's unbind operation walks through the submodules to
> unregister and clean things up. But if the unbind happens because the DP
> controller itself is being removed, all the memory for those submodules
> has just been freed.
> 
> Change the order of these operations to avoid the many use-after-free
> that otherwise happens in this code path.
> 
> [...]

Applied, thanks!

[1/1] drm/msm/dp: Free resources after unregistering them
  https://gitlab.freedesktop.org/lumag/msm/-/commit/fa0048a4b1fa

Best regards,
-- 
Dmitry Baryshkov

Re: [Freedreno] [PATCH] drm/msm/dp: Drop aux devices together with DP controller

2023-06-15 Thread Dmitry Baryshkov



On Mon, 12 Jun 2023 15:01:06 -0700, Bjorn Andersson wrote:
> Using devres to depopulate the aux bus made sure that upon a probe
> deferral the EDP panel device would be destroyed and recreated upon next
> attempt.
> 
> But the struct device which the devres is tied to is the DPUs
> (drm_dev->dev), which may be happen after the DP controller is torn
> down.
> 
> [...]

Applied, thanks!

[1/1] drm/msm/dp: Drop aux devices together with DP controller
  https://gitlab.freedesktop.org/lumag/msm/-/commit/a7bfb2ad2184

Best regards,
-- 
Dmitry Baryshkov

Re: [Freedreno] [PATCH v6 0/6] Add DSC v1.2 Support for DSI

2023-06-15 Thread Dmitry Baryshkov



On Fri, 09 Jun 2023 15:57:12 -0700, Jessica Zhang wrote:
> This is a series of changes for DSI to enable command mode support
> for DSC v1.2.
> 
> This includes:
> 
> 1) Rounding up `hdisplay / 3` in dsc_timing_setup()
> 2) Adjusting pclk_rate to account for compression
> 3) Fixing incorrect uses of slice_count in DSI DSC calculations
> 4) Setting the DATA_COMPRESS bit when DSC is enabled
> 
> [...]

Applied, thanks!

[1/6] msm/drm/dsi: Round up DSC hdisplay calculation
  https://gitlab.freedesktop.org/lumag/msm/-/commit/21bf617110ba
[2/6] drm/msm/dsi: Reduce pclk rate for compression
  https://gitlab.freedesktop.org/lumag/msm/-/commit/7c9e4a554d4a
[3/6] drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature flag for DPU >= 7.0
  https://gitlab.freedesktop.org/lumag/msm/-/commit/22598cfc94bb
[4/6] drm/msm/dpu: Set DATA_COMPRESS on command mode for DCE/DSC 1.2
  https://gitlab.freedesktop.org/lumag/msm/-/commit/1642b5803473
[5/6] drm/msm/dsi: Remove incorrect references to slice_count
  https://gitlab.freedesktop.org/lumag/msm/-/commit/155fa3a91d64

Note, patch 6 is skipped for now

Best regards,
-- 
Dmitry Baryshkov

Re: [Freedreno] [PATCH 1/2] drm/msm/dsi: dsi_host: drop unused clocks

2023-06-15 Thread Dmitry Baryshkov



On Thu, 15 Jun 2023 01:44:01 +0300, Dmitry Baryshkov wrote:
> Several source clocks are not used anymore, so stop handling them.
> 
> 

Applied, thanks!

[1/2] drm/msm/dsi: dsi_host: drop unused clocks
  https://gitlab.freedesktop.org/lumag/msm/-/commit/2d1ae9a5ae51
[2/2] drm/msm/dsi: split dsi_ctrl_config() function
  https://gitlab.freedesktop.org/lumag/msm/-/commit/518269541298

Best regards,
-- 
Dmitry Baryshkov

Re: [Freedreno] [PATCH 1/2] drm/msm: provide fb_dirty implemenation

2023-06-15 Thread Dmitry Baryshkov



On Mon, 12 Jun 2023 06:16:15 +0300, Dmitry Baryshkov wrote:
> Since commit 93e81e38e197 ("drm/fb_helper: Minimize damage-helper
> overhead") the drm_fb_helper_funcs::fb_dirty helper is required for
> proper dirty/damage processing. The drm/msm driver requires that to
> function to let CMD panels to work. Use simplified version of
> drm_fbdev_generic_helper_fb_dirty() to fix support for CMD mode panels.
> 
> 
> [...]

Applied, thanks!

[1/2] drm/msm: provide fb_dirty implemenation
  https://gitlab.freedesktop.org/lumag/msm/-/commit/fda520976ef4

Best regards,
-- 
Dmitry Baryshkov

Re: [Freedreno] [PATCH v2 00/22]drm/msm/dpu: another catalog rework

2023-06-15 Thread Dmitry Baryshkov



On Tue, 13 Jun 2023 03:09:39 +0300, Dmitry Baryshkov wrote:
> Having a macro with 10 arguments doesn't seem like a good idea. It makes
> it inherently harder to compare the actual structure values. Also this
> leads to adding macros covering varieties of the block.
> 
> As it was previously discussed, inline all foo_BLK macros in order to
> ease performing changes to the catalog data.
> 
> [...]

Applied, thanks!

[01/22] drm/msm/dpu: fix sc7280 and sc7180 PINGPONG done interrupts
https://gitlab.freedesktop.org/lumag/msm/-/commit/5efc0fec31d8
[02/22] drm/msm/dpu: correct MERGE_3D length
https://gitlab.freedesktop.org/lumag/msm/-/commit/f01fb5e211fd
[03/22] drm/msm/dpu: remove unused INTF_NONE interfaces
https://gitlab.freedesktop.org/lumag/msm/-/commit/17bf6f8efc50

Best regards,
-- 
Dmitry Baryshkov

Re: [Freedreno] [PATCH 1/2] drm/msm/dpu: do not enable color-management if DSPPs are not available

2023-06-15 Thread Dmitry Baryshkov



On Mon, 12 Jun 2023 21:25:33 +0300, Dmitry Baryshkov wrote:
> We can not support color management without DSPP blocks being provided
> in the HW catalog. Do not enable color management for CRTCs if num_dspps
> is 0.
> 
> 

Applied, thanks!

[1/2] drm/msm/dpu: do not enable color-management if DSPPs are not available
  https://gitlab.freedesktop.org/lumag/msm/-/commit/3bcfc7b90465
[2/2] drm/msm/dpu/catalog: define DSPP blocks found on sdm845
  https://gitlab.freedesktop.org/lumag/msm/-/commit/c72375172194

Best regards,
-- 
Dmitry Baryshkov

Re: [Freedreno] [PATCH] drm/msm/adreno: make adreno_is_a690()'s argument const

2023-06-15 Thread Dmitry Baryshkov



On Mon, 12 Jun 2023 21:25:27 +0300, Dmitry Baryshkov wrote:
> Change adreno_is_a690() prototype to accept the const struct adreno_gpu
> pointer instead of a non-const one. This fixes the following warning:
> 
> In file included from drivers/gpu/drm/msm/msm_drv.c:33:
> drivers/gpu/drm/msm/adreno/adreno_gpu.h: In function ‘adreno_is_a660_family’:
> drivers/gpu/drm/msm/adreno/adreno_gpu.h:303:54: warning: passing argument 1 
> of ‘adreno_is_a690’ discards ‘const’ qualifier from pointer target type 
> [-Wdiscarded-qualifiers]
>   303 | return adreno_is_a660(gpu) || adreno_is_a690(gpu) || 
> adreno_is_7c3(gpu);
> 
> [...]

Applied, thanks!

[1/1] drm/msm/adreno: make adreno_is_a690()'s argument const
  https://gitlab.freedesktop.org/lumag/msm/-/commit/b263325b4f34

Best regards,
-- 
Dmitry Baryshkov

Re: [Freedreno] [PATCH v8 07/18] drm/msm/a6xx: Add a helper for software-resetting the GPU

2023-06-15 Thread Konrad Dybcio

On 6.06.2023 19:18, Akhil P Oommen wrote:
> On Mon, May 29, 2023 at 03:52:26PM +0200, Konrad Dybcio wrote:
>>
>> Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper
>> GPUs and reuse it in a6xx_gmu_force_off().
>>
>> This helper, contrary to the original usage in GMU code paths, adds
>> a write memory barrier which together with the necessary delay should
>> ensure that the reset is never deasserted too quickly due to e.g. OoO
>> execution going crazy.
>>
>> Signed-off-by: Konrad Dybcio 
>> ---
>>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c |  3 +--
>>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++
>>  drivers/gpu/drm/msm/adreno/a6xx_gpu.h |  1 +
>>  3 files changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
>> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> index b86be123ecd0..5ba8cba69383 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>> @@ -899,8 +899,7 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
>>  a6xx_bus_clear_pending_transactions(adreno_gpu, true);
>>  
>>  /* Reset GPU core blocks */
>> -gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1);
>> -udelay(100);
>> +a6xx_gpu_sw_reset(gpu, true);
>>  }
>>  
>>  static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu 
>> *gmu)
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
>> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index e3ac3f045665..083ccb5bcb4e 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -1634,6 +1634,17 @@ void a6xx_bus_clear_pending_transactions(struct 
>> adreno_gpu *adreno_gpu, bool gx_
>>  gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
>>  }
>>  
>> +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert)
>> +{
>> +gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert);
>> +/* Add a barrier to avoid bad surprises */
> Can you please make this comment a bit more clear? Highlight that we
> should ensure the register is posted at hw before polling.
> 
> I think this barrier is required only during assert.
Generally it should not be strictly required at all, but I'm thinking
that it'd be good to keep it in both cases, so that:

if (assert)
we don't keep writing things to the GPU if it's in reset
else
we don't start writing things to the GPU becomes it comes
out of reset

Also, if you squint hard enough at the commit message, you'll notice
I intended for this so only be a wmb, but for some reason generalized
it.. Perhaps that's another thing I should fix!
for v9..

Konrad
> 
> -Akhil.
>> +mb();
>> +
>> +/* The reset line needs to be asserted for at least 100 us */
>> +if (assert)
>> +udelay(100);
>> +}
>> +
>>  static int a6xx_pm_resume(struct msm_gpu *gpu)
>>  {
>>  struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h 
>> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> index 9580def06d45..aa70390ee1c6 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> @@ -89,5 +89,6 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu 
>> *gpu);
>>  int a6xx_gpu_state_put(struct msm_gpu_state *state);
>>  
>>  void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, 
>> bool gx_off);
>> +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert);
>>  
>>  #endif /* __A6XX_GPU_H__ */
>>
>> -- 
>> 2.40.1
>>

Re: [Freedreno] [PATCH] drm/msm/dp: Free resources after unregistering them

2023-06-15 Thread Dmitry Baryshkov


On 13/06/2023 01:02, Bjorn Andersson wrote:

The DP component's unbind operation walks through the submodules to
unregister and clean things up. But if the unbind happens because the DP
controller itself is being removed, all the memory for those submodules
has just been freed.

Change the order of these operations to avoid the many use-after-free
that otherwise happens in this code path.

Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support")
Signed-off-by: Bjorn Andersson 
---
  drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
b/drivers/gpu/drm/msm/dp/dp_display.c
index bbb0550a022b..ebc84b8fddf8 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -1337,9 +1337,9 @@ static int dp_display_remove(struct platform_device *pdev)
  {
struct dp_display_private *dp = dev_get_dp_display_private(>dev);
  
+	component_del(>dev, _display_comp_ops);

dp_display_deinit_sub_modules(dp);
  
-	component_del(>dev, _display_comp_ops);

platform_set_drvdata(pdev, NULL);


This matches more or less the order in dp_display_probe().

Reviewed-by: Dmitry Baryshkov 

A note for the possible followup: the driver initializes DP debugfs from 
dpu_kms (ugh) by calling msm_dp_debugfs_init() -> dp_debug_get(). I 
think that dp_debug_put() in dp_display_deinit_sub_modules() does not 
look correct.


  
  	return 0;


--
With best wishes
Dmitry

Re: [Freedreno] [PATCH v8 18/18] drm/msm/a6xx: Add A610 speedbin support

2023-06-15 Thread Konrad Dybcio

On 14.06.2023 22:18, Akhil P Oommen wrote:
> On Mon, May 29, 2023 at 03:52:37PM +0200, Konrad Dybcio wrote:
>>
>> A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
>> (trinket) and SM6225 (khaje). Trinket does not support speed binning
>> (only a single SKU exists) and we don't yet support khaje upstream.
>> Hence, add a fuse mapping table for bengal to allow for per-chip
>> frequency limiting.
>>
>> Reviewed-by: Dmitry Baryshkov 
>> Signed-off-by: Konrad Dybcio 
>> ---
>>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++
>>  1 file changed, 27 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
>> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index d046af5f6de2..c304fa118cff 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -2098,6 +2098,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct 
>> msm_ringbuffer *ring)
>>  return progress;
>>  }
>>  
>> +static u32 a610_get_speed_bin(u32 fuse)
>> +{
>> +/*
>> + * There are (at least) three SoCs implementing A610: SM6125 (trinket),
>> + * SM6115 (bengal) and SM6225 (khaje). Trinket does not have 
>> speedbinning,
>> + * as only a single SKU exists and we don't support khaje upstream yet.
>> + * Hence, this matching table is only valid for bengal and can be easily
>> + * expanded if need be.
>> + */
>> +
>> +if (fuse == 0)
>> +return 0;
>> +else if (fuse == 206)
>> +return 1;
>> +else if (fuse == 200)
>> +return 2;
>> +else if (fuse == 157)
>> +return 3;
>> +else if (fuse == 127)
>> +return 4;
>> +
>> +return UINT_MAX;
>> +}
>> +
>>  static u32 a618_get_speed_bin(u32 fuse)
>>  {
>>  if (fuse == 0)
>> @@ -2195,6 +2219,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct 
>> adreno_gpu *adreno_gpu, u3
>>  {
>>  u32 val = UINT_MAX;
>>  
>> +if (adreno_is_a610(adreno_gpu))
>> +val = a610_get_speed_bin(fuse);
>> +
> 
> Didn't you update here to convert to 'else if' in one of the earlier
> patches??
Right, missed this one!

Konrad
> 
> Reviewed-by: Akhil P Oommen 
> 
> -Akhil.
>>  if (adreno_is_a618(adreno_gpu))
>>  val = a618_get_speed_bin(fuse);
>>  
>>
>> -- 
>> 2.40.1
>>

Re: [Freedreno] [PATCH v8 13/18] drm/msm/a6xx: Add A610 support

2023-06-15 Thread Konrad Dybcio

On 14.06.2023 21:41, Akhil P Oommen wrote:
> On Mon, May 29, 2023 at 03:52:32PM +0200, Konrad Dybcio wrote:
>>
>> A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
>> features no GMU, as it's implemented solely on SoCs with SMD_RPM.
>> What's more interesting is that it does not feature a VDDGX line
>> either, being powered solely by VDDCX and has an unfortunate hardware
>> quirk that makes its reset line broken - after a couple of assert/
>> deassert cycles, it will hang for good and will not wake up again.
>>
>> This GPU requires mesa changes for proper rendering, and lots of them
>> at that. The command streams are quite far away from any other A6XX
>> GPU and hence it needs special care. This patch was validated both
>> by running an (incomplete) downstream mesa with some hacks (frames
>> rendered correctly, though some instructions made the GPU hangcheck
>> which is expected - garbage in, garbage out) and by replaying RD
>> traces captured with the downstream KGSL driver - no crashes there,
>> ever.
>>
>> Add support for this GPU on the kernel side, which comes down to
>> pretty simply adding A612 HWCG tables, altering a few values and
>> adding a special case for handling the reset line.
>>
>> Reviewed-by: Dmitry Baryshkov 
>> Signed-off-by: Konrad Dybcio 
>> ---
>>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c  | 101 
>> +
>>  drivers/gpu/drm/msm/adreno/adreno_device.c |  12 
>>  drivers/gpu/drm/msm/adreno/adreno_gpu.h|   8 ++-
>>  3 files changed, 108 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
>> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index bb04f65e6f68..c0d5973320d9 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -252,6 +252,56 @@ static void a6xx_submit(struct msm_gpu *gpu, struct 
>> msm_gem_submit *submit)
>>  a6xx_flush(gpu, ring);
>>  }
>>  
>> +const struct adreno_reglist a612_hwcg[] = {
>> +{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x},
>> +{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x0220},
>> +{REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x0081},
>> +{REG_A6XX_RBBM_CLOCK_HYST_SP0, 0xf3cf},
>> +{REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x},
>> +{REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x},
>> +{REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x},
>> +{REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x0002},
>> +{REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x},
>> +{REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x},
>> +{REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x},
>> +{REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x0001},
>> +{REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x},
>> +{REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x},
>> +{REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x},
>> +{REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x0007},
>> +{REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x},
>> +{REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x0120},
>> +{REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x2220},
>> +{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
>> +{REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
>> +{REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x},
>> +{REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x0011},
>> +{REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
>> +{REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x0422},
>> +{REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x},
>> +{REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x0222},
>> +{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x0002},
>> +{REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x},
>> +{REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000},
>> +{REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x},
>> +{REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x0200},
>> +{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x},
>> +{REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x},
>> +{REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x},
>> +{REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
>> +{REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x},
>> +{REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x},
>> +{REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x0004},
>> +{REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x0002},
>> +{REG_A6XX_RBBM_ISDB_CNT, 0x0182},
>> +{REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x},
>> +{REG_A6XX_RBBM_SP_HYST_CNT, 0x},
>> +{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x0222},
>> +{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x0111},
>> +{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x0555},
>> +{},
>> +};
>> +
>>  /* For a615 family (a615, a616, a618 and a619) */
>>  const struct adreno_reglist a615_hwcg[] = {
>>  {REG_A6XX_RBBM_CLOCK_CNTL_SP0,  0x0222},
>> @@ -602,6 +652,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool 
>> state)
>>  
>>  if (adreno_is_a630(adreno_gpu))
>>  clock_cntl_on = 0x8aa8aa02;
>> +else if (adreno_is_a610(adreno_gpu))
>> +clock_cntl_on = 0xaaa8aa82;
>>  else
>>  clock_cntl_on = 0x8aa8aa82;
>>  
>> @@ -612,13 +664,15 @@ static

Re: [Freedreno] [PATCH 1/2] drm/msm/dpu: do not enable color-management if DSPPs are not available

2023-06-15 Thread Yongqin Liu

On Tue, 13 Jun 2023 at 02:25, Dmitry Baryshkov
 wrote:
>
> We can not support color management without DSPP blocks being provided
> in the HW catalog. Do not enable color management for CRTCs if num_dspps
> is 0.
>
> Fixes: 4259ff7ae509 ("drm/msm/dpu: add support for pcc color block in dpu 
> driver")
> Reported-by: Yongqin Liu 
> Signed-off-by: Dmitry Baryshkov 
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)

Thanks for this fix!
With it applied to the ACK android-mainline branch,
the "dpu error" problem reported here:

https://lore.kernel.org/lkml/camso37vmhb1-pup1qu8gaxoxtu98eeymwd71foai+cwlb-j...@mail.gmail.com/
is not reproduced.

Tested-by: Yongqin Liu 

> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 6e684a7b49a1..1edf2b6b0a26 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -1463,6 +1463,8 @@ static const struct drm_crtc_helper_funcs 
> dpu_crtc_helper_funcs = {
>  struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane 
> *plane,
> struct drm_plane *cursor)
>  {
> +   struct msm_drm_private *priv = dev->dev_private;
> +   struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
> struct drm_crtc *crtc = NULL;
> struct dpu_crtc *dpu_crtc = NULL;
> int i, ret;
> @@ -1494,7 +1496,8 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
> struct drm_plane *plane,
>
> drm_crtc_helper_add(crtc, _crtc_helper_funcs);
>
> -   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
> +   if (dpu_kms->catalog->dspp_count)
> +   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
>
> /* save user friendly CRTC name for later */
> snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
> --
> 2.39.2
>

-- 
Best Regards,
Yongqin Liu
---
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[Freedreno] [bug report] drm/msm/a5xx: really check for A510 in a5xx_gpu_init

2023-06-15 Thread Dan Carpenter

Hello Dmitry Baryshkov,

This is a semi-automatic email about new static checker warnings.

The patch 736a93273656: "drm/msm/a5xx: really check for A510 in
a5xx_gpu_init" from Apr 9, 2023, leads to the following Smatch
complaint:

drivers/gpu/drm/msm/adreno/a5xx_gpu.c:1753 a5xx_gpu_init()
warn: variable dereferenced before check 'pdev' (see line 1746)

drivers/gpu/drm/msm/adreno/a5xx_gpu.c
  1745  struct platform_device *pdev = priv->gpu_pdev;
  1746  struct adreno_platform_config *config = pdev->dev.platform_data;
^^^
The patch adds an unchecked dereference

  1747  struct a5xx_gpu *a5xx_gpu = NULL;
  1748  struct adreno_gpu *adreno_gpu;
  1749  struct msm_gpu *gpu;
  1750  unsigned int nr_rings;
  1751  int ret;
  1752  
  1753  if (!pdev) {
^
But the existing code assumes it can be NULL.  Do we really need this
check?

  1754  DRM_DEV_ERROR(dev->dev, "No A5XX device is defined\n");
  1755  return ERR_PTR(-ENXIO);

regards,
dan carpenter

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