Re: Free up bits in DECLs and TYPEs

[DJ Delorie]

I'm OK with the msp430 part :-)

Re: [PATCH 1/6] [DJGPP] libstdc++-v3/config/os/djgpp/error_constants.h: Update according to errno codes available for DJGPP

[DJ Delorie]

> I can't really judge this one.  Either DJ or Jon would need to some in 
> on this.

Looks OK to me, although in the default configuration (plain DJGPP)
the #ifdefs will always be false (omitted), which is harmless.

[rx] avoid long calls

[DJ Delorie]

Immediate mode jumps have limits; this new option tells gcc to avoid
those instructions (by using indirect mode ones) in those rare cases
where the user has a program that big.  Committed.

* config/rx/rx.opt (-mjsr): Add.
* config/rx/predicates.md (rx_call_operand): Avoid overflowing
calls when -mjsr.
* config/rx/rx.c (rx_function_ok_for_sibcall): Likewise for
overflowing jumps.
* doc/invoke.texi (-mjsr): Document it.

Index: doc/invoke.texi
===
--- doc/invoke.texi (revision 231438)
+++ doc/invoke.texi (working copy)
@@ -965,12 +965,13 @@ See RS/6000 and PowerPC Options.
 -mas100-syntax -mno-as100-syntax@gol
 -mrelax@gol
 -mmax-constant-size=@gol
 -mint-register=@gol
 -mpid@gol
 -mallow-string-insns -mno-allow-string-insns@gol
+-mjsr@gol
 -mno-warn-multiple-fast-interrupts@gol
 -msave-acc-in-interrupts}
 
 @emph{S/390 and zSeries Options}
 @gccoptlist{-mtune=@var{cpu-type}  -march=@var{cpu-type} @gol
 -mhard-float  -msoft-float  -mhard-dfp -mno-hard-dfp @gol
@@ -20682,12 +20683,21 @@ disabled automatically.  Instead it is r
 use the @option{-mno-allow-string-insns} option if their program
 accesses I/O space.
 
 When the instructions are enabled GCC defines the C preprocessor
 symbol @code{__RX_ALLOW_STRING_INSNS__}, otherwise it defines the
 symbol @code{__RX_DISALLOW_STRING_INSNS__}.
+
+@item -mjsr
+@itemx -mno-jsr
+@opindex mjsr
+@opindex mno-jsr
+Use only (or not only) @code{JSR} instructions to access functions.
+This option can be used when code size exceeds the range of @code{BSR}
+instructions.  Note that @option{-mno-jsr} does not mean to not use
+@code{JSR} but instead means that any type of branch may be used.
 @end table
 
 @emph{Note:} The generic GCC command-line option @option{-ffixed-@var{reg}}
 has special significance to the RX port when used with the
 @code{interrupt} function attribute.  This attribute indicates a
 function intended to process fast interrupts.  GCC ensures
Index: config/rx/predicates.md
===
--- config/rx/predicates.md (revision 231438)
+++ config/rx/predicates.md (working copy)
@@ -21,13 +21,15 @@
 
 
 ;; Check that the operand is suitable for a call insn.
 ;; Only registers and symbol refs are allowed.
 
 (define_predicate "rx_call_operand"
-  (match_code "symbol_ref,reg")
+  (ior (match_code "reg")
+   (and (match_test "!TARGET_JSR")
+   (match_code "symbol_ref")))
 )
 
 ;; For sibcall operations we can only use a symbolic address.
 
 (define_predicate "rx_symbolic_call_operand"
   (match_code "symbol_ref")
Index: config/rx/rx.c
===
--- config/rx/rx.c  (revision 231438)
+++ config/rx/rx.c  (working copy)
@@ -2854,12 +2854,15 @@ rx_warn_func_return (tree decl)
 /* Return nonzero if it is ok to make a tail-call to DECL,
a function_decl or NULL if this is an indirect call, using EXP  */
 
 static bool
 rx_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
 {
+  if (TARGET_JSR)
+return false;
+
   /* Do not allow indirect tailcalls.  The
  sibcall patterns do not support them.  */
   if (decl == NULL)
 return false;
 
   /* Never tailcall from inside interrupt handlers or naked functions.  */
Index: config/rx/rx.opt
===
--- config/rx/rx.opt(revision 231438)
+++ config/rx/rx.opt(working copy)
@@ -146,6 +146,12 @@ Enable the use of the LRA register alloc
 
 ;---
 
 mallow-string-insns
 Target Report Var(rx_allow_string_insns) Init(1)
 Enables or disables the use of the SMOVF, SMOVB, SMOVU, SUNTIL, SWHILE and 
RMPA instructions.  Enabled by default.
+
+;---
+
+mjsr
+Target Report Mask(JSR)
+Always use JSR, never BSR, for calls.

[rl78] fix far addressing etc

[DJ Delorie]

Various fixes for far memory addressing (and large programs in general).  
Committed.

* config/rl78/constraints.md (Wfr): Change to be a non-memory
constraint.
* config/rl78/rl78-protos.h (rl78_one_far_p): Declare.
* config/rl78/rl78.c (rl78_one_far_p): Define.
* config/rl78/rl78-virt (movqi_virt): Fix far memory
alternatives.
(movhi_virt): Likewise.
(zero_extendqihi2_virt): Likewise.
(extendqihi2_virt): Likewise.
(add3_virt): Likewise.
(sub3_virt): Likewise.
(andqi3_virt): Likewise.
(iorqi3_virt): Likewise.
(xorqi3_virt): Likewise.
* config/rl78/rl78-real.md (bf,br): Use long forms to avoid reloc
overflow in large files.

Index: gcc/config/rl78/constraints.md
===
--- gcc/config/rl78/constraints.md  (revision 231385)
+++ gcc/config/rl78/constraints.md  (working copy)
@@ -361,13 +361,13 @@
 (define_memory_constraint "Ws1"
   "es:word8[SP]"
   (match_test "(rl78_es_addr (op) && satisfies_constraint_Cs1 (rl78_es_base 
(op)))
|| satisfies_constraint_Cs1 (op)")
   )
 
-(define_memory_constraint "Wfr"
+(define_constraint "Wfr"
   "ES/CS far pointer"
   (and (match_code "mem")
(match_test "rl78_far_p (op)"))
   )
 
 (define_memory_constraint "Wsa"
Index: gcc/config/rl78/rl78-protos.h
===
--- gcc/config/rl78/rl78-protos.h   (revision 231385)
+++ gcc/config/rl78/rl78-protos.h   (working copy)
@@ -51,6 +51,8 @@ bool  rl78_flags_already_set (rtx, rtx);
 void   rl78_output_symbol_ref (FILE *, rtx);
 void   rl78_output_labelref (FILE *, const char *);
 intrl78_saddr_p (rtx x);
 intrl78_sfr_p (rtx x);
 void   rl78_output_aligned_common (FILE *, tree, const char *,
int, int, int);
+
+intrl78_one_far_p (rtx *operands, int num_operands);
Index: gcc/config/rl78/rl78-real.md
===
--- gcc/config/rl78/rl78-real.md(revision 231385)
+++ gcc/config/rl78/rl78-real.md(working copy)
@@ -586,25 +586,25 @@
(if_then_else (eq (and (reg:QI A_REG)
   (match_operand 0 "immediate_operand" "n"))
  (const_int 0))
  (label_ref (match_operand 1 "" ""))
  (pc)))]
   ""
-  "bf\tA.%B0, $%1"
+  "bt\tA.%B0, $1f\n\tbr !!%1\n\t1:"
   [(set (attr "update_Z") (const_string "clobber"))]
 )
 
 (define_insn "bt"
   [(set (pc)
(if_then_else (ne (and (reg:QI A_REG)
   (match_operand 0 "immediate_operand" "n"))
  (const_int 0))
  (label_ref (match_operand 1 "" ""))
  (pc)))]
   ""
-  "bt\tA.%B0, $%1"
+  "bf\tA.%B0, $1f\n\tbr !!%1\n\t1:"
   [(set (attr "update_Z") (const_string "clobber"))]
 )
 
 ;; NOTE: These peepholes are fragile.  They rely upon GCC generating
 ;; a specific sequence on insns, based upon examination of test code.
 ;; Improvements to GCC or using code other than the test code can result
Index: gcc/config/rl78/rl78-virt.md
===
--- gcc/config/rl78/rl78-virt.md(revision 231385)
+++ gcc/config/rl78/rl78-virt.md(working copy)
@@ -39,14 +39,14 @@
   "rl78_virt_insns_ok ()"
   "v.mov %0, %1"
   [(set_attr "valloc" "op1")]
 )
 
 (define_insn "*movqi_virt"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=vY,v,Wfr")
-   (match_operand1 "general_operand" "vInt8J,YWfr,vInt8J"))]
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=vY,v,*Wfr,Y,*Wfr,*Wfr")
+   (match_operand1 "general_operand" 
"vInt8JY,*Wfr,vInt8J,*Wfr,Y,*Wfr"))]
   "rl78_virt_insns_ok ()"
   "v.mov %0, %1"
   [(set_attr "valloc" "op1")]
 )
 
 (define_insn "*movhi_virt_mm"
@@ -55,33 +55,33 @@
   "rl78_virt_insns_ok ()"
   "v.movw %0, %1"
   [(set_attr "valloc" "op1")]
 )
 
 (define_insn "*movhi_virt"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=vS,  Y,   v,   Wfr")
-   (match_operand:HI 1 "general_operand"  "viYS, viS, Wfr, vi"))]
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=vS,  Y,   v,   *Wfr")
+   (match_operand:HI 1 "general_operand"  "viYS, viS, *Wfr, vi"))]
   "rl78_virt_insns_ok ()"
   "v.movw %0, %1"
   [(set_attr "valloc" "op1")]
 )
 
 ;;-- Conversions 
 
 (define_insn "*zero_extendqihi2_virt"
-  [(set (match_operand:HI 0 "rl78_nonfar_nonimm_operand" "=vm")
-   (zero_extend:HI (match_operand:QI 1 "general_operand" "vim")))]
-  "rl78_virt_insns_ok ()"
+  [(set (match_operand:HI 0 "rl78_nonfar_nonimm_operand" 
"=vY,*Wfr")
+   (zero_extend:HI (match_operand:QI 1 "general_operand" "vim,viY")))]
+  

Proposal to deprecate: mep (Toshiba Media Processor)

[DJ Delorie]

Given a combination of "I have new responsibilities" and "nothing has
happened with mep for a long time" I would like to step down as mep
maintainer.

If someone would like to pick up maintainership of this target, please
contact me and/or the steering committee.  Otherwise, I propose this
target be deprecated in GCC 6 and removed in 7.

DJ

msp430: fix alignment in multiply

[DJ Delorie]

Minor fix, committed.

2015-11-19  DJ Delorie  <d...@redhat.com>

* config/msp430/lib2hw_mul.S: Fix alignment.

Index: libgcc/config/msp430/lib2hw_mul.S
===
--- libgcc/config/msp430/lib2hw_mul.S   (revision 230632)
+++ libgcc/config/msp430/lib2hw_mul.S   (working copy)
@@ -19,13 +19,13 @@
 ; a copy of the GCC Runtime Library Exception along with this program;
 ; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 ; <http://www.gnu.org/licenses/>.
 
 .macro start_func name
.pushsection .text.\name,"ax",@progbits
-   .align 2
+   .p2align 1
.global \name
.type \name , @function
 \name:
PUSH.W  sr  ; Save current interrupt state
DINT; Disable interrupts
NOP ; Account for latency

Re: [PATCH] ctype functions and signedness

[DJ Delorie]

> --- libiberty/pex-win32.c
> +++ /tmp/cocci-output-25924-3a75ca-pex-win32.c
> @@ -547,8 +547,8 @@ env_compare (const void *a_ptr, const vo
>  
>do
>  {
> -  c1 = (unsigned char) tolower (*a++);
> -  c2 = (unsigned char) tolower (*b++);
> +  c1 = (unsigned char) tolower ((unsigned char)*a++);
> +  c2 = (unsigned char) tolower ((unsigned char)*b++);
>  
>if (c1 == '=')
>  c1 = '\0';

Since the only use of a and b in this function are to pass to tolower,
changing the type of a and b to unsigned char (and updating the casts
where they're initialized) would make more sense.

Re: [RFA] Do not use libiberty's getpagesize on Android

[DJ Delorie]

> libiberty/ChangeLog:
> 
> * configure.ac: Set AC_CV_FUNC_GETPAGESIZE to "yes" on
> Android hosts.
> * configure: Regenerate.
> 
> OK to apply?

Ok.

Re: [PATCH] replace BITS_PER_UNIT with __CHAR_BIT__ in target libs

[DJ Delorie]

> $subject as far as I am aware these are the same on all supported targets.

The documentation for __CHAR_BIT__ says not to use it...

  @item __CHAR_BIT__
  Defined to the number of bits used in the representation of the
  @code{char} data type.  It exists to make the standard header given
  numerical limits work correctly.  You should not use
  this macro directly; instead, include the appropriate headers.

And the definition of BITS_PER_UNIT is more appropriate anyway:

  @item BITS_PER_UNIT
  The number of bits in an addressable storage unit (byte).  If you do
  not define this, the default is 8.

If a target had a sizeof(char) != 1, __CHAR_BIT__ and BITS_PER_UNIT
would be different, and IMHO BITS_PER_UNIT is the one we want to use
in the runtime, unless you're specifically talking about the "char"
type:

  cpp_define_formatted (pfile, "__CHAR_BIT__=%u",
TYPE_PRECISION (char_type_node));

Re: [PATCH: RL78] libgcc fixes for divmodsi, divmodhi and divmodqi

[DJ Delorie]

> This is regression tested for RL78 -msim. Please let me know if it is
> OK to commit.

I've committed this patch for you.  Thanks!

> Best Regards,
> Kaushik
> 
> Changelog:
> 2015-08-21  Kaushik Phatak  
> 
> * config/rl78/divmodqi.S: Return 0x00 by default for div by 0.
> * config/rl78/divmodsi.S: Update return register to r8.
> * config/rl78/divmodhi.S: Update return register to r8,r9.
>   Branch to main_loop_done_himode to pop registers before return.

Re: Is anyone working on a Z80 port?

[DJ Delorie]

> I spec'd one out a long time ago for Cygnus/Red Hat, but we never 
> pursued the port.  The register model on the z80 will be problematical, 
> though some of the lessons from the rl78 port would probably be useful.

The RL78 is very much a modern decendent of the Z80 architecture so might
serve as a good starting point.

But yeah, it's a messy port because gcc doesn't like the weird
addressing model.  I ended up using a virtual ISA that gcc could deal
with, then converted that to real instructions after reload.

Re: reload question about unmet constraints

[DJ Delorie]

> So in general, it's really not safe to mark a constraint that accepts
> only far memory as "memory constraint" with current reload.
> 
> Note that *not* marking the constraint as memory constraint actually
> does not prevent reload from fixing up illegitimate addresses, so you
> shouldn't really see much drawbacks from not marking it ...

While working through the regressions on this one I discovered one
seemingly important side-effect...

For such constraints that are memory operands but not
define_memory_constraint, you need to use '*' to keep reload from
trying to guess a register class from them (it guesses wrong for
rl78).

I.e. use "*Wfr" instead of "Wfr".

Re: Repository for the conversion machinery

[DJ Delorie]

Richard Biener  writes:
>> Using d...@gcc.gnu.org would imply that is my email address, but email
>> sent there would vanish.
>
> Would it?  You're supposed to have a valid forwarding address on that.

Frank tested it and it does seem to forward to me, so I guess so.

Re: reload question about unmet constraints

[DJ Delorie]

> And in fact, you should be able to decide at *expand* time which
> of the two you need for the given set of operands.

I already check for multiple fars at expand, and force all but one of
them to registers.  Somewhere before reload they get put back in.

>"rl78_virt_insns_ok () && rl78_far_insn_p (operands)"

Since when does this work reliably?  I've seen cases where insns get
mashed together without regard for validity before...

I tested just this change - adding that function to addhi3 plus the
Wfr constraint sets - and it seems to work.  The big question to me
now is - is this *supposed* to work this way?  Or is is a coincidence
that the relevent passes happen to check that function?

> The Wfr constraint must not be marked as memory constraint (so as to
> avoid reload attempting to use it to access a stack slot).

This also prevents reload from reloading the address when it *is*
needed.  However, it seems to work ok even as a memory constraint.  Is
this change *just* because of the stack slots?  Could you give an
example of how it could be misused, so I can understand the need?

Re: Repository for the conversion machinery

[DJ Delorie]

"Frank Ch. Eigler"  writes:
> That makes sense, but how many people are in cagney's shoes

I am one of those people - I have two email addresses listed in
MAINTAINERS, with two sets of copyright papers filed with the FSF (a
personal assignment and a work one).  I use the appropriate email
address for each commit depending on which maintainership role I'm
reflecting.

Neither address is "obsolete" and neither address is @gcc.gnu.org.

Using d...@gcc.gnu.org would imply that is my email address, but email
sent there would vanish.

But I did discuss my case with esr and understand it's not as easy to
solve as we'd like it to be.

Re: reload question about unmet constraints

[DJ Delorie]

> You would need some way to indicate that while Y does accept a mem,
> this particular mem can't be reloaded to match.  We don't have a way
> to do that.

As a test, I added this API.  It seems to work.  I suppose there could
be a better API where we determine if a constrain matches various
memory spaces, then compare with the memory space of the operand, but
I can't prove that's sufficiently flexible for all targets that
support memory spaces.  Heck, I'm not even sure what to call the
macro, and 
"TARGET_IS_THIS_MEMORY_ADDRESS_RELOADABLE_TO_MATCH_THIS_CONTRAINT_P()"
is a little long ;-)

What do we think of this direction?


Index: reload.c
===
RCS file: /cvs/cvsfiles/gnupro/gcc/reload.c,v
retrieving revision 1.33
diff -p -U 5 -r1.33 reload.c
--- reload.c20 Feb 2014 16:40:26 -  1.33
+++ reload.c15 Sep 2015 05:38:24 -
@@ -3517,20 +3517,26 @@ find_reloads (rtx insn, int replace, int
 && ((reg_equiv_mem (REGNO (operand)) != 0
  && EXTRA_CONSTRAINT_STR 
(reg_equiv_mem (REGNO (operand)), c, p))
 || (reg_equiv_address (REGNO 
(operand)) != 0)))
  win = 1;
 
+#ifndef COMPATIBLE_CONSTRAINT_P
+#define COMPATIBLE_CONSTRAINT_P(c,p,op) 1
+#endif
+   if (!MEM_P (operand) || COMPATIBLE_CONSTRAINT_P (c, 
p, operand))
+ {
/* If we didn't already win, we can reload
   constants via force_const_mem, and other
   MEMs by reloading the address like for 'o'.  */
if (CONST_POOL_OK_P (operand_mode[i], operand)
|| MEM_P (operand))
  badop = 0;
constmemok = 1;
offmemok = 1;
break;
  }
+ }
if (EXTRA_ADDRESS_CONSTRAINT (c, p))
  {
if (EXTRA_CONSTRAINT_STR (operand, c, p))
  win = 1;
 

Index: config/rl78/rl78.c
===
RCS file: /cvs/cvsfiles/gnupro/gcc/config/rl78/rl78.c,v
retrieving revision 1.12.6.16
diff -p -U 5 -r1.12.6.16 rl78.c
--- config/rl78/rl78.c  5 Aug 2015 13:43:59 -   1.12.6.16
+++ config/rl78/rl78.c  15 Sep 2015 05:39:04 -
@@ -1041,10 +1041,18 @@ rl78_far_p (rtx x)
 return 0;
 
   return GET_MODE_BITSIZE (rl78_addr_space_address_mode (MEM_ADDR_SPACE (x))) 
== 32;
 }
 
+int
+rl78_compatible_constraint_p (char c, const char *p, rtx r)
+{
+  if (c == 'Y' && rl78_far_p (r))
+return 0;
+  return 1;
+}
+
 /* Return the appropriate mode for a named address pointer.  */
 #undef  TARGET_ADDR_SPACE_POINTER_MODE
 #define TARGET_ADDR_SPACE_POINTER_MODE rl78_addr_space_pointer_mode
 
 static enum machine_mode

Index: config/rl78/rl78.h
===
RCS file: /cvs/cvsfiles/gnupro/gcc/config/rl78/rl78.h,v
retrieving revision 1.7.8.3
diff -p -U 5 -r1.7.8.3 rl78.h
--- config/rl78/rl78.h  17 Mar 2015 14:54:35 -  1.7.8.3
+++ config/rl78/rl78.h  15 Sep 2015 05:39:28 -
@@ -500,5 +500,7 @@ typedef unsigned int CUMULATIVE_ARGS;
 
 /* NOTE: defined but zero means dwarf2 debugging, but sjlj EH.  */
 #define DWARF2_UNWIND_INFO 0
 
 #define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas()
+
+#define COMPATIBLE_CONSTRAINT_P(C,P,OP) rl78_compatible_constraint_p (C,P,OP)

Re: reload question about unmet constraints

[DJ Delorie]

> I see.  Is it correct then to say that reload will never be able to
> change a near mem into a far mem or vice versa?  If that is true, there
> doesn't appear to be any real benefit to having both near and far mem
> operations as *alternatives* to the same insn pattern.

The RL78 has a segment register, much like the x86.  The segment
register allows you to have a 20-bit address instead of a 16-bit
address.  However, due to details of the port, you can only have *one*
segment register override per operation, even if it applies to more
than one (identical) operand.  So, you can add two near pointers, but
you can't add two different far pointers, but you can add something to
a far pointer (i.e. x += 5).

> In that case, you might be able to fix the bug by splitting the
> offending insns into two patterns, one only handling near mems
> and one handling one far mems, where the near/far-ness of the mem
> is verified by the *predicate* and not the constraints.

But this means that when reload needs to, it moves far mems into
registers, which changes which insn is matched...  It also adds a
*lot* of new patterns, since any of the three operands can be far, and
'0' constraints on far are allowed also - and most insns allow far
this way, so could be up to seven times as many patterns.

You can see why I'd rather not do that :-)

reload question about unmet constraints

[DJ Delorie]

Given this test case for rl78-elf:

extern __far int a, b;
void ffr (int x)
{
  a = b + x;
}

I'm trying to use this patch:

Index: gcc/config/rl78/rl78-virt.md
===
--- gcc/config/rl78/rl78-virt.md  (revision 227360)
+++ gcc/config/rl78/rl78-virt.md(working copy)
@@ -92,15 +92,15 @@
]
   "rl78_virt_insns_ok ()"
   "v.inc\t%0, %1, %2"
 )
 
 (define_insn "*add3_virt"
-  [(set (match_operand:QHI   0 "rl78_nonfar_nonimm_operand" "=vY,S")
-   (plus:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "viY,0")
- (match_operand:QHI 2 "rl78_general_operand" "vim,i")))
+  [(set (match_operand:QHI   0 "rl78_nonimmediate_operand" "=vY,S,Wfr")
+   (plus:QHI (match_operand:QHI 1 "rl78_general_operand" "viY,0,0")
+ (match_operand:QHI 2 "rl78_general_operand" "vim,i,vi")))
]
   "rl78_virt_insns_ok ()"
   "v.add\t%0, %1, %2"
 )
 
 (define_insn "*sub3_virt"


To allow the rl78 port to generate the "Wfr/0/r" case (alternative 3).
(Wfr = far MEM, v = virtual regs).

I expected gcc to see that the operation doesn't meet the constraints,
and move operands into registers to make it work (alternative 1,
"v/v/v").

Instead, it just complains and dies.

dj.c:42:1: error: insn does not satisfy its constraints:
 }
 ^
(insn 10 15 13 2 (set (mem/c:HI (reg:SI 8 r8) [1 a+0 S2 A16 AS2])
(plus:HI (mem/c:HI (plus:HI (reg/f:HI 32 sp)
(const_int 4 [0x4])) [1 x+0 S2 A16])
(mem/c:HI (symbol_ref:SI ("b") ) [1 b+0 
S2 A16 AS2]))) dj.c:41 13 {*addhi3_virt}
 (nil))
dj.c:42:1: internal compiler error: in extract_constrain_insn, at recog.c:2200


Reloads for insn # 10
Reload 0: reload_in (SI) = (symbol_ref:SI ("a")  )
V_REGS, RELOAD_FOR_INPUT (opnum = 0), inc by 2
reload_in_reg: (symbol_ref:SI ("a")  )
reload_reg_rtx: (reg:SI 8 r8)
Reload 1: reload_in (HI) = (mem/c:HI (plus:HI (reg/f:HI 32 sp)
(const_int 4 [0x4])) [2 
x+0 S2 A16])
reload_out (HI) = (mem/c:HI (plus:HI (reg/f:HI 32 sp)
(const_int 4 [0x4])) [2 
x+0 S2 A16])
V_REGS, RELOAD_OTHER (opnum = 1), optional
reload_in_reg: (mem/c:HI (plus:HI (reg/f:HI 32 sp)
(const_int 4 [0x4])) [2 
x+0 S2 A16])
reload_out_reg: (mem/c:HI (plus:HI (reg/f:HI 32 sp)
(const_int 4 [0x4])) [2 
x+0 S2 A16])
Reload 2: reload_in (HI) = (mem/c:HI (symbol_ref:SI ("b")  ) [2 b+0 S2 A16 AS2])
V_REGS, RELOAD_FOR_INPUT (opnum = 2), optional
reload_in_reg: (mem/c:HI (symbol_ref:SI ("b")  ) [2 b+0 S2 A16 AS2])


So this is where I've been banging my head against the
sources... where is the magic that tells gcc to try to copy everything
into registers to meet the constraints?

Note: expand is ok, the initial add insn is:

(insn 9 3 10 2 (set (reg:HI 48 [ D.1375 ])
(plus:HI (reg/v:HI 45 [ x ])
(mem/c:HI (symbol_ref:SI ("b")  ) [2 b+0 
S2 A16 AS2]))) dj.c:43 -1
 (nil))

and just before reload:

(insn 10 9 0 2 (set (mem/c:HI (symbol_ref:SI ("a")  ) [2 a+0 S2 A16 AS2])
(plus:HI (mem/c:HI (reg/f:HI 33 ap) [2 x+0 S2 A16])
(mem/c:HI (symbol_ref:SI ("b")  ) [2 b+0 
S2 A16 AS2]))) dj.c:43 13 {*addhi3_virt}
 (nil))

Re: reload question about unmet constraints

[DJ Delorie]

> It did match the first alternative (alternative 0), but it matched the
> constraints Y/Y/m.

It shouldn't match Y as those are for near addresses (unless it's only
matching MEM==MEM), and the ones in the insn are far, but ...

> Reload doesn't have any concept of two different kinds of memory
> operands which can't be converted via reloads.  If the constraint
> accepts mem, and we have a mem operand, then it will always assume
> that the problem is with the address and reload it.

... this sounds like it could be a problem for me :-P

Re: [PATCH : RL78] Disable interrupts during hardware multiplication routines

[DJ Delorie]

 I have worked out an updated patch, which would save the MDUC specific 
 registers
 in the interrupt routine when the option '-msave-mduc-in-interrupts' is 
 passed.
 This gets active only for the G13 targets.

Perhaps we should have both a -msave... and -mno-save... (gcc provides
these by default) with the default if neither is provided, to be save
if g13?

As an optimization, gcc could test the interrupt function to see if it
has any multiplcation or call insns, and if not, don't bother with the
(determined to be unneeded) saves.

 +(define_insn movqi_from_mduc
 +  [(set (match_operand:QI 0 register_operand =a)
 +(unspec_volatile:QI [(match_operand:QI 1  )] UNS_BUILTIN_MDUC))]
 +  
 +  mov\t%0, !0xf00e8
 +)

You shouldn't need special move insns for these; they're regular
variables.  Just generate the RTL for the memory references (make sure
they're volatile) and use the standard movhi patterns.

Unspec patterns are typically used for unknown *opcodes*, not special
registers or memory locations.

 @@ -1273,6 +1280,7 @@
int i, fs;
rtx sp = gen_rtx_REG (HImode, STACK_POINTER_REGNUM);
rtx ax = gen_rtx_REG (HImode, AX_REG);
 +  rtx operand1;
int rb = 0;
 
if (rl78_is_naked_func ())
 @@ -1330,6 +1338,39 @@
F (emit_insn (gen_push (ax)));
  }
 
 +  /* Save MDUC register from interrupt routine.  */
 +  if (MUST_SAVE_MDUC_REGISTER)
 +{
 +  emit_insn (gen_movqi_from_mduc (gen_rtx_REG (QImode, A_REG),
 +  gen_rtx_UNSPEC_VOLATILE (QImode, gen_rtvec (1, operand1),
 +   UNS_BUILTIN_MDUC)));

You never set operand1 to anything.  Since you never use it, you don't
really need it in the patterns either (just put [(const_int 0)] in the
unspec).  (but better to use a regular movhi as described above).

 +as this makes the interrupt handlers faster. The target option -mg13

That last bit is not a complete sentence.

 This message contains information that may be privileged or
 confidential . . .

Reminder that such notices are inappropriate for public mailing lists.

Re: Repository for the conversion machinery

[DJ Delorie]

Hmmm... I use two email addresses for commits, depending on which target
they're for, i.e.:

$ grep DJ MAINTAINERS 
m32c port   DJ Delorie  d...@redhat.com
DJGPP   DJ Delorie  d...@delorie.com

Most of the DJGPP stuff was long ago but I wonder how the conversion
would handle this?

Re: Offer of help with move to git

[DJ Delorie]

 In the mean time, I'm enclosing a contributor map that will need to be
 filled in whoever does the conversion.  The right sides should become
 full names and preferred email addresses.

This information should be gleanable from the Changelog commits...
do you have a script to scan those?

Re: Question about instruction merge pass when optimizing for size

[DJ Delorie]

I've seen this on other targets too, sometimes so bad I write a quick
target-specific stupid move optimizer pass to clean it up.

A generic pass would be much harder, but very useful.

Re: rx: remove some asserts

[DJ Delorie]

 Hi DJ,
 
 There is no need to assert these just to say not supported and gcc
 may rarely generate addresses from valid code which trigger these
 asserts.  Ok?
 
 OK - please apply.

Thanks, committed.

Re: [PATCH] toplevel: fixes for in-tree libiconv

[DJ Delorie]

I have applied and committed these patches, both in gcc and binutils-gdb.

Re: RFA: RL78: Fix multiply costs when optimizing for size

[DJ Delorie]

   OK to apply ?

Ok.  Thanks!

 gcc/ChangeLog
 2015-08-05  Nick Clifton  ni...@redhat.com
 
   * config/rl78/rl78.c (rl78_rtx_costs): Treat MULT insns as cheap
   if optimizing for size.
 
 Index: gcc/config/rl78/rl78.c
 ===
 RCS file: /cvs/cvsfiles/gnupro/gcc/config/rl78/rl78.c,v
 retrieving revision 1.12.6.15
 diff -u -3 -p -r1.12.6.15 rl78.c
 --- gcc/config/rl78/rl78.c29 Jul 2015 12:24:04 -  1.12.6.15
 +++ gcc/config/rl78/rl78.c30 Jul 2015 15:20:10 -
 @@ -4161,7 +4161,9 @@ static bool rl78_rtx_costs (rtx   x,
switch (code)
   {
   case MULT:
 -   if (RL78_MUL_G14)
 +   if (! speed)
 + * total = COSTS_N_INSNS (5);
 +   else if (RL78_MUL_G14)
   *total = COSTS_N_INSNS (14);
 else if (RL78_MUL_G13)
   *total = COSTS_N_INSNS (29);
 

Re: RFA: RL78: Remove far operand optimization in rl78_force_nonfar_3

[DJ Delorie]

This is OK, but note that it prevents some operations like:

__far int i;

foo()
{
  i ++;
}

from being implemented with a minimum set of opcodes.  This might be
particularly troublesome for volatile far things.

Re: RFA: RL78: Add an optimization to the addsi3 pattern

[DJ Delorie]

Ok, but please don't put non-public issue numbers in the comments.

Re: libstdc++: more __intN tweaks

[DJ Delorie]

  * include/bits/functional_hash.h: Add specializations for __intN
  types.
 
  * include/ext/pb_ds/detail/thin_heap_/thin_heap_.hpp (__gnu_pbds):
  Guard against values that might exceed size_t's precision.
 
 Yes, OK - thanks.

Committed.  Thanks!

libstdc++: more __intN tweaks

[DJ Delorie]

Another place where a list of all types are explicitly listed, and
the __intN types need to be included, and elsewhere protection against
errors [-Wnarrowing] on targets that have small size_t.  Ok?

* include/bits/functional_hash.h: Add specializations for __intN
types.

* include/ext/pb_ds/detail/thin_heap_/thin_heap_.hpp (__gnu_pbds):
Guard against values that might exceed size_t's precision.
 

Index: libstdc++-v3/include/ext/pb_ds/detail/thin_heap_/thin_heap_.hpp
===
--- libstdc++-v3/include/ext/pb_ds/detail/thin_heap_/thin_heap_.hpp 
(revision 226081)
+++ libstdc++-v3/include/ext/pb_ds/detail/thin_heap_/thin_heap_.hpp 
(working copy)
@@ -267,36 +267,45 @@ namespace __gnu_pbds
/* 18*/ 3571ul,
/* 19*/ 5777ul,
/* 20*/ 9349ul,
/* 21*/ 15126ul,
/* 22*/ 24476ul,
/* 23*/ 39602ul,
-   /* 24*/ 64079ul,
+   /* 24*/ 64079ul
+#if __SIZE_MAX__  0xul
+   ,
/* 25*/ 103681ul,
/* 26*/ 167761ul,
/* 27*/ 271442ul,
/* 28*/ 439204ul,
-   /* 29*/ 710646ul,
+   /* 29*/ 710646ul
+#if __SIZE_MAX__  0xful
+   ,
/* 30*/ 1149851ul,
/* 31*/ 1860497ul,
/* 32*/ 3010349ul,
/* 33*/ 4870846ul,
/* 34*/ 7881196ul,
-   /* 35*/ 12752042ul,
+   /* 35*/ 12752042ul
+#if __SIZE_MAX__  0xfful
+   ,
/* 36*/ 20633239ul,
/* 37*/ 33385282ul,
/* 38*/ 54018521ul,
/* 39*/ 87403803ul,
/* 40*/ 141422324ul,
/* 41*/ 228826127ul,
/* 42*/ 370248451ul,
/* 43*/ 599074578ul,
/* 44*/ 969323029ul,
/* 45*/ 1568397607ul,
/* 46*/ 2537720636ul,
/* 47*/ 4106118243ul
+#endif
+#endif
+#endif
/* Pot's good, let's play */
   };
 
 #define PB_DS_ASSERT_NODE_CONSISTENT(_Node, _Bool) \
   _GLIBCXX_DEBUG_ONLY(assert_node_consistent(_Node, _Bool, \
 __FILE__, __LINE__);)
Index: libstdc++-v3/include/bits/functional_hash.h
===
--- libstdc++-v3/include/bits/functional_hash.h (revision 226081)
+++ libstdc++-v3/include/bits/functional_hash.h (working copy)
@@ -118,12 +118,29 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   /// Explicit specialization for unsigned long.
   _Cxx_hashtable_define_trivial_hash(unsigned long)
 
   /// Explicit specialization for unsigned long long.
   _Cxx_hashtable_define_trivial_hash(unsigned long long)
 
+#ifdef __GLIBCXX_TYPE_INT_N_0
+  _Cxx_hashtable_define_trivial_hash(__GLIBCXX_TYPE_INT_N_0)
+  _Cxx_hashtable_define_trivial_hash(__GLIBCXX_TYPE_INT_N_0 unsigned)
+#endif
+#ifdef __GLIBCXX_TYPE_INT_N_1
+  _Cxx_hashtable_define_trivial_hash(__GLIBCXX_TYPE_INT_N_1)
+  _Cxx_hashtable_define_trivial_hash(__GLIBCXX_TYPE_INT_N_1 unsigned)
+#endif
+#ifdef __GLIBCXX_TYPE_INT_N_2
+  _Cxx_hashtable_define_trivial_hash(__GLIBCXX_TYPE_INT_N_2)
+  _Cxx_hashtable_define_trivial_hash(__GLIBCXX_TYPE_INT_N_2 unsigned)
+#endif
+#ifdef __GLIBCXX_TYPE_INT_N_3
+  _Cxx_hashtable_define_trivial_hash(__GLIBCXX_TYPE_INT_N_3)
+  _Cxx_hashtable_define_trivial_hash(__GLIBCXX_TYPE_INT_N_3 unsigned)
+#endif
+
 #undef _Cxx_hashtable_define_trivial_hash
 
   struct _Hash_impl
   {
 static size_t
 hash(const void* __ptr, size_t __clength,

[msp430] minor optimizations and tweaks

[DJ Delorie]

As indicated.  Committed.

* config/msp430/t-msp430 (MULTILIB_DIRNAMES): Remove trailing
slashes.

* config/msp430/msp430.md (ashlhi3): Optimize shifts of subregs.
(ashrhi3): Likewise.
(lshrhi3): Likewise.
(movhi): Take advantage of zero-extend to load small constants.
(movpsi): Likewise.
(andmode3): Likewise.
(zero_extendqihi2): Likewise.
(zero_extendqisi2): New.
* config/msp430/constraints.md (N,O): New.
* config/msp430/msp430.h (WORD_REGISTER_OPERATIONS): Define.

Index: config/msp430/msp430.md
===
--- config/msp430/msp430.md (revision 226084)
+++ config/msp430/msp430.md (working copy)
@@ -196,16 +196,17 @@
   @
   MOV.B\t%1, %0
   MOV%X0.B\t%1, %0
 )
 
 (define_insn movhi
-  [(set (match_operand:HI 0 msp_nonimmediate_operand =rYs,rm)
-   (match_operand:HI 1 msp_general_operand riYs,rmi))]
+  [(set (match_operand:HI 0 msp_nonimmediate_operand =r,rYs,rm)
+   (match_operand:HI 1 msp_general_operand N,riYs,rmi))]
   
   @
+  MOV.B\t%1, %0
   MOV.W\t%1, %0
   MOV%X0.W\t%1, %0
 )
 
 (define_expand movsi
   [(set (match_operand:SI 0 nonimmediate_operand)
@@ -239,16 +240,18 @@
(match_operand:HI 5 general_operand))]
   msp430_split_movsi (operands);
 )
 
 ;; Some MOVX.A cases can be done with MOVA, this is only a few of them.
 (define_insn movpsi
-  [(set (match_operand:PSI 0 msp_nonimmediate_operand =r,Ya,rm)
-   (match_operand:PSI 1 msp_general_operand riYa,r,rmi))]
+  [(set (match_operand:PSI 0 msp_nonimmediate_operand =r,r,r,Ya,rm)
+   (match_operand:PSI 1 msp_general_operand N,O,riYa,r,rmi))]
   
   @
+  MOV.B\t%1, %0
+  MOV.W\t%1, %0
   MOVA\t%1, %0
   MOVA\t%1, %0
   MOVX.A\t%1, %0)
 
 ; This pattern is identical to the truncsipsi2 pattern except
 ; that it uses a SUBREG instead of a TRUNC.  It is needed in
@@ -497,17 +500,18 @@
   @
BIC%x0%b0\t%1, %0
BIC%X0%b0\t%1, %0
 )
 
 (define_insn andmode3
-  [(set (match_operand:QHI 0 msp_nonimmediate_operand =rYs,rm)
-   (and:QHI (match_operand:QHI 1 msp_nonimmediate_operand %0,0)
-(match_operand:QHI 2 msp_general_operand riYs,rmi)))]
+  [(set (match_operand:QHI 0 msp_nonimmediate_operand =r,rYs,rm)
+   (and:QHI (match_operand:QHI 1 msp_nonimmediate_operand %0,0,0)
+(match_operand:QHI 2 msp_general_operand N,riYs,rmi)))]
   
   @
+   AND%x0.B\t%2, %0
AND%x0%b0\t%2, %0
AND%X0%b0\t%2, %0
 )
 
 (define_insn iormode3
   [(set (match_operand:QHI  0 msp_nonimmediate_operand =rYs,rm)
@@ -546,17 +550,19 @@
   @
SXT%X0\t%0
SXT%X0\t%0
 )
 
 (define_insn zero_extendqihi2
-  [(set (match_operand:HI 0 msp_nonimmediate_operand 
=rYs,m)
-   (zero_extend:HI (match_operand:QI 1 msp_nonimmediate_operand 0,0)))]
+  [(set (match_operand:HI 0 msp_nonimmediate_operand 
=rYs,r,r,m)
+   (zero_extend:HI (match_operand:QI 1 msp_nonimmediate_operand 
0,rYs,m,0)))]
   
   @
AND\t#0xff, %0
+   MOV.B\t%1, %0
+   MOV%X0.B\t%1, %0
AND%X0\t#0xff, %0
 )
 
 ;; Eliminate extraneous zero-extends mysteriously created by gcc.
 (define_peephole2
   [(set (match_operand:HI 0 register_operand)
@@ -599,12 +605,20 @@
 )
 
 ;; Look for cases where integer/pointer conversions are suboptimal due
 ;; to missing patterns, despite us not having opcodes for these
 ;; patterns.  Doing these manually allows for alternate optimization
 ;; paths.
+
+(define_insn zero_extendqisi2
+  [(set (match_operand:SI 0 nonimmediate_operand =r)
+   (zero_extend:SI (subreg:HI (match_operand:QI 1 nonimmediate_operand 
rm) 0)))]
+  msp430x
+  MOV.B\t%1,%L0 { CLR\t%H0
+)
+
 (define_insn zero_extendhisi2
   [(set (match_operand:SI 0 nonimmediate_operand =rm,r)
(zero_extend:SI (match_operand:HI 1 nonimmediate_operand 0,r)))]
   msp430x
   @
   MOV.W\t#0,%H0
@@ -731,12 +745,15 @@
 (define_expand ashlhi3
   [(set (match_operand:HI0 nonimmediate_operand)
(ashift:HI (match_operand:HI 1 general_operand)
   (match_operand:HI 2 general_operand)))]
   
   {
+if (GET_CODE (operands[1]) == SUBREG
+ REG_P (XEXP (operands[1], 0)))
+  operands[1] = force_reg (HImode, operands[1]);
 if (msp430x
  REG_P (operands[0])
  REG_P (operands[1])
  CONST_INT_P (operands[2]))
   emit_insn (gen_430x_shift_left (operands[0], operands[1], operands[2]));
 else
@@ -797,12 +814,15 @@
 (define_expand ashrhi3
   [(set (match_operand:HI  0 nonimmediate_operand)
(ashiftrt:HI (match_operand:HI 1 general_operand)
 (match_operand:HI 2 general_operand)))]
   
   {
+if (GET_CODE (operands[1]) == SUBREG
+ REG_P (XEXP (operands[1], 0)))
+  operands[1] = force_reg (HImode, operands[1]);
 if (msp430x
  REG_P (operands[0])
  REG_P (operands[1])
  CONST_INT_P (operands[2]))
 

rx: remove some asserts

[DJ Delorie]

Nick,

There is no need to assert these just to say not supported and gcc
may rarely generate addresses from valid code which trigger these
asserts.  Ok?

Index: gcc/config/rx/rx.c
===
--- gcc/config/rx/rx.c  (revision 225533)
+++ gcc/config/rx/rx.c  (working copy)
@@ -367,14 +367,12 @@ rx_mode_dependent_address_p (const_rtx a
 
case SYMBOL_REF:
case LABEL_REF:
  return true;
 
case MULT:
- gcc_assert (REG_P (XEXP (addr, 0)));
- gcc_assert (CONST_INT_P (XEXP (addr, 1)));
  /* REG+REG*SCALE is always mode dependent.  */
  return true;
 
default:
  /* Not recognized, so treat as mode dependent.  */
  return true;

[rl78] extend set1/clr1 operands

[DJ Delorie]

Minor tweak to allow more addressing modes.  Committed.

* config/rl78/rl78-real.md (andqi3_real): Expand operands for clr1.
(iorqi3_real): Likewise for set1.

Index: config/rl78/rl78-real.md
===
--- config/rl78/rl78-real.md(revision 226022)
+++ config/rl78/rl78-real.md(working copy)
@@ -191,13 +191,13 @@
  (zero_extend:HI (match_operand:QI 2 general_operand x]
   rl78_real_insns_ok ()  !TARGET_G10
   mulu\t%2
 )
 
 (define_insn *andqi3_real
-  [(set (match_operand:QI 0 rl78_nonimmediate_operand  
=Wsf,A,R,vWsa)
+  [(set (match_operand:QI 0 rl78_nonimmediate_operand  
=WsfWsaWhlWab,A,R,vWsa)
(and:QI (match_operand:QI 1 rl78_general_operand   %0,0,0,0)
(match_operand:QI 2 rl78_general_operand   
IBqi,iRvWabWhbWh1Whl,A,i)))
]
   rl78_real_insns_ok ()
   @
clr1\t%0.%B2
@@ -205,13 +205,13 @@
and\t%0, %2
and\t%0, %2
   [(set_attr update_Z *,update_Z,update_Z,update_Z)]
 )
 
 (define_insn *iorqi3_real
-  [(set (match_operand:QI 0 rl78_nonimmediate_operand  
=Wsf,A,R,vWsa)
+  [(set (match_operand:QI 0 rl78_nonimmediate_operand  
=WsfWsaWhlWab,A,R,vWsa)
(ior:QI (match_operand:QI 1 rl78_general_operand   %0,0,0,0)
(match_operand:QI 2 rl78_general_operand   
Ibqi,iRvWabWhbWh1Whl,A,i)))
]
   rl78_real_insns_ok ()
   @
set1\t%0.%B2

Re: [PATCH] S390: Support -mtune=native and -march=native.

[DJ Delorie]

 Sorry about that.  Does the attached Patch fix the problem?

Yup.  Thanks!

Re: [PATCH] S390: Support -mtune=native and -march=native.

[DJ Delorie]

 Version 2 of the patch to enable the configure options
 --with-arch=native and --with-tune=native.

This patch broke cross-compiling with --target=s390-*

s390_host_detect_local_cpu is only defined if the --host is s390-*

but EXTRA_SPEC_FUNCTIONS refers to it when --target is s390-*

s390: larl for Simode on 64-bit

[DJ Delorie]

Is there any reason that LARL can't be used to load a 32-bit symbolic
value, in 64-bit mode?  On TPF (64-bit) the app has the option of
being loaded in the first 4Gb so that all symbols are also valid
32-bit addresses, for backward compatibility.  (and if not, the linker
would complain)

Index: s390.md
===
--- s390.md (revision 225579)
+++ s390.md (working copy)
@@ -1845,13 +1845,13 @@
 emit_symbolic_move (operands);
 })
 
 (define_insn *movsi_larl
   [(set (match_operand:SI 0 register_operand =d)
 (match_operand:SI 1 larl_operand X))]
-  !TARGET_64BIT  TARGET_CPU_ZARCH
+  TARGET_CPU_ZARCH
 !FP_REG_P (operands[0])
   larl\t%0,%1
[(set_attr op_type RIL)
 (set_attr typelarl)
 (set_attr z10prop z10_fwd_A1)])
 

Re: s390: larl for Simode on 64-bit

[DJ Delorie]

In the TPF case, the software has to explicitly mark such pointers as
SImode (such things happen only when structures that contain addresses
can't change size, for backwards compatibility reasons[1]):

int * __attribute__((mode(SImode))) ptr;

  ptr = some_var;

so I wouldn't consider this the default case for those apps, just
*a* case that needs to be handled well enough, and the user is
already telling the compiler that they assume those addresses are
32-bit (that either the whole app, or at least the part with that
object, will be linked below 4Gb).

The majority of the addresses are handled as 64-bit.


[1] /me refrains from commenting on the worth of such practices, just
that they exist and need to be (and have been) supported.

Re: s390: larl for Simode on 64-bit

[DJ Delorie]

 So in effect, we have two pointer sizes, 64 being the default, but
 we can also get a 32 bit pointer via the syntax above?  Wow, I'm
 surprised that works.

Yup, been that way for many years.

 And the only time we'd be able to use larl is a dereference of a
 pointer declared with the syntax above.  Right

larl would be used to load the address of an object to *initialize*
such a pointer, but yes.  Regular pointers still use larl but as a
DImode operation.  I.e. larl will always load a 64-bit value into a
register, even if gcc will only use the 32 LSBs.

 OK for the trunk with a simple testcase.  I think you can just scan
 the assembler output for the larl instruction.

Will do, but it's part of a bigger patch.  I just wanted to make sure
there wasn't some side-effect of larl that precluded this use.

Re: rl78 vs cse vs memory_address_addr_space

[DJ Delorie]

Given a test case like this:

typedef struct {
   unsigned char no0 :1;
   unsigned char no1 :1;
   unsigned char no2 :1;
   unsigned char no3 :1;
   unsigned char no4 :1;
   unsigned char no5 :1;
   unsigned char no6 :1;
   unsigned char no7 :1;
} __BITS8;
#define SFR0_bit (*(volatile union __BITS9 *)0x0)
#define SFREN SFR0_bit.no4

foo() {
   SFREN = 1U;
   SFREN = 0U;
}


(i.e. any code that sets/clears one bit in a volatile memory-mapped
area, which the rl78 has instructions for)

Before:

(insn 5 2 7 2 (set (reg/f:HI 43)
(const_int 240 [0xf0])) test.c:24 7 {*movhi_virt}
 (nil))
(insn 7 5 8 2 (set (reg:QI 45 [ MEM[(volatile union un_per0 *)240B].BIT.no4 ])
(mem/v/j:QI (reg/f:HI 43) [0 MEM[(volatile union un_per0 
*)240B].BIT.no4+0 S1 A16])) test.c:24 5 {movqi_virt}
 (nil))
(insn 8 7 9 2 (set (reg:QI 46)
(ior:QI (reg:QI 45 [ MEM[(volatile union un_per0 *)240B].BIT.no4 ])
(const_int 16 [0x10]))) test.c:24 19 {*iorqi3_virt}
 (expr_list:REG_DEAD (reg:QI 45 [ MEM[(volatile union un_per0 
*)240B].BIT.no4 ])
(nil)))
(insn 9 8 12 2 (set (mem/v/j:QI (reg/f:HI 43) [0 MEM[(volatile union un_per0 
*)240B].BIT.no4+0 S1 A16])
(reg:QI 46)) test.c:24 5 {movqi_virt}
 (expr_list:REG_DEAD (reg:QI 46)
(nil)))
(insn 12 9 13 2 (set (reg:QI 49 [ MEM[(volatile union un_per0 *)240B].BIT.no4 ])
(mem/v/j:QI (reg/f:HI 43) [0 MEM[(volatile union un_per0 
*)240B].BIT.no4+0 S1 A16])) test.c:26 5 {movqi_virt}
 (nil))
(insn 13 12 14 2 (set (reg:QI 50)
(and:QI (reg:QI 49 [ MEM[(volatile union un_per0 *)240B].BIT.no4 ])
(const_int -17 [0xffef]))) test.c:26 18 {*andqi3_virt}
 (expr_list:REG_DEAD (reg:QI 49 [ MEM[(volatile union un_per0 
*)240B].BIT.no4 ])
(nil)))
(insn 14 13 0 2 (set (mem/v/j:QI (reg/f:HI 43) [0 MEM[(volatile union un_per0 
*)240B].BIT.no4+0 S1 A16])
(reg:QI 50)) test.c:26 5 {movqi_virt}
 (expr_list:REG_DEAD (reg:QI 50)
(expr_list:REG_DEAD (reg/f:HI 43)
(nil

Combine gets as far as this:

Trying 5 - 9:
Failed to match this instruction:
(parallel [
(set (mem/v/j:QI (const_int 240 [0xf0]) [0 MEM[(volatile union un_per0 
*)240B].BIT.no4+0 S1 A16])
(ior:QI (mem/v/j:QI (const_int 240 [0xf0]) [0 MEM[(volatile union 
un_per0 *)240B].BIT.no4+0 S1 A16])
(const_int 16 [0x10])))
(set (reg/f:HI 43)
(const_int 240 [0xf0]))
])

(the set is left behind because it's used for the second assignment)

Both of those insns in the parallel are valid rl78 insns.  I tried
adding that parallel as a define-and-split but combine doesn't split
it at the point where it inserts it, so it doesn't work right.  If it
reduced those four instructions to the two in the parallel, but
without the parallel, it would probably work too.

We end up with code like this:

movwr8, #240 ; 5*movhi_real/4   [length 
= 4]
movwax, r8   ; 19   *movhi_real/5   [length 
= 4]
movwhl, ax   ; 21   *movhi_real/6   [length 
= 4]
set1[hl].4   ; 9*iorqi3_real/1  [length 
= 4]
clr1[hl].4   ; 14   *andqi3_real/1  [length 
= 4]

but what we want is this:

set1!240.4   ; 9*iorqi3_real/1  [length 
= 4]
clr1!240.4   ; 14   *andqi3_real/1  [length 
= 4]

( !240 means (mem (const_int 240)) )

(if there's only one such operation in a function, it combines
properly, likely because the address is not needed after the insn it
can combine, unlike the parallel above)

The common addresses are separated at least before lowering to RTL; as the 
initial
expansion has:

;; MEM[(volatile union un_per0 *)240B].BIT.no4 ={v} 1;

(insn 5 4 7 (set (reg/f:HI 43)
(const_int 240 [0xf0])) test.c:24 -1
 (nil))

(insn 7 5 8 (set (reg:QI 45)
(mem/v/j:QI (reg/f:HI 43) [0 MEM[(volatile union un_per0 
*)240B].BIT.no4+0 S1 A16])) test.c:24 -1
 (nil))

(insn 8 7 9 (set (reg:QI 46)
(ior:QI (reg:QI 45)
(const_int 16 [0x10]))) test.c:24 -1
 (nil))

(insn 9 8 0 (set (mem/v/j:QI (reg/f:HI 43) [0 MEM[(volatile union un_per0 
*)240B].BIT.no4+0 S1 A16])
(reg:QI 46)) test.c:24 -1
 (nil))


Yes, I know gcc doesn't like combining volatile accesses into one
insn, but the rl78 backend (my copy at least) has predicates that
allow it, because it's safe on rl78.

Also, if I take out the volatile yet put some sort of barrier (like
a volatile asm) between the two assignments, it still fails, in the
same manner.

Re: rl78 vs cse vs memory_address_addr_space

[DJ Delorie]

 Did you try just a define_split instead?  Ugly, but it should work I think.

It doesn't seem to be able to match a define_split :-(

Re: [s390] Revert TPF C++ library changes

[DJ Delorie]

 Ah, then approved.

Thanks, committed.

Re: update gthr-tpf.h

[DJ Delorie]

Ping?
https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00149.html

 This patch updates gthr-tpf.h to the current gthr.h API and TPF API.  Ok?
 
   * gthr-tpf.h (__GTHREADS_CXX0X): Define.
   (__gthread_t): Define.
   (__gthread_cond_t): Define.
   (__gthread_time_t): Define.
   (__GTHREAD_HAS_COND): Define.
   (__GTHREAD_COND_INIT): Define.
 
   (__gthread_active_p): Check __tpf_pthread_active().
   (__gthread_mutex_lock): Remove unneeded conditional.
   (__gthread_mutex_trylock): Likewise.
   (__gthread_recursive_mutex_lock): Likewise.
   (__gthread_recursive_mutex_trylock): Likewise.
   (__gthread_recursive_mutex_unlock): Likewise.
   (__gthread_recursive_mutex_init_function): Likewise.
 
   (__gthread_join): New.
   (__gthread_detach): New.
   (__gthread_equal): New.
   (__gthread_self): New.
   (__gthread_yield): New.
   (__gthread_mutex_timedlock): New.
   (__gthread_recursive_mutex_timedlock): New.
   (__gthread_cond_broadcast): New.
   (__gthread_cond_signal): New.
   (__gthread_cond_wait): New.
   (__gthread_cond_wait_recursive): New.
   (__gthread_cond_timedwait): New.
   (__gthread_cond_timedwait_recursive): New.
   (__gthread_cond_destroy): New.

rl78 vs cse vs memory_address_addr_space

[DJ Delorie]

In this bit of code in explow.c:

  /* By passing constant addresses through registers
 we get a chance to cse them.  */
  if (! cse_not_expected  CONSTANT_P (x)  CONSTANT_ADDRESS_P (x))
x = force_reg (address_mode, x);

On the rl78 it results in code that's a bit too complex for later
passes to be optimized fully.  Is there any way to indicate that the
above force_reg() is bad for a particular target?

Re: [s390] Revert TPF C++ library changes

[DJ Delorie]

 But don't we need to support the older system (with 2 libstdc++s) and 
 the newer system (just one libstdc++)?  Which implies these changes need 
 to be conditional, right?

The CPP2 configuration was never shipped to TPF customers, so there's
no need to retain both ways.

Re: pr66345.c size_t assumption bug

[DJ Delorie]

 OK.

Thanks, committed.

dwarf DW_AT_decl_name: system headers vs source files?

[DJ Delorie]

Consider:

# 1 dj.c
# 1 dj.h 1 3
int dj(int x);
# 2 dj.c 2

int dj(int x)
{
}

If you compile with -g and look at the dwarf output, you see:

 12d: Abbrev Number: 2 (DW_TAG_subprogram)
2e   DW_AT_external: 1
2e   DW_AT_name: dj
31   DW_AT_decl_file   : 2
32   DW_AT_decl_line   : 1

 The File Name Table:
  Entry Dir TimeSizeName
  1 0   0   0   dj.c
  2 0   0   0   dj.h


Note that the DW_AT_decl_file refers to dj.h and not dj.c.  If you
remove the 3 from the '# 1 dj.h 1 3' line, the DW_AT_decl_file
instead refers to dj.c.  It's been this way for many releases.

Is this intentional?

If so, what is the rationalization for it?

Re: [PATCH] toplevel: fixes for in-tree libiconv

[DJ Delorie]

 Thanks.  I don't have write access, could a toplevel maintainer please
 commit?

Which repos do you not have access to?  Also, did you address Jeff's
comment?

 How was this patch tested?  I don't see anything glaringly wrong, but
 stranger things have happened.
 
 I think just a bootstrap check is fine here (rather than a bootstrap +
 regression test).  If you could bootstrap with and without an in-tree
 libiconv it'd be appreciated.
 
 Jeff

Re: [PATCH] toplevel: fixes for in-tree libiconv

[DJ Delorie]

 This is the first in a series of patches to make a build with an in-tree
 GNU libiconv work as designed.
 
 This patch fixes dependencies for parallel make, and avoids failures
 with make targets not supported by GNU libiconv.

This is OK.  Thanks!

Re: [lto] intN follow-up patch

[DJ Delorie]

Thanks!  Committed.

[lto] intN follow-up patch

[DJ Delorie]

This was missed in the big intN patch set I did last year; it only
shows up if you have a target with an N-bit type that isn't also used
for a pointer type but is used for unwinding (which is a change I also
have pending, hence I noticed ;).  Tested on x86-64 and msp430 (with
the pending patch) with no regressions.  Ok?

* lto-lang.c (lto_type_for_size): Include intN types.
(lto_type_for_mode): Likewise.

Index: gcc/lto/lto-lang.c
===
--- gcc/lto/lto-lang.c  (revision 224364)
+++ gcc/lto/lto-lang.c  (working copy)
@@ -827,12 +827,14 @@ lto_post_options (const char **pfilename
 /* Return an integer type with PRECISION bits of precision,
that is unsigned if UNSIGNEDP is nonzero, otherwise signed.  */
 
 static tree
 lto_type_for_size (unsigned precision, int unsignedp)
 {
+  int i;
+
   if (precision == TYPE_PRECISION (integer_type_node))
 return unsignedp ? unsigned_type_node : integer_type_node;
 
   if (precision == TYPE_PRECISION (signed_char_type_node))
 return unsignedp ? unsigned_char_type_node : signed_char_type_node;
 
@@ -844,12 +846,18 @@ lto_type_for_size (unsigned precision, i
 
   if (precision == TYPE_PRECISION (long_long_integer_type_node))
 return unsignedp
   ? long_long_unsigned_type_node
   : long_long_integer_type_node;
 
+  for (i = 0; i  NUM_INT_N_ENTS; i ++)
+if (int_n_enabled_p[i]
+precision == int_n_data[i].bitsize)
+  return (unsignedp ? int_n_trees[i].unsigned_type
+ : int_n_trees[i].signed_type);
+
   if (precision = TYPE_PRECISION (intQI_type_node))
 return unsignedp ? unsigned_intQI_type_node : intQI_type_node;
 
   if (precision = TYPE_PRECISION (intHI_type_node))
 return unsignedp ? unsigned_intHI_type_node : intHI_type_node;
 
@@ -873,12 +881,13 @@ lto_type_for_size (unsigned precision, i
then UNSIGNEDP selects between saturating and nonsaturating types.  */
 
 static tree
 lto_type_for_mode (machine_mode mode, int unsigned_p)
 {
   tree t;
+  int i;
 
   if (mode == TYPE_MODE (integer_type_node))
 return unsigned_p ? unsigned_type_node : integer_type_node;
 
   if (mode == TYPE_MODE (signed_char_type_node))
 return unsigned_p ? unsigned_char_type_node : signed_char_type_node;
@@ -889,12 +898,18 @@ lto_type_for_mode (machine_mode mode, in
   if (mode == TYPE_MODE (long_integer_type_node))
 return unsigned_p ? long_unsigned_type_node : long_integer_type_node;
 
   if (mode == TYPE_MODE (long_long_integer_type_node))
 return unsigned_p ? long_long_unsigned_type_node : 
long_long_integer_type_node;
 
+  for (i = 0; i  NUM_INT_N_ENTS; i ++)
+if (int_n_enabled_p[i]
+mode == int_n_data[i].m)
+  return (unsigned_p ? int_n_trees[i].unsigned_type
+ : int_n_trees[i].signed_type);
+
   if (mode == QImode)
 return unsigned_p ? unsigned_intQI_type_node : intQI_type_node;
 
   if (mode == HImode)
 return unsigned_p ? unsigned_intHI_type_node : intHI_type_node;
 

Re: RFA: RL78: With -mes0 put read only data in the .frodata section

[DJ Delorie]

Ok.  Thanks!

pr66345.c size_t assumption bug

[DJ Delorie]

The testcase for pr 66345 assumes size_t is unsigned long instead of
using the real type, which causes failures on some 16-bit targets.
Ok?

Also, I note that some tests check for __SIZE_TYPE__ as I do below,
and others use it unconditionally as a replacement for size_t.  Is
there a convention?

* gcc.dg/torture/pr66345.c: Fix assumption about size_t type.
 
 2015-06-08  Tom de Vries  t...@codesourcery.com
Index: gcc.dg/torture/pr66345.c
===
--- gcc.dg/torture/pr66345.c(revision 224260)
+++ gcc.dg/torture/pr66345.c(working copy)
@@ -1,9 +1,15 @@
 /* { dg-do compile } */
 
-extern int snprintf (char *, unsigned long, const char *, ...);
+#ifdef __SIZE_TYPE__
+typedef __SIZE_TYPE__ size_t;
+#else
+typedef unsigned int size_t;
+#endif
+
+extern int snprintf (char *, size_t, const char *, ...);
 const char a[] = ;
 int b;
 void
 get_bar ()
 {
   snprintf (0, 0, %s, a[b]);

Re: [PATCH : RL78] Disable interrupts during hardware multiplication routines

[DJ Delorie]

Have you compared the latency of the multiply instructions to the
overhead of saving those registers in the interrupt handler?  What
about the case where performance is priority, and the developer knows
that the interrupt handlers don't use the multiply registers?

Also, your code doesn't properly handle the case where the interrupts
are already disabled when those functions are called.  It would
re-enable interrupts before the main code was prepared for it.

[s390] Revert TPF C++ library changes

[DJ Delorie]

IBM made changes to no longer require 2 versions of libstdc++, so this
patch changes things back to the previous (compatible) way.

Also, TPF debuggers don't support discriminators, despite what GAS
supports, so disable them.

Ok?

* config/s390/tpf.h (LIBSTDCXX): Change to CPP1.
(LIB_SPEC): Add.
(SUPPORTS_DISCRIMINATOR): Define.

Index: config/s390/tpf.h
===
--- config/s390/tpf.h   (revision 224174)
+++ config/s390/tpf.h   (working copy)
@@ -91,12 +91,16 @@ along with GCC; see the file COPYING3.  
 #define CPLUSPLUS_CPP_SPEC -D_GNU_SOURCE %(cpp)
 
 #undef ASM_SPEC
 #define ASM_SPEC %{m31m64}%{mesamzarch}%{march=*} \
   -alshd=%b.lst
 
+#undef LIB_SPEC
+#define LIB_SPEC -lCTIS -lCISO -lCLBM -lCTAL -lCFVS -lCTBX -lCTXO \
+  -lCJ00 -lCTDF -lCOMX -lCOMS -lCTHD -lCTAD -lTPFSTUB
+
 #define ENTRY_SPEC %{mmain:-entry=_start} \
 %{!mmain:-entry=0}
 
 /* All linking is done shared on TPF-OS.  */
 /* FIXME: When binutils patch for new emulation is committed
then change emulation to elf64_s390_tpf.  */
@@ -107,12 +111,15 @@ along with GCC; see the file COPYING3.  
%{shared: -shared} \
%{!shared:-shared} \
%(entry_spec)
 
 /* IBM copies these libraries over with these names.  */
 #define MATH_LIBRARY CLBM
-#define LIBSTDCXX CPP2
+#define LIBSTDCXX CPP1
 
 #undef TARGET_LIBC_HAS_FUNCTION
 #define TARGET_LIBC_HAS_FUNCTION gnu_libc_has_function
 
+/* GAS supports it, but the debuggers don't, so avoid it.  */
+#define SUPPORTS_DISCRIMINATOR 0
+
 #endif /* ! _TPF_H */

[msp430] support sym+int and sym-sym

[DJ Delorie]

Because sizeof(void*) is 4 but POINTER_SIZE is 3, we have to handle
some things manually.  This is yet another one.  Committed.

* config/msp430/msp430.c (msp430_asm_integer): Support addition
and subtraction too.

Index: config/msp430/msp430.c
===
--- config/msp430/msp430.c  (revision 224181)
+++ config/msp430/msp430.c  (working copy)
@@ -973,13 +973,14 @@ msp430_asm_integer (rtx x, unsigned int 
   if (size == 3  GET_MODE (x) == PSImode)
 size = 4;
 
   switch (size)
 {
 case 4:
-  if (c == SYMBOL_REF || c == CONST || c == LABEL_REF || c == CONST_INT)
+  if (c == SYMBOL_REF || c == CONST || c == LABEL_REF || c == CONST_INT
+ || c == PLUS || c == MINUS)
{
  fprintf (asm_out_file, \t.long\t);
  output_addr_const (asm_out_file, x);
  fputc ('\n', asm_out_file);
  return true;
}

pr64252.c: fix sizeof(int) assumption

[DJ Delorie]

On targets with 2 byte int the vectors are 16 values long, which
breaks the index count in __builtin_shuffle() using more than one
input vector.  Ok?

* gcc.dg/pr64252.c: Fix assumption about sizeof(int).

 2015-06-05  Thomas Koenig  tkoe...@gcc.gnu.org
Index: gcc.dg/pr64252.c
===
--- gcc.dg/pr64252.c(revision 224181)
+++ gcc.dg/pr64252.c(working copy)
@@ -1,11 +1,11 @@
 /* PR target/64252 */
 /* { dg-do run } */
 /* { dg-options -O2 } */
 
-typedef unsigned int V __attribute__((vector_size (32)));
+typedef unsigned int V __attribute__((vector_size (sizeof(unsigned long) * 
8)));
 
 __attribute__((noinline, noclone)) void
 foo (V *a, V *b, V *c, V *d, V *e)
 {
   V t = __builtin_shuffle (*a, *b, *c);
   V v = __builtin_shuffle (t, (V) { ~0U, ~0U, ~0U, ~0U, ~0U, ~0U, ~0U, ~0U }, 
(V) { 0, 1, 8, 3, 4, 5, 9, 7 });

Re: pr64252.c: fix sizeof(int) assumption

[DJ Delorie]

Sorry, I meant unsigned int.

[msp430] special case sym-SI moves

[DJ Delorie]

Symbols are normally PSImode, and the MSP430 has PSImode registers and
PSImode moves to reg/mem.  But sometimes gcc uses an SImode move
instead, if the result will later be used in SImode (as in getP() in
gcc/testsuite/gcc.dg/torture/pr65077.c).  Committed.

* config/msp430/msp430.md (movsi_s): New.  Special case for
storing a 20-bit symbol into a 32-bit register.
* config/msp430/msp430.c (msp430_subreg): Add support for it.
* config/msp430/predicates.md (msp430_symbol_operand): New.

Index: gcc/config/msp430/predicates.md
===
--- gcc/config/msp430/predicates.md (revision 224143)
+++ gcc/config/msp430/predicates.md (working copy)
@@ -79,6 +79,10 @@
 
 ; TRUE for constants which are bit positions for zero_extract
 (define_predicate msp430_bitpos
   (and (match_code const_int)
(match_test (   INTVAL (op) = 0
  INTVAL (op) = 15 
+
+(define_predicate msp430_symbol_operand
+  (match_code symbol_ref)
+)
Index: gcc/config/msp430/msp430.md
===
--- gcc/config/msp430/msp430.md (revision 224143)
+++ gcc/config/msp430/msp430.md (working copy)
@@ -211,12 +211,25 @@
   [(set (match_operand:SI 0 nonimmediate_operand)
(match_operand:SI 1 general_operand))]
   
   
   )
 
+(define_insn_and_split movsi_s
+  [(set (match_operand:SI 0 nonimmediate_operand =rm)
+   (subreg:SI (match_operand:PSI 1 msp430_symbol_operand i) 0))]
+  
+  
+  reload_completed
+  [(set (match_operand:HI 2 nonimmediate_operand)
+   (match_operand:HI 4 general_operand))
+   (set (match_operand:HI 3 nonimmediate_operand)
+   (match_operand:HI 5 general_operand))]
+  msp430_split_movsi (operands);
+  )
+
 (define_insn_and_split movsi_x
   [(set (match_operand:SI 0 nonimmediate_operand =rm)
(match_operand:SI 1 general_operand rmi))]
   
   #
   reload_completed
Index: gcc/config/msp430/msp430.c
===
--- gcc/config/msp430/msp430.c  (revision 224143)
+++ gcc/config/msp430/msp430.c  (working copy)
@@ -2371,12 +2371,19 @@ msp430_subreg (machine_mode mode, rtx r,
rv = gen_rtx_SUBREG (mode, ireg, byte);
   else
rv = simplify_gen_subreg (mode, ireg, imode, byte);
 }
   else if (GET_CODE (r) == MEM)
 rv = adjust_address (r, mode, byte);
+  else if (GET_CODE (r) == SYMBOL_REF
+   (byte == 0 || byte == 2)
+   mode == HImode)
+{
+  rv = gen_rtx_ZERO_EXTRACT (HImode, r, GEN_INT (16), GEN_INT (8*byte));
+  rv = gen_rtx_CONST (HImode, r);
+}
   else
 rv = simplify_gen_subreg (mode, r, omode, byte);
 
   if (!rv)
 gcc_unreachable ();
 

update gthr-tpf.h

[DJ Delorie]

This patch updates gthr-tpf.h to the current gthr.h API and TPF API.  Ok?

* gthr-tpf.h (__GTHREADS_CXX0X): Define.
(__gthread_t): Define.
(__gthread_cond_t): Define.
(__gthread_time_t): Define.
(__GTHREAD_HAS_COND): Define.
(__GTHREAD_COND_INIT): Define.

(__gthread_active_p): Check __tpf_pthread_active().
(__gthread_mutex_lock): Remove unneeded conditional.
(__gthread_mutex_trylock): Likewise.
(__gthread_recursive_mutex_lock): Likewise.
(__gthread_recursive_mutex_trylock): Likewise.
(__gthread_recursive_mutex_unlock): Likewise.
(__gthread_recursive_mutex_init_function): Likewise.

(__gthread_join): New.
(__gthread_detach): New.
(__gthread_equal): New.
(__gthread_self): New.
(__gthread_yield): New.
(__gthread_mutex_timedlock): New.
(__gthread_recursive_mutex_timedlock): New.
(__gthread_cond_broadcast): New.
(__gthread_cond_signal): New.
(__gthread_cond_wait): New.
(__gthread_cond_wait_recursive): New.
(__gthread_cond_timedwait): New.
(__gthread_cond_timedwait_recursive): New.
(__gthread_cond_destroy): New.

Index: libgcc/config/s390/gthr-tpf.h
===
--- libgcc/config/s390/gthr-tpf.h   (revision 224011)
+++ libgcc/config/s390/gthr-tpf.h   (working copy)
@@ -35,6 +35,8 @@
Easy, since the interface is just one-to-one mapping.  */
 
 #define __GTHREADS 1
+/* To enable the c++0x thread library.  */
+#define __GTHREADS_CXX0X 1
 
 /* Some implementations of pthread.h require this to be defined.  */
 #ifndef _REENTRANT
@@ -44,11 +46,17 @@
 #include pthread.h
 #include unistd.h
 
+typedef pthread_t __gthread_t;
 typedef pthread_key_t __gthread_key_t;
 typedef pthread_once_t __gthread_once_t;
 typedef pthread_mutex_t __gthread_mutex_t;
 typedef pthread_mutex_t __gthread_recursive_mutex_t;
+typedef pthread_cond_t __gthread_cond_t; 
+typedef struct timespec __gthread_time_t; 
 
+#define __GTHREAD_HAS_COND 1
+#define __GTHREAD_COND_INIT PTHREAD_COND_INITIALIZER
+
 #if defined(PTHREAD_RECURSIVE_MUTEX_INITIALIZER)
 #define __GTHREAD_RECURSIVE_MUTEX_INIT PTHREAD_RECURSIVE_MUTEX_INITIALIZER
 #elif defined(PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP)
@@ -80,9 +88,15 @@
 __gthrw(pthread_getspecific)
 __gthrw(pthread_setspecific)
 __gthrw(pthread_create)
+__gthrw(pthread_join)
+__gthrw(pthread_detach)
+__gthrw(pthread_equal)
+__gthrw(pthread_self)
+__gthrw(sched_yield)
 
 __gthrw(pthread_mutex_lock)
 __gthrw(pthread_mutex_trylock)
+__gthrw(pthread_mutex_timedlock) 
 __gthrw(pthread_mutex_unlock)
 __gthrw(pthread_mutexattr_init)
 __gthrw(pthread_mutexattr_settype)
@@ -90,31 +104,81 @@
 __gthrw(pthread_mutex_init)
 __gthrw(pthread_mutex_destroy)
 
+__gthrw(pthread_cond_broadcast)
+__gthrw(pthread_cond_signal)
+__gthrw(pthread_cond_wait)
+__gthrw(pthread_cond_timedwait)
+__gthrw(pthread_cond_destroy)
+
+
 static inline int
 __gthread_active_p (void)
 {
-  return 1;
+  return __tpf_pthread_active ();
 }
 
 static inline int
-__gthread_once (__gthread_once_t *__once, void (*__func) (void))
+__gthread_create (__gthread_t *__threadid, void *(*__func) (void*),
+ void *__args)
 {
+  return __gthrw_(pthread_create) (__threadid, NULL, __func, __args);
+}
+
+static inline int
+__gthread_join (__gthread_t __threadid, void **__value_ptr)
+{
   if (__tpf_pthread_active ())
-return __gthrw_(pthread_once) (__once, __func);
+return __gthrw_(pthread_join) (__threadid, __value_ptr);
   else
 return -1;
 }
 
 static inline int
-__gthread_key_create (__gthread_key_t *__key, void (*__dtor) (void *))
+__gthread_detach (__gthread_t __threadid)
 {
   if (__tpf_pthread_active ())
-return __gthrw_(pthread_key_create) (__key, __dtor);
+return __gthrw_(pthread_detach) (__threadid);
   else
 return -1;
 }
 
 static inline int
+__gthread_equal (__gthread_t __t1, __gthread_t __t2)
+{
+  if (__tpf_pthread_active ())
+return __gthrw_(pthread_equal) (__t1, __t2);
+  else
+return -1;
+}
+
+static inline __gthread_t
+__gthread_self (void)
+{
+  return __gthrw_(pthread_self) ();
+}
+
+static inline int
+__gthread_yield (void)
+{
+  return __gthrw_(sched_yield) ();
+}
+
+static inline int
+__gthread_once (__gthread_once_t *__once, void (*__func) (void))
+{
+  if (__tpf_pthread_active ())
+return __gthrw_(pthread_once) (__once, __func);
+  else
+return -1;
+}
+
+static inline int
+__gthread_key_create (__gthread_key_t *__key, void (*__dtor) (void *))
+{
+  return __gthrw_(pthread_key_create) (__key, __dtor);
+}
+
+static inline int
 __gthread_key_delete (__gthread_key_t __key)
 {
   if (__tpf_pthread_active ())
@@ -153,22 +217,23 @@
 static inline int
 __gthread_mutex_lock (__gthread_mutex_t *__mutex)
 {
-  if (__tpf_pthread_active ())
-return __gthrw_(pthread_mutex_lock) 

Re: RFA: RL78:

[DJ Delorie]

Ok.  Thanks!

Re: [PATCH 14/16] gcc: Add CTIMER_PUSH/POP to gcc's copy of libiberty

[DJ Delorie]

This is the same patch as 09/16.  There is only one libiberty master,
controlled by gcc, it is not neccessary to submit separate patches for
each copy of it.

The convention is: Any libiberty patch approved by gcc maintainers is
auto-approved for the other repos.

Re: [PATCH 08/16] libiberty.h: Provide a CLEAR_VAR macro

[DJ Delorie]

 +/* Fill an lvalue with zero bits.  */
 +#define CLEAR_VAR(S) \
 +  do { memset ((S), 0, sizeof (S)); } while (0)

Hmmm... I don't see the point in this.  The macro is almost as long as
a bare memset() would be, and replaces a well-known function with
something unknown outside this project.  It neither hides a bug in an
OS nor provides a common way to handle a difficult task across
platforms.

You also do NOT want to use memset to zero out a C++ structure that
contains more than just plain old data - you could easily corrupt
the structure's hidden data.

Also, pedantically speaking, all bits zero is not guaranteed to be
the same as float 0.0, double 0.0, or pointer (void *)0.

Re: [PATCH 09/16] libiberty.h: Provide CTIMER_PUSH/POP

[DJ Delorie]

libiberty is not an API to gcc, it is a portability library.  If GCC
is exporting a timer, GCC's headers should have the interface in it.

Re: [PATCH 08/16] libiberty.h: Provide a CLEAR_VAR macro

[DJ Delorie]

 FWIW I'm not in love with the name of the macro, but I find it useful.
 In the initial version of patches 10 and 12 (state purging within gas
 and ld subdirs) I didn't have this macro, and had about 30 memset
 invocations.

Another option is to save the state as it was initialized, and restore
it as needed.  That way, structures that don't start off all zero will
get reset properly.  In this case, you're just talking about a
simple assignment:

  saved_vars = my_vars;
  . . .
  my_vars = saved_vars;

In addition to simplicity, the compiler will check the types for you
to make sure you don't goof up.

 Are you thinking of vtables here, public vs private, or of
 inheritance?

Yes.

  FWIW I'm only using this from within binutils, which AFAIK is pure
 C (I'm new to binutils).

Ah, but you're putting the macro in libiberty, which *is* used by C++
files.

  Also, pedantically speaking, all bits zero is not guaranteed to be
  the same as float 0.0, double 0.0, or pointer (void *)0.
 
 The purpose of the code is to restore the state back to what it was when
 the library was first loaded;

That's not what you're doing, what you're doing is setting it to all
zero, even if the data was non-zero at the start.

 Also, if this isn't so much a libiberty thing (not being an
 OS-compatibility thing), is there a place to put it in internal
 support headers?  (in the sense that this would be an implementation
 detail, used by both gas and ld)

bfd.h might be an option, since it's common to most binutils programs.

Re: [expmed] Avoid clobbering a yet-to-be-used base/index register.

[DJ Delorie]

  * expmed.c (extract_bit_field_1): Avoid clobbering a
  yet-to-be-used base/index register.
 OK.
 jeff

Thanks! committed.

s390: SImode pointers vs LR

[DJ Delorie]

In config/s390/s390.c we accept addresses that are SImode:

  if (!REG_P (base)
  || (GET_MODE (base) != SImode
   GET_MODE (base) != Pmode))
return false;

However, there doesn't seem to be anything in the s390's opcodes that
masks the top half of address registers in 64-bit mode, the SImode
convention seems to just be a convention for addresses in the first
4Gb.

So... what happens if gcc uses a subreg to load the lower half of a
register (via LR), leaving the upper half with random bits in it, then
uses that register as an address?  I could see no code that checked
for this, and I have a fairly large and ungainly test case that says
it breaks :-(

My local solution was to just disallow SImode as an address in
s390_decompose_address, which forces gcc to do an explicit SI-DI
conversion to clear the upper bits, and it seems to work, but I wonder
if it's the ideal solution...

Re: [PATCH, v2] Fix bootstrap with in-tree ISL

[DJ Delorie]

A few minor nits...

Your patch includes many whitespace changes, which makes reviewing
your patch more difficult.  Please limit whitespace changes when
they're unrelated to the patch.

Assuming you've looked at the actual diffs for them, and see nothing
beyond changes related to your patch, it's unneecessary to include the
full patch for regenerated files like Makefile.in and configure.  (if
there *are* unrelated changes, you've done something wrong - likely
used the wrong version of the tools).  You'll still need to check in
these changes, of course, but we don't need to review them separately.

As for the patch itself...

Since none of the projects I see have autogen.sh anyway, I don't see
any impact on them from this patch, although that might change in the
future and I worry that developer's source trees will become cluttered
with fixed versions of files.  The GNU projects specify what
versions of auto* tools should be used.  It is not appropriate for a
developer to autogen with the OS's default tools and assume it's OK to
check those files in.  But as I said, this doesn't yet affect any of
the core projects (gcc, binutils+gdb, newlib).

I do worry about autogen.sh failing:

   module_srcdir=[+? module_srcdir (get module_srcdir) (get module)+]; 
 \
 + [ ! -f $$s/$$module_srcdir/configure ]  \
 + [ -f $$s/$$module_srcdir/autogen.sh ]  \
 + (cd $$s/$$module_srcdir/  $(SHELL) ./autogen.sh); \
   [+ IF no-config-site +]rm -f no-such-file || : ; \

There is no logic in here to abort the build process if, for some
reason, autogen.sh returns a nonzero exit code.  This is likely to
happen if, for example, the source tree is read-only, but could also
happen if there's a mismatch between autotools and the config files.
Note that properly signalling the error up through the subshell is
tricky, so don't assume you've got it right until you prove it through
testing ;-)

Re: fix pr65369.c testcase

[DJ Delorie]

Done.  Thanks!

[expmed] Avoid clobbering a yet-to-be-used base/index register.

[DJ Delorie]

20040625-1 fails on targets with pointers bigger than WORD_SIZE (rl78,
msp430/-mlarge) because the base register is clobbered, partially
rebuilt with the new value, then used as a base for the second part of
the calculation.  Ok?

* expmed.c (extract_bit_field_1): Avoid clobbering a
yet-to-be-used base/index register.

 
Index: expmed.c
===
--- expmed.c(revision 223850)
+++ expmed.c(working copy)
@@ -1613,12 +1613,17 @@ extract_bit_field_1 (rtx str_rtx, unsign
   unsigned int i;
   rtx_insn *last;
 
   if (target == 0 || !REG_P (target) || !valid_multiword_target_p (target))
target = gen_reg_rtx (mode);
 
+  /* In case we're about to clobber a base register or something 
+(see gcc.c-torture/execute/20040625-1.c).   */
+  if (reg_mentioned_p (target, str_rtx))
+   target = gen_reg_rtx (mode);
+
   /* Indicate for flow that the entire target reg is being set.  */
   emit_clobber (target);
 
   last = get_last_insn ();
   for (i = 0; i  nwords; i++)
{

fix pr65369.c testcase

[DJ Delorie]

Copied the way other tests get uint32_t.  Ok?

* gcc.c-torture/execute/pr65369.c: Don't assume int is 32 bits.

Index: gcc.c-torture/execute/pr65369.c
===
--- gcc.c-torture/execute/pr65369.c (revision 223737)
+++ gcc.c-torture/execute/pr65369.c (working copy)
@@ -1,7 +1,8 @@
 /* PR tree-optimization/65369 */
+#include stdint.h
 
 static const char data[] =
   12345678901234567890123456789012345678901234567890
   123456789012345678901234567890;
 
 __attribute__ ((noinline))
@@ -11,13 +12,13 @@ static void foo (const unsigned int *buf
 __builtin_abort ();
 }
 
 __attribute__ ((noinline))
 static void bar (const unsigned char *block)
 {
-  unsigned int buf[16];
+  uint32_t buf[16];
   __builtin_memcpy (buf +  0, block +  0, 4);
   __builtin_memcpy (buf +  1, block +  4, 4);
   __builtin_memcpy (buf +  2, block +  8, 4);
   __builtin_memcpy (buf +  3, block + 12, 4);
   __builtin_memcpy (buf +  4, block + 16, 4);
   __builtin_memcpy (buf +  5, block + 20, 4);

Re: [PATCH/libiberty] fix build of gdb/binutils with clang.

[DJ Delorie]

 If the other c file only includes libiberty.h and does not include the
 libiberty/config.h and

In general, such other c files should have their own config.h that
does the same test and has its own HAVE_DECL_ASPRINTF.

That way, the config.h matches the compiler options being used, and
not the compiler options libiberty's build used.

Re: RFA: RL78: Place zero-initialised data into the .bss section

[DJ Delorie]

   OK to apply ?

Ok but..

 +case SECCAT_TBSS:
 +  return default_select_section (decl, reloc, align);
 +
 +default:
 +  gcc_unreachable ();

Would it be better to just default: everything to
default_select_section, instead of enumerating everything we know
about today?

Re: Remove mode argument from gen_rtx_SET

[DJ Delorie]

 What I was confused about is that the first set isn't valid rtl.
 The SET_SRC and SET_DEST always have to have the same mode
 (or VOIDmode in the case of a CONST_INT, etc., where the mode
 is implicitly the same as the SET_DEST).  So wouldn't it have
 to be:
 
   (set (reg:SI 1)
(subreg:SI (reg:PSI 2)))
 
 or:
 
   (set (reg:PSI 1)
(subreg:PSI (reg:SI 2)))
 
 ?

If my memory doesn't match reality, I blame my memory.

I'd have to experiment a while to dig out the details, but the key
point is that a PSI in a reg is not stored the same as a PSI subreg of
an SI reg.  You have to keep that information across subregs or you
lose track of where the actual bits are.

Re: Remove mode argument from gen_rtx_SET

[DJ Delorie]

 ; This pattern is identical to the truncsipsi2 pattern except
 ; that it uses a SUBREG instead of a TRUNC.  It is needed in
 ; order to prevent reload from converting (set:SI (SUBREG:PSI (SI)))
 ; into (SET:PSI (PSI)).
 
 I'm not sure what that's supposed to mean (what's an SI set of a PSI
 subreg?), but I suspect removing the mode would lose information,
 so I left it alone.

MSP430 has 20-bit registers (PSImode-sized).  One register can hold an
HI or PSI sized value, but if you have an SI value it's stored as two
HI registers.

Thus, a PSImode value in a register is *not* just the 20 LSB of an
SImode value.  Also, a PSImode subset of an SI value is stored
different than a PSImode value on its own.

Thus, consider code like this:

(set (reg:SI 1)
 (subreg:PSI (reg:SI 2)))

(set (reg:PSI 1)
 (reg:PSI 2))

On most architectures, you'd say these do the same thing but on
MSP430 they don't.

Re: [RFA] libiberty/mkstemps.c: Include time.h if sys/time.h not available.

[DJ Delorie]

 * mkstemps.c: #include time.h if HAVE_TIME_H is defined
 but not HAVE_SYS_TIME_H.

Ok.

Re: RFA: RL78: Save the frame pointer if it is used.

[DJ Delorie]

   OK to apply ?

Ok, but...

 -  if (regno == FRAME_POINTER_REGNUM  frame_pointer_needed)
 +  if (regno == FRAME_POINTER_REGNUM
 +   (frame_pointer_needed || df_regs_ever_live_p (regno)))

Do we want regs_ever_live or regs_ever_written_to ?  I seem to recall
changing a port... mep perhaps... to only save registers that are
changed, not registers that are used but read-only.

Re: RFA: RL78: Add support for G13 and G14 multiply and divide

[DJ Delorie]

   OK to apply ?

Ok.

 gcc/ChangeLog
 2015-04-15  Nick Clifton  ni...@redhat.com
 
   * config/rl78/rl78-opts.h (enum rl78_mul_types): Add MUL_G14 and
   MUL_UNINIT.
   (enum rl78_cpu_type): New.
   * config/rl78/rl78-virt.md (attr valloc): Add divhi and divsi.
   (umulhi3_shift_virt): Remove m constraint from operand 1.
   (umulqihi3_virt): Likewise.
   * config/rl78/rl78.c (rl78_option_override): Add code to process
   -mcpu and -mmul options.
   (rl78_alloc_physical_registers): Add code to handle divhi and
   divsi valloc attributes.
   (set_origin): Likewise.
   * config/rl78/rl78.h (RL78_MUL_G14): Define.
   (TARGET_G10, TARGET_G13, TARGET_G14): Define.
   (TARGET_CPU_CPP_BUILTINS): Define __RL78_MUL_xxx__ and
   __RL78_Gxx__.
   (ASM_SPEC): Pass -mcpu on to assembler.
   * config/rl78/rl78.md (mulqi3): Add a clobber of AX.
   (mulqi3_rl78): Likewise.
   (mulhi3_g13): Likewise.
   (mulhi3): Generate the G13 or G14 versions of the insn directly.
   (mulsi3): Likewise.
   (mulhi3_g14): Add clobbers of AX and BC.
   (mulsi3_g14): Likewise.
   (mulsi3_g13): Likewise.
   (udivmodhi4, udivmodhi4_g14, udivmodsi4): New patterns.
   (udivmodsi4_g14, udivmodsi4_g13): New patterns.
   * config/rl78/rl78.opt (mmul): Initialise value to
   RL78_MUL_UNINIT.
   (mcpu): New option.
   (m13, m14, mrl78): New option aliases.
   * config/rl78/t-rl78 (MULTILIB_OPTIONS): Add mg13 and mg14.
   (MULTILIB_DIRNAMES): Add g13 and g14.
   * doc/invoke.texi: Document -mcpu and -mmul options.
 
 libgcc/ChangeLog
 2015-04-15  Nick Clifton  ni...@redhat.com
 
   * config/rl78/divmodhi.S: Add G14 and G13 versions of the __divhi3
   and __modhi3 functions.
   * config/rl78/divmodso.S: Add G14 and G13 versions of the
   __divsi3, __udivsi3, __modsi3 and __umodsi3 functions.

Re: RFA: RL78:

[DJ Delorie]

   OK to apply ?

Ok!

 2015-04-14  Nick Clifton  ni...@redhat.com
 
   * config/rl78/rl78.c (rl78_expand_prologue): Mark large stack
   decrement instruction as being frame related.
 (rl78_print_operand_1): Handle 'p' modifier to add +0 to HL
   based addresses.
   If zero extending a function address enclose the operation in
   %code(...).
 (rl78_preferred_reload_class): New function.
 (TARGET_PREFERRED_RELOAD_CLASS): Define.
 * config/rl78/rl78.md: Remove useless constraints in expanders.
 (mulqi3_rl78): Remove + qualifier on input-only operand 1.
 (mulhi3_rl78): Likewise.
 (mulhi3_g13): Likewise.
 (mulsi3_rl78): Likewise.
 (es_addr): Move to before the multiply patterns.

Double check tab-vs-space in the ChangeLog entry, though...

Re: [PATCH] Fix libbacktrace and libiberty tests fail on sanitized GCC due to wrong link options.

[DJ Delorie]

 Is this ok for trunk now?

Yes.

[rl78] fix 'p' test

[DJ Delorie]

Mis-applied patch, committed.

* config/rl78/rl78.c (rl78_print_operand_1): Move 'p' test to
correct clause.

Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c  (revision 221648)
+++ config/rl78/rl78.c  (working copy)
@@ -1641,20 +1641,20 @@ rl78_print_operand_1 (FILE * file, rtx o
GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
REGNO (XEXP (XEXP (op, 0), 0)) == 2)
{
  rl78_print_operand_1 (file, XEXP (XEXP (op, 0), 1), 'u');
  fprintf (file, [);
  rl78_print_operand_1 (file, XEXP (XEXP (op, 0), 0), 0);
- if (letter == 'p'  GET_CODE (XEXP (op, 0)) == REG)
-   fprintf (file, +0);
  fprintf (file, ]);
}
  else
{
  fprintf (file, [);
  rl78_print_operand_1 (file, XEXP (op, 0), letter);
+ if (letter == 'p'  GET_CODE (XEXP (op, 0)) == REG)
+   fprintf (file, +0);
  fprintf (file, ]);
}
}
   break;
 
 case REG:

[rl78] fix ICE with far operands to and/ior

[DJ Delorie]

Committed.

* config/rl78/rl78-virt.md (andqi3_virt): Allow far operands.
(iorqi3_virt): Likewise.

Index: config/rl78/rl78-virt.md
===
--- config/rl78/rl78-virt.md(revision 221505)
+++ config/rl78/rl78-virt.md(working copy)
@@ -128,23 +128,23 @@
   rl78_virt_insns_ok ()  !TARGET_G10
   v.mulu\t%0, %2
   [(set_attr valloc umul)]
 )
 
 (define_insn *andqi3_virt
-  [(set (match_operand:QI 0 rl78_nonfar_nonimm_operand =vm)
-   (and:QI (match_operand:QI 1 rl78_nonfar_operand vim)
+  [(set (match_operand:QI 0 rl78_nonimmediate_operand =vm)
+   (and:QI (match_operand:QI 1 rl78_general_operand vim)
(match_operand:QI 2 rl78_general_operand vim)))
]
   rl78_virt_insns_ok ()
   v.and\t%0, %1, %2
 )
 
 (define_insn *iorqi3_virt
-  [(set (match_operand:QI 0 rl78_nonfar_nonimm_operand =vm)
-   (ior:QI (match_operand:QI 1 rl78_nonfar_operand vim)
+  [(set (match_operand:QI 0 rl78_nonimmediate_operand =vm)
+   (ior:QI (match_operand:QI 1 rl78_general_operand vim)
(match_operand:QI 2 rl78_general_operand vim)))
]
   rl78_virt_insns_ok ()
   v.or\t%0, %1, %2
 )
 

Re: Newlib/Cygwin now under GIT

[DJ Delorie]

 This is a common problem.  I guess newlib/cygwin got the oldest set
 and, afaik, the GCC toplevel stuff is kind of the master.  It would
 be nice if we had some automatism in place to keep all former src
 repos in sync.

There was never any agreement on who the master was for toplevel
sources - no repo was willing to give up control to the other, so no
automatic mirroring was ever done, unlike the libiberty/include
mirror, where src agreed to let gcc be the master.

Also, for the record, I do not wish to, nor do I intend to, provide
any automated merging services for git repos.  I don't like git and
I'd rather not use it if I don't have to.

Re: RFA: RL78: Add muladdhi3 pattern

[DJ Delorie]

   The problem appears to be that GCC will create a multiply-plus-add
   instruction to access the table regardless of whether the backend
   supports such an instruction.  I could not work out where in the
   middle end this was occurring, so instead I created the patch below
   which contains a splitter to separate out the multiply and addition
   operations.

I've seen this before.  The root of the problem is in
expand_expr_real_1() where convert_to_mode() is called (around line
10262 in my tree) to change the address's mode from HImode to SImode,
but this happens *before* the address itself is legitimized (I think).
So we have an invalid address causing the problem, at a point were we
don't care if the address is valid or not.

Either the address must be legitimized before that point, or some
other conversion needs to be used.  Either way, I think adding a
pattern for this particular address is only hiding the problem, not
fixing it.

if (offset)
  {
machine_mode address_mode;
rtx offset_rtx = expand_expr (offset, NULL_RTX, VOIDmode,
  EXPAND_SUM);

gcc_assert (MEM_P (op0));

address_mode = get_address_mode (op0);
if (GET_MODE (offset_rtx) != address_mode)
--   offset_rtx = convert_to_mode (address_mode, offset_rtx, 0);

Re: RFA: RL78: Fix register constraints in rl78-real.md

[DJ Delorie]

   OK to apply ?

Ok.

[rl78] more far addr edge cases

[DJ Delorie]

More edge cases regarding far addresses.  Committed.

* config/rl78/rl78-real.md (*addqi_real): Allow SADDR types for
inc/dec.
(*addhi3_real): Likewise.
* config/rl78/rl78-virt.md (*incmode3_virt): Additional
pattern to match incrementing memory.
* config/rl78/predicates.md (rl78_1_2_operand): New.
* config/rl78/rl78.c (rl78_force_nonfar_3): Allow far mem-mem if
it's the same and only mem.
(rl78_alloc_physical_registers_op2): If there's effectively only
one MEM, transcode it into HL.
(rl78_far_p): Reject addresses that aren't legitimate.

Index: config/rl78/predicates.md
===
--- config/rl78/predicates.md   (revision 221163)
+++ config/rl78/predicates.md   (working copy)
@@ -58,6 +58,21 @@
   (and (match_code const_int)
(match_test IN_RANGE (INTVAL (op), 0, 255
 
+(define_predicate rl78_incdec_memory_operand
+  (and (match_code mem)
+   (match_test rl78_far_p (op)
+|| satisfies_constraint_Wsa (op)
+|| satisfies_constraint_Whl (op)
+|| satisfies_constraint_Wh1 (op)
+|| satisfies_constraint_Wab (op))
+  )
+)
+
+(define_predicate rl78_1_2_operand
+  (and (match_code const_int)
+   (match_test IN_RANGE (INTVAL (op), 1, 2)
+  || IN_RANGE (INTVAL (op), -2, -1
+
 (define_predicate rl78_24_operand
   (and (match_code const_int)
(match_test INTVAL (op) == 2 || INTVAL (op) == 4)))
Index: config/rl78/rl78-real.md
===
--- config/rl78/rl78-real.md(revision 221163)
+++ config/rl78/rl78-real.md(working copy)
@@ -113,14 +113,14 @@
 ;;-- Arithmetic 
 
 (define_insn *addqi3_real
-  [(set (match_operand:QI  0 rl78_nonimmediate_operand  
=rvWabWhlWh1,rvWabWhlWh1,a,*bcdehl,Wsa)
+  [(set (match_operand:QI  0 rl78_nonimmediate_operand  
=rvWabWhlWh1Wsa,rvWabWhlWh1Wsa,a,*bcdehl,Wsa)
(plus:QI (match_operand:QI 1 rl78_general_operand  %0,0,0,0,0)
 (match_operand:QI 2 rl78_general_operand 
K,L,RWhlWh1Wabi,a,i)))
]
   rl78_real_insns_ok ()
   @
-inc\t%0
-dec\t%0
+inc\t%p0
+dec\t%p0
 add\t%0, %2
 add\t%0, %2
 add\t%0, %2
@@ -128,7 +128,7 @@
 )
 
 (define_insn *addhi3_real
-  [(set (match_operand:HI  0 rl78_nonimmediate_operand  
=vABDTWh1Wab,vABDTWh1Wab,v,v,A,S,S,A)
+  [(set (match_operand:HI  0 rl78_nonimmediate_operand  
=vABDTWhlWh1WabWsa,vABDTWhlWh1WabWsa,v,v,A,S,S,A)
(plus:HI (match_operand:HI 1 rl78_general_operand  %0,0,0,0,0,0,0,S)
 (match_operand:HI 2  K,L,N,O,RWh1WhlWabiv,Int8Qs8,J,Ri)))
]
Index: config/rl78/rl78-virt.md
===
--- config/rl78/rl78-virt.md(revision 221163)
+++ config/rl78/rl78-virt.md(working copy)
@@ -85,6 +85,15 @@
 
 ;;-- Arithmetic 
 
+(define_insn *incmode3_virt
+  [(set (match_operand:QHI   0 rl78_incdec_memory_operand =vm)
+   (plus:QHI (match_operand:QHI 1 rl78_incdec_memory_operand 0)
+ (match_operand:QHI 2 rl78_1_2_operand KLNO)))
+   ]
+  rl78_virt_insns_ok ()
+  v.inc\t%0, %1, %2
+)
+
 (define_insn *addmode3_virt
   [(set (match_operand:QHI   0 rl78_nonfar_nonimm_operand =vY,S)
(plus:QHI (match_operand:QHI 1 rl78_nonfar_operand viY,0)
Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c  (revision 221163)
+++ config/rl78/rl78.c  (working copy)
@@ -579,6 +579,13 @@
   int did = 0;
   rtx temp_reg = NULL;
 
+  /* As an exception, we allow two far operands if they're identical
+ and the third operand is not a MEM.  This allows global variables
+ to be incremented, for example.  */
+  if (rtx_equal_p (operands[0], operands[1])
+   ! MEM_P (operands[2]))
+return 0;
+
   /* FIXME: Likewise.  */
   if (rl78_far_p (operands[1]))
 {
@@ -970,6 +977,12 @@
   fprintf (stderr, \033[35mrl78_far_p: ); debug_rtx (x);
   fprintf (stderr,  = %d\033[0m\n, MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR);
 #endif
+
+  /* Not all far addresses are legitimate, because the devirtualizer
+ can't handle them.  */
+  if (! rl78_as_legitimate_address (GET_MODE (x), XEXP (x, 0), false, 
ADDR_SPACE_FAR))
+return 0;
+
   return GET_MODE_BITSIZE (rl78_addr_space_address_mode (MEM_ADDR_SPACE (x))) 
== 32;
 }
 
@@ -3007,9 +3020,18 @@
 
   if (rtx_equal_p (OP (0), OP (1)))
 {
-  OP (0) =
-  OP (1) = transcode_memory_rtx (OP (1), DE, insn);
-  OP (2) = transcode_memory_rtx (OP (2), HL, insn);
+  if (MEM_P (OP (2)))
+   {
+ OP (0) =
+ OP (1) = transcode_memory_rtx (OP (1), DE, insn);
+ OP (2) = transcode_memory_rtx (OP (2), HL, insn);
+   }
+  else
+   {
+ OP (0) =
+ OP (1) = transcode_memory_rtx (OP (1), HL, insn);
+  

[rl78] fix SFmode moves

[DJ Delorie]

SFmode moves were using 8-bit transfers instead of 16-bit.  This patch
copies the SImode move pattern, which expands into 16-bit moves.

Since this only affects rl78, and the SImode code is well tested, I'm
applying this now so it will be in gcc 5.

* config/rl78/rl78-protos.h (rl78_split_movsi): Accept a mode as
well.
* config/rl78/rl78-expand.md (movsf): New, same as movsi.
* config/rl78/rl78.c (rl78_split_movsi): Accept a mode, use it
instead of hardcoding SImode.
 
Index: gcc/config/rl78/rl78-protos.h
===
--- gcc/config/rl78/rl78-protos.h   (revision 220948)
+++ gcc/config/rl78/rl78-protos.h   (working copy)
@@ -18,13 +18,13 @@
along with GCC; see the file COPYING3.  If not see
http://www.gnu.org/licenses/.  */
 
 void   rl78_emit_eh_epilogue (rtx);
 void   rl78_expand_compare (rtx *);
 void   rl78_expand_movsi (rtx *);
-void   rl78_split_movsi (rtx *);
+void   rl78_split_movsi (rtx *, enum machine_mode);
 intrl78_force_nonfar_2 (rtx *, rtx (*gen)(rtx,rtx));
 intrl78_force_nonfar_3 (rtx *, rtx (*gen)(rtx,rtx,rtx));
 void   rl78_expand_eh_epilogue (rtx);
 void   rl78_expand_epilogue (void);
 void   rl78_expand_prologue (void);
 intrl78_far_p (rtx x);
Index: gcc/config/rl78/rl78-expand.md
===
--- gcc/config/rl78/rl78-expand.md  (revision 220948)
+++ gcc/config/rl78/rl78-expand.md  (working copy)
@@ -84,13 +84,27 @@
   #
   
   [(set (match_operand:HI 2 nonimmediate_operand)
(match_operand:HI 4 general_operand))
(set (match_operand:HI 3 nonimmediate_operand)
(match_operand:HI 5 general_operand))]
-  rl78_split_movsi (operands);
+  rl78_split_movsi (operands, SImode);
+  [(set_attr valloc op1)]
+)
+
+(define_insn_and_split movsf
+  [(set (match_operand:SF 0 nonimmediate_operand =vYS,v,Wfr)
+   (match_operand:SF 1 general_operand viYS,Wfr,v))]
+  
+  #
+  
+  [(set (match_operand:HI 2 nonimmediate_operand)
+   (match_operand:HI 4 general_operand))
+   (set (match_operand:HI 3 nonimmediate_operand)
+   (match_operand:HI 5 general_operand))]
+  rl78_split_movsi (operands, SFmode);
   [(set_attr valloc op1)]
 )
 
 ;;-- Conversions 
 
 (define_expand zero_extendqihi2
Index: gcc/config/rl78/rl78.c
===
--- gcc/config/rl78/rl78.c  (revision 220948)
+++ gcc/config/rl78/rl78.c  (working copy)
@@ -503,31 +503,31 @@ rl78_expand_movsi (rtx *operands)
   emit_move_insn (op02, op12);
 }
 }
 
 /* Generate code to move an SImode value.  */
 void
-rl78_split_movsi (rtx *operands)
+rl78_split_movsi (rtx *operands, enum machine_mode omode)
 {
   rtx op00, op02, op10, op12;
 
-  op00 = rl78_subreg (HImode, operands[0], SImode, 0);
-  op02 = rl78_subreg (HImode, operands[0], SImode, 2);
+  op00 = rl78_subreg (HImode, operands[0], omode, 0);
+  op02 = rl78_subreg (HImode, operands[0], omode, 2);
 
   if (GET_CODE (operands[1]) == CONST
   || GET_CODE (operands[1]) == SYMBOL_REF)
 {
   op10 = gen_rtx_ZERO_EXTRACT (HImode, operands[1], GEN_INT (16), GEN_INT 
(0));
   op10 = gen_rtx_CONST (HImode, op10);
   op12 = gen_rtx_ZERO_EXTRACT (HImode, operands[1], GEN_INT (16), GEN_INT 
(16));
   op12 = gen_rtx_CONST (HImode, op12);
 }
   else
 {
-  op10 = rl78_subreg (HImode, operands[1], SImode, 0);
-  op12 = rl78_subreg (HImode, operands[1], SImode, 2);
+  op10 = rl78_subreg (HImode, operands[1], omode, 0);
+  op12 = rl78_subreg (HImode, operands[1], omode, 2);
 }
 
   if (rtx_equal_p (operands[0], operands[1]))
 ;
   else if (rtx_equal_p (op00, op12))
 {

[v850] fix branch limits

[DJ Delorie]

The branch limits are a bit too far, resulting in reloc errors in rare
cases.  Ok?

* config/v850/v850.md (branch_normal): Adjust branch limits.
(branch_invert): Likewise.
(branch_z_normal): Likewise.
(branch_z_invert): Likewise.
(branch_nz_normal): Likewise.
(branch_nz_invert): Likewise.
(jump): Likewise.

Index: gcc/config/v850/v850.md
===
--- gcc/config/v850/v850.md (revision 220821)
+++ gcc/config/v850/v850.md (working copy)
@@ -1452,13 +1452,13 @@
   if (TARGET_V850E3V5_UP  get_attr_length (insn) == 4)
 return b%b1 %l0;
   return b%B1 .+6 ; jr %l0;
 }
  [(set (attr length)
 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
- (const_int 256))
+ (const_int 254))
  (const_int 2)
  (if_then_else (lt (abs (minus (match_dup 0) (pc)))
  (const_int 65536))
  (const_int 4)
  (const_int 6
   (set_attr cc none)])
@@ -1485,13 +1485,13 @@
 return b%B1 %l0;
 
   return b%b1 .+6 ; jr %l0;
 }
  [(set (attr length)
 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
- (const_int 256))
+ (const_int 254))
  (const_int 2)
  (if_then_else (lt (abs (minus (match_dup 0) (pc)))
  (const_int 65536))
  (const_int 4)
  (const_int 6
   (set_attr cc none)])
@@ -1510,13 +1510,13 @@
 return bz %l0;
 
   return bnz 1f ; jr %l0 ; 1:;
 }
  [(set (attr length)
 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
- (const_int 256))
+ (const_int 254))
  (const_int 2)
  (if_then_else (lt (abs (minus (match_dup 0) (pc)))
  (const_int 65536))
  (const_int 4)
  (const_int 6
   (set_attr cc none)])
@@ -1535,13 +1535,13 @@
 return bnz %l0;
 
   return bz 1f ; jr %l0 ; 1:;
 }
  [(set (attr length)
 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
-  (const_int 256))
+  (const_int 254))
  (const_int 2)
  (if_then_else (lt (abs (minus (match_dup 0) (pc)))
  (const_int 65536))
  (const_int 4)
  (const_int 6
   (set_attr cc none)])
@@ -1560,13 +1560,13 @@
 return bnz %l0;
 
   return bz 1f ; jr %l0 ; 1:;
 }
 [(set (attr length)
 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
-  (const_int 256))
+  (const_int 254))
  (const_int 2)
  (if_then_else (lt (abs (minus (match_dup 0) (pc)))
  (const_int 65536))
  (const_int 4)
  (const_int 6
   (set_attr cc none)])
@@ -1585,13 +1585,13 @@
 return bz %l0;
 
   return bnz 1f ; jr %l0 ; 1:;
 }
  [(set (attr length)
 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
- (const_int 256))
+ (const_int 254))
  (const_int 2)
  (if_then_else (lt (abs (minus (match_dup 0) (pc)))
  (const_int 65536))
  (const_int 4)
  (const_int 6
   (set_attr cc none)])
@@ -1607,13 +1607,13 @@
 return br %0;
   else
 return jr %0;
 }
  [(set (attr length)
 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
- (const_int 256))
+ (const_int 254))
  (const_int 2)
  (const_int 4)))
   (set_attr cc none)])
 
 (define_insn indirect_jump
   [(set (pc) (match_operand:SI 0 register_operand r))]

Re: emit-rtl tidy

[DJ Delorie]

The m32c parts are OK.

Re: RFA: RL78: Fix gcc testsuite failures

[DJ Delorie]

Ok.

building against a temporary install dir?

[DJ Delorie]

So here's what I'm trying to do...  I want to build gcc, binutils, and
newlib, run tests, and IF the tests pass, THEN install them all.
However, gcc needs an installed newlib to build it's libraries.

I tried installing newlib into $DESTDIR$PREFIX but gcc ignores
$DESTDIR during the compile.

Any ideas on how to do this, short of building and installing
everything (or at least gcc and newlib) twice?

Re: Rename C files to .c in GCC source

[DJ Delorie]

 Aren't current Windows file systems case-preserving?  Then they
 shouldn't have no problems with .C files.

They are case preserving, but not case sensitive.  A wildcard search
for *.c will match foo.C and bar.c, and foo.c can be opened as FOO.C.

Re: Rename C files to .c in GCC source

[DJ Delorie]

pins...@gmail.com writes:
 No because they are c++ code so capital C is correct. 

However, we should avoid relying on case-sensitive file systems
(Windows) and use .cc or .cxx for C++ files (+ is not a valid file
name character on Windows, so we can't use .c++).

Re: [PATCH] Fix libbacktrace and libiberty tests fail on sanitized GCC due to wrong link options.

[DJ Delorie]

I can't say if this fixes a bug important enough for stage4, but if
someone wants to claim that, you won't have to wait for stage 1 :-)

Re: [PATCH] libiberty/argv.c: Use freeargv() instead of free() to avoid memory leak.

[DJ Delorie]

  memcpy (*argvp + i, file_argv, file_argc * sizeof (char *));

This code copies all the pointers in file_argv[] into argv[], so if
you freeargv them via file_argv, argv[] will point to free'd memory.
Hence the comment:

   /* Free up memory allocated to process the response file.  We do
not use freeargv because the individual options in FILE_ARGV
are now in the main ARGV.  */

Re: [PATCH] Fix libbacktrace and libiberty tests fail on sanitized GCC due to wrong link options.

[DJ Delorie]

 Does the patch look sane?

I don't think anything in the toplevel configury looks sane any
more, but I think this patch is OK.

Re: [PATCH] Workaround -Wmaybe-uninitialized false positives during profiledbootstrap

[DJ Delorie]

 +/* Workaround -Wstrict-overflow false positive during profiledbootstrap.  */
 +
 +# if GCC_VERSION = 4004
 +#pragma GCC diagnostic push
 +#pragma GCC diagnostic ignored -Wstrict-overflow
 +#endif
 +

#pragma diagnostic ignored was added in 4.4 but #pragma diagnostic
push/pop wasn't added until a later release (4.6 I think).  Attempts
to build with 4.4 (i.e. on RHEL 6) causes warnings on most files.

2010-06-21  DJ Delorie  d...@redhat.com

* diagnostic.h (diagnostic_classification_change_t): New.
(diagnostic_context): Add history and push/pop list.
(diagnostic_push_diagnostics): Declare.
(diagnostic_pop_diagnostics): Declare.
* diagnostic.c (diagnostic_classify_diagnostic): Store changes
from pragmas in a history chain instead of the global table.
(diagnostic_push_diagnostics): New.
(diagnostic_pop_diagnostics): New.
(diagnostic_report_diagnostic): Scan history chain to find state
of diagnostics as of the diagnostic location.
* opts.c (set_option): Pass UNKNOWN_LOCATION to
diagnostic_classify_diagnostic.
(enable_warning_as_error): Likewise.
* diagnostic-core.h (DK_POP): Add after real diagnostics, for
use in the history chain.
* doc/extend.texi: Document pragma GCC diagnostic changes.

[rl78] avoid move-elim on volatile mems

[DJ Delorie]

See $subj.  Committed.

* config/rl78/rl78.c (move_elim_pass): Don't optimize away
volatile memory references.

Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c  (revision 220150)
+++ config/rl78/rl78.c  (working copy)
@@ -222,7 +222,12 @@
 can eliminate the second SET.  */
   if (prev
   rtx_equal_p (SET_DEST (prev), SET_SRC (set))
-  rtx_equal_p (SET_DEST (set), SET_SRC (prev)))
+  rtx_equal_p (SET_DEST (set), SET_SRC (prev))
+ /* ... and none of the operands are volatile.  */
+  ! volatile_refs_p (SET_SRC (prev))
+  ! volatile_refs_p (SET_DEST (prev))
+  ! volatile_refs_p (SET_SRC (set))
+  ! volatile_refs_p (SET_DEST (set)))
{
  if (dump_file)
fprintf (dump_file,  Delete insn %d because it is redundant\n,

Re: RFA: RL78: Add assembler versions of some libgcc functions.

[DJ Delorie]

   OK to apply ?

Ok.

Re: RFA: RL78: Minor prologue and epilogue enhancements

[DJ Delorie]

   OK to apply ?

Ok.

Re: [PATCH] Fix generation of m32c target (PR 50928)

[DJ Delorie]

OK for trunk.

OK for 4.9 branch if it's OK with the release manager.

Do you need someone to apply it for you?