Re: [RFC] RISC-V: Add support for Profiles RVA/B23.
在 2024/7/31 4:48, Jeff Law 写道: On 7/28/24 9:24 PM, Jiawei wrote: This patch adds support for RISC-V RVA23 and RVB23 Profiles[1], which depend on the base RISC-V Profiles support[2]. [1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review [2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New Profiles. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-22.c: New test. * gcc.target/riscv/attribute-23.c: New test. So this was discussed in the patch review meeting earlier today. This really needs to wait until the profile is ratified. So I've put the patch into the deferred state for now. jeff Appreciate it, I will await further updates on the ratification process. BR, jiawei
[RFC] RISC-V: Add support for Profiles RVA/B23.
This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
which depend on the base RISC-V Profiles support[2].
[1]
https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
[2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New Profiles.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/attribute-22.c: New test.
* gcc.target/riscv/attribute-23.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 20 +++
gcc/testsuite/gcc.target/riscv/attribute-22.c | 11 ++
gcc/testsuite/gcc.target/riscv/attribute-23.c | 10 ++
3 files changed, 41 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-23.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 23ae07fe2f3..e6e8adf5e1b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -323,6 +323,9 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0},
{"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zimop", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
{"zihpm", ISA_SPEC_CLASS_NONE, 2, 0},
@@ -467,6 +470,23 @@ static const riscv_profiles riscv_profiles_table[] =
"_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
"_zicboz_zfhmin_zkt"},
+ /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions. */
+ {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+ "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+ "_zfa_zawrs"},
+
+
+ /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions. */
+ {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+ "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
+ "_zfa_zawrs"},
+
/* Currently we do not define S/M mode Profiles in gcc part. */
/* Terminate the list. */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-22.c
b/gcc/testsuite/gcc.target/riscv/attribute-22.c
new file mode 100644
index 000..0bbb3242ddd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-22.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVA23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch,
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
+_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
+_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
+_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
+_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-23.c
b/gcc/testsuite/gcc.target/riscv/attribute-23.c
new file mode 100644
index 000..459b5641ca3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-23.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVB23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch,
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
+"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0"
+"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0"
+"_zbb1p0_zbs1p0_zkt1p0\"" } } */
--
2.25.1
[PATCH v3] RISC-V: Supports Profiles in '-march' option.
Supports RISC-V profiles[1] in -march option.
Default input set the profile before other formal extensions.
V2: Fixes some format errors and adds code comments for parse function
Thanks for Jeff Law's review and comments.
V3: Update testcases and profiles extensions support.Remove S/M mode Profiles.
Thanks for Christoph Müllner,Palmer Dabbelt's review and comments.
[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
---
gcc/common/config/riscv/riscv-common.cc | 71 +++-
gcc/config/riscv/riscv-subset.h | 2 +
gcc/testsuite/gcc.target/riscv/arch-41.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-42.c | 12
gcc/testsuite/gcc.target/riscv/arch-43.c | 12
5 files changed, 101 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-41.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-42.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-43.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 682826c0e34..e092026fe9b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -231,6 +231,12 @@ struct riscv_ext_version
int minor_version;
};
+struct riscv_profiles
+{
+ const char *profile_name;
+ const char *profile_string;
+};
+
/* All standard extensions defined in all supported ISA spec. */
static const struct riscv_ext_version riscv_ext_version_table[] =
{
@@ -442,6 +448,31 @@ static const struct riscv_ext_version riscv_combine_info[]
=
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
};
+/* This table records the mapping form RISC-V Profiles into march string. */
+static const riscv_profiles riscv_profiles_table[] =
+{
+ /* RVI20U only contains the base extension 'i' as mandatory extension. */
+ {"RVI20U64", "rv64i"},
+ {"RVI20U32", "rv32i"},
+
+ /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
+ zicclsm,za128rs' as mandatory extensions. */
+ {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+ "_zicclsm_za128rs"},
+
+ /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
+ zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
+ zfhmin,zkt' as mandatory extensions. */
+ {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+ "_zicboz_zfhmin_zkt"},
+
+ /* Currently we do not define S/M mode Profiles in gcc part. */
+
+ /* Terminate the list. */
+ {NULL, NULL}
+};
+
static const riscv_cpu_info riscv_cpu_tables[] =
{
#define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -1047,6 +1078,42 @@ riscv_subset_list::parsing_subset_version (const char
*ext,
return p;
}
+/* Parsing RISC-V Profiles in -march string.
+ Return string with mandatory extensions of Profiles. */
+const char *
+riscv_subset_list::parse_profiles (const char * p){
+ /* Checking if input string contains a Profiles.
+ There are two cases use Profiles in -march option
+
+ 1. Only use Profiles as -march input
+ 2. Mixed Profiles with other extensions
+
+ use '+' to split Profiles and other extension. */
+ for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) {
+const char* match = strstr(p, riscv_profiles_table[i].profile_name);
+const char* plus_ext = strchr(p, '+');
+/* Find profile at the begin. */
+if (match != NULL && match == p) {
+ /* If there's no '+' sign, return the profile_string directly. */
+ if(!plus_ext)
+ return riscv_profiles_table[i].profile_string;
+ /* If there's a '+' sign, need to add profiles with other ext. */
+ else {
+ size_t arch_len = strlen(riscv_profiles_table[i].profile_string)+
+ strlen(plus_ext);
+ /* Reset the input string with Profiles mandatory extensions,
+ end with '_' to connect other additional extensions. */
+ char* result = new char[arch_len + 2];
+ strcpy(result, riscv_profiles_table[i].profile_string);
+ strcat(result, "_");
+ strcat(result, plus_ext + 1); /* skip the '+'. */
+ return result;
+ }
+}
+ }
+ return p;
+}
+
/* Parsing function for base extensions, rv[32|64][i|e|g]
Return Value:
@@ -1060,6 +1127,8 @@ riscv_subset_list::parse_base_ext (const char *p)
unsigned major_version = 0;
unsigned minor_version = 0;
bool explicit_version_p = false;
+
+ p = parse_profiles(p);
if (startswith (p, "rv32"))
{
@@ -1073,7 +1142,7 @@ riscv_subset_list::parse_base_ext (const char *p)
}
else
{
- error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32 or
rv64",
+ error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32, rv64
or Profile",
m_arch);
return NULL;
}
diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
index dace4de6575..98fd9877f74 100644
Re: [PATCH] Update SLP reductions process.
Thanks for your quick reply,sorry for the missing of information.
I meet this problem in risc-v test:
gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c
I found that this SLP change will add additional instrutions in the
test, please see this link:
https://godbolt.org/z/5Tfqs9zqj
在 2024/07/18 15:05, Richard Biener 写道:
On Thu, 18 Jul 2024, Jiawei wrote:
This patch improves SLP reduction handling by ensuring proper processing
even for a single reduction statement.Vectorization instances are now built
only when there are multiple scalar statements to combine into an SLP
reduction.
An example seehttps://gcc.gnu.org/bugzilla/show_bug.cgi?id=110632,
this patch fix this problem,handling SLP reduction as expected.
That PR is lacking any information so I'm not sure what kind of problem
you are fixing.
But the patch is clearly wrong - we want to use SLP even for single
reduction statements, the non-SLP path is going away.
I located the problem from the following modifications and made some
attempts.
But it seems wrong, do you have any suggestions?
- if (scalar_stmts.length () > 1)
+ /* Save for re-processing on failure. */
+ vec saved_stmts = scalar_stmts.copy ();
+ vec roots = vNULL;
+ vec remain = vNULL;
+ if (scalar_stmts.length () <= 1
+ || !vect_build_slp_instance (loop_vinfo,
+ slp_inst_kind_reduc_group,
+ scalar_stmts, roots, remain,
+ max_tree_size, , bst_map,
+ NULL))
{
- vec roots = vNULL;
- vec remain = vNULL;
- vect_build_slp_instance (loop_vinfo,
slp_inst_kind_reduc_group,
- scalar_stmts, roots, remain,
- max_tree_size, , bst_map,
NULL);
BR,
Jiawei
Richard.
gcc/ChangeLog:
* tree-vect-slp.cc (vect_analyze_slp): Improved handling of SLP
reductions
for single reduction statements.
---
gcc/tree-vect-slp.cc | 49 +---
1 file changed, 23 insertions(+), 26 deletions(-)
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 55ae496cbb2..b6dfd9fd32f 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -4054,34 +4054,31 @@ vect_analyze_slp (vec_info *vinfo, unsigned
max_tree_size)
}
}
/* Save for re-processing on failure. */
- vec saved_stmts = scalar_stmts.copy ();
- vec roots = vNULL;
- vec remain = vNULL;
- if (scalar_stmts.length () <= 1
- || !vect_build_slp_instance (loop_vinfo,
- slp_inst_kind_reduc_group,
- scalar_stmts, roots, remain,
- max_tree_size, , bst_map,
- NULL))
- {
- if (scalar_stmts.length () <= 1)
- scalar_stmts.release ();
- /* Do SLP discovery for single-lane reductions. */
- for (auto stmt_info : saved_stmts)
- {
- vec stmts;
- vec roots = vNULL;
- vec remain = vNULL;
- stmts.create (1);
- stmts.quick_push (vect_stmt_to_vectorize (stmt_info));
- vect_build_slp_instance (vinfo,
- slp_inst_kind_reduc_group,
- stmts, roots, remain,
- max_tree_size, ,
- bst_map, NULL);
+ if (loop_vinfo->reductions.length() > 0) {
+ vec scalar_stmts;
+ scalar_stmts.create(loop_vinfo->reductions.length());
+
+ for (auto next_info : loop_vinfo->reductions) {
+ if (STMT_VINFO_DEF_TYPE(next_info) == vect_reduction_def) {
+ gassign *g = dyn_cast(STMT_VINFO_STMT(next_info));
+ if (!g || !lane_reducing_op_p(gimple_assign_rhs_code(g))) {
+ scalar_stmts.quick_push(next_info);
}
- saved_stmts.release ();
+ }
}
+
+ if (scalar_stmts.length() > 1) {
+ vec roots = vNULL;
+ vec remain = vNULL;
+ if (!vect_build_slp_instance(loop_vinfo, slp_inst_kind_reduc_group,
scalar_stmts, roots, remain, max_tree_size, , bst_map, NULL)) {
+ scalar_stmts.release();
+ }
+ }
+ else {
+ scalar_stmts.release();
+ }
+ }
+
}
}
[Bug target/110632] RISC-V: SLP optimisation
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110632 jiawei changed: What|Removed |Added CC||jiawei at iscas dot ac.cn --- Comment #1 from jiawei --- Also find in: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115980， See https://godbolt.org/z/5Tfqs9zqj
[PATCH] Update SLP reductions process.
This patch improves SLP reduction handling by ensuring proper processing
even for a single reduction statement.Vectorization instances are now built
only when there are multiple scalar statements to combine into an SLP
reduction.
An example see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110632,
this patch fix this problem,handling SLP reduction as expected.
gcc/ChangeLog:
* tree-vect-slp.cc (vect_analyze_slp): Improved handling of SLP
reductions
for single reduction statements.
---
gcc/tree-vect-slp.cc | 49 +---
1 file changed, 23 insertions(+), 26 deletions(-)
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 55ae496cbb2..b6dfd9fd32f 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -4054,34 +4054,31 @@ vect_analyze_slp (vec_info *vinfo, unsigned
max_tree_size)
}
}
/* Save for re-processing on failure. */
- vec saved_stmts = scalar_stmts.copy ();
- vec roots = vNULL;
- vec remain = vNULL;
- if (scalar_stmts.length () <= 1
- || !vect_build_slp_instance (loop_vinfo,
- slp_inst_kind_reduc_group,
- scalar_stmts, roots, remain,
- max_tree_size, , bst_map,
- NULL))
- {
- if (scalar_stmts.length () <= 1)
- scalar_stmts.release ();
- /* Do SLP discovery for single-lane reductions. */
- for (auto stmt_info : saved_stmts)
- {
- vec stmts;
- vec roots = vNULL;
- vec remain = vNULL;
- stmts.create (1);
- stmts.quick_push (vect_stmt_to_vectorize (stmt_info));
- vect_build_slp_instance (vinfo,
- slp_inst_kind_reduc_group,
- stmts, roots, remain,
- max_tree_size, ,
- bst_map, NULL);
+ if (loop_vinfo->reductions.length() > 0) {
+ vec scalar_stmts;
+ scalar_stmts.create(loop_vinfo->reductions.length());
+
+ for (auto next_info : loop_vinfo->reductions) {
+ if (STMT_VINFO_DEF_TYPE(next_info) == vect_reduction_def) {
+ gassign *g = dyn_cast(STMT_VINFO_STMT(next_info));
+ if (!g || !lane_reducing_op_p(gimple_assign_rhs_code(g))) {
+ scalar_stmts.quick_push(next_info);
}
- saved_stmts.release ();
+ }
}
+
+ if (scalar_stmts.length() > 1) {
+ vec roots = vNULL;
+ vec remain = vNULL;
+ if (!vect_build_slp_instance(loop_vinfo, slp_inst_kind_reduc_group,
scalar_stmts, roots, remain, max_tree_size, , bst_map, NULL)) {
+ scalar_stmts.release();
+ }
+ }
+ else {
+ scalar_stmts.release();
+ }
+ }
+
}
}
--
2.25.1
[Bug c/115980] New: RISC-V: RVV dynamic-lmul test fail
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115980 Bug ID: 115980 Summary: RISC-V: RVV dynamic-lmul test fail Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: jiawei at iscas dot ac.cn Target Milestone: --- Current gcc trunk generated some unnecessary instructions with the case gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c https://godbolt.org/z/5Tfqs9zqj
Re: [PATCH] Fix Wstringop-overflow-47.c warning in RISC-V target.
在 2024/07/16 8:28, Jeff Law 写道: IIRC these fails are dependent upon whether or not the statements turn into vector stores or not. So to remove the xfail don't you have to know if vector is enabled/disabled? I am not sure, I tried to enable with RVV, but it still pass the test: https://godbolt.org/z/bvWfffTe5 Any suggestions?
[PATCH] Fix Wstringop-overflow-47.c warning in RISC-V target.
Update warning test info for RISC-V target, compared on godbolt:
https://godbolt.org/z/Mexd3dfcc
gcc/testsuite/ChangeLog:
* gcc.dg/Wstringop-overflow-47.c: Remove xfail target.
---
gcc/testsuite/gcc.dg/Wstringop-overflow-47.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c
b/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c
index 883921b097f..9fb78e55046 100644
--- a/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c
+++ b/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c
@@ -65,15 +65,15 @@ void warn_i16_64 (int16_t i)
like x86_64 it's a series of BIT_FIELD_REFs. The overflow by
the former is detected but the latter is not yet. */
- extern char warn_a64[64]; // { dg-message "at offset (1|128) into
destination object 'warn_a64' of size (63|64)" "pr97027 note" { xfail { ! {
aarch64-*-* riscv*-*-* } } } }
+ extern char warn_a64[64]; // { dg-message "at offset (1|128) into
destination object 'warn_a64' of size (63|64)" "pr97027 note" { xfail { ! {
aarch64-*-* } } } }
void *p = warn_a64 + 1;
I16_64 *q = (I16_64*)p;
- *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* riscv*-*-* } } } }
+ *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* } } } }
char a64[64];
p = a64 + 1;
q = (I16_64*)p;
- *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* riscv*-*-* } } } }
+ *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* } } } }
sink (p);
}
--
2.25.1
[gcc r14-10350] tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE
https://gcc.gnu.org/g:6e6f10c3ad6f96752acd9c35b653b387d5c3fcf6
commit r14-10350-g6e6f10c3ad6f96752acd9c35b653b387d5c3fcf6
Author: Jiawei
Date: Mon May 27 15:40:51 2024 +0800
tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at
tree-ssa-pre.c:2780): Return NULL_TREE when deal special cases.
Return NULL_TREE when genop3 equal EXACT_DIV_EXPR.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652641.html
version log v3: remove additional POLY_INT_CST check.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652795.html
gcc/ChangeLog:
* tree-ssa-pre.cc (create_component_ref_by_pieces_1): New
conditions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr115214.c: New test.
Diff:
---
.../gcc.target/riscv/rvv/vsetvl/pr115214.c | 52 ++
gcc/tree-ssa-pre.cc| 10 +++--
2 files changed, 59 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
new file mode 100644
index 000..fce2e9da766
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w"
} */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+
+#include
+
+static inline __attribute__(()) int vaddq_f32();
+static inline __attribute__(()) int vload_tillz_f32(int nlane) {
+ vint32m1_t __trans_tmp_9;
+ {
+int __trans_tmp_0 = nlane;
+{
+ vint64m1_t __trans_tmp_1;
+ vint64m1_t __trans_tmp_2;
+ vint64m1_t __trans_tmp_3;
+ vint64m1_t __trans_tmp_4;
+ if (__trans_tmp_0 == 1) {
+{
+ __trans_tmp_3 =
+ __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
+}
+__trans_tmp_4 = __trans_tmp_2;
+ }
+ __trans_tmp_4 = __trans_tmp_3;
+ __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
+}
+ }
+ return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot
be passed to an unprototyped function} } */
+}
+
+char CFLOAT_add_args[3];
+const int *CFLOAT_add_steps;
+const int CFLOAT_steps;
+
+__attribute__(()) void CFLOAT_add() {
+ char *b_src0 = _add_args[0], *b_src1 = _add_args[1],
+ *b_dst = _add_args[2];
+ const float *src1 = (float *)b_src1;
+ float *dst = (float *)b_dst;
+ const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
+ const int sdst = CFLOAT_add_steps[2] / sizeof(float);
+ const int hstep = 4 / 2;
+ vfloat32m1x2_t a;
+ int len = 255;
+ for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
+int b = vload_tillz_f32(len);
+int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type
'__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
+ }
+ for (; len > 0; --len, b_src0 += CFLOAT_steps,
+ b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
+;
+}
diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
index 75217f5cde1..5cf1968bc26 100644
--- a/gcc/tree-ssa-pre.cc
+++ b/gcc/tree-ssa-pre.cc
@@ -2685,11 +2685,15 @@ create_component_ref_by_pieces_1 (basic_block block,
vn_reference_t ref,
here as the element alignment may be not visible. See
PR43783. Simply drop the element size for constant
sizes. */
- if (TREE_CODE (genop3) == INTEGER_CST
+ if ((TREE_CODE (genop3) == INTEGER_CST
&& TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == INTEGER_CST
&& wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
-(wi::to_offset (genop3)
- * vn_ref_op_align_unit (currop
+(wi::to_offset (genop3) * vn_ref_op_align_unit
(currop
+ || (TREE_CODE (genop3) == EXACT_DIV_EXPR
+ && TREE_CODE (TREE_OPERAND (genop3, 1)) == INTEGER_CST
+ && operand_equal_p (TREE_OPERAND (genop3, 0), TYPE_SIZE_UNIT
(elmt_type))
+ && wi::eq_p (wi::to_offset (TREE_OPERAND (genop3, 1)),
+vn_ref_op_align_unit (currop
genop3 = NULL_TREE;
else
{
[gcc r15-917] tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE
https://gcc.gnu.org/g:c9842f99042454bef99fe82506c6dd50f34e283e
commit r15-917-gc9842f99042454bef99fe82506c6dd50f34e283e
Author: Jiawei
Date: Mon May 27 15:40:51 2024 +0800
tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at
tree-ssa-pre.c:2780): Return NULL_TREE when deal special cases.
Return NULL_TREE when genop3 equal EXACT_DIV_EXPR.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652641.html
version log v3: remove additional POLY_INT_CST check.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652795.html
gcc/ChangeLog:
* tree-ssa-pre.cc (create_component_ref_by_pieces_1): New
conditions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr115214.c: New test.
Diff:
---
.../gcc.target/riscv/rvv/vsetvl/pr115214.c | 52 ++
gcc/tree-ssa-pre.cc| 10 +++--
2 files changed, 59 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
new file mode 100644
index 000..fce2e9da766
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w"
} */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+
+#include
+
+static inline __attribute__(()) int vaddq_f32();
+static inline __attribute__(()) int vload_tillz_f32(int nlane) {
+ vint32m1_t __trans_tmp_9;
+ {
+int __trans_tmp_0 = nlane;
+{
+ vint64m1_t __trans_tmp_1;
+ vint64m1_t __trans_tmp_2;
+ vint64m1_t __trans_tmp_3;
+ vint64m1_t __trans_tmp_4;
+ if (__trans_tmp_0 == 1) {
+{
+ __trans_tmp_3 =
+ __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
+}
+__trans_tmp_4 = __trans_tmp_2;
+ }
+ __trans_tmp_4 = __trans_tmp_3;
+ __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
+}
+ }
+ return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot
be passed to an unprototyped function} } */
+}
+
+char CFLOAT_add_args[3];
+const int *CFLOAT_add_steps;
+const int CFLOAT_steps;
+
+__attribute__(()) void CFLOAT_add() {
+ char *b_src0 = _add_args[0], *b_src1 = _add_args[1],
+ *b_dst = _add_args[2];
+ const float *src1 = (float *)b_src1;
+ float *dst = (float *)b_dst;
+ const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
+ const int sdst = CFLOAT_add_steps[2] / sizeof(float);
+ const int hstep = 4 / 2;
+ vfloat32m1x2_t a;
+ int len = 255;
+ for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
+int b = vload_tillz_f32(len);
+int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type
'__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
+ }
+ for (; len > 0; --len, b_src0 += CFLOAT_steps,
+ b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
+;
+}
diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
index 75217f5cde1..5cf1968bc26 100644
--- a/gcc/tree-ssa-pre.cc
+++ b/gcc/tree-ssa-pre.cc
@@ -2685,11 +2685,15 @@ create_component_ref_by_pieces_1 (basic_block block,
vn_reference_t ref,
here as the element alignment may be not visible. See
PR43783. Simply drop the element size for constant
sizes. */
- if (TREE_CODE (genop3) == INTEGER_CST
+ if ((TREE_CODE (genop3) == INTEGER_CST
&& TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == INTEGER_CST
&& wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
-(wi::to_offset (genop3)
- * vn_ref_op_align_unit (currop
+(wi::to_offset (genop3) * vn_ref_op_align_unit
(currop
+ || (TREE_CODE (genop3) == EXACT_DIV_EXPR
+ && TREE_CODE (TREE_OPERAND (genop3, 1)) == INTEGER_CST
+ && operand_equal_p (TREE_OPERAND (genop3, 0), TYPE_SIZE_UNIT
(elmt_type))
+ && wi::eq_p (wi::to_offset (TREE_OPERAND (genop3, 1)),
+vn_ref_op_align_unit (currop
genop3 = NULL_TREE;
else
{
[Bug tree-optimization/115214] tree-ssa-pre.c(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115214 jiawei changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #2 from jiawei --- Fixed on upstream. https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652806.html
[PATCH v3] tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE when deal special cases.
Return NULL_TREE when genop3 equal EXACT_DIV_EXPR.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652641.html
version log v3: remove additional POLY_INT_CST check.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652795.html
gcc/ChangeLog:
* tree-ssa-pre.cc (create_component_ref_by_pieces_1): New conditions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr115214.c: New test.
---
.../gcc.target/riscv/rvv/vsetvl/pr115214.c| 52 +++
gcc/tree-ssa-pre.cc | 10 ++--
2 files changed, 59 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
new file mode 100644
index 000..fce2e9da766
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w"
} */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+
+#include
+
+static inline __attribute__(()) int vaddq_f32();
+static inline __attribute__(()) int vload_tillz_f32(int nlane) {
+ vint32m1_t __trans_tmp_9;
+ {
+int __trans_tmp_0 = nlane;
+{
+ vint64m1_t __trans_tmp_1;
+ vint64m1_t __trans_tmp_2;
+ vint64m1_t __trans_tmp_3;
+ vint64m1_t __trans_tmp_4;
+ if (__trans_tmp_0 == 1) {
+{
+ __trans_tmp_3 =
+ __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
+}
+__trans_tmp_4 = __trans_tmp_2;
+ }
+ __trans_tmp_4 = __trans_tmp_3;
+ __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
+}
+ }
+ return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot
be passed to an unprototyped function} } */
+}
+
+char CFLOAT_add_args[3];
+const int *CFLOAT_add_steps;
+const int CFLOAT_steps;
+
+__attribute__(()) void CFLOAT_add() {
+ char *b_src0 = _add_args[0], *b_src1 = _add_args[1],
+ *b_dst = _add_args[2];
+ const float *src1 = (float *)b_src1;
+ float *dst = (float *)b_dst;
+ const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
+ const int sdst = CFLOAT_add_steps[2] / sizeof(float);
+ const int hstep = 4 / 2;
+ vfloat32m1x2_t a;
+ int len = 255;
+ for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
+int b = vload_tillz_f32(len);
+int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type
'__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
+ }
+ for (; len > 0; --len, b_src0 += CFLOAT_steps,
+ b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
+;
+}
diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
index 75217f5cde1..5cf1968bc26 100644
--- a/gcc/tree-ssa-pre.cc
+++ b/gcc/tree-ssa-pre.cc
@@ -2685,11 +2685,15 @@ create_component_ref_by_pieces_1 (basic_block block,
vn_reference_t ref,
here as the element alignment may be not visible. See
PR43783. Simply drop the element size for constant
sizes. */
- if (TREE_CODE (genop3) == INTEGER_CST
+ if ((TREE_CODE (genop3) == INTEGER_CST
&& TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == INTEGER_CST
&& wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
-(wi::to_offset (genop3)
- * vn_ref_op_align_unit (currop
+(wi::to_offset (genop3) * vn_ref_op_align_unit
(currop
+ || (TREE_CODE (genop3) == EXACT_DIV_EXPR
+ && TREE_CODE (TREE_OPERAND (genop3, 1)) == INTEGER_CST
+ && operand_equal_p (TREE_OPERAND (genop3, 0), TYPE_SIZE_UNIT
(elmt_type))
+ && wi::eq_p (wi::to_offset (TREE_OPERAND (genop3, 1)),
+vn_ref_op_align_unit (currop
genop3 = NULL_TREE;
else
{
--
2.25.1
[PATCH v2] tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE when deal special cases.
Return NULL_TREE when match the POLY_INT case.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652641.html
gcc/ChangeLog:
* tree-ssa-pre.cc (create_component_ref_by_pieces_1): New
* conditions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr115214.c: New test.
---
.../gcc.target/riscv/rvv/vsetvl/pr115214.c| 51 +++
gcc/tree-ssa-pre.cc | 13 +++--
2 files changed, 61 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
new file mode 100644
index 000..9d19641196f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w"
} */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+
+#include
+
+static inline __attribute__(()) int vaddq_f32();
+static inline __attribute__(()) int vload_tillz_f32(int nlane) {
+ vint32m1_t __trans_tmp_9;
+ {
+int __trans_tmp_0 = nlane;
+{
+ vint64m1_t __trans_tmp_1;
+ vint64m1_t __trans_tmp_2;
+ vint64m1_t __trans_tmp_3;
+ vint64m1_t __trans_tmp_4;
+ if (__trans_tmp_0 == 1) {
+{
+ __trans_tmp_3 =
+ __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
+}
+__trans_tmp_4 = __trans_tmp_2;
+ }
+ __trans_tmp_4 = __trans_tmp_3;
+ __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
+}
+ }
+ return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot
be passed to an unprototyped function} } */
+}
+
+char CFLOAT_add_args[3];
+const int *CFLOAT_add_steps;
+const int CFLOAT_steps;
+
+__attribute__(()) void CFLOAT_add() {
+ char *b_src0 = _add_args[0], *b_src1 = _add_args[1],
+ *b_dst = _add_args[2];
+ const float *src1 = (float *)b_src1;
+ float *dst = (float *)b_dst;
+ const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
+ const int sdst = CFLOAT_add_steps[2] / sizeof(float);
+ const int hstep = 4 / 2;
+ vfloat32m1x2_t a;
+ int len = 255;
+ for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
+int b = vload_tillz_f32(len);
+int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type
'__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
+ }
+ for (; len > 0; --len, b_src0 += CFLOAT_steps,
+ b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
+;
+}
\ No newline at end of file
diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
index 75217f5cde1..b185f858c7f 100644
--- a/gcc/tree-ssa-pre.cc
+++ b/gcc/tree-ssa-pre.cc
@@ -2685,11 +2685,18 @@ create_component_ref_by_pieces_1 (basic_block block,
vn_reference_t ref,
here as the element alignment may be not visible. See
PR43783. Simply drop the element size for constant
sizes. */
- if (TREE_CODE (genop3) == INTEGER_CST
+ if ((TREE_CODE (genop3) == INTEGER_CST
&& TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == INTEGER_CST
&& wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
-(wi::to_offset (genop3)
- * vn_ref_op_align_unit (currop
+ (wi::to_offset (genop3) * vn_ref_op_align_unit (currop
+ || (TREE_CODE (genop3) == POLY_INT_CST
+ && TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == POLY_INT_CST
+ && wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
+ (wi::to_offset (genop3) * vn_ref_op_align_unit (currop
+ || (TREE_CODE (genop3) == EXACT_DIV_EXPR
+ && TREE_CODE (TREE_OPERAND (genop3, 1)) == INTEGER_CST
+ && wi::eq_p (wi::to_offset (TREE_OPERAND (genop3, 1)),
+ vn_ref_op_align_unit (currop
genop3 = NULL_TREE;
else
{
--
2.25.1
Re: [PATCH] tree-ssa-pre.c/1071140(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE if no equal.
On 2024/5/24 20:33, Richard Biener wrote:
On Fri, May 24, 2024 at 1:49 PM Jiawei wrote:
An ICE bug reported in
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1071140.
https://godbolt.org/z/WE9aGYvoo
Return NULL_TREE when TREE_CODE(op) not equal to SSA_NAME.
The assert is on purpose. Can you open a GCC bug for this please? It looks
like we have unfolded POLY_INT_CST [16, 16] /[ex] 16 here.
It seems that
/* We can't always put a size in units of the element alignment
here as the element alignment may be not visible. See
PR43783. Simply drop the element size for constant
sizes. */
if (TREE_CODE (genop3) == INTEGER_CST
&& TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == INTEGER_CST
&& wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
(wi::to_offset (genop3)
* vn_ref_op_align_unit (currop
genop3 = NULL_TREE;
fails to match the POLY_INT case - the unit alignment is 16 here. One
possibility would be to match the EXACT_DIV_EXPR case and the
INTEGER_CST divisor to vn_ref_op_align_unit and the other half
separately. But maybe this can be written in a "proper" way?
The EXACT_DIV_EXPR is built by copy_reference_ops_from_ref,
I suppose SVE could be similarly affected.
Richard.
Thanks for your quick reply, reported it on bugzilla——
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115214
BR，
Jiawei
gcc/ChangeLog:
* tree-ssa-pre.cc (find_or_generate_expression): Remove assert.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr1071140.c: New test.
---
.../gcc.target/riscv/rvv/vsetvl/pr1071140.c | 52 +++
gcc/tree-ssa-pre.cc | 4 +-
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
new file mode 100644
index 000..4f0815e099f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w"
} */
+
+#include
+
+static inline __attribute__(()) int vaddq_f32();
+static inline __attribute__(()) int vload_tillz_f32(int nlane) {
+ vint32m1_t __trans_tmp_9;
+ {
+int __trans_tmp_0 = nlane;
+{
+ vint64m1_t __trans_tmp_1;
+ vint64m1_t __trans_tmp_2;
+ vint64m1_t __trans_tmp_3;
+ vint64m1_t __trans_tmp_4;
+ if (__trans_tmp_0 == 1) {
+{
+ __trans_tmp_3 =
+ __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
+}
+__trans_tmp_4 = __trans_tmp_2;
+ }
+ __trans_tmp_4 = __trans_tmp_3;
+ __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
+}
+ }
+ return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot
be passed to an unprototyped function} } */
+}
+
+char CFLOAT_add_args[3];
+const int *CFLOAT_add_steps;
+const int CFLOAT_steps;
+
+__attribute__(()) void CFLOAT_add() {
+ char *b_src0 = _add_args[0], *b_src1 = _add_args[1],
+ *b_dst = _add_args[2];
+ const float *src1 = (float *)b_src1;
+ float *dst = (float *)b_dst;
+ const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
+ const int sdst = CFLOAT_add_steps[2] / sizeof(float);
+ const int hstep = 4 / 2;
+ vfloat32m1x2_t a;
+ int len = 255;
+ for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
+int b = vload_tillz_f32(len);
+int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type
'__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
+ }
+ for (; len > 0; --len, b_src0 += CFLOAT_steps,
+ b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
+;
+}
+
diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
index 75217f5cde1..e3d9c47f96b 100644
--- a/gcc/tree-ssa-pre.cc
+++ b/gcc/tree-ssa-pre.cc
@@ -2777,7 +2777,9 @@ find_or_generate_expression (basic_block block, tree op,
gimple_seq *stmts)
if (is_gimple_min_invariant (op))
return op;
- gcc_assert (TREE_CODE (op) == SSA_NAME);
+ if (TREE_CODE (op) != SSA_NAME)
+return NULL_TREE;
+
vn_ssa_aux_t info = VN_INFO (op);
unsigned int lookfor = info->value_id;
if (value_id_constant_p (lookfor))
--
2.25.1
[Bug c/115214] New: tree-ssa-pre.c(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115214
Bug ID: 115214
Summary: tree-ssa-pre.c(ICE in find_or_generate_expression, at
tree-ssa-pre.c:2780)
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: jiawei at iscas dot ac.cn
Target Milestone: ---
We got an ICE when compile this C code use gcc-14 on RISC-V target,see
https://godbolt.org/z/WE9aGYvoo
```
#include
static inline __attribute__(()) int vaddq_f32();
static inline __attribute__(()) int vload_tillz_f32(int nlane) {
vint32m1_t __trans_tmp_9;
{
int __trans_tmp_0 = nlane;
{
vint64m1_t __trans_tmp_1;
vint64m1_t __trans_tmp_2;
vint64m1_t __trans_tmp_3;
vint64m1_t __trans_tmp_4;
if (__trans_tmp_0 == 1) {
{
__trans_tmp_3 =
__riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
}
__trans_tmp_4 = __trans_tmp_2;
}
__trans_tmp_4 = __trans_tmp_3;
__trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
}
}
return vaddq_f32(__trans_tmp_9);
}
char CFLOAT_add_args[3];
const int *CFLOAT_add_steps;
const int CFLOAT_steps;
__attribute__(()) void CFLOAT_add() {
char *b_src0 = _add_args[0], *b_src1 = _add_args[1],
*b_dst = _add_args[2];
const float *src1 = (float *)b_src1;
float *dst = (float *)b_dst;
const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
const int sdst = CFLOAT_add_steps[2] / sizeof(float);
const int hstep = 4 / 2;
vfloat32m1x2_t a;
int len = 255;
for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
int b = vload_tillz_f32(len);
int r = vaddq_f32(a.__val[0], b);
}
for (; len > 0; --len, b_src0 += CFLOAT_steps,
b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
;
}
```
Reports as a bug following Richard Biener's suggestion
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652641.html
[PATCH] tree-ssa-pre.c/1071140(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE if no equal.
An ICE bug reported in
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1071140.
https://godbolt.org/z/WE9aGYvoo
Return NULL_TREE when TREE_CODE(op) not equal to SSA_NAME.
gcc/ChangeLog:
* tree-ssa-pre.cc (find_or_generate_expression): Remove assert.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr1071140.c: New test.
---
.../gcc.target/riscv/rvv/vsetvl/pr1071140.c | 52 +++
gcc/tree-ssa-pre.cc | 4 +-
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
new file mode 100644
index 000..4f0815e099f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w"
} */
+
+#include
+
+static inline __attribute__(()) int vaddq_f32();
+static inline __attribute__(()) int vload_tillz_f32(int nlane) {
+ vint32m1_t __trans_tmp_9;
+ {
+int __trans_tmp_0 = nlane;
+{
+ vint64m1_t __trans_tmp_1;
+ vint64m1_t __trans_tmp_2;
+ vint64m1_t __trans_tmp_3;
+ vint64m1_t __trans_tmp_4;
+ if (__trans_tmp_0 == 1) {
+{
+ __trans_tmp_3 =
+ __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
+}
+__trans_tmp_4 = __trans_tmp_2;
+ }
+ __trans_tmp_4 = __trans_tmp_3;
+ __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
+}
+ }
+ return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot
be passed to an unprototyped function} } */
+}
+
+char CFLOAT_add_args[3];
+const int *CFLOAT_add_steps;
+const int CFLOAT_steps;
+
+__attribute__(()) void CFLOAT_add() {
+ char *b_src0 = _add_args[0], *b_src1 = _add_args[1],
+ *b_dst = _add_args[2];
+ const float *src1 = (float *)b_src1;
+ float *dst = (float *)b_dst;
+ const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
+ const int sdst = CFLOAT_add_steps[2] / sizeof(float);
+ const int hstep = 4 / 2;
+ vfloat32m1x2_t a;
+ int len = 255;
+ for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
+int b = vload_tillz_f32(len);
+int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type
'__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
+ }
+ for (; len > 0; --len, b_src0 += CFLOAT_steps,
+ b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
+;
+}
+
diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
index 75217f5cde1..e3d9c47f96b 100644
--- a/gcc/tree-ssa-pre.cc
+++ b/gcc/tree-ssa-pre.cc
@@ -2777,7 +2777,9 @@ find_or_generate_expression (basic_block block, tree op,
gimple_seq *stmts)
if (is_gimple_min_invariant (op))
return op;
- gcc_assert (TREE_CODE (op) == SSA_NAME);
+ if (TREE_CODE (op) != SSA_NAME)
+return NULL_TREE;
+
vn_ssa_aux_t info = VN_INFO (op);
unsigned int lookfor = info->value_id;
if (value_id_constant_p (lookfor))
--
2.25.1
Re: Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.
-原始邮件-
发件人: "Jeff Law"
发送时间: 2024-03-19 10:54:09 (星期二)
收件人: Jiawei , gcc-patches@gcc.gnu.org
抄送: kito.ch...@sifive.com, pal...@dabbelt.com,
christoph.muell...@vrull.eu, wuwei2...@iscas.ac.cn, shi...@iscas.ac.cn,
shiyul...@iscas.ac.cn, chenyix...@iscas.ac.cn
主题: Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.
On 2/27/24 1:52 AM, Jiawei wrote:
From: Chen Jiawei
Co-Authored by: Lin Jiawei
This patch add XiangShan Nanhu cpu microarchitecture,
Nanhu is a 6-issue, superscalar, out-of-order processor.
More details see:
https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): New def.
(RISCV_CORE): Ditto.
* config/riscv/riscv-opts.h (enum
* riscv_microarchitecture_type): New option.
* config/riscv/riscv.cc: New def.
* config/riscv/riscv.md: New include.
* config/riscv/xiangshan.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-xiangshan-nanhu.c: New test.
As was discussed last Tuesday, this should be safe, even at this late
stage in the gcc-14 cycle.
+/* Costs to use when optimizing for xiangshan nanhu. */
+static const struct riscv_tune_param xiangshan_nanhu_tune_info = {
+ {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},/* fp_add */
+ {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},/* fp_mul */
+ {COSTS_N_INSNS (10), COSTS_N_INSNS (20)}, /* fp_div */
+ {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},/* int_mul */
+ {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},/* int_div */
+ 6, /* issue_rate */
+ 3, /* branch_cost */
+ 3, /* memory_cost */
+ 3, /* fmv_cost */
+ true, /*
slow_unaligned_access */
+ false, /* use_divmod_expansion
*/
+ RISCV_FUSE_ZEXTW | RISCV_FUSE_ZEXTH, /* fusible_ops */
+ NULL, /* vector cost
*/
Is your integer division really that fast? The table above essentially
says that your cpu can do integer division in 6 cycles.
+
+(define_insn_reservation "xiangshan_mul" 3
+ (and (eq_attr "tune" "xiangshan")
+ (eq_attr "type" "imul"))
+ "xs_mdu_rs")
+
+(define_insn_reservation "xiangshan_div" 21
+ (and (eq_attr "tune" "xiangshan")
+ (eq_attr "type" "idiv"))
+ "xs_mdu_rs")
Whereas your pipeline description says it's 21c.
I strongly suspect you want to increase the cost of the int_div in the
tuning table. And with a the higher cost you probably want to turn on
use_divmod_expansion.
I'll also note that your scheduler description also indicates your
division is fully pipelined. Is that correct? if not, you'll want to
adjust that reservation.
+
+(define_insn_reservation "xiangshan_sfdiv" 11
+ (and (eq_attr "tune" "xiangshan")
+ (eq_attr "type" "fdiv")
+ (eq_attr "mode" "SF"))
+ "xs_fmisc_rs")
+
+(define_insn_reservation "xiangshan_sfsqrt" 17
+ (and (eq_attr "tune" "xiangshan")
+ (eq_attr "type" "fsqrt")
+ (eq_attr "mode" "SF"))
+ "xs_fmisc_rs")
+
+(define_insn_reservation "xiangshan_dfdiv" 21
+ (and (eq_attr "tune" "xiangshan")
+ (eq_attr "type" "fdiv")
+ (eq_attr "mode" "DF"))
+ "xs_fmisc_rs")
+
+(define_insn_reservation "xiangshan_dfsqrt" 37
+ (and (eq_attr "tune" "xiangshan")
+ (eq_attr "type" "fsqrt")
+ (eq_attr "mode" "DF"))
+ "xs_fmisc_rs")
Similarly these say your fpdiv and fpsqrt are fully pipelined. It's
certainly possible, but I suspect it's really just an oversight. Given
these values you may also want to adjust the cost of an fp division in
the cost table.
Finally with such high values for for the div/sqrt units, we find that
the DFA "blows up" causing genattrtab to run for a very long time. We'll
have to keep an eye on that.
And just to be clear, I think these can be done as a followup patch. I'm
going to push this patch as-is rather than make any adjustments -- you
almost certainly know the processor's capabilities better than myself or
anyone else on this list :-)
Jeff
Thank you for the comment, some pipeline processing costs may still need to
be confirmed, and I will correct them in next patch.
BR,
Jiawei
[PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.
From: Chen Jiawei
Co-Authored by: Lin Jiawei
This patch add XiangShan Nanhu cpu microarchitecture,
Nanhu is a 6-issue, superscalar, out-of-order processor.
More details see: https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): New def.
(RISCV_CORE): Ditto.
* config/riscv/riscv-opts.h (enum
* riscv_microarchitecture_type): New option.
* config/riscv/riscv.cc: New def.
* config/riscv/riscv.md: New include.
* config/riscv/xiangshan.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-xiangshan-nanhu.c: New test.
---
gcc/config/riscv/riscv-cores.def | 6 +
gcc/config/riscv/riscv-opts.h | 1 +
gcc/config/riscv/riscv.cc | 17 ++
gcc/config/riscv/riscv.md | 3 +-
gcc/config/riscv/xiangshan.md | 148 ++
.../gcc.target/riscv/mcpu-xiangshan-nanhu.c | 34
6 files changed, 208 insertions(+), 1 deletion(-)
create mode 100644 gcc/config/riscv/xiangshan.md
create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 57928bccdc8..ab23bb7a856 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -40,6 +40,7 @@ RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
+RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
RISCV_TUNE("size", generic, optimize_size_tune_info)
@@ -90,4 +91,9 @@ RISCV_CORE("thead-c906",
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
"xtheadcondmov_xtheadfmemidx_xtheadmac_"
"xtheadmemidx_xtheadmempair_xtheadsync",
"thead-c906")
+
+RISCV_CORE("xiangshan-nanhu", "rv64imafdc_zba_zbb_zbc_zbs_"
+ "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_"
+ "svinval_zicbom_zicboz",
+ "xiangshan-nanhu")
#undef RISCV_CORE
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 4edddbadc37..31f9bffa9b6 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -57,6 +57,7 @@ enum riscv_microarchitecture_type {
sifive_7,
sifive_p400,
sifive_p600,
+ xiangshan,
generic_ooo
};
extern enum riscv_microarchitecture_type riscv_microarchitecture;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5e984ee2a55..aa53e25ae03 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -498,6 +498,23 @@ static const struct riscv_tune_param thead_c906_tune_info
= {
NULL,/* vector cost */
};
+/* Costs to use when optimizing for xiangshan nanhu. */
+static const struct riscv_tune_param xiangshan_nanhu_tune_info = {
+ {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_add */
+ {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_mul */
+ {COSTS_N_INSNS (10), COSTS_N_INSNS (20)},/* fp_div */
+ {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* int_mul */
+ {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
+ 6, /* issue_rate */
+ 3, /* branch_cost */
+ 3, /* memory_cost */
+ 3, /* fmv_cost */
+ true,/*
slow_unaligned_access */
+ false, /* use_divmod_expansion */
+ RISCV_FUSE_ZEXTW | RISCV_FUSE_ZEXTH, /* fusible_ops */
+ NULL,/* vector cost */
+};
+
/* Costs to use when optimizing for a generic ooo profile. */
static const struct riscv_tune_param generic_ooo_tune_info = {
{COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* fp_add */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 1fec13092e2..8aafe19ab51 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -685,7 +685,7 @@
;; Microarchitectures we know how to tune for.
;; Keep this in sync with enum riscv_microarchitecture.
(define_attr "tune"
- "generic,sifive_7,sifive_p400,sifive_p600,generic_ooo"
+ "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo"
(const (symbol_ref "((enum attr_tune) r
[Bug target/113087] [14] RISC-V rv64gcv vector: Runtime mismatch with rv64gc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113087 --- Comment #25 from jiawei --- I had run SPEC2017-v1.1.9 with rv64gcv_zvl256b, it passed the compile and run on base and validate cases, used qemu 8.1.0.
[RISC-V] [SIG-toolchain] Meeting cancelled (Dec 14, 2023)
Hi all, Today's meeting will be cancelled. The next RISC-V GNU Toolchain meeting will be held on Jan 11: https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit?usp=sharing Please let me know if you have topics want to discuss in the meeting. BR, Jiawei
Re: Re: [RFC] RISC-V: Support RISC-V Profiles in -march option.
-原始邮件-
发件人: "Jeff Law"
发送时间: 2023-12-12 00:15:44 (星期二)
收件人: Jiawei , gcc-patches@gcc.gnu.org
抄送: kito.ch...@sifive.com, pal...@dabbelt.com, christoph.muell...@vrull.eu
主题: Re: [RFC] RISC-V: Support RISC-V Profiles in -march option.
On 11/20/23 12:14, Jiawei wrote:
Supports RISC-V profiles[1] in -march option.
Default input set the profile is before other formal extensions.
[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (struct
riscv_profiles):
New struct.
(riscv_subset_list::parse_profiles): New function.
(riscv_subset_list::parse): New table.
* config/riscv/riscv-subset.h: New protype.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-29.c: New test.
* gcc.target/riscv/arch-30.c: New test.
* gcc.target/riscv/arch-31.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 58
+++-
gcc/config/riscv/riscv-subset.h | 2 +
gcc/testsuite/gcc.target/riscv/arch-29.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-30.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-31.c | 5 ++
6 files changed, 81 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-29.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-30.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 5111626157b..30617e619b1 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -165,6 +165,12 @@ struct riscv_ext_version
int minor_version;
};
+struct riscv_profiles
+{
+ const char * profile_name;
+ const char * profile_string;
+};
Just a formatting nit, no space between the '*' and the field name.
Fixed.
@@ -348,6 +354,28 @@ static const struct riscv_ext_version
riscv_combine_info[] =
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
};
+static const riscv_profiles riscv_profiles_table[] =
+{
+ {"RVI20U64", "rv64i"},
+ {"RVI20U32", "rv32i"},
+ /*Currently we don't have zicntr,ziccif,ziccrse,ziccamoa,
+zicclsm,za128rs yet. */
It is actually useful to note the extensions not included? I don't
think the profiles are supposed to change once ratified.
+ {"RVA22U64", "rv64imafdc_zicsr_zihintpause_zba_zbb_zbs_"
\
Note the trailing "_", was that intentional? None of the other entries
have a trailing "_".
Here is a line break due to too long length of arch string,
Adjusted the format in the new patch.
@@ -927,6 +955,31 @@ riscv_subset_list::parsing_subset_version (const
char *ext,
return p;
}
+const char *
+riscv_subset_list::parse_profiles (const char * p){
+ for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i)
{
+const char* match = strstr(p,
riscv_profiles_table[i].profile_name);
+const char* plus_ext = strchr(p, '+');
+/* Find profile at the begin. */
+if (match != NULL match == p) {
+ /* If there's no '+' sign, return the profile_string directly.
*/
+ if(!plus_ext)
+ return riscv_profiles_table[i].profile_string;
+ /* If there's a '+' sign, concatenate profiles with other ext.
*/
+ else {
+ size_t arch_len =
strlen(riscv_profiles_table[i].profile_string) +
+ strlen(plus_ext);
+ static char* result = new char[arch_len + 2];
+ strcpy(result, riscv_profiles_table[i].profile_string);
+ strcat(result, "_");
+ strcat(result, plus_ext + 1); /* skip the '+'. */
+ return result;
+ }
+}
+ }
+ return p;
+}
This needs a function comment.
Thanks, added the parse function descrption and some deal logical.
The open curly should always be on a line by itself which is going to
require reindenting all this code. Comments go on separate lines rather
than appending them to an existing line.
I think the consensus in the Tuesday patchwork meeting was that while
there are concerns about profiles, those concerns should prevent this
patch from going forward. So if you could fix the formatting problem as
well as the trailing "_" issue noted above and repost, it would be
appreciated.
Thanks,
Jeff
Thanks for your review and comments, I had update them in the new patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640324.html
BR,
Jiawei
[PATCH v2] RISC-V: Supports RISC-V Profiles in '-march' option.
Supports RISC-V profiles[1] in -march option.
Default input set the profile is before other formal extensions.
V2: Fixes some format errors and adds code comments for parse function
Thanks for Jeff Law's review and comments.
[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (struct riscv_profiles):
New struct.
(riscv_subset_list::parse_profiles): New function.
(riscv_subset_list::parse): New table.
* config/riscv/riscv-subset.h: New protype.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-31.c: New test.
* gcc.target/riscv/arch-32.c: New test.
* gcc.target/riscv/arch-33.c: New test.
* gcc.target/riscv/arch-34.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 83 +++-
gcc/config/riscv/riscv-subset.h | 2 +
gcc/testsuite/gcc.target/riscv/arch-31.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-32.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-33.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-34.c | 7 ++
6 files changed, 106 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-33.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-34.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 4d5a2f874a2..8b674a4a280 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -195,6 +195,12 @@ struct riscv_ext_version
int minor_version;
};
+struct riscv_profiles
+{
+ const char *profile_name;
+ const char *profile_string;
+};
+
/* All standard extensions defined in all supported ISA spec. */
static const struct riscv_ext_version riscv_ext_version_table[] =
{
@@ -379,6 +385,42 @@ static const struct riscv_ext_version riscv_combine_info[]
=
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
};
+/* This table records the mapping form RISC-V Profiles into march string. */
+static const riscv_profiles riscv_profiles_table[] =
+{
+ /* RVI20U only contains the base extesnion 'i' as mandatory extension. */
+ {"RVI20U64", "rv64i"},
+ {"RVI20U32", "rv32i"},
+
+ /* RVA20U contains the 'i,m,a,f,d,c,zicsr' as mandatory extensions.
+ Currently we don't have zicntr,ziccif,ziccrse,ziccamoa,
+ zicclsm,za128rs yet. */
+ {"RVA20U64", "rv64imafdc_zicsr"},
+
+ /* RVA20S64 mandatory include all the extensions in RVA20U64 and
+ additonal 'zifencei' as mandatory extensions.
+ Notes that ss1p11, svbare, sv39, svade, sscptr, ssvecd, sstvala should
+ control by binutils. */
+ {"RVA20S64", "rv64imafdc_zicsr_zifencei"},
+
+ /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,
+ zicbom,zicbop,zicboz,zfhmin,zkt' as mandatory extensions.
+ Currently we don't have zicntr,zihpm,ziccif,ziccrse,ziccamoa,
+ zicclsm,zic64b,za64rs yet. */
+ {"RVA22U64", "rv64imafdc_zicsr_zihintpause_zba_zbb_zbs"
\
+ "_zicbom_zicbop_zicboz_zfhmin_zkt"},
+
+ /* RVA22S64 mandatory include all the extensions in RVA22U64 and
+ additonal 'zifencei,svpbmt,svinval' as mandatory extensions.
+ Notes that ss1p12, svbare, sv39, svade, sscptr, ssvecd, sstvala,
+ scounterenw extentions should control by binutils. */
+ {"RVA22S64","rv64imafdc_zicsr_zifencei_zihintpause"
\
+ "_zba_zbb_zbs_zicbom_zicbop_zicboz_zfhmin_zkt_svpbmt_svinval"},
+
+ /* Terminate the list. */
+ {NULL, NULL}
+};
+
static const riscv_cpu_info riscv_cpu_tables[] =
{
#define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -958,6 +1000,42 @@ riscv_subset_list::parsing_subset_version (const char
*ext,
return p;
}
+/* Parsing RISC-V Profiles in -march string.
+ Return string with mandatory extensions of Profiles. */
+const char *
+riscv_subset_list::parse_profiles (const char * p){
+ /* Checking if input string contains a Profiles.
+ There are two cases use Proifles in -march option
+
+ 1. Only use Proifles as -march input
+ 2. Mixed Profiles with other extensions
+
+ use '+' to split Profiles and other extension. */
+ for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) {
+const char* match = strstr(p, riscv_profiles_table[i].profile_name);
+const char* plus_ext = strchr(p, '+');
+/* Find profile at the begin. */
+if (match != NULL && match == p) {
+ /* If there's no '+' sign, return the profile_string directly. */
+ if(!plus_ext)
+ return riscv_profiles_table[i].profile_string;
+ /* If there's a '+' sign, need to add profiles with other ext. */
+ else {
+ size_t arch_len = strlen(riscv_profiles_table[i].profile_string)+
+ strlen(plus_ext);
+ /* Reset the input string with Profiles mandatory extensions,
+ end with '_'
[RFC] RISC-V: Support RISC-V Profiles in -march option.
Supports RISC-V profiles[1] in -march option.
Default input set the profile is before other formal extensions.
[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (struct riscv_profiles):
New struct.
(riscv_subset_list::parse_profiles): New function.
(riscv_subset_list::parse): New table.
* config/riscv/riscv-subset.h: New protype.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-29.c: New test.
* gcc.target/riscv/arch-30.c: New test.
* gcc.target/riscv/arch-31.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 58 +++-
gcc/config/riscv/riscv-subset.h | 2 +
gcc/testsuite/gcc.target/riscv/arch-29.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-30.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-31.c | 5 ++
6 files changed, 81 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-29.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-30.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 5111626157b..30617e619b1 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -165,6 +165,12 @@ struct riscv_ext_version
int minor_version;
};
+struct riscv_profiles
+{
+ const char * profile_name;
+ const char * profile_string;
+};
+
/* All standard extensions defined in all supported ISA spec. */
static const struct riscv_ext_version riscv_ext_version_table[] =
{
@@ -348,6 +354,28 @@ static const struct riscv_ext_version riscv_combine_info[]
=
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
};
+static const riscv_profiles riscv_profiles_table[] =
+{
+ {"RVI20U64", "rv64i"},
+ {"RVI20U32", "rv32i"},
+ /*Currently we don't have zicntr,ziccif,ziccrse,ziccamoa,
+zicclsm,za128rs yet. */
+ {"RVA20U64", "rv64imafdc_zicsr"},
+ /*Ss1p11, svbare, sv39, svade, sscptr, ssvecd, sstvala should
+control by binutils. */
+ {"RVA20S64", "rv64imafdc_zicsr_zifencei"},
+ /*Currently we don't have zicntr,zihpm,ziccif,ziccrse,ziccamoa,
+zicclsm,zic64b,za64rs yet. */
+ {"RVA22U64", "rv64imafdc_zicsr_zihintpause_zba_zbb_zbs_"
\
+ "zicbom_zicbop_zicboz_zfhmin_zkt"},
+ /*Ss1p12, svbare, sv39, svade, sscptr, ssvecd, sstvala,
+scounterenw should control by binutils. */
+ {"RVA22S64","rv64imafdc_zicsr_zifencei_zihintpause"
\
+ "_zba_zbb_zbs_zicbom_zicbop_zicboz_zfhmin_zkt_svpbmt_svinval"},
+ /* Terminate the list. */
+ {NULL, NULL}
+};
+
static const riscv_cpu_info riscv_cpu_tables[] =
{
#define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -927,6 +955,31 @@ riscv_subset_list::parsing_subset_version (const char *ext,
return p;
}
+const char *
+riscv_subset_list::parse_profiles (const char * p){
+ for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) {
+const char* match = strstr(p, riscv_profiles_table[i].profile_name);
+const char* plus_ext = strchr(p, '+');
+/* Find profile at the begin. */
+if (match != NULL && match == p) {
+ /* If there's no '+' sign, return the profile_string directly. */
+ if(!plus_ext)
+ return riscv_profiles_table[i].profile_string;
+ /* If there's a '+' sign, concatenate profiles with other ext. */
+ else {
+ size_t arch_len = strlen(riscv_profiles_table[i].profile_string) +
+ strlen(plus_ext);
+ static char* result = new char[arch_len + 2];
+ strcpy(result, riscv_profiles_table[i].profile_string);
+ strcat(result, "_");
+ strcat(result, plus_ext + 1); /* skip the '+'. */
+ return result;
+ }
+}
+ }
+ return p;
+}
+
/* Parsing function for standard extensions.
Return Value:
@@ -1430,7 +1483,10 @@ riscv_subset_list::parse (const char *arch, location_t
loc)
riscv_subset_list *subset_list = new riscv_subset_list (arch, loc);
riscv_subset_t *itr;
+
const char *p = arch;
+ p = subset_list->parse_profiles(p);
+
if (startswith (p, "rv32"))
{
subset_list->m_xlen = 32;
@@ -1443,7 +1499,7 @@ riscv_subset_list::parse (const char *arch, location_t
loc)
}
else
{
- error_at (loc, "%<-march=%s%>: ISA string must begin with rv32 or rv64",
+ error_at (loc, "%<-march=%s%>: ISA string must begin with rv32, rv64 or
a profile",
arch);
goto fail;
}
diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
index d2a4bd20530..c8b778330b4 100644
--- a/gcc/config/riscv/riscv-subset.h
+++ b/gcc/config/riscv/riscv-subset.h
@@ -76,6 +76,8 @@ private:
const char *parse_single_multiletter_ext (const char *, const char *,
const char *);
+ const char *parse_profiles (const char*);
+
void handle_implied_ext
[RISC-V] [SIG-toolchain] Meeting will be canceled (Nov 16, 2023)
Hi all, Tommorrow's meeting will be canceled, since there are few new topics to discuss. The next RISC-V GNU Toolchain meeting is collecting topics: https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit?usp=sharing Please add what want to discuss in the next meeting. Regards, Jiawei
[RISCV] RISC-V GNU Toolchain Monthly Sync-up call (Oct 19, 2023)
Hi all, We are collecting tomorrow's RISC-V GNU toolchain meeting topics, if you have any topics want to discuss or share, please change the angenda/notes doc and let me know. https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit# P.S. The meeting calendar .ics file has updated, please check and update it,thanks! Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Monthly Sync-up Time: Oct 19 2023 11:00 PM Singapore Oct 19, 2023 8:00 AM(PTS US)/11:00 AM(PHILADELPHIA Pennsylvania) 17:00 PM(Paris France)/11:00 PM(BEIJING China) Every 4 weeks on Thu, until Dec 14, 2023, 7 occurrence(s) Jun 29, 2023 11:00 PM Jul 27, 2023 11:00 PM Aug 24, 2023 11:00 PM Sep 21, 2023 11:00 PM Oct 19, 2023 11:00 PM Nov 16, 2023 11:00 PM Dec 14, 2023 11:00 PM Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://us02web.zoom.us/meeting/tZ0ufuqurjsjH9XTthkNg3MffX-QsRBuVBET/ics?icsToken=98tyKuGhrTIpHNSVuRyGRpx5A4r4b-7ziGJEgvplqAvtCA5UMS7wMNoPA6FNMs3m Join Zoom Meeting https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20230407T050750Z TZURL:https://www.tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230614T144457Z DTSTART;TZID=Asia/Singapore:20230629T23 DTEND;TZID=Asia/Singapore:20230630T00 SUMMARY:RISC-V GNU Toolchain Monthly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20231214T16;INTERVAL=4;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\n\n---\n\nOne tap mobile\n+6531294892\,\,89393600951#\,\,\,\,*899662# Singapore\n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\n---\ n\nDial by your location\n⢠+65 3129 4892 Singapore\n⢠+65 3158 7288 Sin gapore\n⢠+65 3165 1065 Singapore\n⢠+65 3129 4891 Singapore\n⢠+1 669 9 00 9128 US (San Jose)\n⢠+1 669 444 9171 US\n⢠+1 253 215 8782 US (Tacom a)\n⢠+1 346 248 7799 US (Houston)\n⢠+1 719 359 4580 US\n⢠+1 253 205 0 468 US\n⢠+1 386 347 5053 US\n⢠+1 507 473 4847 US\n⢠+1 564 217 2000 US \n⢠+1 646 558 8656 US (New York)\n⢠+1 646 931 3860 US\n⢠+1 689 278 10 00 US\n⢠+1 301 715 8592 US (Washington DC)\n⢠+1 305 224 1968 US\n⢠+1 309 205 3325 US\n⢠+1 312 626 6799 US (Chicago)\n⢠+1 360 209 5623 US\n\ nMeeting ID: 893 9360 0951\nPasscode: 899662\n\nFind your local number: https://us02web.zoom.us/u/kk9cyIPNJ\n\n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
[RISC-V] [SIG-toolchain] Meeting will be canceled (Aug 24, 2023)
Hi all, Today's meeting will be canceled, since during the China RISC-V Summit. The next RISC-V GNU Toolchain meeting is collecting topics: https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit?usp=sharing Please add what want to discuss in the next meeting. Regards, Jiawei
[RISCV] RISC-V GNU Toolchain Monthly Sync-up call (July 27, 2023)
Hi all, We are collecting tomorrow's RISC-V GNU toolchain meeting topics, if you have any topics want to discuss or share, please change the angenda/notes doc and let me know. https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit# P.S. The meeting calendar .ics file has updated, please check and update it,thanks! Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Monthly Sync-up Time: July 27, 2023 11:00 PM Singapore July 27, 2023 8:00 AM(PTS US)/11:00 AM(PHILADELPHIA Pennsylvania) 17:00 PM(Paris France)/11:00 PM(BEIJING China) Every 4 weeks on Thu, until Dec 14, 2023, 7 occurrence(s) Jun 29, 2023 11:00 PM Jul 27, 2023 11:00 PM Aug 24, 2023 11:00 PM Sep 21, 2023 11:00 PM Oct 19, 2023 11:00 PM Nov 16, 2023 11:00 PM Dec 14, 2023 11:00 PM Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://us02web.zoom.us/meeting/tZ0ufuqurjsjH9XTthkNg3MffX-QsRBuVBET/ics?icsToken=98tyKuGhrTIpHNSVuRyGRpx5A4r4b-7ziGJEgvplqAvtCA5UMS7wMNoPA6FNMs3m Join Zoom Meeting https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20230407T050750Z TZURL:https://www.tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230614T144457Z DTSTART;TZID=Asia/Singapore:20230629T23 DTEND;TZID=Asia/Singapore:20230630T00 SUMMARY:RISC-V GNU Toolchain Monthly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20231214T16;INTERVAL=4;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\n\n---\n\nOne tap mobile\n+6531294892\,\,89393600951#\,\,\,\,*899662# Singapore\n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\n---\ n\nDial by your location\n⢠+65 3129 4892 Singapore\n⢠+65 3158 7288 Sin gapore\n⢠+65 3165 1065 Singapore\n⢠+65 3129 4891 Singapore\n⢠+1 669 9 00 9128 US (San Jose)\n⢠+1 669 444 9171 US\n⢠+1 253 215 8782 US (Tacom a)\n⢠+1 346 248 7799 US (Houston)\n⢠+1 719 359 4580 US\n⢠+1 253 205 0 468 US\n⢠+1 386 347 5053 US\n⢠+1 507 473 4847 US\n⢠+1 564 217 2000 US \n⢠+1 646 558 8656 US (New York)\n⢠+1 646 931 3860 US\n⢠+1 689 278 10 00 US\n⢠+1 301 715 8592 US (Washington DC)\n⢠+1 305 224 1968 US\n⢠+1 309 205 3325 US\n⢠+1 312 626 6799 US (Chicago)\n⢠+1 360 209 5623 US\n\ nMeeting ID: 893 9360 0951\nPasscode: 899662\n\nFind your local number: https://us02web.zoom.us/u/kk9cyIPNJ\n\n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
[RISC-V] RISC-V GNU Toolchain meeting rescheduled
Hi all, We plan to change the meeting schedule from biweekly into monthly，the next meeting will be held in two weeks, There are collecting meeting topics, if you have any topics want to discuss or share, please change the angenda/notes doc and let me know. https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit# P.S. The meeting calendar .ics file has updated, please check and update it,thanks! Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Monthly Sync-up Time: Jun 29, 2023 11:00 PM Singapore Every 4 weeks on Thu, until Dec 14, 2023, 7 occurrence(s) Jun 29, 2023 11:00 PM Jul 27, 2023 11:00 PM Aug 24, 2023 11:00 PM Sep 21, 2023 11:00 PM Oct 19, 2023 11:00 PM Nov 16, 2023 11:00 PM Dec 14, 2023 11:00 PM Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://us02web.zoom.us/meeting/tZ0ufuqurjsjH9XTthkNg3MffX-QsRBuVBET/ics?icsToken=98tyKuGhrTIpHNSVuRyGRpx5A4r4b-7ziGJEgvplqAvtCA5UMS7wMNoPA6FNMs3m Join Zoom Meeting https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20230407T050750Z TZURL:https://www.tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230614T144457Z DTSTART;TZID=Asia/Singapore:20230629T23 DTEND;TZID=Asia/Singapore:20230630T00 SUMMARY:RISC-V GNU Toolchain Monthly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20231214T16;INTERVAL=4;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\n\n---\n\nOne tap mobile\n+6531294892\,\,89393600951#\,\,\,\,*899662# Singapore\n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\n---\ n\nDial by your location\n⢠+65 3129 4892 Singapore\n⢠+65 3158 7288 Sin gapore\n⢠+65 3165 1065 Singapore\n⢠+65 3129 4891 Singapore\n⢠+1 669 9 00 9128 US (San Jose)\n⢠+1 669 444 9171 US\n⢠+1 253 215 8782 US (Tacom a)\n⢠+1 346 248 7799 US (Houston)\n⢠+1 719 359 4580 US\n⢠+1 253 205 0 468 US\n⢠+1 386 347 5053 US\n⢠+1 507 473 4847 US\n⢠+1 564 217 2000 US \n⢠+1 646 558 8656 US (New York)\n⢠+1 646 931 3860 US\n⢠+1 689 278 10 00 US\n⢠+1 301 715 8592 US (Washington DC)\n⢠+1 305 224 1968 US\n⢠+1 309 205 3325 US\n⢠+1 312 626 6799 US (Chicago)\n⢠+1 360 209 5623 US\n\ nMeeting ID: 893 9360 0951\nPasscode: 899662\n\nFind your local number: https://us02web.zoom.us/u/kk9cyIPNJ\n\n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
[PATCH v2 3/3] RISC-V: Add ZC* test for failed march args being passed.
Add ZC* extensions march args tests for error input cases.
Co-Authored by: Nandni Jamnadas
Co-Authored by: Jiawei
Co-Authored by: Mary Bennett
Co-Authored by: Simon Cook
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-22.c: New test.
* gcc.target/riscv/arch-23.c: New test.
---
gcc/testsuite/gcc.target/riscv/arch-22.c | 5 +
gcc/testsuite/gcc.target/riscv/arch-23.c | 5 +
2 files changed, 10 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c
diff --git a/gcc/testsuite/gcc.target/riscv/arch-22.c
b/gcc/testsuite/gcc.target/riscv/arch-22.c
new file mode 100644
index 000..3be4ade65a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-22.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcf -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" {
target *-*-* } 0 } */
+/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" ""
{ target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-23.c
b/gcc/testsuite/gcc.target/riscv/arch-23.c
new file mode 100644
index 000..cecce06e474
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-23.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zce -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64if_zce': zcf extension supports in rv32 only" "" {
target *-*-* } 0 } */
+/* { dg-error "'-march=rv64if_zca_zcb_zce_zcf_zcmp_zcmt': zcf extension
supports in rv32 only" "" { target *-*-* } 0 } */
--
2.25.1
[PATCH v2 2/3] RISC-V: Enable compressible features when use ZC* extensions.
This patch enables the compressible features with ZC* extensions.
Since all ZC* extension depends on the Zca extension, it's sufficient to only
add the target Zca to extend the target RVC.
Co-Authored by: Mary Bennett
Co-Authored by: Nandni Jamnadas
Co-Authored by: Simon Cook
gcc/ChangeLog:
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Enable compressed builtins when ZC* extensions enabled.
* config/riscv/riscv-shorten-memrefs.cc:
Enable shorten_memrefs pass when ZC* extensions enabled.
* config/riscv/riscv.cc (riscv_compressed_reg_p):
Enable compressible registers when ZC* extensions enabled.
(riscv_rtx_costs): Allow adjusting rtx costs when ZC* extensions
enabled.
(riscv_address_cost): Allow adjusting address cost when ZC* extensions
enabled.
(riscv_first_stack_step): Allow compression of the register saves
without adding extra instructions.
* config/riscv/riscv.h (FUNCTION_BOUNDARY): Adjusts function boundary
to 16 bits when ZC* extensions enabled.
---
gcc/config/riscv/riscv-c.cc | 2 +-
gcc/config/riscv/riscv-shorten-memrefs.cc | 3 ++-
gcc/config/riscv/riscv.cc | 11 +++
gcc/config/riscv/riscv.h | 2 +-
4 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 6ad562dcb8b..2937c160071 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -47,7 +47,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
{
builtin_define ("__riscv");
- if (TARGET_RVC)
+ if (TARGET_RVC || TARGET_ZCA)
builtin_define ("__riscv_compressed");
if (TARGET_RVE)
diff --git a/gcc/config/riscv/riscv-shorten-memrefs.cc
b/gcc/config/riscv/riscv-shorten-memrefs.cc
index 8f10d24ec39..6f2b973278e 100644
--- a/gcc/config/riscv/riscv-shorten-memrefs.cc
+++ b/gcc/config/riscv/riscv-shorten-memrefs.cc
@@ -65,7 +65,8 @@ public:
/* opt_pass methods: */
virtual bool gate (function *)
{
- return TARGET_RVC && riscv_mshorten_memrefs && optimize > 0;
+ return (TARGET_RVC || TARGET_ZCA)
+ && riscv_mshorten_memrefs && optimize > 0;
}
virtual unsigned int execute (function *);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 21e7d3b3caa..3a07122bf6a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1176,7 +1176,8 @@ static bool
riscv_compressed_reg_p (int regno)
{
/* x8-x15/f8-f15 are compressible registers. */
- return (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
+ return ((TARGET_RVC || TARGET_ZCA)
+ && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
|| IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)));
}
@@ -2416,7 +2417,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
/* When optimizing for size, make uncompressible 32-bit addresses
more expensive so that compressible 32-bit addresses are
preferred. */
- if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
+ if ((TARGET_RVC || TARGET_ZCA)
+ && !speed && riscv_mshorten_memrefs && mode == SImode
&& !riscv_compressed_lw_address_p (XEXP (x, 0)))
cost++;
@@ -2828,7 +2830,8 @@ riscv_address_cost (rtx addr, machine_mode mode,
{
/* When optimizing for size, make uncompressible 32-bit addresses more
* expensive so that compressible 32-bit addresses are preferred. */
- if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
+ if ((TARGET_RVC || TARGET_ZCA)
+ && !speed && riscv_mshorten_memrefs && mode == SImode
&& !riscv_compressed_lw_address_p (addr))
return riscv_address_insns (addr, mode, false) + 1;
return riscv_address_insns (addr, mode, false);
@@ -5331,7 +5334,7 @@ riscv_first_stack_step (struct riscv_frame_info *frame,
poly_int64 remaining_siz
&& remaining_const_size % IMM_REACH >= min_first_step)
return remaining_const_size % IMM_REACH;
- if (TARGET_RVC)
+ if (TARGET_RVC || TARGET_ZCA)
{
/* If we need two subtracts, and one is small enough to allow compressed
loads and stores, then put that one first. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4541255a8ae..a507db61900 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -186,7 +186,7 @@ ASM_MISA_SPEC
#define PARM_BOUNDARY BITS_PER_WORD
/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
+#define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32)
/* The smallest supported stack boundary the calling convention supports. */
#define STACK_BOUNDARY \
--
2.25.1
[PATCH v2 1/3] RISC-V: Minimal support for ZC* extensions.
This patch is the minimal support for ZC* extensions, include the extension
name, mask and target defination. Also define the dependencies with Zca
and Zce extension. Notes that all ZC* extensions depend on the Zca extension.
Zce includes all relevant ZC* extensions for microcontrollers using. Zce
will imply zcf when 'f' extension enabled in rv32.
Co-Authored by: Charlie Keaney
Co-Authored by: Mary Bennett
Co-Authored by: Nandni Jamnadas
Co-Authored by: Simon Cook
Co-Authored by: Sinan Lin
Co-Authored by: Shihua Liao
Co-Authored by: Yulong Shi
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_subset_list::parse): New
extensions.
* config/riscv/riscv-opts.h (MASK_ZCA): New mask.
(MASK_ZCB): Ditto.
(MASK_ZCE): Ditto.
(MASK_ZCF): Ditto.
(MASK_ZCD): Ditto.
(MASK_ZCMP): Ditto.
(MASK_ZCMT): Ditto.
(TARGET_ZCA): New target.
(TARGET_ZCB): Ditto.
(TARGET_ZCE): Ditto.
(TARGET_ZCF): Ditto.
(TARGET_ZCD): Ditto.
(TARGET_ZCMP): Ditto.
(TARGET_ZCMT): Ditto.
* config/riscv/riscv.opt: New target variable.
---
gcc/common/config/riscv/riscv-common.cc | 38 +
gcc/config/riscv/riscv-opts.h | 16 +++
gcc/config/riscv/riscv.opt | 3 ++
3 files changed, 57 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 3247d526c0a..89bdbef43a5 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -111,6 +111,16 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zhinx", "zhinxmin"},
{"zhinxmin", "zfinx"},
+ {"zce", "zca"},
+ {"zce", "zcb"},
+ {"zce", "zcmp"},
+ {"zce", "zcmt"},
+ {"zcf", "zca"},
+ {"zcd", "zca"},
+ {"zcb", "zca"},
+ {"zcmp", "zca"},
+ {"zcmt", "zca"},
+
{NULL, NULL}
};
@@ -224,6 +234,14 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zca", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcb", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zce", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcf", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcd", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
{"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1156,8 +1174,19 @@ riscv_subset_list::parse (const char *arch, location_t
loc)
subset_list->handle_implied_ext (itr);
}
+ /* Zce only implies zcf when RV32 and 'f' extension exist. */
+ if (subset_list->lookup ("zce") != NULL
+ && subset_list->m_xlen == 32
+ && subset_list->lookup ("f") != NULL
+ && subset_list->lookup ("zcf") == NULL)
+subset_list->add ("zcf", false);
+
subset_list->handle_combine_ext ();
+ if (subset_list->lookup ("zcf") && subset_list->m_xlen == 64)
+error_at (loc, "%<-march=%s%>: zcf extension supports in rv32 only"
+ , arch);
+
if (subset_list->lookup ("zfinx") && subset_list->lookup ("f"))
error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
"extensions", arch);
@@ -1271,6 +1300,15 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zmmul", _options::x_riscv_zm_subext, MASK_ZMMUL},
+ /* Code-size reduction extensions. */
+ {"zca", _options::x_riscv_zc_subext, MASK_ZCA},
+ {"zcb", _options::x_riscv_zc_subext, MASK_ZCB},
+ {"zce", _options::x_riscv_zc_subext, MASK_ZCE},
+ {"zcf", _options::x_riscv_zc_subext, MASK_ZCF},
+ {"zcd", _options::x_riscv_zc_subext, MASK_ZCD},
+ {"zcmp",_options::x_riscv_zc_subext, MASK_ZCMP},
+ {"zcmt",_options::x_riscv_zc_subext, MASK_ZCMT},
+
{"svinval", _options::x_riscv_sv_subext, MASK_SVINVAL},
{"svnapot", _options::x_riscv_sv_subext, MASK_SVNAPOT},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 208a557b8ff..3429fc1218e 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -215,6 +215,22 @@ enum riscv_entity
#define MASK_ZMMUL (1 << 0)
#define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
+#define MASK_ZCA (1 << 0)
+#define MASK_ZCB (1 << 1)
+#define MASK_ZCE (1 << 2)
+#define MASK_ZCF (1 << 3)
+#define MASK_ZCD (1 << 4)
+#define MASK_ZCMP (1 << 5)
+#define MASK_ZCMT (1 << 6)
+
+#define TARGET_ZCA((riscv_zc_subext & MASK_ZCA) != 0)
+#define TARGET_ZCB((riscv_zc_subext & MASK_ZCB) != 0)
+#define TARGET_ZCE((riscv_zc_subext & MASK_ZCE) != 0)
+#define TARGET_ZCF((riscv_zc_subext & MASK_ZCF) != 0)
+#define TARGET_ZCD((riscv_zc_subext & MASK_ZCD) != 0)
+#define TARGET_ZCMP ((riscv_zc_subext & MASK_ZCMP) != 0)
+#define TARGET_ZCMT ((riscv_zc_subext & MASK_ZCMT) != 0)
+
#define MASK_SVINVAL (1 << 0)
#define MASK_SVNAPOT (1 << 1)
diff --git
[PATCH v2 0/3] RISC-V: Support ZC* extensions.
RISC-V Code Size Reduction(ZC*) extensions is a group of extensions which define subsets of the existing C extension (Zca, Zcd, Zcf) and new extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1] The implementation of the RISC-V Code Size Reduction extension in GCC is an important step towards making the RISC-V architecture more efficient. The cooperation with OpenHW group has played a crucial role in this effort, with facilitating the implementation, testing and validation. Currently works can also find in OpenHW group's github repo.[2] Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the specification, and Jeremy Bennett's patient guidance throughout the whole development process.a V2 changes: Fix Kito's comments in first version, Eswin assisted in optimizing the implementation of Zcmp extension: https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617440.html https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617442.html https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620869.html [1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification [2] github.com/openhwgroup/corev-gcc Co-Authored by: Charlie Keaney Co-Authored by: Mary Bennett Co-Authored by: Nandni Jamnadas Co-Authored by: Sinan Lin Co-Authored by: Simon Cook Co-Authored by: Shihua Liao Co-Authored by: Yulong Shi RISC-V: Minimal support for ZC extensions. RISC-V: Enable compressible features when use ZC* extensions. RISC-V: Add ZC* test for march args being passed. Jiawei (3): RISC-V: Minimal support for ZC* extensions. RISC-V: Enable compressible features when use ZC* extensions. RISC-V: Add ZC* test for failed march args being passed. gcc/common/config/riscv/riscv-common.cc | 38 +++ gcc/config/riscv/riscv-c.cc | 2 +- gcc/config/riscv/riscv-opts.h | 16 ++ gcc/config/riscv/riscv-shorten-memrefs.cc | 3 +- gcc/config/riscv/riscv.cc | 11 --- gcc/config/riscv/riscv.h | 2 +- gcc/config/riscv/riscv.opt| 3 ++ gcc/testsuite/gcc.target/riscv/arch-22.c | 5 +++ gcc/testsuite/gcc.target/riscv/arch-23.c | 5 +++ 9 files changed, 78 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c -- 2.25.1
Re: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp
Seems there are some indent format problems in the patch, could you fix them :) ``` patch:509: indent with spaces. x_save_size = riscv_stack_align (num_multi_push * UNITS_PER_WORD); error: patch failed: gcc/config/riscv/riscv.cc:5652 error: gcc/config/riscv/riscv.cc: patch does not apply ``` -原始邮件- 发件人: "Fei Gao" 发送时间: 2023-06-07 13:52:12 (星期三) 收件人: gcc-patches@gcc.gnu.org 抄送: kito.ch...@gmail.com, pal...@dabbelt.com, jeffreya...@gmail.com, sinan@linux.alibaba.com, jia...@iscas.ac.cn, "Fei Gao" 主题: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp Zcmp can share the same logic as save-restore in stack allocation: pre-allocation by cm.push, step 1 and step 2. please be noted cm.push pushes ra, s0-s11 in reverse order than what save-restore does. So adaption has been done in .cfi directives in my patch. Signed-off-by: Fei Gao gcc/ChangeLog: * config/riscv/iterators.md slot0_offset: slot 0 offset in stack GPRs area in bytes slot1_offset: slot 1 offset in stack GPRs area in bytes slot2_offset: likewise slot3_offset: likewise slot4_offset: likewise slot5_offset: likewise slot6_offset: likewise slot7_offset: likewise slot8_offset: likewise slot9_offset: likewise slot10_offset: likewise slot11_offset: likewise slot12_offset: likewise * config/riscv/predicates.md (stack_push_up_to_ra_operand): predicates of stack adjust pushing ra (stack_push_up_to_s0_operand): predicates of stack adjust pushing ra, s0 (stack_push_up_to_s1_operand): likewise (stack_push_up_to_s2_operand): likewise (stack_push_up_to_s3_operand): likewise (stack_push_up_to_s4_operand): likewise (stack_push_up_to_s5_operand): likewise (stack_push_up_to_s6_operand): likewise (stack_push_up_to_s7_operand): likewise (stack_push_up_to_s8_operand): likewise (stack_push_up_to_s9_operand): likewise (stack_push_up_to_s11_operand): likewise (stack_pop_up_to_ra_operand): predicates of stack adjust poping ra (stack_pop_up_to_s0_operand): predicates of stack adjust poping ra, s0 (stack_pop_up_to_s1_operand): likewise (stack_pop_up_to_s2_operand): likewise (stack_pop_up_to_s3_operand): likewise (stack_pop_up_to_s4_operand): likewise (stack_pop_up_to_s5_operand): likewise (stack_pop_up_to_s6_operand): likewise (stack_pop_up_to_s7_operand): likewise (stack_pop_up_to_s8_operand): likewise (stack_pop_up_to_s9_operand): likewise (stack_pop_up_to_s11_operand): likewise * config/riscv/riscv-protos.h (riscv_zcmp_valid_stack_adj_bytes_p):declaration * config/riscv/riscv.cc (struct riscv_frame_info): comment change (riscv_avoid_multi_push): helper function of riscv_use_multi_push (riscv_use_multi_push): true if multi push is used (riscv_multi_push_sregs_count): num of sregs in multi-push (riscv_multi_push_regs_count): num of regs in multi-push (riscv_16bytes_align): align to 16 bytes (riscv_stack_align): moved to a better place (riscv_save_libcall_count): no functional change (riscv_compute_frame_info): add zcmp frame info (riscv_adjust_multi_push_cfi_prologue): adjust cfi for cm.push (riscv_gen_multi_push_pop_insn): gen function for multi push and pop (riscv_expand_prologue): allocate stack by cm.push (riscv_adjust_multi_pop_cfi_epilogue): adjust cfi for cm.pop[ret] (riscv_expand_epilogue): allocate stack by cm.pop[ret] (zcmp_base_adj): calculate stack adjustment base size (zcmp_additional_adj): calculate stack adjustment additional size (riscv_zcmp_valid_stack_adj_bytes_p): check if stack adjustment valid * config/riscv/riscv.h (RETURN_ADDR_MASK): mask of ra (S0_MASK): likewise (S1_MASK): likewise (S2_MASK): likewise (S3_MASK): likewise (S4_MASK): likewise (S5_MASK): likewise (S6_MASK): likewise (S7_MASK): likewise (S8_MASK): likewise (S9_MASK): likewise (S10_MASK): likewise (S11_MASK): likewise (MULTI_PUSH_GPR_MASK): GPR_MASK that cm.push can cover at most (ZCMP_MAX_SPIMM): max spimm value (ZCMP_SP_INC_STEP): zcmp sp increment step (ZCMP_INVALID_S0S10_SREGS_COUNTS): num of s0-s10 (ZCMP_S0S11_SREGS_COUNTS): num of s0-s11 (ZCMP_MAX_GRP_SLOTS): max slots of pushing and poping in zcmp * config/riscv/riscv.md: include zc.md * config/riscv/zc.md: New file. machine description for zcmp gcc/testsuite/ChangeLog: * gcc.target/riscv/rv32e_zcmp.c: New test. * gcc.target/riscv/rv32i_zcmp.c:
Re: Re: [PATCH 2/2] [V3] [RISC-V] support cm.push cm.pop cm.popret in zcmp
Sorry for the late, I will send the binutils patch within this week.
- Original Message -
From: "Kito Cheng"
To: "Fei Gao"
Cc: gcc-patches@gcc.gnu.org, pal...@dabbelt.com, jeffreya...@gmail.com,
sinan@linux.alibaba.com, jia...@iscas.ac.cn
Sent: Mon, 5 Jun 2023 16:31:29 +0800
Subject: Re: [PATCH 2/2] [V3] [RISC-V] support cm.push cm.pop cm.popret in zcmp
Only a few minor comments, otherwise LGTM :)
But I guess we need to wait until binutils merge zc stuff.
> Zcmp can share the same logic as save-restore in stack allocation:
> pre-allocation
> by cm.push, step 1 and step 2.
>
> please be noted cm.push pushes ra, s0-s11 in reverse order than what
> save-restore does.
> So adaption has been done in .cfi directives in my patch.
>
> Signed-off-by: Fei Gao
>
> gcc/ChangeLog:
>
> * config/riscv/iterators.md (-8): slot offset in bytes
> (-16): likewise
> (-24): likewise
> (-32): likewise
> (-40): likewise
> (-48): likewise
> (-56): likewise
> (-64): likewise
> (-72): likewise
> (-80): likewise
> (-88): likewise
> (-96): likewise
> (-104): likewise
Use slot0_offset...slot12_offset.
> @@ -422,6 +430,16 @@ static const struct riscv_tune_info
> riscv_tune_info_table[] = {
> #include "riscv-cores.def"
> };
>
> +typedef enum
> +{
> + PUSH_IDX = 0,
> + POP_IDX,
> + POPRET_IDX,
> + ZCMP_OP_NUM
> +} op_idx;
op_idx -> riscv_zcmp_op_t
> @@ -5388,6 +5487,42 @@ riscv_adjust_libcall_cfi_prologue ()
> return dwarf;
> }
>
> +static rtx
> +riscv_adjust_multi_push_cfi_prologue (int saved_size)
> +{
> + rtx dwarf = NULL_RTX;
> + rtx adjust_sp_rtx, reg, mem, insn;
> + unsigned int mask = cfun->machine->frame.mask;
> + int offset;
> + int saved_cnt = 0;
> +
> + if (mask & S10_MASK)
> + mask |= S11_MASK;
> +
> + for (int regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
> + if (BITSET_P (mask & MULTI_PUSH_GPR_MASK, regno - GP_REG_FIRST))
> + {
> + /* The save order is s11-s0, ra
> + from high to low addr. */
> + offset = saved_size - UNITS_PER_WORD * (++saved_cnt);
> +
> + reg = gen_rtx_REG (SImode, regno);
Should be Pmode rather than SImode, and seems
riscv_adjust_libcall_cfi_prologue has same issue...could you send a
separate patch to fix that?
> + mem = gen_frame_mem (SImode, plus_constant (Pmode,
Same here.
> + stack_pointer_rtx,
> + offset));
> +
> + insn = gen_rtx_SET (mem, reg);
> + dwarf = alloc_reg_note (REG_CFA_OFFSET, insn, dwarf);
> + }
> +
> + /* Debug info for adjust sp. */
> + adjust_sp_rtx = gen_rtx_SET (stack_pointer_rtx,
> + plus_constant(Pmode, stack_pointer_rtx, -saved_size));
> + dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
> + dwarf);
> + return dwarf;
> +}
> +
> static void
> riscv_emit_stack_tie (void)
> {
> @@ -5493,6 +5697,32 @@ riscv_expand_prologue (void)
> }
> }
>
> +static rtx
> +riscv_adjust_multi_pop_cfi_epilogue (int saved_size)
> +{
> + rtx dwarf = NULL_RTX;
> + rtx adjust_sp_rtx, reg;
> + unsigned int mask = cfun->machine->frame.mask;
> +
> + if (mask & S10_MASK)
> + mask |= S11_MASK;
> +
> + /* Debug info for adjust sp. */
> + adjust_sp_rtx = gen_rtx_SET (stack_pointer_rtx,
> + plus_constant(Pmode, stack_pointer_rtx, saved_size));
> + dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
> + dwarf);
> +
> + for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
> + if (BITSET_P (mask, regno - GP_REG_FIRST))
> + {
> + reg = gen_rtx_REG (SImode, regno);
Pmode
> + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
> + }
> +
> + return dwarf;
> +}
> +
> static rtx
> riscv_adjust_libcall_cfi_epilogue ()
> {
> diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
> new file mode 100644
> index 000..f2f2198598c
> --- /dev/null
> +++ b/gcc/config/riscv/zc.md
> @@ -0,0 +1,1042 @@
> +;; Machine description for RISC-V Zc extention.
> +;; Copyright (C) 2011-2023 Free Software Foundation, Inc.
2023 rather than 2011-2023
[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (May 18, 2023)
Hi all, Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any topics want to discuss or share, please change the angenda/notes doc or let me know and I will update them, thanks. https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit# P.S. The meeting calendar .ics file has updated, please check and update it,thanks. Agenda: - New RISC-V ISA spec version - RV64-ILP32 supports introduce - Sub-extensions support status - Open discuss Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Biweekly Sync-up Time: May 18, 2023 UTC+0 15:00 / PST 07:00 / CST 23:00 Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://calendar.google.com/calendar/ical/lm5bddk2krcmtv5iputjgqvoio%40group.calendar.google.com/public/basic.ics Join Zoom Meeting https://zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEIJING, China 23:00pThu, May 18 2023 24:00a Fri, May 18 2023 PST/PDT, Pacific Standard Time (US) 8:00aThu, May 18 2023 9:00aThu, May 18 2023 PHILADELPHIA, United States, Pennsylvania 11:00aThu, May 18 2023 12:00aThu, May 18 2023 Paris, France 17:00pThu, May 18 2023 18:00pThu, May 18 2023BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20230104T023643Z TZURL:https://www.tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230215T105933Z DTSTART;TZID=Asia/Singapore:20230223T23 DTEND;TZID=Asia/Singapore:20230224T00 SUMMARY:RISC-V GNU Toolchain Biweekly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20231228T16;INTERVAL=2;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\nOne tap mobile\n+6531294892\,\,89393600951#\,\,\,\,*899662# Singapore \n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\nDial by your location\n+65 3129 4892 Singapore\n+65 3158 7288 Singapo re\n+65 3165 1065 Singapore\n+65 3129 4891 Singapore\n +1 669 900 9128 US (San Jose)\n+1 669 444 9171 US\n +1 253 215 8782 US (Tacoma)\n+1 346 248 7799 US (Houston)\n +1 719 359 4580 US\n+1 253 205 0468 US\n+1 386 347 5 053 US\n+1 507 473 4847 US\n+1 564 217 2000 US\n +1 646 558 8656 US (New York)\n+1 646 931 3860 US\n+1 68 9 278 1000 US\n+1 301 715 8592 US (Washington DC)\n+1 30 5 224 1968 US\n+1 309 205 3325 US\n+1 312 626 6799 US (C hicago)\n+1 360 209 5623 US\nMeeting ID: 893 9360 0951\nPasscode : 899662\nFind your local number: https://us02web.zoom.us/u/kk9cyIPNJ\n\ n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
[RISC-V] [SIG-toolchain] Meeting will be canceled (May 4, 2023)
Hi all, Tomorrow's meeting will be canceled, since there were few new topics to discuss. The next RISC-V GNU Toolchain meeting is collecting topics: https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit?usp=sharing Please add what want to discuss in the next meeting. GCC 13 released in April 26,you can check changes in the release notes: https://gcc.gnu.org/gcc-13/changes.html Best Regards, Jiawei
RE: [wwwdocs] gcc-13: Add release note for RISC-V
> --- > htdocs/gcc-13/changes.html | 31 ++- > 1 file changed, 30 insertions(+), 1 deletion(-) > > diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html > index f6941534..5427f805 100644 > --- a/htdocs/gcc-13/changes.html > +++ b/htdocs/gcc-13/changes.html > @@ -636,9 +636,32 @@ a work-in-progress. > > RISC-V > > -New ISA extension support for zawrs. > +Supports vector intrinsics as specified in + href="https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/v0.11.x;> > + version 0.11 of the RISC-V vector intrinsic specification, > + thanks Ju-Zhe Zhong from https://rivai-ic.com.cn/;>RiVAI > + for contributing most of implementation. > + > Support for the following vendor extensions has been added: > > + Zawrs > + Zicbom > + Zicboz > + Zicbop > + Zfh > + Zfhmin > + Zmmul > + Zdinx > + Zfinx > + Zhinx > + Zhinxmin > + Zksh > + Zksed > + Zknd > + Zkne > + Zbkb > + Zbkc > + Zbkx > XTheadBa > XTheadBb > XTheadBs > @@ -657,8 +680,14 @@ a work-in-progress. >option (GCC identifiers in parentheses). > > T-Head's XuanTie C906 (thead-c906). > +Ventana's VT1 (ventana-vt1). > > > +Improves the multi-lib selection mechanism for the bare-metal > toolchain > + (riscv*-elf*). GCC will now automatically select the best-fit multi-lib > + candidate instead of requiring all possible reuse rules to be listed at > + build time. > + > > > > -- > 2.39.2LGTM, do we missed the timeline to merge code size reduction extensions > support in > gcc13?https://gcc.gnu.org/pipermail/gcc-patches/2023-April/615287.html
[RISC-V] [SIG-toolchain] Meeting will be canceled (April 20, 2023)
Hi all, Tomorrow's meeting will be canceled, since there were few new topics to discuss. The next RISC-V GNU Toolchain meeting is collecting topics: https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit?usp=sharing Please add what want to discuss in the next meeting. Best Regards, Jiawei
[PATCH 5/5] RISC-V: Add ZCMP push/pop testcases.
Add Zcmp extension testcases, zcmpe means Zcmp with RVE extension.
Co-Authored by: Nandni Jamnadas
Co-Authored by: Yulong Shi
Co-Authored by: Shihua Liao
Co-Authored by: Sinan Lin
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zc-zcmp-push-pop-1.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-2.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-3.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-4.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-5.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-6.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-7.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-1.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-2.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-3.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-4.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-5.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-6.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-7.c: New test.
---
.../gcc.target/riscv/zc-zcmp-push-pop-1.c | 15 +++
.../gcc.target/riscv/zc-zcmp-push-pop-2.c | 17 +
.../gcc.target/riscv/zc-zcmp-push-pop-3.c | 17 +
.../gcc.target/riscv/zc-zcmp-push-pop-4.c | 17 +
.../gcc.target/riscv/zc-zcmp-push-pop-5.c | 17 +
.../gcc.target/riscv/zc-zcmp-push-pop-6.c | 13 +
.../gcc.target/riscv/zc-zcmp-push-pop-7.c | 16
.../gcc.target/riscv/zc-zcmpe-push-pop-1.c | 15 +++
.../gcc.target/riscv/zc-zcmpe-push-pop-2.c | 17 +
.../gcc.target/riscv/zc-zcmpe-push-pop-3.c | 17 +
.../gcc.target/riscv/zc-zcmpe-push-pop-4.c | 17 +
.../gcc.target/riscv/zc-zcmpe-push-pop-5.c | 17 +
.../gcc.target/riscv/zc-zcmpe-push-pop-6.c | 13 +
.../gcc.target/riscv/zc-zcmpe-push-pop-7.c | 16
14 files changed, 224 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-7.c
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-1.c
b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-1.c
new file mode 100644
index 000..58bb39438ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_zca_zcmp -mabi=lp64d -O0" } */
+
+int foo1(int a)
+{
+return a;
+}
+
+int foo2(int b)
+{
+return foo1(b);
+}
+
+/* { dg-final { scan-assembler "cm.push\t{ra,s0},-32" } } */
+/* { dg-final { scan-assembler "cm.popret\t{ra,s0},32" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-2.c
b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-2.c
new file mode 100644
index 000..2c692d80137
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32g_zca_zcmp -mabi=ilp32d -O2" } */
+
+void foo2 (int a, int b);
+
+int foo1(int a, int b)
+{
+if (b < a)
+{
+foo2(a, b);
+foo1(a, b);
+}
+return 0;
+}
+
+/* { dg-final { scan-assembler "cm.push\t{ra,s0-s1},-16" } } */
+/* { dg-final { scan-assembler "cm.popretz\t{ra,s0-s1},16" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-3.c
b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-3.c
new file mode 100644
index 000..ef22ce3d0f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32g_zca_zcmp -mabi=ilp32d -O2" } */
+
+void foo2 (int a, int b, int c, int d);
+
+int foo1(int a, int b, int c, int d)
+{
+if (b < a)
+{
+foo2(a, b, c, d);
+foo1(a, b, c, d);
+}
+return 0;
+}
+
+/* { dg-final { scan-assembler "cm.push\t{ra,s0-s3},-32" } } */
+/* { dg-final { scan-assembler "cm.popretz\t{ra,s0-s3},32" } } */
diff --git
[PATCH 1/5] RISC-V: Minimal support for ZC extensions.
This patch is the minimal support for ZC* extensions, include the extension
name, mask and target defination. Also define the dependencies with Zca
and Zce extension. Notes that all ZC* extensions depend on the Zca extension.
Zce includes all relevant ZC* extensions for microcontrollers using. Zce
will imply zcf when 'f' extension enabled in rv32.
Co-Authored by: Charlie Keaney
Co-Authored by: Mary Bennett
Co-Authored by: Nandni Jamnadas
Co-Authored by: Simon Cook
Co-Authored by: Sinan Lin
Co-Authored by: Shihua Liao
Co-Authored by: Yulong Shi
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_subset_list::parse): New
extensions.
* config/riscv/riscv-opts.h (MASK_ZCA): New mask.
(MASK_ZCB): Ditto.
(MASK_ZCE): Ditto.
(MASK_ZCF): Ditto.
(MASK_ZCD): Ditto.
(MASK_ZCMP): Ditto.
(MASK_ZCMT): Ditto.
(TARGET_ZCA): New target.
(TARGET_ZCB): Ditto.
(TARGET_ZCE): Ditto.
(TARGET_ZCF): Ditto.
(TARGET_ZCD): Ditto.
(TARGET_ZCMP): Ditto.
(TARGET_ZCMT): Ditto.
* config/riscv/riscv.opt: New target variable.
---
gcc/common/config/riscv/riscv-common.cc | 39 +
gcc/config/riscv/riscv-opts.h | 16 ++
gcc/config/riscv/riscv.opt | 3 ++
3 files changed, 58 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 2fc0f8bffc1..933c54edded 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -108,6 +108,16 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zhinx", "zhinxmin"},
{"zhinxmin", "zfinx"},
+ {"zce", "zca"},
+ {"zce", "zcb"},
+ {"zce", "zcmp"},
+ {"zce", "zcmt"},
+ {"zcf", "zca"},
+ {"zcd", "zca"},
+ {"zcb", "zca"},
+ {"zcmp", "zca"},
+ {"zcmt", "zca"},
+
{NULL, NULL}
};
@@ -219,6 +229,14 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zca", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcb", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zce", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcf", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcd", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
{"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1151,14 +1169,26 @@ riscv_subset_list::parse (const char *arch, location_t
loc)
subset_list->handle_implied_ext (itr);
}
+ /* Zce only imply zcf when 'f' extension exist. */
+ if (subset_list->lookup ("zce") != NULL
+ && subset_list->lookup ("f") != NULL
+ && subset_list->lookup ("zcf") == NULL)
+subset_list->add ("zcf", false);
+
subset_list->handle_combine_ext ();
+ if (subset_list->lookup ("zcf") && subset_list->m_xlen == 64)
+error_at (loc, "%<-march=%s%>: zcf extension supports in rv32 only"
+ , arch);
+
if (subset_list->lookup ("zfinx") && subset_list->lookup ("f"))
error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
"extensions", arch);
return subset_list;
+
+
fail:
delete subset_list;
return NULL;
@@ -1262,6 +1292,15 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zmmul", _options::x_riscv_zm_subext, MASK_ZMMUL},
+ /* Code-size reduction extensions. */
+ {"zca", _options::x_riscv_zc_subext, MASK_ZCA},
+ {"zcb", _options::x_riscv_zc_subext, MASK_ZCB},
+ {"zce", _options::x_riscv_zc_subext, MASK_ZCE},
+ {"zcf", _options::x_riscv_zc_subext, MASK_ZCF},
+ {"zcd", _options::x_riscv_zc_subext, MASK_ZCD},
+ {"zcmp",_options::x_riscv_zc_subext, MASK_ZCMP},
+ {"zcmt",_options::x_riscv_zc_subext, MASK_ZCMT},
+
{"svinval", _options::x_riscv_sv_subext, MASK_SVINVAL},
{"svnapot", _options::x_riscv_sv_subext, MASK_SVNAPOT},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index cf0cd669be4..101d87d38b1 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -175,6 +175,22 @@ enum stack_protector_guard {
#define MASK_ZMMUL (1 << 0)
#define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
+#define MASK_ZCA (1 << 0)
+#define MASK_ZCB (1 << 1)
+#define MASK_ZCE (1 << 2)
+#define MASK_ZCF (1 << 3)
+#define MASK_ZCD (1 << 4)
+#define MASK_ZCMP (1 << 5)
+#define MASK_ZCMT (1 << 6)
+
+#define TARGET_ZCA((riscv_zc_subext & MASK_ZCA) != 0)
+#define TARGET_ZCB((riscv_zc_subext & MASK_ZCB) != 0)
+#define TARGET_ZCE((riscv_zc_subext & MASK_ZCE) != 0)
+#define TARGET_ZCF((riscv_zc_subext & MASK_ZCF) != 0)
+#define TARGET_ZCD((riscv_zc_subext & MASK_ZCD) != 0)
+#define TARGET_ZCMP ((riscv_zc_subext & MASK_ZCMP) != 0)
+#define TARGET_ZCMT ((riscv_zc_subext & MASK_ZCMT) != 0)
+
#define MASK_SVINVAL (1 << 0)
#define
[PATCH 4/5] RISC-V: Add Zcmp extension supports.
Add Zcmp extension instructions support. Generate push/pop
with follow steps:
1. preprocessing:
1.1. if there is no push rtx, then just return. e.g.
(note 5 1 22 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 22 5 23 2 (set (reg/f:SI 2 sp)
(plus:SI (reg/f:SI 2 sp)
(const_int -32 [0xffe0])))
(nil))
(note 23 22 2 2 NOTE_INSN_PROLOGUE_END)
1.2. if push rtx exists, then we compute the number of
pushed s-registers, n_sreg.
push rtx should be find before NOTE_INSN_PROLOGUE_END tag
[2 and 3 happend simultaneously]
2. find valid move pattern, mv sN, aN, where N < n_sreg,
and aN is not used the move pattern, and sN is not
defined before the move pattern (from prologue to the
position of move pattern).
3. analysis use and reach of every instruction from prologue
to the position of move pattern.
if any sN is used, then we mark the corresponding argument list
candidate as invalid.
e.g.
push {ra,s0-s3}, {}, -32
sw s0,44(sp) # s0 is used, then argument list is invalid
mv a0,a5 # a0 is defined, then argument list is invalid
...
mv s0,a0
mv s1,a1
mv s2,a2
4. if there is a valid argument list, then replace the pop
push parallel insn, and delete mv pattern.
if not, skip.
All "zcmpe" means Zcmp with RVE extension.
The push/pop instrunction implement is mostly finished by Sinan Lin.
Co-Authored by: Sinan Lin
Co-Authored by: Simon Cook
Co-Authored by: Shihua Liao
gcc/ChangeLog:
* config.gcc: New object.
* config/riscv/predicates.md (riscv_stack_push_operation):
New predicate.
(riscv_stack_pop_operation): Ditto.
(pop_return_value_constant): Ditto.
* config/riscv/riscv-passes.def (INSERT_PASS_AFTER): New pass.
* config/riscv/riscv-protos.h (riscv_output_popret_p):
New routine.
(riscv_valid_stack_push_pop_p): Ditto.
(riscv_check_regno): Ditto.
(make_pass_zcmp_popret): New pass.
* config/riscv/riscv.cc (struct riscv_frame_info): New variable.
(riscv_output_popret_p): New function.
(riscv_print_pop_size): Ditto.
(riscv_print_reglist): Ditto.
(riscv_print_operand): New case symbols.
(riscv_save_push_pop_count): New function.
(riscv_push_pop_base_sp_adjust): Ditto.
(riscv_use_push_pop): Ditto.
(riscv_compute_frame_info): Adjust frame value.
(riscv_emit_pop_insn): New function.
(riscv_check_regno): Ditto.
(riscv_valid_stack_push_pop_p): Ditto.
(riscv_emit_push_insn): Ditto.
(riscv_expand_prologue): Modify frame pattern.
(riscv_expand_epilogue): Ditto.
* config/riscv/riscv.h (RETURN_VALUE_REGNUM):
(RISCV_ZCE_PUSH_POP_MASK): New mask.
(RISCV_ZCMPE_PUSH_POP_MASK): Ditto.
* config/riscv/riscv.md: Add new reg number and include info.
* config/riscv/t-riscv: New object rules.
* config/riscv/riscv-zcmp-popret.cc: New file.
* config/riscv/zc.md: New file.
---
gcc/config.gcc| 2 +-
gcc/config/riscv/predicates.md| 16 +
gcc/config/riscv/riscv-passes.def | 1 +
gcc/config/riscv/riscv-protos.h | 4 +
gcc/config/riscv/riscv-zcmp-popret.cc | 260 +++
gcc/config/riscv/riscv.cc | 437 +-
gcc/config/riscv/riscv.h | 4 +
gcc/config/riscv/riscv.md | 3 +
gcc/config/riscv/t-riscv | 4 +
gcc/config/riscv/zc.md| 47 +++
10 files changed, 767 insertions(+), 11 deletions(-)
create mode 100644 gcc/config/riscv/riscv-zcmp-popret.cc
create mode 100644 gcc/config/riscv/zc.md
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 629d324b5ef..a991c5273f9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -529,7 +529,7 @@ pru-*-*)
;;
riscv*)
cpu_type=riscv
- extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o
riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o"
+ extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o
riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o
riscv-zcmp-popret.o"
extra_objs="${extra_objs} riscv-vector-builtins.o
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o"
d_target_objs="riscv-d.o"
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 0d9d7701c7e..6bff6cd047a 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -412,3 +412,19 @@
(and (match_code "const_int")
(ior (match_operand 0 "not_uimm_extra_bit_operand")
(match_operand 0 "const_nottwobits_operand"
+
+(define_special_predicate "riscv_stack_push_operation"
+ (match_code "parallel")
+{
+ return riscv_valid_stack_push_pop_p (op, true);
+})
+
[PATCH 0/5] RISC-V: Support ZC* extensions.
RISC-V Code Size Reduction(ZC*) extensions is a group of extensions which define subsets of the existing C extension (Zca, Zcd, Zcf) and new extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1] The implementation of the RISC-V Code Size Reduction extension in GCC is an important step towards making the RISC-V architecture more efficient. The cooperation with OpenHW group has played a crucial role in this effort, with facilitating the implementation, testing and validation. Currently works can also find in OpenHW group's github repo.[2] Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the specification, and Jeremy Bennett's patient guidance throughout the whole development process. [1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification [2] github.com/openhwgroup/corev-gcc Co-Authored by: Charlie Keaney Co-Authored by: Mary Bennett Co-Authored by: Nandni Jamnadas Co-Authored by: Sinan Lin Co-Authored by: Simon Cook Co-Authored by: Shihua Liao Co-Authored by: Yulong Shi RISC-V: Minimal support for ZC extensions. RISC-V: Enable compressible features when use ZC* extensions. RISC-V: Add ZC* test for march args being passed. RISC-V: Add Zcmp extension supports. RISC-V: Add ZCMP push/pop testcases. gcc/common/config/riscv/riscv-common.cc | 39 ++ gcc/config.gcc| 2 +- gcc/config/riscv/predicates.md| 16 + gcc/config/riscv/riscv-c.cc | 2 +- gcc/config/riscv/riscv-opts.h | 16 + gcc/config/riscv/riscv-passes.def | 1 + gcc/config/riscv/riscv-protos.h | 4 + gcc/config/riscv/riscv-shorten-memrefs.cc | 3 +- gcc/config/riscv/riscv-zcmp-popret.cc | 260 ++ gcc/config/riscv/riscv.cc | 453 +- gcc/config/riscv/riscv.h | 6 +- gcc/config/riscv/riscv.md | 3 + gcc/config/riscv/riscv.opt| 3 + gcc/config/riscv/t-riscv | 4 + gcc/config/riscv/zc.md| 47 ++ gcc/testsuite/gcc.target/riscv/arch-20.c | 5 + gcc/testsuite/gcc.target/riscv/arch-21.c | 5 + gcc/testsuite/gcc.target/riscv/zc-zca-arch.c | 9 + gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c | 9 + .../gcc.target/riscv/zc-zcb-m-arch.c | 9 + .../gcc.target/riscv/zc-zcb-zba-arch.c| 9 + .../gcc.target/riscv/zc-zcb-zbb-arch.c| 9 + gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c | 9 + gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c | 9 + .../gcc.target/riscv/zc-zcmp-push-pop-1.c | 15 + .../gcc.target/riscv/zc-zcmp-push-pop-2.c | 17 + .../gcc.target/riscv/zc-zcmp-push-pop-3.c | 17 + .../gcc.target/riscv/zc-zcmp-push-pop-4.c | 17 + .../gcc.target/riscv/zc-zcmp-push-pop-5.c | 17 + .../gcc.target/riscv/zc-zcmp-push-pop-6.c | 13 + .../gcc.target/riscv/zc-zcmp-push-pop-7.c | 16 + .../gcc.target/riscv/zc-zcmpe-arch.c | 9 + .../gcc.target/riscv/zc-zcmpe-push-pop-1.c| 15 + .../gcc.target/riscv/zc-zcmpe-push-pop-2.c| 17 + .../gcc.target/riscv/zc-zcmpe-push-pop-3.c| 17 + .../gcc.target/riscv/zc-zcmpe-push-pop-4.c| 17 + .../gcc.target/riscv/zc-zcmpe-push-pop-5.c| 17 + .../gcc.target/riscv/zc-zcmpe-push-pop-6.c| 13 + .../gcc.target/riscv/zc-zcmpe-push-pop-7.c| 16 + gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c | 9 + 40 files changed, 1153 insertions(+), 21 deletions(-) create mode 100644 gcc/config/riscv/riscv-zcmp-popret.cc create mode 100644 gcc/config/riscv/zc.md create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zca-arch.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-2.c create mode
[PATCH 3/5] RISC-V: Add ZC* test for march args being passed.
From: Charlie Keaney
Add all ZC* extensions march args tests.
Co-Authored by: Nandni Jamnadas
Co-Authored by: Jiawei
Co-Authored by: Mary Bennett
Co-Authored by: Simon Cook
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/arch-21.c: New test.
* gcc.target/riscv/zc-zca-arch.c: New test.
* gcc.target/riscv/zc-zcb-arch.c: New test.
* gcc.target/riscv/zc-zcb-m-arch.c: New test.
* gcc.target/riscv/zc-zcb-zba-arch.c: New test.
* gcc.target/riscv/zc-zcb-zbb-arch.c: New test.
* gcc.target/riscv/zc-zcf-arch.c: New test.
* gcc.target/riscv/zc-zcmp-arch.c: New test.
* gcc.target/riscv/zc-zcmpe-arch.c: New test.
* gcc.target/riscv/zc-zcmt-arch.c: New test.
---
gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +
gcc/testsuite/gcc.target/riscv/arch-21.c | 5 +
gcc/testsuite/gcc.target/riscv/zc-zca-arch.c | 9 +
gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c | 9 +
gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c | 9 +
gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c | 9 +
gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c | 9 +
gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c | 9 +
gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c| 9 +
gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c | 9 +
gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c| 9 +
11 files changed, 91 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c
diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c
b/gcc/testsuite/gcc.target/riscv/arch-20.c
new file mode 100644
index 000..3be4ade65a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcf -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" {
target *-*-* } 0 } */
+/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" ""
{ target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-21.c
b/gcc/testsuite/gcc.target/riscv/arch-21.c
new file mode 100644
index 000..cecce06e474
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-21.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zce -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64if_zce': zcf extension supports in rv32 only" "" {
target *-*-* } 0 } */
+/* { dg-error "'-march=rv64if_zca_zcb_zce_zcf_zcmp_zcmt': zcf extension
supports in rv32 only" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
new file mode 100644
index 000..bcb8321e709
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zca -mabi=ilp32" } */
+
+int foo()
+{
+asm("c.sw x9, 32(x10)");
+}
+
+/* { dg-final { scan-assembler "c.sw x9, 32\\(x10\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
new file mode 100644
index 000..54d4dff63ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zcb -mabi=ilp32" } */
+
+int foo()
+{
+asm("c.lbu x9,1(x8)");
+}
+
+/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
new file mode 100644
index 000..f23fe304607
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32im_zcb -mabi=ilp32" } */
+
+int foo()
+{
+asm("c.lbu x9,1(x8)");
+}
+
+/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
new file mode 100644
index 000..6b4a8762078
--- /dev/null
+++ b/gcc/testsuite/gcc.ta
[PATCH 2/5] RISC-V: Enable compressible features when use ZC* extensions.
This patch enables the compressible features with ZC* extensions.
Since all ZC* extension depends on the Zca extension, it's sufficient to only
add the target Zca to extend the target RVC.
Co-Authored by: Mary Bennett
Co-Authored by: Nandni Jamnadas
Co-Authored by: Simon Cook
gcc/ChangeLog:
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Enable compressed builtins when ZC* extensions enabled.
* config/riscv/riscv-shorten-memrefs.cc:
Enable shorten_memrefs pass when ZC* extensions enabled.
* config/riscv/riscv.cc (riscv_compressed_reg_p):
Enable compressible registers when ZC* extensions enabled.
(riscv_rtx_costs):
Allow adjusting rtx costs when ZC* extensions enabled.
(riscv_address_cost):
Allow adjusting address cost when ZC* extensions enabled.
(riscv_first_stack_step):
Allow compression of the register saves without
adding extra instructions.
* config/riscv/riscv.h (FUNCTION_BOUNDARY):
Adjusts function boundary to 16 bits when ZC* extensions enabled.
---
gcc/config/riscv/riscv-c.cc | 2 +-
gcc/config/riscv/riscv-shorten-memrefs.cc | 3 ++-
gcc/config/riscv/riscv.cc | 16 +---
gcc/config/riscv/riscv.h | 2 +-
4 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 6ad562dcb8b..2937c160071 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -47,7 +47,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
{
builtin_define ("__riscv");
- if (TARGET_RVC)
+ if (TARGET_RVC || TARGET_ZCA)
builtin_define ("__riscv_compressed");
if (TARGET_RVE)
diff --git a/gcc/config/riscv/riscv-shorten-memrefs.cc
b/gcc/config/riscv/riscv-shorten-memrefs.cc
index 8f10d24ec39..27803e2c657 100644
--- a/gcc/config/riscv/riscv-shorten-memrefs.cc
+++ b/gcc/config/riscv/riscv-shorten-memrefs.cc
@@ -65,7 +65,8 @@ public:
/* opt_pass methods: */
virtual bool gate (function *)
{
- return TARGET_RVC && riscv_mshorten_memrefs && optimize > 0;
+ return (TARGET_RVC || TARGET_ZCA)
+ && riscv_mshorten_memrefs && optimize > 0;
}
virtual unsigned int execute (function *);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5f542932d13..5f8cbfc15ed 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1118,8 +1118,9 @@ static bool
riscv_compressed_reg_p (int regno)
{
/* x8-x15/f8-f15 are compressible registers. */
- return (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
- || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)));
+ return ((TARGET_RVC || TARGET_ZCA)
+ && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
+ || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)));
}
/* Return true if x is an unsigned 5-bit immediate scaled by 4. */
@@ -2323,8 +2324,9 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
/* When optimizing for size, make uncompressible 32-bit addresses
more expensive so that compressible 32-bit addresses are
preferred. */
- if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
- && !riscv_compressed_lw_address_p (XEXP (x, 0)))
+ if ((TARGET_RVC || TARGET_ZCA) && !speed && riscv_mshorten_memrefs
+ && mode == SImode
+ && !riscv_compressed_lw_address_p (XEXP (x, 0)))
cost++;
*total = COSTS_N_INSNS (cost + tune_param->memory_cost);
@@ -2735,8 +2737,8 @@ riscv_address_cost (rtx addr, machine_mode mode,
{
/* When optimizing for size, make uncompressible 32-bit addresses more
* expensive so that compressible 32-bit addresses are preferred. */
- if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
- && !riscv_compressed_lw_address_p (addr))
+ if ((TARGET_RVC || TARGET_ZCA) && !speed && riscv_mshorten_memrefs
+ && mode == SImode && !riscv_compressed_lw_address_p (addr))
return riscv_address_insns (addr, mode, false) + 1;
return riscv_address_insns (addr, mode, false);
}
@@ -5202,7 +5204,7 @@ riscv_first_stack_step (struct riscv_frame_info *frame)
&& frame_total_constant_size % IMM_REACH >= min_first_step)
return frame_total_constant_size % IMM_REACH;
- if (TARGET_RVC)
+ if (TARGET_RVC || TARGET_ZCA)
{
/* If we need two subtracts, and one is small enough to allow compressed
loads and stores, then put that one first. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 66fb07d6652..d05b1d59853 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -183,7 +183,7 @@ ASM_MISA_SPEC
#define PARM_BOUNDARY BITS_PER_WORD
/* Allocation
Re: Re: [PATCH v2] RISC-V: Add Z*inx imcompatible check in gcc.
-原始邮件-
发件人: "Jeff Law"
发送时间: 2023-04-05 09:30:43 (星期三)
收件人: "Hans-Peter Nilsson" , Jiawei
抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@dabbelt.com,
christoph.muell...@vrull.eu, wuwei2...@iscas.ac.cn
主题: Re: [PATCH v2] RISC-V: Add Z*inx imcompatible check in gcc.
On 4/3/23 19:46, Hans-Peter Nilsson wrote:
On Tue, 28 Mar 2023, Jiawei wrote:
+ // Zfinx is conflict with float extensions.
+ if (TARGET_ZFINX TARGET_HARD_FLOAT)
+error ("z*inx is conflict with float extensions");
+
While I'm not a native English speaker, "is conflict with"
doesn't sound grammatically correct. Perhaps "conflicts with"
or "is in conflict with"?
"conflicts with" is better.
Jeff
Thanks for your reply, fixed in the trunk.
BR,
Jiawei
[Bug target/109384] [13 Regression] unquoted keyword 'float' in format [-Werror=format-diag]
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109384 --- Comment #8 from jiawei --- Thank you for this fix, I neglected to confirm the format, sorry for that.
[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (April 5, 2023)
Hi all, Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any topics want to discuss or share, please change the angenda/notes doc or let me know and I will update them, thanks. https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit# P.S. The meeting calendar .ics file has updated, please check and update it,thanks. Agenda: - RVV gcc support status - Profile toolchain implementation draft - Sub-extensions support status - CI status of currently toolchain - Open discuss Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Biweekly Sync-up Time: Feb 9, 2023 UTC+0 15:00 / PST 07:00 / CST 23:00 Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://calendar.google.com/calendar/ical/lm5bddk2krcmtv5iputjgqvoio%40group.calendar.google.com/public/basic.ics Join Zoom Meeting https://zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEIJING, China 23:00pThu, Apr 6 2023 24:00a Fri, Apr 6 2023 PST/PDT, Pacific Standard Time (US) 8:00aThu, Apr 6 2023 9:00aThu, Apr 6 2023 PHILADELPHIA, United States, Pennsylvania 11:00aThu, Apr 6 2023 12:00aThu, Apr 6 2023 Paris, France 17:00pThu, Apr 6 2023 18:00pThu, Apr 6 2023BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20230104T023643Z TZURL:https://www.tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230215T105933Z DTSTART;TZID=Asia/Singapore:20230223T23 DTEND;TZID=Asia/Singapore:20230224T00 SUMMARY:RISC-V GNU Toolchain Biweekly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20231228T16;INTERVAL=2;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\nOne tap mobile\n+6531294892\,\,89393600951#\,\,\,\,*899662# Singapore \n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\nDial by your location\n+65 3129 4892 Singapore\n+65 3158 7288 Singapo re\n+65 3165 1065 Singapore\n+65 3129 4891 Singapore\n +1 669 900 9128 US (San Jose)\n+1 669 444 9171 US\n +1 253 215 8782 US (Tacoma)\n+1 346 248 7799 US (Houston)\n +1 719 359 4580 US\n+1 253 205 0468 US\n+1 386 347 5 053 US\n+1 507 473 4847 US\n+1 564 217 2000 US\n +1 646 558 8656 US (New York)\n+1 646 931 3860 US\n+1 68 9 278 1000 US\n+1 301 715 8592 US (Washington DC)\n+1 30 5 224 1968 US\n+1 309 205 3325 US\n+1 312 626 6799 US (C hicago)\n+1 360 209 5623 US\nMeeting ID: 893 9360 0951\nPasscode : 899662\nFind your local number: https://us02web.zoom.us/u/kk9cyIPNJ\n\ n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
[PATCH v3] RISC-V: Add Z*inx imcompatible check in gcc
Z*inx is conflict with float extensions, add incompatible check when
z*inx and f extension both enabled.
Since all float extension imply f extension and all z*inx extension
imply zfinx extension, so we just need to check f with zfinx extension
as the base case.
Co-Authored by: Kito Cheng
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
* New check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-19.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 5 +
gcc/testsuite/gcc.target/riscv/arch-19.c | 4
2 files changed, 9 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-19.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index ef221be1eb1..b3c6ec97e7a 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1153,6 +1153,11 @@ riscv_subset_list::parse (const char *arch, location_t
loc)
subset_list->handle_combine_ext ();
+ if (subset_list->lookup("zfinx") && subset_list->lookup("f"))
+ error_at (loc,
+ "%<-march=%s%>: z*inx is conflict with float extensions",
+ arch);
+
return subset_list;
fail:
diff --git a/gcc/testsuite/gcc.target/riscv/arch-19.c
b/gcc/testsuite/gcc.target/riscv/arch-19.c
new file mode 100644
index 000..83c6e00a755
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-19.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zfinx -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64if_zfinx': z\\*inx is conflict with float
extensions" "" { target *-*-* } 0 } */
--
2.25.1
Re: Re: [PATCH v2] RISC-V: Add Z*inx imcompatible check in gcc.
Hi Kito,
Thanks for your sugestions, I had added the new testcases in the new patch.
I feel it's hard to check long string name extension by use
riscv_subset_list::parse,
Since it just check one char when the pointer moving, So I still keep the
implement
by check the extenstison with target. Maybe we can add new check function in
the new
version :)
-原始邮件-
发件人: "Kito Cheng"
发送时间: 2023-03-27 16:15:00 (星期一)
收件人: Jiawei
抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@dabbelt.com,
christoph.muell...@vrull.eu, wuwei2...@iscas.ac.cn
主题: Re: [PATCH] RISC-V: Add Z*inx incompatible check in gcc.
HI Jiawei:
Thanks for the fix!
Two comments:
- Could you add testcase like
https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.target/riscv/arch-12.c
- And I would prefer those check happened in riscv_subset_list::parse
@gcc/common/config/riscv/riscv-common.cc
On Sun, Mar 26, 2023 at 4:36 PM Jiawei wrote:
Z*inx is conflict with float extensions, add incompatible check when
z*inx and hard_float both enabled.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): New check.
---
gcc/config/riscv/riscv.cc | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..162ba14d3c7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6285,6 +6285,10 @@ riscv_option_override (void)
riscv_abi != ABI_LP64 riscv_abi !=
ABI_ILP32E)
error ("z*inx requires ABI ilp32, ilp32e or lp64");
+ // Zfinx is conflict with float extensions.
+ if (TARGET_ZFINX TARGET_HARD_FLOAT)
+error ("z*inx is conflict with float extensions");
+
/* We do not yet support ILP32 on RV64. */
if (BITS_PER_WORD != POINTER_SIZE)
error ("ABI requires %-march=rv%d%", POINTER_SIZE);
--
2.25.1
[PATCH v2] RISC-V: Add Z*inx imcompatible check in gcc.
Z*inx is conflict with float extensions, add incompatible check when
z*inx and hard_float both enabled.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): New check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-19.c: New test.
---
gcc/config/riscv/riscv.cc| 4
gcc/testsuite/gcc.target/riscv/arch-19.c | 4
2 files changed, 8 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-19.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..162ba14d3c7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6285,6 +6285,10 @@ riscv_option_override (void)
&& riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
error ("z*inx requires ABI ilp32, ilp32e or lp64");
+ // Zfinx is conflict with float extensions.
+ if (TARGET_ZFINX && TARGET_HARD_FLOAT)
+error ("z*inx is conflict with float extensions");
+
/* We do not yet support ILP32 on RV64. */
if (BITS_PER_WORD != POINTER_SIZE)
error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
diff --git a/gcc/testsuite/gcc.target/riscv/arch-19.c
b/gcc/testsuite/gcc.target/riscv/arch-19.c
new file mode 100644
index 000..a6f72af3677
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-19.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zfinx -mabi=lp64" } */
+int foo() {}
+/* { dg-error "z*inx is conflict with float extensions" "" { target *-*-* } 0
} */
--
2.25.1
[PATCH] RISC-V: Add Z*inx incompatible check in gcc.
Z*inx is conflict with float extensions, add incompatible check when
z*inx and hard_float both enabled.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): New check.
---
gcc/config/riscv/riscv.cc | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..162ba14d3c7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6285,6 +6285,10 @@ riscv_option_override (void)
&& riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
error ("z*inx requires ABI ilp32, ilp32e or lp64");
+ // Zfinx is conflict with float extensions.
+ if (TARGET_ZFINX && TARGET_HARD_FLOAT)
+error ("z*inx is conflict with float extensions");
+
/* We do not yet support ILP32 on RV64. */
if (BITS_PER_WORD != POINTER_SIZE)
error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
--
2.25.1
[RISC-V] [SIG-toolchain] Meeting will be canceled (March 23, 2023)
Hi all, Tomorrow's meeting will be canceled, since there were few new topics to discuss. The next RISC-V GNU Toolchain meeting is collecting topics: https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit?usp=sharing Please add what want to discuss in the next meeting. Best Regards, Jiawei
[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (Mar 9, 2023)
Hi all, Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any topics want to discuss or share, please change the angenda/notes doc or let me know and I will update them, thanks. https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit# P.S. The meeting calendar .ics file has updated, please check and update it,thanks. Agenda: - Minutes of meeting is available now - RVV gcc support status - Benchmark support/porting status tracing - Sub-extensions support status - Open discuss Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Biweekly Sync-up Time: Feb 9, 2023 UTC+0 15:00 / PST 07:00 / CST 23:00 Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://calendar.google.com/calendar/ical/lm5bddk2krcmtv5iputjgqvoio%40group.calendar.google.com/public/basic.ics Join Zoom Meeting https://zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEIJING, China 23:00pThu, Mar 9 2023 24:00a Fri, Mar 9 2023 PST/PDT, Pacific Standard Time (US) 7:00aThu, Mar 9 2023 8:00aThu, Mar 9 2023 PHILADELPHIA, United States, Pennsylvania 10:00aThu, Mar 9 2023 11:00aThu, Mar 9 2023 Paris, France 16:00pThu, Mar 9 2023 17:00pThu, Mar 9 2023BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20230104T023643Z TZURL:https://www.tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230215T105933Z DTSTART;TZID=Asia/Singapore:20230223T23 DTEND;TZID=Asia/Singapore:20230224T00 SUMMARY:RISC-V GNU Toolchain Biweekly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20231228T16;INTERVAL=2;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\nOne tap mobile\n+6531294892\,\,89393600951#\,\,\,\,*899662# Singapore \n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\nDial by your location\n+65 3129 4892 Singapore\n+65 3158 7288 Singapo re\n+65 3165 1065 Singapore\n+65 3129 4891 Singapore\n +1 669 900 9128 US (San Jose)\n+1 669 444 9171 US\n +1 253 215 8782 US (Tacoma)\n+1 346 248 7799 US (Houston)\n +1 719 359 4580 US\n+1 253 205 0468 US\n+1 386 347 5 053 US\n+1 507 473 4847 US\n+1 564 217 2000 US\n +1 646 558 8656 US (New York)\n+1 646 931 3860 US\n+1 68 9 278 1000 US\n+1 301 715 8592 US (Washington DC)\n+1 30 5 224 1968 US\n+1 309 205 3325 US\n+1 312 626 6799 US (C hicago)\n+1 360 209 5623 US\nMeeting ID: 893 9360 0951\nPasscode : 899662\nFind your local number: https://us02web.zoom.us/u/kk9cyIPNJ\n\ n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
Re: [PATCH] RISC-V: Optimize the MASK opt generation
; MASK_ZVL4096B) != 0)> -#define > TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)> -#define > TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)> -#define > TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)> -#define > TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)> -> -#define > MASK_ZICBOZ (1 << 0)> -#define MASK_ZICBOM (1 << 1)> -#define MASK_ZICBOP > (1 << 2)> -> -#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != > 0)> -#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)> > -#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)> -> -#define > MASK_ZFHMIN (1 << 0)> -#define MASK_ZFH (1 << 1)> -> -#define > TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)> -#define TARGET_ZFH > ((riscv_zf_subext & MASK_ZFH) != 0)> -> -#define MASK_ZMMUL (1 << 0)> > -#define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)> -> -#define > MASK_SVINVAL (1 << 0)> -#define MASK_SVNAPOT (1 << 1)> -> -#define > TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)> -#define > TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)> -> /* Bit of > riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is> set, > e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use> popcount > to caclulate the minimal VLEN. */> diff --git a/gcc/config/riscv/riscv.opt > b/gcc/config/riscv/riscv.opt> index 7c3ca48d1cc..77f553356b1 100644> --- > a/gcc/config/riscv/riscv.opt> +++ b/gcc/config/riscv/riscv.opt> @@ -203,36 > +203,126 @@ long riscv_stack_protector_guard_offset = 0> TargetVariable> > int riscv_zi_subext> > +Mask(ZICSR) in TargetVariable(riscv_zi_subext)> +> > +Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)> +> TargetVariable> int > riscv_za_subext> > +Mask(ZAWRS) in TargetVariable(riscv_za_subext)> +> > TargetVariable> int riscv_zb_subext> > +Mask(ZBA) in > TargetVariable(riscv_zb_subext)> +> +Mask(ZBB) in > TargetVariable(riscv_zb_subext)> +> +Mask(ZBC) in > TargetVariable(riscv_zb_subext)> +> +Mask(ZBS) in > TargetVariable(riscv_zb_subext)> +> TargetVariable> int riscv_zinx_subext> > > +Mask(ZFINX) in TargetVariable(riscv_zinx_subext)> +> +Mask(ZDINX) in > TargetVariable(riscv_zinx_subext)> +> +Mask(ZHINX) in > TargetVariable(riscv_zinx_subext)> +> +Mask(ZHINXMIN) in > TargetVariable(riscv_zinx_subext)> +> TargetVariable> int riscv_zk_subext> > > +Mask(ZBKB) in TargetVariable(riscv_zk_subext)> +> +Mask(ZBKC) in > TargetVariable(riscv_zk_subext)> +> +Mask(ZBKX) in > TargetVariable(riscv_zk_subext)> +> +Mask(ZKNE) in > TargetVariable(riscv_zk_subext)> +> +Mask(ZKND) in > TargetVariable(riscv_zk_subext)> +> +Mask(ZKNH) in > TargetVariable(riscv_zk_subext)> +> +Mask(ZKR) in > TargetVariable(riscv_zk_subext)> +> +Mask(ZKSED) in > TargetVariable(riscv_zk_subext)> +> +Mask(ZKSH) in > TargetVariable(riscv_zk_subext)> +> +Mask(ZKT) in > TargetVariable(riscv_zk_subext)> +> TargetVariable> int > riscv_vector_elen_flags> > +Mask(VECTOR_ELEN_32) in > TargetVariable(riscv_vector_elen_flags)> +> +Mask(VECTOR_ELEN_64) in > TargetVariable(riscv_vector_elen_flags)> +> +Mask(VECTOR_ELEN_FP_32) in > TargetVariable(riscv_vector_elen_flags)> +> +Mask(VECTOR_ELEN_FP_64) in > TargetVariable(riscv_vector_elen_flags)> +> TargetVariable> int > riscv_zvl_flags> > +Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)> +> > +Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL128B) in > TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL256B) in > TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL512B) in > TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL1024B) in > TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL2048B) in > TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL4096B) in > TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL8192B) in > TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL16384B) in > TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL32768B) in > TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL65536B) in > TargetVariable(riscv_zvl_flags)> +> TargetVariable> int riscv_zicmo_subext> > > +Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)> +> +Mask(ZICBOM) in > TargetVariable(riscv_zicmo_subext)> +> +Mask(ZICBOP) in > TargetVariable(riscv_zicmo_subext)> +> TargetVariable>
Re: [PATCH] RISC-V: Optimize the MASK opt generation
/config/riscv/riscv.opt
@@ -203,36 +203,126 @@ long riscv_stack_protector_guard_offset = 0
TargetVariable
int riscv_zi_subext
+Mask(ZICSR) in TargetVariable(riscv_zi_subext)
+
+Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)
+
TargetVariable
int riscv_za_subext
+Mask(ZAWRS) in TargetVariable(riscv_za_subext)
+
TargetVariable
int riscv_zb_subext
+Mask(ZBA) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBB) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBC) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBS) in TargetVariable(riscv_zb_subext)
+
TargetVariable
int riscv_zinx_subext
+Mask(ZFINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZDINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZHINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZHINXMIN) in TargetVariable(riscv_zinx_subext)
+
TargetVariable
int riscv_zk_subext
+Mask(ZBKB) in TargetVariable(riscv_zk_subext)
+
+Mask(ZBKC) in TargetVariable(riscv_zk_subext)
+
+Mask(ZBKX) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKNE) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKND) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKNH) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKR) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKSED) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKSH) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKT) in TargetVariable(riscv_zk_subext)
+
TargetVariable
int riscv_vector_elen_flags
+Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_64) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_32) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_64) in TargetVariable(riscv_vector_elen_flags)
+
TargetVariable
int riscv_zvl_flags
+Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL128B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL256B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL512B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL1024B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL2048B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL4096B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL8192B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL16384B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL32768B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL65536B) in TargetVariable(riscv_zvl_flags)
+
TargetVariable
int riscv_zicmo_subext
+Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
+
TargetVariable
int riscv_zf_subext
+Mask(ZFHMIN) in TargetVariable(riscv_zf_subext)
+
+Mask(ZFH) in TargetVariable(riscv_zf_subext)
+
TargetVariable
int riscv_zm_subext
+Mask(ZMMUL) in TargetVariable(riscv_zm_subext)
+
TargetVariable
int riscv_sv_subext
+Mask(SVINVAL) in TargetVariable(riscv_sv_subext)
+
+Mask(SVNAPOT) in TargetVariable(riscv_sv_subext)
+It looks like a good idea. However, there are still many modules that look
very similar, can we further optimize these codes.BR,Jiawei
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
index 2aee0b9f1c3..9d6080d64a8 100644
--- a/gcc/opt-functions.awk
+++ b/gcc/opt-functions.awk
@@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option,
uinteger_used)
else
return "-1, -1"
}
+
+# Find the index of target variable from extra_target_vars
+function find_index(var, var_arry, n_var_arry)
+{
+for (var_index = 0; var_index < n_var_arry; var_index++)
+{
+if (var_arry[var_index] == var)
+break
+}
+return var_index
+}
\ No newline at end of file
diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
index ce3617c8d4a..ebe48db968b 100644
--- a/gcc/opt-read.awk
+++ b/gcc/opt-read.awk
@@ -22,6 +22,7 @@ BEGIN {
n_opts = 0
n_langs = 0
n_target_save = 0
+ n_target_vars = 0
n_extra_vars = 0
n_extra_target_vars = 0
n_extra_masks = 0
@@ -121,7 +122,20 @@ BEGIN {
n_opts++;
}
else {
- extra_masks[n_extra_masks++] = name
+ if($0 ~ "in")
+ {
+ target_var = opt_args("TargetVariable",
$1)
+ var_index = find_index(target_var,
target_vars, n_target_vars)
+ if (var_index == n_target_vars)
+ {
+ target_vars[n_target_vars++] =
target_var
+ }
+
other_masks[var_index][n_other_mask[var_index]++] = name
+ }
+ else
+
[RISC-V] [SIG-toolchain] Meeting will be canceled (Feb 23, 2023)
Hi all, Tomorrow's meeting will be canceled, since there were few new topics to discuss. The next RISC-V GNU Toolchain meeting is collecting topics: https://docs.google.com/document/d/1JSs-BSlPJ3QYbAb-Add1TlbYx0nOT1ur3jcsITIJ01U/edit?usp=sharing Please add what want to discuss in the next meeting. Best Regards, Jiawei
[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (Feb 9, 2023)
Hi all, Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any topics want to discuss or share, please let me know and I will add them to the agenda, thanks. Agenda: - RVV gcc support progress - Intrinsic naming guidelines - Libsanitizer option support - Profile progress discuss - Sub-extensions support status - Open discuss Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Biweekly Sync-up Time: Feb 9, 2023 UTC+0 15:00 / PST 07:00 / CST 23:00 Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://calendar.google.com/calendar/ical/lm5bddk2krcmtv5iputjgqvoio%40group.calendar.google.com/public/basic.ics Join Zoom Meeting https://zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEIJING, China 23:00pThu, Feb 9 2023 24:00a Fri, Feb 9 2023 PST/PDT, Pacific Standard Time (US) 7:00aThu, Feb 9 2023 8:00aThu, Feb 9 2023 PHILADELPHIA, United States, Pennsylvania 10:00aThu, Feb 9 2023 11:00aThu, Feb 9 2023 Paris, France 16:00pThu, Feb 9 2023 17:00pThu, Feb 9 2023BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20220317T223602Z TZURL:http://tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220713T134316Z DTSTART;TZID=Asia/Singapore:20220714T23 DTEND;TZID=Asia/Singapore:20220715T00 SUMMARY:RISC-V GNU Toolchain Biweekly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20230323T16;INTERVAL=2;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\nOne tap mobile\n+6531651065\,\,89393600951#\,\,\,\,*899662# Singapore \n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\nDial by your location\n+65 3165 1065 Singapore\n+65 3158 7288 Singapo re\n+1 669 900 9128 US (San Jose)\n+1 669 444 9171 US\n +1 346 248 7799 US (Houston)\n+1 253 215 8782 US (Tacoma) \n+1 312 626 6799 US (Chicago)\n+1 646 558 8656 US (New York)\n+1 646 931 3860 US\n+1 301 715 8592 US (Washingto n DC)\nMeeting ID: 893 9360 0951\nPasscode: 899662\nFind your local numb er: https://us02web.zoom.us/u/kk9cyIPNJ\n\n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
[RISC-V] [SIG-toolchain] Meeting will be canceled (Jan 25, 2023)
Hi all, Tomorrow's RISC-V GNU Toolchain meeting will be canceled, since during the Spring Festival holiday. The next RISC-V GNU Toolchain meeting is collecting topics. Please let me know if you have any topics want to discuss in the next meeting. BR Jiawei
[RISC-V] [SIG-toolchain] Meeting will be canceled (Jan 12, 2023)
Hi all, Tomorrow's RISC-V GNU Toolchain meeting will be canceled, since there are few new topics to discuss. The next RISC-V GNU Toolchain meeting is collecting topics. Please let me know if you have any topics want to discuss in the next meeting. BR Jiawei
[Bug target/108185] [RISC-V]RVV assemble not set vsetvli correct.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 --- Comment #3 from jiawei --- (In reply to Kito Cheng from comment #2) > It seems right to me? Yes, It have the same behavior with clang, but it could generate better assemble code like: vl1re8.vv24,0(a0) addi a4,a1,800 vs1r.v v24,0(a1) vsetvli a5,zero,e8,m1,ta,ma vlm v24,0(a0) vsm v24,0(a4) ret > > > ``` > $ riscv64-unknown-elf-gcc pr108185.c -march=rv64gcv -mabi=lp64d -O3 -S -o > - > .file "pr108185.c" > .option nopic > .attribute arch, > "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1 > p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" > .attribute unaligned_access, 0 > .attribute stack_align, 16 > .text > .align 1 > .globl foo5_3 > .type foo5_3, @function > foo5_3: > csrrt0,vlenb > sllit1,t0,1 > csrra5,vlenb > sub sp,sp,t1 > sllia3,a5,1 > add a3,a3,sp > vl1re8.vv25,0(a0) # Load value from *(vint8m1_t*)in > sub a5,a3,a5 > vs1r.v v25,0(a1) # Store value to *(vint8m1_t*)out > vs1r.v v25,0(a5) # Store value to stack, although it's > unused. > addia4,a1,800 > csrrt0,vlenb > sllit1,t0,1 > vsetvli a5,zero,e8,m1,ta,ma # Right vsetvli for vsm.v > vsm.v v25,0(a4) > add sp,sp,t1 > jr ra > .size foo5_3, .-foo5_3 > .ident "GCC: (g44b22ab81cf) 13.0.0 20221229 (experimental)" > ```
[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (Dec 29, 2022)
Hi all, Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any topics want to discuss or share, please let me know and I will add them to the agenda, thanks. Agenda: - RVV gcc support status - Profile progress discuss - Sub-extensions support status - Open discuss Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Biweekly Sync-up Time: Dec 29, 2022 00:00 PM Singapore Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://calendar.google.com/calendar/ical/lm5bddk2krcmtv5iputjgqvoio%40group.calendar.google.com/public/basic.ics Join Zoom Meeting https://zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEIJING, China 00:00pThu, Nov 03 2022 1:00aFri, Nov 03 2022 PST/PDT, Pacific Standard Time (US) 8:00aThu, Nov 03 2022 9:00aThu, Nov 03 2022 PHILADELPHIA, United States, Pennsylvania 11:00aThu, Nov 03 2022 12:00aThu, Nov 03 2022 Paris, France 17:00pThu, Nov 03 2022 18:00pThu, Nov 03 2022BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20220317T223602Z TZURL:http://tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220713T134316Z DTSTART;TZID=Asia/Singapore:20220714T23 DTEND;TZID=Asia/Singapore:20220715T00 SUMMARY:RISC-V GNU Toolchain Biweekly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20230323T16;INTERVAL=2;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\nOne tap mobile\n+6531651065\,\,89393600951#\,\,\,\,*899662# Singapore \n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\nDial by your location\n+65 3165 1065 Singapore\n+65 3158 7288 Singapo re\n+1 669 900 9128 US (San Jose)\n+1 669 444 9171 US\n +1 346 248 7799 US (Houston)\n+1 253 215 8782 US (Tacoma) \n+1 312 626 6799 US (Chicago)\n+1 646 558 8656 US (New York)\n+1 646 931 3860 US\n+1 301 715 8592 US (Washingto n DC)\nMeeting ID: 893 9360 0951\nPasscode: 899662\nFind your local numb er: https://us02web.zoom.us/u/kk9cyIPNJ\n\n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
[Bug target/108185] [RISC-V]RVV assemble not set vsetvli correct.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 jiawei changed: What|Removed |Added Version|13.0|fortran-dev --- Comment #1 from jiawei --- vl1re8.vv25,0(a0) sub a5,a3,a5 vs1r.v v25,0(a1) vs1r.v v25,0(a5) addia4,a1,800 csrrt0,vlenb sllit1,t0,1 vsetvli a5,zero,e8,m1,ta,ma vsm.v v25,0(a4)
[Bug target/108185] New: [RISC-V]RVV assemble not set vsetvli correct.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185
Bug ID: 108185
Summary: [RISC-V]RVV assemble not set vsetvli correct.
Product: gcc
Version: 13.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: jiawei at iscas dot ac.cn
Target Milestone: ---
Currently, when use gcc13 to compile follow code with rvv
extension(-march=rv64gcv -O3),
void foo5_3 (int32_t * restrict in, int32_t * restrict out, size_t n, int
cond)
{
vint8m1_t v = *(vint8m1_t*)in;
*(vint8m1_t*)out = v;
vbool8_t v3 = *(vbool8_t*)in;
*(vbool8_t*)(out + 200) = v3;
}
it will generate asm as:
vl1re8.vv25,0(a0)
sub a5,a3,a5
vs1r.v v25,0(a1)
vs1r.v v25,0(a5)
seems not use vsetvli correctly, any suggestions?
[RISC-V] [SIG-toolchain] Meeting will be canceled (Dec 15, 2022)
Hi all, Tomorrow's meeting will be canceled, since there was few new topics to discuss. The next RISC-V GNU Toolchain meeting is collecting. Please let me know if you have any topics want to discuss in the next meeting. Best Regards, Jiawei
[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (Dec 01, 2022)
Hi all, Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any topics want to discuss or share, please let me know and I will add them to the agenda, thanks. Agenda: - riscv-gnu-toolchain repo's updates - RVV gcc support & RVV c intrinsic api progress - -march option doesn't take ISA strings - New extensions support patches in binutils - ZC* extension support status - Open discuss Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Biweekly Sync-up Time: Dec 01, 2022 11:00 PM Singapore Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://calendar.google.com/calendar/ical/lm5bddk2krcmtv5iputjgqvoio%40group.calendar.google.com/public/basic.ics Join Zoom Meeting https://zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEIJING, China 11:00pThu, Nov 03 2022 12:00aFri, Nov 03 2022 PST/PDT, Pacific Standard Time (US) 7:00aThu, Nov 03 2022 8:00aThu, Nov 03 2022 PHILADELPHIA, United States, Pennsylvania 10:00aThu, Nov 03 2022 11:00aThu, Nov 03 2022 Paris, France 16:00pThu, Nov 03 2022 17:00pThu, Nov 03 2022BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20220317T223602Z TZURL:http://tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220713T134316Z DTSTART;TZID=Asia/Singapore:20220714T23 DTEND;TZID=Asia/Singapore:20220715T00 SUMMARY:RISC-V GNU Toolchain Biweekly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20230323T16;INTERVAL=2;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\nOne tap mobile\n+6531651065\,\,89393600951#\,\,\,\,*899662# Singapore \n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\nDial by your location\n+65 3165 1065 Singapore\n+65 3158 7288 Singapo re\n+1 669 900 9128 US (San Jose)\n+1 669 444 9171 US\n +1 346 248 7799 US (Houston)\n+1 253 215 8782 US (Tacoma) \n+1 312 626 6799 US (Chicago)\n+1 646 558 8656 US (New York)\n+1 646 931 3860 US\n+1 301 715 8592 US (Washingto n DC)\nMeeting ID: 893 9360 0951\nPasscode: 899662\nFind your local numb er: https://us02web.zoom.us/u/kk9cyIPNJ\n\n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
Re: Re: [PATCH] RISC-V: Add RVV registers register spilling
-原始邮件- 发件人: "Jeff Law" 发送时间: 2022-11-21 23:26:37 (星期一) 收件人: "juzhe.zh...@rivai.ai" , schwab 抄送: gcc-patches , "monk.chiang" , "kito.cheng" , jiawei 主题: Re: [PATCH] RISC-V: Add RVV registers register spilling On 11/21/22 02:25, juzhe.zh...@rivai.ai wrote: https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606523.html This patch obviously didn't include scalable size frame. So it ICE in offset = cfun-machine-frame.gp_sp_offset.to_constant (); We can't directly use to_constant if the frame is a scalable. Please fix it or revert it. Thanks We probably just need to reject everything in riscv_get_setparate_components if the offset isn't constant. Something like the attached patch (untested) might be enough to resolve the problem. Jeff I tested this patch and it fix that problem and works well, thanks for you works! Jiawei
[RISC-V] [SIG-toolchain] Meeting will be canceled (Nov 17, 2022)
Hi all, Tomorrow's meeting will be canceled, since there was few new topics to discuss. The next RISC-V GNU Toolchain meeting will be held on Dec 1. Please let me know if you have any topics want to discuss in the next meeting. Best Regards, Jiawei
[PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase.
This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.
---
.../gcc.target/riscv/rvv/base/spill-sp-adjust.c | 13 +
1 file changed, 13 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
new file mode 100644
index 000..0226554abf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv" } */
+
+#include "spill-1.c"
+
+void
+spill_sp_adjust (int8_t *v)
+{
+ vint8mf8_t v1 = *(vint8mf8_t*)v;
+}
+
+/* Make sure we do not have a useless SP adjustment. */
+/* { dg-final { scan-assembler-not "addi\tsp,sp,0" } } */
--
2.25.1
[PATCH v2 2/2] RISC-V: Optimize RVV epilogue logic.
Sometimes "step1 -= scalable_frame" will cause adjust equal to
zero. And it will generate additional redundant instruction
"addi sp,sp,0". Add checking segement to skip that case.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue):
New check segement.
---
gcc/config/riscv/riscv.cc | 35 +++
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 02a01ca0b7c..433b9b13eb6 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5185,25 +5185,28 @@ riscv_expand_epilogue (int style)
step1 -= scalable_frame;
}
- /* Get an rtx for STEP1 that we can add to BASE. */
- rtx adjust = GEN_INT (step1.to_constant ());
- if (!SMALL_OPERAND (step1.to_constant ()))
- {
- riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
- adjust = RISCV_PROLOGUE_TEMP (Pmode);
- }
-
- insn = emit_insn (
- gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
-
- rtx dwarf = NULL_RTX;
- rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+ /* Get an rtx for STEP1 that we can add to BASE.
+ Skip if adjust equal to zero. */
+ if (step1.to_constant () != 0)
+ {
+rtx adjust = GEN_INT (step1.to_constant ());
+if (!SMALL_OPERAND (step1.to_constant ()))
+{
+ riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
+ adjust = RISCV_PROLOGUE_TEMP (Pmode);
+}
+
+insn = emit_insn (
+ gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
+rtx dwarf = NULL_RTX;
+rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
GEN_INT (step2));
- dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
- RTX_FRAME_RELATED_P (insn) = 1;
+dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
+RTX_FRAME_RELATED_P (insn) = 1;
- REG_NOTES (insn) = dwarf;
+REG_NOTES (insn) = dwarf;
+ }
}
else if (frame_pointer_needed)
{
--
2.25.1
[PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.
Current epilogue will generate "addi sp,sp,0" redundant instruction. ``` csrrt0,vlenb sllit1,t0,1 add sp,sp,t1 addisp,sp,0 ld s0,24(sp) addisp,sp,32 jr ra ``` Optimize it by check if adjust equal to zero, remove redundant insn gen. ``` csrrt0,vlenb sllit1,t0,1 add sp,sp,t1 ld s0,24(sp) addisp,sp,32 jr ra ``` Thanks for Kito and Jeff's suggestion, add testcase and fix code format. jiawei (2): RISC-V: Add spill sp adjust check testcase. RISC-V: Optimize RVV epilogue logic. gcc/config/riscv/riscv.cc | 35 ++- .../riscv/rvv/base/spill-sp-adjust.c | 13 +++ 2 files changed, 32 insertions(+), 16 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c -- 2.25.1
Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.
-原始邮件-
发件人: "Kito Cheng"
发送时间: 2022-11-15 09:48:26 (星期二)
收件人: jiawei
抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@rivosinc.com,
juzhe.zh...@rivai.ai, christoph.muell...@vrull.eu, philipp.toms...@vrull.eu,
wuwei2...@iscas.ac.cn
主题: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.
Could you provide some testcase?
Sorry for not giving a clear description，
You can use amost all testcases in gcc.target/riscv/rvv/base/spill-*.c
compile with -march=rv64gcv and check the assemble file spill-*.s,
before this patch, it will generate assemble code contain additional
`addi sp,sp,0`:
```
csrrt0,vlenb
sllit1,t0,1
add sp,sp,t1
addisp,sp,0
ld s0,24(sp)
addisp,sp,32
jr ra
```
after this patch it will removed:
```
csrrt0,vlenb
sllit1,t0,1
add sp,sp,t1
ld s0,24(sp)
addisp,sp,32
jr ra
```
On Tue, Nov 15, 2022 at 12:29 AM jiawei wrote:
Skip add insn generate if the adjust size equal to zero.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue):
New if control segement.
---
gcc/config/riscv/riscv.cc | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 02a01ca0b7c..af138db7545 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style)
}
/* Get an rtx for STEP1 that we can add to BASE. */
- rtx adjust = GEN_INT (step1.to_constant ());
- if (!SMALL_OPERAND (step1.to_constant ()))
+ if (step1.to_constant () != 0){
+rtx adjust = GEN_INT (step1.to_constant ());
+if (!SMALL_OPERAND (step1.to_constant ()))
{
riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
adjust = RISCV_PROLOGUE_TEMP (Pmode);
}
- insn = emit_insn (
+insn = emit_insn (
gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
adjust));
- rtx dwarf = NULL_RTX;
- rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+rtx dwarf = NULL_RTX;
+rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
GEN_INT (step2));
- dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx,
dwarf);
- RTX_FRAME_RELATED_P (insn) = 1;
+dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx,
dwarf);
+RTX_FRAME_RELATED_P (insn) = 1;
- REG_NOTES (insn) = dwarf;
+REG_NOTES (insn) = dwarf;
+ }
}
else if (frame_pointer_needed)
{
--
2.25.1
[PATCH] RISC-V: Optimal RVV epilogue logic.
Skip add insn generate if the adjust size equal to zero.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue):
New if control segement.
---
gcc/config/riscv/riscv.cc | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 02a01ca0b7c..af138db7545 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style)
}
/* Get an rtx for STEP1 that we can add to BASE. */
- rtx adjust = GEN_INT (step1.to_constant ());
- if (!SMALL_OPERAND (step1.to_constant ()))
+ if (step1.to_constant () != 0){
+rtx adjust = GEN_INT (step1.to_constant ());
+if (!SMALL_OPERAND (step1.to_constant ()))
{
riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
adjust = RISCV_PROLOGUE_TEMP (Pmode);
}
- insn = emit_insn (
+insn = emit_insn (
gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
- rtx dwarf = NULL_RTX;
- rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+rtx dwarf = NULL_RTX;
+rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
GEN_INT (step2));
- dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
- RTX_FRAME_RELATED_P (insn) = 1;
+dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
+RTX_FRAME_RELATED_P (insn) = 1;
- REG_NOTES (insn) = dwarf;
+REG_NOTES (insn) = dwarf;
+ }
}
else if (frame_pointer_needed)
{
--
2.25.1
[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (Nov 03, 2022)
Hi all, Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any topics want to discuss or share, please let me know and I will add them to the agenda, thanks. Agenda: - RISC-V profile progress - RVV gcc support progress - Zcmt relaxation and speical section - Open discuss Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Biweekly Sync-up Time: Nov 03, 2022 11:00 PM Singapore Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://calendar.google.com/calendar/ical/lm5bddk2krcmtv5iputjgqvoio%40group.calendar.google.com/public/basic.ics Join Zoom Meeting https://zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEIJING, China 11:00pThu, Nov 03 2022 12:00aFri, Nov 03 2022 PST/PDT, Pacific Standard Time (US) 8:00aThu, Nov 03 2022 9:00aThu, Nov 03 2022 PHILADELPHIA, United States, Pennsylvania 11:00aThu, Nov 03 2022 12:00aThu, Nov 03 2022 Paris, France 17:00pThu, Nov 03 2022 18:00pThu, Nov 03 2022BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20220317T223602Z TZURL:http://tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220713T134316Z DTSTART;TZID=Asia/Singapore:20220714T23 DTEND;TZID=Asia/Singapore:20220715T00 SUMMARY:RISC-V GNU Toolchain Biweekly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20230323T16;INTERVAL=2;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\nOne tap mobile\n+6531651065\,\,89393600951#\,\,\,\,*899662# Singapore \n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\nDial by your location\n+65 3165 1065 Singapore\n+65 3158 7288 Singapo re\n+1 669 900 9128 US (San Jose)\n+1 669 444 9171 US\n +1 346 248 7799 US (Houston)\n+1 253 215 8782 US (Tacoma) \n+1 312 626 6799 US (Chicago)\n+1 646 558 8656 US (New York)\n+1 646 931 3860 US\n+1 301 715 8592 US (Washingto n DC)\nMeeting ID: 893 9360 0951\nPasscode: 899662\nFind your local numb er: https://us02web.zoom.us/u/kk9cyIPNJ\n\n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
[RFC] RISC-V: Add profile supports.
Add two new function to handle profile input,
"parse_profile" will check if a input into -march is
legal, if it is then "handle_profile" will check the
profile's type[I/M/A], year[20/22] and mode[U/S/M],
set different extensions combine, just deal mandatory
part currently.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse_profile): Check if profile name is valid or
not.
(riscv_subset_list::parse_std_ext): If input of -march option is
a profile,skip first ISA check.
(riscv_subset_list::parse): Handle rofile input in -march.
(riscv_subset_list::handle_profile): Handle differen profiles
expand to extensions.
* config/riscv/riscv-subset.h: New function prototypes.
---
gcc/common/config/riscv/riscv-common.cc | 95 +++--
gcc/config/riscv/riscv-subset.h | 5 +-
2 files changed, 94 insertions(+), 6 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 602491c638d..da06bd89144 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -777,6 +777,35 @@ riscv_subset_list::parsing_subset_version (const char *ext,
return p;
}
+/* Parsing function for profile.
+
+ Return Value:
+ Points to the end of profile.
+
+ Arguments:
+ `p`: Current parsing position. */
+
+const char *
+riscv_subset_list::parse_profile (const char *p)
+{
+ if(*p == 'I' || *p == 'M' || *p == 'A'){
+p++;
+if(startswith (p, "20") || startswith (p, "22"))
+ p += 2;
+if (*p == 'U' || *p == 'S' || *p == 'M')
+ p++;
+if(startswith (p, "64") || startswith (p, "32")){
+ p += 2;
+ riscv_subset_list::handle_profile(p-6, p-4, p-3);
+ return p;
+}
+ }
+ else
+error_at (m_loc, "%<-march=%s%>: Invalid profile.", m_arch);
+ return NULL;
+}
+
+
/* Parsing function for standard extensions.
Return Value:
@@ -786,7 +815,7 @@ riscv_subset_list::parsing_subset_version (const char *ext,
`p`: Current parsing position. */
const char *
-riscv_subset_list::parse_std_ext (const char *p)
+riscv_subset_list::parse_std_ext (const char *p, bool isprofile)
{
const char *all_std_exts = riscv_supported_std_ext ();
const char *std_exts = all_std_exts;
@@ -795,8 +824,8 @@ riscv_subset_list::parse_std_ext (const char *p)
unsigned minor_version = 0;
char std_ext = '\0';
bool explicit_version_p = false;
-
- /* First letter must start with i, e or g. */
+ if (!isprofile){
+/* First letter must start with i, e or g. */
switch (*p)
{
case 'i':
@@ -850,6 +879,7 @@ riscv_subset_list::parse_std_ext (const char *p)
"% or %", m_arch);
return NULL;
}
+}
while (p != NULL && *p)
{
@@ -1093,6 +1123,7 @@ riscv_subset_list::parse (const char *arch, location_t
loc)
riscv_subset_list *subset_list = new riscv_subset_list (arch, loc);
riscv_subset_t *itr;
const char *p = arch;
+ bool isprofile = false;
if (startswith (p, "rv32"))
{
subset_list->m_xlen = 32;
@@ -1103,15 +1134,26 @@ riscv_subset_list::parse (const char *arch, location_t
loc)
subset_list->m_xlen = 64;
p += 4;
}
+ else if (startswith (p, "RV"))
+{
+ if (startswith (p+6, "64"))
+ subset_list->m_xlen = 64;
+ else
+ subset_list->m_xlen = 32;
+ p += 2;
+ /* Parsing profile name. */
+ p = subset_list->parse_profile (p);
+ isprofile = true;
+}
else
{
- error_at (loc, "%<-march=%s%>: ISA string must begin with rv32 or rv64",
+ error_at (loc, "%<-march=%s%>: ISA string must begin with rv32 , rv64 or
a profile",
arch);
goto fail;
}
/* Parsing standard extension. */
- p = subset_list->parse_std_ext (p);
+ p = subset_list->parse_std_ext (p,isprofile);
if (p == NULL)
goto fail;
@@ -1349,6 +1391,49 @@ riscv_handle_option (struct gcc_options *opts,
}
}
+/* Expand profile with defined mandatory extensions,
+ M-type/mode is emtpy and set as base right now. */
+void riscv_subset_list::handle_profile(const char *profile_type,
+ const char *profile_year,
+ const char *profile_mode)
+{
+ add ("i", false);
+ if(*profile_type == 'A'){
+add ("m", false);
+add ("a", false);
+add ("f", false);
+add ("d", false);
+add ("c", false);
+add ("ziccamoa", false);
+add ("ziccif", false);
+add ("zicclsm", false);
+add ("ziccrse", false);
+add ("zicntr", false);
+add ("zicsr", false);
+
+if(*profile_mode == 'S')
+ add ("zifencei", false);
+
+if(*profile_year == '2')
+{
+ add ("zihintpause", false);
+ add ("zihpm", false);
+ add ("zba", false);
+ add ("zbb", false);
+ add ("zbs", false);
+ add
[RFC] RISC-V: Add profile supports.
Supports RISC-V profiles[1] in -march option, add minimal extension name supports. Default input set the profile is before other formal extensions. Test with -march=RV[I/M/A]2[0/2][U/M/S][64/32]+otherextensions. [1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc jiawei (2): RISC-V: Add minimal supports for new extension in profile. RISC-V: Add profile supports. gcc/common/config/riscv/riscv-common.cc | 115 ++-- gcc/config/riscv/riscv-opts.h | 15 gcc/config/riscv/riscv-subset.h | 5 +- 3 files changed, 129 insertions(+), 6 deletions(-) -- 2.25.1
[RFC] RISC-V: Minimal supports for new extensions in profile.
This patch just add name support contain in profiles.
Set the extension version as 0.1.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extensions.
* config/riscv/riscv-opts.h (MASK_ZICCAMOA): New mask.
(MASK_ZICCIF): Ditto.
(MASK_ZICCLSM): Ditto.
(MASK_ZICCRSE): Ditto.
(MASK_ZICNTR): Ditto.
(MASK_ZIHINTPAUSE): Ditto.
(MASK_ZIHPM): Ditto.
(TARGET_ZICCAMOA): New target.
(TARGET_ZICCIF): Ditto.
(TARGET_ZICCLSM): Ditto.
(TARGET_ZICCRSE): Ditto.
(TARGET_ZICNTR): Ditto.
(TARGET_ZIHINTPAUSE): Ditto.
(TARGET_ZIHPM): Ditto.
(MASK_SVPBMT): New mask.
---
gcc/common/config/riscv/riscv-common.cc | 20
gcc/config/riscv/riscv-opts.h | 15 +++
2 files changed, 35 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index d6404a01205..602491c638d 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -163,6 +163,15 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
+ {"ziccamoa", ISA_SPEC_CLASS_NONE, 0, 1},
+ {"ziccif", ISA_SPEC_CLASS_NONE, 0, 1},
+ {"zicclsm", ISA_SPEC_CLASS_NONE, 0, 1},
+ {"ziccrse", ISA_SPEC_CLASS_NONE, 0, 1},
+ {"zicntr", ISA_SPEC_CLASS_NONE, 0, 1},
+
+ {"zihintpause", ISA_SPEC_CLASS_NONE, 0, 1},
+ {"zihpm", ISA_SPEC_CLASS_NONE, 0, 1},
+
{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -219,6 +228,7 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
{"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"svpbmt", ISA_SPEC_CLASS_NONE, 0, 1},
/* Terminate the list. */
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
@@ -1179,6 +1189,14 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zicsr",_options::x_riscv_zi_subext, MASK_ZICSR},
{"zifencei", _options::x_riscv_zi_subext, MASK_ZIFENCEI},
+ {"ziccamoa", _options::x_riscv_zi_subext, MASK_ZICCAMOA},
+ {"ziccif", _options::x_riscv_zi_subext, MASK_ZICCIF},
+ {"zicclsm", _options::x_riscv_zi_subext, MASK_ZICCLSM},
+ {"ziccrse", _options::x_riscv_zi_subext, MASK_ZICCRSE},
+ {"zicntr", _options::x_riscv_zi_subext, MASK_ZICNTR},
+
+ {"zihintpause", _options::x_riscv_zi_subext, MASK_ZIHINTPAUSE},
+ {"zihpm", _options::x_riscv_zi_subext, MASK_ZIHPM},
{"zba",_options::x_riscv_zb_subext, MASK_ZBA},
{"zbb",_options::x_riscv_zb_subext, MASK_ZBB},
@@ -1230,6 +1248,7 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zvl1024b", _options::x_riscv_zvl_flags, MASK_ZVL1024B},
{"zvl2048b", _options::x_riscv_zvl_flags, MASK_ZVL2048B},
{"zvl4096b", _options::x_riscv_zvl_flags, MASK_ZVL4096B},
+
{"zvl8192b", _options::x_riscv_zvl_flags, MASK_ZVL8192B},
{"zvl16384b", _options::x_riscv_zvl_flags, MASK_ZVL16384B},
{"zvl32768b", _options::x_riscv_zvl_flags, MASK_ZVL32768B},
@@ -1242,6 +1261,7 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"svinval", _options::x_riscv_sv_subext, MASK_SVINVAL},
{"svnapot", _options::x_riscv_sv_subext, MASK_SVNAPOT},
+ {"svpbmt", _options::x_riscv_sv_subext, MASK_SVPBMT},
{NULL, NULL, 0}
};
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1dfe8c89209..906b6280188 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -69,9 +69,23 @@ enum stack_protector_guard {
#define MASK_ZICSR(1 << 0)
#define MASK_ZIFENCEI (1 << 1)
+#define MASK_ZICCAMOA (1 << 2)
+#define MASK_ZICCIF (1 << 3)
+#define MASK_ZICCLSM (1 << 4)
+#define MASK_ZICCRSE (1 << 5)
+#define MASK_ZICNTR (1 << 6)
+#define MASK_ZIHINTPAUSE (1 << 7)
+#define MASK_ZIHPM(1 << 8)
#define TARGET_ZICSR((riscv_zi_subext & MASK_ZICSR) != 0)
#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
+#define TARGET_ZICCAMOA ((riscv_zi_subext & MASK_ZICCAMOA) != 0)
+#define TARGET_ZICCIF ((riscv_zi_subext & MASK_ZICCIF) != 0)
+#define TARGET_ZICCLSM ((riscv_zi_subext & MASK_ZICCLSM) != 0)
+#define TARGET_ZICCRSE ((riscv_zi_subext & MASK_ZICCRSE) != 0)
+#define TARGET_ZICNTR ((riscv_zi_subext & MASK_ZICNTR) != 0)
+#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0)
+#define TARGET_ZIHPM((riscv_zi_subext & MASK_ZIHPM) != 0)
#define MASK_ZBA (1 << 0)
#define MASK_ZBB (1 << 1)
@@ -174,6 +188,7 @@ enum stack_protector_guard {
#define MASK_SVINVAL (1 << 0)
#define MASK_SVNAPOT (1 << 1)
+#define MASK_SVPBMT (1 << 2)
#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
--
2.25.1
[Bug target/107357] [RISC-V]RVV broken with zve32x/f
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357 jiawei changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED |RESOLVED --- Comment #3 from jiawei --- Fixed.
[Bug target/107357] [RISC-V]RVV broken with zve32x/f
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357 --- Comment #2 from jiawei --- Verified, Thanks!
[Bug other/107357] New: [RISC-V]RVV broken with zve32x/f
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357 Bug ID: 107357 Summary: [RISC-V]RVV broken with zve32x/f Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal Priority: P3 Component: other Assignee: unassigned at gcc dot gnu.org Reporter: jiawei at iscas dot ac.cn Target Milestone: --- When build target riscv with arch "rv64gc_zve32x" or "rv64gc_zve32f" it will got an error: /root/riscv-gnu-toolchain/gcc/gcc/simplify-rtx.cc:8369: test_vector_subregs_modes: FAIL: ASSERT_TRUE ((outer_x != (rtx) 0)) cc1: internal compiler error: in fail, at selftest.cc:47 0x1a9f331 selftest::fail(selftest::location const&, char const*) /root/riscv-gnu-toolchain/gcc/gcc/selftest.cc:47 0xf7e430 test_vector_subregs_modes /root/riscv-gnu-toolchain/gcc/gcc/simplify-rtx.cc:8369 0xf7e557 test_vector_subregs_repeating /root/riscv-gnu-toolchain/gcc/gcc/simplify-rtx.cc:8417 0xf84a66 test_vector_subregs /root/riscv-gnu-toolchain/gcc/gcc/simplify-rtx.cc:8466 0xf84a66 test_vector_ops /root/riscv-gnu-toolchain/gcc/gcc/simplify-rtx.cc:8487 0xf84a66 selftest::simplify_rtx_cc_tests() /root/riscv-gnu-toolchain/gcc/gcc/simplify-rtx.cc:8547 0x19b842c selftest::run_tests() /root/riscv-gnu-toolchain/gcc/gcc/selftest-run-tests.cc:115 0xfa7add toplev::run_self_tests() /root/riscv-gnu-toolchain/gcc/gcc/toplev.cc:2184
[v4 PATCH 3/4] RISC-V: Limit regs use for z*inx extension.
From: Jiawei
Limit z*inx abi support with 'ilp32','ilp32e','lp64' only.
Use GPR instead FPR when 'zfinx' enable, Only use even registers
in RV32 when 'zdinx' enable.
Enable FLOAT16 when Zhinx/Zhinxmin enabled.
Co-Authored-By: Sinan Lin.
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_ZFINX ? GR_REGS): Set GPRS
use while Zfinx is enable.
* config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Limit odd
registers use when Zdinx enable in RV32 cases.
(riscv_option_override): New target enable MASK_FDIV.
(riscv_libgcc_floating_mode_supported_p): New error info when
use incompatible arch
(riscv_excess_precision): New target enable FLOAT16.
---
gcc/config/riscv/constraints.md | 5 +++--
gcc/config/riscv/riscv.cc | 21 +
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 8997284f32e..c53e0f38920 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -21,8 +21,9 @@
;; Register constraints
-(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
- "A floating-point register (if available).")
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS :
+ (TARGET_ZFINX ? GR_REGS) : NO_REGS"
+ "A floating-point register (if available, reuse GPR as FPR when use zfinx).")
(define_register_constraint "j" "SIBCALL_REGS"
"@internal")
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ad57b995e7b..38631605b2c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5356,6 +5356,13 @@ riscv_hard_regno_mode_ok (unsigned int regno,
machine_mode mode)
!= call_used_or_fixed_reg_p (regno + i))
return false;
+ /* Only use even registers in RV32 ZDINX */
+ if (!TARGET_64BIT && TARGET_ZDINX){
+if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
+ GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
+return !(regno & 1);
+ }
+
return true;
}
@@ -5595,7 +5602,7 @@ riscv_option_override (void)
error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
/* Likewise floating-point division and square root. */
- if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
+ if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit &
MASK_FDIV) == 0)
target_flags |= MASK_FDIV;
/* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
@@ -5641,6 +5648,11 @@ riscv_option_override (void)
if (TARGET_RVE && riscv_abi != ABI_ILP32E)
error ("rv32e requires ilp32e ABI");
+ // Zfinx require abi ilp32,ilp32e or lp64.
+ if (TARGET_ZFINX && riscv_abi != ABI_ILP32
+ && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
+error ("z*inx requires ABI ilp32, ilp32e or lp64");
+
/* We do not yet support ILP32 on RV64. */
if (BITS_PER_WORD != POINTER_SIZE)
error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
@@ -6273,7 +6285,7 @@ riscv_libgcc_floating_mode_supported_p (scalar_float_mode
mode)
precision of the _FloatN type; evaluate all other operations and
constants to the range and precision of the semantic type;
- If we have the zfh extensions then we support _Float16 in native
+ If we have the zfh/zhinx extensions then we support _Float16 in native
precision, so we should set this to 16. */
static enum flt_eval_method
riscv_excess_precision (enum excess_precision_type type)
@@ -6282,8 +6294,9 @@ riscv_excess_precision (enum excess_precision_type type)
{
case EXCESS_PRECISION_TYPE_FAST:
case EXCESS_PRECISION_TYPE_STANDARD:
- return (TARGET_ZFH ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
-: FLT_EVAL_METHOD_PROMOTE_TO_FLOAT);
+ return ((TARGET_ZFH || TARGET_ZHINX || TARGET_ZHINXMIN)
+ ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
+ : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT);
case EXCESS_PRECISION_TYPE_IMPLICIT:
case EXCESS_PRECISION_TYPE_FLOAT16:
return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16;
--
2.25.1
[v4 PATCH 4/4] RISC-V: Add zhinx/zhinxmin testcases.
From: Jiawei
Test zhinx/zhinxmin support, same like with zfh/zfhmin testcases
but use gprs and don't use fmv instruction.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/_Float16-zhinx-1.c: New test.
* gcc.target/riscv/_Float16-zhinx-2.c: New test.
* gcc.target/riscv/_Float16-zhinx-3.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-1.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-2.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-3.c: New test.
---
gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c| 10 ++
gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c| 9 +
gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c| 9 +
gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c | 10 ++
gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c | 10 ++
gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c | 10 ++
6 files changed, 58 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
new file mode 100644
index 000..90172b57e05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+return b;
+}
+
+/* { dg-final { scan-assembler-not "fmv.h" } } */
+/* { dg-final { scan-assembler-times "mv" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
new file mode 100644
index 000..26f01198c97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+/* { dg-final { scan-assembler-not "fadd.h fa" } } */
+/* { dg-final { scan-assembler-times "fadd.h a" 1 } } */
+return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
new file mode 100644
index 000..573913568e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+int foo1 (_Float16 a, _Float16 b)
+{
+/* { dg-final { scan-assembler-not "fgt.h fa" } } */
+/* { dg-final { scan-assembler-times "fgt.ha" 1 } } */
+return a > b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
new file mode 100644
index 000..0070ebf616c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinxmin -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+/* { dg-final { scan-assembler-not "fmv.h" } } */
+/* { dg-final { scan-assembler-not "fmv.s" } } */
+/* { dg-final { scan-assembler-times "mv" 1 } } */
+return b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
new file mode 100644
index 000..17f45a938d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinxmin -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+/* { dg-final { scan-assembler-not "fadd.h" } } */
+/* { dg-final { scan-assembler-not "fadd.s fa" } } */
+/* { dg-final { scan-assembler-times "fadd.s a" 1 } } */
+return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
new file mode 100644
index 000..7a43641a5a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zfhmin -mabi=lp64f -O" } */
+
+int foo1 (_Float16 a, _Float16 b)
+{
+/* { dg-final { scan-assembler-not "fgt.h" } } */
+/* { dg-final { scan-assembler-not "fgt.s fa" } } */
+/* { dg-final { scan-assembler-times "fgt.sa" 1 } } */
+return a > b;
+}
--
2.25.1
[v4 PATCH 2/4] RISC-V: Target support for z*inx extension.
From: Jiawei
Support 'TARGET_ZFINX' with float instruction pattern and builtin function.
Reuse 'TARGET_HADR_FLOAT', 'TARGET_DOUBLE_FLOAT' and 'TARGET_ZHINX' patterns.
gcc/ChangeLog:
* config/riscv/iterators.md (TARGET_ZFINX):New target.
(TARGET_ZDINX): Ditto.
(TARGET_ZHINX): Ditto.
* config/riscv/riscv-builtins.cc (AVAIL): Ditto.
(riscv_atomic_assign_expand_fenv): Ditto.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Ditto.
* config/riscv/riscv.md: Ditto.
---
gcc/config/riscv/iterators.md | 6 +--
gcc/config/riscv/riscv-builtins.cc | 4 +-
gcc/config/riscv/riscv-c.cc| 2 +-
gcc/config/riscv/riscv.md | 78 +++---
4 files changed, 46 insertions(+), 44 deletions(-)
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 39dffabc235..50380ecfac9 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -59,9 +59,9 @@
(define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
;; Iterator for hardware-supported floating-point modes.
-(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
- (DF "TARGET_DOUBLE_FLOAT")
- (HF "TARGET_ZFH")])
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
+ (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
+ (HF "TARGET_ZFH || TARGET_ZHINX")])
;; Iterator for floating-point modes that can be loaded into X registers.
(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
diff --git a/gcc/config/riscv/riscv-builtins.cc
b/gcc/config/riscv/riscv-builtins.cc
index 14865d70955..1534cfd860b 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -87,7 +87,7 @@ struct riscv_builtin_description {
unsigned int (*avail) (void);
};
-AVAIL (hard_float, TARGET_HARD_FLOAT)
+AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX)
AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT)
@@ -322,7 +322,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget
ATTRIBUTE_UNUSED,
void
riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
{
- if (!TARGET_HARD_FLOAT)
+ if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
return;
tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags);
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 78f6eacb068..826ae0067bb 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -61,7 +61,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
if (TARGET_HARD_FLOAT)
builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
- if (TARGET_HARD_FLOAT && TARGET_FDIV)
+ if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV)
{
builtin_define ("__riscv_fdiv");
builtin_define ("__riscv_fsqrt");
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 2d1cda2b98f..09ca91fb2c3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -434,7 +434,7 @@
[(set (match_operand:ANYF0 "register_operand" "=f")
(plus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fadd.\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "")])
@@ -565,7 +565,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fsub.\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "")])
@@ -735,7 +735,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(mult:ANYF (match_operand:ANYF1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT || TARGET_ZFINX"
"fmul.\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "")])
@@ -1042,7 +1042,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_ope
[v4 PATCH 0/4] RISC-V: Support z*inx extensions.
Zfinx extension[1] had already ratified. Here is the implementation patch set that reuse floating point pattern and ban the use of fpr when use z*inx as a target. Current works can be find in follow links, binutils and simulator works already supported on upstream. https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase Thanks for Tariq Kurd, Kito Cheng, Jim Willson, Jeremy Bennett helped us a lot with this work. [1] https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf Version log: v2: As Kito Cheng's comment, add Changelog part in patches, update imply info in riscv-common.c, remove useless check and update annotation in riscv.c. v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as default, fix the lack of fcsr use in zfinx. v4: Rebase patch with upstream, add zhinx/zhinxmin extensions support. Add additional zhinx/zhinxmin same like zfh/zfhmin. Jiawei (4): RISC-V: Minimal support of z*inx extension. RISC-V: Target support for z*inx extension. RISC-V: Limit regs use for z*inx extension. RISC-V: Add zhinx/zhinxmin testcases. gcc/common/config/riscv/riscv-common.cc | 18 + gcc/config/riscv/arch-canonicalize| 5 ++ gcc/config/riscv/constraints.md | 5 +- gcc/config/riscv/iterators.md | 6 +- gcc/config/riscv/riscv-builtins.cc| 4 +- gcc/config/riscv/riscv-c.cc | 2 +- gcc/config/riscv/riscv-opts.h | 10 +++ gcc/config/riscv/riscv.cc | 21 - gcc/config/riscv/riscv.md | 78 ++- gcc/config/riscv/riscv.opt| 3 + .../gcc.target/riscv/_Float16-zhinx-1.c | 10 +++ .../gcc.target/riscv/_Float16-zhinx-2.c | 9 +++ .../gcc.target/riscv/_Float16-zhinx-3.c | 9 +++ .../gcc.target/riscv/_Float16-zhinxmin-1.c| 10 +++ .../gcc.target/riscv/_Float16-zhinxmin-2.c| 10 +++ .../gcc.target/riscv/_Float16-zhinxmin-3.c| 10 +++ 16 files changed, 160 insertions(+), 50 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c -- 2.25.1
[v4 PATCH 1/4] RISC-V: Minimal support of z*inx extension.
From: Jiawei
Minimal support of z*inx extension, include 'zfinx'， 'zdinx' and
'zhinx/zhinxmin'
corresponding to 'f', 'd' and 'zfh/zfhmin', the 'zdinx' will imply 'zfinx'
same as 'd' imply 'f', 'zhinx' will aslo imply 'zfinx', all zfinx extension
imply 'zicsr'.
Co-Authored-By: Sinan Lin.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extensions.
* config/riscv/arch-canonicalize: New imply relations.
* config/riscv/riscv-opts.h (MASK_ZFINX): New mask.
(MASK_ZDINX): Ditto.
(MASK_ZHINX): Ditto.
(MASK_ZHINXMIN): Ditto.
(TARGET_ZFINX): New target.
(TARGET_ZDINX): Ditto.
(TARGET_ZHINX): Ditto.
(TARGET_ZHINXMIN): Ditto.
* config/riscv/riscv.opt: New target variable.
---
gcc/common/config/riscv/riscv-common.cc | 18 ++
gcc/config/riscv/arch-canonicalize | 5 +
gcc/config/riscv/riscv-opts.h | 10 ++
gcc/config/riscv/riscv.opt | 3 +++
4 files changed, 36 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index c39ed2e2696..55f3328df7a 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -51,6 +51,11 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"d", "f"},
{"f", "zicsr"},
{"d", "zicsr"},
+
+ {"zdinx", "zfinx"},
+ {"zfinx", "zicsr"},
+ {"zdinx", "zicsr"},
+
{"zk", "zkn"},
{"zk", "zkr"},
{"zk", "zkt"},
@@ -99,6 +104,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zfh", "zfhmin"},
{"zfhmin", "f"},
+
+ {"zhinx", "zhinxmin"},
+ {"zhinxmin", "zfinx"},
{NULL, NULL}
};
@@ -158,6 +166,11 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zhinx", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zhinxmin", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"zbkb", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbkc", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbkx", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1168,6 +1181,11 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zbc",_options::x_riscv_zb_subext, MASK_ZBC},
{"zbs",_options::x_riscv_zb_subext, MASK_ZBS},
+ {"zfinx",_options::x_riscv_zinx_subext, MASK_ZFINX},
+ {"zdinx",_options::x_riscv_zinx_subext, MASK_ZDINX},
+ {"zhinx",_options::x_riscv_zinx_subext, MASK_ZHINX},
+ {"zhinxmin", _options::x_riscv_zinx_subext, MASK_ZHINXMIN},
+
{"zbkb", _options::x_riscv_zk_subext, MASK_ZBKB},
{"zbkc", _options::x_riscv_zk_subext, MASK_ZBKC},
{"zbkx", _options::x_riscv_zk_subext, MASK_ZBKX},
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-canonicalize
index fd7651ac491..2498db506b7 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -41,6 +41,11 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
IMPLIED_EXT = {
"d" : ["f", "zicsr"],
"f" : ["zicsr"],
+ "zdinx" : ["zfinx", "zicsr"],
+ "zfinx" : ["zicsr"],
+ "zhinx" : ["zhinxmin", "zfinx", "zicsr"],
+ "zhinxmin" : ["zfinx", "zicsr"],
+
"zk" : ["zkn", "zkr", "zkt"],
"zkn" : ["zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"],
"zks" : ["zbkb", "zbkc", "zbkx", "zksed", "zksh"],
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 55e0bc0a0e9..bb2322ad182 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,6 +83,16 @@ enum stack_protector_guard {
#define TARGET_ZBC((riscv_zb_subext & MASK_ZBC) != 0)
#define TARGET_ZBS((riscv_zb_subext & MASK_ZBS) != 0)
+#define MASK_ZFINX (1 << 0)
+#define MASK_ZDINX (1 << 1)
+#define MASK_ZHINX (1 << 2)
+#define MASK_ZHINXMIN (1 << 3)
+
+#define TARGET_ZFINX((riscv_zinx_subext & MASK_ZFINX) != 0)
+#define TARGET_ZDINX((riscv_zinx_subext & MASK_ZDINX) != 0)
+#define TARGET_ZHINX((riscv_zinx_subext & MASK_ZHINX) != 0)
+#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
+
#define MASK_ZBKB (1 << 0)
#define MASK_ZBKC (1 << 1)
#define MASK_ZBKX (1 << 2)
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 8923a11a97d..7c1e0ed5f2d 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -206,6 +206,9 @@ int riscv_zi_subext
TargetVariable
int riscv_zb_subext
+TargetVariable
+int riscv_zinx_subext
+
TargetVariable
int riscv_zk_subext
--
2.25.1
[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (Oct 20, 2022)
Hi all, Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any topics want to discuss or share, please let me know and I will add them to the agenda, thanks. Agenda: - RISC-V profile develop plan - Patchwork for patch initial review - RISC-V sub-extension supports progress RVV gcc support progress Zc* extension support progress - Open discuss Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Biweekly Sync-up Time: Oct 20, 2022 11:00 PM Singapore Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://calendar.google.com/calendar/ical/lm5bddk2krcmtv5iputjgqvoio%40group.calendar.google.com/public/basic.ics Join Zoom Meeting https://zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEIJING, China 11:00pThu, Oct 20 2022 12:00aFri, Oct 20 2022 PST/PDT, Pacific Standard Time (US) 8:00aThu, Oct 20 2022 9:00aThu, Oct 20 2022 PHILADELPHIA, United States, Pennsylvania 11:00aThu, Oct 20 2022 12:00aThu, Oct 20 2022 Paris, France 17:00pThu, Oct 20 2022 18:00pThu, Oct 20 2022BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20220317T223602Z TZURL:http://tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220713T134316Z DTSTART;TZID=Asia/Singapore:20220714T23 DTEND;TZID=Asia/Singapore:20220715T00 SUMMARY:RISC-V GNU Toolchain Biweekly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20230323T16;INTERVAL=2;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\nOne tap mobile\n+6531651065\,\,89393600951#\,\,\,\,*899662# Singapore \n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\nDial by your location\n+65 3165 1065 Singapore\n+65 3158 7288 Singapo re\n+1 669 900 9128 US (San Jose)\n+1 669 444 9171 US\n +1 346 248 7799 US (Houston)\n+1 253 215 8782 US (Tacoma) \n+1 312 626 6799 US (Chicago)\n+1 646 558 8656 US (New York)\n+1 646 931 3860 US\n+1 301 715 8592 US (Washingto n DC)\nMeeting ID: 893 9360 0951\nPasscode: 899662\nFind your local numb er: https://us02web.zoom.us/u/kk9cyIPNJ\n\n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
[RISC-V] [SIG-toolchain] Meeting will be canceled (Sep 22, 2022)
Hi all, Tomorrow's meeting will be canceled, since there was few new topics to discuss. The next RISC-V GNU Toolchain meeting will be held on Oct 6. Please let me know if you have any topics want to discuss in the next meeting. Best Regards, Jiawei
Re: [PATCH] RISC-V: Don't try to vectorize tree-ssa/gen-vect-34.c
LGTM, Maybe we can try is after RVV supported.> We don't yet support
vectorization on RISC-V.
> > gcc/testsuite/ChangeLog> > * gcc.dg/tree-ssa/gen-vect-34.c: Skip RISC-V
> > targets.> ---> gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c | 2 +-> 1 file
> > changed, 1 insertion(+), 1 deletion(-)> > diff --git
> > a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c
> > b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c> index
> > 8d2d36401fe..41877e05efd 100644> ---
> > a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c> +++
> > b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c> @@ -13,4 +13,4 @@ float
> > summul(int n, float *arg1, float *arg2)> return res1;
> > > }> > -/* { dg-final { scan-tree-dump-times
> > "vectorized 1 loops" 1 "vect" { target { ! { avr-*-* pru-*-* } } } } } */>
> > +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {
> > target { ! { avr-*-* pru-*-* riscv*-*-* } } } } } */> -- > 2.34.1
[V2 PATCH] RISC-V:Add '-m[no]-csr-check' option in gcc.
From: Jiawei
Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option,
it will add csr-check in .option section and pass this to assembler.
V2: Add assembler support check info for -mcsr-check. Thanks for Kito's
suggestions.
gcc/ChangeLog:
* config.in: New def.
* config/riscv/riscv.cc (riscv_file_start): New .option.
* config/riscv/riscv.opt: New options.
* configure.ac: New check.
* doc/invoke.texi: New def.
---
gcc/config.in | 6 ++
gcc/config/riscv/riscv.cc | 5 +
gcc/config/riscv/riscv.opt | 6 ++
gcc/configure.ac | 5 +
gcc/doc/invoke.texi| 6 ++
5 files changed, 28 insertions(+)
diff --git a/gcc/config.in b/gcc/config.in
index 9c53319b544..a4c39e1384d 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -616,6 +616,12 @@
#endif
+/* Define if your assembler supports -mcsr-check. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_AS_MCSR_CHECK
+#endif
+
+
/* Define if your Mac OS X assembler supports -mllvm -x86-pad-for-align=false.
*/
#ifndef USED_FOR_TARGET
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 675d92c0961..e98e6b1f561 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5135,6 +5135,11 @@ riscv_file_start (void)
if (! riscv_mrelax)
fprintf (asm_out_file, "\t.option norelax\n");
+ /* If the user specifies "-mcsr-check" on the command line then enable csr
+ check in the assembler. */
+ if (riscv_mcsr_check)
+fprintf (asm_out_file, "\t.option csr-check\n");
+
if (riscv_emit_attribute_p)
riscv_emit_attribute ();
}
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index fbca91b956c..3a12dd47310 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -132,6 +132,12 @@ Target Bool Var(riscv_mrelax) Init(1)
Take advantage of linker relaxations to reduce the number of instructions
required to materialize symbol addresses.
+mcsr-check
+Target Bool Var(riscv_mcsr_check) Init(1)
+Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
+The ISA-dependent CSR are only valid when the specific ISA is set. The
+read-only CSR can not be written by the CSR instructions.
+
Mask(64BIT)
Mask(MUL)
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 50bb61c1b61..1a9288ee659 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5269,6 +5269,11 @@ configured with --enable-newlib-nano-formatted-io.])
[-march=rv32i_zifencei2p0],,,
[AC_DEFINE(HAVE_AS_MARCH_ZIFENCEI, 1,
[Define if the assembler understands -march=rv*_zifencei.])])
+gcc_GAS_CHECK_FEATURE([-mcsr-check],
+ gcc_cv_as_riscv_csr_check,
+ [-mcsr-check],,,
+ [AC_DEFINE(HAVE_AS_MCSR_CHECK, 1,
+[Define if the assembler understands -mcsr-check.])])
;;
loongarch*-*-*)
gcc_GAS_CHECK_FEATURE([.dtprelword support],
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dd3302fcd15..7caade26b94 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1224,6 +1224,7 @@ See RS/6000 and PowerPC Options.
-mbig-endian -mlittle-endian @gol
-mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol
-mstack-protector-guard-offset=@var{offset}}
+-mcsr-check -mno-csr-check @gol
@emph{RL78 Options}
@gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs @gol
@@ -28551,6 +28552,11 @@ linker relaxations.
Emit (do not emit) RISC-V attribute to record extra information into ELF
objects. This feature requires at least binutils 2.32.
+@item -mcsr-check
+@itemx -mno-csr-check
+@opindex mcsr-check
+Enables or disables the CSR checking.
+
@item -malign-data=@var{type}
@opindex malign-data
Control how GCC aligns variables and constants of array, structure, or union
--
2.34.1
[PATCH] RISC-V:Add '-m[no]-csr-check' option in gcc.
From: Jiawei
Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option,
it will add csr-check in .option section and pass this to assembler.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_file_start): New .option.
* config/riscv/riscv.opt: New options.
* doc/invoke.texi: New definations.
---
gcc/config/riscv/riscv.cc | 5 +
gcc/config/riscv/riscv.opt | 6 ++
gcc/doc/invoke.texi| 6 ++
3 files changed, 17 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 675d92c0961..e98e6b1f561 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5135,6 +5135,11 @@ riscv_file_start (void)
if (! riscv_mrelax)
fprintf (asm_out_file, "\t.option norelax\n");
+ /* If the user specifies "-mcsr-check" on the command line then enable csr
+ check in the assembler. */
+ if (riscv_mcsr_check)
+fprintf (asm_out_file, "\t.option csr-check\n");
+
if (riscv_emit_attribute_p)
riscv_emit_attribute ();
}
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index fbca91b956c..3a12dd47310 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -132,6 +132,12 @@ Target Bool Var(riscv_mrelax) Init(1)
Take advantage of linker relaxations to reduce the number of instructions
required to materialize symbol addresses.
+mcsr-check
+Target Bool Var(riscv_mcsr_check) Init(1)
+Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
+The ISA-dependent CSR are only valid when the specific ISA is set. The
+read-only CSR can not be written by the CSR instructions.
+
Mask(64BIT)
Mask(MUL)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dd3302fcd15..7caade26b94 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1224,6 +1224,7 @@ See RS/6000 and PowerPC Options.
-mbig-endian -mlittle-endian @gol
-mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol
-mstack-protector-guard-offset=@var{offset}}
+-mcsr-check -mno-csr-check @gol
@emph{RL78 Options}
@gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs @gol
@@ -28551,6 +28552,11 @@ linker relaxations.
Emit (do not emit) RISC-V attribute to record extra information into ELF
objects. This feature requires at least binutils 2.32.
+@item -mcsr-check
+@itemx -mno-csr-check
+@opindex mcsr-check
+Enables or disables the CSR checking.
+
@item -malign-data=@var{type}
@opindex malign-data
Control how GCC aligns variables and constants of array, structure, or union
--
2.34.1
[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (Sep 08, 2022)
Hi all, Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any topics want to discuss or share, please let me know and I will add them to the agenda, thanks. Agenda: - Bump riscv-gnu-toolchain repo's submodules - RISC-V sub-extension supports progress RVV gcc support progress ZFH gcc support progress Zmmul support progress AIA support patches - Open topics RISC-V RVV C Intrinsic Vendor extension patches Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Biweekly Sync-up Time: Sep 08, 2022 11:00 PM Singapore Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://calendar.google.com/calendar/ical/lm5bddk2krcmtv5iputjgqvoio%40group.calendar.google.com/public/basic.ics Join Zoom Meeting https://zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEIJING, China 11:00pThu, Sep 08 2022 12:00aFri, Sep 08 2022 PST/PDT, Pacific Standard Time (US) 8:00aThu, Sep 08 2022 9:00aThu, Sep 08 2022 PHILADELPHIA, United States, Pennsylvania 11:00aThu, Sep 08 2022 12:00aThu, Sep 08 2022 Paris, France 17:00pThu, Aug 11 2022 18:00pThu, Aug 11 2022BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20220317T223602Z TZURL:http://tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220713T134316Z DTSTART;TZID=Asia/Singapore:20220714T23 DTEND;TZID=Asia/Singapore:20220715T00 SUMMARY:RISC-V GNU Toolchain Biweekly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20230323T16;INTERVAL=2;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\nOne tap mobile\n+6531651065\,\,89393600951#\,\,\,\,*899662# Singapore \n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\nDial by your location\n+65 3165 1065 Singapore\n+65 3158 7288 Singapo re\n+1 669 900 9128 US (San Jose)\n+1 669 444 9171 US\n +1 346 248 7799 US (Houston)\n+1 253 215 8782 US (Tacoma) \n+1 312 626 6799 US (Chicago)\n+1 646 558 8656 US (New York)\n+1 646 931 3860 US\n+1 301 715 8592 US (Washingto n DC)\nMeeting ID: 893 9360 0951\nPasscode: 899662\nFind your local numb er: https://us02web.zoom.us/u/kk9cyIPNJ\n\n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
[RISC-V] [SIG-toolchain] Meeting will be canceled (Agust 25, 2022)
Hi all, Tommorrow's meeting will be canceled, since it during 2022 RISC-V Summit China . The next RISC-V GNU toolchian meeting will be held on Sep 8. Please let me know if you have any topics want to discuss in the next meeting. Best Regards, Jiawei
[Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in do_SUBST in C++ code
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106586 jiawei changed: What|Removed |Added CC||jiawei at iscas dot ac.cn --- Comment #7 from jiawei --- I had roll back the RISC-V commit and found that this modification cause this building failure. https://gcc.gnu.org/git/?p=gcc.git;a=blobdiff;f=gcc/config/riscv/riscv.h;h=6f7f4d3fbdcfa6c8ca03604fbe5817aad6278e2e;hp=5083a1c24b08233810dd3b2aa4278b3ef8a75791;hb=4e72ccad80d69a76d149fba59603b8173fffe8fe;hpb=d19b4342c19e5a7fd84888aa06ebc106438d0c46 But I am not sure what's wrong with it, any suggestions?
Re: [RISC-V] [tech-toolchain] Fw: [RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (Aug 11, 2022)
BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20220317T223602Z TZURL:http://tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220713T134316Z DTSTART;TZID=Asia/Singapore:20220714T23 DTEND;TZID=Asia/Singapore:20220715T00 SUMMARY:RISC-V GNU Toolchain Biweekly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20230323T16;INTERVAL=2;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\nOne tap mobile\n+6531651065\,\,89393600951#\,\,\,\,*899662# Singapore \n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\nDial by your location\n+65 3165 1065 Singapore\n+65 3158 7288 Singapo re\n+1 669 900 9128 US (San Jose)\n+1 669 444 9171 US\n +1 346 248 7799 US (Houston)\n+1 253 215 8782 US (Tacoma) \n+1 312 626 6799 US (Chicago)\n+1 646 558 8656 US (New York)\n+1 646 931 3860 US\n+1 301 715 8592 US (Washingto n DC)\nMeeting ID: 893 9360 0951\nPasscode: 899662\nFind your local numb er: https://us02web.zoom.us/u/kk9cyIPNJ\n\n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (Aug 11, 2022)
Hi all, Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any topics want to discuss or share, please let me know and I will add them to the agenda, thanks. Agenda: - Call for contributors/maintainers: riscv-gnu-toolchain repo - Unify interface to query supported option for extension https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/24 - RVV supports progress - Open topics Zbs build failure on RV32 Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Biweekly Sync-up Time: Aug 11, 2022 11:00 PM Singapore Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://calendar.google.com/calendar/ical/lm5bddk2krcmtv5iputjgqvoio%40group.calendar.google.com/public/basic.ics Join Zoom Meeting https://zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEIJING, China 11:00pThu, Aug 11 2022 12:00aFri, Aug 11 2022 PST/PDT, Pacific Standard Time (US) 8:00aThu, Aug 11 2022 9:00aThu, Aug 11 2022 PHILADELPHIA, United States, Pennsylvania 11:00aThu, Aug 11 2022 12:00aThu, Aug 11 2022 Paris, France 17:00pThu, Aug 11 2022 18:00pThu, Aug 11 2022BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20220317T223602Z TZURL:http://tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220713T141948Z DTSTART;TZID=Asia/Singapore:20220714T15 DTEND;TZID=Asia/Singapore:20220714T16 SUMMARY:RISC-V GNU å·¥å ·é¾åå¨åæ¥ä¼ï¼ä¸æï¼ RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20230323T08;INTERVAL=2;BYDAY=TH UID:ZOOM82424890125 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/82424890125?pwd=SVpvYk p0ZlJ2aG5CTzNJeWU2Qzdvdz09\n\nMeeting ID: 824 2489 0125\nPasscode: 53310 0\nOne tap mobile\n+6531651065\,\,82424890125#\,\,\,\,*533100# Singapore \n+6531587288\,\,82424890125#\,\,\,\,*533100# Singapore\n\nDial by your location\n+65 3165 1065 Singapore\n+65 3158 7288 Singapo re\n+1 669 900 9128 US (San Jose)\n+1 669 444 9171 US\n +1 346 248 7799 US (Houston)\n+1 253 215 8782 US (Tacoma) \n+1 646 931 3860 US\n+1 301 715 8592 US (Washington DC) \n+1 312 626 6799 US (Chicago)\n+1 646 558 8656 US (New York)\nMeeting ID: 824 2489 0125\nPasscode: 533100\nFind your local numb er: https://us02web.zoom.us/u/kd9elwl9Jv\n\n LOCATION:https://us02web.zoom.us/j/82424890125?pwd=SVpvYkp0ZlJ2aG5CTzNJeW U2Qzdvdz09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
Re: Re: [PATCH] testsuite: Add extra RISC-V options so that -fprefetch-loop-arrays works
-原始邮件-
发件人: "Richard Biener"
发送时间: 2022-07-28 15:45:27 (星期四)
收件人: jiawei
抄送: gcc-patches@gcc.gnu.org, ja...@redhat.com, pal...@rivosinc.com,
kito.ch...@gmail.com, jim.wilson@gmail.com, wuwei2...@iscas.ac.cn
主题: Re: [PATCH] testsuite: Add extra RISC-V options so that
-fprefetch-loop-arrays works
On Thu, 28 Jul 2022, jiawei wrote:
This patch adds the additional options on RISC-V target.
"-fprefetch-loop-arrays" option needs enable prefetch instruction,
for RISC-V that contained in "zicbop" extension.
Use "-march" with "zicbop" will enable this feature.
OK.
Note -fprefetch-loop-arrays is just required to trigger an ICE,
do you see a diagnostic when prefetching is not supported? Maybe
simply adding -w is better then.
Yes, without -march support it report warning info:
cc1: warning: '-fprefetch-loop-arrays' not supported for this target (try
'-march' switches)
after add -w the warning ignored.
gcc/testsuite/ChangeLog:
* gcc.dg/pr106397.c: New dg-additional-options for RISC-V.
---
gcc/testsuite/gcc.dg/pr106397.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/pr106397.c
b/gcc/testsuite/gcc.dg/pr106397.c
index 2bc17f8cf80..19274fa8771 100644
--- a/gcc/testsuite/gcc.dg/pr106397.c
+++ b/gcc/testsuite/gcc.dg/pr106397.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0
--param prefetch-latency=3 -fprefetch-loop-arrays" } */
/* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-*
x86_64-*-* } ia32 } } } */
+/* { dg-additional-options "-march=rv64gc_zicbop" { target {
riscv64-*-* } } */
+/* { dg-additional-options "-march=rv32gc_zicbop" { target {
riscv32-*-* } } */
int
bar (void)
--
Richard Biener
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman;
HRB 36809 (AG Nuernberg)
[PATCH] testsuite: Add extra RISC-V options so that -fprefetch-loop-arrays works
This patch adds the additional options on RISC-V target.
"-fprefetch-loop-arrays" option needs enable prefetch instruction,
for RISC-V that contained in "zicbop" extension.
Use "-march" with "zicbop" will enable this feature.
gcc/testsuite/ChangeLog:
* gcc.dg/pr106397.c: New dg-additional-options for RISC-V.
---
gcc/testsuite/gcc.dg/pr106397.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
index 2bc17f8cf80..19274fa8771 100644
--- a/gcc/testsuite/gcc.dg/pr106397.c
+++ b/gcc/testsuite/gcc.dg/pr106397.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param
prefetch-latency=3 -fprefetch-loop-arrays" } */
/* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-*
x86_64-*-* } && ia32 } } } */
+/* { dg-additional-options "-march=rv64gc_zicbop" { target { riscv64-*-* } } */
+/* { dg-additional-options "-march=rv32gc_zicbop" { target { riscv32-*-* } } */
int
bar (void)
--
2.25.1
[RISCV] RISC-V GNU Toolchain Meeting Cancell (July, 28, 2022)
Hi all, Tomorrow meeting will cancel since there are few new topics to discuss. The next meeting will be two weeks later, and we are collecting the themes. If you have any questions want to discuss please mail me and I will add it into the agenda for next meeting. Best wishes, Jiawei
Re: [RFC] RISC-V: Add support for RV64E/lp64e
gcc/ChangeLog
* config.gcc (riscv): Accept rv64e and lp64e.
* config/riscv/arch-canonicalize: Likewise.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Likewise.
* config/riscv/riscv-opts.h (riscv_abi_type): Likewise.
* config/riscv/riscv.cc (riscv_option_override): Likewise
* config/riscv/riscv.h (UNITS_PER_FP_ARG): Likewise.
(STACK_BOUNDARY): Likewise.
(ABI_STACK_BOUNDARY): Likewise.
(MAX_ARGS_IN_REGISTERS): Likewise.
(ABI_SPEC): Likewise.
* config/riscv/riscv.opt (abi_type): Likewise.
* doc/invoke.texi (RISC-V) <-mabi>: Likewise.
---
This is all still in flight, but evidently RV64E exists. I haven't
tested this at all, but given that we don't even have the ABI docs lined
up yet it's likely a bit away from being mergable.
---
gcc/config.gcc | 8 +---
gcc/config/riscv/arch-canonicalize | 2 +-
gcc/config/riscv/riscv-c.cc| 1 +
gcc/config/riscv/riscv-opts.h | 1 +
gcc/config/riscv/riscv.cc | 6 --
gcc/config/riscv/riscv.h | 11 +++
gcc/config/riscv/riscv.opt | 3 +++
gcc/doc/invoke.texi| 5 +++--
8 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 4e3b15bb5e9..4617ecb8d9b 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4637,7 +4637,7 @@ case "${target}" in
# Infer arch from --with-arch, --target, and --with-abi.
case "${with_arch}" in
-rv32e* | rv32i* | rv32g* | rv64i* | rv64g*)
+rv32e* | rv32i* | rv32g* | rv64e* | rv64i* | rv64g*)
# OK.
;;
"")
@@ -4645,12 +4645,13 @@ case "${target}" in
case "${with_abi}" in
ilp32e) with_arch="rv32e" ;;
ilp32 | ilp32f | ilp32d) with_arch="rv32gc" ;;
+lp64e) with_arch="rv64e" ;;
lp64 | lp64f | lp64d) with_arch="rv64gc" ;;
*) with_arch="rv${xlen}gc" ;;
esac
;;
*)
-echo "--with-arch=${with_arch} is not supported. The argument must begin
with rv32e, rv32i, rv32g, rv64i, or rv64g." 1>&2
+echo "--with-arch=${with_arch} is not supported. The argument must begin
with rv32e, rv32i, rv32g, rv64e, rv64i, or rv64g." 1>&2
exit 1
;;
esac
@@ -4672,6 +4673,7 @@ case "${target}" in
rv32e*) with_abi=ilp32e ;;
rv32*) with_abi=ilp32 ;;
rv64*d* | rv64g*) with_abi=lp64d ;;
+rv64e*) with_abi=lp64e ;;
rv64*) with_abi=lp64 ;;
esac
;;
@@ -4687,7 +4689,7 @@ case "${target}" in
ilp32,rv32* | ilp32e,rv32e* \
| ilp32f,rv32*f* | ilp32f,rv32g* \
| ilp32d,rv32*d* | ilp32d,rv32g* \
-| lp64,rv64* \
+| lp64,rv64* | lp64e,rv64e* \
| lp64f,rv64*f* | lp64f,rv64g* \
| lp64d,rv64*d* | lp64d,rv64g*)
;;
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-canonicalize
index fd7651ac491..8db3e88ddd7 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -71,7 +71,7 @@ def arch_canonicalize(arch, isa_spec):
new_arch = ""
extra_long_ext = []
std_exts = []
- if arch[:5] in ['rv32e', 'rv32i', 'rv32g', 'rv64i', 'rv64g']:
+ if arch[:5] in ['rv32e', 'rv32i', 'rv32g', 'rv64e', 'rv64i', 'rv64g']:
new_arch = arch[:5].replace("g", "i")
if arch[:5] in ['rv32g', 'rv64g']:
std_exts = ['m', 'a', 'f', 'd']
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index eb7ef09297e..4614dc6b6d9 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -67,6 +67,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
switch (riscv_abi)
{
case ABI_ILP32E:
+case ABI_LP64E:
builtin_define ("__riscv_abi_rve");
gcc_fallthrough ();
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1e153b3a6e7..70fe708cbae 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -27,6 +27,7 @@ enum riscv_abi_type {
ABI_ILP32F,
ABI_ILP32D,
ABI_LP64,
+ ABI_LP64E,
ABI_LP64F,
ABI_LP64D
};
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2e83ca07394..51b7195c17b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5047,8 +5047,10 @@ riscv_option_override (void)
error ("requested ABI requires %<-march%> to subsume the %qc
extension",
UNITS_PER_FP_ARG > 8 ? 'Q' : (UNITS_PER_FP_ARG > 4 ? 'D' : 'F'));
- if (TARGET_RVE && riscv_abi != ABI_ILP32E)
+ if (riscv_xlen == 32 && TARGET_RVE && riscv_abi != ABI_ILP32E)
error ("rv32e requires ilp32e ABI");
+ if (riscv_xlen == 64 && TARGET_RVE && riscv_abi != ABI_LP64E)
+error ("rv64e requires lp64e ABI");
Hi Palmer, I just run this patch and report unresolve the symbol "riscv_xlen"
here,
maybe we can use "!TARGET_64BIT" and "TARGET_64BIT" to instead of them, thanks.
/* We do not yet support ILP32 on RV64. */
if (BITS_PER_WORD != POINTER_SIZE)
@@ -5140,7 +5142,7 @@ riscv_conditional_register_usage (void)
fixed_regs[r] = 1;
}
- if (riscv_abi == ABI_ILP32E)
+ if (riscv_abi == ABI_ILP32E ||
[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (July 14, 2022)
Hi all, Here is the agenda for tomorrow's RISC-V GNU toolchain meeting. If you have any topics want to discuss or share, please let me know and I will add them to the agenda, thanks. Agenda: - [RFC] RV64E/lp64e supports gcc: https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598307.html gas: https://sourceware.org/pipermail/binutils/2022-July/121785.html - RISC-V sub-extension supports status Zfh supports on gcc S-extension supports on binutils Zmmul extension supports - RVV supports progress - Open topics How can we get what extesnions supported set with toolchain that without a source code? Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting. Topic: RISC-V GNU Toolchain Biweekly Sync-up Time: July 14, 2022 11:00 PM Singapore Please download and import the following iCalendar (.ics) files to your calendar system. Weekly: https://zoom.us/meeting/tZ0ufuqurjsjH9XTthkNg3MffX-QsRBuVBET/ics?icsToken=98tyKuGhrTIpHNSVuRyGRpx5A4r4b-7ziGJEgvplqAvtCA5UMS7wMNoPA6FNMs3m Join Zoom Meeting https://zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZjZZMHhRQT09 Meeting ID: 893 9360 0951 Passcode: 899662 BEIJING, China 11:00pThu, July 14 2022 12:00aFri, July 14 2022 PST/PDT, Pacific Standard Time (US) 8:00aThu, July 14 2022 9:00aThu, July 14 2022 PHILADELPHIA, United States, Pennsylvania 11:00aThu, July 14 2022 12:00aThu, July 14 2022 Paris, France 17:00pThu, July 14 2022 18:00pThu, July 14 2022BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:Asia/Singapore LAST-MODIFIED:20201011T015911Z TZURL:http://tzurl.org/zoneinfo-outlook/Asia/Singapore X-LIC-LOCATION:Asia/Singapore BEGIN:STANDARD TZNAME:+08 TZOFFSETFROM:+0800 TZOFFSETTO:+0800 DTSTART:19700101T00 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220309T112636Z DTSTART;TZID=Asia/Singapore:20220310T23 DTEND;TZID=Asia/Singapore:20220311T00 SUMMARY:RISC-V GNU Toolchain Biweekly Sync-up RRULE:FREQ=WEEKLY;WKST=SU;UNTIL=20220630T16;INTERVAL=2;BYDAY=TH UID:ZOOM89393600951 TZID:Asia/Singapore DESCRIPTION:Wei Wu - PLCT Lab is inviting you to a scheduled Zoom meeting .\n\nJoin Zoom Meeting\nhttps://us02web.zoom.us/j/89393600951?pwd=ZFpWMk Z6Tm1TbUFXT1hZZjZZMHhRQT09\n\nMeeting ID: 893 9360 0951\nPasscode: 89966 2\nOne tap mobile\n+6531651065\,\,89393600951#\,\,\,\,*899662# Singapore \n+6531587288\,\,89393600951#\,\,\,\,*899662# Singapore\n\nDial by your location\n+65 3165 1065 Singapore\n+65 3158 7288 Singapo re\n+1 669 900 9128 US (San Jose)\n+1 346 248 7799 US (H ouston)\n+1 253 215 8782 US (Tacoma)\n+1 312 626 6799 US (Chicago)\n+1 646 558 8656 US (New York)\n+1 301 715 85 92 US (Washington DC)\nMeeting ID: 893 9360 0951\nPasscode: 899662\nFind your local number: https://us02web.zoom.us/u/kk9cyIPNJ\n\n LOCATION:https://us02web.zoom.us/j/89393600951?pwd=ZFpWMkZ6Tm1TbUFXT1hZZj ZZMHhRQT09 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR
