Re: subreg against register allocation?
Quoting Ian Lance Taylor i...@google.com: Hmmm, you could be right. I wrote and tested some examples when working on lower-subreg, but I never committed them. The current define_splits in i386.md which can do parallel sets only run if reload_completed is true, when simplify_gen_subreg will return different hard registers. While I don't know of any reason that it wouldn't work, I guess I don't know for sure that it is safe. On targets with different register sizes, subregs are not useful before reload to describe what happens with the smaller registers; because of the uncertainty of the register allocation, the semantics are still undefined. It would really be useful if we replaced STRICT_LOW_PART with something like STRICT_SUBREG to refer to parts of a REG like SUBREG, but always leave the rest of the register alone.
Re: subreg against register allocation?
Amker.Cheng amker.ch...@gmail.com writes: here are three more questions 1 , If I am talking the right thing, there are two insns like *mulsi3_1 and *smulsi3_highpart_insn, which set two parts of DImode pseudo regs of DImode mult. Since both parts pf result are used in the original example, I am not sure how to make split pattern to handle this case without generating two duplicate mult insns in parallel. The idea is that you would have a single insn which sets two registers in parallel, one to the high part of the mult and one to the low part. 2 , If I could set the two parts of result in parallel insn, I also have to handle mips specific constraints in this case, i.e, constraints for HI/LO registers. Unfortunately, There is no h constraint now according to patch http://gcc.gnu.org/ml/gcc-patches/2008-05/msg01750.html It is not possible to write hi reg without clobbering the lo reg now, How should I handle this? That is kind of a fatal problem for this approach. You would have to reintroduce the h constraint, I guess. 3 , Since I am studying IRA right now, I am very curious about whether possible to solve this in IRA. e.g, by shrinking live ranges of multi-word pseudo regs? I don't know. My intuition is that it would be better to keep subreg splitting separate from IRA, to avoid overcomplicating IRA. Ian
Re: subreg against register allocation?
Jeff Law l...@redhat.com writes: Note that lower-subreg is rather conservative when determining what subregs to lower, particularly when the pseudo appears in different modes (ie, some accesses are via SUBREGs, others are naked REGs). So this approach may not necessarily work. Right; it only works if all uses of the subreg can be split. Ian
Re: subreg against register allocation?
Bernd Schmidt wrote: On 06/15/2010 12:06 AM, Ian Lance Taylor wrote: Well, as you know, subregs have two meanings which look similar but are in fact entirely different. It's valid to set subregs of the same pseudo in parallel if the subregs represent different hard registers. It's not valid if the subregs represent different pieces of the same hard register. Are you aware of any examples of this in the compiler? The explanation is of course plausible, but do we know that we handle this correctly everywhere? I ran into problems trying to do this on s390; that's why e.g. the divmod patterns now look like [(set (match_operand:TI 0 register_operand =d,d) (ior:TI (ashift:TI (zero_extend:TI (mod:DI (match_operand:DI 1 register_operand 0,0) (match_operand:DI 2 general_operand d,RT))) (const_int 64)) (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)] instead of a parallel set of two subregs. In particular, there seemed to be problems with dataflow not recognizing a parallel set of two subregs as actually fully setting the whole register ... But of course, that was a long time ago, maybe the new dataflow mechanism has fixed this now. Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com
Re: subreg against register allocation?
Amker.Cheng amker.ch...@gmail.com writes: Wondering whether possible to handle multi-word mode with more accuracy, in either subreg or IRA pass? Yes, it is possible. What you need to do is to write a split which turns the mult:DI insn into an insn which sets two separate subregs. The values for the two subregs will be written as shifts and truncates of the mult:DI; see, e.g., smulmode3_highpart in i386.md. If you do that, then with luck the second lower subreg pass will be able to pull apart the values, and IRA will allocate them independently. You want to write it as a split so that the RTL CSE and combine passes see the mult:DI, in case they can do anything with it. Ian
Re: subreg against register allocation?
On 06/14/2010 07:58 PM, Ian Lance Taylor wrote: Amker.Cheng amker.ch...@gmail.com writes: Wondering whether possible to handle multi-word mode with more accuracy, in either subreg or IRA pass? Yes, it is possible. What you need to do is to write a split which turns the mult:DI insn into an insn which sets two separate subregs. Is it valid to have an insn set two different subregs of the same pseudo in parallel? I have the same problem on ARM, but I couldn't convince myself that writing such a split was safe so I'm currently trying to solve the problem in the register allocator. Bernd
Re: subreg against register allocation?
Bernd Schmidt ber...@codesourcery.com writes: On 06/14/2010 07:58 PM, Ian Lance Taylor wrote: Amker.Cheng amker.ch...@gmail.com writes: Wondering whether possible to handle multi-word mode with more accuracy, in either subreg or IRA pass? Yes, it is possible. What you need to do is to write a split which turns the mult:DI insn into an insn which sets two separate subregs. Is it valid to have an insn set two different subregs of the same pseudo in parallel? I have the same problem on ARM, but I couldn't convince myself that writing such a split was safe so I'm currently trying to solve the problem in the register allocator. Well, as you know, subregs have two meanings which look similar but are in fact entirely different. It's valid to set subregs of the same pseudo in parallel if the subregs represent different hard registers. It's not valid if the subregs represent different pieces of the same hard register. Ian
Re: subreg against register allocation?
On 06/15/2010 12:06 AM, Ian Lance Taylor wrote: Well, as you know, subregs have two meanings which look similar but are in fact entirely different. It's valid to set subregs of the same pseudo in parallel if the subregs represent different hard registers. It's not valid if the subregs represent different pieces of the same hard register. Are you aware of any examples of this in the compiler? The explanation is of course plausible, but do we know that we handle this correctly everywhere? Bernd
Re: subreg against register allocation?
Bernd Schmidt ber...@codesourcery.com writes: On 06/15/2010 12:06 AM, Ian Lance Taylor wrote: Well, as you know, subregs have two meanings which look similar but are in fact entirely different. It's valid to set subregs of the same pseudo in parallel if the subregs represent different hard registers. It's not valid if the subregs represent different pieces of the same hard register. Are you aware of any examples of this in the compiler? The explanation is of course plausible, but do we know that we handle this correctly everywhere? Hmmm, you could be right. I wrote and tested some examples when working on lower-subreg, but I never committed them. The current define_splits in i386.md which can do parallel sets only run if reload_completed is true, when simplify_gen_subreg will return different hard registers. While I don't know of any reason that it wouldn't work, I guess I don't know for sure that it is safe. Ian
Re: subreg against register allocation?
Ian Lance Taylor wrote: Well, as you know, subregs have two meanings which look similar but are in fact entirely different. It's valid to set subregs of the same pseudo in parallel if the subregs represent different hard registers. Are you aware of any examples of this in the compiler? The explanation is of course plausible, but do we know that we handle this correctly everywhere? Hmmm, you could be right. Of course, if we think this *should* work in principle (i.e., that it makes sense for this to be meaningful RTL), and we don't know that it doesn't work, it's reasonable to put this into GCC, changing the documentation to specify the semantics of this form of RTL, and then fixing any bugs as they occur. Thanks, -- Mark Mitchell CodeSourcery m...@codesourcery.com (650) 331-3385 x713
Re: subreg against register allocation?
Thanks for explanation. here are three more questions 1 , If I am talking the right thing, there are two insns like *mulsi3_1 and *smulsi3_highpart_insn, which set two parts of DImode pseudo regs of DImode mult. Since both parts pf result are used in the original example, I am not sure how to make split pattern to handle this case without generating two duplicate mult insns in parallel. 2 , If I could set the two parts of result in parallel insn, I also have to handle mips specific constraints in this case, i.e, constraints for HI/LO registers. Unfortunately, There is no h constraint now according to patch http://gcc.gnu.org/ml/gcc-patches/2008-05/msg01750.html It is not possible to write hi reg without clobbering the lo reg now, How should I handle this? 3 , Since I am studying IRA right now, I am very curious about whether possible to solve this in IRA. e.g, by shrinking live ranges of multi-word pseudo regs? PS, maybe I am talking gibberish, Sorry If not clear enough. Thanks. -- Best Regards.
Re: subreg against register allocation?
On 06/14/10 11:58, Ian Lance Taylor wrote: Amker.Chengamker.ch...@gmail.com writes: Wondering whether possible to handle multi-word mode with more accuracy, in either subreg or IRA pass? Yes, it is possible. What you need to do is to write a split which turns the mult:DI insn into an insn which sets two separate subregs. The values for the two subregs will be written as shifts and truncates of the mult:DI; see, e.g.,smulmode3_highpart in i386.md. If you do that, then with luck the second lower subreg pass will be able to pull apart the values, and IRA will allocate them independently. You want to write it as a split so that the RTL CSE and combine passes see the mult:DI, in case they can do anything with it. Note that lower-subreg is rather conservative when determining what subregs to lower, particularly when the pseudo appears in different modes (ie, some accesses are via SUBREGs, others are naked REGs). So this approach may not necessarily work. jeff
