[Bug target/100093] different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100093 Hongtao.liu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED |RESOLVED --- Comment #4 from Hongtao.liu --- Fixed in GCC12.
[Bug target/100093] different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100093 --- Comment #3 from CVS Commits --- The master branch has been updated by hongtao Liu : https://gcc.gnu.org/g:342de04d993beaa644d0b0087c20bef5dad5bf5f commit r12-78-g342de04d993beaa644d0b0087c20bef5dad5bf5f Author: liuhongt Date: Fri Apr 16 11:29:10 2021 +0800 MASK_AVX256_SPLIT_UNALIGNED_STORE/LOAD should be cleared in opts->x_target_flags when X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL is enabled by target attribute. gcc/ChangeLog: PR target/100093 * config/i386/i386-options.c (ix86_option_override_internal): Clear MASK_AVX256_SPLIT_UNALIGNED_LOAD/STORE in x_target_flags when X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL is enabled by target attribute. gcc/testsuite/ChangeLog: PR target/100093 * gcc.target/i386/pr100093.c: New test.
[Bug target/100093] different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100093 --- Comment #2 from Hongtao.liu --- Created attachment 50611 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=50611=edit tested patch waiting for GCC12. [i386] MASK_AVX256_SPLIT_UNALIGNED_STORE/LOAD should be cleared in opts->x_target_flags when X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL is enabled by target attribute. gcc/ChangeLog: PR target/10093 * config/i386/i386-options.c (ix86_option_override_internal): Clear MASK_AVX256_SPLIT_UNALIGNED_LOAD/STORE in x_target_flags when X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL is enabled by target attribute. gcc/testsuite/ChangeLog: PR target/10093 * gcc.target/i386/pr10093.c: New test. 2 files changed, 19 insertions(+) gcc/config/i386/i386-options.c | 7 +++ gcc/testsuite/gcc.target/i386/pr10093.c | 12 modified gcc/config/i386/i386-options.c @@ -2853,9 +2853,16 @@ ix86_option_override_internal (bool main_args_p, if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL] && !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_LOAD)) opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_LOAD; + else if (!main_args_p + && ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL]) +opts->x_target_flags &= ~MASK_AVX256_SPLIT_UNALIGNED_LOAD; + if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL] && !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_STORE)) opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE; + else if (!main_args_p + && ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL]) +opts->x_target_flags &= ~MASK_AVX256_SPLIT_UNALIGNED_STORE; /* Enable 128-bit AVX instruction generation
[Bug target/100093] different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100093 --- Comment #1 from Hongtao.liu --- When ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL] is false, GCC goes to set up the bit MASK_AVX256_SPLIT_UNALIGNED_LOAD/STORE, but when ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL features[X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL] is true, it doesn't to clear the bit which causes the issue. if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL] && !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_LOAD)) opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_LOAD; if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL] && !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_STORE)) opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
