[Bug target/64154] enable fipa-ra for Thumb1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64154 Andrew Pinski changed: What|Removed |Added Keywords||FIXME Last reconfirmed|2014-12-12 00:00:00 |2022-1-9 --- Comment #5 from Andrew Pinski --- Note the code is now: /* In Thumb1 mode, we emit the epilogue in RTL, but the last insn - epilogue_insns - does not accurately model the corresponding insns emitted in the asm file. In particular, see the comment in thumb_exit 'Find out how many of the (return) argument registers we can corrupt'. As a consequence, the epilogue may clobber registers without fipa-ra finding out about it. Therefore, disable fipa-ra in Thumb1 mode. TODO: Accurately model clobbers for epilogue_insns and reenable fipa-ra. */ if (TARGET_THUMB1_P (opts->x_target_flags)) opts->x_flag_ipa_ra = 0; else opts->x_flag_ipa_ra = to->x_flag_ipa_ra;
[Bug target/64154] enable fipa-ra for Thumb1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64154
--- Comment #2 from Terry Guo terry.guo at arm dot com ---
Hi Tom,
I enabled this optimization to thumb1 target cortex-m0 and found this IPA-RA
optimization doesn't consider the register clobber information attached to call
rtx and thus generated bad code. Here are the bad rtxs I extracted from the
dump of cprop_hardreg pass:
(insn 292 291 141 13 (set (reg:SI 4 r4 [orig:163 ivtmp.108 ] [163])
(reg:SI 12 ip [orig:163 ivtmp.108 ] [163])) 742 {*thumb1_movsi_insn}
(expr_list:REG_DEAD (reg:SI 12 ip [orig:163 ivtmp.108 ] [163])
(nil)))
(call_insn 141 292 142 13 (parallel [
(call (mem:SI (symbol_ref:SI (f2) [flags 0x3] function_decl
0x7f8182689100 f2) [0 f2 S4 A32])
(const_int 0 [0]))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
])
/myssd/terguo01/toolchain-build/GCC32RM-424/src/gcc/gcc/testsuite/gcc.dg/vshift-3.c:119
770 {*call_insn}
(expr_list:REG_CALL_DECL (symbol_ref:SI (f2) [flags 0x3] function_decl
0x7f8182689100 f2)
(expr_list:REG_EH_REGION (const_int 0 [0])
(nil)))
(expr_list (clobber (reg:SI 12 ip))
(nil)))
(insn 11 10 12 13 (set (reg:SI 0 r0 [orig:170 ivtmp.130 ] [170])
(reg:SI 12 ip [orig:163 ivtmp.108 ] [163]))
/myssd/terguo01/toolchain-build/GCC32RM-424/src/gcc/gcc/testsuite/gcc.dg/vshift-3.c:121
742 {*thumb1_movsi_insn}
(expr_list:REG_EQUAL (symbol_ref:SI (j) [flags 0x80] var_decl
0x7f81827d0750 j)
(nil)))
I checked the code in 'if (CALL_P (insn))' part in file regcprop.c and found
the algorithm doesn't consider the '(expr_list (clobber (reg:SI 12 ip))' in
insn 141 which makes current algorithm think it is safe to propagate ip from
insn 292 to insn 11.
The case is from gcc regression test and compiled with option -mthumb
-mcpu=cortex-m0 -O3.
[Bug target/64154] enable fipa-ra for Thumb1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64154
--- Comment #3 from vries at gcc dot gnu.org ---
(In reply to Terry Guo from comment #2)
Hi Tom,
I enabled this optimization to thumb1 target cortex-m0
Does that mean you just reverted the patch for PR63718?
and found this IPA-RA
optimization doesn't consider the register clobber information attached to
call rtx
The IPA-RA analysis does consider that clobber. It's using
find_all_hard_reg_sets, and that function contains a loop over
CALL_INSN_FUNCTION_USAGE.
and thus generated bad code. Here are the bad rtxs I extracted from
the dump of cprop_hardreg pass:
(insn 292 291 141 13 (set (reg:SI 4 r4 [orig:163 ivtmp.108 ] [163])
(reg:SI 12 ip [orig:163 ivtmp.108 ] [163])) 742 {*thumb1_movsi_insn}
(expr_list:REG_DEAD (reg:SI 12 ip [orig:163 ivtmp.108 ] [163])
(nil)))
(call_insn 141 292 142 13 (parallel [
(call (mem:SI (symbol_ref:SI (f2) [flags 0x3] function_decl
0x7f8182689100 f2) [0 f2 S4 A32])
(const_int 0 [0]))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
])
/myssd/terguo01/toolchain-build/GCC32RM-424/src/gcc/gcc/testsuite/gcc.dg/
vshift-3.c:119 770 {*call_insn}
(expr_list:REG_CALL_DECL (symbol_ref:SI (f2) [flags 0x3]
function_decl 0x7f8182689100 f2)
(expr_list:REG_EH_REGION (const_int 0 [0])
(nil)))
(expr_list (clobber (reg:SI 12 ip))
(nil)))
(insn 11 10 12 13 (set (reg:SI 0 r0 [orig:170 ivtmp.130 ] [170])
(reg:SI 12 ip [orig:163 ivtmp.108 ] [163]))
/myssd/terguo01/toolchain-build/GCC32RM-424/src/gcc/gcc/testsuite/gcc.dg/
vshift-3.c:121 742 {*thumb1_movsi_insn}
(expr_list:REG_EQUAL (symbol_ref:SI (j) [flags 0x80] var_decl
0x7f81827d0750 j)
(nil)))
That is wrong indeed: ip is explicitly clobbered by the call in
CALL_INSN_FUNCTION_USAGE, but used as if not clobbered by the call.
I checked the code in 'if (CALL_P (insn))' part in file regcprop.c and found
the algorithm doesn't consider the '(expr_list (clobber (reg:SI 12 ip))' in
insn 141 which makes current algorithm think it is safe to propagate ip from
insn 292 to insn 11.
I cannot reproduce the wrong code as listed above. But I can reproduce the
clobber being skipped by copyprop_hardreg_forward_1. So I agree, cprop_hardreg
does not respect the clobber on the call in CALL_INSN_FUNCTION_USAGE.
I'll file a PR.
[Bug target/64154] enable fipa-ra for Thumb1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64154 --- Comment #4 from vries at gcc dot gnu.org --- I'll file a PR. PR 64539: '[5 regression] cprop_hardreg does not respect clobbers in C_I_F_U'
[Bug target/64154] enable fipa-ra for Thumb1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64154 Ramana Radhakrishnan ramana at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed||2014-12-12 CC||ramana at gcc dot gnu.org Ever confirmed|0 |1
[Bug target/64154] enable fipa-ra for Thumb1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64154 vries at gcc dot gnu.org changed: What|Removed |Added Summary|enable fuse-caller-save for |enable fipa-ra for Thumb1 |Thumb1 | --- Comment #1 from vries at gcc dot gnu.org --- -fuse-caller-save has been renamed to -fipa-ra
