[gcc r14-9383] MAINTAINERS: Fix order in Write After Aproval
https://gcc.gnu.org/g:1329dacdc0fbe7d43550294fe8b0323a6dc5ce9e commit r14-9383-g1329dacdc0fbe7d43550294fe8b0323a6dc5ce9e Author: Filip Kastl Date: Fri Mar 8 09:14:44 2024 +0100 MAINTAINERS: Fix order in Write After Aproval ChangeLog: * MAINTAINERS: Fix order of names in Write After Aproval Signed-off-by: Filip Kastl Diff: --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index a681518d704..8f64ee630b4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -448,9 +448,9 @@ Wei Guozhi Vineet Gupta Naveen H.S Mostafa Hagog -Demin Han Jivan Hakobyan Andrew Haley +Demin Han Frederik Harwath Stuart Hastings Michael Haubenwallner
[gcc r14-9385] dwarf2out: Emit DW_AT_export_symbols on anon unions/structs [PR113918]
https://gcc.gnu.org/g:05109b1bd5ef4ee9d78fe17d4563889694a26d05
commit r14-9385-g05109b1bd5ef4ee9d78fe17d4563889694a26d05
Author: Jakub Jelinek
Date: Fri Mar 8 09:14:32 2024 +0100
dwarf2out: Emit DW_AT_export_symbols on anon unions/structs [PR113918]
DWARF5 added DW_AT_export_symbols both for use on inline namespaces (where
we emit it), but also on anonymous unions/structs (and we didn't emit that
attribute there).
The following patch fixes it.
2024-03-08 Jakub Jelinek
PR debug/113918
gcc/
* dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
gcc/c/
* c-tree.h (c_type_dwarf_attribute): Declare.
* c-objc-common.h (LANG_HOOKS_TYPE_DWARF_ATTRIBUTE): Redefine.
* c-objc-common.cc: Include dwarf2.h.
(c_type_dwarf_attribute): New function.
gcc/cp/
* cp-objcp-common.cc (cp_type_dwarf_attribute): Return 1
for DW_AT_export_symbols on anonymous structs or unions.
gcc/testsuite/
* c-c++-common/dwarf2/pr113918.c: New test.
Diff:
---
gcc/c/c-objc-common.cc | 23 +++
gcc/c/c-objc-common.h| 3 +++
gcc/c/c-tree.h | 1 +
gcc/cp/cp-objcp-common.cc| 5 +
gcc/dwarf2out.cc | 11 ++
gcc/testsuite/c-c++-common/dwarf2/pr113918.c | 33
6 files changed, 76 insertions(+)
diff --git a/gcc/c/c-objc-common.cc b/gcc/c/c-objc-common.cc
index 116b73af6db..b7c72d2609c 100644
--- a/gcc/c/c-objc-common.cc
+++ b/gcc/c/c-objc-common.cc
@@ -30,6 +30,7 @@ along with GCC; see the file COPYING3. If not see
#include "gcc-rich-location.h"
#include "stringpool.h"
#include "attribs.h"
+#include "dwarf2.h"
static bool c_tree_printer (pretty_printer *, text_info *, const char *,
int, bool, bool, bool, bool *, const char **);
@@ -446,3 +447,25 @@ instantiation_dependent_expression_p (tree)
{
return false;
}
+
+/* Return -1 if dwarf ATTR shouldn't be added for TYPE, or the attribute
+ value otherwise. */
+int
+c_type_dwarf_attribute (const_tree type, int attr)
+{
+ if (type == NULL_TREE)
+return -1;
+
+ switch (attr)
+{
+case DW_AT_export_symbols:
+ if (RECORD_OR_UNION_TYPE_P (type) && TYPE_NAME (type) == NULL_TREE)
+ return 1;
+ break;
+
+default:
+ break;
+}
+
+ return -1;
+}
diff --git a/gcc/c/c-objc-common.h b/gcc/c/c-objc-common.h
index 35a59988e90..20af5a5bb94 100644
--- a/gcc/c/c-objc-common.h
+++ b/gcc/c/c-objc-common.h
@@ -119,6 +119,9 @@ static const scoped_attribute_specs *const
c_objc_attribute_table[] =
#undef LANG_HOOKS_GIMPLIFY_EXPR
#define LANG_HOOKS_GIMPLIFY_EXPR c_gimplify_expr
+#undef LANG_HOOKS_TYPE_DWARF_ATTRIBUTE
+#define LANG_HOOKS_TYPE_DWARF_ATTRIBUTE c_type_dwarf_attribute
+
#undef LANG_HOOKS_OMP_PREDETERMINED_SHARING
#define LANG_HOOKS_OMP_PREDETERMINED_SHARING c_omp_predetermined_sharing
diff --git a/gcc/c/c-tree.h b/gcc/c/c-tree.h
index 1fba9c8dae7..22b0009874b 100644
--- a/gcc/c/c-tree.h
+++ b/gcc/c/c-tree.h
@@ -731,6 +731,7 @@ extern bool c_warn_unused_global_decl (const_tree);
extern void c_initialize_diagnostics (diagnostic_context *);
extern bool c_var_mod_p (tree x, tree fn);
extern alias_set_type c_get_alias_set (tree);
+extern int c_type_dwarf_attribute (const_tree, int);
/* in c-typeck.cc */
extern int in_alignof;
diff --git a/gcc/cp/cp-objcp-common.cc b/gcc/cp/cp-objcp-common.cc
index 85dde0459fa..86e0b49d46b 100644
--- a/gcc/cp/cp-objcp-common.cc
+++ b/gcc/cp/cp-objcp-common.cc
@@ -410,6 +410,11 @@ cp_type_dwarf_attribute (const_tree type, int attr)
return 1;
break;
+case DW_AT_export_symbols:
+ if (ANON_AGGR_TYPE_P (type))
+ return 1;
+ break;
+
default:
break;
}
diff --git a/gcc/dwarf2out.cc b/gcc/dwarf2out.cc
index 03d73f9eecd..87e4240b871 100644
--- a/gcc/dwarf2out.cc
+++ b/gcc/dwarf2out.cc
@@ -25162,6 +25162,17 @@ gen_field_die (tree decl, struct vlr_context *ctx,
dw_die_ref context_die)
add_accessibility_attribute (decl_die, decl);
+ /* Add DW_AT_export_symbols to anonymous unions or structs. */
+ if ((dwarf_version >= 5 || !dwarf_strict) && DECL_NAME (decl) == NULL_TREE)
+if (tree type = member_declared_type (decl))
+ if (lang_hooks.types.type_dwarf_attribute (TYPE_MAIN_VARIANT (type),
+DW_AT_export_symbols) != -1)
+ {
+ dw_die_ref type_die = lookup_type_die (TYPE_MAIN_VARIANT (type));
+ if (type_die && get_AT (type_die, DW_AT_export_symbols) == NULL)
+ add_AT_flag (type_die, DW_AT_export_symbols, 1);
+ }
+
/* Equate decl number to die, so that we can look up this decl later on. */
equate_decl_number_to_die (decl,
[gcc r14-9384] c++: Fix up parameter pack diagnostics on xobj vs. varargs functions [PR113802]
https://gcc.gnu.org/g:3ecc5071797c4ceb6da67a6c2b2527a046091de2
commit r14-9384-g3ecc5071797c4ceb6da67a6c2b2527a046091de2
Author: Jakub Jelinek
Date: Fri Mar 8 09:11:57 2024 +0100
c++: Fix up parameter pack diagnostics on xobj vs. varargs functions
[PR113802]
The simple presence of ellipsis as next token after the parameter
declaration doesn't imply it is a parameter pack, it sometimes is, e.g.
if its type is a pack, but sometimes is not and in that case it acts
the same as if the next tokens were , ... instead of just ...
The xobj param cannot be a function parameter pack though treats both
the declarator->parameter_pack_p and token->type == CPP_ELLIPSIS as
sufficient conditions for the error. The conditions for CPP_ELLIPSIS
are done a little bit later in the same function and complex enough that
IMHO shouldn't be repeated, on the other side for the
declarator->parameter_pack_p case we clear that flag for xobj params
for error recovery reasons.
This patch just moves the diagnostics later (after the CPP_ELLIPSIS
handling)
and changes the error recovery behavior by pretending the this specifier
didn't appear if an error is reported.
2024-03-08 Jakub Jelinek
PR c++/113802
* parser.cc (cp_parser_parameter_declaration): Move the xobj_param_p
pack diagnostics after ellipsis handling and if an error is
reported,
pretend this specifier didn't appear. Formatting fix.
* g++.dg/cpp23/explicit-obj-diagnostics3.C (S0, S1, S2, S3, S4):
Don't
expect any diagnostics on f and fd member function templates, add
similar templates with ...Selves instead of Selves as k and kd and
expect diagnostics for those. Expect extra diagnostics in error
recovery for g and gd member function templates.
Diff:
---
gcc/cp/parser.cc | 38 +++---
.../g++.dg/cpp23/explicit-obj-diagnostics3.C | 61 ++
2 files changed, 69 insertions(+), 30 deletions(-)
diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index e32acfc30a2..bc3aa9dd6ad 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -25734,22 +25734,6 @@ cp_parser_parameter_declaration (cp_parser *parser,
decl_specifiers.locations[ds_this] = 0;
}
- if (xobj_param_p
- && ((declarator && declarator->parameter_pack_p)
- || cp_lexer_next_token_is (parser->lexer, CPP_ELLIPSIS)))
-{
- location_t xobj_param
- = make_location (decl_specifiers.locations[ds_this],
-decl_spec_token_start->location,
-input_location);
- error_at (xobj_param,
- "an explicit object parameter cannot "
- "be a function parameter pack");
- /* Suppress errors that occur down the line. */
- if (declarator)
- declarator->parameter_pack_p = false;
-}
-
/* If a function parameter pack was specified and an implicit template
parameter was introduced during cp_parser_parameter_declaration,
change any implicit parameters introduced into packs. */
@@ -25762,9 +25746,10 @@ cp_parser_parameter_declaration (cp_parser *parser,
(INNERMOST_TEMPLATE_PARMS (current_template_parms));
if (latest_template_parm_idx != template_parm_idx)
- decl_specifiers.type = convert_generic_types_to_packs
- (decl_specifiers.type,
- template_parm_idx, latest_template_parm_idx);
+ decl_specifiers.type
+ = convert_generic_types_to_packs (decl_specifiers.type,
+ template_parm_idx,
+ latest_template_parm_idx);
}
if (cp_lexer_next_token_is (parser->lexer, CPP_ELLIPSIS))
@@ -25794,6 +25779,21 @@ cp_parser_parameter_declaration (cp_parser *parser,
}
}
+ if (xobj_param_p
+ && (declarator ? declarator->parameter_pack_p
+: PACK_EXPANSION_P (decl_specifiers.type)))
+{
+ location_t xobj_param
+ = make_location (decl_specifiers.locations[ds_this],
+decl_spec_token_start->location,
+input_location);
+ error_at (xobj_param,
+ "an explicit object parameter cannot "
+ "be a function parameter pack");
+ xobj_param_p = false;
+ decl_specifiers.locations[ds_this] = 0;
+}
+
/* The restriction on defining new types applies only to the type
of the parameter, not to the default argument. */
parser->type_definition_forbidden_message = saved_message;
diff --git a/gcc/testsuite/g++.dg/cpp23/explicit-obj-diagnostics3.C
b/gcc/testsuite/g++.dg/cpp23/explicit-obj-diagnostics3.C
index 304cf029f8f..f6a892eb069 100644
--- a/gcc/testsuite/g++.dg/cpp23/explicit-obj-diagnostics3.C
+++ b/gcc/testsuite/g++.dg/cpp23/explicit-obj-diagnostics3.C
@@ -24,101 +24,140
[gcc r14-9386] c-family, c++: Fix up handling of types which may have padding in __atomic_{compare_}exchange
https://gcc.gnu.org/g:eed4e541711ab4ae7783f75dd132e2acca71fdb9
commit r14-9386-geed4e541711ab4ae7783f75dd132e2acca71fdb9
Author: Jakub Jelinek
Date: Fri Mar 8 09:15:39 2024 +0100
c-family, c++: Fix up handling of types which may have padding in
__atomic_{compare_}exchange
On Fri, Feb 16, 2024 at 01:51:54PM +, Jonathan Wakely wrote:
> Ah, although __atomic_compare_exchange only takes pointers, the
> compiler replaces that with a call to __atomic_compare_exchange_n
> which takes the newval by value, which presumably uses an 80-bit FP
> register and so the padding bits become indeterminate again.
The problem is that __atomic_{,compare_}exchange lowering if it has
a supported atomic 1/2/4/8/16 size emits code like:
_3 = *p2;
_4 = VIEW_CONVERT_EXPR (_3);
so if long double or some small struct etc. has some carefully filled
padding bits, those bits can be lost on the assignment. The library call
for __atomic_{,compare_}exchange would actually work because it woiuld
load the value from memory using integral type or memcpy.
E.g. on
void
foo (long double *a, long double *b, long double *c)
{
__atomic_compare_exchange (a, b, c, false, __ATOMIC_RELAXED,
__ATOMIC_RELAXED);
}
we end up with -O0 with:
fldt(%rax)
fstpt -48(%rbp)
movq-48(%rbp), %rax
movq-40(%rbp), %rdx
i.e. load *c from memory into 387 register, store it back to uninitialized
stack slot (the padding bits are now random in there) and then load a
__uint128_t (pair of GPR regs). The problem is that we first load it using
whatever type the pointer points to and then VIEW_CONVERT_EXPR that value:
p2 = build_indirect_ref (loc, p2, RO_UNARY_STAR);
p2 = build1 (VIEW_CONVERT_EXPR, I_type, p2);
The following patch fixes that by creating a MEM_REF instead, with the
I_type type, but with the original pointer type on the second argument for
aliasing purposes, so we actually preserve the padding bits that way.
With this patch instead of the above assembly we emit
movq8(%rax), %rdx
movq(%rax), %rax
I had to add support for MEM_REF in pt.cc, though with the assumption
that it has been already originally created with non-dependent
types/operands (which is the case here for the __atomic*exchange lowering).
2024-03-08 Jakub Jelinek
gcc/c-family/
* c-common.cc (resolve_overloaded_atomic_exchange): Instead of
setting
p1 to VIEW_CONVERT_EXPR (*p1), set it to MEM_REF with p1 and
(typeof (p1)) 0 operands and I_type type.
(resolve_overloaded_atomic_compare_exchange): Similarly for p2.
gcc/cp/
* pt.cc (tsubst_expr): Handle MEM_REF.
gcc/testsuite/
* g++.dg/ext/atomic-5.C: New test.
Diff:
---
gcc/c-family/c-common.cc| 22 +--
gcc/cp/pt.cc| 8 +++
gcc/testsuite/g++.dg/ext/atomic-5.C | 42 +
3 files changed, 66 insertions(+), 6 deletions(-)
diff --git a/gcc/c-family/c-common.cc b/gcc/c-family/c-common.cc
index e15eff698df..48844b17f77 100644
--- a/gcc/c-family/c-common.cc
+++ b/gcc/c-family/c-common.cc
@@ -7793,9 +7793,14 @@ resolve_overloaded_atomic_exchange (location_t loc, tree
function,
/* Convert object pointer to required type. */
p0 = build1 (VIEW_CONVERT_EXPR, I_type_ptr, p0);
(*params)[0] = p0;
- /* Convert new value to required type, and dereference it. */
- p1 = build_indirect_ref (loc, p1, RO_UNARY_STAR);
- p1 = build1 (VIEW_CONVERT_EXPR, I_type, p1);
+ /* Convert new value to required type, and dereference it.
+ If *p1 type can have padding or may involve floating point which
+ could e.g. be promoted to wider precision and demoted afterwards,
+ state of padding bits might not be preserved. */
+ build_indirect_ref (loc, p1, RO_UNARY_STAR);
+ p1 = build2_loc (loc, MEM_REF, I_type,
+ build1 (VIEW_CONVERT_EXPR, I_type_ptr, p1),
+ build_zero_cst (TREE_TYPE (p1)));
(*params)[1] = p1;
/* Move memory model to the 3rd position, and end param list. */
@@ -7873,9 +7878,14 @@ resolve_overloaded_atomic_compare_exchange (location_t
loc, tree function,
p1 = build1 (VIEW_CONVERT_EXPR, I_type_ptr, p1);
(*params)[1] = p1;
- /* Convert desired value to required type, and dereference it. */
- p2 = build_indirect_ref (loc, p2, RO_UNARY_STAR);
- p2 = build1 (VIEW_CONVERT_EXPR, I_type, p2);
+ /* Convert desired value to required type, and dereference it.
+ If *p2 type can have padding or may involve floating point which
+ could e.g. be promoted to wider precision and demoted afterwards,
+ state of padding bits might not be preserved. */
+ build_indirect_ref (loc, p2, RO_UNARY_STAR);
+ p2 = build2_loc (loc, MEM_REF, I_type,
+
[gcc r14-9387] i386: Guard noreturn no-callee-saved-registers optimization with -mnoreturn-no-callee-saved-register
https://gcc.gnu.org/g:a307a26e8b392ba65edfdae15489556b7701db81
commit r14-9387-ga307a26e8b392ba65edfdae15489556b7701db81
Author: Jakub Jelinek
Date: Fri Mar 8 09:18:19 2024 +0100
i386: Guard noreturn no-callee-saved-registers optimization with
-mnoreturn-no-callee-saved-registers [PR38534]
The following patch hides the noreturn no_callee_saved_registers (except bp)
optimization with a not enabled by default option.
The reason is that most noreturn functions should be called just once in a
program (unless they are recursive or invoke longjmp or similar, for
exceptions
we already punt), so it isn't that essential to save a few instructions in
their
prologue, but more importantly because it interferes with debugging.
And unlike most other optimizations, doesn't actually make it harder to
debug
the given function, which can be solved by recompiling the given function if
it is too hard to debug, but makes it harder to debug the callers of that
noreturn function. Those can be from a different translation unit,
different
binary or even different package, so if e.g. glibc abort needs to use all
of the callee saved registers (%rbx, %rbp, %r12, %r13, %r14, %r15),
debugging
any programs which abort will be harder because any DWARF expressions which
use those registers will be optimized out, not just in the immediate caller,
but in other callers as well until some frame restores a particular register
from some stack slot.
2024-03-08 Jakub Jelinek
PR target/38534
* config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
option.
* config/i386/i386-options.cc (ix86_set_func_type): Don't use
TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
ix86_noreturn_no_callee_saved_registers is enabled.
* doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
* gcc.target/i386/pr38534-1.c: Add
-mnoreturn-no-callee-saved-registers
to dg-options.
* gcc.target/i386/pr38534-2.c: Likewise.
* gcc.target/i386/pr38534-3.c: Likewise.
* gcc.target/i386/pr38534-4.c: Likewise.
* gcc.target/i386/pr38534-5.c: Likewise.
* gcc.target/i386/pr38534-6.c: Likewise.
* gcc.target/i386/pr114097-1.c: Likewise.
* gcc.target/i386/stack-check-17.c: Likewise.
Diff:
---
gcc/config/i386/i386-options.cc| 6 --
gcc/config/i386/i386.opt | 4
gcc/doc/invoke.texi| 10 ++
gcc/testsuite/gcc.target/i386/pr114097-1.c | 2 +-
gcc/testsuite/gcc.target/i386/pr38534-1.c | 2 +-
gcc/testsuite/gcc.target/i386/pr38534-2.c | 2 +-
gcc/testsuite/gcc.target/i386/pr38534-3.c | 2 +-
gcc/testsuite/gcc.target/i386/pr38534-4.c | 2 +-
gcc/testsuite/gcc.target/i386/pr38534-5.c | 2 +-
gcc/testsuite/gcc.target/i386/pr38534-6.c | 2 +-
gcc/testsuite/gcc.target/i386/stack-check-17.c | 2 +-
11 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 2f8c85f66d4..3cc147fa70c 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -3384,7 +3384,8 @@ ix86_set_func_type (tree fndecl)
{
/* No need to save and restore callee-saved registers for a noreturn
function with nothrow or compiled with -fno-exceptions unless when
- compiling with -O0 or -Og. So that backtrace works for those at least
+ compiling with -O0 or -Og, except that it interferes with debugging
+ of callers. So that backtrace works for those at least
in most cases, save the bp register if it is used, because it often
is used in callers to compute CFA.
@@ -3401,7 +3402,8 @@ ix86_set_func_type (tree fndecl)
if (lookup_attribute ("no_callee_saved_registers",
TYPE_ATTRIBUTES (TREE_TYPE (fndecl
no_callee_saved_registers = TYPE_NO_CALLEE_SAVED_REGISTERS;
- else if (TREE_THIS_VOLATILE (fndecl)
+ else if (ix86_noreturn_no_callee_saved_registers
+ && TREE_THIS_VOLATILE (fndecl)
&& optimize
&& !optimize_debug
&& (TREE_NOTHROW (fndecl) || !flag_exceptions)
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 5b4f1bff25f..d5f793a9e8b 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -659,6 +659,10 @@ mstore-max=
Target RejectNegative Joined Var(ix86_store_max) Enum(prefer_vector_width)
Init(PVW_NONE) Save
Maximum number of bits that can be stored to memory efficiently.
+mnoreturn-no-callee-saved-registers
+Target Var(ix86_noreturn_no_callee_saved_registers)
+Optimize noreturn functions by not saving callee-saved registers used in the
function.
+
;; ISA support
m32
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 2390d4781
[gcc r14-9388] bb-reorder: Fix assertion
https://gcc.gnu.org/g:d6bcc2e257026b383ac3e6ccdee13f7763b38621 commit r14-9388-gd6bcc2e257026b383ac3e6ccdee13f7763b38621 Author: Jakub Jelinek Date: Fri Mar 8 12:49:43 2024 +0100 bb-reorder: Fix assertion When touching bb-reorder yesterday, I've noticed the checking assert doesn't actually check what it meant to. Because asm_noperands returns >= 0 for inline asm patterns (in that case number of input+output+label operands, so asm goto has at least one) and -1 if it isn't inline asm. The following patch fixes the assertion to actually check that it is asm goto. 2024-03-08 Jakub Jelinek * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert, asm_noperands < 0 means it is not asm goto too. Diff: --- gcc/bb-reorder.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/bb-reorder.cc b/gcc/bb-reorder.cc index 7998c0a148e..ba11a2337ab 100644 --- a/gcc/bb-reorder.cc +++ b/gcc/bb-reorder.cc @@ -2024,7 +2024,8 @@ fix_up_fall_thru_edges (void) See PR108596. */ rtx_insn *j = BB_END (cur_bb); gcc_checking_assert (JUMP_P (j) - && asm_noperands (PATTERN (j))); + && (asm_noperands (PATTERN (j)) + > 0)); edge e2 = find_edge (cur_bb, e->dest); if (e2) e2->flags |= EDGE_CROSSING;
[gcc r14-9389] AVR: Add an insn combine pattern for offset computation.
https://gcc.gnu.org/g:40209cb15a3f2af8233ee887dc960992f358ad86
commit r14-9389-g40209cb15a3f2af8233ee887dc960992f358ad86
Author: Georg-Johann Lay
Date: Fri Mar 8 13:29:13 2024 +0100
AVR: Add an insn combine pattern for offset computation.
Computing uint16_t += 2 * uint8_t can occur when an offset
into a 16-bit array is computed. Without this pattern is costs
six instructions: A move (1), a zero-extend (1), a shift (2) and
an addition (2). With this pattern it costs 4.
gcc/
* config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
* config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
Diff:
---
gcc/config/avr/avr.cc | 11 +++
gcc/config/avr/avr.md | 33 +
2 files changed, 44 insertions(+)
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index b87ae6a256d..1fa4b557f5d 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -12513,6 +12513,17 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int
outer_code,
return true;
case PLUS:
+ // uint16_t += 2 * uint8_t;
+ if (mode == HImode
+ && GET_CODE (XEXP (x, 0)) == ASHIFT
+ && REG_P (XEXP (x, 1))
+ && XEXP (XEXP (x, 0), 1) == const1_rtx
+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
+ {
+ *total = COSTS_N_INSNS (4);
+ return true;
+ }
+
if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
&& REG_P (XEXP (x, 1)))
{
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index bc8a59c956c..52b6cff4a8b 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -1630,6 +1630,39 @@
"subi %A0,%n2\;sbc %B0,%B0"
[(set_attr "length" "2")])
+
+;; Occurs when computing offsets into 16-bit arrays.
+;; Saves up to 2 instructions.
+(define_insn_and_split "*addhi3_zero_extend.ashift1.split"
+ [(set (match_operand:HI 0 "register_operand"
"=r")
+(plus:HI (ashift:HI (zero_extend:HI (match_operand:QI 1
"register_operand" "r"))
+(const_int 1))
+ (match_operand:HI 2 "register_operand"
"0")))]
+ ""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:HI (ashift:HI (zero_extend:HI (match_dup 1))
+ (const_int 1))
+(match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addhi3_zero_extend.ashift1"
+ [(set (match_operand:HI 0 "register_operand"
"=r")
+(plus:HI (ashift:HI (zero_extend:HI (match_operand:QI 1
"register_operand" "r"))
+(const_int 1))
+ (match_operand:HI 2 "register_operand"
"0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
+ {
+return reg_overlap_mentioned_p (operands[1], operands[0])
+ ? "mov __tmp_reg__,%1\;add %A0,__tmp_reg__\;adc %B0,__zero_reg__\;add
%A0,__tmp_reg__\;adc %B0,__zero_reg__"
+ : "add %A0,%1\;adc %B0,__zero_reg__\;add %A0,%1\;adc %B0,__zero_reg__";
+ }
+ [(set (attr "length")
+(symbol_ref ("4 + reg_overlap_mentioned_p (operands[1],
operands[0])")))])
+
+
(define_insn_and_split "*usum_widenqihi3_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
[gcc r14-9390] modula2: Rebuild bootstrap tools with faster dynamic arrays
https://gcc.gnu.org/g:3cdaa6491fe805ffc1dc545722b97660f31572fa
commit r14-9390-g3cdaa6491fe805ffc1dc545722b97660f31572fa
Author: Gaius Mulley
Date: Fri Mar 8 12:52:04 2024 +
modula2: Rebuild bootstrap tools with faster dynamic arrays
This patch configures the larger dynamic arrays to use a larger
growth factor and larger initial size. It also rebuilds mc and pge
using the improved default array sizes in Indexing.mod.
gcc/m2/ChangeLog:
* gm2-compiler/M2Quads.mod (Init): Use InitIndexTuned with
default size 65K.
* gm2-compiler/SymbolConversion.mod (Init): Ditto.
* gm2-compiler/SymbolTable.mod (BEGIN): Ditto.
* mc-boot/GM2Dependent.cc: Rebuild.
* mc-boot/GM2Dependent.h: Rebuild.
* mc-boot/GM2RTS.cc: Rebuild.
* pge-boot/GIndexing.cc: Rebuild.
* pge-boot/GIndexing.h: Rebuild.
* pge-boot/GM2Dependent.cc: Rebuild.
* pge-boot/GM2Dependent.h: Rebuild.
* pge-boot/GM2RTS.cc: Rebuild.
Signed-off-by: Gaius Mulley
Diff:
---
gcc/m2/gm2-compiler/M2Quads.mod | 5 +-
gcc/m2/gm2-compiler/SymbolConversion.mod | 6 +-
gcc/m2/gm2-compiler/SymbolTable.mod | 7 +-
gcc/m2/mc-boot/GM2Dependent.cc | 202 +--
gcc/m2/mc-boot/GM2Dependent.h| 32 +
gcc/m2/mc-boot/GM2RTS.cc | 118 ++
gcc/m2/pge-boot/GIndexing.cc | 59 +++--
gcc/m2/pge-boot/GIndexing.h | 15 +++
gcc/m2/pge-boot/GM2Dependent.cc | 202 +--
gcc/m2/pge-boot/GM2Dependent.h | 32 +
gcc/m2/pge-boot/GM2RTS.cc| 119 ++
11 files changed, 540 insertions(+), 257 deletions(-)
diff --git a/gcc/m2/gm2-compiler/M2Quads.mod b/gcc/m2/gm2-compiler/M2Quads.mod
index ff0fda9cd41..2be229d0bf8 100644
--- a/gcc/m2/gm2-compiler/M2Quads.mod
+++ b/gcc/m2/gm2-compiler/M2Quads.mod
@@ -230,7 +230,8 @@ FROM M2StackWord IMPORT StackOfWord, InitStackWord,
KillStackWord,
PushWord, PopWord, PeepWord, RemoveTop,
IsEmptyWord, NoOfItemsInStackWord ;
-FROM Indexing IMPORT Index, InitIndex, GetIndice, PutIndice, InBounds,
HighIndice, IncludeIndiceIntoIndex ;
+FROM Indexing IMPORT Index, InitIndex, GetIndice, PutIndice, InBounds,
HighIndice,
+ IncludeIndiceIntoIndex, InitIndexTuned ;
FROM M2Range IMPORT InitAssignmentRangeCheck,
InitReturnRangeCheck,
@@ -15451,7 +15452,7 @@ BEGIN
LogicalXorTok := MakeKey('_LXOR') ;
LogicalDifferenceTok := MakeKey('_LDIFF') ;
ArithPlusTok := MakeKey ('_ARITH_+') ;
- QuadArray := InitIndex (1) ;
+ QuadArray := InitIndexTuned (1, 1024*1024 DIV 16, 16) ;
FreeList := 1 ;
NewQuad(NextQuad) ;
Assert(NextQuad=1) ;
diff --git a/gcc/m2/gm2-compiler/SymbolConversion.mod
b/gcc/m2/gm2-compiler/SymbolConversion.mod
index c3c484db00a..b8f0f70b435 100644
--- a/gcc/m2/gm2-compiler/SymbolConversion.mod
+++ b/gcc/m2/gm2-compiler/SymbolConversion.mod
@@ -24,7 +24,7 @@ IMPLEMENTATION MODULE SymbolConversion ;
FROM NameKey IMPORT Name ;
FROM Indexing IMPORT Index, InitIndex, PutIndice, GetIndice, InBounds,
- DebugIndex ;
+ DebugIndex, InitIndexTuned ;
FROM SymbolTable IMPORT IsConst, PopValue, IsValueSolved, GetSymName,
GetType, SkipType ;
@@ -237,8 +237,8 @@ END Poison ;
PROCEDURE Init ;
BEGIN
- mod2gcc := InitIndex(1) ;
- ALLOCATE(PoisonedSymbol, 1)
+ mod2gcc := InitIndexTuned (1, 1024*1024 DIV 16, 16) ;
+ ALLOCATE (PoisonedSymbol, 1)
END Init ;
diff --git a/gcc/m2/gm2-compiler/SymbolTable.mod
b/gcc/m2/gm2-compiler/SymbolTable.mod
index c57c0333188..b49cc889dca 100644
--- a/gcc/m2/gm2-compiler/SymbolTable.mod
+++ b/gcc/m2/gm2-compiler/SymbolTable.mod
@@ -28,7 +28,10 @@ FROM M2Debug IMPORT Assert ;
FROM libc IMPORT printf ;
IMPORT Indexing ;
-FROM Indexing IMPORT InitIndex, InBounds, LowIndice, HighIndice, PutIndice,
GetIndice ;
+
+FROM Indexing IMPORT InitIndex, InBounds, LowIndice, HighIndice,
+ PutIndice, GetIndice, InitIndexTuned ;
+
FROM Sets IMPORT Set, InitSet, IncludeElementIntoSet, IsElementInSet ;
FROM m2linemap IMPORT location_t ;
@@ -1644,7 +1647,7 @@ BEGIN
InitTree (ConstLitPoolTree) ;
InitTree (DefModuleTree) ;
InitTree (ModuleTree) ;
- Symbols := InitIndex (1) ;
+ Symbols := InitIndexTuned (1, 1024*1024 DIV 16, 16) ;
ConstLitArray := InitIndex (1) ;
FreeSymbol := 1 ;
ScopePtr := 1 ;
diff --git a/gcc/m2/mc-boot/GM2Dependent.cc b/gcc/m2/mc-boot/GM2Dependent.cc
index cda07e8460b..bf0daab4563 100644
--- a/gcc/m2/mc-boot/GM2Dependent.cc
+++ b/gcc/m2/mc-boot/GM2Dependent.cc
@@ -55,7 +55,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If
not, see
# include "GSYSTEM.h"
# include "GStor
[gcc r14-9391] tree-optimization/114269 - 434.zeusmp regression after SCEV analysis fix
https://gcc.gnu.org/g:018ddc86b928514d7dfee024dcdeb204d5dcdd61
commit r14-9391-g018ddc86b928514d7dfee024dcdeb204d5dcdd61
Author: Richard Biener
Date: Fri Mar 8 13:27:12 2024 +0100
tree-optimization/114269 - 434.zeusmp regression after SCEV analysis fix
The following addresses a performance regression caused by the recent
SCEV analysis fix with regard to folding multiplications and undefined
behavior on overflow. We do not handle (T) { a, +, b } * c but can
treat sign-conversions from unsigned by performing the multiplication
in the unsigned type. That's what we already do for additions (but
that misses one case that turns out important).
This fixes the 434.zeusmp regression for me.
PR tree-optimization/114269
PR tree-optimization/114074
* tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
in the third CASE_CONVERT case as well.
(chrec_fold_multiply): Handle sign-conversions from unsigned
by performing the operation in the unsigned type.
Diff:
---
gcc/tree-chrec.cc | 48
1 file changed, 48 insertions(+)
diff --git a/gcc/tree-chrec.cc b/gcc/tree-chrec.cc
index 2e6c7356d3b..7cd0ebc1010 100644
--- a/gcc/tree-chrec.cc
+++ b/gcc/tree-chrec.cc
@@ -325,6 +325,22 @@ chrec_fold_plus_1 (enum tree_code code, tree type,
: build_int_cst_type (type, -1)));
CASE_CONVERT:
+ {
+ /* We can strip sign-conversions to signed by performing the
+ operation in unsigned. */
+ tree optype = TREE_TYPE (TREE_OPERAND (op1, 0));
+ if (INTEGRAL_TYPE_P (type)
+ && INTEGRAL_TYPE_P (optype)
+ && tree_nop_conversion_p (type, optype)
+ && TYPE_UNSIGNED (optype))
+ return chrec_convert (type,
+ chrec_fold_plus_1 (code, optype,
+ chrec_convert (optype,
+ op0,
NULL),
+ TREE_OPERAND (op1, 0)),
+ NULL);
+ }
+
if (tree_contains_chrecs (op1, NULL))
return chrec_dont_know;
/* FALLTHRU */
@@ -424,6 +440,22 @@ chrec_fold_multiply (tree type,
return chrec_fold_multiply_poly_poly (type, op0, op1);
CASE_CONVERT:
+ {
+ /* We can strip sign-conversions to signed by performing the
+ operation in unsigned. */
+ tree optype = TREE_TYPE (TREE_OPERAND (op1, 0));
+ if (INTEGRAL_TYPE_P (type)
+ && INTEGRAL_TYPE_P (optype)
+ && tree_nop_conversion_p (type, optype)
+ && TYPE_UNSIGNED (optype))
+ return chrec_convert (type,
+ chrec_fold_multiply (optype,
+chrec_convert (optype,
+ op0,
NULL),
+TREE_OPERAND (op1, 0)),
+ NULL);
+ }
+
if (tree_contains_chrecs (op1, NULL))
return chrec_dont_know;
/* FALLTHRU */
@@ -474,6 +506,22 @@ chrec_fold_multiply (tree type,
}
CASE_CONVERT:
+ {
+ /* We can strip sign-conversions to signed by performing the
+ operation in unsigned. */
+ tree optype = TREE_TYPE (TREE_OPERAND (op0, 0));
+ if (INTEGRAL_TYPE_P (type)
+ && INTEGRAL_TYPE_P (optype)
+ && tree_nop_conversion_p (type, optype)
+ && TYPE_UNSIGNED (optype))
+ return chrec_convert (type,
+ chrec_fold_multiply (optype,
+TREE_OPERAND (op0, 0),
+chrec_convert (optype,
+ op1, NULL)),
+ NULL);
+ }
+
if (tree_contains_chrecs (op0, NULL))
return chrec_dont_know;
/* FALLTHRU */
[gcc r14-9392] testsuite: Fix up pr113617 test for darwin [PR113617]
https://gcc.gnu.org/g:8263a4b6505f84973c2ed2fb8d4f2036ca335ff3
commit r14-9392-g8263a4b6505f84973c2ed2fb8d4f2036ca335ff3
Author: Jakub Jelinek
Date: Fri Mar 8 15:18:56 2024 +0100
testsuite: Fix up pr113617 test for darwin [PR113617]
The test attempts to link a shared library, and apparently Darwin doesn't
allow by default for shared libraries to contain undefined symbols.
The following patch just adds dummy definitions for the symbols, so that
the library no longer has any undefined symbols at least in my linux
testing.
Furthermore, for target { !shared } targets (like darwin until the it is
fixed in target-supports.exp), because we then link a program rather than
shared library, the patch also adds a dummy main definition so that it
can link.
2024-03-08 Jakub Jelinek
PR rtl-optimization/113617
PR target/114233
* g++.dg/other/pr113617.C: Define -DSHARED when linking with
-shared.
* g++.dg/other/pr113617-aux.cc: Add definitions for used methods and
templates not defined elsewhere.
Diff:
---
gcc/testsuite/g++.dg/other/pr113617-aux.cc | 39 ++
gcc/testsuite/g++.dg/other/pr113617.C | 2 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/g++.dg/other/pr113617-aux.cc
b/gcc/testsuite/g++.dg/other/pr113617-aux.cc
index e6900e05a5f..0576cee34bd 100644
--- a/gcc/testsuite/g++.dg/other/pr113617-aux.cc
+++ b/gcc/testsuite/g++.dg/other/pr113617-aux.cc
@@ -7,3 +7,42 @@ void qux() {
A a;
a.foo(0, 0);
}
+
+namespace R {
+template<>
+Y >::AI
+Y >::operator->()
+{
+ return AI();
+}
+template<>
+Y >::AI
+Y >::operator->()
+{
+ return AI();
+}
+}
+
+N1::N2::N3::AB ab;
+
+N1::N2::N3::AB &
+N1::N2::N3::AB::bleh()
+{
+ return ab;
+}
+
+N1::N2::N3::AC::AC(int)
+{
+}
+
+void
+N1::N2::N3::AC::m1(R::S)
+{
+}
+
+#ifndef SHARED
+int
+main()
+{
+}
+#endif
diff --git a/gcc/testsuite/g++.dg/other/pr113617.C
b/gcc/testsuite/g++.dg/other/pr113617.C
index a02dda1420d..0ee62c134e6 100644
--- a/gcc/testsuite/g++.dg/other/pr113617.C
+++ b/gcc/testsuite/g++.dg/other/pr113617.C
@@ -2,7 +2,7 @@
// { dg-do link { target c++11 } }
// { dg-options "-O2" }
// { dg-additional-options "-fPIC" { target fpic } } */
-// { dg-additional-options "-shared" { target shared } } */
+// { dg-additional-options "-shared -DSHARED" { target shared } } */
// { dg-additional-sources pr113617-aux.cc }
#include "pr113617.h"
[gcc r14-9393] contrib: Improve dg-extract-results.sh's Python detection [PR109668]
https://gcc.gnu.org/g:64273a7e6bd8ba60058174d147521dd65d705637
commit r14-9393-g64273a7e6bd8ba60058174d147521dd65d705637
Author: Sam James
Date: Fri Mar 8 15:24:20 2024 +0100
contrib: Improve dg-extract-results.sh's Python detection [PR109668]
'python' on some systems (e.g. SLES 15) might be Python 2. Prefer python3,
then python, then python2 (as the script still tries to work there).
PR other/109668
* dg-extract-results.sh: Check for python3 before python. Check for
python2 last.
Diff:
---
contrib/dg-extract-results.sh | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/contrib/dg-extract-results.sh b/contrib/dg-extract-results.sh
index 00ef80046f7..539d596a89d 100755
--- a/contrib/dg-extract-results.sh
+++ b/contrib/dg-extract-results.sh
@@ -28,14 +28,17 @@
PROGNAME=dg-extract-results.sh
-# Try to use the python version if possible, since it tends to be faster.
+# Try to use the python version if possible, since it tends to be faster and
+# produces more stable results.
PYTHON_VER=`echo "$0" | sed 's/sh$/py/'`
-if test "$PYTHON_VER" != "$0" &&
- test -f "$PYTHON_VER" &&
- python -c 'import sys, getopt, re, io, datetime, operator; sys.exit (0 if
sys.version_info >= (2, 6) else 1)' \
- > /dev/null 2> /dev/null; then
- exec python $PYTHON_VER "$@"
-fi
+for python in python3 python python2 ; do
+ if test "$PYTHON_VER" != "$0" &&
+ test -f "$PYTHON_VER" &&
+ ${python} -c 'import sys, getopt, re, io, datetime, operator; sys.exit (0
if sys.version_info >= (2, 6) else 1)' \
+ > /dev/null 2> /dev/null; then
+exec ${python} $PYTHON_VER "$@"
+ fi
+done
usage() {
cat <&2
[gcc r14-9394] ARM: Fix builtin-bswap-1.c test [PR113915]
https://gcc.gnu.org/g:5119c7927c70b02ab9768b30f40564480f556432
commit r14-9394-g5119c7927c70b02ab9768b30f40564480f556432
Author: Wilco Dijkstra
Date: Fri Mar 8 15:01:15 2024 +
ARM: Fix builtin-bswap-1.c test [PR113915]
On Thumb-2 the use of CBZ blocks conditional execution, so change the
test to compare with a non-zero value.
gcc/testsuite/ChangeLog:
PR target/113915
* gcc.target/arm/builtin-bswap.x: Fix test to avoid emitting CBZ.
Diff:
---
gcc/testsuite/gcc.target/arm/builtin-bswap.x | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/builtin-bswap.x
b/gcc/testsuite/gcc.target/arm/builtin-bswap.x
index c96dbe6329c..dc8f910e000 100644
--- a/gcc/testsuite/gcc.target/arm/builtin-bswap.x
+++ b/gcc/testsuite/gcc.target/arm/builtin-bswap.x
@@ -10,7 +10,7 @@ extern short foos16 (short);
short swaps16_cond (short x, int y)
{
short z = x;
- if (y)
+ if (y != 2)
z = __builtin_bswap16 (x);
return foos16 (z);
}
@@ -27,7 +27,7 @@ extern unsigned short foou16 (unsigned short);
unsigned short swapu16_cond (unsigned short x, int y)
{
unsigned short z = x;
- if (y)
+ if (y != 2)
z = __builtin_bswap16 (x);
return foou16 (z);
}
@@ -43,7 +43,7 @@ extern int foos32 (int);
int swaps32_cond (int x, int y)
{
int z = x;
- if (y)
+ if (y != 2)
z = __builtin_bswap32 (x);
return foos32 (z);
}
@@ -60,7 +60,7 @@ extern unsigned int foou32 (unsigned int);
unsigned int swapsu2 (unsigned int x, int y)
{
int z = x;
- if (y)
+ if (y != 2)
z = __builtin_bswap32 (x);
return foou32 (z);
}
[gcc r14-9395] GCN, nvptx: Fatal error for missing symbols in 'libhsa-runtime64.so.1', 'libcuda.so.1'
https://gcc.gnu.org/g:ab70addf560e18210d238edfd605fc91fcce9df1
commit r14-9395-gab70addf560e18210d238edfd605fc91fcce9df1
Author: Thomas Schwinge
Date: Thu Mar 7 12:31:52 2024 +0100
GCN, nvptx: Fatal error for missing symbols in 'libhsa-runtime64.so.1',
'libcuda.so.1'
If 'libhsa-runtime64.so.1', 'libcuda.so.1' are not available, the
corresponding
libgomp plugin/device gets disabled, as before. But if they are available,
report any inconsistencies such as missing symbols, similar to how we fail
in
presence of other issues during device initialization.
libgomp/
* plugin/plugin-gcn.c (init_hsa_runtime_functions): Fatal error
for missing symbols.
* plugin/plugin-nvptx.c (init_cuda_lib): Likewise.
Diff:
---
libgomp/plugin/plugin-gcn.c | 3 ++-
libgomp/plugin/plugin-nvptx.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/libgomp/plugin/plugin-gcn.c b/libgomp/plugin/plugin-gcn.c
index 2771123252a..4b7ab5e83c5 100644
--- a/libgomp/plugin/plugin-gcn.c
+++ b/libgomp/plugin/plugin-gcn.c
@@ -1382,9 +1382,10 @@ init_hsa_runtime_functions (void)
#define DLSYM_FN(function) \
hsa_fns.function##_fn = dlsym (handle, #function); \
if (hsa_fns.function##_fn == NULL) \
-return false;
+GOMP_PLUGIN_fatal ("'%s' is missing '%s'", hsa_runtime_lib, #function);
#define DLSYM_OPT_FN(function) \
hsa_fns.function##_fn = dlsym (handle, #function);
+
void *handle = dlopen (hsa_runtime_lib, RTLD_LAZY);
if (handle == NULL)
return false;
diff --git a/libgomp/plugin/plugin-nvptx.c b/libgomp/plugin/plugin-nvptx.c
index c04c3acd679..2bc7b850671 100644
--- a/libgomp/plugin/plugin-nvptx.c
+++ b/libgomp/plugin/plugin-nvptx.c
@@ -126,7 +126,7 @@ init_cuda_lib (void)
# define CUDA_ONE_CALL_1(call, allow_null) \
cuda_lib.call = dlsym (h, #call);\
if (!allow_null && cuda_lib.call == NULL)\
-return false;
+GOMP_PLUGIN_fatal ("'%s' is missing '%s'", cuda_runtime_lib, #call);
#include "cuda-lib.def"
# undef CUDA_ONE_CALL
# undef CUDA_ONE_CALL_1
[gcc r14-9396] nvptx: 'cuDeviceGetCount' failure is fatal
https://gcc.gnu.org/g:37078f241a22c45db6380c5e9a79b4d08054bb3d commit r14-9396-g37078f241a22c45db6380c5e9a79b4d08054bb3d Author: Thomas Schwinge Date: Thu Mar 7 13:18:23 2024 +0100 nvptx: 'cuDeviceGetCount' failure is fatal Per commit 683f11843974f0bdf42f79cdcbb0c2b43c7b81b0 "OpenMP: Move omp requires checks to libgomp", we're now using 'return -1' from 'GOMP_OFFLOAD_get_num_devices' for 'omp_requires_mask' purposes. This missed that via 'nvptx_get_num_devices', we could also 'return -1' for 'cuDeviceGetCount' failure. Before, this meant (in 'gomp_target_init') to silently ignore the plugin/device -- which also has been doubtful behavior. Let's instead turn 'cuDeviceGetCount' failure into a fatal error, similar to other errors during device initialization. libgomp/ * plugin/plugin-nvptx.c (nvptx_get_num_devices): 'cuDeviceGetCount' failure is fatal. Diff: --- libgomp/plugin/plugin-nvptx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libgomp/plugin/plugin-nvptx.c b/libgomp/plugin/plugin-nvptx.c index 2bc7b850671..ced6e014ece 100644 --- a/libgomp/plugin/plugin-nvptx.c +++ b/libgomp/plugin/plugin-nvptx.c @@ -612,7 +612,7 @@ nvptx_get_num_devices (void) } } - CUDA_CALL_ERET (-1, cuDeviceGetCount, &n); + CUDA_CALL_ASSERT (cuDeviceGetCount, &n); return n; }
[gcc r14-9397] GCN: The original meaning of 'GCN_SUPPRESS_HOST_FALLBACK' isn't applicable (non-shared memory system
https://gcc.gnu.org/g:84fc8f4f3263d66503663bb784b58b49dd714dd9
commit r14-9397-g84fc8f4f3263d66503663bb784b58b49dd714dd9
Author: Thomas Schwinge
Date: Thu Mar 7 15:51:54 2024 +0100
GCN: The original meaning of 'GCN_SUPPRESS_HOST_FALLBACK' isn't applicable
(non-shared memory system)
'GCN_SUPPRESS_HOST_FALLBACK' originated as 'HSA_SUPPRESS_HOST_FALLBACK' in
the
libgomp HSA plugin, where the idea was -- in my understanding -- that you
wouldn't have device code available for all functions that may be called,
and
in that case transparently (shared memory system!) do host-fallback
execution.
Or, with 'HSA_SUPPRESS_HOST_FALLBACK' set, you'd get those diagnosed.
This has then been copied into the libgomp GCN plugin as
'GCN_SUPPRESS_HOST_FALLBACK'. However, the original meaning isn't
applicable
for the libgomp GCN plugin anymore: we assume that we're generating device
code
for all relevant functions, and we're implementing a non-shared memory
system,
where we cannot transparently do host-fallback execution for individual
functions.
However, 'GCN_SUPPRESS_HOST_FALLBACK' has gained an additional meaning, to
enforce a fatal error in case that 'libhsa-runtime64.so.1' can't be
dynamically
loaded; keep that meaning.
libgomp/
* plugin/plugin-gcn.c (GOMP_OFFLOAD_can_run): Don't consider
'GCN_SUPPRESS_HOST_FALLBACK' anymore (assume always-'true').
(init_hsa_context): Adjust 'GCN_SUPPRESS_HOST_FALLBACK' error
message.
Diff:
---
libgomp/plugin/plugin-gcn.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/libgomp/plugin/plugin-gcn.c b/libgomp/plugin/plugin-gcn.c
index 4b7ab5e83c5..7e141a85f31 100644
--- a/libgomp/plugin/plugin-gcn.c
+++ b/libgomp/plugin/plugin-gcn.c
@@ -1524,9 +1524,11 @@ init_hsa_context (void)
init_environment_variables ();
if (!init_hsa_runtime_functions ())
{
- GCN_WARNING ("Run-time could not be dynamically opened\n");
+ const char *msg = "Run-time could not be dynamically opened";
if (suppress_host_fallback)
- GOMP_PLUGIN_fatal ("GCN host fallback has been suppressed");
+ GOMP_PLUGIN_fatal ("%s\n", msg);
+ else
+ GCN_WARNING ("%s\n", msg);
return false;
}
status = hsa_fns.hsa_init_fn ();
@@ -3855,15 +3857,9 @@ GOMP_OFFLOAD_can_run (void *fn_ptr)
init_kernel (kernel);
if (kernel->initialization_failed)
-goto failure;
+GOMP_PLUGIN_fatal ("kernel initialization failed");
return true;
-
-failure:
- if (suppress_host_fallback)
-GOMP_PLUGIN_fatal ("GCN host fallback has been suppressed");
- GCN_WARNING ("GCN target cannot be launched, doing a host fallback\n");
- return false;
}
/* Allocate memory on device N. */
[gcc(refs/users/aoliva/heads/testme)] [strub] improve handling of indirected volatile parms [PR112938]
https://gcc.gnu.org/g:e74e6e4f783b7aecd712e36b996174ac78f19185
commit e74e6e4f783b7aecd712e36b996174ac78f19185
Author: Alexandre Oliva
Date: Fri Mar 8 10:27:59 2024 -0300
[strub] improve handling of indirected volatile parms [PR112938]
The earlier patch for PR112938 arranged for volatile parms to be made
indirect in internal strub wrapped bodies.
The first problem that remained, more evident, was that the indirected
parameter remained volatile, despite the indirection, but it wasn't
regimplified, so indirecting it was malformed gimple.
Regimplifying turned out not to be needed. The best course of action
was to drop the volatility from the by-reference parm, that was being
unexpectedly inherited from the original volatile parm.
That exposed another problem: the dereferences would then lose their
volatile status, so we had to bring volatile back to them.
for gcc/ChangeLog
PR middle-end/112938
* ipa-strub.cc (pass_ipa_strub::execute): Drop volatility from
indirected parm.
(maybe_make_indirect): Restore volatility in dereferences.
for gcc/testsuite/ChangeLog
PR middle-end/112938
* g++.dg/strub-internal-pr112938.cc: New.
Diff:
---
gcc/ipa-strub.cc| 7 +++
gcc/testsuite/g++.dg/strub-internal-pr112938.cc | 12
2 files changed, 19 insertions(+)
diff --git a/gcc/ipa-strub.cc b/gcc/ipa-strub.cc
index dff94222351..8fa7bdf5300 100644
--- a/gcc/ipa-strub.cc
+++ b/gcc/ipa-strub.cc
@@ -1940,6 +1940,9 @@ maybe_make_indirect (indirect_parms_t &indirect_parms,
tree op, int *rec)
TREE_TYPE (TREE_TYPE (op)),
op,
build_int_cst (TREE_TYPE (op), 0));
+ if (TYPE_VOLATILE (TREE_TYPE (TREE_TYPE (op)))
+ && !TREE_THIS_VOLATILE (ret))
+ TREE_SIDE_EFFECTS (ret) = TREE_THIS_VOLATILE (ret) = 1;
return ret;
}
}
@@ -2894,6 +2897,10 @@ pass_ipa_strub::execute (function *)
probably drop the TREE_ADDRESSABLE and keep the TRUE. */
tree ref_type = build_ref_type_for (nparm);
+ if (TREE_THIS_VOLATILE (nparm)
+ && TYPE_VOLATILE (TREE_TYPE (nparm))
+ && !TYPE_VOLATILE (ref_type))
+ TREE_SIDE_EFFECTS (nparm) = TREE_THIS_VOLATILE (nparm) = 0;
DECL_ARG_TYPE (nparm) = TREE_TYPE (nparm) = ref_type;
relayout_decl (nparm);
TREE_ADDRESSABLE (nparm) = 0;
diff --git a/gcc/testsuite/g++.dg/strub-internal-pr112938.cc
b/gcc/testsuite/g++.dg/strub-internal-pr112938.cc
new file mode 100644
index 000..5a74becc269
--- /dev/null
+++ b/gcc/testsuite/g++.dg/strub-internal-pr112938.cc
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-fdump-tree-optimized -O2" } */
+/* { dg-require-effective-target strub } */
+
+bool __attribute__ ((__strub__ ("internal")))
+f(bool i, volatile bool j)
+{
+ return (i ^ j) == j;
+}
+
+/* Check for two dereferences of the indirected volatile j parm. */
+/* { dg-final { scan-tree-dump-times {={v} \*j_[0-9][0-9]*(D)} 2 "optimized" }
} */
[gcc(refs/users/aoliva/heads/testme)] [tree-prof] skip if errors were seen [PR113681]
https://gcc.gnu.org/g:a2b5748ee9fd2e254ec9bda4bca0d5224e9abd6e
commit a2b5748ee9fd2e254ec9bda4bca0d5224e9abd6e
Author: Alexandre Oliva
Date: Fri Mar 8 12:26:43 2024 -0300
[tree-prof] skip if errors were seen [PR113681]
ipa_tree_profile asserts that the symtab is in IPA_SSA state, but we
don't reach that state and ICE if e.g. ipa-strub passes report errors.
Skip this pass if errors were seen.
for gcc/ChangeLog
PR tree-optimization/113681
* tree-profiling.cc (pass_ipa_tree_profile::gate): Skip if
seen_errors.
for gcc/testsuite/ChangeLog
PR tree-optimization/113681
* c-c++-common/strub-pr113681.c: New.
Diff:
---
gcc/testsuite/c-c++-common/strub-pr113681.c | 22 ++
gcc/tree-profile.cc | 3 ++-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/c-c++-common/strub-pr113681.c
b/gcc/testsuite/c-c++-common/strub-pr113681.c
new file mode 100644
index 000..3ef9017b2eb
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/strub-pr113681.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-fstrub=relaxed -fbranch-probabilities" } */
+/* { dg-require-effective-target strub } */
+
+/* Same as torture/strub-inlineable1.c, but with -fbranch-probabilities, to
+ check that IPA tree-profiling won't ICE. It would when we refrained from
+ running passes that would take it to IPA_SSA, but ran the pass that asserted
+ for IPA_SSA. */
+
+inline void __attribute__ ((strub ("internal"), always_inline))
+inl_int_ali (void)
+{
+ /* No internal wrapper, so this body ALWAYS gets inlined,
+ but it cannot be called from non-strub contexts. */
+}
+
+void
+bat (void)
+{
+ /* Not allowed, not a strub context. */
+ inl_int_ali (); /* { dg-error "context" } */
+}
diff --git a/gcc/tree-profile.cc b/gcc/tree-profile.cc
index aed13e2b1bc..d2bdbe3a08c 100644
--- a/gcc/tree-profile.cc
+++ b/gcc/tree-profile.cc
@@ -999,7 +999,8 @@ pass_ipa_tree_profile::gate (function *)
disabled. */
return (!in_lto_p && !flag_auto_profile
&& (flag_branch_probabilities || flag_test_coverage
- || profile_arc_flag));
+ || profile_arc_flag)
+ && !seen_error ());
}
} // anon namespace
[gcc r14-9398] bpf: testsuite: fix unresolved test in memset-1.c
https://gcc.gnu.org/g:10c609191c4462133d6a4ea10a739167204f2cd3
commit r14-9398-g10c609191c4462133d6a4ea10a739167204f2cd3
Author: David Faust
Date: Thu Mar 7 09:23:38 2024 -0800
bpf: testsuite: fix unresolved test in memset-1.c
The test was trying to do too much by both checking for an error, and
checking the resulting assembly. Of course, due to the error no asm was
produced, so the scan-asm went unresolved. Split it into two separate
tests to fix the issue.
gcc/testsuite/
* gcc.target/bpf/memset-1.c: Move error test case to...
* gcc.target/bpf/memset-2.c: ... here. New test.
Diff:
---
gcc/testsuite/gcc.target/bpf/memset-1.c | 8
gcc/testsuite/gcc.target/bpf/memset-2.c | 22 ++
2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/gcc/testsuite/gcc.target/bpf/memset-1.c
b/gcc/testsuite/gcc.target/bpf/memset-1.c
index 9e9f8eff028..7c4768c6e73 100644
--- a/gcc/testsuite/gcc.target/bpf/memset-1.c
+++ b/gcc/testsuite/gcc.target/bpf/memset-1.c
@@ -28,12 +28,4 @@ set_large (struct context *ctx)
__builtin_memset (dest, 0xfe, 130);
}
-void
-set_variable (struct context *ctx)
-{
- void *data = (void *)(long)ctx->data;
- char *dest = data;
- __builtin_memset (dest, 0xbc, ctx->data_meta); /* { dg-error "could not
inline call" } */
-}
-
/* { dg-final { scan-assembler-times "call" 0 } } */
diff --git a/gcc/testsuite/gcc.target/bpf/memset-2.c
b/gcc/testsuite/gcc.target/bpf/memset-2.c
new file mode 100644
index 000..0602a1a277c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/bpf/memset-2.c
@@ -0,0 +1,22 @@
+/* Test that we error if memset cannot be expanded inline. */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct context {
+ unsigned int data;
+ unsigned int data_end;
+ unsigned int data_meta;
+ unsigned int ingress;
+ unsigned int queue_index;
+ unsigned int egress;
+};
+
+
+void
+set_variable (struct context *ctx)
+{
+ void *data = (void *)(long)ctx->data;
+ char *dest = data;
+ __builtin_memset (dest, 0xbc, ctx->data_meta); /* { dg-error "could not
inline call" } */
+}
[gcc r14-9399] arm: testsuite: tweak bics_3.c [PR113542]
https://gcc.gnu.org/g:ac829a89fb56cfd914d5e29ed4695e499b0dbc95
commit r14-9399-gac829a89fb56cfd914d5e29ed4695e499b0dbc95
Author: Richard Earnshaw
Date: Fri Mar 8 16:23:53 2024 +
arm: testsuite: tweak bics_3.c [PR113542]
This test was too simple, which meant that the compiler was sometimes
able to find a better optimization of the code than using a BICS
instruction. Fix this by changing the test slightly to produce a
sequence where BICS should always be the preferred solution.
gcc/testsuite:
PR target/113542
* gcc.target/arm/bics_3.c: Adjust code to something which should
always result in BICS.
Diff:
---
gcc/testsuite/gcc.target/arm/bics_3.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/bics_3.c
b/gcc/testsuite/gcc.target/arm/bics_3.c
index e056b264e15..4d6938948a1 100644
--- a/gcc/testsuite/gcc.target/arm/bics_3.c
+++ b/gcc/testsuite/gcc.target/arm/bics_3.c
@@ -2,13 +2,11 @@
/* { dg-options "-O2 --save-temps -fno-inline" } */
/* { dg-require-effective-target arm32 } */
-extern void abort (void);
-
int
bics_si_test (int a, int b)
{
- if (a & ~b)
-return 1;
+ if ((a & ~b) >= 0)
+return 3;
else
return 0;
}
@@ -16,8 +14,8 @@ bics_si_test (int a, int b)
int
bics_si_test2 (int a, int b)
{
- if (a & ~ (b << 2))
-return 1;
+ if ((a & ~ (b << 2)) >= 0)
+return 3;
else
return 0;
}
@@ -28,13 +26,12 @@ main (void)
int a = 5;
int b = 5;
int c = 20;
- if (bics_si_test (a, b))
-abort ();
- if (bics_si_test2 (c, b))
-abort ();
+ if (bics_si_test (a, b) != 3)
+__builtin_abort ();
+ if (bics_si_test2 (c, b) != 3)
+__builtin_abort ();
return 0;
}
/* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" 2
} } */
/* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+,
.sl #2" 1 } } */
-
[gcc r14-9400] bpf: add size threshold for inlining mem builtins
https://gcc.gnu.org/g:0e850eff58539fb79483664962fac6c46d65c79d
commit r14-9400-g0e850eff58539fb79483664962fac6c46d65c79d
Author: David Faust
Date: Thu Mar 7 09:29:32 2024 -0800
bpf: add size threshold for inlining mem builtins
BPF cannot fall back on library calls to implement memmove, memcpy and
memset, so we attempt to expand these inline always if possible.
However, this inline expansion was being attempted even for excessively
large operations, which could result in gcc consuming huge amounts of
memory and hanging.
Add a size threshold in the BPF backend below which to always expand
these operations inline, and introduce an option
-minline-memops-threshold= to control the threshold. Defaults to
1024 bytes.
gcc/
* config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
not attempt inline expansion if size is above threshold.
* config/bpf/bpf.opt (-minline-memops-threshold): New option.
* doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
Document.
gcc/testsuite/
* gcc.target/bpf/inline-memops-threshold-1.c: New test.
* gcc.target/bpf/inline-memops-threshold-2.c: New test.
Diff:
---
gcc/config/bpf/bpf.cc | 26 +-
gcc/config/bpf/bpf.opt | 4
gcc/doc/invoke.texi| 11 -
.../gcc.target/bpf/inline-memops-threshold-1.c | 15 +
.../gcc.target/bpf/inline-memops-threshold-2.c | 11 +
5 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc
index 0e33f4347ba..fb60770c170 100644
--- a/gcc/config/bpf/bpf.cc
+++ b/gcc/config/bpf/bpf.cc
@@ -1244,9 +1244,9 @@ bool
bpf_expand_cpymem (rtx *operands, bool is_move)
{
/* Size must be constant for this expansion to work. */
+ const char *name = is_move ? "memmove" : "memcpy";
if (!CONST_INT_P (operands[2]))
{
- const char *name = is_move ? "memmove" : "memcpy";
if (flag_building_libgcc)
warning (0, "could not inline call to %<__builtin_%s%>: "
"size must be constant", name);
@@ -1275,6 +1275,18 @@ bpf_expand_cpymem (rtx *operands, bool is_move)
gcc_unreachable ();
}
+ /* For sizes above threshold, always use a libcall. */
+ if (size_bytes > (unsigned HOST_WIDE_INT) bpf_inline_memops_threshold)
+{
+ if (flag_building_libgcc)
+ warning (0, "could not inline call to %<__builtin_%s%>: "
+"too many bytes, use %<-minline-memops-threshold%>", name);
+ else
+ error ("could not inline call to %<__builtin_%s%>: "
+ "too many bytes, use %<-minline-memops-threshold%>", name);
+ return false;
+}
+
unsigned iters = size_bytes >> ceil_log2 (align);
unsigned remainder = size_bytes & (align - 1);
@@ -1347,6 +1359,18 @@ bpf_expand_setmem (rtx *operands)
gcc_unreachable ();
}
+ /* For sizes above threshold, always use a libcall. */
+ if (size_bytes > (unsigned HOST_WIDE_INT) bpf_inline_memops_threshold)
+{
+ if (flag_building_libgcc)
+ warning (0, "could not inline call to %<__builtin_memset%>: "
+"too many bytes, use %<-minline-memops-threshold%>");
+ else
+ error ("could not inline call to %<__builtin_memset%>: "
+ "too many bytes, use %<-minline-memops-threshold%>");
+ return false;
+}
+
unsigned iters = size_bytes >> ceil_log2 (align);
unsigned remainder = size_bytes & (align - 1);
unsigned inc = GET_MODE_SIZE (mode);
diff --git a/gcc/config/bpf/bpf.opt b/gcc/config/bpf/bpf.opt
index acfddebdad7..541ebe4dfc4 100644
--- a/gcc/config/bpf/bpf.opt
+++ b/gcc/config/bpf/bpf.opt
@@ -108,3 +108,7 @@ Enum(asm_dialect) String(normal) Value(ASM_NORMAL)
EnumValue
Enum(asm_dialect) String(pseudoc) Value(ASM_PSEUDOC)
+
+minline-memops-threshold=
+Target RejectNegative Joined UInteger Var(bpf_inline_memops_threshold)
Init(1024)
+-minline-memops-threshold= Maximum size of memset/memmove/memcpy to
inline, larger sizes will use a library call.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c0d604a2c5c..85c938d4a14 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -971,7 +971,7 @@ Objective-C and Objective-C++ Dialects}.
@gccoptlist{-mbig-endian -mlittle-endian
-mframe-limit=@var{bytes} -mxbpf -mco-re -mno-co-re -mjmpext
-mjmp32 -malu32 -mv3-atomics -mbswap -msdiv -msmov -mcpu=@var{version}
--masm=@var{dialect}}
+-masm=@var{dialect} -minline-memops-threshold=@var{bytes}}
@emph{FR30 Options}
@gccoptlist{-msmall-model -mno-lsim}
@@ -25701,6 +25701,15 @@ Outputs pseudo-c assembly dialect.
@end table
+@opindex -minline-memops-threshold
+@item -minline-memops-threshold=@var{bytes}
+Specifies a size threshold in bytes at or below which memmove, memcpy
+and memset
[gcc r14-9401] [PR113790][LRA]: Fixing LRA ICE on riscv64
https://gcc.gnu.org/g:cebbaa2a84586a7345837f74a53b7a0263bf29ee
commit r14-9401-gcebbaa2a84586a7345837f74a53b7a0263bf29ee
Author: Vladimir N. Makarov
Date: Fri Mar 8 14:48:33 2024 -0500
[PR113790][LRA]: Fixing LRA ICE on riscv64
LRA failed to consider all insn alternatives when non-reload pseudo
did not get a hard register. This resulted in failure to generate
code by LRA. The patch fixes this problem.
gcc/ChangeLog:
PR target/113790
* lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
for non-reload pseudo too.
Diff:
---
gcc/lra-assigns.cc | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/gcc/lra-assigns.cc b/gcc/lra-assigns.cc
index d1b2b35ffc9..7dfa6f70941 100644
--- a/gcc/lra-assigns.cc
+++ b/gcc/lra-assigns.cc
@@ -1430,13 +1430,19 @@ assign_by_spills (void)
hard_regno = spill_for (regno, &all_spilled_pseudos, iter == 1);
if (hard_regno < 0)
{
- if (reload_p) {
- /* Put unassigned reload pseudo first in the
- array. */
- regno2 = sorted_pseudos[nfails];
- sorted_pseudos[nfails++] = regno;
- sorted_pseudos[i] = regno2;
- }
+ if (reload_p)
+ {
+ /* Put unassigned reload pseudo first in the array. */
+ regno2 = sorted_pseudos[nfails];
+ sorted_pseudos[nfails++] = regno;
+ sorted_pseudos[i] = regno2;
+ }
+ else
+ {
+ /* Consider all alternatives on the next constraint
+subpass. */
+ bitmap_set_bit (&all_spilled_pseudos, regno);
+ }
}
else
{
[gcc(refs/users/meissner/heads/work162)] Revert some changes
https://gcc.gnu.org/g:022085bbe5093b4baf9ba82080b71569bce7bb01
commit 022085bbe5093b4baf9ba82080b71569bce7bb01
Author: Michael Meissner
Date: Fri Mar 8 16:21:19 2024 -0500
Revert some changes
Diff:
---
gcc/config.gcc | 5 +-
gcc/config/rs6000/aix71.h| 1 -
gcc/config/rs6000/aix72.h| 1 -
gcc/config/rs6000/aix73.h| 1 -
gcc/config/rs6000/driver-rs6000.cc | 2 -
gcc/config/rs6000/power10.md | 142 +--
gcc/config/rs6000/ppc-auxv.h | 3 +-
gcc/config/rs6000/rs6000-builtin.cc | 1 -
gcc/config/rs6000/rs6000-c.cc| 2 -
gcc/config/rs6000/rs6000-cpus.def| 5 -
gcc/config/rs6000/rs6000-opts.h | 3 +-
gcc/config/rs6000/rs6000-string.cc | 1 -
gcc/config/rs6000/rs6000-tables.opt | 3 -
gcc/config/rs6000/rs6000.cc | 50 ++
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt | 3 -
gcc/doc/invoke.texi | 5 +-
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 ---
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 --
gcc/testsuite/lib/target-supports.exp| 17
22 files changed, 85 insertions(+), 206 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 02004bee30b..624e0dae191 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -531,8 +531,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
- xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5559,7 +5558,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x \
+ | power[3456789] | power10 | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d..24bc301e37d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b4..c43974f577a 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 1318b0b3662..b1572bde81f 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index f4900724b98..3ebbaa42622 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -451,7 +451,6 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpwr8" },
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
- { "power11", "-mpwr11" },
{ "powerpc", "-mppc" },
{ "rs64","-mppc" },
{ "603", "-m603" },
@@ -480,7 +479,6 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpower8" },
{ "power9", "-mpower9" },
{ "power10", "-mpower10" },
- { "power11", "-mpower11" },
{ "a2", "-ma2" },
{ "powerpc", "-mppc" },
{ "powerpc64", "-mppc64" },
diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index 22851db3318..fcc2199ab29 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -97,12 +97,12 @@
(eq_attr "update" "no
[gcc r14-9402] libbacktrace: don't assume compressed section is aligned
https://gcc.gnu.org/g:5825bd0e0d0040126e78269e56c9b9f533e2a520
commit r14-9402-g5825bd0e0d0040126e78269e56c9b9f533e2a520
Author: Ian Lance Taylor
Date: Fri Mar 8 13:55:34 2024 -0800
libbacktrace: don't assume compressed section is aligned
Patch originally by GitHub user ubyte at
https://github.com/ianlancetaylor/libbacktrace/pull/120.
* elf.c (elf_uncompress_chdr): Don't assume compressed section is
aligned.
Diff:
---
libbacktrace/elf.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/libbacktrace/elf.c b/libbacktrace/elf.c
index 7841c86cd9c..3cd87020b03 100644
--- a/libbacktrace/elf.c
+++ b/libbacktrace/elf.c
@@ -5076,7 +5076,7 @@ elf_uncompress_chdr (struct backtrace_state *state,
backtrace_error_callback error_callback, void *data,
unsigned char **uncompressed, size_t *uncompressed_size)
{
- const b_elf_chdr *chdr;
+ b_elf_chdr chdr;
char *alc;
size_t alc_len;
unsigned char *po;
@@ -5088,27 +5088,30 @@ elf_uncompress_chdr (struct backtrace_state *state,
if (compressed_size < sizeof (b_elf_chdr))
return 1;
- chdr = (const b_elf_chdr *) compressed;
+ /* The lld linker can misalign a compressed section, so we can't safely read
+ the fields directly as we can for other ELF sections. See
+ https://github.com/ianlancetaylor/libbacktrace/pull/120. */
+ memcpy (&chdr, compressed, sizeof (b_elf_chdr));
alc = NULL;
alc_len = 0;
- if (*uncompressed != NULL && *uncompressed_size >= chdr->ch_size)
+ if (*uncompressed != NULL && *uncompressed_size >= chdr.ch_size)
po = *uncompressed;
else
{
- alc_len = chdr->ch_size;
+ alc_len = chdr.ch_size;
alc = backtrace_alloc (state, alc_len, error_callback, data);
if (alc == NULL)
return 0;
po = (unsigned char *) alc;
}
- switch (chdr->ch_type)
+ switch (chdr.ch_type)
{
case ELFCOMPRESS_ZLIB:
if (!elf_zlib_inflate_and_verify (compressed + sizeof (b_elf_chdr),
compressed_size - sizeof (b_elf_chdr),
- zdebug_table, po, chdr->ch_size))
+ zdebug_table, po, chdr.ch_size))
goto skip;
break;
@@ -5116,7 +5119,7 @@ elf_uncompress_chdr (struct backtrace_state *state,
if (!elf_zstd_decompress (compressed + sizeof (b_elf_chdr),
compressed_size - sizeof (b_elf_chdr),
(unsigned char *)zdebug_table, po,
- chdr->ch_size))
+ chdr.ch_size))
goto skip;
break;
@@ -5126,7 +5129,7 @@ elf_uncompress_chdr (struct backtrace_state *state,
}
*uncompressed = po;
- *uncompressed_size = chdr->ch_size;
+ *uncompressed_size = chdr.ch_size;
return 1;
@@ -6876,8 +6879,8 @@ elf_add (struct backtrace_state *state, const char
*filename, int descriptor,
}
}
- // A debuginfo file may not have a useful .opd section, but we can use the
- // one from the original executable.
+ /* A debuginfo file may not have a useful .opd section, but we can use the
+ one from the original executable. */
if (opd == NULL)
opd = caller_opd;
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=power11 support.
https://gcc.gnu.org/g:0296376c2c19ba06eef70e36bbc41f5cfe947905
commit 0296376c2c19ba06eef70e36bbc41f5cfe947905
Author: Michael Meissner
Date: Fri Mar 8 16:42:18 2024 -0500
Add -mcpu=power11 support.
This patch adds the power11 option to the -mcpu= and -mtune= switches.
This patch treats the power11 like a power10 in terms of costs and
reassociation
width.
This patch issues a ".machine power11" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
2024-03-08 Michael Meissner
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR11 if -mcpu=power11.
* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add power11 isa bit.
(power11 cpu): Add power11 definition.
* rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (power11_cost): Add power11 support.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add power11.
* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=power11.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 50 -
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 5 ++--
9 files changed, 64 insertions(+), 10 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index ce0b14a8d37..ebed8b9554a 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -447,6 +447,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
if ((flags & OPTION_MASK_POWER10) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
+ if ((flags & OPTION_MASK_POWER11) != 0)
+rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 28249600318..3237a5ada30 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,6 +86,9 @@
| OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS)
+#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
+ | OPTION_MASK_POWER11)
+
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
| OPTION_MASK_FLOAT128_KEYWORD \
@@ -125,6 +128,7 @@
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND\
| OPTION_MASK_POWER10 \
+| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
@@ -257,3 +261,4 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64,
OPTION_MASK_PPC_GFXOPT
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
| ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 |
ISA_POWER11_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 33fd0efc936..4f5af57ae1a 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -67,7 +67,8 @@ enum processor_type
PROCESSOR_MPCCORE,
PROCESSOR_CELL,
PROCESSOR_PPCA2,
- PROC
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=power11 support part 2
https://gcc.gnu.org/g:31e9b8945f5b9261b0d3f0f95465a5092a470205
commit 31e9b8945f5b9261b0d3f0f95465a5092a470205
Author: Michael Meissner
Date: Fri Mar 8 17:06:33 2024 -0500
Add -mcpu=power11 support part 2
This patch allows GCC to be configured with the --with-cpu=power11 and
--with-tune=power11 options.
This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
This patch adds support for using "power11" in the __builtin_cpu_is built-in
function.
2024-03-08 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
Diff:
---
gcc/config.gcc | 6 --
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/ppc-auxv.h| 3 +--
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000.h | 1 +
8 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 624e0dae191..8adc71d82e9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -531,7 +531,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5558,7 +5560,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d..41037b3852d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index c43974f577a..fe59f8319b4 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index b1572bde81f..1318b0b3662 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index 3ebbaa42622..f4900724b98 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -451,6 +451,7 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpwr8" },
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
+ { "power11", "-mpwr11" },
{ "powerpc", "-mppc" },
{ "rs64","-mppc" },
{ "603", "-m603" },
@@ -479,6 +480,7 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpower8" },
{ "power9", "-mpower9" },
{ "power10", "-mpower10" },
+ { "power11", "-mpower11" },
{ "a2", "-ma2" },
{ "powerpc", "-mppc" },
{ "powerpc64", "-mppc64" },
diff --git a/gcc/config/rs6000/ppc-auxv.h b/gcc/config/rs6000/ppc-auxv.h
index 364bba427d1..ed269e3b72b 100644
--- a/gcc/config/rs6000/ppc-auxv.h
+++ b/gc
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=power11 support part 3.
https://gcc.gnu.org/g:6e71a74b12f729ac8f11437829011e1882256061 commit 6e71a74b12f729ac8f11437829011e1882256061 Author: Michael Meissner Date: Fri Mar 8 17:11:47 2024 -0500 Add -mcpu=power11 support part 3. This patch makes -mtune=power11 use the same tuning decision as -mtune=power10. 2024-03-08 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add power11 as an alterntive to power10. Diff: --- gcc/config/rs6000/power10.md | 142 +-- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fcc2199ab29..22851db3318 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") ; stxvp (define_insn_reservation "power10-vecstore-pair" 0 (and (eq_attr "type" "vecstore") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,stu0_power10+stu1_power10")
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=power11 tests.
https://gcc.gnu.org/g:3901cdd34ce7d6c5258061c60a23a1fba3fbfe55
commit 3901cdd34ce7d6c5258061c60a23a1fba3fbfe55
Author: Michael Meissner
Date: Fri Mar 8 17:15:04 2024 -0500
Add -mcpu=power11 tests.
This patch adds some simple tests for -mcpu=power11 support. In order to
run
these tests, you need an assembler that supports the -mpwr11 option.
2024-03-08 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
* lib/target-supports.exp (check_effective_target_power11_ok): Add
new
effective target.
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++
gcc/testsuite/lib/target-supports.exp| 17 +
4 files changed, 60 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index 000..6a2e802eedf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index 000..7b9904c1d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index 000..9b2d643cc0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ae33c4f1e3a..f68e440c35e 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7104,6 +7104,23 @@ proc check_effective_target_power10_ok { } {
}
}
+# Return 1 if this is a PowerPC target supporting -mcpu=power11.
+
+proc check_effective_target_power11_ok { } {
+if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages power11_ok object {
+ int main (void) {
+ #ifndef _ARCH_PWR11
+ #error "-mcpu=power11 is not supported"
+ #endif
+ return 0;
+ }
+ } "-mcpu=power11"]
+} else {
+ return 0
+}
+}
+
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
[gcc(refs/users/meissner/heads/work162)] Update ChangeLog.*
https://gcc.gnu.org/g:336a35cac4639c05b04ccc4d61840a06aca04f4a commit 336a35cac4639c05b04ccc4d61840a06aca04f4a Author: Michael Meissner Date: Fri Mar 8 17:17:45 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 75 ++ 1 file changed, 63 insertions(+), 12 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 4ed95d0b991..57ff03ef74b 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,6 +1,45 @@ - Branch work162, patch #11 + Branch work162, patch #24 + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the -mpwr11 option. + +2024-03-08 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new + effective target. + + Branch work162, patch #23 + +Add -mcpu=power11 support part 3. + +This patch makes -mtune=power11 use the same tuning decision as -mtune=power10. + +2024-03-08 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add power11 as an + alterntive to power10. + + Branch work162, patch #22 + +Add -mcpu=power11 support part 2 + +This patch allows GCC to be configured with the --with-cpu=power11 and +--with-tune=power11 options. + +This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. + +This patch adds support for using "power11" in the __builtin_cpu_is built-in +function. -Add -mcpu=power11 support. 2024-03-08 Michael Meissner @@ -11,16 +50,35 @@ gcc/ * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. * config/rs6000/driver-rs6000.cc (asm_names): Likewise. - * config/rs6000/power10.md (all reservations): Add power11 as an - alterntive to power10. * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define. * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + + Branch work162, patch #21 + +Add -mcpu=power11 support. + +This patch adds the power11 option to the -mcpu= and -mtune= switches. + +This patch treats the power11 like a power10 in terms of costs and reassociation +width. + +This patch issues a ".machine power11" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. + +2024-03-08 Michael Meissner + +gcc/ + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define _ARCH_PWR11 if -mcpu=power11. * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define. (POWERPC_MASKS): Add power11 isa bit. (power11 cpu): Add power11 definition. * rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (power11_cost): Add power11 support. (rs6000_option_override_internal): Likewise. @@ -32,18 +90,11 @@ gcc/ (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Likewise. - * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add power11. * config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11. -gcc/testsuite/ - - * gcc.target/powerpc/power11-1.c: New test. - * gcc.target/powerpc/power11-2.c: Likewise. - * gcc.target/powerpc/power11-3.c: Likewise. - * lib/target-supports.exp (check_effective_target_power11_ok): Add new - effective target. + Branch work162, patch #11 was reverted Branch work162, patches #1..7 were reverted
[gcc r14-9403] ipa: Avoid excessive removing of SSAs (PR 113757)
https://gcc.gnu.org/g:54e505d0446f86b7ad383acbb8e5501f20872b64
commit r14-9403-g54e505d0446f86b7ad383acbb8e5501f20872b64
Author: Martin Jambor
Date: Sat Mar 9 00:47:22 2024 +0100
ipa: Avoid excessive removing of SSAs (PR 113757)
PR 113757 shows that the code which was meant to debug-reset and
remove SSAs defined by LHSs of calls redirected to
__builtin_unreachable can trigger also when speculative
devirtualization creates a call to a noreturn function (and since it
is noreturn, it does not bother dealing with its return value).
What is more, it seems that the code handling this case is not really
necessary. I feel slightly idiotic about this because I have a
feeling that I added it because of a failing test-case but I can
neither find the testcase nor a reason why the code in
cgraph_edge::redirect_call_stmt_to_callee would not be sufficient (it
turns the SSA name into a default-def, a bit like IPA-SRA, but any
code dominated by a call to a noreturn is not dangerous when it comes
to its side-effects). So this patch just removes the handling.
gcc/ChangeLog:
2024-02-07 Martin Jambor
PR ipa/113757
* tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
id->killed_new_ssa_names.
gcc/testsuite/ChangeLog:
2024-02-07 Martin Jambor
PR ipa/113757
* g++.dg/ipa/pr113757.C: New test.
Diff:
---
gcc/testsuite/g++.dg/ipa/pr113757.C | 14 ++
gcc/tree-inline.cc | 14 ++
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/gcc/testsuite/g++.dg/ipa/pr113757.C
b/gcc/testsuite/g++.dg/ipa/pr113757.C
new file mode 100644
index 000..885d4010a10
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ipa/pr113757.C
@@ -0,0 +1,14 @@
+// { dg-do compile }
+// { dg-options "-O2 -fPIC" }
+// { dg-require-effective-target fpic }
+
+long size();
+struct ll { virtual int hh(); };
+ll *slice_owner;
+int ll::hh() { __builtin_exit(0); }
+int nn() {
+ if (size())
+return 0;
+ return slice_owner->hh();
+}
+int (*a)() = nn;
diff --git a/gcc/tree-inline.cc b/gcc/tree-inline.cc
index f0a067f5812..eebcea8a029 100644
--- a/gcc/tree-inline.cc
+++ b/gcc/tree-inline.cc
@@ -2984,23 +2984,13 @@ redirect_all_calls (copy_body_data * id, basic_block bb)
gimple *stmt = gsi_stmt (si);
if (is_gimple_call (stmt))
{
- tree old_lhs = gimple_call_lhs (stmt);
struct cgraph_edge *edge = id->dst_node->get_edge (stmt);
if (edge)
{
if (!id->killed_new_ssa_names)
id->killed_new_ssa_names = new hash_set (16);
- gimple *new_stmt
- = cgraph_edge::redirect_call_stmt_to_callee (edge,
- id->killed_new_ssa_names);
- if (old_lhs
- && TREE_CODE (old_lhs) == SSA_NAME
- && !gimple_call_lhs (new_stmt))
- /* In case of IPA-SRA removing the LHS, the name should have
- been already added to the hash. But in case of redirecting
- to builtin_unreachable it was not and the name still should
- be pruned from debug statements. */
- id->killed_new_ssa_names->add (old_lhs);
+ cgraph_edge::redirect_call_stmt_to_callee (edge,
+ id->killed_new_ssa_names);
if (stmt == last && id->call_stmt && maybe_clean_eh_stmt (stmt))
gimple_purge_dead_eh_edges (bb);
[gcc/meissner/heads/work162-ajit] (24 commits) Merge commit 'refs/users/meissner/heads/work162-ajit' of gi
The branch 'meissner/heads/work162-ajit' was updated to point to: 5d73f63c135... Merge commit 'refs/users/meissner/heads/work162-ajit' of gi It previously pointed to: 6ff76c0056b... Add ChangeLog.ajit and update REVISION. Diff: Summary of changes (added commits): --- 5d73f63... Merge commit 'refs/users/meissner/heads/work162-ajit' of gi b51edbc... Add ChangeLog.ajit and update REVISION. 336a35c... Update ChangeLog.* (*) 3901cdd... Add -mcpu=power11 tests. (*) 6e71a74... Add -mcpu=power11 support part 3. (*) 31e9b89... Add -mcpu=power11 support part 2 (*) 0296376... Add -mcpu=power11 support. (*) 022085b... Revert some changes (*) 39310cc... Update ChangeLog.* (*) cc5432b... Add -mcpu=power11 support. (*) 799fc05... Revert some changes (*) 9e3ef76... Update ChangeLog.* (*) 1153585... Fix thinko (*) a6d5674... Update ChangeLog.* (*) c7f6d4b... Add power11 to rs6000-string.cc (*) d6d22a4... Update ChangeLog.* (*) e94d4f5... Allow configuration of power11 (*) 3679731... Reallow power11 2nd sched charges for sched pass one. (*) 654bc8f... Update ChangeLog.* (*) 4b97e79... Reallow power11 sched charges for sched pass one. (*) f03992d... Update ChangeLog.* (*) e6c7ed9... Revert some changes (*) 2f02fdf... Update ChangeLog.* (*) a82d291... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work162-ajit' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work162-ajit)] Add ChangeLog.ajit and update REVISION.
https://gcc.gnu.org/g:b51edbc68c611a63cac80f48a099b61fd2ce6124 commit b51edbc68c611a63cac80f48a099b61fd2ce6124 Author: Michael Meissner Date: Thu Mar 7 11:08:43 2024 -0500 Add ChangeLog.ajit and update REVISION. 2024-03-07 Michael Meissner gcc/ * ChangeLog.ajit: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.ajit | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.ajit b/gcc/ChangeLog.ajit new file mode 100644 index 000..eb5570e2484 --- /dev/null +++ b/gcc/ChangeLog.ajit @@ -0,0 +1,6 @@ + Branch work162-ajit, baseline + +2024-03-07 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 1f2b7b56b83..1fa4bd9178d 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work162 branch +work162-ajit branch
[gcc(refs/users/meissner/heads/work162-ajit)] Merge commit 'refs/users/meissner/heads/work162-ajit' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:5d73f63c13539fdffece4813e111fcf3b8022a02 commit 5d73f63c13539fdffece4813e111fcf3b8022a02 Merge: b51edbc68c6 6ff76c0056b Author: Michael Meissner Date: Fri Mar 8 18:57:47 2024 -0500 Merge commit 'refs/users/meissner/heads/work162-ajit' of git+ssh://gcc.gnu.org/git/gcc into me/work162-ajit Diff:
[gcc/meissner/heads/work162-dmf] (24 commits) Merge commit 'refs/users/meissner/heads/work162-dmf' of git
The branch 'meissner/heads/work162-dmf' was updated to point to: f8660bb40a9... Merge commit 'refs/users/meissner/heads/work162-dmf' of git It previously pointed to: 4b27e55d4c6... Add ChangeLog.dmf and update REVISION. Diff: Summary of changes (added commits): --- f8660bb... Merge commit 'refs/users/meissner/heads/work162-dmf' of git 0e8838d... Add ChangeLog.dmf and update REVISION. 336a35c... Update ChangeLog.* (*) 3901cdd... Add -mcpu=power11 tests. (*) 6e71a74... Add -mcpu=power11 support part 3. (*) 31e9b89... Add -mcpu=power11 support part 2 (*) 0296376... Add -mcpu=power11 support. (*) 022085b... Revert some changes (*) 39310cc... Update ChangeLog.* (*) cc5432b... Add -mcpu=power11 support. (*) 799fc05... Revert some changes (*) 9e3ef76... Update ChangeLog.* (*) 1153585... Fix thinko (*) a6d5674... Update ChangeLog.* (*) c7f6d4b... Add power11 to rs6000-string.cc (*) d6d22a4... Update ChangeLog.* (*) e94d4f5... Allow configuration of power11 (*) 3679731... Reallow power11 2nd sched charges for sched pass one. (*) 654bc8f... Update ChangeLog.* (*) 4b97e79... Reallow power11 sched charges for sched pass one. (*) f03992d... Update ChangeLog.* (*) e6c7ed9... Revert some changes (*) 2f02fdf... Update ChangeLog.* (*) a82d291... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work162-dmf' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work162-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:0e8838d70db787dfadc43efb612cd915e0878e21 commit 0e8838d70db787dfadc43efb612cd915e0878e21 Author: Michael Meissner Date: Thu Mar 7 11:05:59 2024 -0500 Add ChangeLog.dmf and update REVISION. 2024-03-07 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index 000..4bf550e6556 --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work162-dmf, baseline + +2024-03-07 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 1f2b7b56b83..58945f7a1ad 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work162 branch +work162-dmf branch
[gcc(refs/users/meissner/heads/work162-dmf)] Merge commit 'refs/users/meissner/heads/work162-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work16
https://gcc.gnu.org/g:f8660bb40a90101ed35c0244d367f553c35f95c3 commit f8660bb40a90101ed35c0244d367f553c35f95c3 Merge: 0e8838d70db 4b27e55d4c6 Author: Michael Meissner Date: Fri Mar 8 18:59:10 2024 -0500 Merge commit 'refs/users/meissner/heads/work162-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work162-dmf Diff:
[gcc/meissner/heads/work162-test] (24 commits) Merge commit 'refs/users/meissner/heads/work162-test' of gi
The branch 'meissner/heads/work162-test' was updated to point to: f8f47c34771... Merge commit 'refs/users/meissner/heads/work162-test' of gi It previously pointed to: 13f39d24c7c... Add ChangeLog.test and update REVISION. Diff: Summary of changes (added commits): --- f8f47c3... Merge commit 'refs/users/meissner/heads/work162-test' of gi 689b3ad... Add ChangeLog.test and update REVISION. 336a35c... Update ChangeLog.* (*) 3901cdd... Add -mcpu=power11 tests. (*) 6e71a74... Add -mcpu=power11 support part 3. (*) 31e9b89... Add -mcpu=power11 support part 2 (*) 0296376... Add -mcpu=power11 support. (*) 022085b... Revert some changes (*) 39310cc... Update ChangeLog.* (*) cc5432b... Add -mcpu=power11 support. (*) 799fc05... Revert some changes (*) 9e3ef76... Update ChangeLog.* (*) 1153585... Fix thinko (*) a6d5674... Update ChangeLog.* (*) c7f6d4b... Add power11 to rs6000-string.cc (*) d6d22a4... Update ChangeLog.* (*) e94d4f5... Allow configuration of power11 (*) 3679731... Reallow power11 2nd sched charges for sched pass one. (*) 654bc8f... Update ChangeLog.* (*) 4b97e79... Reallow power11 sched charges for sched pass one. (*) f03992d... Update ChangeLog.* (*) e6c7ed9... Revert some changes (*) 2f02fdf... Update ChangeLog.* (*) a82d291... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work162-test' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work162-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:689b3adeae096be74d72a87156883dcdf99d87d4 commit 689b3adeae096be74d72a87156883dcdf99d87d4 Author: Michael Meissner Date: Thu Mar 7 11:09:39 2024 -0500 Add ChangeLog.test and update REVISION. 2024-03-07 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index 000..9512bcddaf9 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work162-test, baseline + +2024-03-07 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 1f2b7b56b83..6bf4941fb03 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work162 branch +work162-test branch
[gcc(refs/users/meissner/heads/work162-test)] Merge commit 'refs/users/meissner/heads/work162-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:f8f47c3477162f6c0160eae55da973a2ab227417 commit f8f47c3477162f6c0160eae55da973a2ab227417 Merge: 689b3adeae0 13f39d24c7c Author: Michael Meissner Date: Fri Mar 8 19:00:24 2024 -0500 Merge commit 'refs/users/meissner/heads/work162-test' of git+ssh://gcc.gnu.org/git/gcc into me/work162-test Diff:
[gcc/meissner/heads/work162-vpair] (24 commits) Merge commit 'refs/users/meissner/heads/work162-vpair' of g
The branch 'meissner/heads/work162-vpair' was updated to point to: ed10bc0b1be... Merge commit 'refs/users/meissner/heads/work162-vpair' of g It previously pointed to: 9a1cabc3c3c... Add ChangeLog.vpair and update REVISION. Diff: Summary of changes (added commits): --- ed10bc0... Merge commit 'refs/users/meissner/heads/work162-vpair' of g 1e29771... Add ChangeLog.vpair and update REVISION. 336a35c... Update ChangeLog.* (*) 3901cdd... Add -mcpu=power11 tests. (*) 6e71a74... Add -mcpu=power11 support part 3. (*) 31e9b89... Add -mcpu=power11 support part 2 (*) 0296376... Add -mcpu=power11 support. (*) 022085b... Revert some changes (*) 39310cc... Update ChangeLog.* (*) cc5432b... Add -mcpu=power11 support. (*) 799fc05... Revert some changes (*) 9e3ef76... Update ChangeLog.* (*) 1153585... Fix thinko (*) a6d5674... Update ChangeLog.* (*) c7f6d4b... Add power11 to rs6000-string.cc (*) d6d22a4... Update ChangeLog.* (*) e94d4f5... Allow configuration of power11 (*) 3679731... Reallow power11 2nd sched charges for sched pass one. (*) 654bc8f... Update ChangeLog.* (*) 4b97e79... Reallow power11 sched charges for sched pass one. (*) f03992d... Update ChangeLog.* (*) e6c7ed9... Revert some changes (*) 2f02fdf... Update ChangeLog.* (*) a82d291... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work162-vpair' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work162-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:1e297710cc0f278b26d02cfead1ac48116e89aff commit 1e297710cc0f278b26d02cfead1ac48116e89aff Author: Michael Meissner Date: Thu Mar 7 11:07:00 2024 -0500 Add ChangeLog.vpair and update REVISION. 2024-03-07 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index 000..faeb03cac7b --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work162-vpair, baseline + +2024-03-07 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 1f2b7b56b83..5f53efe48c3 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work162 branch +work162-vpair branch
[gcc(refs/users/meissner/heads/work162-vpair)] Merge commit 'refs/users/meissner/heads/work162-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work
https://gcc.gnu.org/g:ed10bc0b1bee74ec29f44a18ba41392fd71a02c6 commit ed10bc0b1bee74ec29f44a18ba41392fd71a02c6 Merge: 1e297710cc0 9a1cabc3c3c Author: Michael Meissner Date: Fri Mar 8 19:01:41 2024 -0500 Merge commit 'refs/users/meissner/heads/work162-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work162-vpair Diff:
[gcc r14-9405] libstdc++: Fix parsing of leap seconds as chrono::utc_time [PR114279]
https://gcc.gnu.org/g:f4a52c184d608325c14338b57f464f7d0bbc7526
commit r14-9405-gf4a52c184d608325c14338b57f464f7d0bbc7526
Author: Jonathan Wakely
Date: Fri Mar 8 14:41:47 2024 +
libstdc++: Fix parsing of leap seconds as chrono::utc_time [PR114279]
Implementing all chrono::from_stream overloads in terms of
chrono::sys_time meant that a leap second time like 23:59:60.001 cannot
be parsed, because that cannot be represented in a sys_time.
The fix to support parsing leap seconds as utc_time is to convert the
parsed date to utc_time and then add the parsed time to that,
which allows the result to land in a leap second, rather than doing all
the arithmetic with sys_time which doesn't have leap seconds.
For local_time we also allow %S to parse a 60s value, because doing
otherwise might disallow some valid uses. We can't know all use cases
users have for treating times as local_time.
For all other clocks, we can reject times that have 60 or 60.nnn as the
seconds part, because that cannot occur in a valid UNIX, GPS, or TAI
time. Since our chrono::file_clock uses sys_time, it can't occur for
that clock either.
In order to support this a new _M_is_leap_second member is needed in the
_Parser type. This can be added at the end, where most targets currently
have padding bytes. Similar to what I did recently for formatter _Spec
structs, we can also reserve additional padding bits for future
expansion.
This also fixes bugs in the from_stream overloads for utc_time,
tai_time, gps_time, and file_time, which were not using time_point_cast
to explicitly convert to the result type. That's needed because the
result type might have lower precision than the value returned from
from_sys or from_utc, which has a precision no lower than seconds.
libstdc++-v3/ChangeLog:
PR libstdc++/114279
* include/bits/chrono_io.h (_Parser::_M_is_leap_second): New
data member.
(_Parser::_M_reserved): Reserve padding bits for future use.
(_Parser::operator()): Set _M_is_leap_second if %S reads 60s.
(from_stream): Only allow _M_is_leap_second for utc_time and
local_time. Adjust arithmetic for utc_time so that leap seconds
are preserved. Use time_point_cast to convert to a possibly
lower-precision result type.
* testsuite/std/time/parse.cc: Move to ...
* testsuite/std/time/parse/parse.cc: ... here.
* testsuite/std/time/parse/114279.cc: New test.
Diff:
---
libstdc++-v3/include/bits/chrono_io.h | 74 ++
libstdc++-v3/testsuite/std/time/parse/114279.cc| 53
.../testsuite/std/time/{ => parse}/parse.cc| 0
3 files changed, 115 insertions(+), 12 deletions(-)
diff --git a/libstdc++-v3/include/bits/chrono_io.h
b/libstdc++-v3/include/bits/chrono_io.h
index 412e8b83fb7..eaa36b8a074 100644
--- a/libstdc++-v3/include/bits/chrono_io.h
+++ b/libstdc++-v3/include/bits/chrono_io.h
@@ -2164,6 +2164,8 @@ namespace __detail
year_month_day _M_ymd{};
weekday _M_wd{};
__format::_ChronoParts _M_need;
+ unsigned _M_is_leap_second : 1 {};
+ unsigned _M_reserved : 15 {};
template
basic_istream<_CharT, _Traits>&
@@ -2742,8 +2744,13 @@ namespace __detail
__detail::_Parser_t<_Duration> __p(__need);
if (__p(__is, __fmt, __abbrev, __offset))
{
- auto __st = __p._M_sys_days + __p._M_time - *__offset;
- __tp = chrono::time_point_cast<_Duration>(__st);
+ if (__p._M_is_leap_second)
+ __is.setstate(ios_base::failbit);
+ else
+ {
+ auto __st = __p._M_sys_days + __p._M_time - *__offset;
+ __tp = chrono::time_point_cast<_Duration>(__st);
+ }
}
return __is;
}
@@ -2765,9 +2772,21 @@ namespace __detail
basic_string<_CharT, _Traits, _Alloc>* __abbrev = nullptr,
minutes* __offset = nullptr)
{
- sys_time<_Duration> __st;
- if (chrono::from_stream(__is, __fmt, __st, __abbrev, __offset))
- __tp = utc_clock::from_sys(__st);
+ minutes __off{};
+ if (!__offset)
+ __offset = &__off;
+ using __format::_ChronoParts;
+ auto __need = _ChronoParts::_Year | _ChronoParts::_Month
+ | _ChronoParts::_Day | _ChronoParts::_TimeOfDay;
+ __detail::_Parser_t<_Duration> __p(__need);
+ if (__p(__is, __fmt, __abbrev, __offset))
+ {
+ // Converting to utc_time before adding _M_time is necessary for
+ // "23:59:60" to correctly produce a time within a leap second.
+ auto __ut = utc_clock::from_sys(__p._M_sys_days) + __p._M_time
+ - *__offset;
+ __tp = chrono::time_point_cast<_Duration>(__ut);
+ }
return __is;
}
[gcc r14-9406] libstdc++: Do not require a time-of-day when parsing sys_days [PR114240]
https://gcc.gnu.org/g:3e8ee03edd018eed43444755f601cdb9d5931654
commit r14-9406-g3e8ee03edd018eed43444755f601cdb9d5931654
Author: Jonathan Wakely
Date: Fri Mar 8 16:15:57 2024 +
libstdc++: Do not require a time-of-day when parsing sys_days [PR114240]
When parsing a std::chrono::sys_days (or a sys_time with an even longer
period) we should not require a time-of-day to be present in the input,
because we can't represent that in the result type anyway.
Rather than trying to decide which specializations should require a
time-of-date and which should not, follow the direction of Howard
Hinnant's date library, which allows extracting a sys_time of any period
from input that only contains a date, defaulting the time-of-day part to
00:00:00. This seems consistent with the intent of the standard, which
says it's an error "If the parse fails to decode a valid date" (i.e., it
doesn't care about decoding a valid time, only a date).
libstdc++-v3/ChangeLog:
PR libstdc++/114240
* include/bits/chrono_io.h (_Parser::operator()): Assume
hours(0) for a time_point, so that a time is not required
to be present.
* testsuite/std/time/parse/114240.cc: New test.
Diff:
---
libstdc++-v3/include/bits/chrono_io.h | 12 -
libstdc++-v3/testsuite/std/time/parse/114240.cc | 36 +
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/libstdc++-v3/include/bits/chrono_io.h
b/libstdc++-v3/include/bits/chrono_io.h
index eaa36b8a074..b9eb3d2be53 100644
--- a/libstdc++-v3/include/bits/chrono_io.h
+++ b/libstdc++-v3/include/bits/chrono_io.h
@@ -3157,6 +3157,16 @@ namespace __detail
minutes __tz_offset = __bad_min;
basic_string<_CharT, _Traits> __tz_abbr;
+ if ((_M_need & _ChronoParts::_TimeOfDay)
+ && (_M_need & _ChronoParts::_Year))
+ {
+ // For time_points assume "00:00:00" is implicitly present,
+ // so we don't fail to parse if it's not (PR libstdc++/114240).
+ // We will still fail to parse if there's no year+month+day.
+ __h = hours(0);
+ __parts = _ChronoParts::_TimeOfDay;
+ }
+
// bool __is_neg = false; // TODO: how is this handled for parsing?
_CharT __mod{}; // One of 'E' or 'O' or nul.
@@ -4098,7 +4108,7 @@ namespace __detail
const bool __need_wday = _M_need & _ChronoParts::_Weekday;
// Whether the caller wants _M_sys_days and _M_time.
- // Only true for time_points.
+ // Only true for durations and time_points.
const bool __need_time = _M_need & _ChronoParts::_TimeOfDay;
if (__need_wday && __wday != __bad_wday)
diff --git a/libstdc++-v3/testsuite/std/time/parse/114240.cc
b/libstdc++-v3/testsuite/std/time/parse/114240.cc
new file mode 100644
index 000..46310efd09a
--- /dev/null
+++ b/libstdc++-v3/testsuite/std/time/parse/114240.cc
@@ -0,0 +1,36 @@
+// { dg-do run { target c++20 } }
+
+// PR libstdc++/114240 sys_days not being parsed with only a date in the stream
+
+#include
+#include
+#include
+
+template
+void
+test_parse_date_only()
+{
+ using namespace std::chrono;
+
+ using CDays = time_point;
+ CDays td;
+ std::istringstream is("2024-03-05");
+ VERIFY( is >> parse("%Y-%m-%d ", td) );
+ if constexpr (std::is_same_v)
+VERIFY( td == static_cast>(2024y/March/5) );
+ else
+ {
+auto tp = clock_cast(sys_days(2024y/March/5));
+VERIFY( td == time_point_cast(tp) );
+ }
+}
+
+int main()
+{
+ test_parse_date_only();
+ test_parse_date_only();
+ test_parse_date_only();
+ test_parse_date_only();
+ test_parse_date_only();
+ test_parse_date_only();
+}
[gcc r14-9407] LoongArch: Fixed an issue with the implementation of the template atomic_compare_and_swapsi.
https://gcc.gnu.org/g:3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2
commit r14-9407-g3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2
Author: Lulu Cheng
Date: Tue Mar 5 14:43:04 2024 +0800
LoongArch: Fixed an issue with the implementation of the template
atomic_compare_and_swapsi.
If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to
be
implemented through "ll.w+sc.w". In the implementation of the instruction
sequence,
it is necessary to determine whether the two registers are equal.
Since LoongArch's comparison instructions do not distinguish between 32-bit
and 64-bit, the two operand registers that need to be compared are
symbolically
extended, and one of the operand registers is obtained from memory through
the
"ll.w" instruction, which can ensure that the symbolic expansion is carried
out.
However, the value of the other operand register is not guaranteed to be the
value of the sign extension.
gcc/ChangeLog:
* config/loongarch/sync.md (atomic_cas_value_strong):
In loongarch64, a sign extension operation is added when
operands[2] is a register operand and the mode is SImode.
gcc/testsuite/ChangeLog:
* g++.target/loongarch/atomic-cas-int.C: New test.
Diff:
---
gcc/config/loongarch/sync.md | 46 --
.../g++.target/loongarch/atomic-cas-int.C | 32 +++
2 files changed, 67 insertions(+), 11 deletions(-)
diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index 8f35a5b48d2..d41c2d26811 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -245,18 +245,42 @@
(clobber (match_scratch:GPR 5 "=&r"))]
""
{
- return "1:\\n\\t"
-"ll.\\t%0,%1\\n\\t"
-"bne\\t%0,%z2,2f\\n\\t"
-"or%i3\\t%5,$zero,%3\\n\\t"
-"sc.\\t%5,%1\\n\\t"
-"beqz\\t%5,1b\\n\\t"
-"b\\t3f\\n\\t"
-"2:\\n\\t"
-"%G4\\n\\t"
-"3:\\n\\t";
+ output_asm_insn ("1:", operands);
+ output_asm_insn ("ll.\t%0,%1", operands);
+
+ /* Like the test case atomic-cas-int.C, in loongarch64, O1 and higher, the
+ return value of the val_without_const_folding will not be truncated and
+ will be passed directly to the function compare_exchange_strong.
+ However, the instruction 'bne' does not distinguish between 32-bit and
+ 64-bit operations. so if the upper 32 bits of the register are not
+ extended by the 32nd bit symbol, then the comparison may not be valid
+ here. This will affect the result of the operation. */
+
+ if (TARGET_64BIT && REG_P (operands[2])
+ && GET_MODE (operands[2]) == SImode)
+{
+ output_asm_insn ("addi.w\t%5,%2,0", operands);
+ output_asm_insn ("bne\t%0,%5,2f", operands);
+}
+ else
+output_asm_insn ("bne\t%0,%z2,2f", operands);
+
+ output_asm_insn ("or%i3\t%5,$zero,%3", operands);
+ output_asm_insn ("sc.\t%5,%1", operands);
+ output_asm_insn ("beqz\t%5,1b", operands);
+ output_asm_insn ("b\t3f", operands);
+ output_asm_insn ("2:", operands);
+ output_asm_insn ("%G4", operands);
+ output_asm_insn ("3:", operands);
+
+ return "";
}
- [(set (attr "length") (const_int 28))])
+ [(set (attr "length")
+ (if_then_else
+ (and (match_test "GET_MODE (operands[2]) == SImode")
+(match_test "REG_P (operands[2])"))
+ (const_int 32)
+ (const_int 28)))])
(define_insn "atomic_cas_value_strong_amcas"
[(set (match_operand:QHWD 0 "register_operand" "=&r")
diff --git a/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
new file mode 100644
index 000..830ce48267a
--- /dev/null
+++ b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include
+#include
+
+__attribute__ ((noinline)) long
+val_without_const_folding (long val)
+{
+ return val;
+}
+
+int
+main ()
+{
+ int oldval = 0xaa;
+ int newval = 0xbb;
+ std::atomic amo;
+
+ amo.store (oldval);
+
+ long longval = val_without_const_folding (0xff80 + oldval);
+ oldval = static_cast (longval);
+
+ amo.compare_exchange_strong (oldval, newval);
+
+ if (newval != amo.load (std::memory_order_relaxed))
+__builtin_abort ();
+
+ return 0;
+}
+
[gcc r14-9408] LoongArch: testsuite: Add compilation options to the regname-fp-s9.c.
https://gcc.gnu.org/g:6fe63013e3292a45288461b7efa9d52e0ac234dc
commit r14-9408-g6fe63013e3292a45288461b7efa9d52e0ac234dc
Author: Lulu Cheng
Date: Thu Mar 7 09:44:03 2024 +0800
LoongArch: testsuite: Add compilation options to the regname-fp-s9.c.
When the value of the macro DEFAULT_CFLAGS is set to '-ansi
-pedantic-errors',
regname-s9-fp.c will test to fail. To solve this problem, add the
compilation
option '-Wno-pedantic -std=gnu90' to this test case.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/regname-fp-s9.c: Add compilation option
'-Wno-pedantic -std=gnu90'.
Diff:
---
gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c
b/gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c
index d2e3b80f83c..77a74f1f667 100644
--- a/gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c
+++ b/gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c
@@ -1,3 +1,4 @@
/* { dg-do compile } */
+/* { dg-additional-options "-Wno-pedantic -std=gnu90" } */
register long s9 asm("s9"); /* { dg-note "conflicts with 's9'" } */
register long fp asm("fp"); /* { dg-warning "register of 'fp' used for
multiple global register variables" } */
[gcc(refs/users/meissner/heads/work162)] Revert some changes
https://gcc.gnu.org/g:448253a197ef21591eed7b67a6d1c49baaa673e5
commit 448253a197ef21591eed7b67a6d1c49baaa673e5
Author: Michael Meissner
Date: Fri Mar 8 22:30:22 2024 -0500
Revert some changes
Diff:
---
gcc/config.gcc | 6 +-
gcc/config/rs6000/aix71.h| 1 -
gcc/config/rs6000/aix72.h| 1 -
gcc/config/rs6000/aix73.h| 1 -
gcc/config/rs6000/driver-rs6000.cc | 2 -
gcc/config/rs6000/power10.md | 142 +--
gcc/config/rs6000/ppc-auxv.h | 3 +-
gcc/config/rs6000/rs6000-builtin.cc | 1 -
gcc/config/rs6000/rs6000-c.cc| 2 -
gcc/config/rs6000/rs6000-cpus.def| 5 -
gcc/config/rs6000/rs6000-opts.h | 3 +-
gcc/config/rs6000/rs6000-string.cc | 1 -
gcc/config/rs6000/rs6000-tables.opt | 3 -
gcc/config/rs6000/rs6000.cc | 50 ++
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt | 3 -
gcc/doc/invoke.texi | 5 +-
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 ---
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 --
gcc/testsuite/lib/target-supports.exp| 17
22 files changed, 85 insertions(+), 207 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 8adc71d82e9..624e0dae191 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -531,9 +531,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
- xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
- | xe5500 | xe6500)
+
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5560,7 +5558,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x \
+ | power[3456789] | power10 | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d..24bc301e37d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b4..c43974f577a 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 1318b0b3662..b1572bde81f 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index f4900724b98..3ebbaa42622 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -451,7 +451,6 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpwr8" },
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
- { "power11", "-mpwr11" },
{ "powerpc", "-mppc" },
{ "rs64","-mppc" },
{ "603", "-m603" },
@@ -480,7 +479,6 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpower8" },
{ "power9", "-mpower9" },
{ "power10", "-mpower10" },
- { "power11", "-mpower11" },
{ "a2", "-ma2" },
{ "powerpc", "-mppc" },
{ "powerpc64", "-mppc64" },
diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index 22851db3318..fcc2199ab29 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -97,12 +97,12 @@
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=power11 support.
https://gcc.gnu.org/g:79df8d6772b1aecab388c0853cac305837a18b18
commit 79df8d6772b1aecab388c0853cac305837a18b18
Author: Michael Meissner
Date: Fri Mar 8 22:46:47 2024 -0500
Add -mcpu=power11 support.
This patch adds the power11 option to the -mcpu= and -mtune= switches.
This patch treats the power11 like a power10 in terms of costs and
reassociation
width.
This patch issues a ".machine power11" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
2024-03-08 Michael Meissner
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR11 if -mcpu=power11.
* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add power11 isa bit.
(power11 cpu): Add power11 definition.
* rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (power11_cost): Add power11 support.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add power11.
* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=power11.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 29 ++---
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 5 +++--
9 files changed, 42 insertions(+), 11 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index ce0b14a8d37..ebed8b9554a 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -447,6 +447,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
if ((flags & OPTION_MASK_POWER10) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
+ if ((flags & OPTION_MASK_POWER11) != 0)
+rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 28249600318..3237a5ada30 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,6 +86,9 @@
| OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS)
+#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
+ | OPTION_MASK_POWER11)
+
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
| OPTION_MASK_FLOAT128_KEYWORD \
@@ -125,6 +128,7 @@
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND\
| OPTION_MASK_POWER10 \
+| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
@@ -257,3 +261,4 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64,
OPTION_MASK_PPC_GFXOPT
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
| ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 |
ISA_POWER11_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 33fd0efc936..4f5af57ae1a 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -67,7 +67,8 @@ enum processor_type
PROCESSOR_MPCCORE,
PROCESSOR_CELL,
PROCESSOR_PPCA2,
- PROCESSOR_
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=power11 support part 2
https://gcc.gnu.org/g:a09c97da2830f55b5cc1509f67188867df14cdf3
commit a09c97da2830f55b5cc1509f67188867df14cdf3
Author: Michael Meissner
Date: Fri Mar 8 22:47:22 2024 -0500
Add -mcpu=power11 support part 2
This patch allows GCC to be configured with the --with-cpu=power11 and
--with-tune=power11 options.
This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
This patch adds support for using "power11" in the __builtin_cpu_is built-in
function.
2024-03-08 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
Diff:
---
gcc/config.gcc | 6 --
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/ppc-auxv.h| 3 +--
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000.h | 1 +
8 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 624e0dae191..8adc71d82e9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -531,7 +531,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5558,7 +5560,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d..41037b3852d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index c43974f577a..fe59f8319b4 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index b1572bde81f..1318b0b3662 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index 3ebbaa42622..f4900724b98 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -451,6 +451,7 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpwr8" },
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
+ { "power11", "-mpwr11" },
{ "powerpc", "-mppc" },
{ "rs64","-mppc" },
{ "603", "-m603" },
@@ -479,6 +480,7 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpower8" },
{ "power9", "-mpower9" },
{ "power10", "-mpower10" },
+ { "power11", "-mpower11" },
{ "a2", "-ma2" },
{ "powerpc", "-mppc" },
{ "powerpc64", "-mppc64" },
diff --git a/gcc/config/rs6000/ppc-auxv.h b/gcc/config/rs6000/ppc-auxv.h
index 364bba427d1..ed269e3b72b 100644
--- a/gcc/config/rs6000/ppc-auxv.h
+++ b/gc
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=power11 support part 3.
https://gcc.gnu.org/g:8939ee2bb506e2a2efadf48105f35aba964a4afd commit 8939ee2bb506e2a2efadf48105f35aba964a4afd Author: Michael Meissner Date: Fri Mar 8 22:47:58 2024 -0500 Add -mcpu=power11 support part 3. This patch makes -mtune=power11 use the same tuning decision as -mtune=power10. 2024-03-08 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add power11 as an alterntive to power10. Diff: --- gcc/config/rs6000/power10.md | 142 +-- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fcc2199ab29..22851db3318 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") ; stxvp (define_insn_reservation "power10-vecstore-pair" 0 (and (eq_attr "type" "vecstore") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,stu0_power10+stu1_power10")
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=power11 tests.
https://gcc.gnu.org/g:35fe3606f7e3a96836e68e99cca93c21ff9fb817
commit 35fe3606f7e3a96836e68e99cca93c21ff9fb817
Author: Michael Meissner
Date: Fri Mar 8 22:48:41 2024 -0500
Add -mcpu=power11 tests.
This patch adds some simple tests for -mcpu=power11 support. In order to
run
these tests, you need an assembler that supports the -mpwr11 option.
2024-03-08 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
* lib/target-supports.exp (check_effective_target_power11_ok): Add
new
effective target.
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++
gcc/testsuite/lib/target-supports.exp| 17 +
4 files changed, 60 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index 000..6a2e802eedf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index 000..7b9904c1d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index 000..9b2d643cc0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ae33c4f1e3a..f68e440c35e 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7104,6 +7104,23 @@ proc check_effective_target_power10_ok { } {
}
}
+# Return 1 if this is a PowerPC target supporting -mcpu=power11.
+
+proc check_effective_target_power11_ok { } {
+if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages power11_ok object {
+ int main (void) {
+ #ifndef _ARCH_PWR11
+ #error "-mcpu=power11 is not supported"
+ #endif
+ return 0;
+ }
+ } "-mcpu=power11"]
+} else {
+ return 0
+}
+}
+
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=future support.
https://gcc.gnu.org/g:522bd06b7abf4de674693dc57569547e6de09306
commit 522bd06b7abf4de674693dc57569547e6de09306
Author: Michael Meissner
Date: Fri Mar 8 23:14:31 2024 -0500
Add -mcpu=future support.
This patch adds the future option to the -mcpu= and -mtune= switches.
This patch treats the future like a power11 in terms of costs and
reassociation
width.
This patch issues a ".machine future" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
2024-03-08 Michael Meissner
gcc/
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add future isa bit.
(power11 cpu): Add future definition.
* rs6000-opts.h (PROCESSOR_FUTURE): Add future processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
future
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add future.
* config/rs6000/rs6000.opt (-mpower11): Add internal future ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=future.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 26 --
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 2 +-
9 files changed, 38 insertions(+), 9 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index ebed8b9554a..d15bb85743c 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -449,6 +449,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
if ((flags & OPTION_MASK_POWER11) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
+ if ((flags & OPTION_MASK_FUTURE) != 0)
+rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 3237a5ada30..47365534af8 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -89,6 +89,9 @@
#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
| OPTION_MASK_POWER11)
+#define ISA_FUTURE_MASKS_SERVER(ISA_POWER11_MASKS_SERVER
\
+| OPTION_MASK_FUTURE)
+
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
| OPTION_MASK_FLOAT128_KEYWORD \
@@ -127,6 +130,7 @@
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND\
+| OPTION_MASK_FUTURE \
| OPTION_MASK_POWER10 \
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
@@ -262,3 +266,4 @@ RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
| ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 |
ISA_POWER11_MASKS_SERVER)
+RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 |
ISA_FUTURE_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 4f5af57ae1a..d6c766309aa 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -68,7 +68,8 @@ enum processor_type
PROCESSOR_CELL,
PROCESSOR_PPCA2,
PROCESSOR_TITAN,
- PROCESSOR_POWER11
+ P
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=future support part 2
https://gcc.gnu.org/g:ea0193ba078ba6d9747329266de9aa9b2a9bb5d5
commit ea0193ba078ba6d9747329266de9aa9b2a9bb5d5
Author: Michael Meissner
Date: Fri Mar 8 23:26:03 2024 -0500
Add -mcpu=future support part 2
This patch allows GCC to be configured with the --with-cpu=future and
--with-tune=future options.
This patch passes -mfutue to the assembler if the user uses -mcpu=future.
2024-03-08 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/rs6000.h | 3 ++-
6 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 8adc71d82e9..e0ae4760539 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -532,7 +532,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
| xe5500 | xe6500)
cpu_is_64bit=yes
;;
@@ -5560,7 +5560,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x |
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b4..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 1318b0b3662..2bd6b4bb3c4 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index f4900724b98..07852fa50cf 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -441,6 +441,7 @@ struct asm_name {
static const struct asm_name asm_names[] = {
#if defined (_AIX)
+ { "future", "-mfuture" },
{ "power3", "-m620" },
{ "power4", "-mpwr4" },
{ "power5", "-mpwr5" },
@@ -470,6 +471,7 @@ static const struct asm_name asm_names[] = {
#else
{ "cell","-mcell" },
+ { "future", "-mfuture },
{ "power3", "-mppc64" },
{ "power4", "-mpower4" },
{ "power5", "-mpower5" },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 81e2f0a33ef..79ce1a8cbf1 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -106,8 +106,9 @@
you make changes here, make them also there. */
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=power10: -mpower10; \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpower11; \
+ mcpu=power10: -mpower10; \
mcpu=power9: -mpower9; \
mcpu=power8|mcpu=powerpc64le: -mpower8; \
mcpu=power7: -mpower7; \
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=future support part 3.
https://gcc.gnu.org/g:6712015cc1f80178502cf904fef6102ce76022e0 commit 6712015cc1f80178502cf904fef6102ce76022e0 Author: Michael Meissner Date: Fri Mar 8 23:28:52 2024 -0500 Add -mcpu=future support part 3. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2024-03-08 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 142 +-- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 22851db3318..a9deff0e8ec 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") ; stxvp (define_ins
[gcc(refs/users/meissner/heads/work162)] Revert all changes
https://gcc.gnu.org/g:ae3aa1809af8e3ce60b33a0e7c39139ea86a1ee8
commit ae3aa1809af8e3ce60b33a0e7c39139ea86a1ee8
Author: Michael Meissner
Date: Fri Mar 8 23:30:40 2024 -0500
Revert all changes
Diff:
---
gcc/config.gcc | 6 +-
gcc/config/rs6000/aix71.h| 2 -
gcc/config/rs6000/aix72.h| 2 -
gcc/config/rs6000/aix73.h| 2 -
gcc/config/rs6000/driver-rs6000.cc | 4 -
gcc/config/rs6000/power10.md | 142 +--
gcc/config/rs6000/ppc-auxv.h | 3 +-
gcc/config/rs6000/rs6000-builtin.cc | 1 -
gcc/config/rs6000/rs6000-c.cc| 4 -
gcc/config/rs6000/rs6000-cpus.def| 10 --
gcc/config/rs6000/rs6000-opts.h | 4 +-
gcc/config/rs6000/rs6000-string.cc | 2 -
gcc/config/rs6000/rs6000-tables.opt | 6 --
gcc/config/rs6000/rs6000.cc | 43 ++--
gcc/config/rs6000/rs6000.h | 2 -
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt | 6 --
gcc/doc/invoke.texi | 5 +-
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 ---
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 --
gcc/testsuite/lib/target-supports.exp| 17
22 files changed, 86 insertions(+), 220 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index e0ae4760539..624e0dae191 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -531,9 +531,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
- xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
- | xe5500 | xe6500)
+
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5560,7 +5558,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x |
future \
+ | power[3456789] | power10 | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 570ddcc451d..24bc301e37d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,8 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
- mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index 242ca94bd06..c43974f577a 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,8 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
- mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 2bd6b4bb3c4..b1572bde81f 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,8 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
- mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index 07852fa50cf..3ebbaa42622 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -441,7 +441,6 @@ struct asm_name {
static const struct asm_name asm_names[] = {
#if defined (_AIX)
- { "future", "-mfuture" },
{ "power3", "-m620" },
{ "power4", "-mpwr4" },
{ "power5", "-mpwr5" },
@@ -452,7 +451,6 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpwr8" },
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
- { "power11", "-mpwr11" },
{ "powerpc", "-mppc" },
{ "rs64","-mppc" },
{ "603", "-m603" },
@@ -471,7 +469,6 @@ static const struct asm_name asm_names[] = {
#else
{ "cell","-mcell" },
- { "future", "-mfuture },
{ "power3", "-
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=power11 support.
https://gcc.gnu.org/g:a2e7314507fe70f16adad23dbc68a421728ff6a0
commit a2e7314507fe70f16adad23dbc68a421728ff6a0
Author: Michael Meissner
Date: Fri Mar 8 23:48:20 2024 -0500
Add -mcpu=power11 support.
This patch adds the power11 option to the -mcpu= and -mtune= switches.
This patch treats the power11 like a power10 in terms of costs and
reassociation
width.
This patch issues a ".machine power11" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
This patch allows GCC to be configured with the --with-cpu=power11 and
--with-tune=power11 options.
This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
This patch adds support for using "power11" in the __builtin_cpu_is built-in
function.
2024-03-08 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR11 if -mcpu=power11.
* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add power11 isa bit.
(power11 cpu): Add power11 definition.
* rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
power11
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add power11.
* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=power11.
Diff:
---
gcc/config.gcc | 6 --
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/ppc-auxv.h| 3 +--
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 29 ++---
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 5 +++--
17 files changed, 54 insertions(+), 15 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 624e0dae191..8adc71d82e9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -531,7 +531,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5558,7 +5560,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d..41037b3852d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=power11 tuning support.
https://gcc.gnu.org/g:34edbd6e747facce21703d48f6c513e9caa19315 commit 34edbd6e747facce21703d48f6c513e9caa19315 Author: Michael Meissner Date: Fri Mar 8 23:51:01 2024 -0500 Add -mcpu=power11 tuning support. This patch makes -mtune=power11 use the same tuning decision as -mtune=power10. 2024-03-08 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add power11 as an alterntive to power10. Diff: --- gcc/config/rs6000/power10.md | 142 +-- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fcc2199ab29..22851db3318 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") ; stxvp (define_insn_reservation "power10-vecstore-pair" 0 (and (eq_attr "type" "vecstore") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,stu0_power10+stu1_power10")
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=power11 tests.
https://gcc.gnu.org/g:c87c9fa6ccf75da5ddf2b774e7f40bec244a9bdc
commit c87c9fa6ccf75da5ddf2b774e7f40bec244a9bdc
Author: Michael Meissner
Date: Fri Mar 8 23:52:28 2024 -0500
Add -mcpu=power11 tests.
This patch adds some simple tests for -mcpu=power11 support. In order to
run
these tests, you need an assembler that supports the -mpwr11 option.
2024-03-08 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
* lib/target-supports.exp (check_effective_target_power11_ok): Add
new
effective target.
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++
gcc/testsuite/lib/target-supports.exp| 17 +
4 files changed, 60 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index 000..6a2e802eedf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index 000..7b9904c1d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index 000..9b2d643cc0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ae33c4f1e3a..f68e440c35e 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7104,6 +7104,23 @@ proc check_effective_target_power10_ok { } {
}
}
+# Return 1 if this is a PowerPC target supporting -mcpu=power11.
+
+proc check_effective_target_power11_ok { } {
+if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages power11_ok object {
+ int main (void) {
+ #ifndef _ARCH_PWR11
+ #error "-mcpu=power11 is not supported"
+ #endif
+ return 0;
+ }
+ } "-mcpu=power11"]
+} else {
+ return 0
+}
+}
+
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=future support.
https://gcc.gnu.org/g:5180f01d1d48691a088a0074d5a402ab4530d7f7
commit 5180f01d1d48691a088a0074d5a402ab4530d7f7
Author: Michael Meissner
Date: Sat Mar 9 00:05:03 2024 -0500
Add -mcpu=future support.
This patch adds the future option to the -mcpu= and -mtune= switches.
This patch treats the future like a power11 in terms of costs and
reassociation
width.
This patch issues a ".machine future" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
This patch allows GCC to be configured with the --with-cpu=future and
--with-tune=future options.
This patch passes -mfuture to the assembler if the user uses -mcpu=future.
2024-03-08 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add future isa bit.
(power11 cpu): Add future definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
future
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add future.
* config/rs6000/rs6000.opt (-mpower11): Add internal future ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=future.
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 26 --
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 2 +-
15 files changed, 46 insertions(+), 11 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 8adc71d82e9..e0ae4760539 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -532,7 +532,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
| xe5500 | xe6500)
cpu_is_64bit=yes
;;
@@ -5560,7 +5560,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x |
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b4..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work162)] Add -mcpu=future tuning support.
https://gcc.gnu.org/g:0746a203639d08e07d35a09a0160a92298f5ff71 commit 0746a203639d08e07d35a09a0160a92298f5ff71 Author: Michael Meissner Date: Sat Mar 9 00:07:07 2024 -0500 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2024-03-08 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 142 +-- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 22851db3318..a9deff0e8ec 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") ; stxvp (define_ins
[gcc r13-8413] LoongArch: Fixed an issue with the implementation of the template atomic_compare_and_swapsi.
https://gcc.gnu.org/g:bf784936bc8be013db8b3e35002e76838f830f40
commit r13-8413-gbf784936bc8be013db8b3e35002e76838f830f40
Author: Lulu Cheng
Date: Tue Mar 5 14:43:04 2024 +0800
LoongArch: Fixed an issue with the implementation of the template
atomic_compare_and_swapsi.
If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to
be
implemented through "ll.w+sc.w". In the implementation of the instruction
sequence,
it is necessary to determine whether the two registers are equal.
Since LoongArch's comparison instructions do not distinguish between 32-bit
and 64-bit, the two operand registers that need to be compared are
symbolically
extended, and one of the operand registers is obtained from memory through
the
"ll.w" instruction, which can ensure that the symbolic expansion is carried
out.
However, the value of the other operand register is not guaranteed to be the
value of the sign extension.
gcc/ChangeLog:
* config/loongarch/sync.md (atomic_cas_value_strong):
In loongarch64, a sign extension operation is added when
operands[2] is a register operand and the mode is SImode.
gcc/testsuite/ChangeLog:
* g++.target/loongarch/atomic-cas-int.C: New test.
(cherry picked from commit 3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2)
Diff:
---
gcc/config/loongarch/sync.md | 46 --
.../g++.target/loongarch/atomic-cas-int.C | 32 +++
2 files changed, 67 insertions(+), 11 deletions(-)
diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index db3a21690b8..89956e07c79 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -129,18 +129,42 @@
(clobber (match_scratch:GPR 6 "=&r"))]
""
{
- return "1:\\n\\t"
-"ll.\\t%0,%1\\n\\t"
-"bne\\t%0,%z2,2f\\n\\t"
-"or%i3\\t%6,$zero,%3\\n\\t"
-"sc.\\t%6,%1\\n\\t"
-"beqz\\t%6,1b\\n\\t"
-"b\\t3f\\n\\t"
-"2:\\n\\t"
-"%G5\\n\\t"
-"3:\\n\\t";
+ output_asm_insn ("1:", operands);
+ output_asm_insn ("ll.\t%0,%1", operands);
+
+ /* Like the test case atomic-cas-int.C, in loongarch64, O1 and higher, the
+ return value of the val_without_const_folding will not be truncated and
+ will be passed directly to the function compare_exchange_strong.
+ However, the instruction 'bne' does not distinguish between 32-bit and
+ 64-bit operations. so if the upper 32 bits of the register are not
+ extended by the 32nd bit symbol, then the comparison may not be valid
+ here. This will affect the result of the operation. */
+
+ if (TARGET_64BIT && REG_P (operands[2])
+ && GET_MODE (operands[2]) == SImode)
+{
+ output_asm_insn ("addi.w\t%6,%2,0", operands);
+ output_asm_insn ("bne\t%0,%6,2f", operands);
+}
+ else
+output_asm_insn ("bne\t%0,%z2,2f", operands);
+
+ output_asm_insn ("or%i3\t%6,$zero,%3", operands);
+ output_asm_insn ("sc.\t%6,%1", operands);
+ output_asm_insn ("beqz\t%6,1b", operands);
+ output_asm_insn ("b\t3f", operands);
+ output_asm_insn ("2:", operands);
+ output_asm_insn ("%G5", operands);
+ output_asm_insn ("3:", operands);
+
+ return "";
}
- [(set (attr "length") (const_int 28))])
+ [(set (attr "length")
+ (if_then_else
+ (and (match_test "GET_MODE (operands[2]) == SImode")
+(match_test "REG_P (operands[2])"))
+ (const_int 32)
+ (const_int 28)))])
(define_expand "atomic_compare_and_swap"
[(match_operand:SI 0 "register_operand" "") ;; bool output
diff --git a/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
new file mode 100644
index 000..830ce48267a
--- /dev/null
+++ b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include
+#include
+
+__attribute__ ((noinline)) long
+val_without_const_folding (long val)
+{
+ return val;
+}
+
+int
+main ()
+{
+ int oldval = 0xaa;
+ int newval = 0xbb;
+ std::atomic amo;
+
+ amo.store (oldval);
+
+ long longval = val_without_const_folding (0xff80 + oldval);
+ oldval = static_cast (longval);
+
+ amo.compare_exchange_strong (oldval, newval);
+
+ if (newval != amo.load (std::memory_order_relaxed))
+__builtin_abort ();
+
+ return 0;
+}
+
[gcc r12-10200] LoongArch: Fixed an issue with the implementation of the template atomic_compare_and_swapsi.
https://gcc.gnu.org/g:d77ed1d6eb82fb5ef5cd94c06f5c67db753fb7c2
commit r12-10200-gd77ed1d6eb82fb5ef5cd94c06f5c67db753fb7c2
Author: Lulu Cheng
Date: Tue Mar 5 14:43:04 2024 +0800
LoongArch: Fixed an issue with the implementation of the template
atomic_compare_and_swapsi.
If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to
be
implemented through "ll.w+sc.w". In the implementation of the instruction
sequence,
it is necessary to determine whether the two registers are equal.
Since LoongArch's comparison instructions do not distinguish between 32-bit
and 64-bit, the two operand registers that need to be compared are
symbolically
extended, and one of the operand registers is obtained from memory through
the
"ll.w" instruction, which can ensure that the symbolic expansion is carried
out.
However, the value of the other operand register is not guaranteed to be the
value of the sign extension.
gcc/ChangeLog:
* config/loongarch/sync.md (atomic_cas_value_strong):
In loongarch64, a sign extension operation is added when
operands[2] is a register operand and the mode is SImode.
gcc/testsuite/ChangeLog:
* g++.target/loongarch/atomic-cas-int.C: New test.
(cherry picked from commit 3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2)
Diff:
---
gcc/config/loongarch/sync.md | 46 --
.../g++.target/loongarch/atomic-cas-int.C | 32 +++
2 files changed, 67 insertions(+), 11 deletions(-)
diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index b8763b8f9d1..c2f0d33ab21 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -129,18 +129,42 @@
(clobber (match_scratch:GPR 6 "=&r"))]
""
{
- return "1:\\n\\t"
-"ll.\\t%0,%1\\n\\t"
-"bne\\t%0,%z2,2f\\n\\t"
-"or%i3\\t%6,$zero,%3\\n\\t"
-"sc.\\t%6,%1\\n\\t"
-"beqz\\t%6,1b\\n\\t"
-"b\\t3f\\n\\t"
-"2:\\n\\t"
-"%G5\\n\\t"
-"3:\\n\\t";
+ output_asm_insn ("1:", operands);
+ output_asm_insn ("ll.\t%0,%1", operands);
+
+ /* Like the test case atomic-cas-int.C, in loongarch64, O1 and higher, the
+ return value of the val_without_const_folding will not be truncated and
+ will be passed directly to the function compare_exchange_strong.
+ However, the instruction 'bne' does not distinguish between 32-bit and
+ 64-bit operations. so if the upper 32 bits of the register are not
+ extended by the 32nd bit symbol, then the comparison may not be valid
+ here. This will affect the result of the operation. */
+
+ if (TARGET_64BIT && REG_P (operands[2])
+ && GET_MODE (operands[2]) == SImode)
+{
+ output_asm_insn ("addi.w\t%6,%2,0", operands);
+ output_asm_insn ("bne\t%0,%6,2f", operands);
+}
+ else
+output_asm_insn ("bne\t%0,%z2,2f", operands);
+
+ output_asm_insn ("or%i3\t%6,$zero,%3", operands);
+ output_asm_insn ("sc.\t%6,%1", operands);
+ output_asm_insn ("beqz\t%6,1b", operands);
+ output_asm_insn ("b\t3f", operands);
+ output_asm_insn ("2:", operands);
+ output_asm_insn ("%G5", operands);
+ output_asm_insn ("3:", operands);
+
+ return "";
}
- [(set (attr "length") (const_int 28))])
+ [(set (attr "length")
+ (if_then_else
+ (and (match_test "GET_MODE (operands[2]) == SImode")
+(match_test "REG_P (operands[2])"))
+ (const_int 32)
+ (const_int 28)))])
(define_expand "atomic_compare_and_swap"
[(match_operand:SI 0 "register_operand" "") ;; bool output
diff --git a/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
new file mode 100644
index 000..830ce48267a
--- /dev/null
+++ b/gcc/testsuite/g++.target/loongarch/atomic-cas-int.C
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include
+#include
+
+__attribute__ ((noinline)) long
+val_without_const_folding (long val)
+{
+ return val;
+}
+
+int
+main ()
+{
+ int oldval = 0xaa;
+ int newval = 0xbb;
+ std::atomic amo;
+
+ amo.store (oldval);
+
+ long longval = val_without_const_folding (0xff80 + oldval);
+ oldval = static_cast (longval);
+
+ amo.compare_exchange_strong (oldval, newval);
+
+ if (newval != amo.load (std::memory_order_relaxed))
+__builtin_abort ();
+
+ return 0;
+}
+
