[gcc r15-103] Remove live-info global bitmap

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:5176402d6fdbf131d176b5f43ac6449c1bda072b

commit r15-103-g5176402d6fdbf131d176b5f43ac6449c1bda072b
Author: Richard Biener 
Date:   Tue Apr 9 11:28:47 2024 +0200

Remove live-info global bitmap

The following removes the unused tree_live_info_d->global bitmap.

* tree-ssa-live.h (tree_live_info_d::global): Remove.
(partition_is_global): Likewise.
(make_live_on_entry): Do not set bit in global.
* tree-ssa-live.cc (new_tree_live_info): Do not allocate
global bitmap.
(delete_tree_live_info): Do not release it.
(set_var_live_on_entry): Do not set bits in it.

Diff:
---
 gcc/tree-ssa-live.cc | 13 +
 gcc/tree-ssa-live.h  | 13 -
 2 files changed, 1 insertion(+), 25 deletions(-)

diff --git a/gcc/tree-ssa-live.cc b/gcc/tree-ssa-live.cc
index d94e94eb3bc..fa6be2fced3 100644
--- a/gcc/tree-ssa-live.cc
+++ b/gcc/tree-ssa-live.cc
@@ -1015,7 +1015,6 @@ new_tree_live_info (var_map map)
   live->work_stack = XNEWVEC (int, last_basic_block_for_fn (cfun));
   live->stack_top = live->work_stack;
 
-  live->global = BITMAP_ALLOC (NULL);
   return live;
 }
 
@@ -1035,7 +1034,6 @@ delete_tree_live_info (tree_live_info_p live)
   bitmap_obstack_release (&live->liveout_obstack);
   free (live->liveout);
 }
-  BITMAP_FREE (live->global);
   free (live->work_stack);
   free (live);
 }
@@ -1123,7 +1121,6 @@ set_var_live_on_entry (tree ssa_name, tree_live_info_p 
live)
   use_operand_p use;
   basic_block def_bb = NULL;
   imm_use_iterator imm_iter;
-  bool global = false;
 
   p = var_to_partition (live->map, ssa_name);
   if (p == NO_PARTITION)
@@ -1173,16 +1170,8 @@ set_var_live_on_entry (tree ssa_name, tree_live_info_p 
live)
 
   /* If there was a live on entry use, set the bit.  */
   if (add_block)
-{
- global = true;
- bitmap_set_bit (&live->livein[add_block->index], p);
-   }
+   bitmap_set_bit (&live->livein[add_block->index], p);
 }
-
-  /* If SSA_NAME is live on entry to at least one block, fill in all the live
- on entry blocks between the def and all the uses.  */
-  if (global)
-bitmap_set_bit (live->global, p);
 }
 
 
diff --git a/gcc/tree-ssa-live.h b/gcc/tree-ssa-live.h
index e86ce0c1768..ac39091f5d2 100644
--- a/gcc/tree-ssa-live.h
+++ b/gcc/tree-ssa-live.h
@@ -237,9 +237,6 @@ typedef struct tree_live_info_d
   /* Var map this relates to.  */
   var_map map;
 
-  /* Bitmap indicating which partitions are global.  */
-  bitmap global;
-
   /* Bitmaps of live on entry blocks for partition elements.  */
   bitmap_head *livein;
 
@@ -276,15 +273,6 @@ extern bitmap live_vars_at_stmt (vec &, 
live_vars_map *,
 gimple *);
 extern void destroy_live_vars (vec &);
 
-/*  Return TRUE if P is marked as a global in LIVE.  */
-
-inline int
-partition_is_global (tree_live_info_p live, int p)
-{
-  gcc_checking_assert (live->global);
-  return bitmap_bit_p (live->global, p);
-}
-
 
 /* Return the bitmap from LIVE representing the live on entry blocks for
partition P.  */
@@ -329,7 +317,6 @@ inline void
 make_live_on_entry (tree_live_info_p live, basic_block bb , int p)
 {
   bitmap_set_bit (&live->livein[bb->index], p);
-  bitmap_set_bit (live->global, p);
 }

[gcc r15-104] Make graph dumps use graphviz format

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:c59708fba3f98a4cc257741b88216b6caf6b4a87

commit r15-104-gc59708fba3f98a4cc257741b88216b6caf6b4a87
Author: Richard Biener 
Date:   Tue Apr 30 13:01:43 2024 +0200

Make graph dumps use graphviz format

SLP build eventually uses graphds graphs, the following makes its
dump use graphviz format so you can easily visualize it.

* graphds.cc (dump_graph): Dump in graphviz format.

Diff:
---
 gcc/graphds.cc | 17 ++---
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/gcc/graphds.cc b/gcc/graphds.cc
index 17d08966f53..ed5bfeb2808 100644
--- a/gcc/graphds.cc
+++ b/gcc/graphds.cc
@@ -31,22 +31,17 @@ dump_graph (FILE *f, struct graph *g)
   int i;
   struct graph_edge *e;
 
+  fprintf (f, "digraph {\n");
   for (i = 0; i < g->n_vertices; i++)
 {
-  if (!g->vertices[i].pred
- && !g->vertices[i].succ)
-   continue;
-
-  fprintf (f, "%d (%d)\t<-", i, g->vertices[i].component);
+  fprintf (f, "\"%d\" [label=\"%d (%d): %p\"];\n",
+  i, i, g->vertices[i].component, g->vertices[i].data);
   for (e = g->vertices[i].pred; e; e = e->pred_next)
-   fprintf (f, " %d", e->src);
-  fprintf (f, "\n");
-
-  fprintf (f, "\t->");
+   fprintf (f, "\"%d\" -> \"%d\" [label=\"%p\"];\n", e->src, e->dest, 
e->data);
   for (e = g->vertices[i].succ; e; e = e->succ_next)
-   fprintf (f, " %d", e->dest);
-  fprintf (f, "\n");
+   fprintf (f, "\"%d\" -> \"%d\";\n", e->src, e->dest);
 }
+  fprintf (f, "}\n");
 }
 
 /* Creates a new graph with N_VERTICES vertices.  */

[gcc r15-105] c++: Implement C++26 P2573R2 - = delete("should have a reason"); [PR114458]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:2f15787f2e1a3afe2c2ad93d4eb0d3c1f73c8fbd

commit r15-105-g2f15787f2e1a3afe2c2ad93d4eb0d3c1f73c8fbd
Author: Jakub Jelinek 
Date:   Thu May 2 09:34:31 2024 +0200

c++: Implement C++26 P2573R2 - = delete("should have a reason"); [PR114458]

The following patch implements the C++26 P2573R2
= delete("should have a reason"); paper.
I've tried to avoid increasing compile time memory for it when it isn't
used (e.g. by adding a new lang_decl tree member), so the reason is
represented as STRING_CST in DECL_INITIAL (which normally is for
DECL_DELETED_FN error_mark_node) and to differentiate this delete("reason")
initializer from some bogus attempt to initialize a function with "reason"
using the RID_DELETE identifier as TREE_TYPE of the STRING_CST, as nothing
needs to care about the type of the reason.  If preferred it could
be say TREE_LIST with the reason STRING_CST and RID_DELETE identifier or
something similar instead, but that would need more compile time memory when
it is used.

2024-05-02  Jakub Jelinek  

PR c++/114458
gcc/c-family/
* c-cppbuiltin.cc (c_cpp_builtins): Predefine
__cpp_deleted_function=202403L for C++26.
gcc/cp/ChangeLog
* parser.cc (cp_parser_pure_specifier): Implement C++26 P2573R2
- = delete("should have a reason");.  Parse deleted-function-body.
* decl.cc (duplicate_decls): Copy DECL_INITIAL from DECL_DELETED_FN
olddecl to newdecl if it is a STRING_CST.
(cp_finish_decl): Handle deleted init with a reason.
* decl2.cc: Include "escaped_string.h".
(grokfield): Handle deleted init with a reason.
(mark_used): Emit DECL_DELETED_FN reason in the message if any.
* cp-tree.h (DECL_DELETED_FN): Document representation of
= delete("reason") on a DECL.
gcc/testsuite/
* g++.dg/cpp26/feat-cxx26.C (__cpp_deleted_function): Add test.
* g++.dg/cpp26/delete-reason1.C: New test.
* g++.dg/cpp26/delete-reason2.C: New test.
* g++.dg/parse/error65.C (f1): Adjust expected diagnostics.

Diff:
---
 gcc/c-family/c-cppbuiltin.cc|  1 +
 gcc/cp/cp-tree.h|  5 +++-
 gcc/cp/decl.cc  | 13 ++---
 gcc/cp/decl2.cc | 23 +---
 gcc/cp/parser.cc| 21 +++
 gcc/testsuite/g++.dg/cpp26/delete-reason1.C | 41 +
 gcc/testsuite/g++.dg/cpp26/delete-reason2.C | 20 ++
 gcc/testsuite/g++.dg/cpp26/feat-cxx26.C |  6 +
 gcc/testsuite/g++.dg/parse/error65.C|  3 +--
 9 files changed, 124 insertions(+), 9 deletions(-)

diff --git a/gcc/c-family/c-cppbuiltin.cc b/gcc/c-family/c-cppbuiltin.cc
index 0a927b28836..b6f25e4db3c 100644
--- a/gcc/c-family/c-cppbuiltin.cc
+++ b/gcc/c-family/c-cppbuiltin.cc
@@ -1092,6 +1092,7 @@ c_cpp_builtins (cpp_reader *pfile)
  cpp_define (pfile, "__cpp_static_assert=202306L");
  cpp_define (pfile, "__cpp_placeholder_variables=202306L");
  cpp_define (pfile, "__cpp_structured_bindings=202403L");
+ cpp_define (pfile, "__cpp_deleted_function=202403L");
}
   if (flag_concepts)
 {
diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index 5d1bd6ba493..933504b4821 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -4477,7 +4477,10 @@ get_vec_init_expr (tree t)
&& DECL_DECLARED_CONSTEXPR_P (NODE) \
&& DECL_CLASS_SCOPE_P (NODE)))
 
-/* Nonzero if DECL was declared with '= delete'.  */
+/* Nonzero if DECL was declared with '= delete'.
+   = delete("reason") is represented in addition to this flag by DECL_INITIAL
+   being STRING_CST with the reason and TREE_TYPE of the STRING_CST the
+   RID_DELETE IDENTIFIER_NODE.  */
 #define DECL_DELETED_FN(DECL) \
   (LANG_DECL_FN_CHECK (DECL)->min.base.threadprivate_or_deleted_p)
 
diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc
index de0c02a39ee..378311c0f04 100644
--- a/gcc/cp/decl.cc
+++ b/gcc/cp/decl.cc
@@ -2420,6 +2420,10 @@ duplicate_decls (tree newdecl, tree olddecl, bool 
hiding, bool was_hidden)
"previous declaration of %qD", olddecl);
}
  DECL_DELETED_FN (newdecl) |= DECL_DELETED_FN (olddecl);
+ if (DECL_DELETED_FN (olddecl)
+ && DECL_INITIAL (olddecl)
+ && TREE_CODE (DECL_INITIAL (olddecl)) == STRING_CST)
+   DECL_INITIAL (newdecl) = DECL_INITIAL (olddecl);
}
 }
 
@@ -8597,17 +8601,20 @@ cp_finish_decl (tree decl, tree init, bool 
init_const_expr_p,
   if (init && TREE_CODE (decl) == FUNCTION_DECL)
 {
   tree clone;
-  if (init == ridpointers[(int)RID_DELETE])
+  if (init == ridpointers[(int)RID_DELETE]
+ || (TREE_CODE (init) == STRING_CST
+ && TREE_TYPE (init

[gcc r15-106] libgomp: Add gfx90c, 1036 and 1103 declare variant tests

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:5eb25d1561dd22316331feee92164f97ca79d1c3

commit r15-106-g5eb25d1561dd22316331feee92164f97ca79d1c3
Author: Jakub Jelinek 
Date:   Thu May 2 11:56:16 2024 +0200

libgomp: Add gfx90c, 1036 and 1103 declare variant tests

Recently -march=gfx{90c,1036,1103} support has been added, but corresponding
changes weren't done in the testsuite.

The following patch adds that.

Tested on x86_64-linux (with fiji and gfx1103 devices; had to use
OMP_DEFAULT_DEVICE=1 there, fiji doesn't really work due to LLVM dropping
support, but we still list those as offloading devices).

2024-05-02  Jakub Jelinek  

* testsuite/libgomp.c/declare-variant-4.h (gfx90c, gfx1036, 
gfx1103):
New functions.
(f): Add #pragma omp declare variant directives for those.
* testsuite/libgomp.c/declare-variant-4-gfx90c.c: New test.
* testsuite/libgomp.c/declare-variant-4-gfx1036.c: New test.
* testsuite/libgomp.c/declare-variant-4-gfx1103.c: New test.

Diff:
---
 .../libgomp.c/declare-variant-4-gfx1036.c  |  8 
 .../libgomp.c/declare-variant-4-gfx1103.c  |  8 
 .../testsuite/libgomp.c/declare-variant-4-gfx90c.c |  8 
 libgomp/testsuite/libgomp.c/declare-variant-4.h| 24 ++
 4 files changed, 48 insertions(+)

diff --git a/libgomp/testsuite/libgomp.c/declare-variant-4-gfx1036.c 
b/libgomp/testsuite/libgomp.c/declare-variant-4-gfx1036.c
new file mode 100644
index 000..93b8641b3e1
--- /dev/null
+++ b/libgomp/testsuite/libgomp.c/declare-variant-4-gfx1036.c
@@ -0,0 +1,8 @@
+/* { dg-do link { target { offload_target_amdgcn } } } */
+/* { dg-additional-options -foffload=amdgcn-amdhsa } */
+/* { dg-additional-options -foffload=-march=gfx1036 } */
+/* { dg-additional-options "-foffload=-fdump-tree-optimized" } */
+
+#include "declare-variant-4.h"
+
+/* { dg-final { only_for_offload_target amdgcn-amdhsa scan-offload-tree-dump 
"= gfx1036 \\(\\);" "optimized" } } */
diff --git a/libgomp/testsuite/libgomp.c/declare-variant-4-gfx1103.c 
b/libgomp/testsuite/libgomp.c/declare-variant-4-gfx1103.c
new file mode 100644
index 000..6a6dc4fba3f
--- /dev/null
+++ b/libgomp/testsuite/libgomp.c/declare-variant-4-gfx1103.c
@@ -0,0 +1,8 @@
+/* { dg-do link { target { offload_target_amdgcn } } } */
+/* { dg-additional-options -foffload=amdgcn-amdhsa } */
+/* { dg-additional-options -foffload=-march=gfx1103 } */
+/* { dg-additional-options "-foffload=-fdump-tree-optimized" } */
+
+#include "declare-variant-4.h"
+
+/* { dg-final { only_for_offload_target amdgcn-amdhsa scan-offload-tree-dump 
"= gfx1103 \\(\\);" "optimized" } } */
diff --git a/libgomp/testsuite/libgomp.c/declare-variant-4-gfx90c.c 
b/libgomp/testsuite/libgomp.c/declare-variant-4-gfx90c.c
new file mode 100644
index 000..44629a806b4
--- /dev/null
+++ b/libgomp/testsuite/libgomp.c/declare-variant-4-gfx90c.c
@@ -0,0 +1,8 @@
+/* { dg-do link { target { offload_target_amdgcn } } } */
+/* { dg-additional-options -foffload=amdgcn-amdhsa } */
+/* { dg-additional-options -foffload=-march=gfx90c } */
+/* { dg-additional-options "-foffload=-fdump-tree-optimized" } */
+
+#include "declare-variant-4.h"
+
+/* { dg-final { only_for_offload_target amdgcn-amdhsa scan-offload-tree-dump 
"= gfx90c \\(\\);" "optimized" } } */
diff --git a/libgomp/testsuite/libgomp.c/declare-variant-4.h 
b/libgomp/testsuite/libgomp.c/declare-variant-4.h
index d2e9194bf5b..f244d09c655 100644
--- a/libgomp/testsuite/libgomp.c/declare-variant-4.h
+++ b/libgomp/testsuite/libgomp.c/declare-variant-4.h
@@ -35,6 +35,13 @@ gfx90a (void)
   return 0x90a;
 }
 
+__attribute__ ((noipa))
+int
+gfx90c (void)
+{
+  return 0x90c;
+}
+
 __attribute__ ((noipa))
 int
 gfx1030 (void)
@@ -42,6 +49,13 @@ gfx1030 (void)
   return 0x1030;
 }
 
+__attribute__ ((noipa))
+int
+gfx1036 (void)
+{
+  return 0x1036;
+}
+
 __attribute__ ((noipa))
 int
 gfx1100 (void)
@@ -49,6 +63,13 @@ gfx1100 (void)
   return 0x1100;
 }
 
+__attribute__ ((noipa))
+int
+gfx1103 (void)
+{
+  return 0x1103;
+}
+
 #ifdef USE_FIJI_FOR_GFX803
 #pragma omp declare variant(gfx803) match(device = {isa("fiji")})
 #else
@@ -58,8 +79,11 @@ gfx1100 (void)
 #pragma omp declare variant(gfx906) match(device = {isa("gfx906")})
 #pragma omp declare variant(gfx908) match(device = {isa("gfx908")})
 #pragma omp declare variant(gfx90a) match(device = {isa("gfx90a")})
+#pragma omp declare variant(gfx90c) match(device = {isa("gfx90c")})
 #pragma omp declare variant(gfx1030) match(device = {isa("gfx1030")})
+#pragma omp declare variant(gfx1036) match(device = {isa("gfx1036")})
 #pragma omp declare variant(gfx1100) match(device = {isa("gfx1100")})
+#pragma omp declare variant(gfx1103) match(device = {isa("gfx1103")})
 __attribute__ ((noipa))
 int
 f (void)

[gcc r15-107] Driver: Add new -truncate option

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:985b5a90f70c7376c771317c6c8c3bc5ef05e227

commit r15-107-g985b5a90f70c7376c771317c6c8c3bc5ef05e227
Author: Peter Damianov 
Date:   Sun Apr 28 16:16:11 2024 -0700

Driver: Add new -truncate option

This commit adds a new option to the driver that truncates one file after
linking.

Tested likeso:

$ gcc hello.c -c
$ du -h hello.o
4.0K  hello.o
$ gcc hello.o -truncate hello.o
$ ./a.out
Hello world
$ du -h hello.o
$ 0   hello.o

$ gcc hello.o -truncate
gcc: error: missing filename after '-truncate'

The motivation for adding this is PR110710. It is used by lto-wrapper to
truncate files in a shell-independent manner.

Signed-off-by: Peter Damianov 

PR lto/110710
* common.opt (truncate): New internal option.
* gcc.cc (totruncate_file): New global.
(driver_handle_option): Handle -truncate .
(driver::final_actions): Truncate the file indicated.

Diff:
---
 gcc/common.opt |  6 ++
 gcc/gcc.cc | 14 ++
 2 files changed, 20 insertions(+)

diff --git a/gcc/common.opt b/gcc/common.opt
index ad348844775..40cab3cb36a 100644
--- a/gcc/common.opt
+++ b/gcc/common.opt
@@ -422,6 +422,12 @@ Display target specific command line options (including 
assembler and linker opt
 -time
 Driver Alias(time)
 
+;; Truncate the file specified after linking.
+;; This option is used by lto-wrapper to reduce the peak disk-usage when
+;; linking with many .LTRANS units.
+truncate
+Driver Separate Undocumented MissingArgError(missing filename after %qs)
+
 -verbose
 Driver Alias(v)
 
diff --git a/gcc/gcc.cc b/gcc/gcc.cc
index 728332b8153..830a4700a87 100644
--- a/gcc/gcc.cc
+++ b/gcc/gcc.cc
@@ -2138,6 +2138,10 @@ static int have_E = 0;
 /* Pointer to output file name passed in with -o. */
 static const char *output_file = 0;
 
+/* Pointer to input file name passed in with -truncate.
+   This file should be truncated after linking. */
+static const char *totruncate_file = 0;
+
 /* This is the list of suffixes and codes (%g/%u/%U/%j) and the associated
temp file.  If the HOST_BIT_BUCKET is used for %j, no entry is made for
it here.  */
@@ -4538,6 +4542,11 @@ driver_handle_option (struct gcc_options *opts,
   do_save = false;
   break;
 
+case OPT_truncate:
+  totruncate_file = arg;
+  do_save = false;
+  break;
+
 case OPT:
   /* "-###"
 This is similar to -v except that there is no execution
@@ -9286,6 +9295,11 @@ driver::final_actions () const
 delete_failure_queue ();
   delete_temp_files ();
 
+  if (totruncate_file != NULL && !seen_error ())
+/* Truncate file specified by -truncate.
+   Used by lto-wrapper to reduce temporary disk-space usage. */
+truncate(totruncate_file, 0);
+
   if (print_help_list)
 {
   printf (("\nFor bug reporting instructions, please see:\n"));

[gcc r15-108] lto-wrapper: Truncate files using -truncate driver option [PR110710]

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:a704554d2e798e2e1b74b9fea4baf3477180bd9d

commit r15-108-ga704554d2e798e2e1b74b9fea4baf3477180bd9d
Author: Peter Damianov 
Date:   Sun Apr 28 16:16:12 2024 -0700

lto-wrapper: Truncate files using -truncate driver option [PR110710]

This commit changes the Makefiles generated by lto-wrapper to no longer use
the "mv" and "touch" shell commands. These don't exist on Windows, so when 
the
Makefile attempts to call them, it results in errors like:
The system cannot find the file specified.

This problem only manifested when calling gcc from cmd.exe, and having no
sh.exe present on the PATH. The Windows port of GNU Make searches the PATH 
for
an sh.exe, and uses it if present.

I have tested this in environments with and without sh.exe on the PATH and
confirmed it works as expected.

Signed-off-by: Peter Damianov 

PR lto/110710
* lto-wrapper.cc (run_gcc): Instead of truncating a processed
ltrans input from the Makefile use the new -truncate option
to accomplish the same.

Diff:
---
 gcc/lto-wrapper.cc | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/gcc/lto-wrapper.cc b/gcc/lto-wrapper.cc
index 02579951569..cfded757f26 100644
--- a/gcc/lto-wrapper.cc
+++ b/gcc/lto-wrapper.cc
@@ -2023,14 +2023,12 @@ cont:
  fprintf (mstream, "%s:\n\t@%s ", output_name, new_argv[0]);
  for (j = 1; new_argv[j] != NULL; ++j)
fprintf (mstream, " '%s'", new_argv[j]);
- fprintf (mstream, "\n");
  /* If we are not preserving the ltrans input files then
 truncate them as soon as we have processed it.  This
 reduces temporary disk-space usage.  */
  if (! save_temps)
-   fprintf (mstream, "\t@-touch -r \"%s\" \"%s.tem\" > /dev/null "
-"2>&1 && mv \"%s.tem\" \"%s\"\n",
-input_name, input_name, input_name, input_name); 
+   fprintf (mstream, " -truncate '%s'", input_name);
+ fprintf (mstream, "\n");
}
  else
{

[gcc r11-11411] libstdc++: Add missing std::tuple constructor [PR114147]

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:0ecb0967b4f7e68027492ac03e5dc03b5bcfdcf7

commit r11-11411-g0ecb0967b4f7e68027492ac03e5dc03b5bcfdcf7
Author: Jonathan Wakely 
Date:   Fri Mar 1 11:16:58 2024 +

libstdc++: Add missing std::tuple constructor [PR114147]

I caused a regression with commit r10-908 by adding a constraint to the
non-explicit allocator-extended default constructor, but seemingly
forgot to add an explicit overload with the corresponding constraint.

libstdc++-v3/ChangeLog:

PR libstdc++/114147
* include/std/tuple (tuple::tuple(allocator_arg_t, const Alloc&)):
Add missing overload of allocator-extended default constructor.
(tuple::tuple(allocator_arg_t, const Alloc&)): Likewise.
* testsuite/20_util/tuple/cons/114147.cc: New test.

(cherry picked from commit 0a545ac7000501844670add0b3560ebdbcb123c6)

Diff:
---
 libstdc++-v3/include/std/tuple  | 14 ++
 libstdc++-v3/testsuite/20_util/tuple/cons/114147.cc | 15 +++
 2 files changed, 29 insertions(+)

diff --git a/libstdc++-v3/include/std/tuple b/libstdc++-v3/include/std/tuple
index 63bd68fbe43..b02b0bfbd59 100644
--- a/libstdc++-v3/include/std/tuple
+++ b/libstdc++-v3/include/std/tuple
@@ -801,6 +801,13 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
tuple(allocator_arg_t __tag, const _Alloc& __a)
: _Inherited(__tag, __a) { }
 
+  template::value> = false>
+   _GLIBCXX20_CONSTEXPR
+   explicit
+   tuple(allocator_arg_t __tag, const _Alloc& __a)
+   : _Inherited(__tag, __a) { }
+
   template= 1),
   _ImplicitCtor<_NotEmpty, const _Elements&...> = true>
_GLIBCXX20_CONSTEXPR
@@ -1155,6 +1162,13 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
tuple(allocator_arg_t __tag, const _Alloc& __a)
: _Inherited(__tag, __a) { }
 
+  template::value, _T1, _T2> = false>
+   _GLIBCXX20_CONSTEXPR
+   explicit
+   tuple(allocator_arg_t __tag, const _Alloc& __a)
+   : _Inherited(__tag, __a) { }
+
   template = true>
_GLIBCXX20_CONSTEXPR
diff --git a/libstdc++-v3/testsuite/20_util/tuple/cons/114147.cc 
b/libstdc++-v3/testsuite/20_util/tuple/cons/114147.cc
new file mode 100644
index 000..916e7204964
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/tuple/cons/114147.cc
@@ -0,0 +1,15 @@
+// { dg-do compile { target c++11 } }
+
+// PR libstdc++/114147
+// tuple allocator-extended ctor requires non-explicit default ctor
+
+#include 
+#include 
+
+struct X { explicit X(); };
+
+std::allocator a;
+std::tuple t0(std::allocator_arg, a);
+std::tuple t1(std::allocator_arg, a);
+std::tuple t2(std::allocator_arg, a);
+std::tuple t3(std::allocator_arg, a);

[gcc r15-109] fix single argument static_assert

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:4bb21b5cd7a805b78ea85f46cbb82438ca757a56

commit r15-109-g4bb21b5cd7a805b78ea85f46cbb82438ca757a56
Author: Marc Poulhiès 
Date:   Thu May 2 12:23:36 2024 +0200

fix single argument static_assert

Single argument static_assert is C++17 only.

gcc/ChangeLog:

* value-range.h: fix static_assert to use 2 arguments.

Diff:
---
 gcc/value-range.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/value-range.h b/gcc/value-range.h
index f1c638f8cd0..934eec9e386 100644
--- a/gcc/value-range.h
+++ b/gcc/value-range.h
@@ -741,7 +741,7 @@ private:
 
   vrange *m_vrange;
   // The buffer must be at least the size of the largest range.
-  static_assert (sizeof (int_range_max) > sizeof (frange));
+  static_assert (sizeof (int_range_max) > sizeof (frange), "");
   char m_buffer[sizeof (int_range_max)];
 };

[gcc r15-110] PR modula2/113836 gm2 does not dump gimple or quadruples to a file

[Gaius Mulley via Gcc-cvs]

https://gcc.gnu.org/g:43dc4302b4181535d24e83759514b774ae4dbfcc

commit r15-110-g43dc4302b4181535d24e83759514b774ae4dbfcc
Author: Gaius Mulley 
Date:   Thu May 2 13:16:07 2024 +0100

PR modula2/113836 gm2 does not dump gimple or quadruples to a file

This patch completes the implementation of dumping the intermediate forms
to file.  It implements the filtering on symbol rules.  Filtering can be
performed through the full text name (given to the GCC tree) or qualified
modula-2 symbol or filename:qualident.

gcc/ChangeLog:

PR modula2/113836
* doc/gm2.texi (Compiler options): Add -fm2-debug-trace=,
-fm2-dump, -fm2-dump-decl=, -fm2-dump-gimple=, -fm2-dump-quad=
and -fm2-dump-filter=.

gcc/m2/ChangeLog:

PR modula2/113836
* gm2-compiler/M2AsmUtil.def: Remove export qualified and
unused import.
* gm2-compiler/M2LangDump.mod (AddRuleTextDump): New procedure.
(AddRuleScopeQualidentDump): Add warning check against unmatched
rule.
(GenQualidentSymString): New procedure function.
(IdentQualidentMatch): New procedure function.
(IsRuleFilenameMatch): New procedure function.
(CheckRuleMatch): New procedure function.
(AddRuleFilenameDump): New procedure function.
* gm2-gcc/m2misc.cc (m2misc_warning_m2_dump_filter): New function.
* gm2-gcc/m2misc.def (warning_m2_dump_filter): New procedure.
* gm2-gcc/m2misc.h (m2misc_warning_m2_dump_filter): New prototype.
* gm2-gcc/m2pp.cc (VERBOSE_TYPE_DESC): New define.
(m2pp_identifier): Define out verbose type info.
(m2pp_constructor): Define out verbose type info.
(m2pp_assignment): Define out verbose type info.
* gm2-lang.cc (ENABLE_M2DUMP_ALL): Remove.
* lang.opt (fm2-dump): Add.
(fm2-dump-decl=): Add.
(fm2-dump-gimple=): Add.
(fm2-dump-quad=): Add.
(fm2-dump-filter=): Add.

Signed-off-by: Gaius Mulley 

Diff:
---
 gcc/doc/gm2.texi   |  39 --
 gcc/m2/gm2-compiler/M2AsmUtil.def  |   2 -
 gcc/m2/gm2-compiler/M2LangDump.mod | 150 +++--
 gcc/m2/gm2-gcc/m2misc.cc   |  10 +++
 gcc/m2/gm2-gcc/m2misc.def  |   3 +-
 gcc/m2/gm2-gcc/m2misc.h|   1 +
 gcc/m2/gm2-gcc/m2pp.cc |  21 +-
 gcc/m2/gm2-lang.cc |   4 -
 gcc/m2/lang.opt|  20 +
 9 files changed, 225 insertions(+), 25 deletions(-)

diff --git a/gcc/doc/gm2.texi b/gcc/doc/gm2.texi
index 19b864573c1..b38d6a15de0 100644
--- a/gcc/doc/gm2.texi
+++ b/gcc/doc/gm2.texi
@@ -466,10 +466,39 @@ this option forces the use of the static version.
 @c Modula-2 Joined
 @c set all location values to a specific value (internal switch)
 
-@c fm2-debug-trace=
-@c Modula-2 Joined
-@c turn on trace debugging using a comma separated list:
-@c line,token,quad,all.
+@item -fm2-debug-trace=
+turn on trace debugging using a comma separated list:
+@samp{line,token,quad,all}.  This is an internal command line option.
+
+@item -fm2-dump=
+enable dumping of modula-2 internal representation of data structures
+using a comma separated list.  The list can contain:
+@samp{quad,gimple,decl,all}.
+
+@item -fm2-dump-decl=@file{filestem}
+dump the modula-2 representation of a symbol to the @file{filestem}
+specified.  This option only takes effect if the
+@samp{-fm2-dump-filter} is specified.
+
+@item -fm2-dump-gimple=@file{filestem}
+dump modula-2 gimple representation to the @file{filestem} specified.
+
+@item -fm2-dump-quad=@file{filestem}
+dump quadruple representation to the @file{filestem} specified.
+
+@item -fm2-dump-filter=@samp{rules}
+filter the language dumps @samp{-fdump-lang-decl},
+@samp{-fdump-lang-gimple} and@samp{-fdump-lang-quad}
+on @samp{rules}.  @samp{rules} must be a comma
+separated list which can take three forms: the full decl textual name
+of a procedure, @samp{[libname.]module.ident} or
+@samp{[filename:]module.ident}.  This is an internal command line
+option.  Currently it only filters on procedure names and regexp
+matching is not implemented.  Three examples of its use following
+the previous forms could be:
+@code{-fm2-dump-filter=_M2_hello_init},
+@code{-fm2-dump-filter=m2pim.StrIO.WriteString} and
+@code{-fm2-dump-filter=StrLib.mod:StrIO.WriteString}.
 
 @item -fm2-g
 improve the debugging experience for new programmers at the expense
@@ -487,7 +516,7 @@ specify the module mangled prefix name for all modules in 
the
 following include paths.
 
 @item -fm2-pathnameI
-for internal use only: used by the driver to copy the user facing -I
+for internal use only: used by the driver to copy the user facing @samp{-I}
 option.
 
 @item -fm2-plugin
diff --git a/gcc/m2/gm2-compiler/M2AsmUtil.def 
b/gcc/m2/gm2-compiler/M2AsmUtil.def

[gcc r15-111] Objective-C, NeXT, v2: Correct a regression in code-gen.

[Iain D Sandoe via Gcc-cvs]

https://gcc.gnu.org/g:9b5c0be59d0f94df0517820f00b4520b5abddd8c

commit r15-111-g9b5c0be59d0f94df0517820f00b4520b5abddd8c
Author: Iain Sandoe 
Date:   Tue Apr 30 15:11:56 2024 +0100

Objective-C, NeXT, v2: Correct a regression in code-gen.

There have been several changes in the ABI of Objective-C which
depend on the OS version targetted.  In this case Protocols and
LabelProtocols should be made weak/hidden/extern from macOS 10.7
however there was a mistake in the code causing this to occur
from macOS 10.6.  Fixed thus.

gcc/objc/ChangeLog:

* objc-next-runtime-abi-02.cc (WEAK_PROTOCOLS_AFTER): New.
(next_runtime_abi_02_protocol_decl): Use WEAK_PROTOCOLS_AFTER
to determine this ABI change.
(build_v2_protocol_list_address_table): Likewise.

Signed-off-by: Iain Sandoe 

Diff:
---
 gcc/objc/objc-next-runtime-abi-02.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/gcc/objc/objc-next-runtime-abi-02.cc 
b/gcc/objc/objc-next-runtime-abi-02.cc
index cdf559b9bea..248ef641281 100644
--- a/gcc/objc/objc-next-runtime-abi-02.cc
+++ b/gcc/objc/objc-next-runtime-abi-02.cc
@@ -72,6 +72,7 @@ along with GCC; see the file COPYING3.  If not see
 #define TAG_MSGSENDSUPER_STRET "objc_msgSendSuper2_stret"
 
 #define USE_FIXUP_BEFORE   100600
+#define WEAK_PROTOCOLS_AFTER   100700
 #define TAG_FIXUP  "_fixup"
 
 
@@ -1025,7 +1026,7 @@ next_runtime_abi_02_protocol_decl (tree p)
   /* static struct _objc_protocol _OBJC_Protocol_; */
   snprintf (buf, BUFSIZE, "_OBJC_Protocol_%s",
IDENTIFIER_POINTER (PROTOCOL_NAME (p)));
-  if (flag_next_runtime >= USE_FIXUP_BEFORE)
+  if (flag_next_runtime >= WEAK_PROTOCOLS_AFTER)
 {
   decl = create_hidden_decl (objc_v2_protocol_template, buf);
   DECL_WEAK (decl) = true;
@@ -2315,7 +2316,7 @@ build_v2_protocol_list_address_table (void)
   gcc_assert (ref->id && TREE_CODE (ref->id) == PROTOCOL_INTERFACE_TYPE);
   snprintf (buf, BUFSIZE, "_OBJC_LabelProtocol_%s",
IDENTIFIER_POINTER (PROTOCOL_NAME (ref->id)));
-  if (flag_next_runtime >= USE_FIXUP_BEFORE)
+  if (flag_next_runtime >= WEAK_PROTOCOLS_AFTER)
{
  decl = create_hidden_decl (objc_protocol_type, buf, /*is def=*/true);
  DECL_WEAK (decl) = true;

[gcc r12-10408] rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:135402288a1b1b082d2e71ff2ee5c63b7dafed9f

commit r12-10408-g135402288a1b1b082d2e71ff2ee5c63b7dafed9f
Author: Peter Bergner 
Date:   Tue Apr 9 15:24:39 2024 -0500

rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR 
[PR101865]

This is a cleanup patch in preparation to fixing the real bug in PR101865.
TARGET_DIRECT_MOVE is redundant with TARGET_P8_VECTOR, so alias it to that.
Also replace all usages of OPTION_MASK_DIRECT_MOVE with 
OPTION_MASK_P8_VECTOR
and delete the now dead mask.

2024-04-09  Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000.h (TARGET_DIRECT_MOVE): Define.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete 
redundant
OPTION_MASK_DIRECT_MOVE usage.  Delete TARGET_DIRECT_MOVE dead code.
(rs6000_opt_masks): Neuter the "direct-move" option.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete useless
comment.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
OPTION_MASK_DIRECT_MOVE.
(OTHER_P8_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (mdirect-move): Remove Mask and Var.

(cherry picked from commit 7924e352523b37155ed9d76dc426701de9d11a22)

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 14 +-
 gcc/config/rs6000/rs6000-cpus.def |  3 ---
 gcc/config/rs6000/rs6000.cc   | 14 +++---
 gcc/config/rs6000/rs6000.h|  2 ++
 gcc/config/rs6000/rs6000.opt  |  2 +-
 5 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index fa0c93e1841..cc848478a20 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -432,19 +432,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned on in the following condition:
- 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not
-explicitly disabled.
-Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
-have been turned on explicitly.
- Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned off in any of the following conditions:
- 1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
-   disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
-   enabled.
- 2. TARGET_VSX is off.  */
-  if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
+  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 963947f6939..7dc8679ac9d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -49,7 +49,6 @@
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_QUAD_MEMORY  \
 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
@@ -94,7 +93,6 @@
 /* Flags that need to be turned off if -mno-power8-vector.  */
 #define OTHER_P8_VECTOR_MASKS  (OTHER_P9_VECTOR_MASKS  \
 | OPTION_MASK_P9_VECTOR\
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_CRYPTO)
 
 /* Flags that need to be turned off if -mno-vsx.  */
@@ -125,7 +123,6 @@
 | OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_DLMZB\
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 70406c21c1c..34c533dba31 100644
--- a/gcc/config/rs6000/rs6000.cc
+++

[gcc r12-10409] rs6000: Add OPTION_MASK_POWER8 [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:04ca18ff5e2592ac88a5b72248332f519a17184b

commit r12-10409-g04ca18ff5e2592ac88a5b72248332f519a17184b
Author: Will Schmidt 
Date:   Fri Apr 12 14:55:16 2024 -0500

rs6000: Add OPTION_MASK_POWER8 [PR101865]

The bug in PR101865 is the _ARCH_PWR8 predefine macro is conditional upon
TARGET_DIRECT_MOVE, which can be false for some -mcpu=power8 compiles if the
-mno-altivec or -mno-vsx options are used.  The solution here is to create
a new OPTION_MASK_POWER8 mask that is true for -mcpu=power8, regardless of
Altivec or VSX enablement.

Unfortunately, the only way to create an OPTION_MASK_* mask is to create
a new option, which we have done here, but marked it as WarnRemoved since
we do not want users using it.  For stage1, we will look into how we can
create ISA mask flags for use in the compiler without the need for explicit
options.

2024-04-12  Will Schmidt  
Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER8.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use
OPTION_MASK_POWER8.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add 
OPTION_MASK_POWER8.
(ISA_2_7_MASKS_SERVER): Likewise.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Update
comment.  Use OPTION_MASK_POWER8 and TARGET_POWER8.
* config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8.
* config/rs6000/rs6000.md (define_attr "isa"): Add p8.
(define_attr "enabled"): Handle it.
(define_insn "prefetch"): Use TARGET_POWER8.
* config/rs6000/rs6000.opt (mpower8-internal): New.

gcc/testsuite/
PR target/101865
* gcc.target/powerpc/predefine-p7-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec.c: New test.
* gcc.target/powerpc/predefine-p8-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-pragma-vsx.c: New test.
* gcc.target/powerpc/predefine-p9-novsx.c: New test.

(cherry picked from commit aa57af93ba22865be747f926e4e5f219e7f8758a)

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc|   2 +-
 gcc/config/rs6000/rs6000-c.cc  |   2 +-
 gcc/config/rs6000/rs6000-cpus.def  |   2 +
 gcc/config/rs6000/rs6000.cc|   7 +-
 gcc/config/rs6000/rs6000.h |   2 +-
 gcc/config/rs6000/rs6000.md|   8 +-
 gcc/config/rs6000/rs6000.opt   |   4 +
 .../gcc.target/powerpc/predefine-p7-novsx.c|  22 +
 .../powerpc/predefine-p8-noaltivec-novsx.c |  26 ++
 .../gcc.target/powerpc/predefine-p8-noaltivec.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-novsx.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-pragma-vsx.c   | 101 +
 .../gcc.target/powerpc/predefine-p9-novsx.c|  26 ++
 13 files changed, 245 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 39a07a27c86..ff5830532d2 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -168,7 +168,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P7_64:
   return TARGET_POPCNTD && TARGET_POWERPC64;
 case ENB_P8:
-  return TARGET_DIRECT_MOVE;
+  return TARGET_POWER8;
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index cc848478a20..77d8de70e7a 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -432,7 +432,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
+  if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 7dc8679ac9d..a052914b246 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,6 +47,7 @@
fusion here, instead set it in rs6000.cc if we are tuning for a power8
system.  */
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
+| OPTION_MASK_POWER8   \
 | OPTION_MASK_P8_VECTOR

[gcc r15-112] Improve SLP dump and graph

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:bf33fe90e75c2c463d77f83d9a44dc61abe087f5

commit r15-112-gbf33fe90e75c2c463d77f83d9a44dc61abe087f5
Author: Richard Biener 
Date:   Wed Mar 27 10:53:11 2024 +0100

Improve SLP dump and graph

The following notes which lanes are considered live and adds an overload
to produce a graphviz graph for multiple entries into an SLP graph.

* tree-vect-slp.cc (vect_print_slp_tree): Mark live lanes.
(dot_slp_tree): New overload for multiple entries.

Diff:
---
 gcc/tree-vect-slp.cc | 21 -
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 133606fa6f3..3eb326d20b5 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -2759,7 +2759,9 @@ vect_print_slp_tree (dump_flags_t dump_kind, 
dump_location_t loc,
 }
   if (SLP_TREE_SCALAR_STMTS (node).exists ())
 FOR_EACH_VEC_ELT (SLP_TREE_SCALAR_STMTS (node), i, stmt_info)
-  dump_printf_loc (metadata, user_loc, "\tstmt %u %G", i, stmt_info->stmt);
+  dump_printf_loc (metadata, user_loc, "\t%sstmt %u %G",
+  STMT_VINFO_LIVE_P (stmt_info) ? "[l] " : "",
+  i, stmt_info->stmt);
   else
 {
   dump_printf_loc (metadata, user_loc, "\t{ ");
@@ -2840,6 +2842,23 @@ dot_slp_tree (const char *fname, slp_tree node)
   fclose (f);
 }
 
+DEBUG_FUNCTION void
+dot_slp_tree (const char *fname, const vec &slp_instances)
+{
+  FILE *f = fopen (fname, "w");
+  fprintf (f, "digraph {\n");
+  fflush (f);
+{
+  debug_dump_context ctx (f);
+  hash_set visited;
+  for (auto inst : slp_instances)
+   dot_slp_tree (f, SLP_INSTANCE_TREE (inst), visited);
+}
+  fflush (f);
+  fprintf (f, "}\n");
+  fclose (f);
+}
+
 /* Dump a slp tree NODE using flags specified in DUMP_KIND.  */
 
 static void

[gcc r15-113] modula2: Regenerate libgm2 Makefile.ins using correct include order

[Gaius Mulley via Gcc-cvs]

https://gcc.gnu.org/g:67e66c973ce31e375caa9611b2db290fbfc1904d

commit r15-113-g67e66c973ce31e375caa9611b2db290fbfc1904d
Author: Gaius Mulley 
Date:   Thu May 2 14:38:51 2024 +0100

modula2: Regenerate libgm2 Makefile.ins using correct include order

Regenerated libgm2/Makefile.in (and subdir Makefile.in) using
aclocal -I .. -I ../config (or autoreconf).

libgm2/ChangeLog:

* Makefile.in: Regenerate.
* libm2cor/Makefile.in: Ditto.
* libm2iso/Makefile.in: Ditto.
* libm2log/Makefile.in: Ditto.
* libm2min/Makefile.in: Ditto.
* libm2pim/Makefile.in: Ditto.
* aclocal.m4: Ditto.

Signed-off-by: Gaius Mulley 

Diff:
---
 libgm2/Makefile.in  | 10 +-
 libgm2/aclocal.m4   | 10 +-
 libgm2/libm2cor/Makefile.in | 10 +-
 libgm2/libm2iso/Makefile.in | 10 +-
 libgm2/libm2log/Makefile.in | 10 +-
 libgm2/libm2min/Makefile.in | 10 +-
 libgm2/libm2pim/Makefile.in | 10 +-
 7 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/libgm2/Makefile.in b/libgm2/Makefile.in
index f259df7842c..9cd79824a53 100644
--- a/libgm2/Makefile.in
+++ b/libgm2/Makefile.in
@@ -90,15 +90,15 @@ host_triplet = @host@
 target_triplet = @target@
 subdir = .
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/../libtool.m4 \
-   $(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \
-   $(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \
-   $(top_srcdir)/../config/acx.m4 \
+am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/../config/lead-dot.m4 \
$(top_srcdir)/../config/multi.m4 \
$(top_srcdir)/../config/no-executables.m4 \
-   $(top_srcdir)/../config/override.m4 $(top_srcdir)/acinclude.m4 \
+   $(top_srcdir)/../config/override.m4 \
+   $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
+   $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
+   $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/acinclude.m4 \
$(top_srcdir)/../config/gc++filt.m4 \
$(top_srcdir)/../config/tls.m4 $(top_srcdir)/../config/gthr.m4 \
$(top_srcdir)/../config/cet.m4 $(top_srcdir)/configure.ac
diff --git a/libgm2/aclocal.m4 b/libgm2/aclocal.m4
index bee67b05dee..19cfb0d1eb2 100644
--- a/libgm2/aclocal.m4
+++ b/libgm2/aclocal.m4
@@ -1187,15 +1187,15 @@ AC_SUBST([am__tar])
 AC_SUBST([am__untar])
 ]) # _AM_PROG_TAR
 
-m4_include([../libtool.m4])
-m4_include([../ltoptions.m4])
-m4_include([../ltsugar.m4])
-m4_include([../ltversion.m4])
-m4_include([../lt~obsolete.m4])
 m4_include([../config/acx.m4])
 m4_include([../config/depstand.m4])
 m4_include([../config/lead-dot.m4])
 m4_include([../config/multi.m4])
 m4_include([../config/no-executables.m4])
 m4_include([../config/override.m4])
+m4_include([../libtool.m4])
+m4_include([../ltoptions.m4])
+m4_include([../ltsugar.m4])
+m4_include([../ltversion.m4])
+m4_include([../lt~obsolete.m4])
 m4_include([acinclude.m4])
diff --git a/libgm2/libm2cor/Makefile.in b/libgm2/libm2cor/Makefile.in
index 63299388dd8..f9952cff71a 100644
--- a/libgm2/libm2cor/Makefile.in
+++ b/libgm2/libm2cor/Makefile.in
@@ -108,15 +108,15 @@ target_triplet = @target@
 @BUILD_CORLIB_TRUE@@ENABLE_DARWIN_AT_RPATH_TRUE@am__append_1 = 
-nodefaultrpaths -Wl,-rpath,@loader_path/
 subdir = libm2cor
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/../libtool.m4 \
-   $(top_srcdir)/../ltoptions.m4 $(top_srcdir)/../ltsugar.m4 \
-   $(top_srcdir)/../ltversion.m4 $(top_srcdir)/../lt~obsolete.m4 \
-   $(top_srcdir)/../config/acx.m4 \
+am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/../config/lead-dot.m4 \
$(top_srcdir)/../config/multi.m4 \
$(top_srcdir)/../config/no-executables.m4 \
-   $(top_srcdir)/../config/override.m4 $(top_srcdir)/acinclude.m4 \
+   $(top_srcdir)/../config/override.m4 \
+   $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
+   $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
+   $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/acinclude.m4 \
$(top_srcdir)/../config/gc++filt.m4 \
$(top_srcdir)/../config/tls.m4 $(top_srcdir)/../config/gthr.m4 \
$(top_srcdir)/../config/cet.m4 $(top_srcdir)/configure.ac
diff --git a/libgm2/libm2iso/Makefile.in b/libgm2/libm2iso/Makefile.in
index 964c6da8527..370837f15b8 100644
--- a/libgm2/libm2iso/Makefile.in
+++ b/libgm2/libm2iso/Makefile.in
@@ -108,15 +108,15 @@ target_triplet = @target@
 @BUILD_ISOLIB_TRUE@@ENABLE_DARWIN_AT_RPATH_TRUE@am__append_1 = 
-nodefaultrpaths -Wl,-rpath,@loader_path/
 subdir = libm2iso
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/../libtool.m4 \
-   $(top_srcdir)/../ltoptions.m4 $(top_s

[gcc r15-114] c++: Clear is_unbraced_* when parsing declaration_seq_opt [PR114917]

[Nathaniel Shead via Gcc-cvs]

https://gcc.gnu.org/g:7317d62a1200dbd3685015e5d6b811497a27fe5f

commit r15-114-g7317d62a1200dbd3685015e5d6b811497a27fe5f
Author: Nathaniel Shead 
Date:   Thu May 2 12:55:24 2024 +1000

c++: Clear is_unbraced_* when parsing declaration_seq_opt [PR114917]

Currently we incorrectly retain "in_unbraced_linkage_specification_p"
and "in_unbraced_export_declaration_p" when parsing a (braced)
declaration-seq.  This patch ensures that we clear these flags before
parsing the toplevel declarations.

Strictly speaking we don't need to save and restore the flags around the
parsing because there's currently no way to provide new declarations
within the unbraced context after the closing brace, but this patch does
it anyway in case this ever changes and for consistency with other
places that these flags are adjusted.

PR c++/114917

gcc/cp/ChangeLog:

* parser.cc (cp_parser_declaration_seq_opt): Clear
parser->in_unbraced_* flags when parsing toplevel declarations.

gcc/testsuite/ChangeLog:

* g++.dg/modules/export-5_a.C: New test.
* g++.dg/modules/export-5_b.C: New test.
* g++.dg/parse/linkage4.C: New test.

Signed-off-by: Nathaniel Shead 

Diff:
---
 gcc/cp/parser.cc  | 15 +++
 gcc/testsuite/g++.dg/modules/export-5_a.C | 17 +
 gcc/testsuite/g++.dg/modules/export-5_b.C | 13 +
 gcc/testsuite/g++.dg/parse/linkage4.C | 11 +++
 4 files changed, 56 insertions(+)

diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index 7c3cfcfcf4b..66ce161252c 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -15341,6 +15341,16 @@ cp_parser_module_export (cp_parser *parser)
 static void
 cp_parser_declaration_seq_opt (cp_parser* parser)
 {
+  bool saved_in_unbraced_linkage_specification_p
+= parser->in_unbraced_linkage_specification_p;
+  bool saved_in_unbraced_export_declaration_p
+= parser->in_unbraced_export_declaration_p;
+
+  /* We're not in an unbraced linkage-specification
+ or export-declaration anymore.  */
+  parser->in_unbraced_linkage_specification_p = false;
+  parser->in_unbraced_export_declaration_p = false;
+
   while (true)
 {
   cp_token *token = cp_lexer_peek_token (parser->lexer);
@@ -15351,6 +15361,11 @@ cp_parser_declaration_seq_opt (cp_parser* parser)
   else
cp_parser_toplevel_declaration (parser);
 }
+
+  parser->in_unbraced_linkage_specification_p
+= saved_in_unbraced_linkage_specification_p;
+  parser->in_unbraced_export_declaration_p
+= saved_in_unbraced_export_declaration_p;
 }
 
 /* Parse a declaration.  The distinction between name-declaration
diff --git a/gcc/testsuite/g++.dg/modules/export-5_a.C 
b/gcc/testsuite/g++.dg/modules/export-5_a.C
new file mode 100644
index 000..a325591ca8e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/export-5_a.C
@@ -0,0 +1,17 @@
+// PR c++/114917
+// { dg-additional-options "-fmodules-ts" }
+// { dg-module-cmi M }
+
+export module M;
+
+export namespace ns {
+  template  struct S {};
+  template  struct S { using a = int; };
+  template <> struct S { using b = int; };
+  template struct S;
+};
+
+export extern "C++" namespace ns {
+  template  void foo() {}
+  template <> void foo() {}
+}
diff --git a/gcc/testsuite/g++.dg/modules/export-5_b.C 
b/gcc/testsuite/g++.dg/modules/export-5_b.C
new file mode 100644
index 000..cb10e37c7fc
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/export-5_b.C
@@ -0,0 +1,13 @@
+// PR c++/114917
+// { dg-additional-options "-fmodules-ts" }
+
+import M;
+
+int main() {
+  ns::S::a x{};
+  ns::S::b y{};
+  ns::S z{};
+
+  ns::foo();
+  ns::foo();
+}
diff --git a/gcc/testsuite/g++.dg/parse/linkage4.C 
b/gcc/testsuite/g++.dg/parse/linkage4.C
new file mode 100644
index 000..10fcc77e9d5
--- /dev/null
+++ b/gcc/testsuite/g++.dg/parse/linkage4.C
@@ -0,0 +1,11 @@
+// PR c++/114917
+// { dg-do compile }
+
+extern "C++" namespace ns {
+  struct Incomplete;
+  Incomplete foo;  // { dg-error "incomplete type" }
+}
+
+extern "C" extern "C" {
+  static int bar;  // { dg-bogus "invalid" }
+}

[gcc r13-8674] libstdc++: Reverse arguments in constraint for std::optional's <=> [PR104606]

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:3d16f8f2aec9583422d00c531732ca9d33e6ef26

commit r13-8674-g3d16f8f2aec9583422d00c531732ca9d33e6ef26
Author: Jonathan Wakely 
Date:   Wed Mar 27 21:51:13 2024 +

libstdc++: Reverse arguments in constraint for std::optional's <=> 
[PR104606]

This is a workaround for a possible compiler bug that causes constraint
recursion in the operator<=>(const optional&, const U&) overload.

libstdc++-v3/ChangeLog:

PR libstdc++/104606
* include/std/optional (operator<=>(const optional&, const U&)):
Reverse order of three_way_comparable_with template arguments.
* testsuite/20_util/optional/relops/104606.cc: New test.

(cherry picked from commit 7f65d8267fbfd19cf21a3dc71d27e989e75044a3)

Diff:
---
 libstdc++-v3/include/std/optional  |  2 +-
 .../testsuite/20_util/optional/relops/104606.cc| 18 ++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/libstdc++-v3/include/std/optional 
b/libstdc++-v3/include/std/optional
index 29f534b9861..e4f3fc65340 100644
--- a/libstdc++-v3/include/std/optional
+++ b/libstdc++-v3/include/std/optional
@@ -1434,7 +1434,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 #ifdef __cpp_lib_three_way_comparison
   template
 requires (!__is_optional_v<_Up>)
-  && three_way_comparable_with<_Tp, _Up>
+  && three_way_comparable_with<_Up, _Tp>
 constexpr compare_three_way_result_t<_Tp, _Up>
 operator<=>(const optional<_Tp>& __x, const _Up& __v)
 { return bool(__x) ? *__x <=> __v : strong_ordering::less; }
diff --git a/libstdc++-v3/testsuite/20_util/optional/relops/104606.cc 
b/libstdc++-v3/testsuite/20_util/optional/relops/104606.cc
new file mode 100644
index 000..2b8df245219
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/optional/relops/104606.cc
@@ -0,0 +1,18 @@
+// { dg-do compile { target c++17 } }
+
+// Bug 104606 comparison operator resolution with std::optional and -std=c++20
+
+#include 
+#include 
+#include 
+
+struct Value : std::variant> { };
+
+struct Comparator {
+  template  bool operator<=(const T &) { return true; }
+};
+
+std::optional o;
+Comparator c;
+
+auto x = c <= o;

[gcc r13-8675] libstdc++: Fix infinite loop in std::istream::ignore(n, delim) [PR93672]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:fcf60d0baafa1245f768ac375dc60a07e92e9673

commit r13-8675-gfcf60d0baafa1245f768ac375dc60a07e92e9673
Author: Jonathan Wakely 
Date:   Thu Apr 4 10:33:33 2024 +0100

libstdc++: Fix infinite loop in std::istream::ignore(n, delim) [PR93672]

A negative delim value passed to std::istream::ignore can never match
any character in the stream, because the comparison is done using
traits_type::eq_int_type(sb->sgetc(), delim) and sgetc() never returns
negative values (except at EOF). The optimized version of ignore for the
std::istream specialization uses traits_type::find to locate the delim
character in the streambuf, which _can_ match a negative delim on
platforms where char is signed, but then we do another comparison using
eq_int_type which fails. The code then keeps looping forever, with
traits_type::find locating the character and traits_type::eq_int_type
saying it's not a match, so traits_type::find is used again and finds
the same character again.

A possible fix would be to check with eq_int_type after a successful
find, to see whether we really have a match. However, that would be
suboptimal since we know that a negative delimiter will never match
using eq_int_type. So a better fix is to adjust the check at the top of
the function that handles delim==eof(), so that we treat all negative
delim values as equivalent to EOF. That way we don't bother using find
to search for something that will never match with eq_int_type.

The version of ignore in the primary template doesn't need a change,
because it doesn't use traits_type::find, instead characters are
extracted one-by-one and always matched using eq_int_type. That avoids
the inconsistency between find and eq_int_type. The specialization for
std::wistream does use traits_type::find, but traits_type::to_int_type
is equivalent to an implicit conversion from wchar_t to wint_t, so
passing a wchar_t directly to ignore without using to_int_type works.

libstdc++-v3/ChangeLog:

PR libstdc++/93672
* src/c++98/istream.cc (istream::ignore(streamsize, int_type)):
Treat all negative delimiter values as eof().
* testsuite/27_io/basic_istream/ignore/char/93672.cc: New test.
* testsuite/27_io/basic_istream/ignore/wchar_t/93672.cc: New
test.

(cherry picked from commit 2d694414ada8e3b58f504c1b175d31088529632e)

Diff:
---
 libstdc++-v3/src/c++98/istream.cc  |  13 ++-
 .../27_io/basic_istream/ignore/char/93672.cc   | 101 +
 .../27_io/basic_istream/ignore/wchar_t/93672.cc|  34 +++
 3 files changed, 146 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/src/c++98/istream.cc 
b/libstdc++-v3/src/c++98/istream.cc
index 74bf7b6f4fa..ebac7a6010b 100644
--- a/libstdc++-v3/src/c++98/istream.cc
+++ b/libstdc++-v3/src/c++98/istream.cc
@@ -112,8 +112,17 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 basic_istream::
 ignore(streamsize __n, int_type __delim)
 {
-  if (traits_type::eq_int_type(__delim, traits_type::eof()))
-   return ignore(__n);
+  {
+   // If conversion to int_type changes the value then __delim does not
+   // correspond to a value of type char_type, and so will never match
+   // a character extracted from the input sequence. Just use ignore(n).
+   const int_type chk_delim = traits_type::to_int_type(__delim);
+   const bool matchable = traits_type::eq_int_type(chk_delim, __delim);
+   if (__builtin_expect(!matchable, 0))
+ return ignore(__n);
+   // Now we know that __delim is a valid char_type value, so it's safe
+   // for the code below to use traits_type::find to search for it.
+  }
 
   _M_gcount = 0;
   sentry __cerb(*this, true);
diff --git a/libstdc++-v3/testsuite/27_io/basic_istream/ignore/char/93672.cc 
b/libstdc++-v3/testsuite/27_io/basic_istream/ignore/char/93672.cc
new file mode 100644
index 000..96737485b83
--- /dev/null
+++ b/libstdc++-v3/testsuite/27_io/basic_istream/ignore/char/93672.cc
@@ -0,0 +1,101 @@
+// { dg-do run }
+
+#include 
+#include 
+#include 
+
+void
+test_pr93672() // std::basic_istream::ignore hangs if delim MSB is set
+{
+  std::istringstream in(".\xfc..\xfd...\xfe.");
+
+  // This should find '\xfd' even on platforms where char is signed,
+  // because the delimiter is correctly converted to the stream's int_type.
+  in.ignore(100, std::char_traits::to_int_type('\xfc'));
+  VERIFY( in.gcount() == 2 );
+  VERIFY( ! in.eof() );
+
+  // This should work equivalently to traits_type::to_int_type
+  in.ignore(100, (unsigned char)'\xfd');
+  VERIFY( in.gcount() == 3 );
+  VERIFY( ! in.eof() );
+
+  // This only works if char is unsigned.
+  in.ignore(100, '\xfe');
+  if (std::numeric_limits::is_signed)
+  {
+// When char is signed, '\xfe' != traits_type::to_int_type('\xfe')
+// so 

[gcc r15-115] [committed] [RISC-V] Don't run new rounding tests on newlib risc-v targets

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:1e29da0b6508b23a7a6b14a7fb643b917a195003

commit r15-115-g1e29da0b6508b23a7a6b14a7fb643b917a195003
Author: Jeff Law 
Date:   Thu May 2 08:42:32 2024 -0600

[committed] [RISC-V] Don't run new rounding tests on newlib risc-v targets

The new round_32.c and round_64.c tests depend on the optimizers to 
recognize
the conversions feeding the floor/ceil calls and convert them into ceilf,
floorf and the like.

Those transformations only occur when the target indicates the C library has
the appropriate routines (fnclass == function_c99_misc).  While newlib has
these routines, they are not exposed as available to the compiler and thus 
the
transformation the tests depend on do not happen. Naturally the scan-tests 
then
fail.

gcc/testsuite
* gcc.target/riscv/round_32.c: Add require-effective-target glibc.
* gcc.target/riscv/round_64.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/riscv/round_32.c | 1 +
 gcc/testsuite/gcc.target/riscv/round_64.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/round_32.c 
b/gcc/testsuite/gcc.target/riscv/round_32.c
index f9fea70ad55..88ff77aff2e 100644
--- a/gcc/testsuite/gcc.target/riscv/round_32.c
+++ b/gcc/testsuite/gcc.target/riscv/round_32.c
@@ -1,4 +1,5 @@
 /* { dg-do compile { target { riscv32*-*-* } } } */
+/* { dg-require-effective-target glibc } */
 /* { dg-options "-march=rv32gc -mabi=ilp32d -fno-math-errno 
-funsafe-math-optimizations -fno-inline" } */
 /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/round_64.c 
b/gcc/testsuite/gcc.target/riscv/round_64.c
index e79690979a5..5e13bccdcd2 100644
--- a/gcc/testsuite/gcc.target/riscv/round_64.c
+++ b/gcc/testsuite/gcc.target/riscv/round_64.c
@@ -1,4 +1,5 @@
 /* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-require-effective-target glibc } */
 /* { dg-options "-march=rv64gc -mabi=lp64d -fno-math-errno 
-funsafe-math-optimizations -fno-inline" } */
 /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Don't run new rounding tests on newlib risc-v targets

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:951478ab3bfe126e0f07cbf26366c48e08883b1f

commit 951478ab3bfe126e0f07cbf26366c48e08883b1f
Author: Jeff Law 
Date:   Thu May 2 08:42:32 2024 -0600

[committed] [RISC-V] Don't run new rounding tests on newlib risc-v targets

The new round_32.c and round_64.c tests depend on the optimizers to 
recognize
the conversions feeding the floor/ceil calls and convert them into ceilf,
floorf and the like.

Those transformations only occur when the target indicates the C library has
the appropriate routines (fnclass == function_c99_misc).  While newlib has
these routines, they are not exposed as available to the compiler and thus 
the
transformation the tests depend on do not happen. Naturally the scan-tests 
then
fail.

gcc/testsuite
* gcc.target/riscv/round_32.c: Add require-effective-target glibc.
* gcc.target/riscv/round_64.c: Likewise.

(cherry picked from commit 1e29da0b6508b23a7a6b14a7fb643b917a195003)

Diff:
---
 gcc/testsuite/gcc.target/riscv/round_32.c | 1 +
 gcc/testsuite/gcc.target/riscv/round_64.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/round_32.c 
b/gcc/testsuite/gcc.target/riscv/round_32.c
index f9fea70ad55..88ff77aff2e 100644
--- a/gcc/testsuite/gcc.target/riscv/round_32.c
+++ b/gcc/testsuite/gcc.target/riscv/round_32.c
@@ -1,4 +1,5 @@
 /* { dg-do compile { target { riscv32*-*-* } } } */
+/* { dg-require-effective-target glibc } */
 /* { dg-options "-march=rv32gc -mabi=ilp32d -fno-math-errno 
-funsafe-math-optimizations -fno-inline" } */
 /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/round_64.c 
b/gcc/testsuite/gcc.target/riscv/round_64.c
index e79690979a5..5e13bccdcd2 100644
--- a/gcc/testsuite/gcc.target/riscv/round_64.c
+++ b/gcc/testsuite/gcc.target/riscv/round_64.c
@@ -1,4 +1,5 @@
 /* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-require-effective-target glibc } */
 /* { dg-options "-march=rv64gc -mabi=lp64d -fno-math-errno 
-funsafe-math-optimizations -fno-inline" } */
 /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */

[gcc r15-116] RISC-V: Add testcase for pr114734

[Patrick O'Neill via Gcc-cvs]

https://gcc.gnu.org/g:ff4dc8b10a421cdb0c56f7f8c238609de4f9fbe2

commit r15-116-gff4dc8b10a421cdb0c56f7f8c238609de4f9fbe2
Author: Patrick O'Neill 
Date:   Tue Apr 30 13:26:45 2024 -0700

RISC-V: Add testcase for pr114734

gcc/testsuite/ChangeLog:

PR middle-end/114734

* gcc.target/riscv/rvv/autovec/pr114734.c: New test.

Signed-off-by: Patrick O'Neill 

Diff:
---
 .../gcc.target/riscv/rvv/autovec/pr114734.c| 25 ++
 1 file changed, 25 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
new file mode 100644
index 000..b605d992aa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v } */
+/* { dg-options { -march=rv64gcv_zvl256b -mabi=lp64d -fwhole-program -O3 
-mrvv-vector-bits=zvl  } } */
+
+int f[18];
+int g[18];
+int h[18][18][18];
+int a[324];
+long b[18];
+int *i = g;
+int (*j)[18][18] = h;
+int z;
+int main() {
+  for (int m = 0; m < 18; ++m)
+f[m] = 3;
+  for (int m = 0; m < 18; m += 1)
+for (int n = 0; n < 18; n += 3) {
+  a[m * 8 + n] = j[m][m][0] ? i[n] : 0;
+  b[n] = f[n] ? -i[m] : 0;
+}
+  for (long n = 0; n < 8; ++n)
+z = a[n];
+  if (b[15] != 0)
+__builtin_abort();
+}

[gcc] Created branch 'meissner/heads/work165' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work165' was created in namespace 'refs/users' 
pointing to:

 ff4dc8b10a4... RISC-V: Add testcase for pr114734

[gcc(refs/users/meissner/heads/work165)] Add ChangeLog.meissner and REVISION.

[Michael Meissner via Libstdc++-cvs]

https://gcc.gnu.org/g:b9eabf648477255adae3c56a2a15b8d6720d665f

commit b9eabf648477255adae3c56a2a15b8d6720d665f
Author: Michael Meissner 
Date:   Thu May 2 14:00:29 2024 -0400

Add ChangeLog.meissner and REVISION.

2024-05-02  Michael Meissner  

gcc/

* REVISION: New file for branch.
* ChangeLog.meissner: New file.

gcc/c-family/

* ChangeLog.meissner: New file.

gcc/c/

* ChangeLog.meissner: New file.

gcc/cp/

* ChangeLog.meissner: New file.

gcc/fortran/

* ChangeLog.meissner: New file.

gcc/testsuite/

* ChangeLog.meissner: New file.

libgcc/

* ChangeLog.meissner: New file.

Diff:
---
 gcc/ChangeLog.meissner   | 6 ++
 gcc/REVISION | 1 +
 gcc/c-family/ChangeLog.meissner  | 6 ++
 gcc/c/ChangeLog.meissner | 6 ++
 gcc/cp/ChangeLog.meissner| 6 ++
 gcc/fortran/ChangeLog.meissner   | 6 ++
 gcc/testsuite/ChangeLog.meissner | 6 ++
 libgcc/ChangeLog.meissner| 6 ++
 libstdc++-v3/ChangeLog.meissner  | 6 ++
 9 files changed, 49 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
new file mode 100644
index 000..fadf36aa1b3
--- /dev/null
+++ b/gcc/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work165, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index 000..c1acb0df2c0
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work165 branch
diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner
new file mode 100644
index 000..fadf36aa1b3
--- /dev/null
+++ b/gcc/c-family/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work165, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner
new file mode 100644
index 000..fadf36aa1b3
--- /dev/null
+++ b/gcc/c/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work165, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner
new file mode 100644
index 000..fadf36aa1b3
--- /dev/null
+++ b/gcc/cp/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work165, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner
new file mode 100644
index 000..fadf36aa1b3
--- /dev/null
+++ b/gcc/fortran/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work165, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
new file mode 100644
index 000..fadf36aa1b3
--- /dev/null
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work165, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner
new file mode 100644
index 000..fadf36aa1b3
--- /dev/null
+++ b/libgcc/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work165, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner
new file mode 100644
index 000..fadf36aa1b3
--- /dev/null
+++ b/libstdc++-v3/ChangeLog.meissner
@@ -0,0 +1,6 @@
+ Branch work165, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+

[gcc] Created branch 'meissner/heads/work165-dmf' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work165-dmf' was created in namespace 'refs/users' 
pointing to:

 b9eabf64847... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work165-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:9c86f6446956d93cb99623c13c89f14304254527

commit 9c86f6446956d93cb99623c13c89f14304254527
Author: Michael Meissner 
Date:   Thu May 2 14:01:24 2024 -0400

Add ChangeLog.dmf and update REVISION.

2024-05-02  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index 000..d94e03e767e
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,6 @@
+ Branch work165-dmf, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index c1acb0df2c0..84e8cdcc4ef 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work165 branch
+work165-dmf branch

[gcc] Created branch 'meissner/heads/work165-vpair' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work165-vpair' was created in namespace 'refs/users' 
pointing to:

 b9eabf64847... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work165-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:127051cce9903b16d99320c348bb8ab536fe84af

commit 127051cce9903b16d99320c348bb8ab536fe84af
Author: Michael Meissner 
Date:   Thu May 2 14:02:24 2024 -0400

Add ChangeLog.vpair and update REVISION.

2024-05-02  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 6 ++
 gcc/REVISION| 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index 000..01a40b0cd7f
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,6 @@
+ Branch work165-vpair, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index c1acb0df2c0..446e8bf93ed 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work165 branch
+work165-vpair branch

[gcc] Created branch 'meissner/heads/work165-tar' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work165-tar' was created in namespace 'refs/users' 
pointing to:

 b9eabf64847... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work165-tar)] Add ChangeLog.tar and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:7922492691ac5ad660132b80f321cbd99dc86b49

commit 7922492691ac5ad660132b80f321cbd99dc86b49
Author: Michael Meissner 
Date:   Thu May 2 14:03:29 2024 -0400

Add ChangeLog.tar and update REVISION.

2024-05-02  Michael Meissner  

gcc/

* ChangeLog.tar: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.tar | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
new file mode 100644
index 000..26f27bb12ae
--- /dev/null
+++ b/gcc/ChangeLog.tar
@@ -0,0 +1,6 @@
+ Branch work165-tar, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index c1acb0df2c0..057e8867862 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work165 branch
+work165-tar branch

[gcc] Created branch 'meissner/heads/work165-bugs' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work165-bugs' was created in namespace 'refs/users' 
pointing to:

 b9eabf64847... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work165-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:2b46c7250c1e70e08ebd7a669a434552d1ee6a11

commit 2b46c7250c1e70e08ebd7a669a434552d1ee6a11
Author: Michael Meissner 
Date:   Thu May 2 14:04:30 2024 -0400

Add ChangeLog.bugs and update REVISION.

2024-05-02  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index 000..bbfddc4b438
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,6 @@
+ Branch work165-bugs, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index c1acb0df2c0..2d5ce10c39a 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work165 branch
+work165-bugs branch

[gcc] Created branch 'meissner/heads/work165-test' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work165-test' was created in namespace 'refs/users' 
pointing to:

 b9eabf64847... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work165-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:23c1e5caf3d786300845f78d0db6198a16e6413b

commit 23c1e5caf3d786300845f78d0db6198a16e6413b
Author: Michael Meissner 
Date:   Thu May 2 14:05:38 2024 -0400

Add ChangeLog.test and update REVISION.

2024-05-02  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index 000..6f9db439615
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,6 @@
+ Branch work165-test, baseline 
+
+2024-05-02   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index c1acb0df2c0..7e21c32ee45 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work165 branch
+work165-test branch

[gcc] Created branch 'meissner/heads/work165-orig' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work165-orig' was created in namespace 'refs/users' 
pointing to:

 ff4dc8b10a4... RISC-V: Add testcase for pr114734

[gcc(refs/users/meissner/heads/work165-orig)] Add REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0aabe840e9842432f47d30a73820c7ab994eff2d

commit 0aabe840e9842432f47d30a73820c7ab994eff2d
Author: Michael Meissner 
Date:   Thu May 2 14:06:36 2024 -0400

Add REVISION.

2024-05-02  Michael Meissner  

gcc/

* REVISION: New file for branch.

Diff:
---
 gcc/REVISION | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index 000..4c67071ea00
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work165-orig branch

[gcc r13-8676] tree-optimization/114672 - WIDEN_MULT_PLUS_EXPR type mismatch

[Richard Ball via Gcc-cvs]

https://gcc.gnu.org/g:0d625dc1bffd885b04eb90ff48a6d34acacc3e0b

commit r13-8676-g0d625dc1bffd885b04eb90ff48a6d34acacc3e0b
Author: Richard Biener 
Date:   Wed Apr 10 10:33:40 2024 +0200

tree-optimization/114672 - WIDEN_MULT_PLUS_EXPR type mismatch

The following makes sure to restrict WIDEN_MULT*_EXPR to a mode
precision final compute type as the mode is used to find the optab
and type checking chokes when seeing bit-precisions later which
would likely also not properly expanded to RTL.

PR tree-optimization/114672
* tree-ssa-math-opts.cc (convert_plusminus_to_widen): Only
allow mode-precision results.

* gcc.dg/torture/pr114672.c: New testcase.

(cherry picked from commit 912753cc5f18d786e334dd425469fa7f93155661)

Diff:
---
 gcc/testsuite/gcc.dg/torture/pr114672.c | 14 ++
 gcc/tree-ssa-math-opts.cc   |  5 +++--
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/torture/pr114672.c 
b/gcc/testsuite/gcc.dg/torture/pr114672.c
new file mode 100644
index 000..b69511fe8db
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr114672.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+
+struct {
+  __INT64_TYPE__ m : 60;
+} s;
+
+short a;
+short b;
+
+void
+foo ()
+{
+  s.m += a * b;
+}
diff --git a/gcc/tree-ssa-math-opts.cc b/gcc/tree-ssa-math-opts.cc
index ff949e4fec9..08cf33214ad 100644
--- a/gcc/tree-ssa-math-opts.cc
+++ b/gcc/tree-ssa-math-opts.cc
@@ -2875,8 +2875,9 @@ convert_plusminus_to_widen (gimple_stmt_iterator *gsi, 
gimple *stmt,
 
   lhs = gimple_assign_lhs (stmt);
   type = TREE_TYPE (lhs);
-  if (TREE_CODE (type) != INTEGER_TYPE
-  && TREE_CODE (type) != FIXED_POINT_TYPE)
+  if ((TREE_CODE (type) != INTEGER_TYPE
+   && TREE_CODE (type) != FIXED_POINT_TYPE)
+  || !type_has_mode_precision_p (type))
 return false;
 
   if (code == MINUS_EXPR)

[gcc r12-10410] tree-optimization/114672 - WIDEN_MULT_PLUS_EXPR type mismatch

[Richard Ball via Gcc-cvs]

https://gcc.gnu.org/g:87e37c72cfb153d65ac8b26d6f2d1fe155818318

commit r12-10410-g87e37c72cfb153d65ac8b26d6f2d1fe155818318
Author: Richard Biener 
Date:   Wed Apr 10 10:33:40 2024 +0200

tree-optimization/114672 - WIDEN_MULT_PLUS_EXPR type mismatch

The following makes sure to restrict WIDEN_MULT*_EXPR to a mode
precision final compute type as the mode is used to find the optab
and type checking chokes when seeing bit-precisions later which
would likely also not properly expanded to RTL.

PR tree-optimization/114672
* tree-ssa-math-opts.cc (convert_plusminus_to_widen): Only
allow mode-precision results.

* gcc.dg/torture/pr114672.c: New testcase.

(cherry picked from commit 912753cc5f18d786e334dd425469fa7f93155661)

Diff:
---
 gcc/testsuite/gcc.dg/torture/pr114672.c | 14 ++
 gcc/tree-ssa-math-opts.cc   |  5 +++--
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/torture/pr114672.c 
b/gcc/testsuite/gcc.dg/torture/pr114672.c
new file mode 100644
index 000..b69511fe8db
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr114672.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+
+struct {
+  __INT64_TYPE__ m : 60;
+} s;
+
+short a;
+short b;
+
+void
+foo ()
+{
+  s.m += a * b;
+}
diff --git a/gcc/tree-ssa-math-opts.cc b/gcc/tree-ssa-math-opts.cc
index bab0cc5aef4..ffd8eebd2a9 100644
--- a/gcc/tree-ssa-math-opts.cc
+++ b/gcc/tree-ssa-math-opts.cc
@@ -2802,8 +2802,9 @@ convert_plusminus_to_widen (gimple_stmt_iterator *gsi, 
gimple *stmt,
 
   lhs = gimple_assign_lhs (stmt);
   type = TREE_TYPE (lhs);
-  if (TREE_CODE (type) != INTEGER_TYPE
-  && TREE_CODE (type) != FIXED_POINT_TYPE)
+  if ((TREE_CODE (type) != INTEGER_TYPE
+   && TREE_CODE (type) != FIXED_POINT_TYPE)
+  || !type_has_mode_precision_p (type))
 return false;
 
   if (code == MINUS_EXPR)

[gcc r15-118] [RFA][RISC-V] Improve constant synthesis for constants with 2 bits set

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:9b54bea455e54fd138bf2b045bdcc133ed4e8a84

commit r15-118-g9b54bea455e54fd138bf2b045bdcc133ed4e8a84
Author: Jeff Law 
Date:   Thu May 2 14:06:22 2024 -0600

[RFA][RISC-V] Improve constant synthesis for constants with 2 bits set

In doing some preparation work for using zbkb's pack instructions for 
constant
synthesis I figured it would be wise to get a sense of how well our constant
synthesis is actually working and address any clear issues.

So the first glaring inefficiency is in our handling of constants with a 
small
number of bits set.  Let's start with just two bits set.   There are 2016
distinct constants in that space (rv64).  With Zbs enabled the absolute 
worst
we should ever do is two instructions (bseti+bseti).  Yet we have 503 cases
where we're generating 3+ instructions when there's just two bits set in the
constant.  A constant like 0x80001000 generates 4 instructions!

This patch adds bseti (and indirectly binvi if we needed it) as a first 
class
citizen for constant synthesis.  There's two components to this change.

First, we can't generate an IOR with a constant like (1 << 45) as an 
operand.
The IOR/XOR define_insn is in riscv.md.  The constant argument for those
patterns must match an arith_operand which means its not really usable for
generating bseti directly in the cases we care about (at least one of the 
bits
will be in the 32..63 range and thus won't match arith_operand).

We have a few things we could do.  One would be to extend the existing 
pattern
to incorporate bseti cases.  But I suspect folks like the separation of the
base architecture (riscv.md) from the Zb* extensions (bitmanip.md).  We 
could
also try to generate the RTL for bseti
directly, bypassing gen_fmt_ee (which forces undesirable constants into 
registers based on the predicate of the appropriate define_insn). Neither of 
these seemed particularly appealing to me.

So what I've done instead is to make ior/xor a define_expand and have the
expander allow a wider set of constant operands when Zbs is enabled.  That
allows us to keep the bulk of Zb* support inside bitmanip.md and continue to
use gen_fmt_ee in the constant synthesis paths.

Note the code generation in this case is designed to first set as many bits 
as
we can with lui, then with addi since those can both set multiple bits at a
time.  If there are any residual bits left to set we can emit bseti
instructions up to the current cost ceiling.

This results in fixing all of the 503 2-bit set cases where we emitted too 
many
instructions.  It also significantly helps other scenarios with more bits 
set.

The testcase I'm including verifies the number of instructions we generate 
for
the full set of 2016 possible cases.  Obviously this won't be possible as we
increase the number of bits (there are something like 48k cases with just 3
bits set).

gcc/

* config/riscv/predicates.md (arith_or_zbs_operand): New predicate.
* config/riscv/riscv.cc (riscv_build_integer_one): Use bseti to set
single bits when profitable.
* config/riscv/riscv.md (*3): Renamed with '*' prefix.
(3): New expander for IOR/XOR.

gcc/testsuite
* gcc.target/riscv/synthesis-1.c: New test.

Diff:
---
 gcc/config/riscv/predicates.md   |8 +
 gcc/config/riscv/riscv.cc|   65 +-
 gcc/config/riscv/riscv.md|   17 +-
 gcc/testsuite/gcc.target/riscv/synthesis-1.c | 2034 ++
 4 files changed, 2110 insertions(+), 14 deletions(-)

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 539e0f7379b..e7d797d4dbf 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -386,6 +386,14 @@
   (and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (UINTVAL (op))")))
 
+;; Register, small constant or single bit constant for use in
+;; bseti/binvi.
+(define_predicate "arith_or_zbs_operand"
+  (ior (match_operand 0 "const_arith_operand")
+   (match_operand 0 "register_operand")
+   (and (match_test "TARGET_ZBS")
+   (match_operand 0 "single_bit_mask_operand"
+
 (define_predicate "not_single_bit_mask_operand"
   (and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (~UINTVAL (op))")))
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 24d1ead3902..8ed9df8126a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -725,6 +725,9 @@ riscv_build_integer_1 (struct riscv_integer_op 
codes[RISCV_MAX_INTEGER_OPS],
   HOST_WIDE_INT low_part = CONST_LOW_PART (value);
   int cost = RISCV_MAX_INTEGER_OPS + 1, alt_cost;
   struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS];
+  int upper_trailing_o

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RFA][RISC-V] Improve constant synthesis for constants with 2 bits set

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:8ff25863a65093b168fed2c36b0a40088fed1b0a

commit 8ff25863a65093b168fed2c36b0a40088fed1b0a
Author: Jeff Law 
Date:   Thu May 2 14:06:22 2024 -0600

[RFA][RISC-V] Improve constant synthesis for constants with 2 bits set

In doing some preparation work for using zbkb's pack instructions for 
constant
synthesis I figured it would be wise to get a sense of how well our constant
synthesis is actually working and address any clear issues.

So the first glaring inefficiency is in our handling of constants with a 
small
number of bits set.  Let's start with just two bits set.   There are 2016
distinct constants in that space (rv64).  With Zbs enabled the absolute 
worst
we should ever do is two instructions (bseti+bseti).  Yet we have 503 cases
where we're generating 3+ instructions when there's just two bits set in the
constant.  A constant like 0x80001000 generates 4 instructions!

This patch adds bseti (and indirectly binvi if we needed it) as a first 
class
citizen for constant synthesis.  There's two components to this change.

First, we can't generate an IOR with a constant like (1 << 45) as an 
operand.
The IOR/XOR define_insn is in riscv.md.  The constant argument for those
patterns must match an arith_operand which means its not really usable for
generating bseti directly in the cases we care about (at least one of the 
bits
will be in the 32..63 range and thus won't match arith_operand).

We have a few things we could do.  One would be to extend the existing 
pattern
to incorporate bseti cases.  But I suspect folks like the separation of the
base architecture (riscv.md) from the Zb* extensions (bitmanip.md).  We 
could
also try to generate the RTL for bseti
directly, bypassing gen_fmt_ee (which forces undesirable constants into 
registers based on the predicate of the appropriate define_insn). Neither of 
these seemed particularly appealing to me.

So what I've done instead is to make ior/xor a define_expand and have the
expander allow a wider set of constant operands when Zbs is enabled.  That
allows us to keep the bulk of Zb* support inside bitmanip.md and continue to
use gen_fmt_ee in the constant synthesis paths.

Note the code generation in this case is designed to first set as many bits 
as
we can with lui, then with addi since those can both set multiple bits at a
time.  If there are any residual bits left to set we can emit bseti
instructions up to the current cost ceiling.

This results in fixing all of the 503 2-bit set cases where we emitted too 
many
instructions.  It also significantly helps other scenarios with more bits 
set.

The testcase I'm including verifies the number of instructions we generate 
for
the full set of 2016 possible cases.  Obviously this won't be possible as we
increase the number of bits (there are something like 48k cases with just 3
bits set).

gcc/

* config/riscv/predicates.md (arith_or_zbs_operand): New predicate.
* config/riscv/riscv.cc (riscv_build_integer_one): Use bseti to set
single bits when profitable.
* config/riscv/riscv.md (*3): Renamed with '*' prefix.
(3): New expander for IOR/XOR.

gcc/testsuite
* gcc.target/riscv/synthesis-1.c: New test.

Diff:
---
 gcc/config/riscv/predicates.md   |8 +
 gcc/config/riscv/riscv.cc|   65 +-
 gcc/config/riscv/riscv.md|   17 +-
 gcc/testsuite/gcc.target/riscv/synthesis-1.c | 2034 ++
 4 files changed, 2110 insertions(+), 14 deletions(-)

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 539e0f7379b..e7d797d4dbf 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -386,6 +386,14 @@
   (and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (UINTVAL (op))")))
 
+;; Register, small constant or single bit constant for use in
+;; bseti/binvi.
+(define_predicate "arith_or_zbs_operand"
+  (ior (match_operand 0 "const_arith_operand")
+   (match_operand 0 "register_operand")
+   (and (match_test "TARGET_ZBS")
+   (match_operand 0 "single_bit_mask_operand"
+
 (define_predicate "not_single_bit_mask_operand"
   (and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (~UINTVAL (op))")))
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 24d1ead3902..8ed9df8126a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -725,6 +725,9 @@ riscv_build_integer_1 (struct riscv_integer_op 
codes[RISCV_MAX_INTEGER_OPS],
   HOST_WIDE_INT low_part = CONST_LOW_PART (value);
   int cost = RISCV_MAX_INTEGER_OPS + 1, alt_cost;
   struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS];
+  int upper_trailing_ones = ctz

[gcc(refs/users/meissner/heads/work165)] Add -mcpu=power11 tests.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a545c5b944c7b9e5e574623c18396a9f3864e8df

commit a545c5b944c7b9e5e574623c18396a9f3864e8df
Author: Michael Meissner 
Date:   Thu May 2 16:20:22 2024 -0400

Add -mcpu=power11 tests.

This patch adds some simple tests for -mcpu=power11 support.  In order to 
run
these tests, you need an assembler that supports the appropriate option for
supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under 
AIX).

2024-05-02  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
* lib/target-supports.exp (check_effective_target_power11_ok): Add 
new
effective target.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +
 gcc/testsuite/gcc.target/powerpc/power11-2.c | 20 
 gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++
 gcc/testsuite/lib/target-supports.exp| 17 +
 4 files changed, 60 insertions(+)

diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c 
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index 000..6a2e802eedf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11.  */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c 
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index 000..7b9904c1d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute.  */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c 
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index 000..9b2d643cc0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } }  */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" }  */
+
+/* Check if we can set the power11 target via a target_clones attribute.  */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 3a55b2a4159..3d2a51604db 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7109,6 +7109,23 @@ proc check_effective_target_power10_ok { } {
 }
 }
 
+# Return 1 if this is a PowerPC target supporting -mcpu=power11.
+
+proc check_effective_target_power11_ok { } {
+if { ([istarget powerpc*-*-*]) } {
+   return [check_no_compiler_messages power11_ok object {
+   int main (void) {
+   #ifndef _ARCH_PWR11
+   #error "-mcpu=power11 is not supported"
+   #endif
+   return 0;
+   }
+   } "-mcpu=power11"]
+} else {
+   return 0
+}
+}
+
 # Return 1 if this is a PowerPC target supporting -mfloat128 via either
 # software emulation on power7/power8 systems or hardware support on power9.

[gcc(refs/users/meissner/heads/work165)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:59236fdd0cc45513ebc6d1c48220b46004b26473

commit 59236fdd0cc45513ebc6d1c48220b46004b26473
Author: Michael Meissner 
Date:   Thu May 2 16:22:35 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 121 -
 1 file changed, 120 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index fadf36aa1b3..0c4392bd9d9 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,6 +1,125 @@
+ Branch work165, patch #3 
+
+Add -mcpu=power11 tests.
+
+This patch adds some simple tests for -mcpu=power11 support.  In order to run
+these tests, you need an assembler that supports the appropriate option for
+supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX).
+
+2024-05-02  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/power11-1.c: New test.
+   * gcc.target/powerpc/power11-2.c: Likewise.
+   * gcc.target/powerpc/power11-3.c: Likewise.
+   * lib/target-supports.exp (check_effective_target_power11_ok): Add new
+   effective target.
+
+ Branch work165, patch #2 
+
+Add -mcpu=power11 tuning support.
+
+This patch makes -mtune=power11 use the same tuning decisions as 
-mtune=power10.
+
+2024-05-02  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/power10.md (all reservations): Add power11 as an
+   alternative to power10.
+
+ Branch work165, patch #1 
+
+Add -mcpu=power11 support.
+
+This patch adds the power11 option to the -mcpu= and -mtune= switches.
+
+This patch treats the power11 like a power10 in terms of costs and 
reassociation
+width.
+
+This patch issues a ".machine power11" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
+
+This patch allows GCC to be configured with the --with-cpu=power11 and
+--with-tune=power11 options.
+
+This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
+
+This patch adds support for using "power11" in the __builtin_cpu_is built-in
+function.
+
+2024-05-02  Michael Meissner  
+
+gcc/
+
+   * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
+   * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
+   * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+   * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
+   * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+   _ARCH_PWR11 if -mcpu=power11.
+   * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define.
+   (POWERPC_MASKS): Add power11 isa bit.
+   (power11 cpu): Add power11 definition.
+   * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 
processor.
+   * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
+   * config/rs6000/rs6000-tables.opt: Regenerate.
+   * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11
+   support.
+   (rs6000_machine_from_flags): Likewise.
+   (rs6000_reassociation_width): Likewise.
+   (rs6000_adjust_cost): Likewise.
+   (rs6000_issue_rate): Likewise.
+   (rs6000_sched_reorder): Likewise.
+   (rs6000_sched_reorder2): Likewise.
+   (rs6000_register_move_cost): Likewise.
+   (rs6000_opt_masks): Likewise.
+   * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/rs6000.md (cpu attribute): Add power11.
+   * config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag.
+   * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11.
+
  Branch work165, baseline 
 
+Add ChangeLog.meissner and REVISION.
+
+2024-05-02  Michael Meissner  
+
+gcc/
+
+   * REVISION: New file for branch.
+   * ChangeLog.meissner: New file.
+
+gcc/c-family/
+
+   * ChangeLog.meissner: New file.
+
+gcc/c/
+
+   * ChangeLog.meissner: New file.
+
+gcc/cp/
+
+   * ChangeLog.meissner: New file.
+
+gcc/fortran/
+
+   * ChangeLog.meissner: New file.
+
+gcc/testsuite/
+
+   * ChangeLog.meissner: New file.
+
+libgcc/
+
+   * ChangeLog.meissner: New file.
+
 2024-05-02   Michael Meissner  
 
Clone branch
-

[gcc(refs/users/meissner/heads/work165)] Add -mcpu=power11 tuning support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:eb2f8908c20c3d2b5ae4552d896931484c27b461

commit eb2f8908c20c3d2b5ae4552d896931484c27b461
Author: Michael Meissner 
Date:   Thu May 2 16:17:34 2024 -0400

Add -mcpu=power11 tuning support.

This patch makes -mtune=power11 use the same tuning decisions as 
-mtune=power10.

2024-05-02  Michael Meissner  

gcc/

* config/rs6000/power10.md (all reservations): Add power11 as an
alternative to power10.

Diff:
---
 gcc/config/rs6000/power10.md | 144 +--
 1 file changed, 72 insertions(+), 72 deletions(-)

diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index fcc2199ab29..90312643858 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,4 @@
-;; Scheduling description for the IBM POWER10 processor.
+;; Scheduling description for the IBM POWER10 and POWER11 processors.
 ;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
 ;;
 ;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -97,12 +97,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-fused-load" 4
   (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +110,13 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-load-update" 4
   (and (eq_attr "type" "load")
(eq_attr "update" "yes")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +124,7 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +132,14 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-double" 4
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +148,27 @@
   (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-single" 7
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-vecload" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,LU_power10")
 
 ; lxvp
 (define_insn_reservation "power10-vecload-pair" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "256")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; Store Unit
@@ -178,12 +178,12 @@
(eq_attr "prefixed" "no")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-store" 0
   (and (eq_attr "type" "fused_store_store")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,STU_power10")
 
 (define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +191,52 @@
(eq_attr "prefixed" "yes")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,STU_power10")
 
 ; Update forms have 2 cycle latency for updated addr reg
 (define_insn_reservation "power10-store-update" 2
   (and (eq_attr "type" "store,fpstore")
(eq_attr "update" "yes")
-   (eq_attr "cpu" "power10"))
+   (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,STU_powe

[gcc(refs/users/meissner/heads/work165)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8b80d699784540a8f3cad07e7b0efbb144ab943e

commit 8b80d699784540a8f3cad07e7b0efbb144ab943e
Author: Michael Meissner 
Date:   Thu May 2 16:32:06 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 64 ++
 1 file changed, 64 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 0c4392bd9d9..981cda2e4b9 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,67 @@
+ Branch work165, patch #11 
+
+Add -mcpu=future tuning support.
+
+This patch makes -mtune=future use the same tuning decision as -mtune=power11.
+
+2024-04-08  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/power10.md (all reservations): Add future as an
+   alterntive to power10 and power11.
+
+ Branch work165, patch #10 
+
+Add -mcpu=future support.
+
+This patch adds the future option to the -mcpu= and -mtune= switches.
+
+This patch treats the future like a power11 in terms of costs and reassociation
+width.
+
+This patch issues a ".machine future" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
+
+This patch allows GCC to be configured with the --with-cpu=future and
+--with-tune=future options.
+
+This patch passes -mfuture to the assembler if the user uses -mcpu=future.
+
+2024-04-08  Michael Meissner  
+
+gcc/
+
+   * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
+   * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
+   * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+   _ARCH_PWR_FUTURE if -mcpu=future.
+   * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define.
+   (POWERPC_MASKS): Add future isa bit.
+   (power11 cpu): Add future definition.
+   * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor.
+   * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
+   * config/rs6000/rs6000-tables.opt: Regenerate.
+   * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future
+   support.
+   (rs6000_machine_from_flags): Likewise.
+   (rs6000_reassociation_width): Likewise.
+   (rs6000_adjust_cost): Likewise.
+   (rs6000_issue_rate): Likewise.
+   (rs6000_sched_reorder): Likewise.
+   (rs6000_sched_reorder2): Likewise.
+   (rs6000_register_move_cost): Likewise.
+   (rs6000_opt_masks): Likewise.
+   * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/rs6000.md (cpu attribute): Add future.
+   * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag.
+   * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future.
+
  Branch work165, patch #3 
 
 Add -mcpu=power11 tests.

[gcc(refs/users/meissner/heads/work165)] Add -mcpu=future tuning support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8f57958b33f5a9d0fdfd1057e1deb04eed29e35f

commit 8f57958b33f5a9d0fdfd1057e1deb04eed29e35f
Author: Michael Meissner 
Date:   Thu May 2 16:30:35 2024 -0400

Add -mcpu=future tuning support.

This patch makes -mtune=future use the same tuning decision as 
-mtune=power11.

2024-05-02  Michael Meissner  

gcc/

* config/rs6000/power10.md (all reservations): Add future as an
alterntive to power10 and power11.

Diff:
---
 gcc/config/rs6000/power10.md | 145 ++-
 1 file changed, 73 insertions(+), 72 deletions(-)

diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index 90312643858..1ec1bef0726 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,5 @@
-;; Scheduling description for the IBM POWER10 and POWER11 processors.
+;; Scheduling description for the IBM POWER10 and POWER11 processors as well as
+;; potential future processors.
 ;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
 ;;
 ;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -97,12 +98,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-fused-load" 4
   (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +111,13 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-load-update" 4
   (and (eq_attr "type" "load")
(eq_attr "update" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +125,7 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "no")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +133,14 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "yes")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-double" 4
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +149,27 @@
   (and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-single" 7
   (and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-vecload" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,LU_power10")
 
 ; lxvp
 (define_insn_reservation "power10-vecload-pair" 4
   (and (eq_attr "type" "vecload")
(eq_attr "size" "256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; Store Unit
@@ -178,12 +179,12 @@
(eq_attr "prefixed" "no")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-store" 0
   (and (eq_attr "type" "fused_store_store")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 (define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +192,52 @@
(eq_attr "prefixed" "yes")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
-   (eq_attr "cpu" "power10,power11"))
+   (eq_attr "cpu" "power10,power11,future"))
   "DU_even_power10,STU_power10")
 
 ; Update forms

[gcc(refs/users/meissner/heads/work165)] Add -mcpu=power11 support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b5e0d816387824fb95e5cf2fdb3e949c826af3f2

commit b5e0d816387824fb95e5cf2fdb3e949c826af3f2
Author: Michael Meissner 
Date:   Thu May 2 16:15:43 2024 -0400

Add -mcpu=power11 support.

This patch adds the power11 option to the -mcpu= and -mtune= switches.

This patch treats the power11 like a power10 in terms of costs and 
reassociation
width.

This patch issues a ".machine power11" to the assembly file if you use
-mcpu=power11.

This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.

This patch allows GCC to be configured with the --with-cpu=power11 and
--with-tune=power11 options.

This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.

This patch adds support for using "power11" in the __builtin_cpu_is built-in
function.

2024-05-02  Michael Meissner  

gcc/

* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for 
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR11 if -mcpu=power11.
* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New 
define.
(POWERPC_MASKS): Add power11 isa bit.
(power11 cpu): Add power11 definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add 
power11
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add power11.
* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA 
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document 
-mcpu=power11.

Diff:
---
 gcc/config.gcc  |  6 --
 gcc/config/rs6000/aix71.h   |  1 +
 gcc/config/rs6000/aix72.h   |  1 +
 gcc/config/rs6000/aix73.h   |  1 +
 gcc/config/rs6000/driver-rs6000.cc  |  2 ++
 gcc/config/rs6000/ppc-auxv.h|  3 +--
 gcc/config/rs6000/rs6000-builtin.cc |  1 +
 gcc/config/rs6000/rs6000-c.cc   |  2 ++
 gcc/config/rs6000/rs6000-cpus.def   |  5 +
 gcc/config/rs6000/rs6000-opts.h |  3 ++-
 gcc/config/rs6000/rs6000-string.cc  |  1 +
 gcc/config/rs6000/rs6000-tables.opt |  3 +++
 gcc/config/rs6000/rs6000.cc | 32 
 gcc/config/rs6000/rs6000.h  |  1 +
 gcc/config/rs6000/rs6000.md |  2 +-
 gcc/config/rs6000/rs6000.opt|  3 +++
 gcc/doc/invoke.texi |  5 +++--
 17 files changed, 56 insertions(+), 16 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 95c91ee02be..c84f94e1d29 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -534,7 +534,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h 
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-   
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+   xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+   | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+   | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5601,7 +5603,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
-   | power[3456789] | power10 | power5+ | power6x \
+   | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d..41037b3852d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {  

[gcc(refs/users/meissner/heads/work165)] Add -mcpu=future support.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:553119d5df3bed5807c97e50c4aaf5e2fd8c7b99

commit 553119d5df3bed5807c97e50c4aaf5e2fd8c7b99
Author: Michael Meissner 
Date:   Thu May 2 16:27:59 2024 -0400

Add -mcpu=future support.

This patch adds the future option to the -mcpu= and -mtune= switches.

This patch treats the future like a power11 in terms of costs and 
reassociation
width.

This patch issues a ".machine future" to the assembly file if you use
-mcpu=power11.

This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.

This patch allows GCC to be configured with the --with-cpu=future and
--with-tune=future options.

This patch passes -mfuture to the assembler if the user uses -mcpu=future.

2024-05-02  Michael Meissner  

gcc/

* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for 
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New 
define.
(POWERPC_MASKS): Add future isa bit.
(power11 cpu): Add future definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future 
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add 
future
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add future.
* config/rs6000/rs6000.opt (-mpower11): Add internal future ISA 
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document 
-mcpu=future.

Diff:
---
 gcc/config.gcc  |  4 ++--
 gcc/config/rs6000/aix71.h   |  1 +
 gcc/config/rs6000/aix72.h   |  1 +
 gcc/config/rs6000/aix73.h   |  1 +
 gcc/config/rs6000/driver-rs6000.cc  |  2 ++
 gcc/config/rs6000/rs6000-c.cc   |  2 ++
 gcc/config/rs6000/rs6000-cpus.def   |  5 +
 gcc/config/rs6000/rs6000-opts.h |  3 ++-
 gcc/config/rs6000/rs6000-string.cc  |  1 +
 gcc/config/rs6000/rs6000-tables.opt |  3 +++
 gcc/config/rs6000/rs6000.cc | 30 ++
 gcc/config/rs6000/rs6000.h  |  1 +
 gcc/config/rs6000/rs6000.md |  2 +-
 gcc/config/rs6000/rs6000.opt|  3 +++
 gcc/doc/invoke.texi |  2 +-
 15 files changed, 48 insertions(+), 13 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index c84f94e1d29..0cea179a585 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -535,7 +535,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
-   | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+   | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 | 
xe500mc64 \
| xe5500 | xe6500)
cpu_is_64bit=yes
;;
@@ -5603,7 +5603,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
-   | power[3456789] | power1[01] | power5+ | power6x \
+   | power[3456789] | power1[01] | power5+ | power6x | 
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {  
\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
+  mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
   mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b4..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {   

[gcc r11-11412] rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:26d48b6d3e2d07583f25f0769d0c005864760aee

commit r11-11412-g26d48b6d3e2d07583f25f0769d0c005864760aee
Author: Peter Bergner 
Date:   Tue Apr 9 15:24:39 2024 -0500

rs6000: Replace OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR 
[PR101865]

This is a cleanup patch in preparation to fixing the real bug in PR101865.
TARGET_DIRECT_MOVE is redundant with TARGET_P8_VECTOR, so alias it to that.
Also replace all usages of OPTION_MASK_DIRECT_MOVE with 
OPTION_MASK_P8_VECTOR
and delete the now dead mask.

2024-04-09  Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000.h (TARGET_DIRECT_MOVE): Define.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete 
redundant
OPTION_MASK_DIRECT_MOVE usage.  Delete TARGET_DIRECT_MOVE dead code.
(rs6000_opt_masks): Neuter the "direct-move" option.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Replace
OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR.  Delete useless
comment.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
OPTION_MASK_DIRECT_MOVE.
(OTHER_P8_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (mdirect-move): Remove Mask and Var.

(cherry picked from commit 7924e352523b37155ed9d76dc426701de9d11a22)

Diff:
---
 gcc/config/rs6000/rs6000-c.c  | 14 +-
 gcc/config/rs6000/rs6000-cpus.def |  3 ---
 gcc/config/rs6000/rs6000.c| 14 +++---
 gcc/config/rs6000/rs6000.h|  2 ++
 gcc/config/rs6000/rs6000.opt  |  2 +-
 5 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index afcb5bb6e39..1e3117899bb 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -432,19 +432,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned on in the following condition:
- 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not
-explicitly disabled.
-Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
-have been turned on explicitly.
- Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
- turned off in any of the following conditions:
- 1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
-   disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
-   enabled.
- 2. TARGET_VSX is off.  */
-  if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
+  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 907e1469736..518897df935 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -49,7 +49,6 @@
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_QUAD_MEMORY  \
 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
@@ -94,7 +93,6 @@
 /* Flags that need to be turned off if -mno-power8-vector.  */
 #define OTHER_P8_VECTOR_MASKS  (OTHER_P9_VECTOR_MASKS  \
 | OPTION_MASK_P9_VECTOR\
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_CRYPTO)
 
 /* Flags that need to be turned off if -mno-vsx.  */
@@ -125,7 +123,6 @@
 | OPTION_MASK_CMPB \
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_DFP  \
-| OPTION_MASK_DIRECT_MOVE  \
 | OPTION_MASK_DLMZB\
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
 | OPTION_MASK_FLOAT128_HW  \
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 3e5281c0f05..4864c959a6e 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/co

[gcc r11-11413] rs6000: Add OPTION_MASK_POWER8 [PR101865]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:f8f02fd0bfeeb733a044a120b394eeac48de318a

commit r11-11413-gf8f02fd0bfeeb733a044a120b394eeac48de318a
Author: Peter Bergner 
Date:   Thu May 2 18:07:05 2024 -0500

rs6000: Add OPTION_MASK_POWER8 [PR101865]

The bug in PR101865 is the _ARCH_PWR8 predefine macro is conditional upon
TARGET_DIRECT_MOVE, which can be false for some -mcpu=power8 compiles if the
-mno-altivec or -mno-vsx options are used.  The solution here is to create
a new OPTION_MASK_POWER8 mask that is true for -mcpu=power8, regardless of
Altivec or VSX enablement.

Unfortunately, the only way to create an OPTION_MASK_* mask is to create
a new option, which we have done here, but marked it as WarnRemoved since
we do not want users using it.  For stage1, we will look into how we can
create ISA mask flags for use in the compiler without the need for explicit
options.

2024-04-12  Will Schmidt  
Peter Bergner  

gcc/
PR target/101865
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Use
OPTION_MASK_POWER8.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add 
OPTION_MASK_POWER8.
(ISA_2_7_MASKS_SERVER): Likewise.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Update
comment.  Use OPTION_MASK_POWER8 and TARGET_POWER8.
* config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8.
* config/rs6000/rs6000.md (define_attr "isa"): Add p8.
(define_attr "enabled"): Handle it.
(define_insn "prefetch"): Use TARGET_POWER8.
* config/rs6000/rs6000.opt (mpower8-internal): New.

gcc/testsuite/
PR target/101865
* gcc.target/powerpc/predefine-p7-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-noaltivec.c: New test.
* gcc.target/powerpc/predefine-p8-novsx.c: New test.
* gcc.target/powerpc/predefine-p8-pragma-vsx.c: New test.
* gcc.target/powerpc/predefine-p9-novsx.c: New test.

(cherry picked from commit aa57af93ba22865be747f926e4e5f219e7f8758a)

Diff:
---
 gcc/config/rs6000/rs6000-c.c   |   2 +-
 gcc/config/rs6000/rs6000-cpus.def  |   2 +
 gcc/config/rs6000/rs6000.c |   7 +-
 gcc/config/rs6000/rs6000.h |   2 +-
 gcc/config/rs6000/rs6000.md|   8 +-
 gcc/config/rs6000/rs6000.opt   |   4 +
 .../gcc.target/powerpc/predefine-p7-novsx.c|  22 +
 .../powerpc/predefine-p8-noaltivec-novsx.c |  26 ++
 .../gcc.target/powerpc/predefine-p8-noaltivec.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-novsx.c|  26 ++
 .../gcc.target/powerpc/predefine-p8-pragma-vsx.c   | 101 +
 .../gcc.target/powerpc/predefine-p9-novsx.c|  26 ++
 12 files changed, 244 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 1e3117899bb..60cbb1118ec 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -432,7 +432,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
+  if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 518897df935..6a1acbd3136 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,6 +47,7 @@
fusion here, instead set it in rs6000.c if we are tuning for a power8
system.  */
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
+| OPTION_MASK_POWER8   \
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
@@ -137,6 +138,7 @@
 | OPTION_MASK_MODULO   \
 | OPTION_MASK_MULHW\
 | OPTION_MASK_NO_UPDATE\
+| OPTION_MASK_POWER8   \
 | OPTION_MASK_P8_FUSION\
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_P9_MINMAX

[gcc r15-120] [committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:8367c996e55b2c54aeee25e446357a1015a1d11d

commit r15-120-g8367c996e55b2c54aeee25e446357a1015a1d11d
Author: Jeff Law 
Date:   Thu May 2 17:13:12 2024 -0600

[committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits

The CI system tripped an execution failure for rv32 with the ceil/round 
patch.

The fundamental problem is the FP->INT step in these sequences requires the
input size to match the output size.  The output size was based on 
rv32/rv64.
Meaning that we'd try to do DF->SI->DF.

That doesn't preserve the semantics we want in at least two ways.

The net is we can't use this trick for DF values on rv32.  While inside the
code I realized we had a similar problem for HF modes.  HF modes we can 
support
only for Zfa.  So I fixed that proactively.

The CI system also pointed out various formatting nits.  I think this fixes 
all
but one overly long line.

Note I could have factored the TARGET_ZFA test.  But I think as-written it's
clearer what the desired cases to transform are.

gcc/
* config/riscv/riscv.md (2): Adjust
condition to match what can be properly implemented.  Fix various
formatting issues.
(lsi2_sext): Fix formatting

Diff:
---
 gcc/config/riscv/riscv.md | 65 +--
 1 file changed, 34 insertions(+), 31 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b9b0acf92c7..d4676507b45 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2077,8 +2077,8 @@
 (define_insn "lsi2_sext"
   [(set (match_operand:DI   0 "register_operand" "=r")
 (sign_extend:DI (unspec:SI
-[(match_operand:ANYF 1 "register_operand" " f")]
-  ROUND)))]
+[(match_operand:ANYF 1 "register_operand" " f")]
+ ROUND)))]
   "TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)"
   "fcvt.w. %0,%1,"
   [(set_attr "type" "fcvt_f2i")
@@ -2094,13 +2094,25 @@
   [(set_attr "type" "fcvt_f2i")
(set_attr "mode" "")])
 
+;; There are a couple non-obvious restrictions to be aware of.
+;;
+;; We'll do a FP-INT conversion in the sequence.  But we don't
+;; have a .l (64bit) variant of those instructions for rv32.
+;; To preserve proper semantics we must reject DFmode inputs
+;; for rv32 unless Zfa is enabled.
+;;
+;; The ANYF iterator allows HFmode.  We don't have all the
+;; necessary patterns defined for HFmode.  So restrict HFmode
+;; to TARGET_ZFA.
 (define_expand "2"
   [(set (match_operand:ANYF 0 "register_operand" "=f")
-(unspec:ANYF
-[(match_operand:ANYF 1 "register_operand" " f")]
-ROUND))]
-  "TARGET_HARD_FLOAT && (TARGET_ZFA
- || flag_fp_int_builtin_inexact || 
!flag_trapping_math)"
+   (unspec:ANYF
+   [(match_operand:ANYF 1 "register_operand" " f")]
+   ROUND))]
+  "(TARGET_HARD_FLOAT
+&& (TARGET_ZFA || flag_fp_int_builtin_inexact || !flag_trapping_math)
+&& (TARGET_ZFA || TARGET_64BIT || mode != DFmode)
+&& (TARGET_ZFA || mode != HFmode))"
 {
   if (TARGET_ZFA)
 emit_insn (gen__zfa2 (operands[0],
@@ -2116,7 +2128,7 @@
 
   riscv_emit_move (tmp_reg, operands[1]);
   riscv_emit_move (coeff_reg,
-   riscv_vector::get_fp_rounding_coefficient 
(mode));
+  riscv_vector::get_fp_rounding_coefficient 
(mode));
   emit_insn (gen_abs2 (abs_reg, operands[1]));
 
   riscv_expand_conditional_branch (label, LT, abs_reg, coeff_reg);
@@ -2126,29 +2138,20 @@
 
   emit_label (label);
   switch (mode)
-{
-case SFmode:
-  reg = gen_reg_rtx (SImode);
-  emit_insn (gen_lsfsi2 (reg, operands[1]));
-  emit_insn (gen_floatsisf2 (abs_reg, reg));
-  break;
-case DFmode:
-  if (TARGET_64BIT)
-{
-  reg = gen_reg_rtx (DImode);
-  emit_insn (gen_ldfdi2 (reg, operands[1]));
-  emit_insn (gen_floatdidf2 (abs_reg, reg));
-}
-  else
-{
-  reg = gen_reg_rtx (SImode);
-  emit_insn (gen_ldfsi2 (reg, operands[1]));
-  emit_insn (gen_floatsidf2 (abs_reg, reg));
-}
-  break;
-default:
-  gcc_unreachable ();
-}
+   {
+   case SFmode:
+ reg = gen_reg_rtx (SImode);
+ emit_insn (gen_lsfsi2 (reg, operands[1]));
+ emit_insn (gen_floatsisf2 (abs_reg, reg));
+ break;
+   case DFmode:
+ reg = gen_reg_rtx (DImode);
+ emit_insn (gen_ldfdi2 (reg, operands[1]));
+ emit_insn (gen_floatdidf2 (abs_reg, reg));
+ break;
+   default:
+ gcc_unreachable ();
+   }
 
   emit_insn (gen_copysign3 (tmp_reg, abs_reg, operands[1]));

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:af8ad1d874dcfdd12e1c362785fcd8ff653b1244

commit af8ad1d874dcfdd12e1c362785fcd8ff653b1244
Author: Jeff Law 
Date:   Thu May 2 17:13:12 2024 -0600

[committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits

The CI system tripped an execution failure for rv32 with the ceil/round 
patch.

The fundamental problem is the FP->INT step in these sequences requires the
input size to match the output size.  The output size was based on 
rv32/rv64.
Meaning that we'd try to do DF->SI->DF.

That doesn't preserve the semantics we want in at least two ways.

The net is we can't use this trick for DF values on rv32.  While inside the
code I realized we had a similar problem for HF modes.  HF modes we can 
support
only for Zfa.  So I fixed that proactively.

The CI system also pointed out various formatting nits.  I think this fixes 
all
but one overly long line.

Note I could have factored the TARGET_ZFA test.  But I think as-written it's
clearer what the desired cases to transform are.

gcc/
* config/riscv/riscv.md (2): Adjust
condition to match what can be properly implemented.  Fix various
formatting issues.
(lsi2_sext): Fix formatting

(cherry picked from commit 8367c996e55b2c54aeee25e446357a1015a1d11d)

Diff:
---
 gcc/config/riscv/riscv.md | 65 +--
 1 file changed, 34 insertions(+), 31 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b9b0acf92c7..d4676507b45 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2077,8 +2077,8 @@
 (define_insn "lsi2_sext"
   [(set (match_operand:DI   0 "register_operand" "=r")
 (sign_extend:DI (unspec:SI
-[(match_operand:ANYF 1 "register_operand" " f")]
-  ROUND)))]
+[(match_operand:ANYF 1 "register_operand" " f")]
+ ROUND)))]
   "TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)"
   "fcvt.w. %0,%1,"
   [(set_attr "type" "fcvt_f2i")
@@ -2094,13 +2094,25 @@
   [(set_attr "type" "fcvt_f2i")
(set_attr "mode" "")])
 
+;; There are a couple non-obvious restrictions to be aware of.
+;;
+;; We'll do a FP-INT conversion in the sequence.  But we don't
+;; have a .l (64bit) variant of those instructions for rv32.
+;; To preserve proper semantics we must reject DFmode inputs
+;; for rv32 unless Zfa is enabled.
+;;
+;; The ANYF iterator allows HFmode.  We don't have all the
+;; necessary patterns defined for HFmode.  So restrict HFmode
+;; to TARGET_ZFA.
 (define_expand "2"
   [(set (match_operand:ANYF 0 "register_operand" "=f")
-(unspec:ANYF
-[(match_operand:ANYF 1 "register_operand" " f")]
-ROUND))]
-  "TARGET_HARD_FLOAT && (TARGET_ZFA
- || flag_fp_int_builtin_inexact || 
!flag_trapping_math)"
+   (unspec:ANYF
+   [(match_operand:ANYF 1 "register_operand" " f")]
+   ROUND))]
+  "(TARGET_HARD_FLOAT
+&& (TARGET_ZFA || flag_fp_int_builtin_inexact || !flag_trapping_math)
+&& (TARGET_ZFA || TARGET_64BIT || mode != DFmode)
+&& (TARGET_ZFA || mode != HFmode))"
 {
   if (TARGET_ZFA)
 emit_insn (gen__zfa2 (operands[0],
@@ -2116,7 +2128,7 @@
 
   riscv_emit_move (tmp_reg, operands[1]);
   riscv_emit_move (coeff_reg,
-   riscv_vector::get_fp_rounding_coefficient 
(mode));
+  riscv_vector::get_fp_rounding_coefficient 
(mode));
   emit_insn (gen_abs2 (abs_reg, operands[1]));
 
   riscv_expand_conditional_branch (label, LT, abs_reg, coeff_reg);
@@ -2126,29 +2138,20 @@
 
   emit_label (label);
   switch (mode)
-{
-case SFmode:
-  reg = gen_reg_rtx (SImode);
-  emit_insn (gen_lsfsi2 (reg, operands[1]));
-  emit_insn (gen_floatsisf2 (abs_reg, reg));
-  break;
-case DFmode:
-  if (TARGET_64BIT)
-{
-  reg = gen_reg_rtx (DImode);
-  emit_insn (gen_ldfdi2 (reg, operands[1]));
-  emit_insn (gen_floatdidf2 (abs_reg, reg));
-}
-  else
-{
-  reg = gen_reg_rtx (SImode);
-  emit_insn (gen_ldfsi2 (reg, operands[1]));
-  emit_insn (gen_floatsidf2 (abs_reg, reg));
-}
-  break;
-default:
-  gcc_unreachable ();
-}
+   {
+   case SFmode:
+ reg = gen_reg_rtx (SImode);
+ emit_insn (gen_lsfsi2 (reg, operands[1]));
+ emit_insn (gen_floatsisf2 (abs_reg, reg));
+ break;
+   case DFmode:
+ reg = gen_reg_rtx (DImode);
+ emit_insn (gen_ldfdi2 (reg, operands[1]));
+ emit_insn (gen_floatdidf2 (abs_reg, reg));
+ break;
+   default:
+ gcc_unreachable ();
+   }
 
   emit_insn (gen_copysign3 (tm

[gcc r15-122] PR modula2/114929 for loop fails to iterate down to zero when using a cardinal type

[Gaius Mulley via Gcc-cvs]

https://gcc.gnu.org/g:a561dc0f6c7085e102fe9e9b6abd7f2138512576

commit r15-122-ga561dc0f6c7085e102fe9e9b6abd7f2138512576
Author: Gaius Mulley 
Date:   Fri May 3 01:22:10 2024 +0100

PR modula2/114929 for loop fails to iterate down to zero when using a 
cardinal type

There is a bug in the for loop control code which is exposed when an
unsigned type is used in the iterator variable.  See
gm2/pim/run/pass/testforloopzero[234].mod.  The bug is in the
calculation of the last iterator value.  The bug fix is to avoid using
negative expressions when calculating the last iterator value with a
negative step value.  This patch detects if e1, e2, step value are all
constant, in which case the ztype is used internally and there is no
overflow.  If the last iterator value is held in a variable then it
uses a different method to calculate the last iterator depending upon
the sign of the step value.

gcc/m2/ChangeLog:

PR modula2/114929
* gm2-compiler/M2LangDump.mod (GenQualidentSymString): Add
missing return result into identstr.
* gm2-compiler/M2Quads.mod (ForLoopLastIteratorVariable): New
procedure.
(ForLoopLastIteratorConstant): Ditto.
(ForLoopLastIterator): Ditto.
(BuildForToByDo): Remove LastIterator calculation and call
ForLoopLastIterator instead.
(FinalValue): Replace with ...
(LastIterator): ... this.

gcc/testsuite/ChangeLog:

PR modula2/114929
* gm2/pim/run/pass/testforloopzero.mod: New test.
* gm2/pim/run/pass/testforloopzero2.mod: New test.
* gm2/pim/run/pass/testforloopzero3.mod: New test.
* gm2/pim/run/pass/testforloopzero4.mod: New test.

Signed-off-by: Gaius Mulley 

Diff:
---
 gcc/m2/gm2-compiler/M2LangDump.mod |   2 +-
 gcc/m2/gm2-compiler/M2Quads.mod| 191 +
 gcc/testsuite/gm2/pim/run/pass/testforloopzero.mod |  33 
 .../gm2/pim/run/pass/testforloopzero2.mod  |  35 
 .../gm2/pim/run/pass/testforloopzero3.mod  |  32 
 .../gm2/pim/run/pass/testforloopzero4.mod  |  32 
 6 files changed, 290 insertions(+), 35 deletions(-)

diff --git a/gcc/m2/gm2-compiler/M2LangDump.mod 
b/gcc/m2/gm2-compiler/M2LangDump.mod
index e65f5b040a5..2ce77a03d14 100644
--- a/gcc/m2/gm2-compiler/M2LangDump.mod
+++ b/gcc/m2/gm2-compiler/M2LangDump.mod
@@ -260,7 +260,7 @@ BEGIN
WHILE GetScope (sym) # NulSym DO
   sym := GetScope (sym) ;
   identstr := InitStringCharStar (KeyToCharStar (GetSymName (sym))) ;
-  ConCatChar (identstr, '.') ;
+  identstr := ConCatChar (identstr, '.') ;
   qualidentstr := ConCat (identstr, Mark (qualidentstr))
END ;
RETURN qualidentstr
diff --git a/gcc/m2/gm2-compiler/M2Quads.mod b/gcc/m2/gm2-compiler/M2Quads.mod
index 8a9a23013b2..3f414e186b2 100644
--- a/gcc/m2/gm2-compiler/M2Quads.mod
+++ b/gcc/m2/gm2-compiler/M2Quads.mod
@@ -4583,6 +4583,144 @@ BEGIN
 END BuildForLoopToRangeCheck ;
 
 
+(*
+   ForLoopLastIteratorVariable - assigns the last value of the index variable 
to
+ symbol LastIterator.
+ The For Loop is regarded:
+
+ For ident := e1 To e2 By BySym Do
+
+ End
+*)
+
+PROCEDURE ForLoopLastIteratorVariable (LastIterator, e1, e2, BySym, ByType: 
CARDINAL ;
+   e1tok, e2tok, bytok: CARDINAL) ;
+VAR
+   PBType,
+   PositiveBy,
+   ElseQuad,
+   t, f  : CARDINAL ;
+BEGIN
+   Assert (IsVar (LastIterator)) ;
+   (* If By > 0 then.  *)
+   (* q+1 if >=  by0  q+3.  *)
+   (* q+2 GotoOp  q+else.   *)
+   PushTFtok (BySym, ByType, bytok) ;  (* BuildRelOp  1st parameter *)
+   PushT (GreaterEqualTok) ;   (* 2nd parameter *)
+   (* 3rd parameter *)
+   PushZero (bytok, ByType) ;
+   BuildRelOp (e2tok) ;   (* Choose final expression position.  *)
+   PopBool (t, f) ;
+   BackPatch (t, NextQuad) ;
+
+   (* LastIterator := ((e2-e1) DIV By) * By + e1.  *)
+   PushTF (LastIterator, GetSType (LastIterator)) ;
+   PushTFtok (e2, GetSType (e2), e2tok) ;
+   PushT (MinusTok) ;
+   PushTFtok (e1, GetSType (e1), e1tok) ;
+   doBuildBinaryOp (TRUE, FALSE) ;
+   PushT (DivideTok) ;
+   PushTFtok (BySym, ByType, bytok) ;
+   doBuildBinaryOp (FALSE, FALSE) ;
+   PushT (TimesTok) ;
+   PushTFtok (BySym, ByType, bytok) ;
+   doBuildBinaryOp (FALSE, FALSE) ;
+   PushT (ArithPlusTok) ;
+   PushTFtok (e1, GetSType (e1), e1tok) ;
+   doBuildBinaryOp (FALSE, FALSE) ;
+   BuildForLoopToRangeCheck ;
+   BuildAssignmentWithoutBounds (e1tok, FALSE, FALSE) ;
+   GenQuad (GotoOp, NulSym, NulSym, 0) ;
+   ElseQuad := NextQuad-1 ;
+
+   (* Else.  *)
+
+   BackPatch (f, NextQuad) ;
+
+   PushTtok

[gcc r15-123] c++: remove lookup_template_class's entering_scope flag

[Patrick Palka via Gcc-cvs]

https://gcc.gnu.org/g:f04dc89a991ddc6c08ac92c8ad29c6915c4ecafa

commit r15-123-gf04dc89a991ddc6c08ac92c8ad29c6915c4ecafa
Author: Patrick Palka 
Date:   Thu May 2 21:14:30 2024 -0400

c++: remove lookup_template_class's entering_scope flag

lookup_template_class's entering_scope flag controls whether to prefer
returning the primary template type A instead of the corresponding
implicit instantiation A.  When we want to set this flag as part of
substitution, we need to use tsubst_aggr_type which also takes this flag
as a parameter.  But having this separate entry point to type substitution
turned out to be subtly problematic because it doesn't reuse typedefs
like tsubst does, which r13-4729-gbe124477b38a71 fixed in a way that
respects the flag after the fact, by adjusting the entering_scope=false
result of lookup_template_class as if entering_scope=true was passed.

But if that's possible then it means lookup_template_class's
entering_scope flag is not necessary after all -- we can just do the
after-the-fact adjustment everywhere that we currently pass
entering_scope=true to it and tsubst_aggr_type.

To that end, this patch replaces this flag with an adjustment function
adjust_type_for_entering_scope, to be used whereever we currently need
the entering_scope=true behavior.  In turn we can get rid of
tsubst_aggr_type since the only reason we needed this entry point
was to be able to pass entering_scope=true to lookup_template_class.

gcc/cp/ChangeLog:

* coroutines.cc (instantiate_coro_traits): Adjust call to
lookup_template_class.
(instantiate_coro_handle_for_promise_type): Likewise.
* cp-tree.h (adjust_type_for_entering_scope): Declare.
(lookup_template_class): Adjust declaration.
* decl.cc (make_typename_type): Adjust call to
lookup_template_class. Likewise.
(get_tuple_size): Likewise.
(get_tuple_element_type): Likewise.
* pt.cc (adjust_type_for_entering_scope): Define.
(tsubst_entering_scope): Define.
(lookup_template_class): Remove entering_scope parameter.
Replace tsubst_aggr_type call with tsubst_entering_scope.
(tsubst_aggr_type): Remove.
(tsubst_aggr_type_1): Inline into tsubst.
(tsubst_function_decl): Replace tsubst_aggr_type call
with tsubst_entering_scope.
(tsubst_template_decl): Likewise.
(tsubst_decl): Likewise.
(tsubst) :
Inlined from tsubst_aggr_type_1.
: Adjust calls to
lookup_template_class.
: Replace tsubst_aggr_type call with
tsubst_entering_scope.
: Likewise.
Increment processing_template_decl when substituting the
context.
(tsubst_expr) : Replace tsubst_aggr_type
call with tsubst_entering_scope.
: Likewise.
(instantiate_template): Likewise.
(resolve_typename_type): Adjust lookup_template_class call
and call adjust_type_for_entering_scope afterward.
(listify): Adjust lookup_template_class call.
(alias_ctad_tweaks): Likewise.
* semantics.cc (finish_template_type): Adjust lookup_template_class
call and maybe call adjust_type_for_entering_scope afterward.

Reviewed-by: Jason Merrill 

Diff:
---
 gcc/cp/coroutines.cc |   4 +-
 gcc/cp/cp-tree.h |   3 +-
 gcc/cp/decl.cc   |   4 +-
 gcc/cp/pt.cc | 207 ---
 gcc/cp/semantics.cc  |   4 +-
 5 files changed, 88 insertions(+), 134 deletions(-)

diff --git a/gcc/cp/coroutines.cc b/gcc/cp/coroutines.cc
index b05cb9eb330..97bc211ff67 100644
--- a/gcc/cp/coroutines.cc
+++ b/gcc/cp/coroutines.cc
@@ -353,7 +353,7 @@ instantiate_coro_traits (tree fndecl, location_t kw)
   tree traits_class
 = lookup_template_class (coro_traits_templ, targ,
 /*in_decl=*/NULL_TREE, /*context=*/NULL_TREE,
-/*entering scope=*/false, tf_warning_or_error);
+tf_warning_or_error);
 
   if (traits_class == error_mark_node)
 {
@@ -400,7 +400,7 @@ instantiate_coro_handle_for_promise_type (location_t kw, 
tree promise_type)
 = lookup_template_class (coro_handle_identifier, targ,
 /* in_decl=*/NULL_TREE,
 /* context=*/std_node,
-/* entering scope=*/false, tf_warning_or_error);
+tf_warning_or_error);
 
   if (handle_type == error_mark_node)
 {
diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index 933504b4821..1ba7054f8bc 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -7524,8 +7524,9 @@ extern tree push_template_decl(tree, 
bool is_frien

[gcc r15-124] tree-optimization/114921 - _Float16 -> __bf16 isn't noop

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:87e35da16df74cd1c4729a55d94e7bc592487f48

commit r15-124-g87e35da16df74cd1c4729a55d94e7bc592487f48
Author: Richard Biener 
Date:   Thu May 2 13:55:15 2024 +0200

tree-optimization/114921 - _Float16 -> __bf16 isn't noop

The vectorizer handles a _Float16 to __bf16 conversion through
vectorizable_assignment, thinking it's a noop.  The following
fixes this by requiring the same vector component mode when
checking for CONVERT_EXPR_CODE_P, being stricter than for
VIEW_CONVERT_EXPR.

PR tree-optimization/114921
* tree-vect-stmts.cc (vectorizable_assignment): Require
same vector component modes for input and output for
CONVERT_EXPR_CODE_P.

Diff:
---
 gcc/tree-vect-stmts.cc | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index f8d8636b139..7e571968a59 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -5955,14 +5955,17 @@ vectorizable_assignment (vec_info *vinfo,
   if (!vectype_in)
 vectype_in = get_vectype_for_scalar_type (vinfo, TREE_TYPE (op), slp_node);
 
-  /* We can handle NOP_EXPR conversions that do not change the number
- of elements or the vector size.  */
-  if ((CONVERT_EXPR_CODE_P (code)
-   || code == VIEW_CONVERT_EXPR)
-  && (!vectype_in
- || maybe_ne (TYPE_VECTOR_SUBPARTS (vectype_in), nunits)
- || maybe_ne (GET_MODE_SIZE (TYPE_MODE (vectype)),
-  GET_MODE_SIZE (TYPE_MODE (vectype_in)
+  /* We can handle VIEW_CONVERT conversions that do not change the number
+ of elements or the vector size or other conversions when the component
+ mode keeps the same.  */
+  if (!vectype_in
+  || maybe_ne (TYPE_VECTOR_SUBPARTS (vectype_in), nunits)
+  || (code == VIEW_CONVERT_EXPR
+ && maybe_ne (GET_MODE_SIZE (TYPE_MODE (vectype)),
+  GET_MODE_SIZE (TYPE_MODE (vectype_in
+  || (CONVERT_EXPR_CODE_P (code)
+ && (TYPE_MODE (TREE_TYPE (vectype))
+ != TYPE_MODE (TREE_TYPE (vectype_in)
 return false;
 
   if (VECTOR_BOOLEAN_TYPE_P (vectype) != VECTOR_BOOLEAN_TYPE_P (vectype_in))