[gcc r15-717] Use pblendw instead of pand to clear upper 16 bits.
https://gcc.gnu.org/g:0ebaffccb294d90184ad78367de66b6307de3ac0
commit r15-717-g0ebaffccb294d90184ad78367de66b6307de3ac0
Author: liuhongt
Date: Fri Mar 22 14:40:00 2024 +0800
Use pblendw instead of pand to clear upper 16 bits.
For vec_pack_truncv8si/v4si w/o AVX512,
(const_vector:v4si (const_int 0x) x4) is used as mask to clear
upper 16 bits, but vpblendw with zero_vector can also be used, and
zero vector is cheaper than (const_vector:v4si (const_int 0x) x4).
gcc/ChangeLog:
PR target/114427
* config/i386/i386-expand.cc (expand_vec_perm_even_odd_pack):
Use pblendw instead of pand to clear upper bits.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr114427.c: New test.
Diff:
---
gcc/config/i386/i386-expand.cc | 34
gcc/testsuite/gcc.target/i386/pr114427.c | 18 +
2 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 100fb2afb3a..7142c0a9d77 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -22587,6 +22587,7 @@ expand_vec_perm_even_odd_pack (struct expand_vec_perm_d
*d)
{
rtx op, dop0, dop1, t;
unsigned i, odd, c, s, nelt = d->nelt;
+ int pblendw_i = 0;
bool end_perm = false;
machine_mode half_mode;
rtx (*gen_and) (rtx, rtx, rtx);
@@ -22608,6 +22609,7 @@ expand_vec_perm_even_odd_pack (struct expand_vec_perm_d
*d)
gen_and = gen_andv2si3;
gen_pack = gen_mmx_packusdw;
gen_shift = gen_lshrv2si3;
+ pblendw_i = 0x5;
break;
case E_V8HImode:
/* Required for "pack". */
@@ -22619,6 +22621,7 @@ expand_vec_perm_even_odd_pack (struct expand_vec_perm_d
*d)
gen_and = gen_andv4si3;
gen_pack = gen_sse4_1_packusdw;
gen_shift = gen_lshrv4si3;
+ pblendw_i = 0x55;
break;
case E_V8QImode:
/* No check as all instructions are SSE2. */
@@ -22647,6 +22650,7 @@ expand_vec_perm_even_odd_pack (struct expand_vec_perm_d
*d)
gen_and = gen_andv8si3;
gen_pack = gen_avx2_packusdw;
gen_shift = gen_lshrv8si3;
+ pblendw_i = 0x;
end_perm = true;
break;
case E_V32QImode:
@@ -22682,10 +22686,32 @@ expand_vec_perm_even_odd_pack (struct
expand_vec_perm_d *d)
dop1 = gen_reg_rtx (half_mode);
if (odd == 0)
{
- t = gen_const_vec_duplicate (half_mode, GEN_INT (c));
- t = force_reg (half_mode, t);
- emit_insn (gen_and (dop0, t, gen_lowpart (half_mode, d->op0)));
- emit_insn (gen_and (dop1, t, gen_lowpart (half_mode, d->op1)));
+ /* Use pblendw since const_vector 0 should be cheaper than
+const_vector 0x. */
+ if (d->vmode == V4HImode
+ || d->vmode == E_V8HImode
+ || d->vmode == E_V16HImode)
+ {
+ rtx dop0_t = gen_reg_rtx (d->vmode);
+ rtx dop1_t = gen_reg_rtx (d->vmode);
+ t = gen_reg_rtx (d->vmode);
+ emit_move_insn (t, CONST0_RTX (d->vmode));
+
+ emit_move_insn (dop0_t, gen_rtx_VEC_MERGE (d->vmode, d->op0, t,
+GEN_INT (pblendw_i)));
+ emit_move_insn (dop1_t, gen_rtx_VEC_MERGE (d->vmode, d->op1, t,
+GEN_INT (pblendw_i)));
+
+ emit_move_insn (dop0, gen_lowpart (half_mode, dop0_t));
+ emit_move_insn (dop1, gen_lowpart (half_mode, dop1_t));
+ }
+ else
+ {
+ t = gen_const_vec_duplicate (half_mode, GEN_INT (c));
+ t = force_reg (half_mode, t);
+ emit_insn (gen_and (dop0, t, gen_lowpart (half_mode, d->op0)));
+ emit_insn (gen_and (dop1, t, gen_lowpart (half_mode, d->op1)));
+ }
}
else
{
diff --git a/gcc/testsuite/gcc.target/i386/pr114427.c
b/gcc/testsuite/gcc.target/i386/pr114427.c
new file mode 100644
index 000..58b66db7fff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr114427.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64-v3 -O2 -mno-avx512f" } */
+/* { dg-final { scan-assembler-not "vpand" } } */
+/* { dg-final { scan-assembler-not "65535" } } */
+
+void
+foo (int* a, short* __restrict b, int* c)
+{
+for (int i = 0; i != 16; i++)
+ b[i] = c[i] + a[i];
+}
+
+void
+foo1 (int* a, short* __restrict b, int* c)
+{
+for (int i = 0; i != 8; i++)
+ b[i] = c[i] + a[i];
+}
[gcc r15-716] testsuite, rs6000: Make powerpc_altivec consider current_compiler_flags [PR114842]
https://gcc.gnu.org/g:3bb8cdbd60cdb4dab45b97235dc045d6b0a1
commit r15-716-g3bb8cdbd60cdb4dab45b97235dc045d6b0a1
Author: Kewen Lin
Date: Mon May 20 21:01:08 2024 -0500
testsuite, rs6000: Make powerpc_altivec consider current_compiler_flags
[PR114842]
As noted in PR114842, most of the test cases which require
effective target check powerpc_altivec_ok actually care
about if ALTIVEC feature is enabled, and they should adopt
effective target powerpc_altivec instead. By considering
we already have a number of test cases having explicit
-maltivec in dg-options etc., to keep them still be tested
as before even without altivec enabled by default, this
patch makes powerpc_altivec consider current_compiler_flags
like what we do for powerpc_vsx.
PR testsuite/114842
gcc/testsuite/ChangeLog:
* lib/target-supports.exp (check_effective_target_powerpc_altivec):
Take current_compiler_flags into account.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 8689c11214d4..3f0f8532dc36 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7323,7 +7323,7 @@ proc check_effective_target_sparc_vis { } {
#else
int dummy;
#endif
- }]
+ } [current_compiler_flags]]
} else {
return 0
}
[gcc r15-715] testsuite, rs6000: Make powerpc_vsx consider current_compiler_flags [PR114842]
https://gcc.gnu.org/g:95080f2a40c5dfc098b75029c30380ecf03875dc
commit r15-715-g95080f2a40c5dfc098b75029c30380ecf03875dc
Author: Kewen Lin
Date: Mon May 20 21:01:08 2024 -0500
testsuite, rs6000: Make powerpc_vsx consider current_compiler_flags
[PR114842]
As noted in PR114842, most of the test cases which require
effective target check powerpc_vsx_ok actually care about
if VSX feature is enabled, and they should adopt effective
target powerpc_vsx instead. By considering we already have
a number of test cases having explicit -mvsx in dg-options
etc., to keep them still be tested as before even without
vsx enabled by default, this patch is to make powerpc_vsx
consider current_compiler_flags.
PR testsuite/114842
gcc/testsuite/ChangeLog:
* lib/target-supports.exp (check_effective_target_powerpc_vsx): Take
current_compiler_flags into account.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index cf5512074ad5..8689c11214d4 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7140,7 +7140,7 @@ proc check_effective_target_powerpc_vsx { } {
nope no vsx
#endif
}
-}]
+} [current_compiler_flags]]
}
# Return 1 if this is a PowerPC target supporting -mvsx
[gcc r15-714] testsuite, rs6000: Remove effective target powerpc_405_nocache
https://gcc.gnu.org/g:7a9a6091b81d8579ab0470e4e21b5682d4ee4ef4
commit r15-714-g7a9a6091b81d8579ab0470e4e21b5682d4ee4ef4
Author: Kewen Lin
Date: Mon May 20 21:01:08 2024 -0500
testsuite, rs6000: Remove effective target powerpc_405_nocache
With the introduction of -mdejagnu-cpu=, when the test case
is specifying -mdejagnu-cpu=405, it would override the other
possibly given -mcpu=, so it would compile for PowerPC 405
for sure. This patch is to remove the effective target
powerpc_405_nocache and update all its uses.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/405-dlmzb-strlen-1.c: Remove the line using
powerpc_405_nocache check.
* gcc.target/powerpc/405-macchw-1.c: Likewise.
* gcc.target/powerpc/405-macchw-2.c: Likewise.
* gcc.target/powerpc/405-macchwu-1.c: Likewise.
* gcc.target/powerpc/405-macchwu-2.c: Likewise.
* gcc.target/powerpc/405-machhw-1.c: Likewise.
* gcc.target/powerpc/405-machhw-2.c: Likewise.
* gcc.target/powerpc/405-machhwu-1.c: Likewise.
* gcc.target/powerpc/405-machhwu-2.c: Likewise.
* gcc.target/powerpc/405-maclhw-1.c: Likewise.
* gcc.target/powerpc/405-maclhw-2.c: Likewise.
* gcc.target/powerpc/405-maclhwu-1.c: Likewise.
* gcc.target/powerpc/405-maclhwu-2.c: Likewise.
* gcc.target/powerpc/405-mulchw-1.c: Likewise.
* gcc.target/powerpc/405-mulchw-2.c: Likewise.
* gcc.target/powerpc/405-mulchwu-1.c: Likewise.
* gcc.target/powerpc/405-mulchwu-2.c: Likewise.
* gcc.target/powerpc/405-mulhhw-1.c: Likewise.
* gcc.target/powerpc/405-mulhhw-2.c: Likewise.
* gcc.target/powerpc/405-mulhhwu-1.c: Likewise.
* gcc.target/powerpc/405-mulhhwu-2.c: Likewise.
* gcc.target/powerpc/405-mullhw-1.c: Likewise.
* gcc.target/powerpc/405-mullhw-2.c: Likewise.
* gcc.target/powerpc/405-mullhwu-1.c: Likewise.
* gcc.target/powerpc/405-mullhwu-2.c: Likewise.
* gcc.target/powerpc/405-nmacchw-1.c: Likewise.
* gcc.target/powerpc/405-nmacchw-2.c: Likewise.
* gcc.target/powerpc/405-nmachhw-1.c: Likewise.
* gcc.target/powerpc/405-nmachhw-2.c: Likewise.
* gcc.target/powerpc/405-nmaclhw-1.c: Likewise.
* gcc.target/powerpc/405-nmaclhw-2.c: Likewise.
* lib/target-supports.exp
(check_effective_target_powerpc_405_nocache): Remove.
Diff:
---
gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-macchw-1.c | 6 +-
gcc/testsuite/gcc.target/powerpc/405-macchw-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-machhw-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-machhw-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c | 1 -
gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c | 1 -
gcc/testsuite/lib/target-supports.exp | 17 -
32 files changed, 5 insertions(+), 48 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c
b/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c
index 5ee427a3b4a9..984ffe7144c4 100644
--- a/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c
@@ -4,7 +4,6 @@
/* { dg-skip-if "" { powerpc*
[gcc r15-710] testsuite, rs6000: Remove all linux*paired* checks and cases
https://gcc.gnu.org/g:458b23bc8b3e2b11a6ea19c69f42ba85abb7d0fe
commit r15-710-g458b23bc8b3e2b11a6ea19c69f42ba85abb7d0fe
Author: Kewen Lin
Date: Mon May 20 21:01:07 2024 -0500
testsuite, rs6000: Remove all linux*paired* checks and cases
Since r9-115-g559289370f76bf the support of paired single
had been dropped, but we still have some test checks and
cases for that, this patch is to get rid of them.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp (check_effective_target_vect_int): Remove
the check on powerpc-*-linux*paired*.
(check_effective_target_vect_intfloat_cvt): Likewise.
(check_effective_target_vect_uintfloat_cvt): Likewise.
(check_effective_target_vect_floatint_cvt): Likewise.
(check_effective_target_vect_floatuint_cvt): Likewise.
(check_effective_target_powerpc_altivec_ok): Likewise.
(check_effective_target_powerpc_p9modulo_ok): Likewise.
(check_effective_target_powerpc_float128_sw_ok): Likewise.
(check_effective_target_powerpc_float128_hw_ok): Likewise.
(check_effective_target_powerpc_vsx_ok): Likewise.
(check_effective_target_powerpc_htm_ok): Likewise.
(check_effective_target_vect_shift): Likewise.
(check_effective_target_vect_char_add): Likewise.
(check_effective_target_vect_shift_char): Likewise.
(check_effective_target_vect_long): Likewise.
(check_effective_target_ifn_copysign): Likewise.
(check_effective_target_vect_sdot_hi): Likewise.
(check_effective_target_vect_udot_hi): Likewise.
(check_effective_target_vect_pack_trunc): Likewise.
(check_effective_target_vect_int_mult): Likewise.
* gcc.target/powerpc/paired-1.c: Remove.
* gcc.target/powerpc/paired-10.c: Remove.
* gcc.target/powerpc/paired-2.c: Remove.
* gcc.target/powerpc/paired-3.c: Remove.
* gcc.target/powerpc/paired-4.c: Remove.
* gcc.target/powerpc/paired-5.c: Remove.
* gcc.target/powerpc/paired-6.c: Remove.
* gcc.target/powerpc/paired-7.c: Remove.
* gcc.target/powerpc/paired-8.c: Remove.
* gcc.target/powerpc/paired-9.c: Remove.
* gcc.target/powerpc/ppc-paired.c: Remove.
Diff:
---
gcc/testsuite/gcc.target/powerpc/paired-1.c | 33 ---
gcc/testsuite/gcc.target/powerpc/paired-10.c | 25
gcc/testsuite/gcc.target/powerpc/paired-2.c | 35
gcc/testsuite/gcc.target/powerpc/paired-3.c | 34 ---
gcc/testsuite/gcc.target/powerpc/paired-4.c | 34 ---
gcc/testsuite/gcc.target/powerpc/paired-5.c | 34 ---
gcc/testsuite/gcc.target/powerpc/paired-6.c | 34 ---
gcc/testsuite/gcc.target/powerpc/paired-7.c | 34 ---
gcc/testsuite/gcc.target/powerpc/paired-8.c | 25
gcc/testsuite/gcc.target/powerpc/paired-9.c | 25
gcc/testsuite/gcc.target/powerpc/ppc-paired.c | 45
gcc/testsuite/lib/target-supports.exp | 59 +--
12 files changed, 20 insertions(+), 397 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/paired-1.c
b/gcc/testsuite/gcc.target/powerpc/paired-1.c
deleted file mode 100644
index 19a66a15b30b..
--- a/gcc/testsuite/gcc.target/powerpc/paired-1.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32} } } */
-/* { dg-options "-mpaired -ffinite-math-only " } */
-
-/* Test PowerPC PAIRED extensions. */
-
-#include
-
-static float in1[2] __attribute__ ((aligned (8))) =
-{6.0, 7.0};
-static float in2[2] __attribute__ ((aligned (8))) =
-{4.0, 3.0};
-
-static float out[2] __attribute__ ((aligned (8)));
-
-vector float a, b, c, d;
-void
-test_api ()
-{
- b = paired_lx (0, in1);
- c = paired_lx (0, in2);
-
- a = paired_sub (b, c);
-
- paired_stx (a, 0, out);
-}
-
-int
-main ()
-{
- test_api ();
- return (0);
-}
-
diff --git a/gcc/testsuite/gcc.target/powerpc/paired-10.c
b/gcc/testsuite/gcc.target/powerpc/paired-10.c
deleted file mode 100644
index 1f904c258413..
--- a/gcc/testsuite/gcc.target/powerpc/paired-10.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */
-/* { dg-options "-mpaired -ffinite-math-only " } */
-
-/* Test PowerPC PAIRED extensions. */
-
-#include
-
-static float out[2] __attribute__ ((aligned (8)));
-void
-test_api (float y, float x)
-{
- vector float c = {x, y};
- vector float b = {0.0, 8.0};
- vector float a;
-
- a = paired_sub (b, c);
- paired_stx (a, 0, out);
-}
-
-
-int main ()
-{
- test_api (6, 7);
- return (0);
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/paired-2.c
b/gcc/testsuite/gcc.target/powerpc/paired-2.c
deleted file mode 100644
index 181bbf1c39cd..000
[gcc r15-713] libgcc, rs6000: Remove powerpcspe related code
https://gcc.gnu.org/g:5d1d2e955d1379da77b000f6445c208ff25cd137
commit r15-713-g5d1d2e955d1379da77b000f6445c208ff25cd137
Author: Kewen Lin
Date: Mon May 20 21:01:08 2024 -0500
libgcc, rs6000: Remove powerpcspe related code
Since r9-4728 the powerpcspe support had been removed, this
follow-up patch is to remove the remaining pieces in libgcc.
libgcc/ChangeLog:
* config.host: Remove powerpc-*-eabispe* support.
* config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Remove
__SPE__ code.
* config/rs6000/t-savresfgpr (LIB2ADD_ST): Remove e500crtres32gpr.S,
e500crtres32gpr.S, e500crtsav64gpr.S, e500crtsav64gprctr.S,
e500crtres64gpr.S, e500crtsav32gpr.S, e500crtsavg32gpr.S,
e500crtres64gprctr.S, e500crtsavg64gprctr.S, e500crtresx32gpr.S,
e500crtrest32gpr.S, e500crtrest64gpr.S and e500crtresx64gpr.S.
* config/rs6000/e500crtres32gpr.S: Remove.
* config/rs6000/e500crtres64gpr.S: Remove.
* config/rs6000/e500crtres64gprctr.S: Remove.
* config/rs6000/e500crtrest32gpr.S: Remove.
* config/rs6000/e500crtrest64gpr.S: Remove.
* config/rs6000/e500crtresx32gpr.S: Remove.
* config/rs6000/e500crtresx64gpr.S: Remove.
* config/rs6000/e500crtsav32gpr.S: Remove.
* config/rs6000/e500crtsav64gpr.S: Remove.
* config/rs6000/e500crtsav64gprctr.S: Remove.
* config/rs6000/e500crtsavg32gpr.S: Remove.
* config/rs6000/e500crtsavg64gpr.S: Remove.
* config/rs6000/e500crtsavg64gprctr.S: Remove.
Diff:
---
libgcc/config.host | 4 --
libgcc/config/rs6000/e500crtres32gpr.S | 73
libgcc/config/rs6000/e500crtres64gpr.S | 73
libgcc/config/rs6000/e500crtres64gprctr.S | 90 -
libgcc/config/rs6000/e500crtrest32gpr.S| 75
libgcc/config/rs6000/e500crtrest64gpr.S| 74
libgcc/config/rs6000/e500crtresx32gpr.S| 75
libgcc/config/rs6000/e500crtresx64gpr.S| 75
libgcc/config/rs6000/e500crtsav32gpr.S | 73
libgcc/config/rs6000/e500crtsav64gpr.S | 72 ---
libgcc/config/rs6000/e500crtsav64gprctr.S | 91 --
libgcc/config/rs6000/e500crtsavg32gpr.S| 73
libgcc/config/rs6000/e500crtsavg64gpr.S| 73
libgcc/config/rs6000/e500crtsavg64gprctr.S | 90 -
libgcc/config/rs6000/linux-unwind.h| 11
libgcc/config/rs6000/t-savresfgpr | 15 +
16 files changed, 1 insertion(+), 1036 deletions(-)
diff --git a/libgcc/config.host b/libgcc/config.host
index 694602d31859..9fae51d4ce7d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1238,10 +1238,6 @@ powerpc*-*-freebsd*)
powerpc-*-netbsd*)
tmake_file="$tmake_file rs6000/t-netbsd rs6000/t-crtstuff"
;;
-powerpc-*-eabispe*)
- tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-savresfgpr
rs6000/t-crtstuff t-crtstuff-pic t-fdpbit"
- extra_parts="$extra_parts crtbegin.o crtend.o crtbeginS.o crtendS.o
crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o"
- ;;
powerpc-*-eabisimaltivec*)
tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-crtstuff
t-crtstuff-pic t-fdpbit"
extra_parts="$extra_parts crtbegin.o crtend.o crtbeginS.o crtendS.o
crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/config/rs6000/e500crtres32gpr.S
b/libgcc/config/rs6000/e500crtres32gpr.S
deleted file mode 100644
index b19703073cad..
--- a/libgcc/config/rs6000/e500crtres32gpr.S
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Special support for e500 eabi and SVR4
- *
- * Copyright (C) 2008-2024 Free Software Foundation, Inc.
- * Written by Nathan Froyd
- *
- * This file is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 3, or (at your option) any
- * later version.
- *
- * This file is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * Under Section 7 of GPL version 3, you are granted additional
- * permissions described in the GCC Runtime Library Exception, version
- * 3.1, as published by the Free Software Foundation.
- *
- * You should have received a copy of the GNU General Public License and
- * a copy of the GCC Runtime Library Exception along with this program;
- * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
- *
[gcc r15-711] testsuite, rs6000: Remove powerpc_popcntb_ok
https://gcc.gnu.org/g:f4598e71cf28478ecad2bc6a47f500e30bd65eb6
commit r15-711-gf4598e71cf28478ecad2bc6a47f500e30bd65eb6
Author: Kewen Lin
Date: Mon May 20 21:01:07 2024 -0500
testsuite, rs6000: Remove powerpc_popcntb_ok
There are three uses of effective target powerpc_popcntb_ok,
they are all for compiling, but powerpc_popcntb_ok checks
for executable generation, which is too heavy. This patch
is to remove powerpc_popcntb_ok and adjust its three uses
accordingly.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp
(check_effective_target_powerpc_popcntb_ok):
Remove.
* gcc.target/powerpc/cmpb-2.c: Adjust with dg-skip-if as
powerpc_popcntb_ok gets removed.
* gcc.target/powerpc/cmpb-3.c: Likewise.
* gcc.target/powerpc/cmpb32-2.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/cmpb-2.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/cmpb-3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/cmpb32-2.c | 3 ++-
gcc/testsuite/lib/target-supports.exp | 20
4 files changed, 6 insertions(+), 23 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c
b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c
index 02b84d0731d5..44a554bee4a2 100644
--- a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
+/* Skip powerpc*-*-darwin* powerpc-*-eabi as dropped popcntb_ok. */
+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-*-eabi } } */
/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target powerpc_popcntb_ok } */
/* { dg-options "-mdejagnu-cpu=power5" } */
void abort ();
diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb-3.c
b/gcc/testsuite/gcc.target/powerpc/cmpb-3.c
index 75641bdb22cc..43de37a571d5 100644
--- a/gcc/testsuite/gcc.target/powerpc/cmpb-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/cmpb-3.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
+/* Skip powerpc*-*-darwin* powerpc-*-eabi as dropped popcntb_ok. */
+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-*-eabi } } */
/* { dg-require-effective-target ilp32 } */
-/* { dg-require-effective-target powerpc_popcntb_ok } */
/* { dg-options "-mdejagnu-cpu=power6" } */
void abort ();
diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c
b/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c
index d4264ab6e7d3..0713c44fcff2 100644
--- a/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c
@@ -1,5 +1,6 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target powerpc_popcntb_ok } */
+/* Skip powerpc*-*-darwin* powerpc-*-eabi as dropped popcntb_ok. */
+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-*-eabi } } */
/* { dg-options "-mdejagnu-cpu=power5" } */
void abort ();
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 82dea149c257..34027b64e520 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3946,26 +3946,6 @@ proc check_effective_target_unsigned_char {} {
}]
}
-proc check_effective_target_powerpc_popcntb_ok { } {
-return [check_cached_effective_target powerpc_popcntb_ok {
-
- # Disable on Darwin.
- if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] ||
[istarget *-*-darwin*]} {
- expr 0
- } else {
- check_runtime_nocache powerpc_popcntb_ok {
- volatile int r;
- volatile int a = 0x12345678;
- int main()
- {
- asm volatile ("popcntb %0,%1" : "=r" (r) : "r" (a));
- return 0;
- }
- } "-mcpu=power5"
- }
-}]
-}
-
# Return 1 if the target supports executing DFP hardware instructions,
# 0 otherwise. Cache the result.
[gcc r15-712] testsuite, rs6000: Remove powerpcspe test cases and checks
https://gcc.gnu.org/g:7fa32ad7a4afc7dc93a0c50204fe0b5c00ac4865
commit r15-712-g7fa32ad7a4afc7dc93a0c50204fe0b5c00ac4865
Author: Kewen Lin
Date: Mon May 20 21:01:08 2024 -0500
testsuite, rs6000: Remove powerpcspe test cases and checks
Since r9-4728 the powerpcspe support had been removed, this
follow-up patch is to remove the remaining pieces in testsuite.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp
(check_effective_target_vect_cmdline_needed): Remove
check_effective_target_powerpc_spe.
(check_effective_target_powerpc_spe_nocache): Remove.
(check_effective_target_powerpc_spe): Remove.
(check_ppc_cpu_supports_hw_available): Remove powerpc*-*-eabispe
check.
(check_p8vector_hw_available): Likewise.
(check_p9vector_hw_available): Likewise.
(check_p9modulo_hw_available): Likewise.
(check_ppc_float128_sw_available): Likewise.
(check_ppc_float128_hw_available): Likewise.
(check_vsx_hw_available): Likewise.
(check_vmx_hw_available): Likewise.
(check_ppc_recip_hw_available): Likewise.
(check_dfp_hw_available): Likewise.
(check_htm_hw_available): Likewise.
* g++.dg/ext/spe1.C: Remove.
* g++.dg/other/opaque-1.C: Remove.
* g++.dg/other/opaque-2.C: Remove.
* g++.dg/other/opaque-3.C: Remove.
* g++.target/powerpc/simd-5.C: Remove.
Diff:
---
gcc/testsuite/g++.dg/ext/spe1.C | 10 --
gcc/testsuite/g++.dg/other/opaque-1.C | 31 ---
gcc/testsuite/g++.dg/other/opaque-2.C | 19
gcc/testsuite/g++.dg/other/opaque-3.C | 12
gcc/testsuite/g++.target/powerpc/simd-5.C | 44 --
gcc/testsuite/lib/target-supports.exp | 51 +++
6 files changed, 5 insertions(+), 162 deletions(-)
diff --git a/gcc/testsuite/g++.dg/ext/spe1.C b/gcc/testsuite/g++.dg/ext/spe1.C
deleted file mode 100644
index b98d4b27b3d7..
--- a/gcc/testsuite/g++.dg/ext/spe1.C
+++ /dev/null
@@ -1,10 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */
-/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */
-
-typedef int v2si __attribute__ ((vector_size (8)));
-
-/* The two specializations must be considered different. */
-template class X { };
-template <>class X<__ev64_opaque__> { };
-template <>class X { };
diff --git a/gcc/testsuite/g++.dg/other/opaque-1.C
b/gcc/testsuite/g++.dg/other/opaque-1.C
deleted file mode 100644
index 669776b9f976..
--- a/gcc/testsuite/g++.dg/other/opaque-1.C
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-do run } */
-/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
-/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */
-
-#define __vector __attribute__((vector_size(8)))
-typedef float __vector __ev64_fs__;
-
-__ev64_fs__ f;
-__ev64_opaque__ o;
-
-int here = 0;
-
-void bar (__ev64_opaque__ x)
-{
- here = 0;
-}
-
-void bar (__ev64_fs__ x)
-{
- here = 888;
-}
-
-int main ()
-{
- f = o;
- o = f;
- bar (f);
- if (here != 888)
-return 1;
- return 0;
-}
diff --git a/gcc/testsuite/g++.dg/other/opaque-2.C
b/gcc/testsuite/g++.dg/other/opaque-2.C
deleted file mode 100644
index 414f87e6c9a0..
--- a/gcc/testsuite/g++.dg/other/opaque-2.C
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
-/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */
-
-#define __vector __attribute__((vector_size(8)))
-typedef float __vector __ev64_fs__;
-
-__ev64_fs__ f;
-__ev64_opaque__ o;
-
-extern void bar (__ev64_opaque__);
-
-int main ()
-{
- f = o;
- o = f;
- bar (f);
- return 0;
-}
diff --git a/gcc/testsuite/g++.dg/other/opaque-3.C
b/gcc/testsuite/g++.dg/other/opaque-3.C
deleted file mode 100644
index f915f840510c..
--- a/gcc/testsuite/g++.dg/other/opaque-3.C
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
-/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */
-
-__ev64_opaque__ o;
-#define v __attribute__((vector_size(8)))
-v unsigned int *p;
-
-void m()
-{
- o = __builtin_spe_evldd(p, 5);
-}
diff --git a/gcc/testsuite/g++.target/powerpc/simd-5.C
b/gcc/testsuite/g++.target/powerpc/simd-5.C
deleted file mode 100644
index 71e117ead2aa..
--- a/gcc/testsuite/g++.target/powerpc/simd-5.C
+++ /dev/null
@@ -1,44 +0,0 @@
-// Test EH with V2SI SIMD registers actually restores correct values.
-// Origin: Joseph Myers
-// { dg-options "-O" }
-// { dg-do run { target { powerpc_spe && { ! *-*-vxworks* } } } }
-
-extern "C" void abort (void);
-extern "C" int memcmp (const void *, const voi
[gcc r15-709] testsuite, rs6000: Remove some checks with aix[456]
https://gcc.gnu.org/g:fa8250630dcd5ab50e2e957747d817cae4403c82
commit r15-709-gfa8250630dcd5ab50e2e957747d817cae4403c82
Author: Kewen Lin
Date: Mon May 20 21:01:07 2024 -0500
testsuite, rs6000: Remove some checks with aix[456]
Since r12-75-g0745b6fa66c69c aix6 support had been dropped,
so we don't need to check for aix[456].* when testing, this
patch is to remove such checks.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp
(check_effective_target_powerpc_altivec_ok): Remove checks for
aix[456].*
(check_effective_target_powerpc_p9modulo_ok): Likewise.
(check_effective_target_powerpc_float128_sw_ok): Likewise.
(check_effective_target_powerpc_float128_hw_ok): Likewise.
(check_effective_target_powerpc_vsx_ok): Likewise.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 29 -
1 file changed, 29 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ec9baa4f32a3..d38c16354ff0 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -6959,11 +6959,6 @@ proc check_effective_target_powerpc_altivec_ok { } {
# Paired Single, then not ok
if { [istarget powerpc-*-linux*paired*] } { return 0 }
-# AltiVec is not supported on AIX before 5.3.
-if { [istarget powerpc*-*-aix4*]
-|| [istarget powerpc*-*-aix5.1*]
-|| [istarget powerpc*-*-aix5.2*] } { return 0 }
-
# Return true iff compiling with -maltivec does not error.
return [check_no_compiler_messages powerpc_altivec_ok object {
int dummy;
@@ -6976,12 +6971,6 @@ proc check_effective_target_powerpc_p9modulo_ok { } {
if { ([istarget powerpc*-*-*]
&& ![istarget powerpc-*-linux*paired*])
|| [istarget rs6000-*-*] } {
- # AltiVec is not supported on AIX before 5.3.
- if { [istarget powerpc*-*-aix4*]
-|| [istarget powerpc*-*-aix5.1*]
-|| [istarget powerpc*-*-aix5.2*] } {
- return 0
- }
return [check_no_compiler_messages powerpc_p9modulo_ok object {
int main (void) {
int i = 5, j = 3, r = -1;
@@ -7112,12 +7101,6 @@ proc check_effective_target_powerpc_float128_sw_ok { } {
if { ([istarget powerpc*-*-*]
&& ![istarget powerpc-*-linux*paired*])
|| [istarget rs6000-*-*] } {
- # AltiVec is not supported on AIX before 5.3.
- if { [istarget powerpc*-*-aix4*]
-|| [istarget powerpc*-*-aix5.1*]
-|| [istarget powerpc*-*-aix5.2*] } {
- return 0
- }
# Darwin doesn't have VSX, so no soft support for float128.
if { [istarget *-*-darwin*] } {
return 0
@@ -7142,12 +7125,6 @@ proc check_effective_target_powerpc_float128_hw_ok { } {
if { ([istarget powerpc*-*-*]
&& ![istarget powerpc-*-linux*paired*])
|| [istarget rs6000-*-*] } {
- # AltiVec is not supported on AIX before 5.3.
- if { [istarget powerpc*-*-aix4*]
-|| [istarget powerpc*-*-aix5.1*]
-|| [istarget powerpc*-*-aix5.2*] } {
- return 0
- }
# Darwin doesn't run on any machine with float128 h/w so far.
if { [istarget *-*-darwin*] } {
return 0
@@ -7211,12 +7188,6 @@ proc check_effective_target_powerpc_vsx_ok { } {
if { ([istarget powerpc*-*-*]
&& ![istarget powerpc-*-linux*paired*])
|| [istarget rs6000-*-*] } {
- # VSX is not supported on AIX before 7.1.
- if { [istarget powerpc*-*-aix4*]
-|| [istarget powerpc*-*-aix5*]
-|| [istarget powerpc*-*-aix6*] } {
- return 0
- }
# Darwin doesn't have VSX, even if it's used with an assembler
# which recognises the insns.
if { [istarget *-*-darwin*] } {
[gcc r15-707] rs6000: Remove useless operands[3]
https://gcc.gnu.org/g:1a87deddf470c728e85cc9ca802b51ed2b1efbd6 commit r15-707-g1a87deddf470c728e85cc9ca802b51ed2b1efbd6 Author: Kewen Lin Date: Mon May 20 21:01:07 2024 -0500 rs6000: Remove useless operands[3] As shown, three uses of operands[3] are totally useless, so this patch is to remove them to avoid any confusion. gcc/ChangeLog: * config/rs6000/rs6000.md (@ieee_128bit_vsx_neg2): Remove the use of operands[3]. (@ieee_128bit_vsx_neg2): Likewise. (*ieee_128bit_vsx_nabs2): Likewise. Diff: --- gcc/config/rs6000/rs6000.md | 3 --- 1 file changed, 3 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7d0019ab410a..f035e68ff0f8 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -9260,7 +9260,6 @@ if (GET_CODE (operands[2]) == SCRATCH) operands[2] = gen_reg_rtx (V16QImode); - operands[3] = gen_reg_rtx (V16QImode); emit_insn (gen_ieee_128bit_negative_zero (operands[2])); } [(set_attr "length" "8") @@ -9289,7 +9288,6 @@ if (GET_CODE (operands[2]) == SCRATCH) operands[2] = gen_reg_rtx (V16QImode); - operands[3] = gen_reg_rtx (V16QImode); emit_insn (gen_ieee_128bit_negative_zero (operands[2])); } [(set_attr "length" "8") @@ -9321,7 +9319,6 @@ if (GET_CODE (operands[2]) == SCRATCH) operands[2] = gen_reg_rtx (V16QImode); - operands[3] = gen_reg_rtx (V16QImode); emit_insn (gen_ieee_128bit_negative_zero (operands[2])); } [(set_attr "length" "8")
[gcc r15-708] testsuite: Fix typo in torture/vector-{1,2}.c
https://gcc.gnu.org/g:f672ab0ae1f4c00276125b9ff49884886834f5c3
commit r15-708-gf672ab0ae1f4c00276125b9ff49884886834f5c3
Author: Kewen Lin
Date: Mon May 20 21:01:07 2024 -0500
testsuite: Fix typo in torture/vector-{1,2}.c
When making some clean up patches, I happened to find test
cases vector-{1,2}.c are having typo "powerpc64--*-*" in
target selector, which should be powerpc64-*-*. The reason
why we didn't catch before is that all our testing machines
support VMX insns, so it passes always. But it would break
if a test machine doesn't support that, so this patch is to
fix it to ensure robustness.
gcc/testsuite/ChangeLog:
* gcc.dg/torture/vector-1.c: Fix typo.
* gcc.dg/torture/vector-2.c: Likewise.
Diff:
---
gcc/testsuite/gcc.dg/torture/vector-1.c | 2 +-
gcc/testsuite/gcc.dg/torture/vector-2.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/torture/vector-1.c
b/gcc/testsuite/gcc.dg/torture/vector-1.c
index 205fee6d6de9..1b98ee26ff3c 100644
--- a/gcc/testsuite/gcc.dg/torture/vector-1.c
+++ b/gcc/testsuite/gcc.dg/torture/vector-1.c
@@ -4,7 +4,7 @@
/* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */
/* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* }
} } */
/* { dg-options "-mabi=altivec" { target { powerpc-*-* powerpc64-*-* } } } */
-/* { dg-require-effective-target vmx_hw { target { powerpc-*-* powerpc64--*-*
} } } */
+/* { dg-require-effective-target vmx_hw { target { powerpc-*-* powerpc64-*-* }
} } */
#define vector __attribute__((vector_size(16) ))
diff --git a/gcc/testsuite/gcc.dg/torture/vector-2.c
b/gcc/testsuite/gcc.dg/torture/vector-2.c
index b004d0057754..c9a3a44d4dff 100644
--- a/gcc/testsuite/gcc.dg/torture/vector-2.c
+++ b/gcc/testsuite/gcc.dg/torture/vector-2.c
@@ -4,7 +4,7 @@
/* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */
/* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* }
} } */
/* { dg-options "-mabi=altivec" { target { powerpc-*-* powerpc64-*-* } } } */
-/* { dg-require-effective-target vmx_hw { target { powerpc-*-* powerpc64--*-*
} } } */
+/* { dg-require-effective-target vmx_hw { target { powerpc-*-* powerpc64-*-* }
} } */
#define vector __attribute__((vector_size(16) ))
[gcc r15-706] rs6000: Remove useless entries in rreg
https://gcc.gnu.org/g:2cd8dfd7d599ad6205e40c4e57275ce6ebd073aa commit r15-706-g2cd8dfd7d599ad6205e40c4e57275ce6ebd073aa Author: Kewen Lin Date: Mon May 20 21:01:07 2024 -0500 rs6000: Remove useless entries in rreg When I was working on a trial patch to get rid of TFmode, I noticed that mode attribute rreg only gets used for mode iterator SFDF, it means that only SF and DF key-value pairs are useful, the other are useless, so this patch is to clean up them. gcc/ChangeLog: * config/rs6000/rs6000.md (mode attribute rreg): Remove useless entries with modes TF, TD, V4SF and V2DF. Diff: --- gcc/config/rs6000/rs6000.md | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ac5651d7420c..7d0019ab410a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -729,11 +729,7 @@ (DI "Y")]) (define_mode_attr rreg [(SF "f") - (DF "wa") - (TF "f") - (TD "f") - (V4SF "wa") - (V2DF "wa")]) + (DF "wa")]) (define_mode_attr rreg2 [(SF "f") (DF "d")])
[gcc r15-705] rs6000: Drop useless vector_{load, store}_ defines
https://gcc.gnu.org/g:a6f8b2b63391ff14c2bf6e1b75abd99546dfbfb8
commit r15-705-ga6f8b2b63391ff14c2bf6e1b75abd99546dfbfb8
Author: Kewen Lin
Date: Mon May 20 21:01:06 2024 -0500
rs6000: Drop useless vector_{load,store}_ defines
When I was working on a patch to get rid of TFmode, I
noticed that define_expands vector_load_ and
vector_store_ are useless. This patch is to clean up
both.
gcc/ChangeLog:
* config/rs6000/vector.md (define_expand vector_load_):
Remove.
(vector_store_): Likewise.
Diff:
---
gcc/config/rs6000/vector.md | 14 --
1 file changed, 14 deletions(-)
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index f9796fb3781b..59489e068399 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -163,20 +163,6 @@
}
})
-;; Generic vector floating point load/store instructions. These will match
-;; insns defined in vsx.md or altivec.md depending on the switches.
-(define_expand "vector_load_"
- [(set (match_operand:VEC_M 0 "vfloat_operand")
- (match_operand:VEC_M 1 "memory_operand"))]
- "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
- "")
-
-(define_expand "vector_store_"
- [(set (match_operand:VEC_M 0 "memory_operand")
- (match_operand:VEC_M 1 "vfloat_operand"))]
- "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
- "")
-
;; Splits if a GPR register was chosen for the move
(define_split
[(set (match_operand:VEC_L 0 "nonimmediate_operand")
[gcc r15-704] rs6000: Clean up TF and TD check with FLOAT128_2REG_P
https://gcc.gnu.org/g:2eb1dff8b34a8a7da02b988878172d1b8f203d96
commit r15-704-g2eb1dff8b34a8a7da02b988878172d1b8f203d96
Author: Kewen Lin
Date: Mon May 20 21:01:06 2024 -0500
rs6000: Clean up TF and TD check with FLOAT128_2REG_P
Commit r6-2116-g2c83faf86827bf did some clean up on TFmode
and TFmode check with FLOAT128_2REG_P, but it missed to
update an assertion, this patch is to make it align.
btw, it's noticed when I'm making a patch to get rid of
TFmode.
gcc/ChangeLog:
* config/rs6000/rs6000-call.cc (rs6000_darwin64_record_arg_recurse):
Clean up TFmode and TDmode check with FLOAT128_2REG_P.
Diff:
---
gcc/config/rs6000/rs6000-call.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc
index 1f8f93a2ee78..a039ff75f3c9 100644
--- a/gcc/config/rs6000/rs6000-call.cc
+++ b/gcc/config/rs6000/rs6000-call.cc
@@ -1391,7 +1391,7 @@ rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum,
const_tree type,
if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
{
gcc_assert (cum->fregno == FP_ARG_MAX_REG
- && (mode == TFmode || mode == TDmode));
+ && FLOAT128_2REG_P (mode));
/* Long double or _Decimal128 split over regs and memory. */
mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
cum->use_stack=1;
[gcc r15-703] rs6000: Add assert !TARGET_VSX if !TARGET_ALTIVEC and strip a useless check
https://gcc.gnu.org/g:b390b0115696353ba579706531fbd3bcf39281c5 commit r15-703-gb390b0115696353ba579706531fbd3bcf39281c5 Author: Kewen Lin Date: Mon May 20 21:01:06 2024 -0500 rs6000: Add assert !TARGET_VSX if !TARGET_ALTIVEC and strip a useless check In function rs6000_option_override_internal, we have the checks and adjustments like: if (TARGET_P8_VECTOR && !TARGET_ALTIVEC) rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR; if (TARGET_P8_VECTOR && !TARGET_VSX) rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR; But in fact some previous code has guaranteed !TARGET_VSX if !TARGET_ALTIVEC, so we can remove the former check and adjustment. This patch is to remove it accordingly and also place an explicit assertion. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove useless check on TARGET_P8_VECTOR && !TARGET_ALTIVEC and add an assertion on !TARGET_VSX if !TARGET_ALTIVEC. Diff: --- gcc/config/rs6000/rs6000.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index d18e262d81de..e4dc629ddcc9 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3940,8 +3940,9 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_FPRND; } - if (TARGET_P8_VECTOR && !TARGET_ALTIVEC) -rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR; + /* Assert !TARGET_VSX if !TARGET_ALTIVEC and make some adjustments + based on either !TARGET_VSX or !TARGET_ALTIVEC concise. */ + gcc_assert (TARGET_ALTIVEC || !TARGET_VSX); if (TARGET_P8_VECTOR && !TARGET_VSX) rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
[gcc r15-702] rs6000: Fix ICE on IEEE128 long double without vsx [PR114402]
https://gcc.gnu.org/g:c547e353597ac4e0af09c2faca8c5a16744dcea4
commit r15-702-gc547e353597ac4e0af09c2faca8c5a16744dcea4
Author: Kewen Lin
Date: Mon May 20 21:01:06 2024 -0500
rs6000: Fix ICE on IEEE128 long double without vsx [PR114402]
As PR114402 shows, we supports IEEE128 format long double
even if there is no vsx support, but there is an ICE about
cbranch as the test case shows. For now, we only supports
compare:CCFP pattern for IEEE128 fp if TARGET_FLOAT128_HW,
so in function rs6000_generate_compare we have a check with
!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode) to make
!TARGET_FLOAT128_HW IEEE128 fp handling go with libcall.
But unfortunately the IEEE128 without vsx support doesn't
meet FLOAT128_VECTOR_P (mode) so it goes further with an
unmatched compare:CCFP pattern which triggers ICE.
So this patch is to make rs6000_generate_compare consider
IEEE128 without vsx as well then it can end up with libcall.
PR target/114402
gcc/ChangeLog:
* config/rs6000/rs6000.cc (rs6000_generate_compare): Make IEEE128
handling without vsx go with libcall.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/pr114402.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.cc | 4 ++--
gcc/testsuite/gcc.target/powerpc/pr114402.c | 16
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index e713a1e1d570..d18e262d81de 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -15283,7 +15283,7 @@ rs6000_generate_compare (rtx cmp, machine_mode mode)
rtx op0 = XEXP (cmp, 0);
rtx op1 = XEXP (cmp, 1);
- if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
+ if (!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode))
comp_mode = CCmode;
else if (FLOAT_MODE_P (mode))
comp_mode = CCFPmode;
@@ -15315,7 +15315,7 @@ rs6000_generate_compare (rtx cmp, machine_mode mode)
/* IEEE 128-bit support in VSX registers when we do not have hardware
support. */
- if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
+ if (!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode))
{
rtx libfunc = NULL_RTX;
bool check_nan = false;
diff --git a/gcc/testsuite/gcc.target/powerpc/pr114402.c
b/gcc/testsuite/gcc.target/powerpc/pr114402.c
new file mode 100644
index ..9323c5ee991d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr114402.c
@@ -0,0 +1,16 @@
+/* Explicitly disable VSX when VSX is on. */
+/* { dg-options "-mno-vsx" { target powerpc_vsx } } */
+
+/* Verify there is no ICE. */
+
+long double a;
+long double b;
+
+int
+foo ()
+{
+ if (a > b)
+return 0;
+ else
+return 1;
+}
[gcc r15-700] PR modula2/115164 initial test code highlighting the problem
https://gcc.gnu.org/g:d642b66a298ece7394e786a6a2d14a4f0b561d9a
commit r15-700-gd642b66a298ece7394e786a6a2d14a4f0b561d9a
Author: Gaius Mulley
Date: Tue May 21 01:11:48 2024 +0100
PR modula2/115164 initial test code highlighting the problem
This patch includes some trivial testcode which highlights
PR 115164. Expect future test code to perform runtime checks
for a series of trailing zeros.
gcc/testsuite/ChangeLog:
PR modula2/115164
* gm2/isolib/run/pass/testlowread.mod: New test.
* gm2/isolib/run/pass/testwritereal.mod: New test.
Signed-off-by: Gaius Mulley
Diff:
---
gcc/testsuite/gm2/isolib/run/pass/testlowread.mod | 9 +
gcc/testsuite/gm2/isolib/run/pass/testwritereal.mod | 9 +
2 files changed, 18 insertions(+)
diff --git a/gcc/testsuite/gm2/isolib/run/pass/testlowread.mod
b/gcc/testsuite/gm2/isolib/run/pass/testlowread.mod
new file mode 100644
index ..fefbcb0b3720
--- /dev/null
+++ b/gcc/testsuite/gm2/isolib/run/pass/testlowread.mod
@@ -0,0 +1,9 @@
+MODULE testlowread ;
+
+FROM LowReal IMPORT places ;
+FROM STextIO IMPORT WriteString, WriteLn ;
+FROM SWholeIO IMPORT WriteCard ;
+
+BEGIN
+ WriteString ('value of places = ') ; WriteCard (places, 0) ; WriteLn
+END testlowread.
diff --git a/gcc/testsuite/gm2/isolib/run/pass/testwritereal.mod
b/gcc/testsuite/gm2/isolib/run/pass/testwritereal.mod
new file mode 100644
index ..025d684175c5
--- /dev/null
+++ b/gcc/testsuite/gm2/isolib/run/pass/testwritereal.mod
@@ -0,0 +1,9 @@
+MODULE testwritereal ;
+
+FROM STextIO IMPORT WriteString, WriteLn ;
+FROM SRealIO IMPORT WriteFloat ;
+FROM RealMath IMPORT pi ;
+
+BEGIN
+ WriteString ('value of pi = ') ; WriteFloat (pi, 0, 0) ; WriteLn
+END testwritereal.
[gcc r14-10222] PHIOPT: Don't transform minmax if middle bb contains a phi [PR115143]
https://gcc.gnu.org/g:89ab128656b9da1359705bd770ae7d2367b33ec2
commit r14-10222-g89ab128656b9da1359705bd770ae7d2367b33ec2
Author: Andrew Pinski
Date: Sat May 18 11:55:58 2024 -0700
PHIOPT: Don't transform minmax if middle bb contains a phi [PR115143]
The problem here is even if last_and_only_stmt returns a statement,
the bb might still contain a phi node which defines a ssa name
which is used in that statement so we need to add a check to make sure
that the phi nodes are empty for the middle bbs in both the
`CMP?MINMAX:MINMAX` case and the `CMP?MINMAX:B` cases.
Bootstrapped and tested on x86_64_linux-gnu with no regressions.
PR tree-optimization/115143
gcc/ChangeLog:
* tree-ssa-phiopt.cc (minmax_replacement): Check for empty
phi nodes for middle bbs for the case where middle bb is not empty.
gcc/testsuite/ChangeLog:
* gcc.c-torture/compile/pr115143-1.c: New test.
* gcc.c-torture/compile/pr115143-2.c: New test.
* gcc.c-torture/compile/pr115143-3.c: New test.
Signed-off-by: Andrew Pinski
(cherry picked from commit 9ff8f041331ef8b56007fb3c4d41d76f9850010d)
Diff:
---
gcc/testsuite/gcc.c-torture/compile/pr115143-1.c | 21 +
gcc/testsuite/gcc.c-torture/compile/pr115143-2.c | 30
gcc/testsuite/gcc.c-torture/compile/pr115143-3.c | 29 +++
gcc/tree-ssa-phiopt.cc | 12 ++
4 files changed, 92 insertions(+)
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr115143-1.c
b/gcc/testsuite/gcc.c-torture/compile/pr115143-1.c
new file mode 100644
index ..5cb119ea4325
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr115143-1.c
@@ -0,0 +1,21 @@
+/* PR tree-optimization/115143 */
+/* This used to ICE.
+ minmax part of phiopt would transform,
+ would transform `a!=0?min(a, b) : 0` into `min(a,b)`
+ which was correct except b was defined by a phi in the inner
+ bb which was not handled. */
+short a, d;
+char b;
+long c;
+unsigned long e, f;
+void g(unsigned long h) {
+ if (c ? e : b)
+if (e)
+ if (d) {
+a = f ? ({
+ unsigned long i = d ? f : 0, j = e ? h : 0;
+ i < j ? i : j;
+}) : 0;
+ }
+}
+
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr115143-2.c
b/gcc/testsuite/gcc.c-torture/compile/pr115143-2.c
new file mode 100644
index ..05c3bbe9738e
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr115143-2.c
@@ -0,0 +1,30 @@
+/* { dg-options "-fgimple" } */
+/* PR tree-optimization/115143 */
+/* This used to ICE.
+ minmax part of phiopt would transform,
+ would transform `a!=0?min(a, b) : 0` into `min(a,b)`
+ which was correct except b was defined by a phi in the inner
+ bb which was not handled. */
+unsigned __GIMPLE (ssa,startwith("phiopt"))
+foo (unsigned a, unsigned b)
+{
+ unsigned j;
+ unsigned _23;
+ unsigned _12;
+
+ __BB(2):
+ if (a_6(D) != 0u)
+goto __BB3;
+ else
+goto __BB4;
+
+ __BB(3):
+ j_10 = __PHI (__BB2: b_11(D));
+ _23 = __MIN (a_6(D), j_10);
+ goto __BB4;
+
+ __BB(4):
+ _12 = __PHI (__BB3: _23, __BB2: 0u);
+ return _12;
+
+}
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr115143-3.c
b/gcc/testsuite/gcc.c-torture/compile/pr115143-3.c
new file mode 100644
index ..53c5fb5588e9
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr115143-3.c
@@ -0,0 +1,29 @@
+/* { dg-options "-fgimple" } */
+/* PR tree-optimization/115143 */
+/* This used to ICE.
+ minmax part of phiopt would transform,
+ would transform `a!=0?min(a, b) : 0` into `min(a,b)`
+ which was correct except b was defined by a phi in the inner
+ bb which was not handled. */
+unsigned __GIMPLE (ssa,startwith("phiopt"))
+foo (unsigned a, unsigned b)
+{
+ unsigned j;
+ unsigned _23;
+ unsigned _12;
+
+ __BB(2):
+ if (a_6(D) > 0u)
+goto __BB3;
+ else
+goto __BB4;
+
+ __BB(3):
+ j_10 = __PHI (__BB2: b_7(D));
+ _23 = __MIN (a_6(D), j_10);
+ goto __BB4;
+
+ __BB(4):
+ _12 = __PHI (__BB3: _23, __BB2: 0u);
+ return _12;
+}
diff --git a/gcc/tree-ssa-phiopt.cc b/gcc/tree-ssa-phiopt.cc
index d1746c4b468a..150e58e39e3f 100644
--- a/gcc/tree-ssa-phiopt.cc
+++ b/gcc/tree-ssa-phiopt.cc
@@ -1918,6 +1918,10 @@ minmax_replacement (basic_block cond_bb, basic_block
middle_bb, basic_block alt_
|| gimple_code (assign) != GIMPLE_ASSIGN)
return false;
+ /* There cannot be any phi nodes in the middle bb. */
+ if (!gimple_seq_empty_p (phi_nodes (middle_bb)))
+ return false;
+
lhs = gimple_assign_lhs (assign);
ass_code = gimple_assign_rhs_code (assign);
if (ass_code != MAX_EXPR && ass_code != MIN_EXPR)
@@ -1931,6 +1935,10 @@ minmax_replacement (basic_block cond_bb, basic_block
middle_bb, basic_block alt_
|| gimple_code (assign) != GIMPLE_ASSIGN)
return false;
+ /* There canno
[gcc r15-699] PHIOPT: Don't transform minmax if middle bb contains a phi [PR115143]
https://gcc.gnu.org/g:9ff8f041331ef8b56007fb3c4d41d76f9850010d
commit r15-699-g9ff8f041331ef8b56007fb3c4d41d76f9850010d
Author: Andrew Pinski
Date: Sat May 18 11:55:58 2024 -0700
PHIOPT: Don't transform minmax if middle bb contains a phi [PR115143]
The problem here is even if last_and_only_stmt returns a statement,
the bb might still contain a phi node which defines a ssa name
which is used in that statement so we need to add a check to make sure
that the phi nodes are empty for the middle bbs in both the
`CMP?MINMAX:MINMAX` case and the `CMP?MINMAX:B` cases.
Bootstrapped and tested on x86_64_linux-gnu with no regressions.
PR tree-optimization/115143
gcc/ChangeLog:
* tree-ssa-phiopt.cc (minmax_replacement): Check for empty
phi nodes for middle bbs for the case where middle bb is not empty.
gcc/testsuite/ChangeLog:
* gcc.c-torture/compile/pr115143-1.c: New test.
* gcc.c-torture/compile/pr115143-2.c: New test.
* gcc.c-torture/compile/pr115143-3.c: New test.
Signed-off-by: Andrew Pinski
Diff:
---
gcc/testsuite/gcc.c-torture/compile/pr115143-1.c | 21 +
gcc/testsuite/gcc.c-torture/compile/pr115143-2.c | 30
gcc/testsuite/gcc.c-torture/compile/pr115143-3.c | 29 +++
gcc/tree-ssa-phiopt.cc | 12 ++
4 files changed, 92 insertions(+)
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr115143-1.c
b/gcc/testsuite/gcc.c-torture/compile/pr115143-1.c
new file mode 100644
index ..5cb119ea4325
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr115143-1.c
@@ -0,0 +1,21 @@
+/* PR tree-optimization/115143 */
+/* This used to ICE.
+ minmax part of phiopt would transform,
+ would transform `a!=0?min(a, b) : 0` into `min(a,b)`
+ which was correct except b was defined by a phi in the inner
+ bb which was not handled. */
+short a, d;
+char b;
+long c;
+unsigned long e, f;
+void g(unsigned long h) {
+ if (c ? e : b)
+if (e)
+ if (d) {
+a = f ? ({
+ unsigned long i = d ? f : 0, j = e ? h : 0;
+ i < j ? i : j;
+}) : 0;
+ }
+}
+
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr115143-2.c
b/gcc/testsuite/gcc.c-torture/compile/pr115143-2.c
new file mode 100644
index ..05c3bbe9738e
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr115143-2.c
@@ -0,0 +1,30 @@
+/* { dg-options "-fgimple" } */
+/* PR tree-optimization/115143 */
+/* This used to ICE.
+ minmax part of phiopt would transform,
+ would transform `a!=0?min(a, b) : 0` into `min(a,b)`
+ which was correct except b was defined by a phi in the inner
+ bb which was not handled. */
+unsigned __GIMPLE (ssa,startwith("phiopt"))
+foo (unsigned a, unsigned b)
+{
+ unsigned j;
+ unsigned _23;
+ unsigned _12;
+
+ __BB(2):
+ if (a_6(D) != 0u)
+goto __BB3;
+ else
+goto __BB4;
+
+ __BB(3):
+ j_10 = __PHI (__BB2: b_11(D));
+ _23 = __MIN (a_6(D), j_10);
+ goto __BB4;
+
+ __BB(4):
+ _12 = __PHI (__BB3: _23, __BB2: 0u);
+ return _12;
+
+}
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr115143-3.c
b/gcc/testsuite/gcc.c-torture/compile/pr115143-3.c
new file mode 100644
index ..53c5fb5588e9
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr115143-3.c
@@ -0,0 +1,29 @@
+/* { dg-options "-fgimple" } */
+/* PR tree-optimization/115143 */
+/* This used to ICE.
+ minmax part of phiopt would transform,
+ would transform `a!=0?min(a, b) : 0` into `min(a,b)`
+ which was correct except b was defined by a phi in the inner
+ bb which was not handled. */
+unsigned __GIMPLE (ssa,startwith("phiopt"))
+foo (unsigned a, unsigned b)
+{
+ unsigned j;
+ unsigned _23;
+ unsigned _12;
+
+ __BB(2):
+ if (a_6(D) > 0u)
+goto __BB3;
+ else
+goto __BB4;
+
+ __BB(3):
+ j_10 = __PHI (__BB2: b_7(D));
+ _23 = __MIN (a_6(D), j_10);
+ goto __BB4;
+
+ __BB(4):
+ _12 = __PHI (__BB3: _23, __BB2: 0u);
+ return _12;
+}
diff --git a/gcc/tree-ssa-phiopt.cc b/gcc/tree-ssa-phiopt.cc
index f166c3132cb7..918cf50b5898 100644
--- a/gcc/tree-ssa-phiopt.cc
+++ b/gcc/tree-ssa-phiopt.cc
@@ -1925,6 +1925,10 @@ minmax_replacement (basic_block cond_bb, basic_block
middle_bb, basic_block alt_
|| gimple_code (assign) != GIMPLE_ASSIGN)
return false;
+ /* There cannot be any phi nodes in the middle bb. */
+ if (!gimple_seq_empty_p (phi_nodes (middle_bb)))
+ return false;
+
lhs = gimple_assign_lhs (assign);
ass_code = gimple_assign_rhs_code (assign);
if (ass_code != MAX_EXPR && ass_code != MIN_EXPR)
@@ -1938,6 +1942,10 @@ minmax_replacement (basic_block cond_bb, basic_block
middle_bb, basic_block alt_
|| gimple_code (assign) != GIMPLE_ASSIGN)
return false;
+ /* There cannot be any phi nodes in the alt middle bb. */
+ if (!gimple_seq_empty_p
[gcc(refs/users/meissner/heads/work166-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:2b03ff803c7f0e6c4f695a0969c966f30c2cf9db commit 2b03ff803c7f0e6c4f695a0969c966f30c2cf9db Author: Michael Meissner Date: Mon May 20 17:18:26 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 94 ++- 1 file changed, 93 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 3e168fa367eb..c09b96a6afc1 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,6 +1,98 @@ + Branch work166-tar, patch #202 + +Add -mtar. + +gcc/ + +2024-05-20 Michael Meissner + + * config/rs6000/constraints.md (h constraint): Add documentation for TAR + register. + (wt constraint): New constraint. + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mtar. + * config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register. + (alt_reg_names): Likewise. + (rs6000_hard_regno_mode_ok_uncached): Add support for -mintspr. + (rs6000_debug_reg_global): Print information about the TAR register and + the wt constraint. + (rs6000_init_hard_regno_mode_ok): Setup the TAR register. Set up the wt + constraint if -mtar. + (rs6000_option_override_internal): If -mtar, make sure we are running on + at least a power9. + (rs6000_conditional_register_usage): Enable TAR register if -mtar. + (print_operand): Handle the TAR register. + (rs6000_debugger_regno): Likewise. + (rs6000_opt_masks): Add -mtar. + * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register. + (FIXED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (enum reg_class): Add TAR_REGS register class. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (enum r6000_reg_class_enum): Add wt constraint. + (rs6000_reg_names): Add TAR register. + * config/rs6000/rs6000.md (TAR_REGNO): New constant. + (mov_internal): Add support for the TAR register. + (movcc_): Likewise. + (movsf_hardfloat): Likewise. + (movsf_hardfloat): Likewise. + (movsd_hardfloat): Likewise. + (mov_hardfloat64): Likewise. + (mov_softfloat64): Likewise. + (@tablejump_insn_normal): Likewise. + (@tablejump_insn_nospec): Likewise. + * config/rs6000/rs6000.opt (-mtar): New option. + +gcc/testsuite/ + +2024-05-14 Michael Meissner + + * gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR register. + * gcc.target/powerpc/pr51513.c: Likewise. + * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise. + + Branch work166-tar, patch #201 + +Add -mmfspr + +2024-05-20 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mmfspr. + * config/rs6000/rs6000.cc (rs6000_register_move_cost): If -mmfspr, make + moves from CTR more expensive. + (rs6000_opt_masks): Add -mmfspr. + * config/rs6000/rs6000.opt (-mmfspr): New option. + + Branch work166-tar, patch #200 + +Add -mintspr + +2024-05-20 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mintspr. + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Restrict + modes that go in SPRs to modes that fit in the SPR and are not complex + modes. If -mintspr, restrict modes that go into SPRs to be scalar + integers. + (rs6000_opt_masks): Add -mintspr. + * config/rs6000/rs6000 (-mintspr): New option. + Branch work166-tar, baseline +Add ChangeLog.tar and update REVISION. + +2024-05-02 Michael Meissner + +gcc/ + + * ChangeLog.tar: New file for branch. + * REVISION: Update. + 2024-05-17 Michael Meissner Clone branch -
[gcc(refs/users/meissner/heads/work166-tar)] Add -mtar.
https://gcc.gnu.org/g:978a8513f7cf7f6a26750d9f7fc1e23d04c34c48
commit 978a8513f7cf7f6a26750d9f7fc1e23d04c34c48
Author: Michael Meissner
Date: Mon May 20 17:11:58 2024 -0400
Add -mtar.
gcc/
2024-05-20 Michael Meissner
* config/rs6000/constraints.md (h constraint): Add documentation
for TAR
register.
(wt constraint): New constraint.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mtar.
* config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register.
(alt_reg_names): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Add support for -mintspr.
(rs6000_debug_reg_global): Print information about the TAR register
and
the wt constraint.
(rs6000_init_hard_regno_mode_ok): Setup the TAR register. Set up
the wt
constraint if -mtar.
(rs6000_option_override_internal): If -mtar, make sure we are
running on
at least a power9.
(rs6000_conditional_register_usage): Enable TAR register if -mtar.
(print_operand): Handle the TAR register.
(rs6000_debugger_regno): Likewise.
(rs6000_opt_masks): Add -mtar.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register.
(FIXED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(enum reg_class): Add TAR_REGS register class.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(enum r6000_reg_class_enum): Add wt constraint.
(rs6000_reg_names): Add TAR register.
* config/rs6000/rs6000.md (TAR_REGNO): New constant.
(mov_internal): Add support for the TAR register.
(movcc_): Likewise.
(movsf_hardfloat): Likewise.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov_hardfloat64): Likewise.
(mov_softfloat64): Likewise.
(@tablejump_insn_normal): Likewise.
(@tablejump_insn_nospec): Likewise.
* config/rs6000/rs6000.opt (-mtar): New option.
gcc/testsuite/
2024-05-14 Michael Meissner
* gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR
register.
* gcc.target/powerpc/pr51513.c: Likewise.
* gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
Diff:
---
gcc/config/rs6000/constraints.md | 5 ++-
gcc/config/rs6000/rs6000-cpus.def | 1 +
gcc/config/rs6000/rs6000.cc| 46 ++
gcc/config/rs6000/rs6000.h | 31 +--
gcc/config/rs6000/rs6000.md| 23 +--
gcc/config/rs6000/rs6000.opt | 4 ++
gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c| 4 +-
gcc/testsuite/gcc.target/powerpc/pr51513.c | 4 +-
.../gcc.target/powerpc/safe-indirect-jump-3.c | 2 +-
9 files changed, 83 insertions(+), 37 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 369a7b75042d..14f0465d7ae5 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -57,7 +57,7 @@
"@internal A compatibility alias for @code{wa}.")
(define_register_constraint "h" "SPECIAL_REGS"
- "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
+ "@internal A special register (@code{vrsave}, @code{ctr}, @code{lr} or
@code{tar}).")
(define_register_constraint "c" "CTR_REGS"
"The count register, @code{ctr}.")
@@ -91,6 +91,9 @@
"@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
@code{NO_REGS}.")
+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
+ "The tar register, @code{tar}.")
+
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
@code{NO_REGS}.")
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 47aca85aa4bc..0907930b2d8b 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -160,6 +160,7 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL\
+| OPTION_MASK_TAR \
| OPTION_MASK_VSX)
#endif
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index ce1a49abe598..1fe3eda838fe 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1224,8 +1224,8 @@ char rs6000_reg_names[][8] =
"lr", "ctr", "ca", "ap",
/* cr0..cr7 */
"
[gcc(refs/users/meissner/heads/work166-tar)] Add -mmfspr
https://gcc.gnu.org/g:5816726d26832b3d0f3a87f06b4b3e38982ce89c
commit 5816726d26832b3d0f3a87f06b4b3e38982ce89c
Author: Michael Meissner
Date: Mon May 20 16:38:25 2024 -0400
Add -mmfspr
2024-05-20 Michael Meissner
gcc/
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mmfspr.
* config/rs6000/rs6000.cc (rs6000_register_move_cost): If -mmfspr,
make
moves from CTR more expensive.
(rs6000_opt_masks): Add -mmfspr.
* config/rs6000/rs6000.opt (-mmfspr): New option.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 1 +
gcc/config/rs6000/rs6000.cc | 12
gcc/config/rs6000/rs6000.opt | 4
3 files changed, 17 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 6fcbcbdadef7..47aca85aa4bc 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -136,6 +136,7 @@
| OPTION_MASK_INTSPR \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF\
+| OPTION_MASK_MFSPR\
| OPTION_MASK_MMA \
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW\
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7d5b94cda101..ce1a49abe598 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -22807,6 +22807,17 @@ rs6000_register_move_cost (machine_mode mode,
ret = 2 * hard_regno_nregs (reg, mode);
}
+ /* Make moves from the CTR register more expensive so that the register
+ allocator does not think of these registers are useful for saving
+ results. */
+ else if (TARGET_MFSPR
+ && reg_classes_intersect_p (to, GENERAL_REGS)
+ && reg_classes_intersect_p (from, CTR_REGS))
+{
+ rclass = from;
+ ret = 32;
+}
+
/* Moves from/to GENERAL_REGS. */
else if ((rclass = from, reg_classes_intersect_p (to, GENERAL_REGS))
|| (rclass = to, reg_classes_intersect_p (from, GENERAL_REGS)))
@@ -24491,6 +24502,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "isel",OPTION_MASK_ISEL, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
+ { "mfspr", OPTION_MASK_MFSPR, false, true },
{ "mma", OPTION_MASK_MMA,false, true },
{ "modulo", OPTION_MASK_MODULO, false, true },
{ "mulhw", OPTION_MASK_MULHW, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 2f3970b664cc..d45746bc24f4 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -634,6 +634,10 @@ mintspr
Target Undocumented Mask(INTSPR) Var(rs6000_isa_flags)
Disallow (allow) non-integer types in SPR registers.
+mmfspr
+Target Undocumented Mask(MFSPR) Var(rs6000_isa_flags)
+Disallow (allow) non-integer types in SPR registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
[gcc(refs/users/meissner/heads/work166-tar)] Add -mintspr
https://gcc.gnu.org/g:fb7e62663cd40d434bbd2ae53082ca3f56ef2ef7
commit fb7e62663cd40d434bbd2ae53082ca3f56ef2ef7
Author: Michael Meissner
Date: Mon May 20 14:25:40 2024 -0400
Add -mintspr
2024-05-20 Michael Meissner
gcc/
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mintspr.
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Restrict
modes that go in SPRs to modes that fit in the SPR and are not
complex
modes. If -mintspr, restrict modes that go into SPRs to be scalar
integers.
(rs6000_opt_masks): Add -mintspr.
* config/rs6000/rs6000 (-mintspr): New option.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 1 +
gcc/config/rs6000/rs6000.cc | 27 ++-
gcc/config/rs6000/rs6000.opt | 4
3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index d625dbeb91fd..6fcbcbdadef7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -133,6 +133,7 @@
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
+| OPTION_MASK_INTSPR \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF\
| OPTION_MASK_MMA \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 96241c18b617..7d5b94cda101 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1851,9 +1851,13 @@ static int
rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
+ bool orig_complex_p = false;
if (COMPLEX_MODE_P (mode))
-mode = GET_MODE_INNER (mode);
+{
+ mode = GET_MODE_INNER (mode);
+ orig_complex_p = true;
+}
/* Vector pair modes need even/odd VSX register pairs. Only allow vector
registers. */
@@ -1935,6 +1939,26 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if (CA_REGNO_P (regno))
return mode == Pmode || mode == SImode;
+ /* Possibly restrict SPR registers to have small scalar integers. */
+ switch (regno)
+{
+case VRSAVE_REGNO:
+case VSCR_REGNO:
+case LR_REGNO:
+case CTR_REGNO:
+ {
+ unsigned reg_size = ((regno == VRSAVE_REGNO || regno == VSCR_REGNO)
+? 4
+: UNITS_PER_WORD);
+
+ return (!orig_complex_p && GET_MODE_SIZE (mode) <= reg_size
+ && (!TARGET_INTSPR || SCALAR_INT_MODE_P (mode)));
+ }
+
+default:
+ break;
+}
+
/* AltiVec only in AldyVec registers. */
if (ALTIVEC_REGNO_P (regno))
return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
@@ -24463,6 +24487,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "power11", OPTION_MASK_POWER11,false, false },
{ "hard-dfp",OPTION_MASK_DFP,false,
true },
{ "htm", OPTION_MASK_HTM,false, true },
+ { "intspr", OPTION_MASK_INTSPR, false, true },
{ "isel",OPTION_MASK_ISEL, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 70fd7080bc52..2f3970b664cc 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -630,6 +630,10 @@ mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.
+mintspr
+Target Undocumented Mask(INTSPR) Var(rs6000_isa_flags)
+Disallow (allow) non-integer types in SPR registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
[gcc r15-698] fortran: Assume there is no cyclic reference with submodule symbols [PR99798]
https://gcc.gnu.org/g:38d1761c0c94b77a081ccc180d6e039f7a670468
commit r15-698-g38d1761c0c94b77a081ccc180d6e039f7a670468
Author: Mikael Morin
Date: Sun May 12 15:16:23 2024 +0200
fortran: Assume there is no cyclic reference with submodule symbols
[PR99798]
This prevents a premature release of memory with procedure symbols from
submodules, causing random compiler crashes.
The problem is a fragile detection of cyclic references, which can match
with procedures host-associated from a module in submodules, in cases where
it
shouldn't. The formal namespace is released, and with it the dummy
arguments
symbols of the procedure. But there is no cyclic reference, so the
procedure
symbol itself is not released and remains, with pointers to its dummy
arguments
now dangling.
The fix adds a condition to avoid the case, and refactors to a new predicate
by the way. Part of the original condition is also removed, for lack of a
reason to keep it.
PR fortran/99798
gcc/fortran/ChangeLog:
* symbol.cc (gfc_release_symbol): Move the condition guarding
the handling cyclic references...
(cyclic_reference_break_needed): ... here as a new predicate.
Remove superfluous parts. Add a condition preventing any premature
release with submodule symbols.
gcc/testsuite/ChangeLog:
* gfortran.dg/submodule_33.f08: New test.
Diff:
---
gcc/fortran/symbol.cc | 54 --
gcc/testsuite/gfortran.dg/submodule_33.f08 | 20 +++
2 files changed, 72 insertions(+), 2 deletions(-)
diff --git a/gcc/fortran/symbol.cc b/gcc/fortran/symbol.cc
index 8f7deac1d1ee..0a1646def678 100644
--- a/gcc/fortran/symbol.cc
+++ b/gcc/fortran/symbol.cc
@@ -3179,6 +3179,57 @@ gfc_free_symbol (gfc_symbol *&sym)
}
+/* Returns true if the symbol SYM has, through its FORMAL_NS field, a reference
+ to itself which should be eliminated for the symbol memory to be released
+ via normal reference counting.
+
+ The implementation is crucial as it controls the proper release of symbols,
+ especially (contained) procedure symbols, which can represent a lot of
memory
+ through the namespace of their body.
+
+ We try to avoid freeing too much memory (causing dangling pointers), to not
+ leak too much (wasting memory), and to avoid expensive walks of the symbol
+ tree (which would be the correct way to check for a cycle). */
+
+bool
+cyclic_reference_break_needed (gfc_symbol *sym)
+{
+ /* Normal symbols don't reference themselves. */
+ if (sym->formal_ns == nullptr)
+return false;
+
+ /* Procedures at the root of the file do have a self reference, but they
don't
+ have a reference in a parent namespace preventing the release of the
+ procedure namespace, so they can use the normal reference counting. */
+ if (sym->formal_ns == sym->ns)
+return false;
+
+ /* If sym->refs == 1, we can use normal reference counting. If sym->refs >
2,
+ the symbol won't be freed anyway, with or without cyclic reference. */
+ if (sym->refs != 2)
+return false;
+
+ /* Procedure symbols host-associated from a module in submodules are special,
+ because the namespace of the procedure block in the submodule is different
+ from the FORMAL_NS namespace generated by host-association. So there are
+ two different namespaces representing the same procedure namespace. As
+ FORMAL_NS comes from host-association, which only imports symbols visible
+ from the outside (dummy arguments basically), we can assume there is no
+ self reference through FORMAL_NS in that case. */
+ if (sym->attr.host_assoc && sym->attr.used_in_submodule)
+return false;
+
+ /* We can assume that contained procedures have cyclic references, because
+ the symbol of the procedure itself is accessible in the procedure body
+ namespace. So we assume that symbols with a formal namespace different
+ from the declaration namespace and two references, one of which is about
+ to be removed, are procedures with just the self reference left. At this
+ point, the symbol SYM matches that pattern, so we return true here to
+ permit the release of SYM. */
+ return true;
+}
+
+
/* Decrease the reference counter and free memory when we reach zero.
Returns true if the symbol has been freed, false otherwise. */
@@ -3188,8 +3239,7 @@ gfc_release_symbol (gfc_symbol *&sym)
if (sym == NULL)
return false;
- if (sym->formal_ns != NULL && sym->refs == 2 && sym->formal_ns != sym->ns
- && (!sym->attr.entry || !sym->module))
+ if (cyclic_reference_break_needed (sym))
{
/* As formal_ns contains a reference to sym, delete formal_ns just
before the deletion of sym. */
diff --git a/gcc/testsuite/gfortran.dg/submodule_33.f08
b/gcc/testsuite/gfortran.dg/submodule_33.f08
new
[gcc r15-697] aarch64: Fold vget_low_* intrinsics to BIT_FIELD_REF [PR102171]
https://gcc.gnu.org/g:a2e4fe5a53cf75cd055f64e745ebd51253e42254
commit r15-697-ga2e4fe5a53cf75cd055f64e745ebd51253e42254
Author: Pengxuan Zheng
Date: Mon May 13 10:47:10 2024 -0700
aarch64: Fold vget_low_* intrinsics to BIT_FIELD_REF [PR102171]
This patch folds vget_low_* intrinsics to BIT_FILED_REF to open up more
optimization opportunities for gimple optimizers.
While we are here, we also remove the vget_low_* definitions from
arm_neon.h and
use the new intrinsics framework.
PR target/102171
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.cc
(AARCH64_SIMD_VGET_LOW_BUILTINS):
New macro to create definitions for all vget_low intrinsics.
(VGET_LOW_BUILTIN): Likewise.
(enum aarch64_builtins): Add vget_low function codes.
(aarch64_general_fold_builtin): Fold vget_low calls.
* config/aarch64/aarch64-simd-builtins.def: Delete vget_low
builtins.
* config/aarch64/aarch64-simd.md (aarch64_get_low): Delete.
(aarch64_vget_lo_halfv8bf): Likewise.
* config/aarch64/arm_neon.h (__attribute__): Delete.
(vget_low_f16): Likewise.
(vget_low_f32): Likewise.
(vget_low_f64): Likewise.
(vget_low_p8): Likewise.
(vget_low_p16): Likewise.
(vget_low_p64): Likewise.
(vget_low_s8): Likewise.
(vget_low_s16): Likewise.
(vget_low_s32): Likewise.
(vget_low_s64): Likewise.
(vget_low_u8): Likewise.
(vget_low_u16): Likewise.
(vget_low_u32): Likewise.
(vget_low_u64): Likewise.
(vget_low_bf16): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/pr113573.c: Replace
__builtin_aarch64_get_lowv8hi
with vget_low_s16.
* gcc.target/aarch64/vget_low_2.c: New test.
* gcc.target/aarch64/vget_low_2_be.c: New test.
Signed-off-by: Pengxuan Zheng
Diff:
---
gcc/config/aarch64/aarch64-builtins.cc | 60 +
gcc/config/aarch64/aarch64-simd-builtins.def | 5 +-
gcc/config/aarch64/aarch64-simd.md | 23 +
gcc/config/aarch64/arm_neon.h| 105 ---
gcc/testsuite/gcc.target/aarch64/pr113573.c | 2 +-
gcc/testsuite/gcc.target/aarch64/vget_low_2.c| 30 +++
gcc/testsuite/gcc.target/aarch64/vget_low_2_be.c | 31 +++
7 files changed, 124 insertions(+), 132 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-builtins.cc
b/gcc/config/aarch64/aarch64-builtins.cc
index 75d21de14011..11b888016ed7 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -658,6 +658,23 @@ static aarch64_simd_builtin_datum
aarch64_simd_builtin_data[] = {
VREINTERPRET_BUILTINS \
VREINTERPRETQ_BUILTINS
+#define AARCH64_SIMD_VGET_LOW_BUILTINS \
+ VGET_LOW_BUILTIN(f16) \
+ VGET_LOW_BUILTIN(f32) \
+ VGET_LOW_BUILTIN(f64) \
+ VGET_LOW_BUILTIN(p8) \
+ VGET_LOW_BUILTIN(p16) \
+ VGET_LOW_BUILTIN(p64) \
+ VGET_LOW_BUILTIN(s8) \
+ VGET_LOW_BUILTIN(s16) \
+ VGET_LOW_BUILTIN(s32) \
+ VGET_LOW_BUILTIN(s64) \
+ VGET_LOW_BUILTIN(u8) \
+ VGET_LOW_BUILTIN(u16) \
+ VGET_LOW_BUILTIN(u32) \
+ VGET_LOW_BUILTIN(u64) \
+ VGET_LOW_BUILTIN(bf16)
+
typedef struct
{
const char *name;
@@ -697,6 +714,9 @@ typedef struct
#define VREINTERPRET_BUILTIN(A, B, L) \
AARCH64_SIMD_BUILTIN_VREINTERPRET##L##_##A##_##B,
+#define VGET_LOW_BUILTIN(A) \
+ AARCH64_SIMD_BUILTIN_VGET_LOW_##A,
+
#undef VAR1
#define VAR1(T, N, MAP, FLAG, A) \
AARCH64_SIMD_BUILTIN_##T##_##N##A,
@@ -732,6 +752,7 @@ enum aarch64_builtins
AARCH64_CRC32_BUILTIN_MAX,
/* SIMD intrinsic builtins. */
AARCH64_SIMD_VREINTERPRET_BUILTINS
+ AARCH64_SIMD_VGET_LOW_BUILTINS
/* ARMv8.3-A Pointer Authentication Builtins. */
AARCH64_PAUTH_BUILTIN_AUTIA1716,
AARCH64_PAUTH_BUILTIN_PACIA1716,
@@ -823,8 +844,37 @@ static aarch64_fcmla_laneq_builtin_datum
aarch64_fcmla_lane_builtin_data[] = {
&& SIMD_INTR_QUAL(A) == SIMD_INTR_QUAL(B) \
},
+#undef VGET_LOW_BUILTIN
+#define VGET_LOW_BUILTIN(A) \
+ {"vget_low_" #A, \
+ AARCH64_SIMD_BUILTIN_VGET_LOW_##A, \
+ 2, \
+ { SIMD_INTR_MODE(A, d), SIMD_INTR_MODE(A, q) }, \
+ { SIMD_INTR_QUAL(A), SIMD_INTR_QUAL(A) }, \
+ FLAG_AUTO_FP, \
+ false \
+ },
+
+#define AARCH64_SIMD_VGET_LOW_BUILTINS \
+ VGET_LOW_BUILTIN(f16) \
+ VGET_LOW_BUILTIN(f32) \
+ VGET_LOW_BUILTIN(f64) \
+ VGET_LOW_BUILTIN(p8) \
+ VGET_LOW_BUILTIN(p16) \
+ VGET_LOW_BUILTIN(p64) \
+ VGET_LOW_BUILTIN(s8) \
+ VGET_LOW_BUILTIN(s16) \
+ VGET_LOW_BUILTIN(s32) \
+ VGET_LOW_BUILTIN(s64) \
+ VGET_LOW_BUILTIN(u8) \
+ VGET_LOW_BUILTIN(u16) \
+ VGET_LOW_BUILTIN(u32) \
+ VGET_LOW_BUILTIN(u64) \
+ VGET_LOW_BUILTIN(bf16)
+
static const aarch64_simd_intrinsic_datum aarch64_simd_intrinsic_data[] = {
AARCH64_SIMD_VREI
[gcc r15-696] AArch64: Improve costing of ctz
https://gcc.gnu.org/g:e14c673ea9ab2eca5de4db91b478f0b5297ef321
commit r15-696-ge14c673ea9ab2eca5de4db91b478f0b5297ef321
Author: Wilco Dijkstra
Date: Wed Apr 17 17:18:23 2024 +0100
AArch64: Improve costing of ctz
Improve costing of ctz - both TARGET_CSSC and vector cases were not handled
yet.
gcc:
* config/aarch64/aarch64.cc (aarch64_rtx_costs): Improve CTZ
costing.
Diff:
---
gcc/config/aarch64/aarch64.cc | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 662ff5a9b0c7..ee12d8897a88 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -14349,10 +14349,24 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int
outer ATTRIBUTE_UNUSED,
return false;
case CTZ:
- *cost = COSTS_N_INSNS (2);
-
- if (speed)
- *cost += extra_cost->alu.clz + extra_cost->alu.rev;
+ if (VECTOR_MODE_P (mode))
+ {
+ *cost = COSTS_N_INSNS (3);
+ if (speed)
+ *cost += extra_cost->vect.alu * 3;
+ }
+ else if (TARGET_CSSC)
+ {
+ *cost = COSTS_N_INSNS (1);
+ if (speed)
+ *cost += extra_cost->alu.clz;
+ }
+ else
+ {
+ *cost = COSTS_N_INSNS (2);
+ if (speed)
+ *cost += extra_cost->alu.clz + extra_cost->alu.rev;
+ }
return false;
case COMPARE:
[gcc r15-695] AArch64: Fix printing of 2-instruction alternatives
https://gcc.gnu.org/g:804fa0bb92f8073394b3859edb810c3e23375530 commit r15-695-g804fa0bb92f8073394b3859edb810c3e23375530 Author: Wilco Dijkstra Date: Thu Apr 25 17:33:00 2024 +0100 AArch64: Fix printing of 2-instruction alternatives Add missing '\' in 2-instruction movsi/di alternatives so that they are printed on separate lines. gcc: * config/aarch64/aarch64.md (movsi_aarch64): Use '\;' to force newline in 2-instruction pattern. (movdi_aarch64): Likewise. Diff: --- gcc/config/aarch64/aarch64.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index dbde066f7478..9dff2d7a2b00 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1447,7 +1447,7 @@ [w , m ; load_4 , fp , 4] ldr\t%s0, %1 [m , r Z; store_4 , * , 4] str\t%w1, %0 [m , w ; store_4 , fp , 4] str\t%s1, %0 - [r , Usw; load_4 , * , 8] adrp\t%x0, %A1;ldr\t%w0, [%x0, %L1] + [r , Usw; load_4 , * , 8] adrp\t%x0, %A1\;ldr\t%w0, [%x0, %L1] [r , Usa; adr , * , 4] adr\t%x0, %c1 [r , Ush; adr , * , 4] adrp\t%x0, %A1 [w , r Z; f_mcr, fp , 4] fmov\t%s0, %w1 @@ -1484,7 +1484,7 @@ [w, m ; load_8 , fp , 4] ldr\t%d0, %1 [m, r Z; store_8 , * , 4] str\t%x1, %0 [m, w ; store_8 , fp , 4] str\t%d1, %0 - [r, Usw; load_8 , * , 8] << TARGET_ILP32 ? "adrp\t%0, %A1;ldr\t%w0, [%0, %L1]" : "adrp\t%0, %A1;ldr\t%0, [%0, %L1]"; + [r, Usw; load_8 , * , 8] << TARGET_ILP32 ? "adrp\t%0, %A1\;ldr\t%w0, [%0, %L1]" : "adrp\t%0, %A1\;ldr\t%0, [%0, %L1]"; [r, Usa; adr , * , 4] adr\t%x0, %c1 [r, Ush; adr , * , 4] adrp\t%x0, %A1 [w, r Z; f_mcr, fp , 4] fmov\t%d0, %x1
[gcc r15-694] aarch64: Further renaming of generic code
https://gcc.gnu.org/g:8579c8ffd25072661bd34758bdbf67d75af2b338
commit r15-694-g8579c8ffd25072661bd34758bdbf67d75af2b338
Author: Ajit Kumar Agarwal
Date: Mon May 20 09:51:46 2024 -0500
aarch64: Further renaming of generic code
Renaming of generic code is done to make target independent
and target dependent code to support multiple targets.
Target independent code is the Generic code with pure virtual function
to interface betwwen target independent and dependent code.
Target dependent code is the implementation of pure virtual function for
aarch64 target and the call to target independent code.
2024-05-20 Ajit Kumar Agarwal
gcc/ChangeLog:
* config/aarch64/aarch64-ldp-fusion.cc: Rename generic parts of code
to avoid "ldp" and "stp".
Diff:
---
gcc/config/aarch64/aarch64-ldp-fusion.cc | 71
1 file changed, 36 insertions(+), 35 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-ldp-fusion.cc
b/gcc/config/aarch64/aarch64-ldp-fusion.cc
index 6b2a44f101bf..085366cdf685 100644
--- a/gcc/config/aarch64/aarch64-ldp-fusion.cc
+++ b/gcc/config/aarch64/aarch64-ldp-fusion.cc
@@ -368,7 +368,7 @@ struct aarch64_pair_fusion : public pair_fusion
};
// State used by the pass for a given basic block.
-struct ldp_bb_info
+struct pair_fusion_bb_info
{
using def_hash = nofree_ptr_hash;
using expr_key_t = pair_hash>;
@@ -389,14 +389,14 @@ struct ldp_bb_info
static const size_t obstack_alignment = sizeof (void *);
- ldp_bb_info (bb_info *bb, pair_fusion *d)
+ pair_fusion_bb_info (bb_info *bb, pair_fusion *d)
: m_bb (bb), m_pass (d), m_emitted_tombstone (false)
{
obstack_specify_allocation (&m_obstack, OBSTACK_CHUNK_SIZE,
obstack_alignment, obstack_chunk_alloc,
obstack_chunk_free);
}
- ~ldp_bb_info ()
+ ~pair_fusion_bb_info ()
{
obstack_free (&m_obstack, nullptr);
@@ -484,7 +484,7 @@ aarch64_pair_fusion::gen_pair (rtx *pats, rtx writeback,
bool load_p)
}
splay_tree_node *
-ldp_bb_info::node_alloc (access_record *access)
+pair_fusion_bb_info::node_alloc (access_record *access)
{
using T = splay_tree_node;
void *addr = obstack_alloc (&m_obstack, sizeof (T));
@@ -532,7 +532,7 @@ drop_writeback (rtx mem)
// RTX_AUTOINC addresses. The interface is like strip_offset except we take a
// MEM so that we know the mode of the access.
static rtx
-ldp_strip_offset (rtx mem, poly_int64 *offset)
+pair_mem_strip_offset (rtx mem, poly_int64 *offset)
{
rtx addr = XEXP (mem, 0);
@@ -658,7 +658,8 @@ access_group::track (Alloc alloc_node, poly_int64 offset,
insn_info *insn)
// MEM_EXPR base (i.e. a tree decl) relative to which we can track the access.
// LFS is used as part of the key to the hash table, see track_access.
bool
-ldp_bb_info::track_via_mem_expr (insn_info *insn, rtx mem, lfs_fields lfs)
+pair_fusion_bb_info::track_via_mem_expr (insn_info *insn, rtx mem,
+lfs_fields lfs)
{
if (!MEM_EXPR (mem) || !MEM_OFFSET_KNOWN_P (mem))
return false;
@@ -706,7 +707,7 @@ ldp_bb_info::track_via_mem_expr (insn_info *insn, rtx mem,
lfs_fields lfs)
// this basic block. LOAD_P is true if the access is a load, and MEM
// is the mem rtx that occurs in INSN.
void
-ldp_bb_info::track_access (insn_info *insn, bool load_p, rtx mem)
+pair_fusion_bb_info::track_access (insn_info *insn, bool load_p, rtx mem)
{
// We can't combine volatile MEMs, so punt on these.
if (MEM_VOLATILE_P (mem))
@@ -739,7 +740,7 @@ ldp_bb_info::track_access (insn_info *insn, bool load_p,
rtx mem)
poly_int64 mem_off;
rtx addr = XEXP (mem, 0);
const bool autoinc_p = GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC;
- rtx base = ldp_strip_offset (mem, &mem_off);
+ rtx base = pair_mem_strip_offset (mem, &mem_off);
if (!REG_P (base))
return;
@@ -1099,7 +1100,7 @@ def_upwards_move_range (def_info *def)
// Class that implements a state machine for building the changes needed to
form
// a store pair instruction. This allows us to easily build the changes in
// program order, as required by rtl-ssa.
-struct stp_change_builder
+struct store_change_builder
{
enum class state
{
@@ -1126,9 +1127,9 @@ struct stp_change_builder
bool done () const { return m_state == state::DONE; }
- stp_change_builder (insn_info *insns[2],
- insn_info *repurpose,
- insn_info *dest)
+ store_change_builder (insn_info *insns[2],
+ insn_info *repurpose,
+ insn_info *dest)
: m_state (state::FIRST), m_insns { insns[0], insns[1] },
m_repurpose (repurpose), m_dest (dest), m_use (nullptr) {}
@@ -1402,7 +1403,7 @@ extract_writebacks (bool load_p, rtx pats[2], int changed)
const bool autoinc_p = GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC;
poly_int64 o
[gcc r15-693] MAINTAINERS: Update Joern Rennecke's status
https://gcc.gnu.org/g:f94598ffaf5affbc9421ff230502357b07c55d9c commit r15-693-gf94598ffaf5affbc9421ff230502357b07c55d9c Author: Gerald Pfeifer Date: Mon May 20 16:43:05 2024 +0200 MAINTAINERS: Update Joern Rennecke's status This is per his mail to g...@gcc.gnu.org on 7 Jul 2023. ChangeLog: * MAINTAINERS: Move Joern Rennecke from arc and epiphany maintainer to Write After Approval. Diff: --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8e0add6bef86..e2870eef2ef1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -56,7 +56,6 @@ aarch64 port Kyrylo Tkachov alpha port Richard Henderson amdgcn portJulian Brown amdgcn portAndrew Stubbs -arc port Joern Rennecke arc port Claudiu Zissulescu arm port Nick Clifton arm port Richard Earnshaw @@ -68,7 +67,6 @@ c6x port Bernd Schmidt cris port Hans-Peter Nilsson c-sky port Xianmiao Qu c-sky port Yunhai Shang -epiphany port Joern Rennecke fr30 port Nick Clifton frv port Nick Clifton frv port Alexandre Oliva @@ -634,6 +632,7 @@ Joe Ramsay Rolf Rasmussen Fritz Reese Volker Reichelt +Joern Rennecke Bernhard Reutner-Fischer Tom Rix Thomas Rodgers
[gcc r14-10221] c++: aggregate CTAD w/ paren init and bases [PR115114]
https://gcc.gnu.org/g:a9837934203d41c96b5cf05e34f68c0d3311c973
commit r14-10221-ga9837934203d41c96b5cf05e34f68c0d3311c973
Author: Patrick Palka
Date: Fri May 17 09:02:52 2024 -0400
c++: aggregate CTAD w/ paren init and bases [PR115114]
During aggregate CTAD with paren init, we're accidentally overlooking
base classes since TYPE_FIELDS of a template type doesn't contain
corresponding base fields. So we need to consider them separately.
PR c++/115114
gcc/cp/ChangeLog:
* pt.cc (maybe_aggr_guide): Consider bases in the paren init case.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/class-deduction-aggr15.C: New test.
Reviewed-by: Jason Merrill
(cherry picked from commit 5aaf47cb1987bbc5508c4b9b7dad5ea7d69af2c2)
Diff:
---
gcc/cp/pt.cc | 7 +++
.../g++.dg/cpp2a/class-deduction-aggr15.C | 23 ++
2 files changed, 30 insertions(+)
diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index b5c494e8d15e..e9882f2a3e0a 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -30205,6 +30205,13 @@ maybe_aggr_guide (tree tmpl, tree init,
vec *args)
else if (TREE_CODE (init) == TREE_LIST)
{
int len = list_length (init);
+ for (tree binfo : BINFO_BASE_BINFOS (TYPE_BINFO (template_type)))
+ {
+ if (!len)
+ break;
+ parms = tree_cons (NULL_TREE, BINFO_TYPE (binfo), parms);
+ --len;
+ }
for (tree field = TYPE_FIELDS (template_type);
len;
--len, field = DECL_CHAIN (field))
diff --git a/gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr15.C
b/gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr15.C
new file mode 100644
index ..16dc0f52b64c
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr15.C
@@ -0,0 +1,23 @@
+// PR c++/115114
+// { dg-do compile { target c++20 } }
+
+struct X {} x;
+struct Y {} y;
+
+template
+struct A : T {
+ U m;
+};
+
+using ty1 = decltype(A{x, 42}); // OK
+using ty1 = decltype(A(x, 42)); // OK, used to fail
+using ty1 = A;
+
+template
+struct B : T, V {
+ U m = 42;
+};
+
+using ty2 = decltype(B{x, y}); // OK
+using ty2 = decltype(B(x, y)); // OK, used to fail
+using ty2 = B;
[gcc r14-10220] c++: lvalueness of non-dependent assignment expr [PR114994]
https://gcc.gnu.org/g:b3399b445ba7495b0479d43f2389e64d48de870e
commit r14-10220-gb3399b445ba7495b0479d43f2389e64d48de870e
Author: Patrick Palka
Date: Tue May 14 22:55:16 2024 -0400
c++: lvalueness of non-dependent assignment expr [PR114994]
r14-4111-g6e92a6a2a72d3b made us check non-dependent simple assignment
expressions ahead of time and give them a type, as was already done for
compound assignments. Unlike for compound assignments however, if a
simple assignment resolves to an operator overload we represent it as a
(typed) MODOP_EXPR instead of a CALL_EXPR to the selected overload.
(I reckoned this was at worst a pessimization -- we'll just have to repeat
overload resolution at instantiatiation time.)
But this turns out to break the below testcase ultimately because
MODOP_EXPR (of non-reference type) is always treated as an lvalue
according to lvalue_kind, which is incorrect for the MODOP_EXPR
representing x=42.
We can fix this by representing such class assignment expressions as
CALL_EXPRs as well, but this turns out to require some tweaking of our
-Wparentheses warning logic and may introduce other fallout making it
unsuitable for backporting.
So this patch instead fixes lvalue_kind to consider the type of a
MODOP_EXPR representing a class assignment.
PR c++/114994
gcc/cp/ChangeLog:
* tree.cc (lvalue_kind) : For a class
assignment, consider the result type.
gcc/testsuite/ChangeLog:
* g++.dg/template/non-dependent32.C: New test.
Reviewed-by: Jason Merrill
(cherry picked from commit c6cc6d4741a880109c4e0e64d5a189687fb526f6)
Diff:
---
gcc/cp/tree.cc | 5 -
gcc/testsuite/g++.dg/template/non-dependent32.C | 18 ++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/tree.cc b/gcc/cp/tree.cc
index f1a23ffe8179..9d37d255d8d5 100644
--- a/gcc/cp/tree.cc
+++ b/gcc/cp/tree.cc
@@ -275,7 +275,10 @@ lvalue_kind (const_tree ref)
/* We expect to see unlowered MODOP_EXPRs only during
template processing. */
gcc_assert (processing_template_decl);
- return clk_ordinary;
+ if (CLASS_TYPE_P (TREE_TYPE (TREE_OPERAND (ref, 0
+ goto default_;
+ else
+ return clk_ordinary;
case MODIFY_EXPR:
case TYPEID_EXPR:
diff --git a/gcc/testsuite/g++.dg/template/non-dependent32.C
b/gcc/testsuite/g++.dg/template/non-dependent32.C
new file mode 100644
index ..54252c7dfaf9
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/non-dependent32.C
@@ -0,0 +1,18 @@
+// PR c++/114994
+// { dg-do compile { target c++11 } }
+
+struct udl_arg {
+ udl_arg operator=(int);
+};
+
+void f(udl_arg&&);
+
+template
+void g() {
+ udl_arg x;
+ f(x=42); // { dg-bogus "cannot bind" }
+}
+
+int main() {
+ g();
+}
[gcc r15-692] Regenerate riscv.opt.urls and i386.opt.urls
https://gcc.gnu.org/g:591bc70139d898c06b1d605ff4fed591ffd2e2e7
commit r15-692-g591bc70139d898c06b1d605ff4fed591ffd2e2e7
Author: Mark Wielaard
Date: Mon May 20 13:13:02 2024 +0200
Regenerate riscv.opt.urls and i386.opt.urls
risc-v added an -mfence-tso option. i386 removed Xeon Phi ISA support
options. But the opt.urls files weren't regenerated.
Fixes: a6114c2a6911 ("RISC-V: Implement -m{,no}fence-tso")
Fixes: e1a7e2c54d52 ("i386: Remove Xeon Phi ISA support")
gcc/ChangeLog:
* config/riscv/riscv.opt.urls: Regenerate.
* config/i386/i386.opt.urls: Likewise.
Diff:
---
gcc/config/i386/i386.opt.urls | 15 ---
gcc/config/riscv/riscv.opt.urls | 3 +++
2 files changed, 3 insertions(+), 15 deletions(-)
diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls
index 81c5bb9a9270..40e8a8449367 100644
--- a/gcc/config/i386/i386.opt.urls
+++ b/gcc/config/i386/i386.opt.urls
@@ -238,12 +238,6 @@ UrlSuffix(gcc/x86-Options.html#index-mavx2)
mavx512f
UrlSuffix(gcc/x86-Options.html#index-mavx512f)
-mavx512pf
-UrlSuffix(gcc/x86-Options.html#index-mavx512pf)
-
-mavx512er
-UrlSuffix(gcc/x86-Options.html#index-mavx512er)
-
mavx512cd
UrlSuffix(gcc/x86-Options.html#index-mavx512cd)
@@ -262,12 +256,6 @@ UrlSuffix(gcc/x86-Options.html#index-mavx512ifma)
mavx512vbmi
UrlSuffix(gcc/x86-Options.html#index-mavx512vbmi)
-mavx5124fmaps
-UrlSuffix(gcc/x86-Options.html#index-mavx5124fmaps)
-
-mavx5124vnniw
-UrlSuffix(gcc/x86-Options.html#index-mavx5124vnniw)
-
mavx512vpopcntdq
UrlSuffix(gcc/x86-Options.html#index-mavx512vpopcntdq)
@@ -409,9 +397,6 @@ UrlSuffix(gcc/x86-Options.html#index-mrdrnd)
mf16c
UrlSuffix(gcc/x86-Options.html#index-mf16c)
-mprefetchwt1
-UrlSuffix(gcc/x86-Options.html#index-mprefetchwt1)
-
mfentry
UrlSuffix(gcc/x86-Options.html#index-mfentry)
diff --git a/gcc/config/riscv/riscv.opt.urls b/gcc/config/riscv/riscv.opt.urls
index 2f01ae5d6271..e02ef3ee3dd9 100644
--- a/gcc/config/riscv/riscv.opt.urls
+++ b/gcc/config/riscv/riscv.opt.urls
@@ -91,3 +91,6 @@ UrlSuffix(gcc/RISC-V-Options.html#index-minline-strlen)
; skipping UrlSuffix for 'mtls-dialect=' due to finding no URLs
+mfence-tso
+UrlSuffix(gcc/RISC-V-Options.html#index-mfence-tso)
+
[gcc r15-691] aarch64: Preparatory patch to place target independent and dependent changed code in one file
https://gcc.gnu.org/g:a974f37d854411628895225cf09952970bc2e86a
commit r15-691-ga974f37d854411628895225cf09952970bc2e86a
Author: Ajit Kumar Agarwal
Date: Mon May 20 04:09:37 2024 -0500
aarch64: Preparatory patch to place target independent and dependent
changed code in one file
Common infrastructure of load store pair fusion is divided into target
independent and target dependent changed code.
Target independent code is the Generic code with pure virtual function
to interface betwwen target independent and dependent code.
Target dependent code is the implementation of pure virtual function for
aarch64 target and the call to target independent code.
2024-05-20 Ajit Kumar Agarwal
gcc/ChangeLog:
* config/aarch64/aarch64-ldp-fusion.cc: Factor out a
target-independent interface and move it to the head of the file
Diff:
---
gcc/config/aarch64/aarch64-ldp-fusion.cc | 555 +--
1 file changed, 373 insertions(+), 182 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-ldp-fusion.cc
b/gcc/config/aarch64/aarch64-ldp-fusion.cc
index 1d9caeab05d4..6b2a44f101bf 100644
--- a/gcc/config/aarch64/aarch64-ldp-fusion.cc
+++ b/gcc/config/aarch64/aarch64-ldp-fusion.cc
@@ -138,6 +138,235 @@ struct alt_base
poly_int64 offset;
};
+// Virtual base class for load/store walkers used in alias analysis.
+struct alias_walker
+{
+ virtual bool conflict_p (int &budget) const = 0;
+ virtual insn_info *insn () const = 0;
+ virtual bool valid () const = 0;
+ virtual void advance () = 0;
+};
+
+// When querying should_handle_writeback, this enum is used to
+// qualify which opportunities we are asking about.
+enum class writeback {
+ // Only those writeback opportunities that arise from existing
+ // auto-increment accesses.
+ EXISTING,
+
+ // All writeback opportunities, including those that involve folding
+ // base register updates into a non-writeback pair.
+ ALL
+};
+
+// This class can be overriden by targets to give a pass that fuses
+// adjacent loads and stores into load/store pair instructions.
+//
+// The target can override the various virtual functions to customize
+// the behaviour of the pass as appropriate for the target.
+struct pair_fusion {
+ pair_fusion ();
+
+ // Given:
+ // - an rtx REG_OP, the non-memory operand in a load/store insn,
+ // - a machine_mode MEM_MODE, the mode of the MEM in that insn, and
+ // - a boolean LOAD_P (true iff the insn is a load), then:
+ // return true if the access should be considered an FP/SIMD access.
+ // Such accesses are segregated from GPR accesses, since we only want
+ // to form pairs for accesses that use the same register file.
+ virtual bool fpsimd_op_p (rtx, machine_mode, bool)
+ {
+return false;
+ }
+
+ // Return true if we should consider forming pairs from memory
+ // accesses with operand mode MODE at this stage in compilation.
+ virtual bool pair_operand_mode_ok_p (machine_mode mode) = 0;
+
+ // Return true iff REG_OP is a suitable register operand for a paired
+ // memory access, where LOAD_P is true if we're asking about loads and
+ // false for stores. MODE gives the mode of the operand.
+ virtual bool pair_reg_operand_ok_p (bool load_p, rtx reg_op,
+ machine_mode mode) = 0;
+
+ // Return alias check limit.
+ // This is needed to avoid unbounded quadratic behaviour when
+ // performing alias analysis.
+ virtual int pair_mem_alias_check_limit () = 0;
+
+ // Return true if we should try to handle writeback opportunities.
+ // WHICH determines the kinds of writeback opportunities the caller
+ // is asking about.
+ virtual bool should_handle_writeback (enum writeback which) = 0;
+
+ // Given BASE_MEM, the mem from the lower candidate access for a pair,
+ // and LOAD_P (true if the access is a load), check if we should proceed
+ // to form the pair given the target's code generation policy on
+ // paired accesses.
+ virtual bool pair_mem_ok_with_policy (rtx base_mem, bool load_p) = 0;
+
+ // Generate the pattern for a paired access. PATS gives the patterns
+ // for the individual memory accesses (which by this point must share a
+ // common base register). If WRITEBACK is non-NULL, then this rtx
+ // describes the update to the base register that should be performed by
+ // the resulting insn. LOAD_P is true iff the accesses are loads.
+ virtual rtx gen_pair (rtx *pats, rtx writeback, bool load_p) = 0;
+
+ // Return true if INSN is a paired memory access. If so, set LOAD_P to
+ // true iff INSN is a load pair.
+ virtual bool pair_mem_insn_p (rtx_insn *insn, bool &load_p) = 0;
+
+ // Return true if we should track loads.
+ virtual bool track_loads_p ()
+ {
+return true;
+ }
+
+ // Return true if we should track stores.
+ virtual bool track_stores_p ()
+ {
+return true;
+ }
+
+ // Return true if OFFSET is in range for a paired memory a
[gcc r15-684] ada: Add Is_Base_Type predicate to C interface
https://gcc.gnu.org/g:aecb63d075838e17673e1b13f21a414d23fcf2cd commit r15-684-gaecb63d075838e17673e1b13f21a414d23fcf2cd Author: Eric Botcazou Date: Fri Mar 29 09:03:28 2024 +0100 ada: Add Is_Base_Type predicate to C interface This also documents what the predicate effectively does. gcc/ada/ * einfo-utils.ads (Is_Base_Type): Move to Miscellaneous Subprograms section and add description. * fe.h (Is_Base_Type): Declare. Diff: --- gcc/ada/einfo-utils.ads | 8 ++-- gcc/ada/fe.h| 4 +++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gcc/ada/einfo-utils.ads b/gcc/ada/einfo-utils.ads index d87a3e34f493..01953c35bc34 100644 --- a/gcc/ada/einfo-utils.ads +++ b/gcc/ada/einfo-utils.ads @@ -183,8 +183,6 @@ package Einfo.Utils is function Has_Null_Abstract_State (Id : E) return B; function Has_Null_Visible_Refinement (Id : E) return B; function Implementation_Base_Type (Id : E) return E; - function Is_Base_Type (Id : E) return B with Inline; - -- Note that Is_Base_Type returns True for nontypes function Is_Boolean_Type (Id : E) return B with Inline; function Is_Constant_Object (Id : E) return B with Inline; function Is_Controlled (Id : E) return B with Inline; @@ -504,6 +502,12 @@ package Einfo.Utils is -- is the name of a class_wide type whose root is incomplete, return the -- corresponding full declaration, else return T itself. + function Is_Base_Type (Id : E) return B with Inline; + -- Return True for a type entity and False for a subtype entity. Note that + -- this returns True for nontypes. + + -- WARNING: There is a matching C declaration of this subprogram in fe.h + function Is_Entity_Name (N : Node_Id) return Boolean with Inline; -- Test if the node N is the name of an entity (i.e. is an identifier, -- expanded name, or an attribute reference that returns an entity). diff --git a/gcc/ada/fe.h b/gcc/ada/fe.h index 692c29a70aff..b4c1aea5c8b2 100644 --- a/gcc/ada/fe.h +++ b/gcc/ada/fe.h @@ -98,9 +98,11 @@ extern void Set_Normalized_First_Bit (Entity_Id, Uint); extern void Set_Normalized_Position(Entity_Id, Uint); extern void Set_RM_Size(Entity_Id, Uint); +#define Is_Base_Type einfo__utils__is_base_type #define Is_Entity_Name einfo__utils__is_entity_name -extern Boolean Is_Entity_Name (Node_Id); +extern Boolean Is_Base_Type(Entity_Id); +extern Boolean Is_Entity_Name (Node_Id); #define Get_Attribute_Definition_Clause einfo__utils__get_attribute_definition_clause
[gcc r15-687] ada: Fix internal error on nested aggregate in conditional expression
https://gcc.gnu.org/g:bfa743ddc9fd1850a7cc282afe5f3101b544ac64 commit r15-687-gbfa743ddc9fd1850a7cc282afe5f3101b544ac64 Author: Eric Botcazou Date: Fri Mar 29 17:46:43 2024 +0100 ada: Fix internal error on nested aggregate in conditional expression This plugs a loophole in the change improving code generation for nested aggregates present in conditional expressions: once the delayed expansion is chosen for the nested aggregate, the expansion of the parent aggregate cannot be left to the back-end and the test must be adjusted to implement this in the presence of conditional expressions too. gcc/ada/ * exp_aggr.adb (Expand_Record_Aggregate.Component_OK_For_Backend): Also return False for a delayed conditional expression. Diff: --- gcc/ada/exp_aggr.adb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb index a386aa85ae43..796b0f1e0de1 100644 --- a/gcc/ada/exp_aggr.adb +++ b/gcc/ada/exp_aggr.adb @@ -8376,7 +8376,9 @@ package body Exp_Aggr is Static_Components := False; return False; -elsif Is_Delayed_Aggregate (Expr_Q) then +elsif Is_Delayed_Aggregate (Expr_Q) + or else Is_Delayed_Conditional_Expression (Expr_Q) +then Static_Components := False; return False;
[gcc r15-688] ada: Add direct workaround for limitations of RTSfind mechanism
https://gcc.gnu.org/g:49eb34ea61c6e8fbb10d3a36484cbf5468580fba commit r15-688-g49eb34ea61c6e8fbb10d3a36484cbf5468580fba Author: Eric Botcazou Date: Sat Mar 30 23:12:51 2024 +0100 ada: Add direct workaround for limitations of RTSfind mechanism This adds a direct workaround for the spurious compilation errors caused by the presence of preconditions/postconditions in the Interfaces.C unit, which trip on limitations of the RTSfind mechanism when it comes to visibility, as well as removes an indirect workaround that was added very recently. These errors were first triggered in the context of finalization and worked around by preloading the System.Finalization_Primitives unit. Now they also appear in the context of tasking, and it turns out that the preloading trick does not work for separate compilation units. gcc/ada/ * exp_ch7.ads (Preload_Finalization_Collection): Delete. * exp_ch7.adb (Allows_Finalization_Collection): Revert change. (Preload_Finalization_Collection): Delete. * opt.ads (Interface_Seen): Likewise. * scng.adb (Scan): Revert latest change. * sem_ch10.adb: Remove clause for Exp_Ch7. (Analyze_Compilation_Unit): Revert latest change. * libgnat/i-c.ads: Use a fully qualified name for the standard "+" operator in the preconditons/postconditions of subprograms. Diff: --- gcc/ada/exp_ch7.adb | 38 -- gcc/ada/exp_ch7.ads | 6 -- gcc/ada/libgnat/i-c.ads | 19 +++ gcc/ada/opt.ads | 4 gcc/ada/scng.adb| 5 + gcc/ada/sem_ch10.adb| 3 --- 6 files changed, 12 insertions(+), 63 deletions(-) diff --git a/gcc/ada/exp_ch7.adb b/gcc/ada/exp_ch7.adb index fdacf1cdc012..993c13c73187 100644 --- a/gcc/ada/exp_ch7.adb +++ b/gcc/ada/exp_ch7.adb @@ -965,12 +965,6 @@ package body Exp_Ch7 is if Restriction_Active (No_Finalization) then return False; - -- The System.Finalization_Primitives unit must have been preloaded if - -- finalization is really required. - - elsif not RTU_Loaded (System_Finalization_Primitives) then - return False; - -- Do not consider C and C++ types since it is assumed that the non-Ada -- side will handle their cleanup. @@ -8630,38 +8624,6 @@ package body Exp_Ch7 is return Scope_Stack.Table (Scope_Stack.Last).Node_To_Be_Wrapped; end Node_To_Be_Wrapped; - -- - -- Preload_Finalization_Collection -- - -- - - procedure Preload_Finalization_Collection (Compilation_Unit : Node_Id) is - begin - -- We can't call RTE (Finalization_Collection) for at least some - -- predefined units, because it would introduce cyclic dependences, - -- as the type is itself a controlled type. - -- - -- It's only needed when finalization is involved in the unit, which - -- requires the presence of controlled or class-wide types in the unit - -- (see the Sem_Util.Needs_Finalization predicate for the rationale). - -- But controlled types are tagged or contain tagged (sub)components - -- so it is sufficient for the parser to detect the "interface" and - -- "tagged" keywords. - -- - -- Don't do it if Finalization_Collection is unavailable in the runtime - - if not In_Predefined_Unit (Compilation_Unit) -and then (Interface_Seen or else Tagged_Seen) -and then not No_Run_Time_Mode -and then RTE_Available (RE_Finalization_Collection) - then - declare -Ignore : constant Entity_Id := RTE (RE_Finalization_Collection); - begin -null; - end; - end if; - end Preload_Finalization_Collection; - -- Store_Actions_In_Scope -- diff --git a/gcc/ada/exp_ch7.ads b/gcc/ada/exp_ch7.ads index 386a02b9283a..712671a427e0 100644 --- a/gcc/ada/exp_ch7.ads +++ b/gcc/ada/exp_ch7.ads @@ -257,12 +257,6 @@ package Exp_Ch7 is -- Build a call to suppress the finalization of the object Obj, only after -- creating the Master_Node of Obj if it does not already exist. - procedure Preload_Finalization_Collection (Compilation_Unit : Node_Id); - -- Call RTE (RE_Finalization_Collection) if necessary to load the packages - -- involved in finalization support. We need to do this explicitly, fairly - -- early during compilation, because otherwise it happens during freezing, - -- which triggers visibility bugs in generic instantiations. - -- Task and Protected Object finalization -- diff --git a/gcc/ada/libgnat/i-c.ads b/gcc/ada/libgnat/i-c.ads index fe87fba32b60..f9f9f75fc037 100644 --- a/gcc/ada/libgn
[gcc r15-685] ada: Formal package comment corrections in sinfo.ads
https://gcc.gnu.org/g:cee232f4bf2e7d6891ec68c0100ecc5063e3e748
commit r15-685-gcee232f4bf2e7d6891ec68c0100ecc5063e3e748
Author: Bob Duff
Date: Fri Mar 29 12:17:56 2024 -0400
ada: Formal package comment corrections in sinfo.ads
Misc comment corrections and clarifications in sinfo.ads
related to generic formal packages.
gcc/ada/
* sinfo.ads: Misc comment corrections and clarifications.
The syntax for GENERIC_ASSOCIATION and FORMAL_PACKAGE_ACTUAL_PART
was wrong.
Emphasize that "others => <>" is not represented as an
N_Generic_Association (with or without Box_Present set),
and give examples illustrating the various possibilities.
Diff:
---
gcc/ada/sinfo.ads | 61 +--
1 file changed, 46 insertions(+), 15 deletions(-)
diff --git a/gcc/ada/sinfo.ads b/gcc/ada/sinfo.ads
index 228082eb823e..599f4f63cce0 100644
--- a/gcc/ada/sinfo.ads
+++ b/gcc/ada/sinfo.ads
@@ -1574,9 +1574,9 @@ package Sinfo is
-- Instance_Spec
--This field is present in generic instantiation nodes, and also in
--formal package declaration nodes (formal package declarations are
- --treated in a manner very similar to package instantiations). It points
- --to the node for the spec of the instance, inserted as part of the
- --semantic processing for instantiations in Sem_Ch12.
+ --treated similarly to package instantiations). It points to the node
+ --for the spec of the instance, inserted as part of the semantic
+ --processing for instantiations in Sem_Ch12.
-- Is_Abort_Block
--Present in N_Block_Statement nodes. True if the block protects a list
@@ -3639,8 +3639,8 @@ package Sinfo is
-- The only choice that appears explicitly is the OTHERS choice, as
-- defined here. Other cases of discrete choice (expression and
- -- discrete range) appear directly. This production is also used
- -- for the OTHERS possibility of an exception choice.
+ -- discrete range) appear directly. N_Others_Choice is also used
+ -- in exception handlers and generic formal packages.
-- Note: in accordance with the syntax, the parser does not check that
-- OTHERS appears at the end on its own in a choice list context. This
@@ -7139,6 +7139,7 @@ package Sinfo is
-- GENERIC_ASSOCIATION ::=
--[generic_formal_parameter_SELECTOR_NAME =>]
+ -- EXPLICIT_GENERIC_ACTUAL_PARAMETER
-- Note: unlike the procedure call case, a generic association node
-- is generated for every association, even if no formal parameter
@@ -7149,7 +7150,8 @@ package Sinfo is
-- In Ada 2005, a formal may be associated with a box, if the
-- association is part of the list of actuals for a formal package.
-- If the association is given by OTHERS => <>, the association is
- -- an N_Others_Choice.
+ -- an N_Others_Choice (not an N_Generic_Association whose Selector_Name
+ -- is an N_Others_Choice).
-- N_Generic_Association
-- Sloc points to first token of generic association
@@ -7442,7 +7444,7 @@ package Sinfo is
-- Defining_Identifier
-- Name
-- Generic_Associations (set to No_List if (<>) case or
- -- empty generic actual part)
+ -- empty formal package actual part)
-- Box_Present
-- Instance_Spec
-- Is_Known_Guaranteed_ABE
@@ -7452,21 +7454,50 @@ package Sinfo is
--
-- FORMAL_PACKAGE_ACTUAL_PART ::=
- --([OTHERS] => <>)
+ --([OTHERS =>] <>)
--| [GENERIC_ACTUAL_PART]
- --(FORMAL_PACKAGE_ASSOCIATION {. FORMAL_PACKAGE_ASSOCIATION}
+ --| (FORMAL_PACKAGE_ASSOCIATION {, FORMAL_PACKAGE_ASSOCIATION}
+ --[, OTHERS => <>])
-- FORMAL_PACKAGE_ASSOCIATION ::=
-- GENERIC_ASSOCIATION
-- | GENERIC_FORMAL_PARAMETER_SELECTOR_NAME => <>
-- There is no explicit node in the tree for a formal package actual
- -- part. Instead the information appears in the parent node (i.e. the
- -- formal package declaration node itself).
-
- -- There is no explicit node for a formal package association. All of
- -- them are represented either by a generic association, possibly with
- -- Box_Present, or by an N_Others_Choice.
+ -- part, nor for a formal package association. A formal package
+ -- association is represented as a generic association, possibly with
+ -- Box_Present.
+ --
+ -- The "others => <>" syntax (both cases) is represented as an
+ -- N_Others_Choice (not an N_Generic_Association whose Selector_Name
+ -- is an N_Others_Choice). This admittedly odd representation does not
+ -- lose information, because "others" cannot be followed by anything
[gcc r15-686] ada: Get rid of secondary stack for indefinite record types with size clause
https://gcc.gnu.org/g:efc7ba5f8f113565b47214d0ffdb27a6638ab8b6 commit r15-686-gefc7ba5f8f113565b47214d0ffdb27a6638ab8b6 Author: Eric Botcazou Date: Fri Mar 29 13:29:54 2024 +0100 ada: Get rid of secondary stack for indefinite record types with size clause This change eliminates the use of the secondary stack for indefinite record types for which a valid (object) size clause is specified. In accordance with the RM, the compiler accepts (object) size clauses on such types only if all the components, including those of the variants of the variant part if any, have a size known at compile time, and only if the clauses specify a value that is at least as large as the largest possible size of objects of the types when all the variants are considered. However, it would still have used the secondary stack, despite valid (object) size clauses, before the change, as soon as a variant part was present in the types. gcc/ada/ * freeze.ads (Check_Compile_Time_Size): Remove obsolete description of usage for the Size_Known_At_Compile_Time flag. * freeze.adb (Check_Compile_Time_Size.Size_Known): In the case where a variant part is present, do not return False if Esize is known. * sem_util.adb (Needs_Secondary_Stack.Caller_Known_Size_Record): Add missing "Start of processing" comment. Return true if either a size clause or an object size clause has been given for the first subtype of the type. Diff: --- gcc/ada/freeze.adb | 1 + gcc/ada/freeze.ads | 11 +-- gcc/ada/sem_util.adb | 12 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/gcc/ada/freeze.adb b/gcc/ada/freeze.adb index 26e9d01d8b20..ea6106e6455a 100644 --- a/gcc/ada/freeze.adb +++ b/gcc/ada/freeze.adb @@ -1077,6 +1077,7 @@ package body Freeze is and then No (Discriminant_Default_Value (First_Discriminant (T))) and then not Known_RM_Size (T) +and then not Known_Esize (T) then return False; end if; diff --git a/gcc/ada/freeze.ads b/gcc/ada/freeze.ads index fc0b7678fdcc..066d8f054f6f 100644 --- a/gcc/ada/freeze.ads +++ b/gcc/ada/freeze.ads @@ -156,17 +156,16 @@ package Freeze is --RM_Size field is set to the required size, allowing for possible front --end packing of an array using this type as a component type. -- - -- Note: the flag Size_Known_At_Compile_Time is used to determine if the - -- secondary stack must be used to return a value of the type, and also - -- to determine whether a component clause is allowed for a component - -- of the given type. - -- - -- Note: this is public because of one dubious use in Sem_Res??? + -- Note: the flag Size_Known_At_Compile_Time is used to determine whether a + -- size clause is allowed for the type, and also whether a component clause + -- is allowed for a component of the type. -- -- Note: Check_Compile_Time_Size does not test the case of the size being -- known because a size clause is specifically given. That is because we -- do not allow a size clause if the size would not otherwise be known at -- compile time in any case. + -- + -- ??? This is public because of dubious uses in Sem_Ch3 and Sem_Res procedure Check_Inherited_Conditions (R : Entity_Id; diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb index 09358278210e..15994b4d1e9c 100644 --- a/gcc/ada/sem_util.adb +++ b/gcc/ada/sem_util.adb @@ -22409,6 +22409,8 @@ package body Sem_Util is return False; end Depends_On_Discriminant; + -- Start of processing for Caller_Known_Size_Record + begin -- This is a protected type without Corresponding_Record_Type set, -- typically because expansion is disabled. The safe thing to do is @@ -22418,6 +22420,16 @@ package body Sem_Util is return True; end if; + -- If either size is specified for the type, then it's known in the + -- caller in particular. Note that, even if the clause is confirming, + -- this does not change the outcome since the size was already known. + + if Has_Size_Clause (First_Subtype (Typ)) + or else Has_Object_Size_Clause (First_Subtype (Typ)) + then +return True; + end if; + -- First see if we have a variant part and return False if it depends -- on discriminants.
[gcc r15-682] ada: Error on instantiation of generic containing legal container aggregate
https://gcc.gnu.org/g:d1e3aae37894079ebd0be2a6baccce5a89a251c3
commit r15-682-gd1e3aae37894079ebd0be2a6baccce5a89a251c3
Author: Gary Dismukes
Date: Tue Mar 26 01:01:57 2024 +
ada: Error on instantiation of generic containing legal container aggregate
When a container aggregate for a predefined container type (such as
a Vector type) that has an iterated component association occurs within
a generic unit and that generic is instantiated, the compiler reports
a spurious error message "iterated component association can only appear
in an array aggregate" and the compilation aborts (because
Unrecoverable_Error
is raised unconditionally after that error). The problem is that as part of
the instantiation process, for aggregates whose type has a partial view,
in Copy_Generic_Node the compiler switches the visibility so that the full
view of the type is available, and for a type whose full view is a record
type this leads to incorrectly trying to process the aggregate as a record
aggregate in Resolve_Aggregate (making a call to Resolve_Record_Aggregate).
Rather than trying to address this by changing what Copy_Generic_Node does,
this can be fixed by reordering and adjusting the code in Resolve_Aggregate,
so that we first test whether we need to resolve as a record aggregate
(if the aggregate is not homogeneous), followed by testing whether the
type has an Aggregate aspect and calling Resolve_Container_Aggregate.
As a bonus, we also remove the subsequent complex condition and redundant
code for handling null container aggregates.
gcc/ada/
* sem_aggr.adb (Resolve_Aggregate): Move condition and call for
Resolve_Record_Aggregate in front of code related to calling
Resolve_Container_Aggregate (and add test that the aggregate
is not homogeneous), and remove special-case testing and call
to Resolve_Container_Aggregate for empty aggregates.
Diff:
---
gcc/ada/sem_aggr.adb | 22 +-
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git a/gcc/ada/sem_aggr.adb b/gcc/ada/sem_aggr.adb
index 658b3a4634c4..6e40e5c25649 100644
--- a/gcc/ada/sem_aggr.adb
+++ b/gcc/ada/sem_aggr.adb
@@ -1182,8 +1182,12 @@ package body Sem_Aggr is
elsif Is_Array_Type (Typ) and then Null_Record_Present (N) then
Error_Msg_N ("null record forbidden in array aggregate", N);
+ elsif Is_Record_Type (Typ)
+and then not Is_Homogeneous_Aggregate (N)
+ then
+ Resolve_Record_Aggregate (N, Typ);
+
elsif Has_Aspect (Typ, Aspect_Aggregate)
-and then Ekind (Typ) /= E_Record_Type
and then Ada_Version >= Ada_2022
then
-- Check for Ada 2022 and () aggregate.
@@ -1194,22 +1198,6 @@ package body Sem_Aggr is
Resolve_Container_Aggregate (N, Typ);
- -- Check Ada 2022 empty aggregate [] initializing a record type that has
- -- aspect aggregate; the empty aggregate will be expanded into a call to
- -- the empty function specified in the aspect aggregate.
-
- elsif Has_Aspect (Typ, Aspect_Aggregate)
-and then Ekind (Typ) = E_Record_Type
-and then Is_Homogeneous_Aggregate (N)
-and then Is_Empty_List (Expressions (N))
-and then Is_Empty_List (Component_Associations (N))
-and then Ada_Version >= Ada_2022
- then
- Resolve_Container_Aggregate (N, Typ);
-
- elsif Is_Record_Type (Typ) then
- Resolve_Record_Aggregate (N, Typ);
-
elsif Is_Array_Type (Typ) then
-- First a special test, for the case of a positional aggregate of
[gcc r15-681] ada: Handle accessibility calculations for 'First and 'Last
https://gcc.gnu.org/g:b226e5605a6e1833da85590b10a5acf0b16d00d8 commit r15-681-gb226e5605a6e1833da85590b10a5acf0b16d00d8 Author: Justin Squirek Date: Wed Mar 27 01:02:41 2024 + ada: Handle accessibility calculations for 'First and 'Last This patch fixes a crash in the compiler whereby calculating the accessibility level of of a local variable whose original expression is an 'First on an array type led to an error during compilation. gcc/ada/ * accessibility.adb (Accessibility_Level): Add cases for 'First and 'Last. Diff: --- gcc/ada/accessibility.adb | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/gcc/ada/accessibility.adb b/gcc/ada/accessibility.adb index c0a9d50f38ab..33ce001718a2 100644 --- a/gcc/ada/accessibility.adb +++ b/gcc/ada/accessibility.adb @@ -465,7 +465,15 @@ package body Accessibility is -- so handle these cases explicitly. elsif Attribute_Name (E) -in Name_Old | Name_Loop_Entry | Name_Result | Name_Super +in Name_Old| + Name_Loop_Entry | + Name_Result | + Name_Super | + Name_Tag| + Name_Safe_First | + Name_Safe_Last | + Name_First | + Name_Last then -- Named access types
[gcc r15-680] ada: Further refine 'Super attribute
https://gcc.gnu.org/g:fd5a221928bb0689f7ff7eadc295970bf58392a5
commit r15-680-gfd5a221928bb0689f7ff7eadc295970bf58392a5
Author: Justin Squirek
Date: Tue Mar 26 15:02:58 2024 +
ada: Further refine 'Super attribute
This patch relaxes the restriction on 'Super such that it can apply to
abstract
type objects.
gcc/ada/
* sem_attr.adb (Analyze_Attribute): Remove restriction on 'Super
for abstract types.
Diff:
---
gcc/ada/sem_attr.adb | 4
1 file changed, 4 deletions(-)
diff --git a/gcc/ada/sem_attr.adb b/gcc/ada/sem_attr.adb
index df52229b6aaf..403810c8b5ec 100644
--- a/gcc/ada/sem_attr.adb
+++ b/gcc/ada/sem_attr.adb
@@ -6683,10 +6683,6 @@ package body Sem_Attr is
elsif Depends_On_Private (P_Type) then
Error_Attr_P ("prefix type of % is a private extension");
--- Check that we don't view convert to an abstract type
-
-elsif Is_Abstract_Type (Node (First_Elmt (Parents))) then
- Error_Attr_P ("type of % cannot be abstract");
end if;
-- Generate a view conversion and analyze it
[gcc r15-679] ada: Fix list of implementation-defined attributes
https://gcc.gnu.org/g:ea65d5b38051aca5071157092546665c446cef60 commit r15-679-gea65d5b38051aca5071157092546665c446cef60 Author: Piotr Trojanek Date: Mon Mar 25 23:00:13 2024 +0100 ada: Fix list of implementation-defined attributes Several of the implementation-defined attributes were wrongly recognized as defined by the Ada RM. This change only affects code with restriction No_Implementation_Attributes. gcc/ada/ * sem_attr.ads (Attribute_Impl_Def): Fix list of implementation-defined attributes. Diff: --- gcc/ada/sem_attr.ads | 27 +++ 1 file changed, 27 insertions(+) diff --git a/gcc/ada/sem_attr.ads b/gcc/ada/sem_attr.ads index 40ec423c4c78..52359e40ef68 100644 --- a/gcc/ada/sem_attr.ads +++ b/gcc/ada/sem_attr.ads @@ -609,6 +609,33 @@ package Sem_Attr is -- for constructing this definition in package System (see note above -- in Default_Bit_Order description). This is a static attribute. + Attribute_Atomic_Always_Lock_Free| + Attribute_Bit_Position | + Attribute_Compiler_Version | + Attribute_Descriptor_Size| + Attribute_Enabled| + Attribute_Fast_Math | + Attribute_From_Any | + Attribute_Has_Access_Values | + Attribute_Has_Tagged_Values | + Attribute_Initialized| + Attribute_Library_Level | + Attribute_Pool_Address | + Attribute_Restriction_Set| + Attribute_Scalar_Storage_Order | + Attribute_Simple_Storage_Pool| + Attribute_Small_Denominator | + Attribute_Small_Numerator| + Attribute_System_Allocator_Alignment | + Attribute_To_Any | + Attribute_TypeCode | + Attribute_Type_Key | + Attribute_Unconstrained_Array| + Attribute_Update | + Attribute_Valid_Value| + Attribute_Wchar_T_Size => True, + -- See description in GNAT RM + others => False); -- The following table lists all attributes that yield a result of a
[gcc r15-678] ada: Fix list of attributes defined by Ada 2012
https://gcc.gnu.org/g:95a13b096df2aa6dc096f65846d6c19067552792 commit r15-678-g95a13b096df2aa6dc096f65846d6c19067552792 Author: Piotr Trojanek Date: Mon Mar 25 22:52:14 2024 +0100 ada: Fix list of attributes defined by Ada 2012 Recognize references to attributes Old, Overlaps_Storage and Result as language-defined in Ada 2012 and implementation-defined in earlier versions of Ada. Other attributes introduced by Ada 2012 RM are correctly categorized. This change only affects code with restriction No_Implementation_Attributes. gcc/ada/ * sem_attr.adb (Attribute_12): Add attributes Old, Overlaps_Storage and Result. Diff: --- gcc/ada/sem_attr.adb | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/gcc/ada/sem_attr.adb b/gcc/ada/sem_attr.adb index 414224e86b69..df52229b6aaf 100644 --- a/gcc/ada/sem_attr.adb +++ b/gcc/ada/sem_attr.adb @@ -170,7 +170,10 @@ package body Sem_Attr is (Attribute_First_Valid | Attribute_Has_Same_Storage | Attribute_Last_Valid | - Attribute_Max_Alignment_For_Allocation => True, + Attribute_Max_Alignment_For_Allocation | + Attribute_Old | + Attribute_Overlaps_Storage | + Attribute_Result => True, others => False); -- The following array is the list of attributes defined in the Ada 2022
[gcc r15-689] ada: Allow 'others' in formal packages with overloaded formals
https://gcc.gnu.org/g:b3cfe6e88ffcc636d83e4ac5708065c3131e1766
commit r15-689-gb3cfe6e88ffcc636d83e4ac5708065c3131e1766
Author: Bob Duff
Date: Mon Apr 1 14:05:14 2024 -0400
ada: Allow 'others' in formal packages with overloaded formals
If a generic package has two or more generic formal parameters with the
same defining name (which can happen only for formal subprograms), then
RM-12.7(4.1/3) disallows named associations in a corresponding formal
package. This is not intended to cover "others => <>".
This patch allows "others => <>" even when it applies to such
formals. Previously, the compiler incorrectly gave an error.
Minor related cleanups involving type Text_Ptr.
gcc/ada/
* sem_ch12.adb: Misc cleanups and comment fixes.
(Check_Overloaded_Formal_Subprogram): Remove the Others_Choice
error message.
(Others_Choice): Remove this variable; no longer needed.
* types.ads (Text_Ptr): Add a range constraint limiting the
subtype to values that are actually used. This has the advantage
that when the compiler is compiled with validity checks,
uninitialized values of subtypes Text_Ptr and Source_Ptr will be
caught.
* sinput.ads (Sloc_Adjust): Use the base subtype; this is used as
an offset, so we need to allow arbitrary negative values.
Diff:
---
gcc/ada/sem_ch12.adb | 27 ++-
gcc/ada/sinput.ads | 2 +-
gcc/ada/types.ads| 7 +++
3 files changed, 14 insertions(+), 22 deletions(-)
diff --git a/gcc/ada/sem_ch12.adb b/gcc/ada/sem_ch12.adb
index 4ceddda20526..9919cda6340c 100644
--- a/gcc/ada/sem_ch12.adb
+++ b/gcc/ada/sem_ch12.adb
@@ -1130,10 +1130,11 @@ package body Sem_Ch12 is
Saved_Formal: Node_Id;
Default_Formals : constant List_Id := New_List;
- -- If an Others_Choice is present, some of the formals may be defaulted.
- -- To simplify the treatment of visibility in an instance, we introduce
- -- individual defaults for each such formal. These defaults are
- -- appended to the list of associations and replace the Others_Choice.
+ -- If an N_Others_Choice is present, some of the formals may be
+ -- defaulted. To simplify the treatment of visibility in an instance,
+ -- we introduce individual defaults for each such formal. These
+ -- defaults are appended to the list of associations and replace the
+ -- N_Others_Choice.
Found_Assoc : Node_Id;
-- Association for the current formal being match. Empty if there are
@@ -1145,9 +1146,8 @@ package body Sem_Ch12 is
Num_Actuals: Nat := 0;
Others_Present : Boolean := False;
- Others_Choice : Node_Id := Empty;
-- In Ada 2005, indicates partial parameterization of a formal
- -- package. As usual an other association must be last in the list.
+ -- package. As usual an 'others' association must be last in the list.
procedure Build_Subprogram_Wrappers;
-- Ada 2022: AI12-0272 introduces pre/postconditions for formal
@@ -1195,7 +1195,7 @@ package body Sem_Ch12 is
procedure Process_Default (Formal : Node_Id);
-- Add a copy of the declaration of a generic formal to the list of
-- associations, and add an explicit box association for its entity
- -- if there is none yet, and the default comes from an Others_Choice.
+ -- if there is none yet, and the default comes from an N_Others_Choice.
function Renames_Standard_Subprogram (Subp : Entity_Id) return Boolean;
-- Determine whether Subp renames one of the subprograms defined in the
@@ -1314,14 +1314,8 @@ package body Sem_Ch12 is
Error_Msg_N
("named association not allowed for overloaded formal",
Found_Assoc);
-
- else
- Error_Msg_N
-("named association not allowed for overloaded formal",
- Others_Choice);
+ Abandon_Instantiation (Instantiation_Node);
end if;
-
- Abandon_Instantiation (Instantiation_Node);
end if;
Next (Temp_Formal);
@@ -1592,7 +1586,7 @@ package body Sem_Ch12 is
Append (Decl, Assoc_List);
- if No (Found_Assoc) then
+ if No (Found_Assoc) then -- i.e. 'others'
Default :=
Make_Generic_Association (Loc,
Selector_Name =>
@@ -1686,7 +1680,6 @@ package body Sem_Ch12 is
while Present (Actual) loop
if Nkind (Actual) = N_Others_Choice then
Others_Present := True;
- Others_Choice := Actual;
if Present (Next (Actual)) then
Error_Msg_N ("OTHERS must be last association", Actual);
@@ -2311,7 +2304,7 @@ package bod
[gcc r15-676] ada: Remove repeated condition in check for implementation attributes
https://gcc.gnu.org/g:4ed963a52a0a7349f0beb765ee0802857d1752eb
commit r15-676-g4ed963a52a0a7349f0beb765ee0802857d1752eb
Author: Piotr Trojanek
Date: Mon Mar 25 22:50:47 2024 +0100
ada: Remove repeated condition in check for implementation attributes
Code cleanup; semantics is unaffected.
gcc/ada/
* sem_attr.adb (Analyze_Attribute): Remove condition that is
already checked by an enclosing IF statement.
Diff:
---
gcc/ada/sem_attr.adb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/ada/sem_attr.adb b/gcc/ada/sem_attr.adb
index 2b22cf13ad00..6c32d201c55c 100644
--- a/gcc/ada/sem_attr.adb
+++ b/gcc/ada/sem_attr.adb
@@ -3225,7 +3225,7 @@ package body Sem_Attr is
if Comes_From_Source (N) then
if not Attribute_83 (Attr_Id) then
-if Ada_Version = Ada_83 and then Comes_From_Source (N) then
+if Ada_Version = Ada_83 then
Error_Msg_Name_1 := Aname;
Error_Msg_N ("(Ada 83) attribute% is not standard??", N);
end if;
[gcc r15-683] ada: Error on instantiation of generic containing legal container aggregate
https://gcc.gnu.org/g:a74dff4d9d0b26e91d02acb81e9ed2e34d0d38e9
commit r15-683-ga74dff4d9d0b26e91d02acb81e9ed2e34d0d38e9
Author: Gary Dismukes
Date: Tue Mar 26 22:36:02 2024 +
ada: Error on instantiation of generic containing legal container aggregate
When a container aggregate for a predefined container type (such as
a Vector type) that has an iterated component association occurs within
a generic unit and that generic is instantiated, the compiler reports
a spurious error message "iterated component association can only appear
in an array aggregate" and the compilation aborts (because
Unrecoverable_Error
is raised unconditionally after that error). The problem is that as part of
the instantiation process, for aggregates whose type has a partial view,
in Copy_Generic_Node the compiler switches the visibility so that the full
view of the type is available, and for a type whose full view is a record
type this leads to incorrectly trying to process the aggregate as a record
aggregate in Resolve_Aggregate (making a call to Resolve_Record_Aggregate).
Rather than trying to address this by changing what Copy_Generic_Node does,
this can be fixed by reordering and adjusting the code in Resolve_Aggregate,
so that we first test whether we need to resolve as a record aggregate
(if the aggregate is not homogeneous), followed by testing whether the
type has an Aggregate aspect and calling Resolve_Container_Aggregate.
As a bonus, we also remove the subsequent complex condition and redundant
code for handling null container aggregates.
gcc/ada/
* sem_aggr.adb (Resolve_Aggregate): Move condition and call for
Resolve_Record_Aggregate in front of code related to calling
Resolve_Container_Aggregate (and add test that the aggregate is
not homogeneous), and remove special-case testing and call to
Resolve_Container_Aggregate for empty aggregates. Also, add error
check for an attempt to use "[]" for an aggregate of a record type
that does not specify an Aggregate aspect.
(Resolve_Record_Aggregate): Remove error check for record
aggregates with "[]" (now done by Resolve_Aggregate).
Diff:
---
gcc/ada/sem_aggr.adb | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/gcc/ada/sem_aggr.adb b/gcc/ada/sem_aggr.adb
index 6e40e5c25649..60738550ec1f 100644
--- a/gcc/ada/sem_aggr.adb
+++ b/gcc/ada/sem_aggr.adb
@@ -1198,6 +1198,14 @@ package body Sem_Aggr is
Resolve_Container_Aggregate (N, Typ);
+ -- Check for an attempt to use "[]" for an aggregate of a record type
+ -- after handling the case where the type has an Aggregate aspect,
+ -- because the aspect can be specified for record types, but if it
+ -- wasn't specified, then this is an error.
+
+ elsif Is_Record_Type (Typ) and then Is_Homogeneous_Aggregate (N) then
+ Error_Msg_N ("record aggregate must use (), not '[']", N);
+
elsif Is_Array_Type (Typ) then
-- First a special test, for the case of a positional aggregate of
@@ -5518,15 +5526,6 @@ package body Sem_Aggr is
return;
end if;
- -- A record aggregate can only use parentheses
-
- if Nkind (N) = N_Aggregate
-and then Is_Homogeneous_Aggregate (N)
- then
- Error_Msg_N ("record aggregate must use (), not '[']", N);
- return;
- end if;
-
-- STEP 2: Verify aggregate structure
Step_2 : declare
[gcc r15-675] ada: Use discrete choice list in declaration of universal type attributes
https://gcc.gnu.org/g:766a3934c13d2732de3af2c219cae399e94a4470 commit r15-675-g766a3934c13d2732de3af2c219cae399e94a4470 Author: Piotr Trojanek Date: Mon Mar 25 23:01:32 2024 +0100 ada: Use discrete choice list in declaration of universal type attributes Code cleanup. gcc/ada/ * sem_attr.ads (Universal_Type_Attribute): Simplify using array aggregate syntax with discrete choice list. Diff: --- gcc/ada/sem_attr.ads | 62 ++-- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/gcc/ada/sem_attr.ads b/gcc/ada/sem_attr.ads index d18bd5b06678..40ec423c4c78 100644 --- a/gcc/ada/sem_attr.ads +++ b/gcc/ada/sem_attr.ads @@ -615,37 +615,37 @@ package Sem_Attr is -- universal type. Universal_Type_Attribute : constant array (Attribute_Id) of Boolean := - (Attribute_Aft => True, - Attribute_Alignment=> True, - Attribute_Component_Size => True, - Attribute_Count=> True, - Attribute_Delta=> True, - Attribute_Digits => True, - Attribute_Exponent => True, - Attribute_First_Bit=> True, - Attribute_Fore => True, - Attribute_Last_Bit => True, - Attribute_Length => True, - Attribute_Machine_Emax => True, - Attribute_Machine_Emin => True, - Attribute_Machine_Mantissa => True, - Attribute_Machine_Radix=> True, - Attribute_Max_Alignment_For_Allocation => True, - Attribute_Max_Size_In_Storage_Elements => True, - Attribute_Model_Emin => True, - Attribute_Model_Epsilon=> True, - Attribute_Model_Mantissa => True, - Attribute_Model_Small => True, - Attribute_Modulus => True, - Attribute_Pos => True, - Attribute_Position => True, - Attribute_Safe_First => True, - Attribute_Safe_Last=> True, - Attribute_Scale=> True, - Attribute_Size => True, - Attribute_Small=> True, - Attribute_Wide_Wide_Width => True, - Attribute_Wide_Width => True, + (Attribute_Aft | + Attribute_Alignment| + Attribute_Component_Size | + Attribute_Count| + Attribute_Delta| + Attribute_Digits | + Attribute_Exponent | + Attribute_First_Bit| + Attribute_Fore | + Attribute_Last_Bit | + Attribute_Length | + Attribute_Machine_Emax | + Attribute_Machine_Emin | + Attribute_Machine_Mantissa | + Attribute_Machine_Radix| + Attribute_Max_Alignment_For_Allocation | + Attribute_Max_Size_In_Storage_Elements | + Attribute_Model_Emin | + Attribute_Model_Epsilon| + Attribute_Model_Mantissa | + Attribute_Model_Small | + Attribute_Modulus | + Attribute_Pos | + Attribute_Position | + Attribute_Safe_First | + Attribute_Safe_Last| + Attribute_Scale| + Attribute_Size | + Attribute_Small| + Attribute_Wide_Wide_Width | + Attribute_Wide_Width | Attribute_Width=> True, others => False);
[gcc r15-673] ada: Tweak handling of thread ID on POSIX
https://gcc.gnu.org/g:0d119fb79e884c9ee5e1ccbbb98311780f92413d commit r15-673-g0d119fb79e884c9ee5e1ccbbb98311780f92413d Author: Ronan Desplanques Date: Mon Mar 25 14:36:56 2024 +0100 ada: Tweak handling of thread ID on POSIX This patch changes the task initialization subprograms on POSIX platforms so that the thread ID of an ATCB is only set once. This has the advantage of getting rid of the Atomic aspect on the corresponding record component, and silences a Helgrind warning about a data race. gcc/ada/ * libgnarl/s-taprop__linux.adb (Enter_Task): Move setting of thread ID out of Enter_Task. (Initialize): Set thread ID for the environment task. (Create_Task): Remove now unnecessary Unrestricted_Access attribute and add justification for a memory write. * libgnarl/s-taprop__posix.adb: Likewise. * libgnarl/s-taprop__qnx.adb: Likewise. * libgnarl/s-taprop__rtems.adb: Likewise. * libgnarl/s-taprop__solaris.adb: Likewise. * libgnarl/s-taspri__posix.ads: Remove pragma Atomic for Private_Data.Thread, and update documentation comment. * libgnarl/s-taspri__lynxos.ads: Likewise. * libgnarl/s-taspri__posix-noaltstack.ads: Likewise. * libgnarl/s-taspri__solaris.ads: Likewise. * libgnarl/s-tporft.adb (Register_Foreign_Thread): Adapt to Enter_Task not setting the thread ID anymore. * libgnarl/s-tassta.adb (Task_Wrapper): Update comment. Diff: --- gcc/ada/libgnarl/s-taprop__linux.adb| 14 +++--- gcc/ada/libgnarl/s-taprop__posix.adb| 14 +++--- gcc/ada/libgnarl/s-taprop__qnx.adb | 14 +++--- gcc/ada/libgnarl/s-taprop__rtems.adb| 14 +++--- gcc/ada/libgnarl/s-taprop__solaris.adb | 16 gcc/ada/libgnarl/s-taspri__lynxos.ads | 16 ++-- gcc/ada/libgnarl/s-taspri__posix-noaltstack.ads | 16 ++-- gcc/ada/libgnarl/s-taspri__posix.ads| 16 ++-- gcc/ada/libgnarl/s-taspri__solaris.ads | 16 ++-- gcc/ada/libgnarl/s-tassta.adb | 2 +- gcc/ada/libgnarl/s-tporft.adb | 1 + 11 files changed, 78 insertions(+), 61 deletions(-) diff --git a/gcc/ada/libgnarl/s-taprop__linux.adb b/gcc/ada/libgnarl/s-taprop__linux.adb index 0c09817739ce..0a51b3601c07 100644 --- a/gcc/ada/libgnarl/s-taprop__linux.adb +++ b/gcc/ada/libgnarl/s-taprop__linux.adb @@ -730,7 +730,6 @@ package body System.Task_Primitives.Operations is raise Invalid_CPU_Number; end if; - Self_ID.Common.LL.Thread := pthread_self; Self_ID.Common.LL.LWP := lwp_self; -- Set thread name to ease debugging. If the name of the task is @@ -1004,14 +1003,14 @@ package body System.Task_Primitives.Operations is -- do not need to manipulate caller's signal mask at this point. -- All tasks in RTS will have All_Tasks_Mask initially. - -- Note: the use of Unrestricted_Access in the following call is needed - -- because otherwise we have an error of getting a access-to-volatile - -- value which points to a non-volatile object. But in this case it is - -- safe to do this, since we know we have no problems with aliasing and - -- Unrestricted_Access bypasses this check. + -- The write to T.Common.LL.Thread is not racy with regard to the + -- created thread because the created thread will not access it until + -- we release the RTS lock (or the current task's lock when + -- Restricted.Stages is used). One can verify that by inspecting the + -- Task_Wrapper procedures. Result := pthread_create -(T.Common.LL.Thread'Unrestricted_Access, +(T.Common.LL.Thread'Access, Thread_Attr'Access, Thread_Body_Access (Wrapper), To_Address (T)); @@ -1385,6 +1384,7 @@ package body System.Task_Primitives.Operations is begin Environment_Task_Id := Environment_Task; + Environment_Task.Common.LL.Thread := pthread_self; Interrupt_Management.Initialize; diff --git a/gcc/ada/libgnarl/s-taprop__posix.adb b/gcc/ada/libgnarl/s-taprop__posix.adb index 7ed52ea2d821..fb70aaf4976e 100644 --- a/gcc/ada/libgnarl/s-taprop__posix.adb +++ b/gcc/ada/libgnarl/s-taprop__posix.adb @@ -636,7 +636,6 @@ package body System.Task_Primitives.Operations is procedure Enter_Task (Self_ID : Task_Id) is begin - Self_ID.Common.LL.Thread := pthread_self; Self_ID.Common.LL.LWP := lwp_self; Specific.Set (Self_ID); @@ -841,14 +840,14 @@ package body System.Task_Primitives.Operations is -- do not need to manipulate caller's signal mask at this point. -- All tasks in RTS will have All_Tasks_Mask initially. - -- Note: the use of Unrestricted_
[gcc r15-672] ada: Extend expansion delaying mechanism to conditional expressions
https://gcc.gnu.org/g:103e7f3a94b85c18a134a0fd8893b85e548882cb commit r15-672-g103e7f3a94b85c18a134a0fd8893b85e548882cb Author: Eric Botcazou Date: Mon Mar 25 11:44:21 2024 +0100 ada: Extend expansion delaying mechanism to conditional expressions When an aggregate that needs to be converted into a series of assignments is present in an expression of a parent aggregate, or in the expression of an allocator, an object declaration, or an assignment in very specific cases, its expansion is delayed until its parent itself is expanded. This makes it possible to avoid creating a superfluous temporary for the aggregate. This change extends the delaying mechanism in the case of record aggregates to intermediate conditional expressions, that is to say, to the conditional expressions that are present between the parent and the aggregate, provided that the aggregate be a dependent expression, directly or recursively. This again makes it possible to avoid creating a temporary for the aggregate. gcc/ada/ * exp_aggr.ads (Is_Delayed_Conditional_Expression): New predicate. * exp_aggr.adb (Convert_To_Assignments.Known_Size): Likewise. (Convert_To_Assignments): Climb the parent chain, looking through qualified expressions and dependent expressions of conditional expressions, to find out whether the expansion may be delayed. Call Known_Size for this in the case of an object declaration. If so, set Expansion_Delayed on the aggregate as well as all the intermediate conditional expressions. (Initialize_Component): Reset the Analyzed flag on an initialization expression that is a conditional expression whose expansion has been delayed. (Is_Delayed_Conditional_Expression): New predicate. * exp_ch3.adb (Expand_N_Object_Declaration): Handle initialization expressions that are conditional expressions whose expansion has been delayed. * exp_ch4.adb (Build_Explicit_Assignment): New procedure. (Expand_Allocator_Expression): Handle initialization expressions that are conditional expressions whose expansion has been delayed. (Expand_N_Case_Expression): Deal with expressions whose expansion has been delayed by waiting for the rewriting of their parent as an assignment statement and then optimizing the assignment. (Expand_N_If_Expression): Likewise. (Expand_N_Qualified_Expression): Do not apply a predicate check to an operand that is a delayed aggregate or conditional expression. * gen_il-gen-gen_nodes.adb (N_If_Expression): Add Expansion_Delayed semantic flag. (N_Case_Expression): Likewise. * sinfo.ads (Expansion_Delayed): Document extended usage. Diff: --- gcc/ada/exp_aggr.adb | 201 -- gcc/ada/exp_aggr.ads | 4 + gcc/ada/exp_ch3.adb | 38 gcc/ada/exp_ch4.adb | 363 ++- gcc/ada/gen_il-gen-gen_nodes.adb | 4 +- gcc/ada/sinfo.ads| 4 + 6 files changed, 479 insertions(+), 135 deletions(-) diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb index 6208b49ffd99..a386aa85ae43 100644 --- a/gcc/ada/exp_aggr.adb +++ b/gcc/ada/exp_aggr.adb @@ -4216,84 +4216,152 @@ package body Exp_Aggr is procedure Convert_To_Assignments (N : Node_Id; Typ : Entity_Id) is Loc : constant Source_Ptr := Sloc (N); - Aggr_Code : List_Id; - Full_Typ: Entity_Id; - Instr : Node_Id; - Parent_Kind : Node_Kind; - Parent_Node : Node_Id; - Target_Expr : Node_Id; - Temp: Entity_Id; - Unc_Decl: Boolean := False; + function Known_Size (Decl : Node_Id; Cond_Init : Boolean) return Boolean; + -- Decl is an N_Object_Declaration node. Return true if it declares an + -- object with a known size; in this context, that is always the case, + -- except for a declaration without explicit constraints of an object, + -- either whose nominal subtype is class-wide, or whose initialization + -- contains a conditional expression and whose nominal subtype is both + -- discriminated and unconstrained. + + + -- Known_Size -- + + + function Known_Size (Decl : Node_Id; Cond_Init : Boolean) return Boolean + is + begin + if Is_Entity_Name (Object_Definition (Decl)) then +declare + Typ : constant Entity_Id := Entity (Object_Definition (Decl)); + +begin + return not Is_Class_Wide_Type (Typ) + and then not (Cond_Init +and then Has_Discriminants (Typ) +
[gcc r15-674] ada: Fix style in list of implementation-defined attributes
https://gcc.gnu.org/g:824755fcf4d82119c8ea7496e43eab7a88d17a2b commit r15-674-g824755fcf4d82119c8ea7496e43eab7a88d17a2b Author: Piotr Trojanek Date: Mon Mar 25 21:47:55 2024 +0100 ada: Fix style in list of implementation-defined attributes Code cleanup. gcc/ada/ * sem_attr.ads (Attribute_Impl_Def): Fix style in comment. Diff: --- gcc/ada/sem_attr.ads | 8 1 file changed, 8 insertions(+) diff --git a/gcc/ada/sem_attr.ads b/gcc/ada/sem_attr.ads index 0e7d1693682a..d18bd5b06678 100644 --- a/gcc/ada/sem_attr.ads +++ b/gcc/ada/sem_attr.ads @@ -288,6 +288,10 @@ package Sem_Attr is -- attribute is primarily intended for use in implementation of the -- standard input-output functions for fixed-point values. + + -- Invalid_Value -- + + Attribute_Invalid_Value => True, -- For every scalar type, S'Invalid_Value designates an undefined value -- of the type. If possible this value is an invalid value, and in fact @@ -298,6 +302,10 @@ package Sem_Attr is -- coding standards in use), but logically no initialization is needed, -- and the value should never be accessed. + + -- Loop_Entry -- + + Attribute_Loop_Entry => True, -- For every object of a non-limited type, S'Loop_Entry [(Loop_Name)] -- denotes the constant value of prefix S at the point of entry into the
[gcc r15-677] ada: Apply restriction No_Implementation_Attributes to source nodes only
https://gcc.gnu.org/g:32aa8b92c59d9c8343a618c7d1614bed7b0e107d commit r15-677-g32aa8b92c59d9c8343a618c7d1614bed7b0e107d Author: Piotr Trojanek Date: Mon Mar 25 22:49:58 2024 +0100 ada: Apply restriction No_Implementation_Attributes to source nodes only Restriction No_Implementation_Attributes must not be applied to nodes that come from expansion. In particular, it must not be applied to Object_Size, which is implementation-defined attribute before Ada 2022, but appears in expansion of tagged types since Ada 95. gcc/ada/ * sem_attr.adb (Analyze_Attribute): Move IF statement that checks restriction No_Implementation_Attributes for Ada 2005, 2012 and Ada 2022 attributes inside Comes_From_Source condition that checks the same restriction for Ada 83 attributes. Diff: --- gcc/ada/sem_attr.adb | 27 ++- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/gcc/ada/sem_attr.adb b/gcc/ada/sem_attr.adb index 6c32d201c55c..414224e86b69 100644 --- a/gcc/ada/sem_attr.adb +++ b/gcc/ada/sem_attr.adb @@ -3221,9 +3221,10 @@ package body Sem_Attr is Check_Restriction_No_Use_Of_Attribute (N); - -- Deal with Ada 83 issues - if Comes_From_Source (N) then + + -- Deal with Ada 83 issues + if not Attribute_83 (Attr_Id) then if Ada_Version = Ada_83 then Error_Msg_Name_1 := Aname; @@ -3234,19 +3235,19 @@ package body Sem_Attr is Check_Restriction (No_Implementation_Attributes, N); end if; end if; - end if; - -- Deal with Ada 2005 attributes that are implementation attributes - -- because they appear in a version of Ada before Ada 2005, ditto for - -- Ada 2012 and Ada 2022 attributes appearing in an earlier version. + -- Deal with Ada 2005 attributes that are implementation attributes + -- because they appear in a version of Ada before Ada 2005, ditto for + -- Ada 2012 and Ada 2022 attributes appearing in an earlier version. - if (Attribute_05 (Attr_Id) and then Ada_Version < Ada_2005) -or else - (Attribute_12 (Attr_Id) and then Ada_Version < Ada_2012) -or else - (Attribute_22 (Attr_Id) and then Ada_Version < Ada_2022) - then - Check_Restriction (No_Implementation_Attributes, N); + if (Attribute_05 (Attr_Id) and then Ada_Version < Ada_2005) + or else +(Attribute_12 (Attr_Id) and then Ada_Version < Ada_2012) + or else +(Attribute_22 (Attr_Id) and then Ada_Version < Ada_2022) + then +Check_Restriction (No_Implementation_Attributes, N); + end if; end if; -- Remote access to subprogram type access attribute reference needs
[gcc r15-690] Manually add ChangeLog entry for r15-575-gda73261ce7731be7f2b164f1db796878cdc23365
https://gcc.gnu.org/g:83d3a218dfb3b7730884ada7e607cf72891d4c11 commit r15-690-g83d3a218dfb3b7730884ada7e607cf72891d4c11 Author: Jakub Jelinek Date: Mon May 20 09:48:27 2024 +0200 Manually add ChangeLog entry for r15-575-gda73261ce7731be7f2b164f1db796878cdc23365 Diff: --- gcc/ChangeLog | 29 + 1 file changed, 29 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bfd2d42e287d..07aad1886112 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -359,6 +359,35 @@ (math_opts_dom_walker::after_dom_children): Try match saturation arith when IOR expr. +2024-05-16 Aldy Hernandez + + Revert: + 2024-05-10 Aldy Hernandez + + Revert: + 2024-05-08 Aldy Hernandez + + * gimple-range-cache.cc (sbr_sparse_bitmap::sbr_sparse_bitmap): + Change irange to prange. + * gimple-range-fold.cc (fold_using_range::fold_stmt): Same. + (fold_using_range::range_of_address): Same. + * gimple-range-fold.h (range_of_address): Same. + * gimple-range-infer.cc (gimple_infer_range::add_nonzero): Same. + * gimple-range-op.cc (class cfn_strlen): Same. + * gimple-range-path.cc + (path_range_query::adjust_for_non_null_uses): Same. + * gimple-ssa-warn-access.cc (pass_waccess::check_pointer_uses): Same. + * tree-ssa-structalias.cc (find_what_p_points_to): Same. + * range-op-ptr.cc (range_op_table::initialize_pointer_ops): Remove + hybrid entries in table. + * range-op.cc (range_op_table::range_op_table): Add pointer + entries for bitwise and/or and min/max. + * value-range.cc (irange::verify_range): Add assert. + * value-range.h (irange::varying_compatible_p): Remove check for + error_mark_node. + (irange::supports_p): Remove pointer support. + * ipa-cp.h (ipa_supports_p): Add prange support. + 2024-05-16 Aldy Hernandez PR tree-optimization/114985
[gcc r15-671] ada: Resolve ACATS compilation and execution issues with container aggregates
https://gcc.gnu.org/g:888a12b48a3ef50d467c04ccbe4cc9c937a8450e
commit r15-671-g888a12b48a3ef50d467c04ccbe4cc9c937a8450e
Author: Gary Dismukes
Date: Mon Mar 18 21:16:58 2024 +
ada: Resolve ACATS compilation and execution issues with container
aggregates
This change set addresses various compilation and execution problems
encountered in the draft ACATS tests for container aggregates:
C435001 (container aggregates with Assign_Indexed)
C435002 (container aggregates with Add_Unnamed)
C435003 (container aggregates with Add_Named)
C435004 (container aggregates with Assign_Indexed and Add_Unnamed)
gcc/ada/
* exp_aggr.adb (Expand_Container_Aggregate): Add top-level
variables Choice_{Lo|Hi} and Int_Choice_{Lo|Hi} used for
determining the low and high bounds of component association
choices. Replace code for determining whether we have an indexed
aggregate with call to new function Sem_Aggr.Is_Indexed_Aggregate.
Remove test of whether Empty_Subp is a function, since it must be
a function. Move Default and Count_Type to be locals of a new
block enclosing the code that creates the object to hold the
aggregate length, and set them according to the default and type
of the Empty function's parameter when present (and to Empty and
Standard_Natural otherwise). Use Siz_Exp for the aggregate length
when set, and use Empty's default length when available, and use
zero for the length otherwise. In generating the call to the
New_Indexed function, use the determined lower and upper bounds if
determined earlier by Aggregate_Size, and otherwise compute those
from the index type's lower bound and the determined aggregate
length. In the case where a call to Empty is generated and the
function has a formal parameter, pass the value saved in Siz_Decl
(otherwise the parameter list is empty). Remove code specific to
making a parameterless call to the Empty function. Extend the code
for handling positional container aggregates to account for types
that define Assign_Indexed, rather than just Add_Unnamed, and in
the case of indexed aggregates, create a temporary object to hold
values of the aggregate's key index, and initialize and increment
that temporary for each call generated to the Assign_Indexed
procedure. For named container aggregates that have key choices
given by ranges, call Expand_Range_Component to generate a loop
that will call the appropriate insertion procedure for each value
of the range. For indexed aggregates with a Component_Associations
list, set and use the Assign_Indexed procedure for each component
association, whether or not there's an iterator specification.
(Add_Range_Size): Add code to determine the low and high bounds of
the range and capture those in up-level variables when their value
is less than or greater than (respectively) the current minimum
and maximum bounds values.
(Aggregate_Size): Separately handle the case where a single choice
is of a discrete type, and call Add_Range_Size to take its value
into consideration for determination of min and max bounds of the
aggregate. Add comments in a couple of places.
(Build_Siz_Exp): Remove the last sentence and "???" from the
comment that talks about accumulating nonstatic sizes, since that
sentence seems to be obsolete. Record the low and high bound
values in Choice_Lo and Choice_Hi in the case of a nonstatic
range.
(Expand_Iterated_Component): Set the Defining_Identifier of the
iterator specification to the Loop_Id in the
N_Iterated_Component_Association case.
(Expand_Range_Component): Procedure unnested from the block
handling indexed aggregates in Expand_Container_Aggregate, and
moved to top level of that procedure so it can also be called for
Add_Named cases. A formal parameter Insert_Op is added, and
existing calls to this procedure are changed to pass the
appropriate insertion procedure's Entity.
* sem_aggr.ads: Add with_clause for Sinfo.Nodes.
(Is_Indexed_Aggregate): New function for use by
Resolve_Container_Aggregate and Expand_Container_Aggregate.
* sem_aggr.adb: Add with_clause for Sem_Ch5. Move with_clause for
Sinfo.Nodes to sem_aggr.ads.
(Is_Indexed_Aggregate): New function to determine whether a
container aggregate is a container aggregate (replacing local
variable of
[gcc r15-670] ada: Fix incorrect free with Task_Info pragma
https://gcc.gnu.org/g:37f4a6f2ac22b633191d02d90054b601a73c80fa commit r15-670-g37f4a6f2ac22b633191d02d90054b601a73c80fa Author: Ronan Desplanques Date: Mon Mar 25 10:12:17 2024 +0100 ada: Fix incorrect free with Task_Info pragma Before this patch, on Linux, the procedure System.Task_Primitives.Operations.Set_Task_Affinity called CPU_FREE on instances of cpu_set_t_ptr that it didn't own when the obsolescent Task_Info pragma was in play. This patch fixes that issue. gcc/ada/ * libgnarl/s-taprop__linux.adb (Set_Task_Affinity): Fix decision about whether to call CPU_FREE. Diff: --- gcc/ada/libgnarl/s-taprop__linux.adb | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/gcc/ada/libgnarl/s-taprop__linux.adb b/gcc/ada/libgnarl/s-taprop__linux.adb index 1faa3d8914e5..0c09817739ce 100644 --- a/gcc/ada/libgnarl/s-taprop__linux.adb +++ b/gcc/ada/libgnarl/s-taprop__linux.adb @@ -1466,12 +1466,13 @@ package body System.Task_Primitives.Operations is and then T.Common.LL.Thread /= Null_Thread_Id then declare -CPUs: constant size_t := -C.size_t (Multiprocessors.Number_Of_CPUs); -CPU_Set : cpu_set_t_ptr := null; -Size: constant size_t := CPU_ALLOC_SIZE (CPUs); +CPUs : constant size_t := + C.size_t (Multiprocessors.Number_Of_CPUs); +CPU_Set : cpu_set_t_ptr := null; +Is_Set_Owned : Boolean := False; +Size : constant size_t := CPU_ALLOC_SIZE (CPUs); -Result : C.int; +Result : C.int; begin -- We look at the specific CPU (Base_CPU) first, then at the @@ -1483,6 +1484,7 @@ package body System.Task_Primitives.Operations is -- Set the affinity to an unique CPU CPU_Set := CPU_ALLOC (CPUs); + Is_Set_Owned := True; System.OS_Interface.CPU_ZERO (Size, CPU_Set); System.OS_Interface.CPU_SET (int (T.Common.Base_CPU), Size, CPU_Set); @@ -1499,6 +1501,7 @@ package body System.Task_Primitives.Operations is -- dispatching domain. CPU_Set := CPU_ALLOC (CPUs); + Is_Set_Owned := True; System.OS_Interface.CPU_ZERO (Size, CPU_Set); for Proc in T.Common.Domain'Range loop @@ -1512,7 +1515,9 @@ package body System.Task_Primitives.Operations is pthread_setaffinity_np (T.Common.LL.Thread, Size, CPU_Set); pragma Assert (Result = 0); -CPU_FREE (CPU_Set); +if Is_Set_Owned then + CPU_FREE (CPU_Set); +end if; end; end if; end Set_Task_Affinity;
[gcc r15-669] ada: Another small cleanup about allocators and aggregates
https://gcc.gnu.org/g:727e7d69240d31215e0fcad9e91c1f67942e4500 commit r15-669-g727e7d69240d31215e0fcad9e91c1f67942e4500 Author: Eric Botcazou Date: Sat Mar 23 14:20:14 2024 +0100 ada: Another small cleanup about allocators and aggregates This eliminates a few more oddities present in the expander for allocators and aggregates nested in allocators and other constructs: - Convert_Aggr_In_Allocator takes both the N_Allocator and the aggregate as parameters, while the sibling procedures Convert_Aggr_In_Assignment and Convert_Aggr_In_Object_Decl only take the former. This changes the first to be consistent with the two others and propagates the change to Convert_Array_Aggr_In_Allocator. - Convert_Aggr_In_Object_Decl contains an awkward code structure with a useless inner block statement. - In_Place_Assign_OK and Convert_To_Assignments have some declarations of local variables not in the right place. No functional changes (presumably). gcc/ada/ * exp_aggr.ads (Convert_Aggr_In_Allocator): Remove Aggr parameter and adjust description. (Convert_Aggr_In_Object_Decl): Adjust description. * exp_aggr.adb (Convert_Aggr_In_Allocator): Remove Aggr parameter and add local variable of the same name instead. Adjust call to Convert_Array_Aggr_In_Allocator. (Convert_Aggr_In_Object_Decl): Add comment for early return and remove useless inner block statement. (Convert_Array_Aggr_In_Allocator): Remove Aggr parameter and add local variable of the same name instead. (In_Place_Assign_OK): Move down declarations of local variables. (Convert_To_Assignments): Put all declarations of local variables in the same place. Fix typo in comment. Replace T with Full_Typ. * exp_ch4.adb (Expand_Allocator_Expression): Call Unqualify instead of Expression on the qualified expression of the allocator for the sake of consistency. Adjust call to Convert_Aggr_In_Allocator. Diff: --- gcc/ada/exp_aggr.adb | 188 +-- gcc/ada/exp_aggr.ads | 18 +++-- gcc/ada/exp_ch4.adb | 4 +- 3 files changed, 104 insertions(+), 106 deletions(-) diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb index 2476675604cc..8a3d1685cb31 100644 --- a/gcc/ada/exp_aggr.adb +++ b/gcc/ada/exp_aggr.adb @@ -282,10 +282,7 @@ package body Exp_Aggr is --Indexes is the current list of expressions used to index the object we --are writing into. - procedure Convert_Array_Aggr_In_Allocator - (N : Node_Id; - Aggr : Node_Id; - Target : Node_Id); + procedure Convert_Array_Aggr_In_Allocator (N : Node_Id; Target : Node_Id); -- If the aggregate appears within an allocator and can be expanded in -- place, this routine generates the individual assignments to components -- of the designated object. This is an optimization over the general @@ -3543,11 +3540,8 @@ package body Exp_Aggr is -- Convert_Aggr_In_Allocator -- --- - procedure Convert_Aggr_In_Allocator - (N: Node_Id; - Aggr : Node_Id; - Temp : Entity_Id) - is + procedure Convert_Aggr_In_Allocator (N : Node_Id; Temp : Entity_Id) is + Aggr : constant Node_Id:= Unqualify (Expression (N)); Loc : constant Source_Ptr := Sloc (Aggr); Typ : constant Entity_Id := Etype (Aggr); @@ -3557,7 +3551,7 @@ package body Exp_Aggr is begin if Is_Array_Type (Typ) then - Convert_Array_Aggr_In_Allocator (N, Aggr, Occ); + Convert_Array_Aggr_In_Allocator (N, Occ); elsif Has_Default_Init_Comps (Aggr) then declare @@ -3605,12 +3599,9 @@ package body Exp_Aggr is Aggr : constant Node_Id:= Unqualify (Expression (N)); Loc : constant Source_Ptr := Sloc (Aggr); Typ : constant Entity_Id := Etype (Aggr); - Occ : constant Node_Id:= New_Occurrence_Of (Obj, Loc); - - Has_Transient_Scope : Boolean := False; function Discriminants_Ok return Boolean; - -- If the object type is constrained, the discriminants in the + -- If the object's subtype is constrained, the discriminants in the -- aggregate must be checked against the discriminants of the subtype. -- This cannot be done using Apply_Discriminant_Checks because after -- expansion there is no aggregate left to check. @@ -3677,10 +3668,19 @@ package body Exp_Aggr is return True; end Discriminants_Ok; + -- Local variables + + Has_Transient_Scope : Boolean; + Occ : Node_Id; + Param : Node_Id; + Stmt: Node_Id; + Stmts : List_Id; + -- Start of processing for Convert_Aggr_
[gcc r15-668] ada: Fix static 'Img for enumeration type with Discard_Names
https://gcc.gnu.org/g:9edbaab0f6eb83351ef65e5bc0e427a415e04915
commit r15-668-g9edbaab0f6eb83351ef65e5bc0e427a415e04915
Author: Piotr Trojanek
Date: Fri Mar 22 14:50:15 2024 +0100
ada: Fix static 'Img for enumeration type with Discard_Names
Fix a short-circuit folding of 'Img for enumeration type, which wrongly
ignored Discard_Names and exposed enumeration literals.
gcc/ada/
* sem_attr.adb (Eval_Attribute): Handle enumeration type with
Discard_Names.
Diff:
---
gcc/ada/sem_attr.adb | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/gcc/ada/sem_attr.adb b/gcc/ada/sem_attr.adb
index 96f216cc587d..2b22cf13ad00 100644
--- a/gcc/ada/sem_attr.adb
+++ b/gcc/ada/sem_attr.adb
@@ -8221,13 +8221,26 @@ package body Sem_Attr is
then
declare
Lit : constant Entity_Id := Expr_Value_E (P);
+Typ : constant Entity_Id := Etype (Entity (P));
Str : String_Id;
begin
Start_String;
-Get_Unqualified_Decoded_Name_String (Chars (Lit));
-Set_Casing (All_Upper_Case);
-Store_String_Chars (Name_Buffer (1 .. Name_Len));
+
+-- If Discard_Names is in effect for the type, then we emit the
+-- numeric representation of the prefix literal 'Pos attribute,
+-- prefixed with a single space.
+
+if Discard_Names (Typ) then
+ UI_Image (Enumeration_Pos (Lit), Decimal);
+ Store_String_Char (' ');
+ Store_String_Chars (UI_Image_Buffer (1 .. UI_Image_Length));
+else
+ Get_Unqualified_Decoded_Name_String (Chars (Lit));
+ Set_Casing (All_Upper_Case);
+ Store_String_Chars (Name_Buffer (1 .. Name_Len));
+end if;
+
Str := End_String;
Rewrite (N, Make_String_Literal (Loc, Strval => Str));
[gcc r15-667] ada: Fix for attribute Width on enumeration types with Discard_Name
https://gcc.gnu.org/g:fbe275e2458458ad517645d64619d3aac4467cf1 commit r15-667-gfbe275e2458458ad517645d64619d3aac4467cf1 Author: Piotr Trojanek Date: Wed Mar 20 23:19:35 2024 +0100 ada: Fix for attribute Width on enumeration types with Discard_Name Fix computation of attribute 'Width for enumeration types with Discard_Name aspect enabled. gcc/ada/ * exp_imgv.adb (Expand_Width_Attribute): Fix for 'Width that is computed at run time. * sem_attr.adb (Eval_Attribute): Fix for 'Width that is computed at compilation time. Diff: --- gcc/ada/exp_imgv.adb | 25 +++-- gcc/ada/sem_attr.adb | 7 --- 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/gcc/ada/exp_imgv.adb b/gcc/ada/exp_imgv.adb index 6dc59f2c6f33..e5d84cc52e34 100644 --- a/gcc/ada/exp_imgv.adb +++ b/gcc/ada/exp_imgv.adb @@ -2294,7 +2294,7 @@ package body Exp_Imgv is -- in the range of the subtype + 1 for the space at the start. We -- build: - -- Tnn : constant Integer := Rtyp'Pos (Ptyp'Last) + -- Tnn : constant Integer := Rtyp'Pos (Ptyp'Last); -- and replace the expression by @@ -2320,9 +2320,15 @@ package body Exp_Imgv is declare Tnn : constant Entity_Id := Make_Temporary (Loc, 'T'); Cexpr : Node_Id; - P : Int; - M : Int; - K : Int; + + P : constant Nat := + UI_To_Int (Enumeration_Pos (Entity (Type_High_Bound (Rtyp; + -- The largest value that might need to be represented + + K : Pos; + M : Pos; + -- K is the number of chars that will fit the image of 0..M-1; + -- M is the smallest number that won't fit in K chars. begin Insert_Action (N, @@ -2342,14 +2348,13 @@ package body Exp_Imgv is Attribute_Name => Name_Last)); -- OK, now we need to build the if expression. First get the - -- value of M, the largest possible value needed. + -- values of K and M for the largest possible value P. - P := UI_To_Int - (Enumeration_Pos (Entity (Type_High_Bound (Rtyp; + K := 2; + M := 10; + -- With 2 characters we can represent values in 0..9 - K := 1; - M := 1; - while M < P loop + while P >= M loop M := M * 10; K := K + 1; end loop; diff --git a/gcc/ada/sem_attr.adb b/gcc/ada/sem_attr.adb index a921909685a7..96f216cc587d 100644 --- a/gcc/ada/sem_attr.adb +++ b/gcc/ada/sem_attr.adb @@ -10906,9 +10906,10 @@ package body Sem_Attr is -- that accommodates the Pos of the largest value, which -- is the high bound of the range + one for the space. - W := 1; - T := Hi; - while T /= 0 loop + W := 1; -- one character for the leading space + W := W + 1; -- one character for the 0 .. 9 digit + T := Hi; -- one character for every decimal digit + while T >= 10 loop T := T / 10; W := W + 1; end loop;
[gcc r15-666] ada: Use System.Address for address computation in System.Pool_Global
https://gcc.gnu.org/g:16cdeadb33400238ea522541009ecd2a24769f0c commit r15-666-g16cdeadb33400238ea522541009ecd2a24769f0c Author: Sebastian Poeplau Date: Wed Mar 20 11:48:22 2024 +0100 ada: Use System.Address for address computation in System.Pool_Global Some architectures don't let us convert System.Storage_Elements.Integer_Address back to a valid System.Address. Using the arithmetic operations on System.Address from System.Storage_Elements prevents the problem while leaving semantics unchanged. gcc/ada/ * libgnat/s-pooglo.adb (Allocate): Use arithmetic on System.Address to compute the aligned address. Diff: --- gcc/ada/libgnat/s-pooglo.adb | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/gcc/ada/libgnat/s-pooglo.adb b/gcc/ada/libgnat/s-pooglo.adb index dea3de15cc51..9ce21c8fd0da 100644 --- a/gcc/ada/libgnat/s-pooglo.adb +++ b/gcc/ada/libgnat/s-pooglo.adb @@ -75,9 +75,10 @@ package body System.Pool_Global is -- Realign the returned address - Aligned_Address := To_Address - (To_Integer (Allocated) + Integer_Address (Alignment) - - (To_Integer (Allocated) mod Integer_Address (Alignment))); + Aligned_Address := + Allocated + Alignment + - Storage_Offset (To_Integer (Allocated) + mod Integer_Address (Alignment)); -- Save the block address
[gcc r15-665] ada: Reject too-strict alignment specifications.
https://gcc.gnu.org/g:caaf20e2678117861a7a4d1da712be91a94596b1
commit r15-665-gcaaf20e2678117861a7a4d1da712be91a94596b1
Author: Steve Baird
Date: Mon Mar 18 14:35:33 2024 -0700
ada: Reject too-strict alignment specifications.
For a discrete (or fixed-point) type T, GNAT requires that T'Object_Size
shall be a multiple of T'Alignment * 8 .
GNAT also requires that T'Object_Size shall be no larger than
Standard'Max_Integer_Size.
For a sufficiently-large alignment specification, these requirements can
conflict.
The conflict is resolved by rejecting such alignment specifications (which
were previously accepted in some cases).
gcc/ada/
* freeze.adb (Adjust_Esize_For_Alignment): Assert that a valid
Alignment specification cannot result in adjusting the given
type's Esize to be larger than System_Max_Integer_Size.
* sem_ch13.adb (Analyze_Attribute_Definition_Clause): In analyzing
an Alignment specification, enforce the rule that a specified
Alignment value for a discrete or fixed-point type shall not be
larger than System_Max_Integer_Size / 8 .
gcc/testsuite/ChangeLog:
* gnat.dg/specs/alignment2.ads: Adjust.
* gnat.dg/specs/alignment2_bis.ads: New test.
Diff:
---
gcc/ada/freeze.adb | 8 --
gcc/ada/sem_ch13.adb | 15 +++
gcc/testsuite/gnat.dg/specs/alignment2.ads | 14 --
gcc/testsuite/gnat.dg/specs/alignment2_bis.ads | 36 ++
4 files changed, 57 insertions(+), 16 deletions(-)
diff --git a/gcc/ada/freeze.adb b/gcc/ada/freeze.adb
index a980c7e5b47a..26e9d01d8b20 100644
--- a/gcc/ada/freeze.adb
+++ b/gcc/ada/freeze.adb
@@ -303,8 +303,12 @@ package body Freeze is
if Known_Esize (Typ) and then Known_Alignment (Typ) then
Align := Alignment_In_Bits (Typ);
- if Align > Esize (Typ) and then Align <= System_Max_Integer_Size then
-Set_Esize (Typ, Align);
+ if Align > Esize (Typ) then
+if Align > System_Max_Integer_Size then
+ pragma Assert (Serious_Errors_Detected > 0);
+else
+ Set_Esize (Typ, Align);
+end if;
end if;
end if;
end Adjust_Esize_For_Alignment;
diff --git a/gcc/ada/sem_ch13.adb b/gcc/ada/sem_ch13.adb
index 13bf93ca5489..59c80022c206 100644
--- a/gcc/ada/sem_ch13.adb
+++ b/gcc/ada/sem_ch13.adb
@@ -6573,6 +6573,21 @@ package body Sem_Ch13 is
("alignment for & set to Maximum_Aligment??", Nam);
Set_Alignment (U_Ent, Max_Align);
+ -- Because Object_Size must be multiple of Alignment (in bits),
+ -- System_Max_Integer_Size limit for discrete and fixed point
+ -- types implies a limit on alignment for such types.
+
+ elsif (Is_Discrete_Type (U_Ent)
+or else Is_Fixed_Point_Type (U_Ent))
+ and then Align > System_Max_Integer_Size / System_Storage_Unit
+ then
+ Error_Msg_N
+("specified alignment too large for discrete or fixed " &
+ "point type", Expr);
+ Set_Alignment
+(U_Ent, UI_From_Int (System_Max_Integer_Size /
+ System_Storage_Unit));
+
-- All other cases
else
diff --git a/gcc/testsuite/gnat.dg/specs/alignment2.ads
b/gcc/testsuite/gnat.dg/specs/alignment2.ads
index 0b6c14f1b7d4..75a002e9bee4 100644
--- a/gcc/testsuite/gnat.dg/specs/alignment2.ads
+++ b/gcc/testsuite/gnat.dg/specs/alignment2.ads
@@ -32,18 +32,4 @@ package Alignment2 is
end record;
for R4'Alignment use 32;
- -- warning
- type I1 is new Integer_32;
- for I1'Size use 32;
- for I1'Alignment use 32; -- { dg-warning "suspiciously large alignment" }
-
- -- warning
- type I2 is new Integer_32;
- for I2'Alignment use 32; -- { dg-warning "suspiciously large alignment" }
-
- -- OK, big size
- type I3 is new Integer_32;
- for I3'Size use 32 * 8; -- { dg-warning "unused" }
- for I3'Alignment use 32;
-
end Alignment2;
diff --git a/gcc/testsuite/gnat.dg/specs/alignment2_bis.ads
b/gcc/testsuite/gnat.dg/specs/alignment2_bis.ads
new file mode 100644
index ..ad31a400b846
--- /dev/null
+++ b/gcc/testsuite/gnat.dg/specs/alignment2_bis.ads
@@ -0,0 +1,36 @@
+-- { dg-do compile }
+
+with Interfaces; use Interfaces;
+
+package Alignment2_Bis is
+
+ pragma Warnings (Off, "*size*");
+
+ -- OK, big size
+ type R3 is record
+A, B, C, D : Integer_8;
+ end record;
+ for R3'Size use 32 * 8;
+ for R3'Alignment use 32;
+
+ -- OK, big size
+ type R4 is record
+A, B, C, D, E, F, G, H : Integer_32;
+ end record;
+ for R4'Alignment use 32;
+
+ -- warning
+ type I1 is new Integer_32;
+ for I1'Size use 32;
[gcc r15-664] ada: One more adjustment coming from aliasing considerations
https://gcc.gnu.org/g:eef3025547ce55cbf6a9018b495ef5c9a562047a commit r15-664-geef3025547ce55cbf6a9018b495ef5c9a562047a Author: Eric Botcazou Date: Tue Mar 19 10:56:34 2024 +0100 ada: One more adjustment coming from aliasing considerations It is needed on PowerPC platforms because of specific calling conventions. gcc/ada/ * libgnat/g-sothco.ads (In_Addr): Add aspect Universal_Aliasing. Diff: --- gcc/ada/libgnat/g-sothco.ads | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/ada/libgnat/g-sothco.ads b/gcc/ada/libgnat/g-sothco.ads index 8c2193336491..da1e6f5bcddf 100644 --- a/gcc/ada/libgnat/g-sothco.ads +++ b/gcc/ada/libgnat/g-sothco.ads @@ -123,10 +123,13 @@ package GNAT.Sockets.Thin_Common is type In_Addr is record S_B1, S_B2, S_B3, S_B4 : C.unsigned_char; - end record with Convention => C, Alignment => C.int'Alignment; + end record + with Convention => C, Alignment => C.int'Alignment, Universal_Aliasing; -- IPv4 address, represented as a network-order C.int. Note that the -- underlying operating system may assume that values of this type have - -- C.int alignment, so we need to provide a suitable alignment clause here. + -- C.int's alignment, so we need to provide a suitable alignment clause. + -- We also need to inhibit strict type-based aliasing optimizations in + -- order to implement the following unchecked conversions efficiently. function To_In_Addr is new Ada.Unchecked_Conversion (C.int, In_Addr); function To_Int is new Ada.Unchecked_Conversion (In_Addr, C.int);
[gcc r15-663] ada: Detect only conflict with synomyms of max queue length
https://gcc.gnu.org/g:d6a10f8173ca9f390cd87691477fa147d4404f3b
commit r15-663-gd6a10f8173ca9f390cd87691477fa147d4404f3b
Author: Jose Ruiz
Date: Thu Mar 7 19:16:18 2024 +0100
ada: Detect only conflict with synomyms of max queue length
Use of duplicated representation aspect is detected elsewhere
so we do not try to detect them here to avoid repetition of
messages.
gcc/ada/
* sem_prag.adb (Analyze_Pragma): Exclude detection of duplicates
because they are detected elsewhere.
Diff:
---
gcc/ada/sem_prag.adb | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/gcc/ada/sem_prag.adb b/gcc/ada/sem_prag.adb
index 0e2ce9de4b53..a895fd2053ac 100644
--- a/gcc/ada/sem_prag.adb
+++ b/gcc/ada/sem_prag.adb
@@ -20388,15 +20388,23 @@ package body Sem_Prag is
("pragma % must apply to a protected entry declaration");
end if;
--- Check for duplicates
+-- Check for conflicting use of synonyms. Note that we exclude
+-- the detection of duplicates here because they are detected
+-- elsewhere.
-if Has_Rep_Pragma (Entry_Id, Name_Max_Entry_Queue_Length)
+if (Has_Rep_Pragma (Entry_Id, Name_Max_Entry_Queue_Length)
+ and then
+Prag_Id /= Pragma_Max_Entry_Queue_Length)
or else
- Has_Rep_Pragma (Entry_Id, Name_Max_Entry_Queue_Depth)
+ (Has_Rep_Pragma (Entry_Id, Name_Max_Entry_Queue_Depth)
+ and then
+Prag_Id /= Pragma_Max_Entry_Queue_Depth)
or else
- Has_Rep_Pragma (Entry_Id, Name_Max_Queue_Length)
+ (Has_Rep_Pragma (Entry_Id, Name_Max_Queue_Length)
+ and then
+Prag_Id /= Pragma_Max_Queue_Length)
then
- Error_Msg_N ("??duplicate Max_Entry_Queue_Length pragma", N);
+ Error_Msg_N ("??maximum entry queue length already set", N);
end if;
-- Mark the pragma as Ghost if the related subprogram is also
[gcc r15-662] ada: Implement representation aspect Max_Entry_Queue_Length
https://gcc.gnu.org/g:bf941670685fd8d646ae8955c3bb086d1512bac2
commit r15-662-gbf941670685fd8d646ae8955c3bb086d1512bac2
Author: Jose Ruiz
Date: Thu Mar 7 11:20:03 2024 +0100
ada: Implement representation aspect Max_Entry_Queue_Length
Enforce Max_Entry_Queue_Length (and its
synonym Max_Entry_Queue_Depth) when applied to individual
protected entries.
gcc/ada/
* exp_ch9.adb (Expand_N_Protected_Type_Declaration): Clarify
comments.
* sem_prag.adb (Analyze_Pragma): Check for duplicates
Max_Entry_Queue_Length, Max_Entry_Queue_Depth and Max_Queue_Length
for the same protected entry.
* sem_util.adb (Get_Max_Queue_Length): Take into account all three
representation aspects that can be used to set this restriction.
(Has_Max_Queue_Length): Likewise.
* doc/gnat_rm/implementation_defined_pragmas.rst:
(pragma Max_Queue_Length): Fix pragma in example.
* gnat_rm.texi: Regenerate.
Diff:
---
.../doc/gnat_rm/implementation_defined_pragmas.rst | 2 +-
gcc/ada/exp_ch9.adb| 6 ++--
gcc/ada/gnat_rm.texi | 2 +-
gcc/ada/sem_prag.adb | 11
gcc/ada/sem_util.adb | 33 --
5 files changed, 41 insertions(+), 13 deletions(-)
diff --git a/gcc/ada/doc/gnat_rm/implementation_defined_pragmas.rst
b/gcc/ada/doc/gnat_rm/implementation_defined_pragmas.rst
index bcbd85984dc0..0661670e0475 100644
--- a/gcc/ada/doc/gnat_rm/implementation_defined_pragmas.rst
+++ b/gcc/ada/doc/gnat_rm/implementation_defined_pragmas.rst
@@ -3771,7 +3771,7 @@ Pragma Max_Queue_Length
Syntax::
- pragma Max_Entry_Queue (static_integer_EXPRESSION);
+ pragma Max_Queue_Length (static_integer_EXPRESSION);
This pragma is used to specify the maximum callers per entry queue for
diff --git a/gcc/ada/exp_ch9.adb b/gcc/ada/exp_ch9.adb
index 051b1df060f8..4de253ab6e83 100644
--- a/gcc/ada/exp_ch9.adb
+++ b/gcc/ada/exp_ch9.adb
@@ -9405,7 +9405,8 @@ package body Exp_Ch9 is
end loop;
-- Create the declaration of an array object which contains the values
- -- of aspect/pragma Max_Queue_Length for all entries of the protected
+ -- of any aspect/pragma Max_Queue_Length, Max_Entry_Queue_Length or
+ -- Max_EntryQueue_Depth for all entries of the protected
-- type. This object is later passed to the appropriate protected object
-- initialization routine.
@@ -9422,7 +9423,8 @@ package body Exp_Ch9 is
Need_Array : Boolean := False;
begin
--- First check if there is any Max_Queue_Length pragma
+-- First check if there is any Max_Queue_Length,
+-- Max_Entry_Queue_Length or Max_Entry_Queue_Depth pragma.
Item := First_Entity (Prot_Typ);
while Present (Item) loop
diff --git a/gcc/ada/gnat_rm.texi b/gcc/ada/gnat_rm.texi
index 40516121b7ab..4dbbb036a259 100644
--- a/gcc/ada/gnat_rm.texi
+++ b/gcc/ada/gnat_rm.texi
@@ -5312,7 +5312,7 @@ no effect in GNAT, other than being syntax checked.
Syntax:
@example
-pragma Max_Entry_Queue (static_integer_EXPRESSION);
+pragma Max_Queue_Length (static_integer_EXPRESSION);
@end example
This pragma is used to specify the maximum callers per entry queue for
diff --git a/gcc/ada/sem_prag.adb b/gcc/ada/sem_prag.adb
index f27e40edcbbf..0e2ce9de4b53 100644
--- a/gcc/ada/sem_prag.adb
+++ b/gcc/ada/sem_prag.adb
@@ -20388,6 +20388,17 @@ package body Sem_Prag is
("pragma % must apply to a protected entry declaration");
end if;
+-- Check for duplicates
+
+if Has_Rep_Pragma (Entry_Id, Name_Max_Entry_Queue_Length)
+ or else
+ Has_Rep_Pragma (Entry_Id, Name_Max_Entry_Queue_Depth)
+ or else
+ Has_Rep_Pragma (Entry_Id, Name_Max_Queue_Length)
+then
+ Error_Msg_N ("??duplicate Max_Entry_Queue_Length pragma", N);
+end if;
+
-- Mark the pragma as Ghost if the related subprogram is also
-- Ghost. This also ensures that any expansion performed further
-- below will produce Ghost nodes.
diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index d512d462b443..09358278210e 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -10714,26 +10714,38 @@ package body Sem_Util is
function Get_Max_Queue_Length (Id : Entity_Id) return Uint is
pragma Assert (Is_Entry (Id));
- Prag : constant Entity_Id := Get_Pragma (Id, Pragma_Max_Queue_Length);
- Max : Uint;
+ PMQL : constant Entity_Id := Get_Pragma (Id, Pragma_Max_Queue_Length);
+ PMEQD : constant Entity_Id :=
+ Get_Pragma (Id, Pragma_Max_Entry_Queue_Depth);
+ PMEQL : constant Entity_Id :=
+ Get_Pr
[gcc r15-661] ada: Small cleanup in System.Finalization_Primitives unit
https://gcc.gnu.org/g:bdf9ebb75880601bb67d63672d2e830005109f8e commit r15-661-gbdf9ebb75880601bb67d63672d2e830005109f8e Author: Eric Botcazou Date: Sat Mar 16 19:20:43 2024 +0100 ada: Small cleanup in System.Finalization_Primitives unit It has been made possible by recent changes. gcc/ada/ * libgnat/s-finpri.ads (Collection_Node): Move to private part. (Collection_Node_Ptr): Likewise. (Header_Alignment): Change to declaration and move completion to private part. (Header_Size): Likewise. (Lock_Type): Delete. (Finalization_Collection): Move Lock component and remove default value for Finalization_Started component. * libgnat/s-finpri.adb (Initialize): Reorder statements. Diff: --- gcc/ada/libgnat/s-finpri.adb | 4 ++-- gcc/ada/libgnat/s-finpri.ads | 48 2 files changed, 28 insertions(+), 24 deletions(-) diff --git a/gcc/ada/libgnat/s-finpri.adb b/gcc/ada/libgnat/s-finpri.adb index 028c9d760625..bc90fe23ac92 100644 --- a/gcc/ada/libgnat/s-finpri.adb +++ b/gcc/ada/libgnat/s-finpri.adb @@ -394,14 +394,14 @@ package body System.Finalization_Primitives is (Collection : in out Finalization_Collection) is begin - Collection.Finalization_Started := False; - -- The dummy head must point to itself in both directions Collection.Head.Prev := Collection.Head'Unchecked_Access; Collection.Head.Next := Collection.Head'Unchecked_Access; Initialize_RTS_Lock (Collection.Lock'Address); + + Collection.Finalization_Started := False; end Initialize; - diff --git a/gcc/ada/libgnat/s-finpri.ads b/gcc/ada/libgnat/s-finpri.ads index 62c2474b4f42..a821f1db657b 100644 --- a/gcc/ada/libgnat/s-finpri.ads +++ b/gcc/ada/libgnat/s-finpri.ads @@ -146,16 +146,6 @@ package System.Finalization_Primitives with Preelaborate is -- collection, in some arbitrary order. Calls to this procedure with -- a collection that has already been finalized have no effect. - type Collection_Node is private; - -- Each controlled object associated with a finalization collection has - -- an associated object of this type. - - type Collection_Node_Ptr is access all Collection_Node; - for Collection_Node_Ptr'Storage_Size use 0; - pragma No_Strict_Aliasing (Collection_Node_Ptr); - -- A reference to a collection node. Since this type may not be used to - -- allocate objects, its storage size is zero. - procedure Attach_Object_To_Collection (Object_Address : System.Address; Finalize_Address : not null Finalize_Address_Ptr; @@ -171,13 +161,13 @@ package System.Finalization_Primitives with Preelaborate is -- Calls to the procedure with an object that has already been detached -- have no effects. - function Header_Alignment return System.Storage_Elements.Storage_Count is - (Collection_Node'Alignment); - -- Return the alignment of type Collection_Node as Storage_Count + function Header_Alignment return System.Storage_Elements.Storage_Count; + -- Return the alignment of the header to be placed immediately in front of + -- a controlled object allocated for some access type, in storage units. - function Header_Size return System.Storage_Elements.Storage_Count is - (Collection_Node'Object_Size / Storage_Unit); - -- Return the object size of type Collection_Node as Storage_Count + function Header_Size return System.Storage_Elements.Storage_Count; + -- Return the size of the header to be placed immediately in front of a + -- controlled object allocated for some access type, in storage units. private @@ -221,6 +211,16 @@ private -- Finalization collections: + type Collection_Node; + -- Each controlled object associated with a finalization collection has + -- an associated object of this type. + + type Collection_Node_Ptr is access all Collection_Node; + for Collection_Node_Ptr'Storage_Size use 0; + pragma No_Strict_Aliasing (Collection_Node_Ptr); + -- A reference to a collection node. Since this type may not be used to + -- allocate objects, its storage size is zero. + -- Collection node type structure. Finalize_Address comes first because it -- is an access-to-subprogram and, therefore, might be twice as large and -- as aligned as an access-to-object on some platforms. @@ -237,7 +237,11 @@ private -- Collection nodes are managed as a circular doubly-linked list end record; - type Lock_Type is mod 2**8 with Size => 8; + function Header_Alignment return System.Storage_Elements.Storage_Count is + (Collection_Node'Alignment); + + function Header_Size return System.Storage_Elements.Storage_Count is + (Collection_Node'Object_Size / Storage_Unit); -- Finalization collection type structure @@ -245,15 +249,15 @@ private new Ada.Fina
[gcc r15-660] ada: Rework and augment documentation on strict aliasing
https://gcc.gnu.org/g:5d6c099ffaa384425f33d4e3a52f55149b9bc99a commit r15-660-g5d6c099ffaa384425f33d4e3a52f55149b9bc99a Author: Eric Botcazou Date: Wed Mar 13 17:05:12 2024 +0100 ada: Rework and augment documentation on strict aliasing The documentation was originally centered around pragma No_Strict_Aliasing and pragma Universal_Aliasing was mentioned only as an afterthought. It also contained a warning about the usage of overlays implemented by means of address clauses that has been obsolete for long. gcc/ada/ * doc/gnat_rm/implementation_defined_pragmas.rst (Universal_Aliasing): Remove reference to No_Strict_Aliasing. * doc/gnat_ugn/gnat_and_program_execution.rst (Optimization and Strict Aliasinng): Simplify first example and make it more consistent with the second. Add description of the effects of pragma Universal_Aliasing and document new warning issued for unchecked conversions. Remove obsolete stuff. * gnat_rm.texi: Regenerate. * gnat_ugn.texi: Regenerate. Diff: --- .../doc/gnat_rm/implementation_defined_pragmas.rst | 7 +- .../doc/gnat_ugn/gnat_and_program_execution.rst| 296 +++- gcc/ada/gnat_rm.texi | 7 +- gcc/ada/gnat_ugn.texi | 306 - 4 files changed, 353 insertions(+), 263 deletions(-) diff --git a/gcc/ada/doc/gnat_rm/implementation_defined_pragmas.rst b/gcc/ada/doc/gnat_rm/implementation_defined_pragmas.rst index 7f221e323446..bcbd85984dc0 100644 --- a/gcc/ada/doc/gnat_rm/implementation_defined_pragmas.rst +++ b/gcc/ada/doc/gnat_rm/implementation_defined_pragmas.rst @@ -6949,10 +6949,9 @@ Syntax: ``type_LOCAL_NAME`` must refer to a type declaration in the current declarative part. The effect is to inhibit strict type-based aliasing -optimization for the given type. In other words, the effect is as though -access types designating this type were subject to pragma No_Strict_Aliasing. -For a detailed description of the strict aliasing optimization, and the -situations in which it must be suppressed, see the section on +optimizations for the given type. For a detailed description of the +strict type-based aliasing optimizations and the situations in which +they need to be suppressed, see the section on ``Optimization and Strict Aliasing`` in the :title:`GNAT User's Guide`. .. _Pragma-Unmodified: diff --git a/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst b/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst index 35e347726589..d502da87eb0b 100644 --- a/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst +++ b/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst @@ -2072,37 +2072,36 @@ the following example: .. code-block:: ada - procedure R is + procedure M is type Int1 is new Integer; +I1 : Int1; + type Int2 is new Integer; -type Int1A is access Int1; -type Int2A is access Int2; -Int1V : Int1A; -Int2V : Int2A; +type A2 is access Int2; +V2 : A2; ... begin ... for J in Data'Range loop - if Data (J) = Int1V.all then - Int2V.all := Int2V.all + 1; + if Data (J) = I1 then + V2.all := V2.all + 1; end if; end loop; ... - end R; + end; -In this example, since the variable ``Int1V`` can only access objects -of type ``Int1``, and ``Int2V`` can only access objects of type -``Int2``, there is no possibility that the assignment to -``Int2V.all`` affects the value of ``Int1V.all``. This means that -the compiler optimizer can "know" that the value ``Int1V.all`` is constant -for all iterations of the loop and avoid the extra memory reference -required to dereference it each time through the loop. +In this example, since ``V2`` can only access objects of type ``Int2`` +and ``I1`` is not one of them, there is no possibility that the assignment +to ``V2.all`` affects the value of ``I1``. This means that the compiler +optimizer can infer that the value ``I1`` is constant for all iterations +of the loop and load it from memory only once, before entering the loop, +instead of in every iteration (this is called load hoisting). -This kind of optimization, called strict aliasing analysis, is +This kind of optimizations, based on strict type-based aliasing, is triggered by specifying an optimization level of :switch:`-O2` or -higher or :switch:`-Os` and allows GNAT to generate more efficient code -when access values are involved. +higher (or :switch:`-Os`) and allows the compiler to generate more +efficient code. However, although this optimization is always correct in terms of the formal semantics of the Ada Reference Manual, difficulties can @@ -2111,173 +2110,214 @@ the typing system. Consider the following complete program exampl
[gcc r15-659] MIPS: Remove -m(no-)lra option
https://gcc.gnu.org/g:d3b4ba120ce3b743838c3545a24554989955722a
commit r15-659-gd3b4ba120ce3b743838c3545a24554989955722a
Author: YunQiang Su
Date: Thu May 16 02:30:50 2024 +0800
MIPS: Remove -m(no-)lra option
PR target/113955
The `-mlra` option was introduced in 2014 for MIPS, and was set to
default since then. It's time for us to drop no-lra support by
dropping -m(no-)lra options.
gcc:
* config/mips/mips.cc(mips_option_override):
Drop mips_lra_flag variable;
(mips_lra_p): Removed.
(TARGET_LRA_P): Remove definition here to use the default one.
* config/mips/mips.md(*mul_acc_si, *mul_acc_si_r3900, *mul_sub_si):
Drop mips_lra_flag variable.
* config/mips/mips.opt(-mlra): Removed.
* config/mips/mips.opt.urls(mlra): Removed.
Diff:
---
gcc/config/mips/mips.cc | 12
gcc/config/mips/mips.md | 24 +++-
gcc/config/mips/mips.opt | 4
gcc/config/mips/mips.opt.urls | 2 --
4 files changed, 3 insertions(+), 39 deletions(-)
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index ce764a5cb359..b63d40a357b7 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -20391,8 +20391,6 @@ mips_option_override (void)
error ("unsupported combination: %s", "-mfp64 -mfpxx");
else if (ISA_MIPS1 && !TARGET_FLOAT32)
error ("%<-march=%s%> requires %<-mfp32%>", mips_arch_info->name);
- else if (TARGET_FLOATXX && !mips_lra_flag)
-error ("%<-mfpxx%> requires %<-mlra%>");
/* End of code shared with GAS. */
@@ -22871,14 +22869,6 @@ mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED,
return NO_REGS;
}
-/* Implement TARGET_LRA_P. */
-
-static bool
-mips_lra_p (void)
-{
- return mips_lra_flag;
-}
-
/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. */
static reg_class_t
@@ -23307,8 +23297,6 @@ mips_bit_clear_p (enum machine_mode mode, unsigned
HOST_WIDE_INT m)
#undef TARGET_SPILL_CLASS
#define TARGET_SPILL_CLASS mips_spill_class
-#undef TARGET_LRA_P
-#define TARGET_LRA_P mips_lra_p
#undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
#define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
mips_ira_change_pseudo_allocno_class
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 26f758c90ddf..7de85123e7c2 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1781,13 +1781,7 @@
(set_attr "mode""SI")
(set_attr "insn_count" "1,1,2")
(set (attr "enabled")
-(cond [(and (eq_attr "alternative" "0")
-(match_test "!mips_lra_flag"))
- (const_string "yes")
- (and (eq_attr "alternative" "1")
-(match_test "mips_lra_flag"))
- (const_string "yes")
- (eq_attr "alternative" "2")
+(cond [(eq_attr "alternative" "1,2")
(const_string "yes")]
(const_string "no")))])
@@ -1811,13 +1805,7 @@
(set_attr "mode""SI")
(set_attr "insn_count" "1,1,1,2")
(set (attr "enabled")
-(cond [(and (eq_attr "alternative" "0")
-(match_test "!mips_lra_flag"))
- (const_string "yes")
- (and (eq_attr "alternative" "1")
-(match_test "mips_lra_flag"))
- (const_string "yes")
- (eq_attr "alternative" "2,3")
+(cond [(eq_attr "alternative" "1,2,3")
(const_string "yes")]
(const_string "no")))])
@@ -2039,13 +2027,7 @@
(set_attr "mode" "SI")
(set_attr "insn_count" "1,1,2")
(set (attr "enabled")
-(cond [(and (eq_attr "alternative" "0")
-(match_test "!mips_lra_flag"))
- (const_string "yes")
- (and (eq_attr "alternative" "1")
-(match_test "mips_lra_flag"))
- (const_string "yes")
- (eq_attr "alternative" "2")
+(cond [(eq_attr "alternative" "1,2")
(const_string "yes")]
(const_string "no")))])
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index c1abb36212f9..99fe93019004 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -413,10 +413,6 @@ msynci
Target Mask(SYNCI)
Use synci instruction to invalidate i-cache.
-mlra
-Target Var(mips_lra_flag) Init(1) Save
-Use LRA instead of reload.
-
mlxc1-sxc1
Target Var(mips_lxc1_sxc1) Init(1)
Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable.
diff --git a/gcc/config/mips/mips.opt.urls b/gcc/config/mips/mips.opt.urls
index 9d166646d65c..5921d6929b28 100644
--- a/gcc/config/mips/mips.opt.urls
+++ b/gcc/config/mips/mips.opt.urls
@@ -222,8 +222,6 @@ UrlSuffix(gcc/MIPS-Options.html#index-msym32)
msynci
UrlSuffix(gcc/MIPS-Options.html#index-msynci)
-; skipping UrlSuffix for 'mlra' due to finding no URLs
-
mlxc1-sxc1
UrlSuffix(gcc/
