[gcc(refs/users/meissner/heads/work174)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:cf133c7218a584ef35be364f159d729cc7ff1e5a

commit cf133c7218a584ef35be364f159d729cc7ff1e5a
Author: Michael Meissner 
Date:   Wed Jul 31 14:38:51 2024 -0400

Revert changes

Diff:
---
 gcc/ChangeLog.meissner | 162 +
 gcc/config/rs6000/rs6000-arch.def  |  48 ---
 gcc/config/rs6000/rs6000-c.cc  |  27 +-
 gcc/config/rs6000/rs6000-cpus.def  |   8 +-
 gcc/config/rs6000/rs6000-opts.h|   1 +
 gcc/config/rs6000/rs6000-protos.h  |   5 +-
 gcc/config/rs6000/rs6000.cc| 363 ++---
 gcc/config/rs6000/rs6000.h |  30 --
 gcc/config/rs6000/rs6000.opt   |  19 +-
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c|  40 +--
 gcc/testsuite/gcc.target/powerpc/pr115688.c|   3 +-
 .../gcc.target/powerpc/vsx-cpu-mismatch.c  |   8 -
 12 files changed, 137 insertions(+), 577 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d53cd48662b0..df473b6b2313 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,164 +1,4 @@
- Branch work174, patch #26 
-
-Move ARCH_* to rs6000.h.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-opts.h: Move ARCH_* stuff from here.
-   * config/rs6000/rs6000.h: Move ARCH_* stuff here.
-
- Branch work174, patch #25 
-
-Update tests to work with architecture flags changes.
-
-Two tests used -mvsx to raise the processor level to at least power7.  These
-tests were rewritten to add cpu=power7 support.
-
-2024-07-31  Michael Meissner  
-
-gcc/testsuite/
-
-   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
-   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
-   to generate only Altivec instructions.
-   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
-   instructions.
-   * gcc.target/powerpc/vsx-cpu-mismatch.c: New test.
-
- Branch work174, patch #24 
-
-Do not allow -mvsx to boost processor to power7.
-
-This patch restructures the code so that -mvsx for example will not silently
-convert the processor to power7.  The user must now use -mcpu=power7 or higher.
-This means if the user does -mvsx and the default processor does not have VSX
-support, it will be an error.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
-   Report an error if the user used an option such as -mvsx when the
-   default processor would not allow the option.
-   (rs6000_option_override_internal): Move some ISA checking code into
-   report_architecture_mismatch.
-
- Branch work174, patch #23 
-
-Use architecture flags for defining _ARCH_PWR macros.
-
-For the newer architectures, this patch changes GCC to define the _ARCH_PWR
-macros using the new architecture flags instead of relying on isa options like
--mpower10.
-
-The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
--mpower11 option was removed completely, since it was just added in GCC 15.  
The
-other two options were marked as WarnRemoved, and the various ISA bits were
-removed.
-
-TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
-instead of the ISA bits.
-
-There are other internal isa bits that aren't removed with this patch because
-the built-in function support uses those bits.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
-   use architecture flags instead of ISA flags for setting most of the
-   _ARCH_PWR* macros.
-   (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
-   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
-   OPTION_MASK_POWER8.
-   (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
-   (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
-   (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
-   OPTION_MASK_POWER11.
-   * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
-   declaration.
-   (rs6000_target_modify_macros_ptr): Likewise.
-   * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
-   (rs6000_option_override_internal): Use architecture flags instead of ISA
-   flags.
-   (rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
-   (rs6000_pragma_target_parse): Use architecture flags as well as ISA
-   flags.
-   * config/rs6000/rs6000.h (TARGET_POWER8): New macro.
-   (TARGET_POWER10): Likewise.
-   * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits.
-   (-mpower10): 

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:4e8a80e5233b5665133847d813044fd91bf6dd47

commit 4e8a80e5233b5665133847d813044fd91bf6dd47
Author: Michael Meissner 
Date:   Wed Jul 31 14:32:47 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index c4f04d2a0134..d53cd48662b0 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,14 @@
+ Branch work174, patch #26 
+
+Move ARCH_* to rs6000.h.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-opts.h: Move ARCH_* stuff from here.
+   * config/rs6000/rs6000.h: Move ARCH_* stuff here.
+
  Branch work174, patch #25 
 
 Update tests to work with architecture flags changes.

[gcc(refs/users/meissner/heads/work174)] Move ARCH_* to rs6000.h.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:931131603c0563365105feb0613079e1a9e1ca23

commit 931131603c0563365105feb0613079e1a9e1ca23
Author: Michael Meissner 
Date:   Wed Jul 31 14:32:02 2024 -0400

Move ARCH_* to rs6000.h.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-opts.h: Move ARCH_* stuff from here.
* config/rs6000/rs6000.h: Move ARCH_* stuff here.

Diff:
---
 gcc/config/rs6000/rs6000-opts.h | 20 
 gcc/config/rs6000/rs6000.h  | 24 
 2 files changed, 24 insertions(+), 20 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index c7764e66cd03..f61cf7d1f662 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -71,26 +71,6 @@ enum processor_type
PROCESSOR_TITAN
 };
 
-/* Define an enumeration to number the architecture masks.  */
-#undef  ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME)ARCH_ENUM_ ## PROC,
-
-enum {
-#include "rs6000-arch.def"
-  ARCH_ENUM_LAST
-};
-
-/* Create an architecture mask for the newer architectures (power6 and
-   up)..  */
-#undef  ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME)
\
-  static const HOST_WIDE_INT ARCH_MASK_ ## PROC
\
-= HOST_WIDE_INT_1 << ARCH_ENUM_ ## PROC;
-
-#include "rs6000-arch.def"
-
-#undef ARCH_EXPAND
-
 /* Types of costly dependences.  */
 enum rs6000_dependence_cost
 {
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ccf6a4201542..f011fa2523c0 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2487,3 +2487,27 @@ while (0)
issues have been resolved.  */
 #define RS6000_DISABLE_SCALAR_MODULO 1
 
+
+
+/* Create the architecture flags.  */
+/* Define an enumeration to number the architecture masks.  */
+#ifdef GCC_HWINT_H
+#undef  ARCH_EXPAND
+#define ARCH_EXPAND(PROC, NAME)ARCH_ENUM_ ## PROC,
+
+enum {
+#include "rs6000-arch.def"
+  ARCH_ENUM_LAST
+};
+
+/* Create an architecture mask for the newer architectures (power6 and
+   up)..  */
+#undef  ARCH_EXPAND
+#define ARCH_EXPAND(PROC, NAME)
\
+  static const HOST_WIDE_INT ARCH_MASK_ ## PROC
\
+= HOST_WIDE_INT_1 << ARCH_ENUM_ ## PROC;
+
+#include "rs6000-arch.def"
+
+#undef ARCH_EXPAND
+#endif /* GCC_HWINT_H.  */

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:763aa18d706801668d3358fb246169dca5b56a58

commit 763aa18d706801668d3358fb246169dca5b56a58
Author: Michael Meissner 
Date:   Wed Jul 31 13:53:32 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 151 -
 1 file changed, 150 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d9918e29052d..c4f04d2a0134 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,153 @@
- Branch work174, patch #1..13 were reverted 

+ Branch work174, patch #25 
+
+Update tests to work with architecture flags changes.
+
+Two tests used -mvsx to raise the processor level to at least power7.  These
+tests were rewritten to add cpu=power7 support.
+
+2024-07-31  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
+   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
+   to generate only Altivec instructions.
+   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
+   instructions.
+   * gcc.target/powerpc/vsx-cpu-mismatch.c: New test.
+
+ Branch work174, patch #24 
+
+Do not allow -mvsx to boost processor to power7.
+
+This patch restructures the code so that -mvsx for example will not silently
+convert the processor to power7.  The user must now use -mcpu=power7 or higher.
+This means if the user does -mvsx and the default processor does not have VSX
+support, it will be an error.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
+   Report an error if the user used an option such as -mvsx when the
+   default processor would not allow the option.
+   (rs6000_option_override_internal): Move some ISA checking code into
+   report_architecture_mismatch.
+
+ Branch work174, patch #23 
+
+Use architecture flags for defining _ARCH_PWR macros.
+
+For the newer architectures, this patch changes GCC to define the _ARCH_PWR
+macros using the new architecture flags instead of relying on isa options like
+-mpower10.
+
+The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
+-mpower11 option was removed completely, since it was just added in GCC 15.  
The
+other two options were marked as WarnRemoved, and the various ISA bits were
+removed.
+
+TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
+instead of the ISA bits.
+
+There are other internal isa bits that aren't removed with this patch because
+the built-in function support uses those bits.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
+   use architecture flags instead of ISA flags for setting most of the
+   _ARCH_PWR* macros.
+   (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
+   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
+   OPTION_MASK_POWER8.
+   (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
+   (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
+   (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
+   OPTION_MASK_POWER11.
+   * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
+   declaration.
+   (rs6000_target_modify_macros_ptr): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
+   (rs6000_option_override_internal): Use architecture flags instead of ISA
+   flags.
+   (rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
+   (rs6000_pragma_target_parse): Use architecture flags as well as ISA
+   flags.
+   * config/rs6000/rs6000.h (TARGET_POWER8): New macro.
+   (TARGET_POWER10): Likewise.
+   * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits.
+   (-mpower10): Likewise.
+   (-mpower11): Likewise.
+
+ Branch work174, patch #22 
+
+Set .machine from the architecture flags
+
+This patch switches the handling of .machine to use architecture masks if they
+exist (power4 through power11).  All of the other PowerPCs will continue to use
+the existing code for setting the .machine option.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine from
+   the architecture flags.
+
+ Branch work174, patch #21 
+
+Make clone_targets use architecture flags.
+
+This patch expands on the previous patch and changes the target_clones support
+to use an architecture mask instead of isa bits.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (struct 

[gcc(refs/users/meissner/heads/work174)] Update tests to work with architecture flags changes.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:99e205eb7b5a43789691a29e59d7f7fdffb3b199

commit 99e205eb7b5a43789691a29e59d7f7fdffb3b199
Author: Michael Meissner 
Date:   Wed Jul 31 13:51:08 2024 -0400

Update tests to work with architecture flags changes.

Two tests used -mvsx to raise the processor level to at least power7.  These
tests were rewritten to add cpu=power7 support.

2024-07-31  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
instructions.
* gcc.target/powerpc/vsx-cpu-mismatch.c: New test.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c| 40 --
 gcc/testsuite/gcc.target/powerpc/pr115688.c|  3 +-
 .../gcc.target/powerpc/vsx-cpu-mismatch.c  |  8 +
 3 files changed, 40 insertions(+), 11 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c 
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index db9ba500e0e1..42f5aa354d0a 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -1,8 +1,8 @@
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-options "-O3 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
 /* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
 /* { dg-final { scan-assembler-times "fadds" 1 } } */
 
@@ -18,10 +18,6 @@
 #error "__VSX__ should not be defined."
 #endif
 
-#pragma GCC target("altivec,vsx")
-#include 
-#pragma GCC reset_options
-
 #pragma GCC push_options
 #pragma GCC target("altivec,no-vsx")
 
@@ -33,6 +29,7 @@
 #error "__VSX__ should not be defined."
 #endif
 
+/* Altivec build, generate vaddfp.  */
 void
 av_add (vector float *a, vector float *b, vector float *c)
 {
@@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
 }
 
-#pragma GCC target("vsx")
+/* cpu=power7 must be used to enable VSX.  */
+#pragma GCC target("cpu=power7,vsx")
 
 #ifndef __ALTIVEC__
 #error "__ALTIVEC__ should be defined."
@@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should be defined."
 #endif
 
+/* VSX build on power7, generate xsaddsp.  */
 void
 vsx_add (vector float *a, vector float *b, vector float *c)
 {
@@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
+}
+
+#pragma GCC target("cpu=power7,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+/* Altivec build on power7 with no VSX, generate vaddfp.  */
+void
+av2_add (vector float *a, vector float *b, vector float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+
+  for (i = 0; i < n; i++)
+a[i] = b[i] + c[i];
 }
 
 #pragma GCC pop_options
-#pragma GCC target("no-vsx,no-altivec")
 
 #ifdef __ALTIVEC__
 #error "__ALTIVEC__ should not be defined."
@@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should not be defined."
 #endif
 
+/* Default power5 build, generate scalar fadds.  */
 void
 norm_add (float *a, float *b, float *c)
 {
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c 
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 5222e66ef170..00c7c301436a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,7 +7,8 @@
 
 /* Verify there is no ICE under 32 bit env.  */
 
-__attribute__((target("vsx")))
+/* cpu=power7 must be used to enable VSX.  */
+__attribute__((target("cpu=power7,vsx")))
 int test (void)
 {
   return 0;
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-cpu-mismatch.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-cpu-mismatch.c
new file mode 100644
index ..ff1efd622523
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-cpu-mismatch.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-options "-O2 -mdejagnu-cpu=power5 -mvsx" } */
+/* { dg-error "‘vsx’ needs at least ‘-mcpu=power7’" } */
+
+/* Make sure -mcpu=power5 -mvsx gives an error if the cpu is not capable of VSX
+   support.  */
+int 

[gcc(refs/users/meissner/heads/work174)] Do not allow -mvsx to boost processor to power7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:505c018b5ecc7b1f05019a3255153718d18e81a3

commit 505c018b5ecc7b1f05019a3255153718d18e81a3
Author: Michael Meissner 
Date:   Wed Jul 31 13:39:16 2024 -0400

Do not allow -mvsx to boost processor to power7.

This patch restructures the code so that -mvsx for example will not silently
convert the processor to power7.  The user must now use -mcpu=power7 or 
higher.
This means if the user does -mvsx and the default processor does not have 
VSX
support, it will be an error.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 129 +++-
 1 file changed, 79 insertions(+), 50 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index caab770cd951..c89a6ea8e792 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1172,6 +1172,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3698,7 +3699,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3967,59 +3967,13 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
-rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_DFP)
-rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
-rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
-rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
-rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
-  else if (TARGET_ALTIVEC)
-rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
+  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
+  report_architecture_mismatch ();
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target attribute or pragma which automatically enables both options,
  unless the altivec ABI was set.  This is set by default for 64-bit, but
- not for 32-bit.  Don't move this before the above code using ignore_masks,
+ not for 32-bit.  Don't move this before report_architecture_mismatch
  since it can reset the cleared VSX/ALTIVEC flag again.  */
   if (main_target_opt && !main_target_opt->x_rs6000_altivec_abi)
 {
@@ -25410,6 +25364,81 @@ rs6000_disable_incompatible_switches (void)
   return ignore_masks;
 }
 
+/* In the past, we would boost up the ISA if you 

[gcc(refs/users/meissner/heads/work174)] Use architecture flags for defining _ARCH_PWR macros.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:bd791494894f276e8b8d81790f3a8670d953b8fd

commit bd791494894f276e8b8d81790f3a8670d953b8fd
Author: Michael Meissner 
Date:   Wed Jul 31 13:36:25 2024 -0400

Use architecture flags for defining _ARCH_PWR macros.

For the newer architectures, this patch changes GCC to define the 
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options 
like
-mpower10.

The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
-mpower11 option was removed completely, since it was just added in GCC 15. 
 The
other two options were marked as WarnRemoved, and the various ISA bits were
removed.

TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
instead of the ISA bits.

There are other internal isa bits that aren't removed with this patch 
because
the built-in function support uses those bits.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
OPTION_MASK_POWER11.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER8): New macro.
(TARGET_POWER10): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag 
bits.
(-mpower10): Likewise.
(-mpower11): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 27 +++
 gcc/config/rs6000/rs6000-cpus.def |  8 +---
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 19 +++
 gcc/config/rs6000/rs6000.h|  6 ++
 gcc/config/rs6000/rs6000.opt  | 11 ++-
 6 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 04882c396bfe..c8f33289fa38 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -419,23 +420,25 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((flags & OPTION_MASK_MFCRF) != 0)
+  if ((flags & OPTION_MASK_POWERPC64) != 0)
+rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((flags & OPTION_MASK_POPCNTD) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & 

[gcc(refs/users/meissner/heads/work174)] Set .machine from the architecture flags

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c8a3a625126a05f3e88fc9a73b327710d964814c

commit c8a3a625126a05f3e88fc9a73b327710d964814c
Author: Michael Meissner 
Date:   Wed Jul 31 13:25:40 2024 -0400

Set .machine from the architecture flags

This patch switches the handling of .machine to use architecture masks if 
they
exist (power4 through power11).  All of the other PowerPCs will continue to 
use
the existing code for setting the .machine option.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine 
from
the architecture flags.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0b113b68eff9..bd84b880fdc7 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5990,27 +5990,28 @@ rs6000_machine_from_flags (void)
 return "ppc64";
 #endif
 
+  HOST_WIDE_INT arch_flags = rs6000_arch_flags;
   HOST_WIDE_INT flags = rs6000_isa_flags;
 
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
 | OPTION_MASK_ALTIVEC);
 
-  if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER11) != 0)
 return "power11";
-  if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER10) != 0)
 return "power10";
-  if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER9) != 0)
 return "power9";
-  if ((flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER8) != 0)
 return "power8";
-  if ((flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 return "power7";
-  if ((flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 return "power6";
-  if ((flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 return "power5";
-  if ((flags & ISA_2_1_MASKS) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 return "power4";
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 return "ppc64";

[gcc(refs/users/meissner/heads/work174)] Make clone_targets use architecture flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:19ef02a218312d0971442cac73042211e0fac41f

commit 19ef02a218312d0971442cac73042211e0fac41f
Author: Michael Meissner 
Date:   Wed Jul 31 13:22:36 2024 -0400

Make clone_targets use architecture flags.

This patch expands on the previous patch and changes the target_clones 
support
to use an architecture mask instead of isa bits.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (struct clone_map): Switch to use 
architecture
flags instead of ISA flags for target_clone support.
(rs6000_clone_map): Likewise.
(rs6000_clone_priority): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index a77a079e6c44..0b113b68eff9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -251,17 +251,17 @@ enum {
 
 /* Map compiler ISA bits into HWCAP names.  */
 struct clone_map {
-  HOST_WIDE_INT isa_mask;  /* rs6000_isa mask */
+  HOST_WIDE_INT arch_mask; /* rs6000_arch_mask.  */
   const char *name;/* name to use in __builtin_cpu_supports.  */
 };
 
 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
-  { 0, "" },   /* Default options.  */
-  { OPTION_MASK_CMPB,  "arch_2_05" },  /* ISA 2.05 (power6).  */
-  { OPTION_MASK_POPCNTD,   "arch_2_06" },  /* ISA 2.06 (power7).  */
-  { OPTION_MASK_P8_VECTOR, "arch_2_07" },  /* ISA 2.07 (power8).  */
-  { OPTION_MASK_P9_VECTOR, "arch_3_00" },  /* ISA 3.0 (power9).  */
-  { OPTION_MASK_POWER10,   "arch_3_1" },   /* ISA 3.1 (power10).  */
+  { 0, "" },   /* Default options.  */
+  { ARCH_MASK_POWER6,  "arch_2_05" },  /* ISA 2.05 (power6).  */
+  { ARCH_MASK_POWER7,  "arch_2_06" },  /* ISA 2.06 (power7).  */
+  { ARCH_MASK_POWER8,  "arch_2_07" },  /* ISA 2.07 (power8).  */
+  { ARCH_MASK_POWER9,  "arch_3_00" },  /* ISA 3.0 (power9).  */
+  { ARCH_MASK_POWER10, "arch_3_1" },   /* ISA 3.1 (power10).  */
 };
 
 
@@ -25433,7 +25433,7 @@ static int
 rs6000_clone_priority (tree fndecl)
 {
   tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
-  HOST_WIDE_INT isa_masks;
+  HOST_WIDE_INT arch_masks;
   int ret = CLONE_DEFAULT;
   tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
   const char *attrs_str = NULL;
@@ -25449,12 +25449,12 @@ rs6000_clone_priority (tree fndecl)
fn_opts = target_option_default_node;
 
   if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
-   isa_masks = rs6000_isa_flags;
+   arch_masks = rs6000_arch_flags;
   else
-   isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
+   arch_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_arch_flags;
 
   for (ret = CLONE_MAX - 1; ret != 0; ret--)
-   if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
+   if ((rs6000_clone_map[ret].arch_mask & arch_masks) != 0)
  break;
 }

[gcc(refs/users/meissner/heads/work174)] Add rs6000 architecture masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e9d20aedfb2cc5881f0ae01006c224243a32ee0e

commit e9d20aedfb2cc5881f0ae01006c224243a32ee0e
Author: Michael Meissner 
Date:   Wed Jul 31 13:21:05 2024 -0400

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000-opts.h: Use rs6000-arch.def to create the
architecture masks needed.
* config/rs6000/rs6000.cc (rs6000_print_isa_options): Add an
architecture flags argument, change all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  48 +++
 gcc/config/rs6000/rs6000-opts.h   |  19 
 gcc/config/rs6000/rs6000.cc   | 176 ++
 gcc/config/rs6000/rs6000.opt  |   8 ++
 4 files changed, 234 insertions(+), 17 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..e5b6e9581331
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -0,0 +1,48 @@
+/* IBM RS/6000 CPU architecture features by processor type.
+   Copyright (C) 1991-2024 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+/* This file defines architecture features that are based on the -mcpu=
+   option, and not on user options that can be turned on or off.  The intention
+   is for newer processors (power7 and above) to not add new ISA bits for the
+   particular processor, but add these bits.  Otherwise we have to add a bunch
+   of hidden options, just so we have the proper ISA bits.
+
+   For example, in the past we added -mpower8-internal, so that on power8,
+   power9, and power10 would inherit the option, but we had to mark the option
+   generate a warning if the user actually used it.  These options have been
+   moved from the ISA flags to the arch flags.
+
+   To use this, define the macro ARCH_EXPAND which takes 2 arguments.  The
+   first argument is the processor name in upper case, and the second argument
+   is a text name for the processor.
+
+   The function get_arch_flags when passed a processor index number will set up
+   the appropriate architecture flags based on the actual processor
+   enumeration.  */
+
+ARCH_EXPAND(POWER4,  "power4")
+ARCH_EXPAND(POWER5,  "power5")
+ARCH_EXPAND(POWER5X, "power5+")
+ARCH_EXPAND(POWER6,  "power6")
+ARCH_EXPAND(POWER7,  "power7")
+ARCH_EXPAND(POWER8,  "power8")
+ARCH_EXPAND(POWER9,  "power9")
+ARCH_EXPAND(POWER10, "power10")
+ARCH_EXPAND(POWER11, "power11")
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 88e357835a5c..c7764e66cd03 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -71,6 +71,25 @@ enum processor_type
PROCESSOR_TITAN
 };
 
+/* Define an enumeration to number the architecture masks.  */
+#undef  ARCH_EXPAND
+#define ARCH_EXPAND(PROC, NAME)ARCH_ENUM_ ## PROC,
+
+enum {
+#include "rs6000-arch.def"
+  ARCH_ENUM_LAST

[gcc(refs/users/meissner/heads/work174)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:892f4318a3eb42c414386caa67fb32b9c8496902

commit 892f4318a3eb42c414386caa67fb32b9c8496902
Author: Michael Meissner 
Date:   Wed Jul 31 13:14:34 2024 -0400

Revert changes

Diff:
---
 gcc/ChangeLog.meissner  | 190 +
 gcc/config/rs6000/rs6000-arch.def   |  48 
 gcc/config/rs6000/rs6000-c.cc   |  25 +-
 gcc/config/rs6000/rs6000-cpus.def   |   8 +-
 gcc/config/rs6000/rs6000-opts.h |  19 --
 gcc/config/rs6000/rs6000-protos.h   |   5 +-
 gcc/config/rs6000/rs6000.cc | 363 ++--
 gcc/config/rs6000/rs6000.h  |   6 -
 gcc/config/rs6000/rs6000.opt|  19 +-
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c |  40 +--
 gcc/testsuite/gcc.target/powerpc/pr115688.c |   3 +-
 11 files changed, 136 insertions(+), 590 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index ece220b9bd2c..d9918e29052d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,192 +1,4 @@
- Branch work174, patch #13 was reverted 

-
- Branch work174, patch #12 
-
-Update arch flags.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000.cc (get_arch_flags): Rewrite.
-
- Branch work174, patch #11 
-
-Add power5+ to arch flags.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-arch.def (ARCH_MASK_POWER5X): Add power5+
-   support.
-   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
-   masks for power4, power5, power5+, and power6.
-   * config/rs6000/rs6000.cc (get_arch_flags): Add support for setting arch
-   flags for non power* processors.  Add support for power5+.
-   (report_architecture_mismatch): Improve error message.
-
- Branch work174, patch #10 
-
-Use const HOST_WIDE_INT for arch masks.
-
-2024-07-30  Michael Meissner  
-
-   * config/rs6000/rs6000-opts.h (ARCH_MASK_*): Encode the masks as const
-   HOST_WIDE_INT and not as an enumeratio.
-
- Branch work174, patch #9 was reverted 
- Branch work174, patch #8 was reverted 
- Branch work174, patch #7 was reverted 
-
- Branch work174, patch #6 
-
-Update tests to work with architecture flags changes.
-
-Two tests used -mvsx to raise the processor level to at least power7.  These
-tests were rewritten to add cpu=power7 support.
-
-2024-07-29  Michael Meissner  
-
-gcc/testsuite/
-
-   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
-   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
-   to generate only Altivec instructions.
-   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
-   instructions.
-
- Branch work174, patch #5 
-
-Do not allow -mvsx to boost processor to power7.
-
-This patch restructures the code so that -mvsx for example will not silently
-convert the processor to power7.  The user must now use -mcpu=power7 or higher.
-This means if the user does -mvsx and the default processor does not have VSX
-support, it will be an error.
-
-2024-07-29  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
-   Report an error if the user used an option such as -mvsx when the
-   default processor would not allow the option.
-   (rs6000_option_override_internal): Move some ISA checking code into
-   report_architecture_mismatch.
-
- Branch work174, patch #4 
-
-Use architecture flags for defining _ARCH_PWR macros.
-
-For the newer architectures, this patch changes GCC to define the _ARCH_PWR
-macros using the new architecture flags instead of relying on isa options like
--mpower10.
-
-The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
--mpower11 option was removed completely, since it was just added in GCC 15.  
The
-other two options were marked as WarnRemoved, and the various ISA bits were
-removed.
-
-TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
-instead of the ISA bits.
-
-There are other internal isa bits that aren't removed with this patch because
-the built-in function support uses those bits.
-
-2024-07-29  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
-   use architecture flags instead of ISA flags for setting most of the
-   _ARCH_PWR* macros.
-   (rs6000_cpu_cpp_builtins): Likewise.
-   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
- 

[gcc(refs/users/meissner/heads/work174)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ed2ed00cc99e53cdbb4ca675882a103c412dc6b8

commit ed2ed00cc99e53cdbb4ca675882a103c412dc6b8
Author: Michael Meissner 
Date:   Wed Jul 31 13:07:18 2024 -0400

Revert changes

Diff:
---
 gcc/ChangeLog.meissner| 14 +-
 gcc/config/rs6000/rs6000-arch.def |  2 --
 gcc/config/rs6000/rs6000-c.cc |  4 ++--
 gcc/config/rs6000/rs6000.cc   | 10 +-
 4 files changed, 4 insertions(+), 26 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index b63c515f38e5..ece220b9bd2c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,16 +1,4 @@
- Branch work174, patch #13 
-
-Add gp, gfx to arch flags.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-arch.def (ARCH_MASK_GP): Add gp.
-   (ARCH_MASK_GFX): Add gfx.
-   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
-   masks for gp and gfx.
-   * config/rs6000/rs6000.cc (get_arch_flags): Add support for gp and gfx.
+ Branch work174, patch #13 was reverted 

 
  Branch work174, patch #12 
 
diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index 91bd2f638cf3..e5b6e9581331 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -37,8 +37,6 @@
the appropriate architecture flags based on the actual processor
enumeration.  */
 
-ARCH_EXPAND(GPOPT,   "gpopt")
-ARCH_EXPAND(GFXOPT,  "gfxopt")
 ARCH_EXPAND(POWER4,  "power4")
 ARCH_EXPAND(POWER5,  "power5")
 ARCH_EXPAND(POWER5X, "power5+")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 63cf580b20b4..d7b1625f0867 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -414,9 +414,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 
   /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
-  if ((arch_flags & ARCH_MASK_GPOPT) != 0)
+  if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
-  if ((arch_flags & ARCH_MASK_GFXOPT) != 0)
+  if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 17c22dc59117..c89a6ea8e792 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1827,9 +1827,7 @@ get_arch_flags (int cpu_index)
 {
   HOST_WIDE_INT ret = 0;
 
-  const HOST_WIDE_INT ARCH_COMBO_POWER4  = (ARCH_MASK_POWER4
-   | ARCH_MASK_GPOPT
-   | ARCH_MASK_GFXOPT);
+  const HOST_WIDE_INT ARCH_COMBO_POWER4  = ARCH_MASK_POWER4;
   const HOST_WIDE_INT ARCH_COMBO_POWER5  = ARCH_MASK_POWER5  | 
ARCH_COMBO_POWER4;
   const HOST_WIDE_INT ARCH_COMBO_POWER5X = ARCH_MASK_POWER5X | 
ARCH_COMBO_POWER5;
   const HOST_WIDE_INT ARCH_COMBO_POWER6  = ARCH_MASK_POWER6  | 
ARCH_COMBO_POWER5X;
@@ -1890,12 +1888,6 @@ get_arch_flags (int cpu_index)
 
if (TARGET_CMPB)
  ret |= ARCH_MASK_POWER6;
-
-   if (TARGET_PPC_GPOPT)
- ret |= ARCH_MASK_GPOPT;
-
-   if (TARGET_PPC_GFXOPT)
- ret |= ARCH_MASK_GFXOPT;
break;
   }

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0b4cf5fc0a949d2815dfcc044729b1f28d996138

commit 0b4cf5fc0a949d2815dfcc044729b1f28d996138
Author: Michael Meissner 
Date:   Wed Jul 31 13:04:36 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index f7cb9a767f6d..b63c515f38e5 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,17 @@
+ Branch work174, patch #13 
+
+Add gp, gfx to arch flags.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-arch.def (ARCH_MASK_GP): Add gp.
+   (ARCH_MASK_GFX): Add gfx.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
+   masks for gp and gfx.
+   * config/rs6000/rs6000.cc (get_arch_flags): Add support for gp and gfx.
+
  Branch work174, patch #12 
 
 Update arch flags.

[gcc(refs/users/meissner/heads/work174)] Add gp, gfx to arch flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:92eb0f0e330ba1b78a339846c0840534bcc11c4c

commit 92eb0f0e330ba1b78a339846c0840534bcc11c4c
Author: Michael Meissner 
Date:   Wed Jul 31 13:03:39 2024 -0400

Add gp, gfx to arch flags.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def (ARCH_MASK_GP): Add gp.
(ARCH_MASK_GFX): Add gfx.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
masks for gp and gfx.
* config/rs6000/rs6000.cc (get_arch_flags): Add support for gp and 
gfx.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  2 ++
 gcc/config/rs6000/rs6000-c.cc |  4 ++--
 gcc/config/rs6000/rs6000.cc   | 10 +-
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index e5b6e9581331..91bd2f638cf3 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -37,6 +37,8 @@
the appropriate architecture flags based on the actual processor
enumeration.  */
 
+ARCH_EXPAND(GPOPT,   "gpopt")
+ARCH_EXPAND(GFXOPT,  "gfxopt")
 ARCH_EXPAND(POWER4,  "power4")
 ARCH_EXPAND(POWER5,  "power5")
 ARCH_EXPAND(POWER5X, "power5+")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index d7b1625f0867..63cf580b20b4 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -414,9 +414,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 
   /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
-  if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
+  if ((arch_flags & ARCH_MASK_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
-  if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
+  if ((arch_flags & ARCH_MASK_GFXOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c89a6ea8e792..17c22dc59117 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1827,7 +1827,9 @@ get_arch_flags (int cpu_index)
 {
   HOST_WIDE_INT ret = 0;
 
-  const HOST_WIDE_INT ARCH_COMBO_POWER4  = ARCH_MASK_POWER4;
+  const HOST_WIDE_INT ARCH_COMBO_POWER4  = (ARCH_MASK_POWER4
+   | ARCH_MASK_GPOPT
+   | ARCH_MASK_GFXOPT);
   const HOST_WIDE_INT ARCH_COMBO_POWER5  = ARCH_MASK_POWER5  | 
ARCH_COMBO_POWER4;
   const HOST_WIDE_INT ARCH_COMBO_POWER5X = ARCH_MASK_POWER5X | 
ARCH_COMBO_POWER5;
   const HOST_WIDE_INT ARCH_COMBO_POWER6  = ARCH_MASK_POWER6  | 
ARCH_COMBO_POWER5X;
@@ -1888,6 +1890,12 @@ get_arch_flags (int cpu_index)
 
if (TARGET_CMPB)
  ret |= ARCH_MASK_POWER6;
+
+   if (TARGET_PPC_GPOPT)
+ ret |= ARCH_MASK_GPOPT;
+
+   if (TARGET_PPC_GFXOPT)
+ ret |= ARCH_MASK_GFXOPT;
break;
   }

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e86b226352aeacda9e0db3ad9768670ef0c5f8be

commit e86b226352aeacda9e0db3ad9768670ef0c5f8be
Author: Michael Meissner 
Date:   Wed Jul 31 12:48:55 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index a40533cb986a..f7cb9a767f6d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,13 @@
+ Branch work174, patch #12 
+
+Update arch flags.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (get_arch_flags): Rewrite.
+
  Branch work174, patch #11 
 
 Add power5+ to arch flags.

[gcc(refs/users/meissner/heads/work174)] Update arch flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8f50688bd3b27770be4017a1ce565d64cbda0ca0

commit 8f50688bd3b27770be4017a1ce565d64cbda0ca0
Author: Michael Meissner 
Date:   Wed Jul 31 12:45:27 2024 -0400

Update arch flags.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (get_arch_flags): Rewrite.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 41 ++---
 1 file changed, 26 insertions(+), 15 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index ec1cf85de12f..c89a6ea8e792 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1827,41 +1827,52 @@ get_arch_flags (int cpu_index)
 {
   HOST_WIDE_INT ret = 0;
 
+  const HOST_WIDE_INT ARCH_COMBO_POWER4  = ARCH_MASK_POWER4;
+  const HOST_WIDE_INT ARCH_COMBO_POWER5  = ARCH_MASK_POWER5  | 
ARCH_COMBO_POWER4;
+  const HOST_WIDE_INT ARCH_COMBO_POWER5X = ARCH_MASK_POWER5X | 
ARCH_COMBO_POWER5;
+  const HOST_WIDE_INT ARCH_COMBO_POWER6  = ARCH_MASK_POWER6  | 
ARCH_COMBO_POWER5X;
+  const HOST_WIDE_INT ARCH_COMBO_POWER7  = ARCH_MASK_POWER7  | 
ARCH_COMBO_POWER6;
+  const HOST_WIDE_INT ARCH_COMBO_POWER8  = ARCH_MASK_POWER8  | 
ARCH_COMBO_POWER7;
+  const HOST_WIDE_INT ARCH_COMBO_POWER9  = ARCH_MASK_POWER9  | 
ARCH_COMBO_POWER8;
+  const HOST_WIDE_INT ARCH_COMBO_POWER10 = ARCH_MASK_POWER10 | 
ARCH_COMBO_POWER9;
+  const HOST_WIDE_INT ARCH_COMBO_POWER11 = ARCH_MASK_POWER11 | 
ARCH_COMBO_POWER10;
+
   if (cpu_index >= 0)
 switch (processor_target_table[cpu_index].processor)
   {
   case PROCESSOR_POWER11:
-   ret |= ARCH_MASK_POWER11;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER11;
+   break;
 
   case PROCESSOR_POWER10:
-   ret |= ARCH_MASK_POWER10;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER10;
+   break;
 
   case PROCESSOR_POWER9:
-   ret |= ARCH_MASK_POWER9;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER9;
+   break;
 
   case PROCESSOR_POWER8:
-   ret |= ARCH_MASK_POWER8;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER8;
+   break;
 
   case PROCESSOR_POWER7:
-   ret |= ARCH_MASK_POWER7;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER7;
+   break;
 
+  case PROCESSOR_PPCA2:
   case PROCESSOR_POWER6:
-   ret |= ARCH_MASK_POWER6;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER6;
+   break;
 
   case PROCESSOR_POWER5:
-   ret |= ARCH_MASK_POWER5;
+   ret = ARCH_COMBO_POWER5;
if (TARGET_FPRND)
  ret |= ARCH_MASK_POWER5X;
-   /* fall through.  */
+   break;
 
   case PROCESSOR_POWER4:
-   ret |= ARCH_MASK_POWER4;
+   ret = ARCH_COMBO_POWER4;
break;
 
   default:

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:00570ace830d9e811e74752afc14c6d1640fc053

commit 00570ace830d9e811e74752afc14c6d1640fc053
Author: Michael Meissner 
Date:   Wed Jul 31 12:24:41 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 16 
 1 file changed, 16 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index ce7ed892daf3..a40533cb986a 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,19 @@
+ Branch work174, patch #11 
+
+Add power5+ to arch flags.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-arch.def (ARCH_MASK_POWER5X): Add power5+
+   support.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
+   masks for power4, power5, power5+, and power6.
+   * config/rs6000/rs6000.cc (get_arch_flags): Add support for setting arch
+   flags for non power* processors.  Add support for power5+.
+   (report_architecture_mismatch): Improve error message.
+
  Branch work174, patch #10 
 
 Use const HOST_WIDE_INT for arch masks.

[gcc(refs/users/meissner/heads/work174)] Add power5+ to arch flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d964bf62dfeeb413f2af87994b677c85aef6408d

commit d964bf62dfeeb413f2af87994b677c85aef6408d
Author: Michael Meissner 
Date:   Wed Jul 31 12:23:55 2024 -0400

Add power5+ to arch flags.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def (ARCH_MASK_POWER5X): Add power5+
support.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
masks for power4, power5, power5+, and power6.
* config/rs6000/rs6000.cc (get_arch_flags): Add support for setting 
arch
flags for non power* processors.  Add support for power5+.
(report_architecture_mismatch): Improve error message.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  1 +
 gcc/config/rs6000/rs6000-c.cc |  8 
 gcc/config/rs6000/rs6000.cc   | 20 +---
 3 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index 6725736076da..e5b6e9581331 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -39,6 +39,7 @@
 
 ARCH_EXPAND(POWER4,  "power4")
 ARCH_EXPAND(POWER5,  "power5")
+ARCH_EXPAND(POWER5X, "power5+")
 ARCH_EXPAND(POWER6,  "power6")
 ARCH_EXPAND(POWER7,  "power7")
 ARCH_EXPAND(POWER8,  "power8")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index a8a6a956874f..d7b1625f0867 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -420,13 +420,13 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((flags & OPTION_MASK_MFCRF) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 19adc66cc801..ec1cf85de12f 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1856,6 +1856,8 @@ get_arch_flags (int cpu_index)
 
   case PROCESSOR_POWER5:
ret |= ARCH_MASK_POWER5;
+   if (TARGET_FPRND)
+ ret |= ARCH_MASK_POWER5X;
/* fall through.  */
 
   case PROCESSOR_POWER4:
@@ -1863,6 +1865,18 @@ get_arch_flags (int cpu_index)
break;
 
   default:
+   /* For other processors, set the arch flags based on the ISA bits.  */
+   if (TARGET_MFCRF)
+ ret |= ARCH_MASK_POWER4;
+
+   if (TARGET_POPCNTB)
+ ret |= ARCH_MASK_POWER5;
+
+   if (TARGET_FPRND)
+ ret |= ARCH_MASK_POWER5X;
+
+   if (TARGET_CMPB)
+ ret |= ARCH_MASK_POWER6;
break;
   }
 
@@ -25359,19 +25373,19 @@ report_architecture_mismatch (void)
   OPTION_MASK_P9_VECTOR | OPTION_MASK_P9_MISC | OPTION_MASK_P9_MINMAX
   | OPTION_MASK_MODULO,
   ARCH_MASK_POWER9,
-  "cpu=power9"
+  "-mcpu=power9"
 },
 
 {
   OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO,
   ARCH_MASK_POWER8,
-  "cpu=power8"
+  "-mcpu=power8"
 },
 
 {
   OPTION_MASK_VSX | OPTION_MASK_POPCNTD,
   ARCH_MASK_POWER7,
-  "cpu=power7"
+  "-mcpu=power7"
 },
   };

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:1b8c6a9878846cc8925df7189f8aee0c1013036c

commit 1b8c6a9878846cc8925df7189f8aee0c1013036c
Author: Michael Meissner 
Date:   Tue Jul 30 18:24:50 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 9 +
 1 file changed, 9 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 75d085b17f0c..ce7ed892daf3 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,12 @@
+ Branch work174, patch #10 
+
+Use const HOST_WIDE_INT for arch masks.
+
+2024-07-30  Michael Meissner  
+
+   * config/rs6000/rs6000-opts.h (ARCH_MASK_*): Encode the masks as const
+   HOST_WIDE_INT and not as an enumeratio.
+
  Branch work174, patch #9 was reverted 
  Branch work174, patch #8 was reverted 
  Branch work174, patch #7 was reverted 

[gcc(refs/users/meissner/heads/work174)] Use const HOST_WIDE_INT for arch masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a66ceb34e3df733362f3ee4b56bb504ff5e2a81c

commit a66ceb34e3df733362f3ee4b56bb504ff5e2a81c
Author: Michael Meissner 
Date:   Tue Jul 30 18:23:14 2024 -0400

Use const HOST_WIDE_INT for arch masks.

2024-07-30  Michael Meissner  

* config/rs6000/rs6000-opts.h (ARCH_MASK_*): Encode the masks as 
const
HOST_WIDE_INT and not as an enumeratio.

Diff:
---
 gcc/config/rs6000/rs6000-opts.h | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 9a52a1d4b147..c7764e66cd03 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -80,15 +80,14 @@ enum {
   ARCH_ENUM_LAST
 };
 
-/* Create an architecture mask for the newer architectures (power7 and
+/* Create an architecture mask for the newer architectures (power6 and
up)..  */
 #undef  ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME)ARCH_MASK_ ## PROC = 1 << ARCH_ENUM_ ## 
PROC,
+#define ARCH_EXPAND(PROC, NAME)
\
+  static const HOST_WIDE_INT ARCH_MASK_ ## PROC
\
+= HOST_WIDE_INT_1 << ARCH_ENUM_ ## PROC;
 
-enum {
 #include "rs6000-arch.def"
-  ARCH_MASK_ZERO   = 0
-};
 
 #undef ARCH_EXPAND

[gcc(refs/users/meissner/heads/work174)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:4d9ccfc12fa1c534d01eb7c3aac57fe0268fc913

commit 4d9ccfc12fa1c534d01eb7c3aac57fe0268fc913
Author: Michael Meissner 
Date:   Tue Jul 30 18:19:52 2024 -0400

Revert changes

Diff:
---
 gcc/ChangeLog.meissner| 26 ++
 gcc/config/rs6000/rs6000-arch.def |  3 ++-
 gcc/config/rs6000/rs6000-c.cc |  2 +-
 gcc/config/rs6000/rs6000-opts.h   |  9 +
 gcc/config/rs6000/rs6000.cc   | 12 ++--
 5 files changed, 20 insertions(+), 32 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 86cc52c8636d..75d085b17f0c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,27 +1,5 @@
- Branch work174, patch #9 
-
-Add a2 processor to arch flags.
-
-2024-07-30  Michael Meissner  
-
-   * config/rs6000/rs6000-arch.def: Add a2 processor.
-
- Branch work174, patch #8 
-
-Remove arch flags power4 and power5.  Use const HOST_WIDE_INT for arch masks.
-
-2024-07-30  Michael Meissner  
-
-   * config/rs6000/rs6000-arch.def: Remove power4 and power5 architecture
-   masks.
-   * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Use arch flags
-   for power6.
-   * config/rs6000/rs6000-opts.h (ARCH_MASK_*): Encode the masks as const
-   HOST_WIDE_INT and not as an enumeratio.
-   * config/rs6000/rs6000.cc (get_arch_flags): Drop power4 and power5 arch
-   flags support.
-   (rs6000_machine_from_flags): Likewise.
-
+ Branch work174, patch #9 was reverted 
+ Branch work174, patch #8 was reverted 
  Branch work174, patch #7 was reverted 
 
  Branch work174, patch #6 
diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index 89b1b87c89ac..6725736076da 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -37,7 +37,8 @@
the appropriate architecture flags based on the actual processor
enumeration.  */
 
-ARCH_EXPAND(PPCA2,   "a2")
+ARCH_EXPAND(POWER4,  "power4")
+ARCH_EXPAND(POWER5,  "power5")
 ARCH_EXPAND(POWER6,  "power6")
 ARCH_EXPAND(POWER7,  "power7")
 ARCH_EXPAND(POWER8,  "power8")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 7d0b24b7c09e..a8a6a956874f 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -426,7 +426,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((arch_flags & ARCH_MASK_POWER6) != 0)
+  if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index c7764e66cd03..9a52a1d4b147 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -80,14 +80,15 @@ enum {
   ARCH_ENUM_LAST
 };
 
-/* Create an architecture mask for the newer architectures (power6 and
+/* Create an architecture mask for the newer architectures (power7 and
up)..  */
 #undef  ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME)
\
-  static const HOST_WIDE_INT ARCH_MASK_ ## PROC
\
-= HOST_WIDE_INT_1 << ARCH_ENUM_ ## PROC;
+#define ARCH_EXPAND(PROC, NAME)ARCH_MASK_ ## PROC = 1 << ARCH_ENUM_ ## 
PROC,
 
+enum {
 #include "rs6000-arch.def"
+  ARCH_MASK_ZERO   = 0
+};
 
 #undef ARCH_EXPAND
 
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index bccf30a44b20..19adc66cc801 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1852,6 +1852,14 @@ get_arch_flags (int cpu_index)
 
   case PROCESSOR_POWER6:
ret |= ARCH_MASK_POWER6;
+   /* fall through.  */
+
+  case PROCESSOR_POWER5:
+   ret |= ARCH_MASK_POWER5;
+   /* fall through.  */
+
+  case PROCESSOR_POWER4:
+   ret |= ARCH_MASK_POWER4;
break;
 
   default:
@@ -5929,9 +5937,9 @@ rs6000_machine_from_flags (void)
 return "power7";
   if ((arch_flags & ARCH_MASK_POWER6) != 0)
 return "power6";
-  if ((flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 return "power5";
-  if ((flags & ISA_2_1_MASKS) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 return "power4";
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 return "ppc64";

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:51e8229f65e2d7e5fd846ae016cd2634e5828e65

commit 51e8229f65e2d7e5fd846ae016cd2634e5828e65
Author: Michael Meissner 
Date:   Tue Jul 30 18:13:59 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 8 
 1 file changed, 8 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index eb0b90a45dbe..86cc52c8636d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,11 @@
+ Branch work174, patch #9 
+
+Add a2 processor to arch flags.
+
+2024-07-30  Michael Meissner  
+
+   * config/rs6000/rs6000-arch.def: Add a2 processor.
+
  Branch work174, patch #8 
 
 Remove arch flags power4 and power5.  Use const HOST_WIDE_INT for arch masks.

[gcc(refs/users/meissner/heads/work174)] Add a2 processor to arch flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:7d2ba2da50c107056bc9a5f589012d42ff1439de

commit 7d2ba2da50c107056bc9a5f589012d42ff1439de
Author: Michael Meissner 
Date:   Tue Jul 30 18:13:07 2024 -0400

Add a2 processor to arch flags.

2024-07-30  Michael Meissner  

* config/rs6000/rs6000-arch.def: Add a2 processor.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index d317200016a2..89b1b87c89ac 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -37,6 +37,7 @@
the appropriate architecture flags based on the actual processor
enumeration.  */
 
+ARCH_EXPAND(PPCA2,   "a2")
 ARCH_EXPAND(POWER6,  "power6")
 ARCH_EXPAND(POWER7,  "power7")
 ARCH_EXPAND(POWER8,  "power8")

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e2a3cfdcb3909f7893afeb36c366c4dba2306206

commit e2a3cfdcb3909f7893afeb36c366c4dba2306206
Author: Michael Meissner 
Date:   Tue Jul 30 18:07:02 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 16 
 1 file changed, 16 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 0f6cd95f9269..eb0b90a45dbe 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,19 @@
+ Branch work174, patch #8 
+
+Remove arch flags power4 and power5.  Use const HOST_WIDE_INT for arch masks.
+
+2024-07-30  Michael Meissner  
+
+   * config/rs6000/rs6000-arch.def: Remove power4 and power5 architecture
+   masks.
+   * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Use arch flags
+   for power6.
+   * config/rs6000/rs6000-opts.h (ARCH_MASK_*): Encode the masks as const
+   HOST_WIDE_INT and not as an enumeratio.
+   * config/rs6000/rs6000.cc (get_arch_flags): Drop power4 and power5 arch
+   flags support.
+   (rs6000_machine_from_flags): Likewise.
+
  Branch work174, patch #7 was reverted 
 
  Branch work174, patch #6 

[gcc(refs/users/meissner/heads/work174)] Remove arch flags power4 and power5. Use const HOST_WIDE_INT for arch masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:816307fad902b82fd4ed6079b9113057b7496252

commit 816307fad902b82fd4ed6079b9113057b7496252
Author: Michael Meissner 
Date:   Tue Jul 30 18:05:54 2024 -0400

Remove arch flags power4 and power5.  Use const HOST_WIDE_INT for arch 
masks.

2024-07-30  Michael Meissner  

* config/rs6000/rs6000-arch.def: Remove power4 and power5 
architecture
masks.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Use arch 
flags
for power6.
* config/rs6000/rs6000-opts.h (ARCH_MASK_*): Encode the masks as 
const
HOST_WIDE_INT and not as an enumeratio.
* config/rs6000/rs6000.cc (get_arch_flags): Drop power4 and power5 
arch
flags support.
(rs6000_machine_from_flags): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  2 --
 gcc/config/rs6000/rs6000-c.cc |  2 +-
 gcc/config/rs6000/rs6000-opts.h   |  9 -
 gcc/config/rs6000/rs6000.cc   | 12 ++--
 4 files changed, 7 insertions(+), 18 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index 6725736076da..d317200016a2 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -37,8 +37,6 @@
the appropriate architecture flags based on the actual processor
enumeration.  */
 
-ARCH_EXPAND(POWER4,  "power4")
-ARCH_EXPAND(POWER5,  "power5")
 ARCH_EXPAND(POWER6,  "power6")
 ARCH_EXPAND(POWER7,  "power7")
 ARCH_EXPAND(POWER8,  "power8")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index a8a6a956874f..7d0b24b7c09e 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -426,7 +426,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 9a52a1d4b147..c7764e66cd03 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -80,15 +80,14 @@ enum {
   ARCH_ENUM_LAST
 };
 
-/* Create an architecture mask for the newer architectures (power7 and
+/* Create an architecture mask for the newer architectures (power6 and
up)..  */
 #undef  ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME)ARCH_MASK_ ## PROC = 1 << ARCH_ENUM_ ## 
PROC,
+#define ARCH_EXPAND(PROC, NAME)
\
+  static const HOST_WIDE_INT ARCH_MASK_ ## PROC
\
+= HOST_WIDE_INT_1 << ARCH_ENUM_ ## PROC;
 
-enum {
 #include "rs6000-arch.def"
-  ARCH_MASK_ZERO   = 0
-};
 
 #undef ARCH_EXPAND
 
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 19adc66cc801..bccf30a44b20 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1852,14 +1852,6 @@ get_arch_flags (int cpu_index)
 
   case PROCESSOR_POWER6:
ret |= ARCH_MASK_POWER6;
-   /* fall through.  */
-
-  case PROCESSOR_POWER5:
-   ret |= ARCH_MASK_POWER5;
-   /* fall through.  */
-
-  case PROCESSOR_POWER4:
-   ret |= ARCH_MASK_POWER4;
break;
 
   default:
@@ -5937,9 +5929,9 @@ rs6000_machine_from_flags (void)
 return "power7";
   if ((arch_flags & ARCH_MASK_POWER6) != 0)
 return "power6";
-  if ((arch_flags & ARCH_MASK_POWER5) != 0)
+  if ((flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
 return "power5";
-  if ((arch_flags & ARCH_MASK_POWER4) != 0)
+  if ((flags & ISA_2_1_MASKS) != 0)
 return "power4";
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 return "ppc64";

[gcc(refs/users/meissner/heads/work174)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b0847289e8894dd1069958bd902bcd66df5c0c71

commit b0847289e8894dd1069958bd902bcd66df5c0c71
Author: Michael Meissner 
Date:   Tue Jul 30 16:51:34 2024 -0400

Revert changes

Diff:
---
 gcc/ChangeLog.meissner| 13 +
 gcc/config/rs6000/rs6000-arch.def |  3 ---
 gcc/config/rs6000/rs6000-c.cc |  6 +++---
 gcc/config/rs6000/rs6000.cc   |  4 
 4 files changed, 4 insertions(+), 22 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 16ad0870ec3e..0f6cd95f9269 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,15 +1,4 @@
- Branch work174, patch #7 
-
-Add more processors to arch flags.
-
-2024-07-30  Michael Meissner  
-
-   * config/rs6000/rs6000-arch.def: Add support for 476, a2, and cell
-   processors.
-   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
-   flags for power4, power5, and power6.
-   * config/rs6000/rs6000.cc (get_arch_flags): Add 476, a2, and cell
-   processors.
+ Branch work174, patch #7 was reverted 
 
  Branch work174, patch #6 
 
diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index 96f176775b59..6725736076da 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -37,9 +37,6 @@
the appropriate architecture flags based on the actual processor
enumeration.  */
 
-ARCH_EXPAND(PPC476,  "476")
-ARCH_EXPAND(PPCA2,   "a2")
-ARCH_EXPAND(CELL,"cell")
 ARCH_EXPAND(POWER4,  "power4")
 ARCH_EXPAND(POWER5,  "power5")
 ARCH_EXPAND(POWER6,  "power6")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 27f18f48e837..a8a6a956874f 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -420,13 +420,13 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((arch_flags & ARCH_MASK_POWER4) != 0)
+  if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((arch_flags & ARCH_MASK_POWER5) != 0)
+  if ((flags & OPTION_MASK_POPCNTB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((arch_flags & ARCH_MASK_POWER6) != 0)
+  if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index f9ccaa67e619..19adc66cc801 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1851,18 +1851,14 @@ get_arch_flags (int cpu_index)
/* fall through.  */
 
   case PROCESSOR_POWER6:
-  case PROCESSOR_PPCA2:
ret |= ARCH_MASK_POWER6;
/* fall through.  */
 
-  case PROCESSOR_PPC476:
   case PROCESSOR_POWER5:
ret |= ARCH_MASK_POWER5;
/* fall through.  */
 
-  case PROCESSOR_CELL:
   case PROCESSOR_POWER4:
-  case PROCESSOR_PPCE6500:
ret |= ARCH_MASK_POWER4;
break;

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:a10a34fe1cb8d4c96f1888942e52f1a4216cb7f3

commit a10a34fe1cb8d4c96f1888942e52f1a4216cb7f3
Author: Michael Meissner 
Date:   Tue Jul 30 16:46:54 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 13 +
 1 file changed, 13 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 58ffd411e22d..16ad0870ec3e 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,16 @@
+ Branch work174, patch #7 
+
+Add more processors to arch flags.
+
+2024-07-30  Michael Meissner  
+
+   * config/rs6000/rs6000-arch.def: Add support for 476, a2, and cell
+   processors.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
+   flags for power4, power5, and power6.
+   * config/rs6000/rs6000.cc (get_arch_flags): Add 476, a2, and cell
+   processors.
+
  Branch work174, patch #6 
 
 Update tests to work with architecture flags changes.

[gcc(refs/users/meissner/heads/work174)] Add more processors to arch flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:48f7791835b495c254452a20d4d06bc9bedd7cae

commit 48f7791835b495c254452a20d4d06bc9bedd7cae
Author: Michael Meissner 
Date:   Tue Jul 30 16:45:47 2024 -0400

Add more processors to arch flags.

2024-07-30  Michael Meissner  

* config/rs6000/rs6000-arch.def: Add support for 476, a2, and cell
processors.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
flags for power4, power5, and power6.
* config/rs6000/rs6000.cc (get_arch_flags): Add 476, a2, and cell
processors.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def | 3 +++
 gcc/config/rs6000/rs6000-c.cc | 6 +++---
 gcc/config/rs6000/rs6000.cc   | 4 
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index 6725736076da..96f176775b59 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -37,6 +37,9 @@
the appropriate architecture flags based on the actual processor
enumeration.  */
 
+ARCH_EXPAND(PPC476,  "476")
+ARCH_EXPAND(PPCA2,   "a2")
+ARCH_EXPAND(CELL,"cell")
 ARCH_EXPAND(POWER4,  "power4")
 ARCH_EXPAND(POWER5,  "power5")
 ARCH_EXPAND(POWER6,  "power6")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index a8a6a956874f..27f18f48e837 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -420,13 +420,13 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((flags & OPTION_MASK_MFCRF) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
   if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 19adc66cc801..f9ccaa67e619 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1851,14 +1851,18 @@ get_arch_flags (int cpu_index)
/* fall through.  */
 
   case PROCESSOR_POWER6:
+  case PROCESSOR_PPCA2:
ret |= ARCH_MASK_POWER6;
/* fall through.  */
 
+  case PROCESSOR_PPC476:
   case PROCESSOR_POWER5:
ret |= ARCH_MASK_POWER5;
/* fall through.  */
 
+  case PROCESSOR_CELL:
   case PROCESSOR_POWER4:
+  case PROCESSOR_PPCE6500:
ret |= ARCH_MASK_POWER4;
break;

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:cef4f3cb53faff4bc3b74ecd1dd4dd3d3d2106df

commit cef4f3cb53faff4bc3b74ecd1dd4dd3d3d2106df
Author: Michael Meissner 
Date:   Mon Jul 29 23:44:58 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 182 -
 1 file changed, 181 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 65c296e69433..58ffd411e22d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,6 +1,186 @@
+ Branch work174, patch #6 
+
+Update tests to work with architecture flags changes.
+
+Two tests used -mvsx to raise the processor level to at least power7.  These
+tests were rewritten to add cpu=power7 support.
+
+2024-07-29  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
+   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
+   to generate only Altivec instructions.
+   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
+   instructions.
+
+ Branch work174, patch #5 
+
+Do not allow -mvsx to boost processor to power7.
+
+This patch restructures the code so that -mvsx for example will not silently
+convert the processor to power7.  The user must now use -mcpu=power7 or higher.
+This means if the user does -mvsx and the default processor does not have VSX
+support, it will be an error.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
+   Report an error if the user used an option such as -mvsx when the
+   default processor would not allow the option.
+   (rs6000_option_override_internal): Move some ISA checking code into
+   report_architecture_mismatch.
+
+ Branch work174, patch #4 
+
+Use architecture flags for defining _ARCH_PWR macros.
+
+For the newer architectures, this patch changes GCC to define the _ARCH_PWR
+macros using the new architecture flags instead of relying on isa options like
+-mpower10.
+
+The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
+-mpower11 option was removed completely, since it was just added in GCC 15.  
The
+other two options were marked as WarnRemoved, and the various ISA bits were
+removed.
+
+TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
+instead of the ISA bits.
+
+There are other internal isa bits that aren't removed with this patch because
+the built-in function support uses those bits.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
+   use architecture flags instead of ISA flags for setting most of the
+   _ARCH_PWR* macros.
+   (rs6000_cpu_cpp_builtins): Likewise.
+   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
+   OPTION_MASK_POWER8.
+   (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
+   (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
+   (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
+   OPTION_MASK_POWER11.
+   * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
+   declaration.
+   (rs6000_target_modify_macros_ptr): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
+   (rs6000_option_override_internal): Use architecture flags instead of ISA
+   flags.
+   (rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
+   (rs6000_pragma_target_parse): Use architecture flags as well as ISA
+   flags.
+   * config/rs6000/rs6000.h (TARGET_POWER8): New macro.
+   (TARGET_POWER10): Likewise.
+   * config/rs6000/rs6000.opt (-mpower8-internal): No longer make this an
+   ISA flag.
+   (-mpower10): Likewise.
+   (-mpower11): Likewise.
+
+ Branch work174, patch #3 
+
+Set .machine from the architecture flags
+
+This patch switches the handling of .machine to use architecture masks if they
+exist (power4 through power11).  All of the other PowerPCs will continue to use
+the existing code for setting the .machine option.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine from
+   the architecture flags.
+
+ Branch work174, patch #2 
+
+Make clone_targets use architecture flags.
+
+This patch expands on the previous patch and changes the target_clones support
+to use an architecture mask instead of isa bits.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (struct clone_map): Switch to use architecture
+   flags instead of ISA flags for target_clone support.
+   (rs6000_clone_map): Likewise.
+   

[gcc(refs/users/meissner/heads/work174)] Update tests to work with architecture flags changes.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b218260ad062bc65820475609bb69cee7dc6f7da

commit b218260ad062bc65820475609bb69cee7dc6f7da
Author: Michael Meissner 
Date:   Mon Jul 29 23:39:45 2024 -0400

Update tests to work with architecture flags changes.

Two tests used -mvsx to raise the processor level to at least power7.  These
tests were rewritten to add cpu=power7 support.

2024-07-29  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
instructions.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c | 40 ++---
 gcc/testsuite/gcc.target/powerpc/pr115688.c |  3 +-
 2 files changed, 32 insertions(+), 11 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c 
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index db9ba500e0e1..42f5aa354d0a 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -1,8 +1,8 @@
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-options "-O3 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
 /* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
 /* { dg-final { scan-assembler-times "fadds" 1 } } */
 
@@ -18,10 +18,6 @@
 #error "__VSX__ should not be defined."
 #endif
 
-#pragma GCC target("altivec,vsx")
-#include 
-#pragma GCC reset_options
-
 #pragma GCC push_options
 #pragma GCC target("altivec,no-vsx")
 
@@ -33,6 +29,7 @@
 #error "__VSX__ should not be defined."
 #endif
 
+/* Altivec build, generate vaddfp.  */
 void
 av_add (vector float *a, vector float *b, vector float *c)
 {
@@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
 }
 
-#pragma GCC target("vsx")
+/* cpu=power7 must be used to enable VSX.  */
+#pragma GCC target("cpu=power7,vsx")
 
 #ifndef __ALTIVEC__
 #error "__ALTIVEC__ should be defined."
@@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should be defined."
 #endif
 
+/* VSX build on power7, generate xsaddsp.  */
 void
 vsx_add (vector float *a, vector float *b, vector float *c)
 {
@@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
+}
+
+#pragma GCC target("cpu=power7,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+/* Altivec build on power7 with no VSX, generate vaddfp.  */
+void
+av2_add (vector float *a, vector float *b, vector float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+
+  for (i = 0; i < n; i++)
+a[i] = b[i] + c[i];
 }
 
 #pragma GCC pop_options
-#pragma GCC target("no-vsx,no-altivec")
 
 #ifdef __ALTIVEC__
 #error "__ALTIVEC__ should not be defined."
@@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should not be defined."
 #endif
 
+/* Default power5 build, generate scalar fadds.  */
 void
 norm_add (float *a, float *b, float *c)
 {
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c 
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 5222e66ef170..00c7c301436a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,7 +7,8 @@
 
 /* Verify there is no ICE under 32 bit env.  */
 
-__attribute__((target("vsx")))
+/* cpu=power7 must be used to enable VSX.  */
+__attribute__((target("cpu=power7,vsx")))
 int test (void)
 {
   return 0;

[gcc(refs/users/meissner/heads/work174)] Do not allow -mvsx to boost processor to power7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:062b226ae470e28d3e8f883dd6db1a4d0e301ac8

commit 062b226ae470e28d3e8f883dd6db1a4d0e301ac8
Author: Michael Meissner 
Date:   Mon Jul 29 23:35:12 2024 -0400

Do not allow -mvsx to boost processor to power7.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 129 +++-
 1 file changed, 79 insertions(+), 50 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 1bd045b8f037..19adc66cc801 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1172,6 +1172,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3673,7 +3674,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3942,59 +3942,13 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
-rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_DFP)
-rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
-rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
-rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
-rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
-  else if (TARGET_ALTIVEC)
-rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
+  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
+  report_architecture_mismatch ();
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target attribute or pragma which automatically enables both options,
  unless the altivec ABI was set.  This is set by default for 64-bit, but
- not for 32-bit.  Don't move this before the above code using ignore_masks,
+ not for 32-bit.  Don't move this before report_architecture_mismatch
  since it can reset the cleared VSX/ALTIVEC flag again.  */
   if (main_target_opt && !main_target_opt->x_rs6000_altivec_abi)
 {
@@ -25385,6 +25339,81 @@ rs6000_disable_incompatible_switches (void)
   return ignore_masks;
 }
 
+/* In the past, we would boost up the ISA if you selected an -m option but
+   did not specify the correct -mcpu= option.  I.e. if you added -mvsx,
+   GCC implictly would assume that you were building for at least power7.  Now,
+   don't allow the -m option to boost up the ISA level.  But you can still
+   do -mcpu=power7 -mno-vsx or 

[gcc(refs/users/meissner/heads/work174)] Use architecture flags for defining _ARCH_PWR macros.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:66b25bd282d5ec1adb4a18ba206c893844c5807e

commit 66b25bd282d5ec1adb4a18ba206c893844c5807e
Author: Michael Meissner 
Date:   Mon Jul 29 23:28:39 2024 -0400

Use architecture flags for defining _ARCH_PWR macros.

For the newer architectures, this patch changes GCC to define the 
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options 
like
-mpower10.

The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
-mpower11 option was removed completely, since it was just added in GCC 15. 
 The
other two options were marked as WarnRemoved, and the various ISA bits were
removed.

TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
instead of the ISA bits.

There are other internal isa bits that aren't removed with this patch 
because
the built-in function support uses those bits.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Likewise.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
OPTION_MASK_POWER11.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER8): New macro.
(TARGET_POWER10): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): No longer make this 
an
ISA flag.
(-mpower10): Likewise.
(-mpower11): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 17 +
 gcc/config/rs6000/rs6000-cpus.def |  8 +---
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 19 +++
 gcc/config/rs6000/rs6000.h|  6 ++
 gcc/config/rs6000/rs6000.opt  | 11 ++-
 6 files changed, 32 insertions(+), 34 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 04882c396bfe..a8a6a956874f 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -427,15 +428,15 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
   if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((flags & OPTION_MASK_POPCNTD) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_MASK_POWER8) != 0)
+  if ((arch_flags & ARCH_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
-  if ((flags & OPTION_MASK_MODULO) != 0)
+  if ((arch_flags & ARCH_MASK_POWER9) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
-  if ((flags & OPTION_MASK_POWER10) != 0)
+  if ((arch_flags & ARCH_MASK_POWER10) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
-  if ((flags & OPTION_MASK_POWER11) != 0)
+  if ((arch_flags & ARCH_MASK_POWER11) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
@@ -605,7 +606,7 @@ void
 

[gcc(refs/users/meissner/heads/work174)] Make clone_targets use architecture flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:63ecac63bac6f2c1e7e151a4ff494f27b41b86e7

commit 63ecac63bac6f2c1e7e151a4ff494f27b41b86e7
Author: Michael Meissner 
Date:   Mon Jul 29 23:15:10 2024 -0400

Make clone_targets use architecture flags.

This patch expands on the previous patch and changes the target_clones 
support
to use an architecture mask instead of isa bits.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (struct clone_map): Switch to use 
architecture
flags instead of ISA flags for target_clone support.
(rs6000_clone_map): Likewise.
(rs6000_clone_priority): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 83ae0157a9ec..0dda6dcc5a1a 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -251,17 +251,17 @@ enum {
 
 /* Map compiler ISA bits into HWCAP names.  */
 struct clone_map {
-  HOST_WIDE_INT isa_mask;  /* rs6000_isa mask */
+  HOST_WIDE_INT arch_mask; /* rs6000_arch_mask.  */
   const char *name;/* name to use in __builtin_cpu_supports.  */
 };
 
 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
-  { 0, "" },   /* Default options.  */
-  { OPTION_MASK_CMPB,  "arch_2_05" },  /* ISA 2.05 (power6).  */
-  { OPTION_MASK_POPCNTD,   "arch_2_06" },  /* ISA 2.06 (power7).  */
-  { OPTION_MASK_P8_VECTOR, "arch_2_07" },  /* ISA 2.07 (power8).  */
-  { OPTION_MASK_P9_VECTOR, "arch_3_00" },  /* ISA 3.0 (power9).  */
-  { OPTION_MASK_POWER10,   "arch_3_1" },   /* ISA 3.1 (power10).  */
+  { 0, "" },   /* Default options.  */
+  { ARCH_MASK_POWER6,  "arch_2_05" },  /* ISA 2.05 (power6).  */
+  { ARCH_MASK_POWER7,  "arch_2_06" },  /* ISA 2.06 (power7).  */
+  { ARCH_MASK_POWER8,  "arch_2_07" },  /* ISA 2.07 (power8).  */
+  { ARCH_MASK_POWER9,  "arch_3_00" },  /* ISA 3.0 (power9).  */
+  { ARCH_MASK_POWER10, "arch_3_1" },   /* ISA 3.1 (power10).  */
 };
 
 
@@ -25408,7 +25408,7 @@ static int
 rs6000_clone_priority (tree fndecl)
 {
   tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
-  HOST_WIDE_INT isa_masks;
+  HOST_WIDE_INT arch_masks;
   int ret = CLONE_DEFAULT;
   tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
   const char *attrs_str = NULL;
@@ -25424,12 +25424,12 @@ rs6000_clone_priority (tree fndecl)
fn_opts = target_option_default_node;
 
   if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
-   isa_masks = rs6000_isa_flags;
+   arch_masks = rs6000_arch_flags;
   else
-   isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
+   arch_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_arch_flags;
 
   for (ret = CLONE_MAX - 1; ret != 0; ret--)
-   if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
+   if ((rs6000_clone_map[ret].arch_mask & arch_masks) != 0)
  break;
 }

[gcc(refs/users/meissner/heads/work174)] Set .machine from the architecture flags

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b923b8d6ce508b1c05a8d64a285bf3511e1ebac5

commit b923b8d6ce508b1c05a8d64a285bf3511e1ebac5
Author: Michael Meissner 
Date:   Mon Jul 29 23:17:40 2024 -0400

Set .machine from the architecture flags

This patch switches the handling of .machine to use architecture masks if 
they
exist (power4 through power11).  All of the other PowerPCs will continue to 
use
the existing code for setting the .machine option.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine 
from
the architecture flags.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0dda6dcc5a1a..ac2f4d769216 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5965,27 +5965,28 @@ rs6000_machine_from_flags (void)
 return "ppc64";
 #endif
 
+  HOST_WIDE_INT arch_flags = rs6000_arch_flags;
   HOST_WIDE_INT flags = rs6000_isa_flags;
 
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
 | OPTION_MASK_ALTIVEC);
 
-  if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER11) != 0)
 return "power11";
-  if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER10) != 0)
 return "power10";
-  if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER9) != 0)
 return "power9";
-  if ((flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER8) != 0)
 return "power8";
-  if ((flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 return "power7";
-  if ((flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 return "power6";
-  if ((flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 return "power5";
-  if ((flags & ISA_2_1_MASKS) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 return "power4";
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 return "ppc64";

[gcc(refs/users/meissner/heads/work174)] Add rs6000 architecture masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e2263a8ee92635ffd1862a8b21036da2d848006c

commit e2263a8ee92635ffd1862a8b21036da2d848006c
Author: Michael Meissner 
Date:   Mon Jul 29 23:11:41 2024 -0400

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000-opts.h: Use rs6000-arch.def to create the
architecture masks needed.
* config/rs6000/rs6000.cc (rs6000_print_isa_options): Add an
architecture flags argument, change all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  47 
 gcc/config/rs6000/rs6000-opts.h   |  20 +
 gcc/config/rs6000/rs6000.cc   | 151 +-
 gcc/config/rs6000/rs6000.opt  |   8 ++
 4 files changed, 209 insertions(+), 17 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..6725736076da
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -0,0 +1,47 @@
+/* IBM RS/6000 CPU architecture features by processor type.
+   Copyright (C) 1991-2024 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+/* This file defines architecture features that are based on the -mcpu=
+   option, and not on user options that can be turned on or off.  The intention
+   is for newer processors (power7 and above) to not add new ISA bits for the
+   particular processor, but add these bits.  Otherwise we have to add a bunch
+   of hidden options, just so we have the proper ISA bits.
+
+   For example, in the past we added -mpower8-internal, so that on power8,
+   power9, and power10 would inherit the option, but we had to mark the option
+   generate a warning if the user actually used it.  These options have been
+   moved from the ISA flags to the arch flags.
+
+   To use this, define the macro ARCH_EXPAND which takes 2 arguments.  The
+   first argument is the processor name in upper case, and the second argument
+   is a text name for the processor.
+
+   The function get_arch_flags when passed a processor index number will set up
+   the appropriate architecture flags based on the actual processor
+   enumeration.  */
+
+ARCH_EXPAND(POWER4,  "power4")
+ARCH_EXPAND(POWER5,  "power5")
+ARCH_EXPAND(POWER6,  "power6")
+ARCH_EXPAND(POWER7,  "power7")
+ARCH_EXPAND(POWER8,  "power8")
+ARCH_EXPAND(POWER9,  "power9")
+ARCH_EXPAND(POWER10, "power10")
+ARCH_EXPAND(POWER11, "power11")
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 88e357835a5c..9a52a1d4b147 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -71,6 +71,26 @@ enum processor_type
PROCESSOR_TITAN
 };
 
+/* Define an enumeration to number the architecture masks.  */
+#undef  ARCH_EXPAND
+#define ARCH_EXPAND(PROC, NAME)ARCH_ENUM_ ## PROC,
+
+enum {
+#include "rs6000-arch.def"
+  ARCH_ENUM_LAST
+};
+
+/* Create an 

[gcc(refs/users/meissner/heads/work173)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8932f6f9903b7b155780e12f4485660fb3fcb442

commit 8932f6f9903b7b155780e12f4485660fb3fcb442
Author: Michael Meissner 
Date:   Mon Jul 29 20:31:40 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 27a75f8891e2..7e64f74af706 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,15 @@
- Branch work173, patch #14 
+ Branch work173, patch #16 
+
+Use old arch code for power4-power6 part 2.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (report_architecture_mismatch): Use old code
+   for power6 options.
+
+ Branch work173, patch #15 
 
 Use old arch code for power4-power6.

[gcc(refs/users/meissner/heads/work173)] Use old arch code for power4-power6 part 2.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:85a5bf5709ae03cd14f54497fa26e49cab383b1c

commit 85a5bf5709ae03cd14f54497fa26e49cab383b1c
Author: Michael Meissner 
Date:   Mon Jul 29 20:30:42 2024 -0400

Use old arch code for power4-power6 part 2.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): Use old 
code
for power6 options.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6f9f3cce5582..abc682683852 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3943,7 +3943,7 @@ rs6000_option_override_internal (bool global_init_p)
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target attribute or pragma which automatically enables both options,
  unless the altivec ABI was set.  This is set by default for 64-bit, but
- not for 32-bit.  Don't move this before the above code using ignore_masks,
+ not for 32-bit.  Don't move this before report_architecture_mismatch
  since it can reset the cleared VSX/ALTIVEC flag again.  */
   if (main_target_opt && !main_target_opt->x_rs6000_altivec_abi)
 {
@@ -25359,12 +25359,7 @@ report_architecture_mismatch (void)
 {
   OPTION_MASK_VSX | OPTION_MASK_POPCNTD,
   ARCH_MASK_POWER7,
-  "cpu=power7" },
-
-{
-  OPTION_MASK_DFP | OPTION_MASK_CMPB,
-  ARCH_MASK_POWER6,
-  "cpu=power6"
+  "cpu=power7"
 },
   };
 
@@ -25395,7 +25390,11 @@ report_architecture_mismatch (void)
 
   /* The following old options are used in multiple processors, so silently
  enable the appropriate ISA options as previous GCC revisions did.  */
-  if (TARGET_FPRND)
+  if (TARGET_DFP)
+rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
+  else if (TARGET_CMPB)
+rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
+  else if (TARGET_FPRND)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
   else if (TARGET_POPCNTB)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);

[gcc(refs/users/meissner/heads/work173)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ad2f2d3a58313501940554940c19854c8f57bef9

commit ad2f2d3a58313501940554940c19854c8f57bef9
Author: Michael Meissner 
Date:   Mon Jul 29 19:37:55 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index a08f187b26cf..27a75f8891e2 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,16 @@
  Branch work173, patch #14 
 
+Use old arch code for power4-power6.
+
+2024-07-29  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use original
+   code for _ARCH_PWR* if older than power7.
+
+ Branch work173, patch #14 
+
 Do not allow -mvsx to boost processor to power7.
 
 2024-07-25  Michael Meissner  

[gcc(refs/users/meissner/heads/work173)] Use old arch code for power4-power6.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e4d2106c7ef57a460688cdc959a61901684ddd9d

commit e4d2106c7ef57a460688cdc959a61901684ddd9d
Author: Michael Meissner 
Date:   Mon Jul 29 19:36:22 2024 -0400

Use old arch code for power4-power6.

2024-07-29  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use 
original
code for _ARCH_PWR* if older than power7.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 2ffaee165885..f3081414721b 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,11 +422,11 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((arch_flags & ARCH_MASK_POWER4) != 0)
+  if ((flags & OPTION_MASK_POPCNTB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((arch_flags & ARCH_MASK_POWER5) != 0)
+  if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((arch_flags & ARCH_MASK_POWER6) != 0)
+  if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");

[gcc(refs/users/meissner/heads/work174-orig)] Add REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:7e5ceefec53e912ced1017e06c9328e0ac6f4546

commit 7e5ceefec53e912ced1017e06c9328e0ac6f4546
Author: Michael Meissner 
Date:   Mon Jul 29 16:43:08 2024 -0400

Add REVISION.

2024-07-29  Michael Meissner  

gcc/

* REVISION: New file for branch.

Diff:
---
 gcc/REVISION | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/REVISION b/gcc/REVISION
new file mode 100644
index ..f83b29522d08
--- /dev/null
+++ b/gcc/REVISION
@@ -0,0 +1 @@
+work174-orig branch

[gcc] Created branch 'meissner/heads/work174-orig' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-orig' was created in namespace 'refs/users' 
pointing to:

 dd2cc71e3898... doc: Improve punctuation and grammar in -fdiagnostics-forma

[gcc(refs/users/meissner/heads/work174-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:6675d319eb77722cf6f288619243e0a4ba8970ce

commit 6675d319eb77722cf6f288619243e0a4ba8970ce
Author: Michael Meissner 
Date:   Mon Jul 29 16:42:06 2024 -0400

Add ChangeLog.test and update REVISION.

2024-07-29  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..56e792180a72
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,6 @@
+ Branch work174-test, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 413941b052d0..e81b8c44fdcd 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work174 branch
+work174-test branch

[gcc] Created branch 'meissner/heads/work174-test' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-test' was created in namespace 'refs/users' 
pointing to:

 82a5c795fd71... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work174-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:eb5e56965437b34344b679e6b6dab6c5d934867c

commit eb5e56965437b34344b679e6b6dab6c5d934867c
Author: Michael Meissner 
Date:   Mon Jul 29 16:41:15 2024 -0400

Add ChangeLog.bugs and update REVISION.

2024-07-29  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..13c3d901068f
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,6 @@
+ Branch work174-bugs, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 413941b052d0..06f7156b252a 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work174 branch
+work174-bugs branch

[gcc] Created branch 'meissner/heads/work174-bugs' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-bugs' was created in namespace 'refs/users' 
pointing to:

 82a5c795fd71... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work174-tar)] Add ChangeLog.tar and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:134e004f00358d070d87a40751adff56ceb2a76c

commit 134e004f00358d070d87a40751adff56ceb2a76c
Author: Michael Meissner 
Date:   Mon Jul 29 16:40:26 2024 -0400

Add ChangeLog.tar and update REVISION.

2024-07-29  Michael Meissner  

gcc/

* ChangeLog.tar: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.tar | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
new file mode 100644
index ..3433e69ba6b5
--- /dev/null
+++ b/gcc/ChangeLog.tar
@@ -0,0 +1,6 @@
+ Branch work174-tar, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 413941b052d0..2c76bc5f8f6d 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work174 branch
+work174-tar branch

[gcc] Created branch 'meissner/heads/work174-tar' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-tar' was created in namespace 'refs/users' 
pointing to:

 82a5c795fd71... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work174-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:621dc107566d596088f3635b11648e0e23616b10

commit 621dc107566d596088f3635b11648e0e23616b10
Author: Michael Meissner 
Date:   Mon Jul 29 16:39:27 2024 -0400

Add ChangeLog.vpair and update REVISION.

2024-07-29  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 6 ++
 gcc/REVISION| 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..7867e637d8f4
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,6 @@
+ Branch work174-vpair, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 413941b052d0..5360dc97f7de 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work174 branch
+work174-vpair branch

[gcc] Created branch 'meissner/heads/work174-vpair' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-vpair' was created in namespace 'refs/users' 
pointing to:

 82a5c795fd71... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work174-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ab0407a87efb9442e73afaec8490c0aa894da99f

commit ab0407a87efb9442e73afaec8490c0aa894da99f
Author: Michael Meissner 
Date:   Mon Jul 29 16:38:35 2024 -0400

Add ChangeLog.dmf and update REVISION.

2024-07-29  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..8b10eface864
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,6 @@
+ Branch work174-dmf, baseline 
+
+2024-07-29   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 413941b052d0..996d497cf07a 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work174 branch
+work174-dmf branch

[gcc] Created branch 'meissner/heads/work174-dmf' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174-dmf' was created in namespace 'refs/users' 
pointing to:

 82a5c795fd71... Add ChangeLog.meissner and REVISION.

[gcc] Created branch 'meissner/heads/work174' in namespace 'refs/users'

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work174' was created in namespace 'refs/users' 
pointing to:

 dd2cc71e3898... doc: Improve punctuation and grammar in -fdiagnostics-forma

[gcc(refs/users/meissner/heads/work173-vpair)] Merge commit 'refs/users/meissner/heads/work173-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:37539f4d77fe5aea35ffa65915e231558be5177b

commit 37539f4d77fe5aea35ffa65915e231558be5177b
Merge: 25bdc9874b6b ba573e905753
Author: Michael Meissner 
Date:   Thu Jul 25 21:42:43 2024 -0400

Merge commit 'refs/users/meissner/heads/work173-vpair' of 
git+ssh://gcc.gnu.org/git/gcc into me/work173-vpair

Diff:

[gcc(refs/users/meissner/heads/work173-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:25bdc9874b6be4af37ecfe8f5ac2305e1c015769

commit 25bdc9874b6be4af37ecfe8f5ac2305e1c015769
Author: Michael Meissner 
Date:   Mon Jul 22 15:04:47 2024 -0400

Add ChangeLog.vpair and update REVISION.

2024-07-22  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 6 ++
 gcc/REVISION| 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..6b79a1e6c689
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,6 @@
+ Branch work173-vpair, baseline 
+
+2024-07-22   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 125a55f99c87..f7e937ee745e 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work173 branch
+work173-vpair branch

[gcc/meissner/heads/work173-vpair] (9 commits) Merge commit 'refs/users/meissner/heads/work173-vpair' of g

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work173-vpair' was updated to point to:

 37539f4d77fe... Merge commit 'refs/users/meissner/heads/work173-vpair' of g

It previously pointed to:

 ba573e905753... Merge commit 'refs/users/meissner/heads/work173-vpair' of g

Diff:

Summary of changes (added commits):
---

  37539f4... Merge commit 'refs/users/meissner/heads/work173-vpair' of g
  25bdc98... Add ChangeLog.vpair and update REVISION.
  cc5fbf9... Update ChangeLog.* (*)
  9a16e24... Do not allow -mvsx to boost processor to power7. (*)
  07ff152... Revert changes (*)
  7b2fece... Update ChangeLog.* (*)
  2e2d883... Update ChangeLog.* (*)
  4bb4829... Do not allow -mvsx to boost processor to power7. (*)
  ffa9cd4... Update ChangeLog.* (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work173-vpair' matches
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[gcc(refs/users/meissner/heads/work173-test)] Merge commit 'refs/users/meissner/heads/work173-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:9f4b3207756ec4b1cae70c18f21e6f1b3fe41684

commit 9f4b3207756ec4b1cae70c18f21e6f1b3fe41684
Merge: c85433210fa2 903574fd9243
Author: Michael Meissner 
Date:   Thu Jul 25 21:41:37 2024 -0400

Merge commit 'refs/users/meissner/heads/work173-test' of 
git+ssh://gcc.gnu.org/git/gcc into me/work173-test

Diff:

[gcc(refs/users/meissner/heads/work173-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c85433210fa2b36961f31bb54d7dffe8ee3ec431

commit c85433210fa2b36961f31bb54d7dffe8ee3ec431
Author: Michael Meissner 
Date:   Mon Jul 22 15:07:51 2024 -0400

Add ChangeLog.test and update REVISION.

2024-07-22  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..03e20764eb03
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,6 @@
+ Branch work173-test, baseline 
+
+2024-07-22   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 125a55f99c87..858e261ae8fb 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work173 branch
+work173-test branch

[gcc/meissner/heads/work173-test] (9 commits) Merge commit 'refs/users/meissner/heads/work173-test' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work173-test' was updated to point to:

 9f4b3207756e... Merge commit 'refs/users/meissner/heads/work173-test' of gi

It previously pointed to:

 903574fd9243... Merge commit 'refs/users/meissner/heads/work173-test' of gi

Diff:

Summary of changes (added commits):
---

  9f4b320... Merge commit 'refs/users/meissner/heads/work173-test' of gi
  c854332... Add ChangeLog.test and update REVISION.
  cc5fbf9... Update ChangeLog.* (*)
  9a16e24... Do not allow -mvsx to boost processor to power7. (*)
  07ff152... Revert changes (*)
  7b2fece... Update ChangeLog.* (*)
  2e2d883... Update ChangeLog.* (*)
  4bb4829... Do not allow -mvsx to boost processor to power7. (*)
  ffa9cd4... Update ChangeLog.* (*)

(*) This commit already exists in another branch.
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[gcc(refs/users/meissner/heads/work173-tar)] Merge commit 'refs/users/meissner/heads/work173-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work17

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e76772cbb5270839ab3fc3edb8477c49dfc4b534

commit e76772cbb5270839ab3fc3edb8477c49dfc4b534
Merge: 12ab1642ae78 1064a2f6906a
Author: Michael Meissner 
Date:   Thu Jul 25 21:39:49 2024 -0400

Merge commit 'refs/users/meissner/heads/work173-tar' of 
git+ssh://gcc.gnu.org/git/gcc into me/work173-tar

Diff:

[gcc(refs/users/meissner/heads/work173-tar)] Add ChangeLog.tar and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:12ab1642ae78a3796fc6de5a491b7944668eb9f3

commit 12ab1642ae78a3796fc6de5a491b7944668eb9f3
Author: Michael Meissner 
Date:   Mon Jul 22 15:05:41 2024 -0400

Add ChangeLog.tar and update REVISION.

2024-07-22  Michael Meissner  

gcc/

* ChangeLog.tar: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.tar | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
new file mode 100644
index ..49bf0b56d50e
--- /dev/null
+++ b/gcc/ChangeLog.tar
@@ -0,0 +1,6 @@
+ Branch work173-tar, baseline 
+
+2024-07-22   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 125a55f99c87..326918224436 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work173 branch
+work173-tar branch

[gcc/meissner/heads/work173-tar] (9 commits) Merge commit 'refs/users/meissner/heads/work173-tar' of git

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work173-tar' was updated to point to:

 e76772cbb527... Merge commit 'refs/users/meissner/heads/work173-tar' of git

It previously pointed to:

 1064a2f6906a... Merge commit 'refs/users/meissner/heads/work173-tar' of git

Diff:

Summary of changes (added commits):
---

  e76772c... Merge commit 'refs/users/meissner/heads/work173-tar' of git
  12ab164... Add ChangeLog.tar and update REVISION.
  cc5fbf9... Update ChangeLog.* (*)
  9a16e24... Do not allow -mvsx to boost processor to power7. (*)
  07ff152... Revert changes (*)
  7b2fece... Update ChangeLog.* (*)
  2e2d883... Update ChangeLog.* (*)
  4bb4829... Do not allow -mvsx to boost processor to power7. (*)
  ffa9cd4... Update ChangeLog.* (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work173-tar' matches
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[gcc(refs/users/meissner/heads/work173-dmf)] Merge commit 'refs/users/meissner/heads/work173-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work17

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:392c1d957d3a7bffc6f1f092f9110e521e255e61

commit 392c1d957d3a7bffc6f1f092f9110e521e255e61
Merge: 466f9e7017bd d8c9901389ec
Author: Michael Meissner 
Date:   Thu Jul 25 21:38:38 2024 -0400

Merge commit 'refs/users/meissner/heads/work173-dmf' of 
git+ssh://gcc.gnu.org/git/gcc into me/work173-dmf

Diff:

[gcc(refs/users/meissner/heads/work173-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:466f9e7017bd6a8f2f281a6ed50550a7097607d9

commit 466f9e7017bd6a8f2f281a6ed50550a7097607d9
Author: Michael Meissner 
Date:   Mon Jul 22 15:03:47 2024 -0400

Add ChangeLog.dmf and update REVISION.

2024-07-22  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..a638f2fb1faa
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,6 @@
+ Branch work173-dmf, baseline 
+
+2024-07-22   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 125a55f99c87..ba813185b130 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work173 branch
+work173-dmf branch

[gcc/meissner/heads/work173-dmf] (9 commits) Merge commit 'refs/users/meissner/heads/work173-dmf' of git

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work173-dmf' was updated to point to:

 392c1d957d3a... Merge commit 'refs/users/meissner/heads/work173-dmf' of git

It previously pointed to:

 d8c9901389ec... Merge commit 'refs/users/meissner/heads/work173-dmf' of git

Diff:

Summary of changes (added commits):
---

  392c1d9... Merge commit 'refs/users/meissner/heads/work173-dmf' of git
  466f9e7... Add ChangeLog.dmf and update REVISION.
  cc5fbf9... Update ChangeLog.* (*)
  9a16e24... Do not allow -mvsx to boost processor to power7. (*)
  07ff152... Revert changes (*)
  7b2fece... Update ChangeLog.* (*)
  2e2d883... Update ChangeLog.* (*)
  4bb4829... Do not allow -mvsx to boost processor to power7. (*)
  ffa9cd4... Update ChangeLog.* (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work173-dmf' matches
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[gcc(refs/users/meissner/heads/work173-bugs)] Merge commit 'refs/users/meissner/heads/work173-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:7b5c21e5698277bdeae84602a0c275c08c24d45b

commit 7b5c21e5698277bdeae84602a0c275c08c24d45b
Merge: 58807e79d3c7 b241f306435a
Author: Michael Meissner 
Date:   Thu Jul 25 17:39:23 2024 -0400

Merge commit 'refs/users/meissner/heads/work173-bugs' of 
git+ssh://gcc.gnu.org/git/gcc into me/work173-bugs

Diff:

[gcc(refs/users/meissner/heads/work173-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:58807e79d3c76380ba8cfae33ae32761906e2ac9

commit 58807e79d3c76380ba8cfae33ae32761906e2ac9
Author: Michael Meissner 
Date:   Mon Jul 22 15:06:29 2024 -0400

Add ChangeLog.bugs and update REVISION.

2024-07-22  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..902aaca7a1a5
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,6 @@
+ Branch work173-bugs, baseline 
+
+2024-07-22   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 125a55f99c87..678ec160dcf8 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work173 branch
+work173-bugs branch

[gcc/meissner/heads/work173-bugs] (9 commits) Merge commit 'refs/users/meissner/heads/work173-bugs' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work173-bugs' was updated to point to:

 7b5c21e56982... Merge commit 'refs/users/meissner/heads/work173-bugs' of gi

It previously pointed to:

 b241f306435a... Merge commit 'refs/users/meissner/heads/work173-bugs' of gi

Diff:

Summary of changes (added commits):
---

  7b5c21e... Merge commit 'refs/users/meissner/heads/work173-bugs' of gi
  58807e7... Add ChangeLog.bugs and update REVISION.
  cc5fbf9... Update ChangeLog.* (*)
  9a16e24... Do not allow -mvsx to boost processor to power7. (*)
  07ff152... Revert changes (*)
  7b2fece... Update ChangeLog.* (*)
  2e2d883... Update ChangeLog.* (*)
  4bb4829... Do not allow -mvsx to boost processor to power7. (*)
  ffa9cd4... Update ChangeLog.* (*)

(*) This commit already exists in another branch.
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[gcc(refs/users/meissner/heads/work173)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:cc5fbf9b8a424bbeefd35984634975f791035502

commit cc5fbf9b8a424bbeefd35984634975f791035502
Author: Michael Meissner 
Date:   Thu Jul 25 17:35:10 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 8 
 1 file changed, 8 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index edb837c4974f..a08f187b26cf 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -12,6 +12,14 @@ gcc/
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.
 
+gcc/testsuite/
+
+   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
+   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
+   to generate only Altivec instructions.
+   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requestion VSX
+   instructions.
+
  Branch work173, patch #13 
 
 Use architecture flags for defining _ARCH_PWR macros.

[gcc(refs/users/meissner/heads/work173)] Do not allow -mvsx to boost processor to power7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:9a16e2464bb6f6ac637119a9dbaf9648d072e057

commit 9a16e2464bb6f6ac637119a9dbaf9648d072e057
Author: Michael Meissner 
Date:   Thu Jul 25 17:34:18 2024 -0400

Do not allow -mvsx to boost processor to power7.

2024-07-25  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

gcc/testsuite/

* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add cpu=power7 when requestion VSX
instructions.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 128 +++-
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c |  40 ++--
 gcc/testsuite/gcc.target/powerpc/pr115688.c |   3 +-
 3 files changed, 111 insertions(+), 60 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 17f98607905f..6f9f3cce5582 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1172,6 +1172,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3673,7 +3674,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3937,54 +3937,8 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
-rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_DFP)
-rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
-rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
-rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
-rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
-  else if (TARGET_ALTIVEC)
-rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
+  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
+  report_architecture_mismatch ();
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target attribute or pragma which automatically enables both options,
@@ -25373,6 +25327,82 @@ rs6000_disable_incompatible_switches (void)
   return ignore_masks;
 }
 
+/* In the past, we would boost up the ISA if you selected an -m option but
+   did not specify the correct -mcpu= option.  I.e. if you added -mvsx,
+   GCC implictly would assume that you were building for at least power7.  Now,
+   

[gcc(refs/users/meissner/heads/work173)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:07ff1525306e09e69b09a29ecda55442e9a9e685

commit 07ff1525306e09e69b09a29ecda55442e9a9e685
Author: Michael Meissner 
Date:   Thu Jul 25 17:06:18 2024 -0400

Revert changes

Diff:
---
 gcc/config/rs6000/rs6000.cc | 128 +---
 1 file changed, 49 insertions(+), 79 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6f9f3cce5582..17f98607905f 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1172,7 +1172,6 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
-static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3674,6 +3673,7 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
+  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3937,8 +3937,54 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
-  report_architecture_mismatch ();
+  /* Handle explicit -mno-{altivec,vsx} and turn off all of
+ the options that depend on those flags.  */
+  ignore_masks = rs6000_disable_incompatible_switches ();
+
+  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
+ unless the user explicitly used the -mno- to disable the code.  */
+  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
+rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
+  else if (TARGET_P9_MINMAX)
+{
+  if (cpu_index >= 0)
+   {
+ if (cpu_index == PROCESSOR_POWER9)
+   {
+ /* legacy behavior: allow -mcpu=power9 with certain
+capabilities explicitly disabled.  */
+ rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
+   }
+ else
+   error ("power9 target option is incompatible with %<%s=%> "
+  "for  less than power9", "-mcpu");
+   }
+  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
+  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
+  & rs6000_isa_flags_explicit))
+   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
+  were explicitly cleared.  */
+   error ("%qs incompatible with explicitly disabled options",
+  "-mpower9-minmax");
+  else
+   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
+}
+  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
+rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
+  else if (TARGET_VSX)
+rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
+  else if (TARGET_POPCNTD)
+rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
+  else if (TARGET_DFP)
+rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
+  else if (TARGET_CMPB)
+rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
+  else if (TARGET_FPRND)
+rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
+  else if (TARGET_POPCNTB)
+rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
+  else if (TARGET_ALTIVEC)
+rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target attribute or pragma which automatically enables both options,
@@ -25327,82 +25373,6 @@ rs6000_disable_incompatible_switches (void)
   return ignore_masks;
 }
 
-/* In the past, we would boost up the ISA if you selected an -m option but
-   did not specify the correct -mcpu= option.  I.e. if you added -mvsx,
-   GCC implictly would assume that you were building for at least power7.  Now,
-   don't allow the -m option to boost up the ISA level.  But you can still
-   do -mcpu=power7 -mno-vsx or -mcpu=power5 -mno-vsx.  */
-
-static void
-report_architecture_mismatch (void)
-{
-  HOST_WIDE_INT ignore_masks = rs6000_disable_incompatible_switches ();
-
-  static const struct {
-const HOST_WIDE_INT isa_flags; /* -m optiona.  */
-const HOST_WIDE_INT arch_flags;/* -mcpu= level.  */
-const char *const arch_name;   /* architecture needed.  */
-  } mismatches[] = {
-{
-  OPTION_MASK_P9_VECTOR | OPTION_MASK_P9_MISC | OPTION_MASK_P9_MINMAX
-  | OPTION_MASK_MODULO,
-  ARCH_MASK_POWER9,
-  "cpu=power9"
-},
-
-{
-  OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO,
-  ARCH_MASK_POWER8,
-  "cpu=power8"
-},
-
-{
-  OPTION_MASK_VSX | OPTION_MASK_POPCNTD,
-  ARCH_MASK_POWER7,
-  "cpu=power7" },
-
-{
-  

[gcc(refs/users/meissner/heads/work173)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:7b2feceacc0ebdd9290dc8dc5af83b911bc4104b

commit 7b2feceacc0ebdd9290dc8dc5af83b911bc4104b
Author: Michael Meissner 
Date:   Thu Jul 25 13:33:14 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 4f8ce49c79de..edb837c4974f 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -7,7 +7,7 @@ Do not allow -mvsx to boost processor to power7.
 gcc/
 
* config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
-   Report and error if the user used an option such as -mvsx when the
+   Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

[gcc(refs/users/meissner/heads/work173)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:2e2d8833c35ea53204bf6ac3bce995f33d971091

commit 2e2d8833c35ea53204bf6ac3bce995f33d971091
Author: Michael Meissner 
Date:   Thu Jul 25 13:30:06 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d03d85ab30f5..4f8ce49c79de 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,17 @@
+ Branch work173, patch #14 
+
+Do not allow -mvsx to boost processor to power7.
+
+2024-07-25  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
+   Report and error if the user used an option such as -mvsx when the
+   default processor would not allow the option.
+   (rs6000_option_override_internal): Move some ISA checking code into
+   report_architecture_mismatch.
+
  Branch work173, patch #13 
 
 Use architecture flags for defining _ARCH_PWR macros.

[gcc(refs/users/meissner/heads/work173)] Do not allow -mvsx to boost processor to power7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:4bb48297e3fac52f9ca336593f9e097cf35c5e96

commit 4bb48297e3fac52f9ca336593f9e097cf35c5e96
Author: Michael Meissner 
Date:   Thu Jul 25 13:28:58 2024 -0400

Do not allow -mvsx to boost processor to power7.

2024-07-25  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report and error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 128 +++-
 1 file changed, 79 insertions(+), 49 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 17f98607905f..6f9f3cce5582 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1172,6 +1172,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3673,7 +3674,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3937,54 +3937,8 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
-rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_DFP)
-rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
-rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
-rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
-rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
-  else if (TARGET_ALTIVEC)
-rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
+  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
+  report_architecture_mismatch ();
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target attribute or pragma which automatically enables both options,
@@ -25373,6 +25327,82 @@ rs6000_disable_incompatible_switches (void)
   return ignore_masks;
 }
 
+/* In the past, we would boost up the ISA if you selected an -m option but
+   did not specify the correct -mcpu= option.  I.e. if you added -mvsx,
+   GCC implictly would assume that you were building for at least power7.  Now,
+   don't allow the -m option to boost up the ISA level.  But you can still
+   do -mcpu=power7 -mno-vsx or -mcpu=power5 -mno-vsx.  */
+
+static void
+report_architecture_mismatch (void)
+{
+  HOST_WIDE_INT ignore_masks = rs6000_disable_incompatible_switches ();
+
+  static const struct {
+const HOST_WIDE_INT isa_flags; /* -m optiona.  */
+const HOST_WIDE_INT arch_flags;/* -mcpu= level.  */
+const char *const arch_name;   /* 

[gcc(refs/users/meissner/heads/work173)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ffa9cd40e223976dd74a74b8526b80e272ce2cf1

commit ffa9cd40e223976dd74a74b8526b80e272ce2cf1
Author: Michael Meissner 
Date:   Thu Jul 25 13:22:51 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 106 +++--
 1 file changed, 59 insertions(+), 47 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 692e2bca61ed..d03d85ab30f5 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,77 +1,89 @@
- Branch work173, patch #2 
+ Branch work173, patch #13 
 
-Modify how arch flags are set.
+Use architecture flags for defining _ARCH_PWR macros.
 
 2024-07-24  Michael Meissner  
 
 gcc/
 
-   * config/rs6000/rs6000.cc (get_arch_flags): Modify how arch flags are
-   set.
-   * config/rs6000/rs6000.h (ARCH_FLAGS_*): Delete.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
+   use architecture flags instead of ISA flags for setting most of the
+   _ARCH_PWR* macros.
+   (rs6000_cpu_cpp_builtins): Likewise.
+   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
+   OPTION_MASK_POWER8.
+   (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
+   (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
+   (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
+   OPTION_MASK_POWER11.
+   * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
+   declaration.
+   (rs6000_target_modify_macros_ptr): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
+   (rs6000_option_override_internal): Use architecture flags instead of ISA
+   flags.
+   (rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
+   (rs6000_pragma_target_parse): Use architecture flags as well as ISA
+   flags.
+   * config/rs6000/rs6000.h (TARGET_POWER8): New macro.
+   (TARGET_POWER10): Likewise.
+   * config/rs6000/rs6000.opt (-mpower8-internal): No longer make this an
+   ISA flag.
+   (-mpower10): Likewise.
+   (-mpower11): Likewise.
 
- Branch work173, patch #2 
+ Branch work173, patch #12 
 
-Remove -mpower10 and -mpower8-internal
+Set .machine from the architecture flags
 
-2024-07-23  Michael Meissner  
+2024-07-24  Michael Meissner  
 
 gcc/
 
-   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove internal
-   options -mpower8-internal, -mpower10, and -mpower11.
-   (ISA_3_1_MASKS_SERVER): Likewise.
-   (POWER11_MASKS_SERVER): Likewise.
-   (POWERPC_MASKS): Likewise.
-   * config/rs6000/rs6000.cc (rs6000_opt_masks): Likewise.
-   * config/rs6000/rs6000.h (TARGET_POWER8): Define in terms of hardware
-   flags.
-   (TARGET_POWER10): Likewise.
-   * config/rs6000/rs6000.opt (-mpower8-internal): Do not create ISA bit.
-   (-mpower10): Likewise.
-   (-mpower11): Delete.
+   * config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine from
+   the architecture flags.
 
- Branch work173, patch #1 
+ Branch work173, patch #11 
 
-Move architecture flags from isa flags
+Make clone_targets use architecture flags.
 
-2024-07-22  Michael Meissner  
+2024-07-24  Michael Meissner  
 
 gcc/
 
-   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Add
-   support for separating the architecture flags from the ISA flags.
-   (rs6000_cpu_cpp_builtins): Likewise.
-   * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
-   declaration.
-   (rs6000_target_modify_macros_ptr): Likewise.
-   * config/rs6000/rs6000.cc (struct clone_map): Switch to using
-   architecture flags instead of isa flags.
+   * config/rs6000/rs6000.cc (struct clone_map): Switch to use architecture
+   flags instead of ISA flags for target_clone support.
(rs6000_clone_map): Likewise.
-   (rs6000_target_modify_macros_ptr): Update declaration.
+   (rs6000_clone_priority): Likewise.
+
+ Branch work173, patch #10 
+
+Separate architecture flags from ISA flags
+
+2024-07-24  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-cpus.def (ARCH_MASK_POWER*): New macros.
+   * config/rs6000/rs6000.cc (rs6000_print_isa_options): Print out the
+   architure bits.
(get_arch_flags): New function.
-   (rs6000_debug_reg_global): Add support for separating architecture
-   flags from the ISA flags.
-   (rs6000_print_isa_options):Likewise.
+   (rs6000_debug_reg_global): Add support for separating architecture flags
+   the ISA flags.
(rs6000_option_override_internal): Likewise.
-   

[gcc(refs/users/meissner/heads/work173-vpair)] Merge commit 'refs/users/meissner/heads/work173-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ba573e90575301a6e35bd0b9d628b22992e8be8c

commit ba573e90575301a6e35bd0b9d628b22992e8be8c
Merge: 2d294966cc54 8515318b78ea
Author: Michael Meissner 
Date:   Thu Jul 25 00:59:51 2024 -0400

Merge commit 'refs/users/meissner/heads/work173-vpair' of 
git+ssh://gcc.gnu.org/git/gcc into me/work173-vpair

Diff:

[gcc(refs/users/meissner/heads/work173-vpair)] Add ChangeLog.vpair and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:2d294966cc549e9ae661ab6875526049486b4d72

commit 2d294966cc549e9ae661ab6875526049486b4d72
Author: Michael Meissner 
Date:   Mon Jul 22 15:04:47 2024 -0400

Add ChangeLog.vpair and update REVISION.

2024-07-22  Michael Meissner  

gcc/

* ChangeLog.vpair: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.vpair | 6 ++
 gcc/REVISION| 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair
new file mode 100644
index ..6b79a1e6c689
--- /dev/null
+++ b/gcc/ChangeLog.vpair
@@ -0,0 +1,6 @@
+ Branch work173-vpair, baseline 
+
+2024-07-22   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 125a55f99c87..f7e937ee745e 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work173 branch
+work173-vpair branch

[gcc/meissner/heads/work173-vpair] (16 commits) Merge commit 'refs/users/meissner/heads/work173-vpair' of g

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work173-vpair' was updated to point to:

 ba573e905753... Merge commit 'refs/users/meissner/heads/work173-vpair' of g

It previously pointed to:

 8515318b78ea... Add ChangeLog.vpair and update REVISION.

Diff:

Summary of changes (added commits):
---

  ba573e9... Merge commit 'refs/users/meissner/heads/work173-vpair' of g
  2d29496... Add ChangeLog.vpair and update REVISION.
  dc0cb0a... Use architecture flags for defining _ARCH_PWR macros. (*)
  377cc95... Set .machine from the architecture flags (*)
  ecaac2a... Make clone_targets use architecture flags. (*)
  db3b4de... Separate architecture flags from ISA flags (*)
  11ca5a8... Revert changes (*)
  b78f446... Update ChangeLog.* (*)
  f3a1dcd... Modify how arch flags are set. (*)
  93b27dd... Update ChangeLog.* (*)
  d64c5ff... Remove -mpower10 and -mpower8-internal (*)
  191fcce... Update ChangeLog.* (*)
  5021a6c... Move architecture flags from isa flags (*)
  f5939df... Revert changes (*)
  a423861... Update ChangeLog.* (*)
  f4fdb95... Move architecture flags from isa flags (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work173-vpair' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work173-test)] Add ChangeLog.test and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:07826cbe9d5665a0e3cc763cce10864dc54e1fb7

commit 07826cbe9d5665a0e3cc763cce10864dc54e1fb7
Author: Michael Meissner 
Date:   Mon Jul 22 15:07:51 2024 -0400

Add ChangeLog.test and update REVISION.

2024-07-22  Michael Meissner  

gcc/

* ChangeLog.test: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.test | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
new file mode 100644
index ..03e20764eb03
--- /dev/null
+++ b/gcc/ChangeLog.test
@@ -0,0 +1,6 @@
+ Branch work173-test, baseline 
+
+2024-07-22   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 125a55f99c87..858e261ae8fb 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work173 branch
+work173-test branch

[gcc(refs/users/meissner/heads/work173-test)] Merge commit 'refs/users/meissner/heads/work173-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:903574fd9243e255f47543de8aaf07e4aede42da

commit 903574fd9243e255f47543de8aaf07e4aede42da
Merge: 07826cbe9d56 7a7b57e177e0
Author: Michael Meissner 
Date:   Thu Jul 25 00:58:25 2024 -0400

Merge commit 'refs/users/meissner/heads/work173-test' of 
git+ssh://gcc.gnu.org/git/gcc into me/work173-test

Diff:

[gcc/meissner/heads/work173-test] (16 commits) Merge commit 'refs/users/meissner/heads/work173-test' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work173-test' was updated to point to:

 903574fd9243... Merge commit 'refs/users/meissner/heads/work173-test' of gi

It previously pointed to:

 7a7b57e177e0... Add ChangeLog.test and update REVISION.

Diff:

Summary of changes (added commits):
---

  903574f... Merge commit 'refs/users/meissner/heads/work173-test' of gi
  07826cb... Add ChangeLog.test and update REVISION.
  dc0cb0a... Use architecture flags for defining _ARCH_PWR macros. (*)
  377cc95... Set .machine from the architecture flags (*)
  ecaac2a... Make clone_targets use architecture flags. (*)
  db3b4de... Separate architecture flags from ISA flags (*)
  11ca5a8... Revert changes (*)
  b78f446... Update ChangeLog.* (*)
  f3a1dcd... Modify how arch flags are set. (*)
  93b27dd... Update ChangeLog.* (*)
  d64c5ff... Remove -mpower10 and -mpower8-internal (*)
  191fcce... Update ChangeLog.* (*)
  5021a6c... Move architecture flags from isa flags (*)
  f5939df... Revert changes (*)
  a423861... Update ChangeLog.* (*)
  f4fdb95... Move architecture flags from isa flags (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work173-test' matches
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no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work173-tar)] Merge commit 'refs/users/meissner/heads/work173-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work17

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:1064a2f6906a3570e576594f45d8f1632979eb8d

commit 1064a2f6906a3570e576594f45d8f1632979eb8d
Merge: 2271a8f96299 c8b6ce9637ad
Author: Michael Meissner 
Date:   Thu Jul 25 00:57:11 2024 -0400

Merge commit 'refs/users/meissner/heads/work173-tar' of 
git+ssh://gcc.gnu.org/git/gcc into me/work173-tar

Diff:

[gcc(refs/users/meissner/heads/work173-tar)] Add ChangeLog.tar and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:2271a8f962993dbd457a1932f0c4084b5373ce94

commit 2271a8f962993dbd457a1932f0c4084b5373ce94
Author: Michael Meissner 
Date:   Mon Jul 22 15:05:41 2024 -0400

Add ChangeLog.tar and update REVISION.

2024-07-22  Michael Meissner  

gcc/

* ChangeLog.tar: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.tar | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
new file mode 100644
index ..49bf0b56d50e
--- /dev/null
+++ b/gcc/ChangeLog.tar
@@ -0,0 +1,6 @@
+ Branch work173-tar, baseline 
+
+2024-07-22   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 125a55f99c87..326918224436 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work173 branch
+work173-tar branch

[gcc/meissner/heads/work173-tar] (16 commits) Merge commit 'refs/users/meissner/heads/work173-tar' of git

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work173-tar' was updated to point to:

 1064a2f6906a... Merge commit 'refs/users/meissner/heads/work173-tar' of git

It previously pointed to:

 c8b6ce9637ad... Add ChangeLog.tar and update REVISION.

Diff:

Summary of changes (added commits):
---

  1064a2f... Merge commit 'refs/users/meissner/heads/work173-tar' of git
  2271a8f... Add ChangeLog.tar and update REVISION.
  dc0cb0a... Use architecture flags for defining _ARCH_PWR macros. (*)
  377cc95... Set .machine from the architecture flags (*)
  ecaac2a... Make clone_targets use architecture flags. (*)
  db3b4de... Separate architecture flags from ISA flags (*)
  11ca5a8... Revert changes (*)
  b78f446... Update ChangeLog.* (*)
  f3a1dcd... Modify how arch flags are set. (*)
  93b27dd... Update ChangeLog.* (*)
  d64c5ff... Remove -mpower10 and -mpower8-internal (*)
  191fcce... Update ChangeLog.* (*)
  5021a6c... Move architecture flags from isa flags (*)
  f5939df... Revert changes (*)
  a423861... Update ChangeLog.* (*)
  f4fdb95... Move architecture flags from isa flags (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work173-tar' matches
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[gcc(refs/users/meissner/heads/work173-dmf)] Merge commit 'refs/users/meissner/heads/work173-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work17

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d8c9901389ecc40f743f432cc433c860924bbfc9

commit d8c9901389ecc40f743f432cc433c860924bbfc9
Merge: fe246621c60b 47fc63ebcee7
Author: Michael Meissner 
Date:   Thu Jul 25 00:56:05 2024 -0400

Merge commit 'refs/users/meissner/heads/work173-dmf' of 
git+ssh://gcc.gnu.org/git/gcc into me/work173-dmf

Diff:

[gcc(refs/users/meissner/heads/work173-dmf)] Add ChangeLog.dmf and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:fe246621c60bd63f6007bacc6b5092ea56583ef0

commit fe246621c60bd63f6007bacc6b5092ea56583ef0
Author: Michael Meissner 
Date:   Mon Jul 22 15:03:47 2024 -0400

Add ChangeLog.dmf and update REVISION.

2024-07-22  Michael Meissner  

gcc/

* ChangeLog.dmf: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.dmf | 6 ++
 gcc/REVISION  | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf
new file mode 100644
index ..a638f2fb1faa
--- /dev/null
+++ b/gcc/ChangeLog.dmf
@@ -0,0 +1,6 @@
+ Branch work173-dmf, baseline 
+
+2024-07-22   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 125a55f99c87..ba813185b130 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work173 branch
+work173-dmf branch

[gcc/meissner/heads/work173-dmf] (16 commits) Merge commit 'refs/users/meissner/heads/work173-dmf' of git

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work173-dmf' was updated to point to:

 d8c9901389ec... Merge commit 'refs/users/meissner/heads/work173-dmf' of git

It previously pointed to:

 47fc63ebcee7... Add ChangeLog.dmf and update REVISION.

Diff:

Summary of changes (added commits):
---

  d8c9901... Merge commit 'refs/users/meissner/heads/work173-dmf' of git
  fe24662... Add ChangeLog.dmf and update REVISION.
  dc0cb0a... Use architecture flags for defining _ARCH_PWR macros. (*)
  377cc95... Set .machine from the architecture flags (*)
  ecaac2a... Make clone_targets use architecture flags. (*)
  db3b4de... Separate architecture flags from ISA flags (*)
  11ca5a8... Revert changes (*)
  b78f446... Update ChangeLog.* (*)
  f3a1dcd... Modify how arch flags are set. (*)
  93b27dd... Update ChangeLog.* (*)
  d64c5ff... Remove -mpower10 and -mpower8-internal (*)
  191fcce... Update ChangeLog.* (*)
  5021a6c... Move architecture flags from isa flags (*)
  f5939df... Revert changes (*)
  a423861... Update ChangeLog.* (*)
  f4fdb95... Move architecture flags from isa flags (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work173-dmf' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work173-bugs)] Add ChangeLog.bugs and update REVISION.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:623a257c9517c3353ea7a3d86aa179f865d2293c

commit 623a257c9517c3353ea7a3d86aa179f865d2293c
Author: Michael Meissner 
Date:   Mon Jul 22 15:06:29 2024 -0400

Add ChangeLog.bugs and update REVISION.

2024-07-22  Michael Meissner  

gcc/

* ChangeLog.bugs: New file for branch.
* REVISION: Update.

Diff:
---
 gcc/ChangeLog.bugs | 6 ++
 gcc/REVISION   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
new file mode 100644
index ..902aaca7a1a5
--- /dev/null
+++ b/gcc/ChangeLog.bugs
@@ -0,0 +1,6 @@
+ Branch work173-bugs, baseline 
+
+2024-07-22   Michael Meissner  
+
+   Clone branch
+
diff --git a/gcc/REVISION b/gcc/REVISION
index 125a55f99c87..678ec160dcf8 100644
--- a/gcc/REVISION
+++ b/gcc/REVISION
@@ -1 +1 @@
-work173 branch
+work173-bugs branch

[gcc(refs/users/meissner/heads/work173-bugs)] Merge commit 'refs/users/meissner/heads/work173-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b241f306435a010151d59b3468286303ea2322e8

commit b241f306435a010151d59b3468286303ea2322e8
Merge: 623a257c9517 34348576103d
Author: Michael Meissner 
Date:   Thu Jul 25 00:54:55 2024 -0400

Merge commit 'refs/users/meissner/heads/work173-bugs' of 
git+ssh://gcc.gnu.org/git/gcc into me/work173-bugs

Diff:

[gcc/meissner/heads/work173-bugs] (16 commits) Merge commit 'refs/users/meissner/heads/work173-bugs' of gi

[Michael Meissner via Gcc-cvs]

The branch 'meissner/heads/work173-bugs' was updated to point to:

 b241f306435a... Merge commit 'refs/users/meissner/heads/work173-bugs' of gi

It previously pointed to:

 34348576103d... Add ChangeLog.bugs and update REVISION.

Diff:

Summary of changes (added commits):
---

  b241f30... Merge commit 'refs/users/meissner/heads/work173-bugs' of gi
  623a257... Add ChangeLog.bugs and update REVISION.
  dc0cb0a... Use architecture flags for defining _ARCH_PWR macros. (*)
  377cc95... Set .machine from the architecture flags (*)
  ecaac2a... Make clone_targets use architecture flags. (*)
  db3b4de... Separate architecture flags from ISA flags (*)
  11ca5a8... Revert changes (*)
  b78f446... Update ChangeLog.* (*)
  f3a1dcd... Modify how arch flags are set. (*)
  93b27dd... Update ChangeLog.* (*)
  d64c5ff... Remove -mpower10 and -mpower8-internal (*)
  191fcce... Update ChangeLog.* (*)
  5021a6c... Move architecture flags from isa flags (*)
  f5939df... Revert changes (*)
  a423861... Update ChangeLog.* (*)
  f4fdb95... Move architecture flags from isa flags (*)

(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work173-bugs' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.

[gcc(refs/users/meissner/heads/work173)] Set .machine from the architecture flags

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:377cc95fa1ec8b8f5000c205f740cc996534613d

commit 377cc95fa1ec8b8f5000c205f740cc996534613d
Author: Michael Meissner 
Date:   Wed Jul 24 19:25:30 2024 -0400

Set .machine from the architecture flags

2024-07-24  Michael Meissner  

gcc/

* config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine 
from
the architecture flags.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7ebf70339324..f736a87db4a9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5960,27 +5960,28 @@ rs6000_machine_from_flags (void)
 return "ppc64";
 #endif
 
+  HOST_WIDE_INT arch_flags = rs6000_arch_flags;
   HOST_WIDE_INT flags = rs6000_isa_flags;
 
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
 | OPTION_MASK_ALTIVEC);
 
-  if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER11) != 0)
 return "power11";
-  if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER10) != 0)
 return "power10";
-  if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER9) != 0)
 return "power9";
-  if ((flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER8) != 0)
 return "power8";
-  if ((flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 return "power7";
-  if ((flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 return "power6";
-  if ((flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 return "power5";
-  if ((flags & ISA_2_1_MASKS) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 return "power4";
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 return "ppc64";

[gcc(refs/users/meissner/heads/work173)] Make clone_targets use architecture flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ecaac2a990989cde515d3ad0159a7db134ff4893

commit ecaac2a990989cde515d3ad0159a7db134ff4893
Author: Michael Meissner 
Date:   Wed Jul 24 19:21:47 2024 -0400

Make clone_targets use architecture flags.

2024-07-24  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (struct clone_map): Switch to use 
architecture
flags instead of ISA flags for target_clone support.
(rs6000_clone_map): Likewise.
(rs6000_clone_priority): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6ceea856c0e4..7ebf70339324 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -251,17 +251,17 @@ enum {
 
 /* Map compiler ISA bits into HWCAP names.  */
 struct clone_map {
-  HOST_WIDE_INT isa_mask;  /* rs6000_isa mask */
+  HOST_WIDE_INT arch_mask; /* rs6000_arch_mask.  */
   const char *name;/* name to use in __builtin_cpu_supports.  */
 };
 
 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
-  { 0, "" },   /* Default options.  */
-  { OPTION_MASK_CMPB,  "arch_2_05" },  /* ISA 2.05 (power6).  */
-  { OPTION_MASK_POPCNTD,   "arch_2_06" },  /* ISA 2.06 (power7).  */
-  { OPTION_MASK_P8_VECTOR, "arch_2_07" },  /* ISA 2.07 (power8).  */
-  { OPTION_MASK_P9_VECTOR, "arch_3_00" },  /* ISA 3.0 (power9).  */
-  { OPTION_MASK_POWER10,   "arch_3_1" },   /* ISA 3.1 (power10).  */
+  { 0, "" },   /* Default options.  */
+  { ARCH_MASK_POWER6,  "arch_2_05" },  /* ISA 2.05 (power6).  */
+  { ARCH_MASK_POWER7,  "arch_2_06" },  /* ISA 2.06 (power7).  */
+  { ARCH_MASK_POWER8,  "arch_2_07" },  /* ISA 2.07 (power8).  */
+  { ARCH_MASK_POWER9,  "arch_3_00" },  /* ISA 3.0 (power9).  */
+  { ARCH_MASK_POWER10, "arch_3_1" },   /* ISA 3.1 (power10).  */
 };
 
 
@@ -25396,7 +25396,7 @@ static int
 rs6000_clone_priority (tree fndecl)
 {
   tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
-  HOST_WIDE_INT isa_masks;
+  HOST_WIDE_INT arch_masks;
   int ret = CLONE_DEFAULT;
   tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
   const char *attrs_str = NULL;
@@ -25412,12 +25412,12 @@ rs6000_clone_priority (tree fndecl)
fn_opts = target_option_default_node;
 
   if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
-   isa_masks = rs6000_isa_flags;
+   arch_masks = rs6000_arch_flags;
   else
-   isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
+   arch_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_arch_flags;
 
   for (ret = CLONE_MAX - 1; ret != 0; ret--)
-   if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
+   if ((rs6000_clone_map[ret].arch_mask & arch_masks) != 0)
  break;
 }

[gcc(refs/users/meissner/heads/work173)] Use architecture flags for defining _ARCH_PWR macros.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:dc0cb0ad7c3f9388eadccdd9bc1cd0f1d11b2fae

commit dc0cb0ad7c3f9388eadccdd9bc1cd0f1d11b2fae
Author: Michael Meissner 
Date:   Wed Jul 24 19:51:02 2024 -0400

Use architecture flags for defining _ARCH_PWR macros.

2024-07-24  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Likewise.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
OPTION_MASK_POWER11.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER8): New macro.
(TARGET_POWER10): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): No longer make this 
an
ISA flag.
(-mpower10): Likewise.
(-mpower11): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 23 ---
 gcc/config/rs6000/rs6000-cpus.def |  8 +---
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 19 +++
 gcc/config/rs6000/rs6000.h|  6 ++
 gcc/config/rs6000/rs6000.opt  | 11 ++-
 6 files changed, 35 insertions(+), 37 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 68519e1397f1..2ffaee165885 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -421,21 +422,21 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((flags & OPTION_MASK_POPCNTD) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_MASK_POWER8) != 0)
+  if ((arch_flags & ARCH_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
-  if ((flags & OPTION_MASK_MODULO) != 0)
+  if ((arch_flags & ARCH_MASK_POWER9) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
-  if ((flags & OPTION_MASK_POWER10) != 0)
+  if ((arch_flags & ARCH_MASK_POWER10) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
-  if ((flags & OPTION_MASK_POWER11) != 0)
+  if ((arch_flags & ARCH_MASK_POWER11) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
@@ -605,7 +606,7 @@ void
 rs6000_cpu_cpp_builtins (cpp_reader *pfile)
 {
   /* Define all of the common macros.  */
-  rs6000_target_modify_macros (true, rs6000_isa_flags);
+  rs6000_target_modify_macros (true, rs6000_isa_flags, rs6000_arch_flags);
 
   if (TARGET_FRE)
 

[gcc(refs/users/meissner/heads/work173)] Separate architecture flags from ISA flags

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:db3b4de65c0e0f05fa78723d978de35519efb482

commit db3b4de65c0e0f05fa78723d978de35519efb482
Author: Michael Meissner 
Date:   Wed Jul 24 19:16:06 2024 -0400

Separate architecture flags from ISA flags

2024-07-24  Michael Meissner  

gcc/

* config/rs6000/rs6000-cpus.def (ARCH_MASK_POWER*): New macros.
* config/rs6000/rs6000.cc (rs6000_print_isa_options): Print out the
architure bits.
(get_arch_flags): New function.
(rs6000_debug_reg_global): Add support for separating architecture 
flags
the ISA flags.
(rs6000_option_override_internal): Likewise.
(struct rs6000_arch_mask): Likewise.
(rs6000_arch_masks): Likewise.
(rs6000_function_specific_save): Likewise.
(rs6000_function_specific_restore): Likewise.
(rs6000_function_specific_print): Likewise.
(rs6000_print_options_internal): Likewise.
(rs6000_can_inline_p): Likewise.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save area for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/rs6000-cpus.def |  15 
 gcc/config/rs6000/rs6000.cc   | 153 +-
 gcc/config/rs6000/rs6000.h|   1 -
 gcc/config/rs6000/rs6000.opt  |   8 ++
 4 files changed, 159 insertions(+), 18 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 84fac8bdac1d..9c982df89dae 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -158,6 +158,21 @@
 
 #endif
 
+/* List of architecture masks (to set the _ARCH_PWR flag that don't have a
+   separate -m option.  It the past, we would have -mpower11, -mpower10,
+   -mpower9, etc. but bad things would happen if the user did -mpower10 instead
+   of -mcpu=power10.  Over time, older options will be removed as -m
+   and moved into this list.  */
+
+#define ARCH_MASK_POWER4   (HOST_WIDE_INT_1 << 1)
+#define ARCH_MASK_POWER5   (HOST_WIDE_INT_1 << 2)
+#define ARCH_MASK_POWER6   (HOST_WIDE_INT_1 << 3)
+#define ARCH_MASK_POWER7   (HOST_WIDE_INT_1 << 4)
+#define ARCH_MASK_POWER8   (HOST_WIDE_INT_1 << 5)
+#define ARCH_MASK_POWER9   (HOST_WIDE_INT_1 << 6)
+#define ARCH_MASK_POWER10  (HOST_WIDE_INT_1 << 7)
+#define ARCH_MASK_POWER11  (HOST_WIDE_INT_1 << 8)
+
 /* This table occasionally claims that a processor does not support a
particular feature even though it does, but the feature is slower than the
alternative.  Thus, it shouldn't be relied on as a complete description of
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index eddd2adbab59..6ceea856c0e4 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1170,7 +1170,7 @@ enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, 
enum reg_class)
 const int INSN_NOT_AVAILABLE = -1;
 
 static void rs6000_print_isa_options (FILE *, int, const char *,
- HOST_WIDE_INT);
+ HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
@@ -1817,6 +1817,57 @@ rs6000_cpu_name_lookup (const char *name)
   return -1;
 }
 
+
+/* Map the processor into the arch bits that are set off of -mcpu= instead
+   of having an internal -m option.  */
+
+static HOST_WIDE_INT
+get_arch_flags (int cpu_index)
+{
+  HOST_WIDE_INT ret = 0;
+
+  if (cpu_index >= 0)
+switch (processor_target_table[cpu_index].processor)
+  {
+  case PROCESSOR_POWER11:
+   ret |= ARCH_MASK_POWER11;
+   /* fall through.  */
+
+  case PROCESSOR_POWER10:
+   ret |= ARCH_MASK_POWER10;
+   /* fall through.  */
+
+  case PROCESSOR_POWER9:
+   ret |= ARCH_MASK_POWER9;
+   /* fall through.  */
+
+  case PROCESSOR_POWER8:
+   ret |= ARCH_MASK_POWER8;
+   /* fall through.  */
+
+  case PROCESSOR_POWER7:
+   ret |= ARCH_MASK_POWER7;
+   /* fall through.  */
+
+  case PROCESSOR_POWER6:
+   ret |= ARCH_MASK_POWER6;
+   /* fall through.  */
+
+  case PROCESSOR_POWER5:
+   ret |= ARCH_MASK_POWER5;
+   /* fall through.  */
+
+  case PROCESSOR_POWER4:
+   ret |= ARCH_MASK_POWER4;
+   break;
+
+  default:
+   break;
+  }
+
+  return ret;
+}
+
 
 /* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
@@ -2398,9 +2449,10 @@ rs6000_debug_reg_global (void)
   const char *name = processor_target_table[rs6000_cpu_index].name;
   HOST_WIDE_INT flags
= processor_target_table[rs6000_cpu_index].target_enable;
+  HOST_WIDE_INT arch_flags = get_arch_flags (rs6000_cpu_index);
 
   sprintf (flags_buffer, "-mcpu=%s flags", name);

[gcc(refs/users/meissner/heads/work173)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:11ca5a8c33f06bf3c1b663870a979638b6cde2c3

commit 11ca5a8c33f06bf3c1b663870a979638b6cde2c3
Author: Michael Meissner 
Date:   Wed Jul 24 18:46:33 2024 -0400

Revert changes

Diff:
---
 gcc/config/rs6000/rs6000-c.cc |  23 ++---
 gcc/config/rs6000/rs6000-cpus.def |   8 +-
 gcc/config/rs6000/rs6000-protos.h |   5 +-
 gcc/config/rs6000/rs6000.cc   | 211 --
 gcc/config/rs6000/rs6000.h|  31 --
 gcc/config/rs6000/rs6000.opt  |  19 ++--
 6 files changed, 73 insertions(+), 224 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 2ffaee165885..68519e1397f1 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,8 +338,7 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
-HOST_WIDE_INT arch_flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -412,7 +411,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
+  /* rs6000_isa_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -422,21 +421,21 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((arch_flags & ARCH_MASK_POWER4) != 0)
+  if ((flags & OPTION_MASK_POPCNTB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((arch_flags & ARCH_MASK_POWER5) != 0)
+  if ((flags & OPTION_MASK_FPRND) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((arch_flags & ARCH_MASK_POWER6) != 0)
+  if ((flags & OPTION_MASK_CMPB) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((arch_flags & ARCH_MASK_POWER7) != 0)
+  if ((flags & OPTION_MASK_POPCNTD) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((arch_flags & ARCH_MASK_POWER8) != 0)
+  if ((flags & OPTION_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
-  if ((arch_flags & ARCH_MASK_POWER9) != 0)
+  if ((flags & OPTION_MASK_MODULO) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
-  if ((arch_flags & ARCH_MASK_POWER10) != 0)
+  if ((flags & OPTION_MASK_POWER10) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
-  if ((arch_flags & ARCH_MASK_POWER11) != 0)
+  if ((flags & OPTION_MASK_POWER11) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
@@ -606,7 +605,7 @@ void
 rs6000_cpu_cpp_builtins (cpp_reader *pfile)
 {
   /* Define all of the common macros.  */
-  rs6000_target_modify_macros (true, rs6000_isa_flags, rs6000_arch_flags);
+  rs6000_target_modify_macros (true, rs6000_isa_flags);
 
   if (TARGET_FRE)
 builtin_define ("__RECIP__");
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index a3568898b0b6..84fac8bdac1d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,6 +47,7 @@
fusion here, instead set it in rs6000.cc if we are tuning for a power8
system.  */
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
+| OPTION_MASK_POWER8   \
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
@@ -82,9 +83,11 @@
 | OPTION_MASK_PREFIXED)
 
 #define ISA_3_1_MASKS_SERVER   (ISA_3_0_MASKS_SERVER   \
+| OPTION_MASK_POWER10  \
 | OTHER_POWER10_MASKS)
 
-#define POWER11_MASKS_SERVER   ISA_3_1_MASKS_SERVER
+#define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
+ | OPTION_MASK_POWER11)
 
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
@@ -122,6 +125,8 @@
 | OPTION_MASK_FLOAT128_HW  \
 | OPTION_MASK_FLOAT128_KEYWORD \
 | 

[gcc(refs/users/meissner/heads/work173)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:b78f446a7e962266a3dd4be002bf54f2dec4fe64

commit b78f446a7e962266a3dd4be002bf54f2dec4fe64
Author: Michael Meissner 
Date:   Wed Jul 24 12:56:54 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 12 
 1 file changed, 12 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d50a89e9c876..692e2bca61ed 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,17 @@
  Branch work173, patch #2 
 
+Modify how arch flags are set.
+
+2024-07-24  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (get_arch_flags): Modify how arch flags are
+   set.
+   * config/rs6000/rs6000.h (ARCH_FLAGS_*): Delete.
+
+ Branch work173, patch #2 
+
 Remove -mpower10 and -mpower8-internal
 
 2024-07-23  Michael Meissner  

[gcc(refs/users/meissner/heads/work173)] Modify how arch flags are set.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:f3a1dcd7eae79994ad592ba3245deec657e60588

commit f3a1dcd7eae79994ad592ba3245deec657e60588
Author: Michael Meissner 
Date:   Wed Jul 24 12:55:44 2024 -0400

Modify how arch flags are set.

2024-07-24  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (get_arch_flags): Modify how arch flags 
are
set.
* config/rs6000/rs6000.h (ARCH_FLAGS_*): Delete.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 55 +++--
 gcc/config/rs6000/rs6000.h  | 10 -
 2 files changed, 38 insertions(+), 27 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 4550fd44036e..17f98607905f 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1824,27 +1824,48 @@ rs6000_cpu_name_lookup (const char *name)
 static HOST_WIDE_INT
 get_arch_flags (int cpu_index)
 {
-  if (cpu_index < 0)
-return 0;
+  HOST_WIDE_INT ret = 0;
 
-  enum processor_type processor = processor_target_table[cpu_index].processor;
+  if (cpu_index >= 0)
+switch (processor_target_table[cpu_index].processor)
+  {
+  case PROCESSOR_POWER11:
+   ret |= ARCH_MASK_POWER11;
+   /* fall through.  */
 
-  switch (processor)
-{
-case PROCESSOR_POWER4:  return ARCH_FLAGS_POWER4;
-case PROCESSOR_POWER5:  return ARCH_FLAGS_POWER5;
-case PROCESSOR_POWER6:  return ARCH_FLAGS_POWER6;
-case PROCESSOR_POWER7:  return ARCH_FLAGS_POWER7;
-case PROCESSOR_POWER8:  return ARCH_FLAGS_POWER8;
-case PROCESSOR_POWER9:  return ARCH_FLAGS_POWER9;
-case PROCESSOR_POWER10: return ARCH_FLAGS_POWER10;
-case PROCESSOR_POWER11: return ARCH_FLAGS_POWER11;
+  case PROCESSOR_POWER10:
+   ret |= ARCH_MASK_POWER10;
+   /* fall through.  */
 
-default:
-  break;
-}
+  case PROCESSOR_POWER9:
+   ret |= ARCH_MASK_POWER9;
+   /* fall through.  */
 
-  return 0;
+  case PROCESSOR_POWER8:
+   ret |= ARCH_MASK_POWER8;
+   /* fall through.  */
+
+  case PROCESSOR_POWER7:
+   ret |= ARCH_MASK_POWER7;
+   /* fall through.  */
+
+  case PROCESSOR_POWER6:
+   ret |= ARCH_MASK_POWER6;
+   /* fall through.  */
+
+  case PROCESSOR_POWER5:
+   ret |= ARCH_MASK_POWER5;
+   /* fall through.  */
+
+  case PROCESSOR_POWER4:
+   ret |= ARCH_MASK_POWER4;
+   break;
+
+  default:
+   break;
+  }
+
+  return ret;
 }
 
 
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 548ef9c0fa50..dbc844a7da10 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2508,16 +2508,6 @@ enum arch_bits {
 #define ARCH_MASK_POWER10  (HOST_WIDE_INT_1 << ARCH_ENUM_POWER10)
 #define ARCH_MASK_POWER11  (HOST_WIDE_INT_1 << ARCH_ENUM_POWER11)
 
-/* Flags to set the architecture bits for a given cpu.  */
-#define ARCH_FLAGS_POWER4  ARCH_MASK_POWER4
-#define ARCH_FLAGS_POWER5  (ARCH_FLAGS_POWER4  | ARCH_MASK_POWER5)
-#define ARCH_FLAGS_POWER6  (ARCH_FLAGS_POWER5  | ARCH_MASK_POWER6)
-#define ARCH_FLAGS_POWER7  (ARCH_FLAGS_POWER6  | ARCH_MASK_POWER7)
-#define ARCH_FLAGS_POWER8  (ARCH_FLAGS_POWER7  | ARCH_MASK_POWER8)
-#define ARCH_FLAGS_POWER9  (ARCH_FLAGS_POWER8  | ARCH_MASK_POWER9)
-#define ARCH_FLAGS_POWER10 (ARCH_FLAGS_POWER9  | ARCH_MASK_POWER10)
-#define ARCH_FLAGS_POWER11 (ARCH_FLAGS_POWER10 | ARCH_MASK_POWER11)
-
 /* We used to use -mpower8-internal and -mpower10 as an ISA bit, switch to use
an architecture bit.  */
 #define TARGET_POWER8  ((rs6000_arch_flags & ARCH_MASK_POWER8)  != 0)

[gcc(refs/users/meissner/heads/work173)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:93b27dd2636726ef51500e0068891ca250242c3d

commit 93b27dd2636726ef51500e0068891ca250242c3d
Author: Michael Meissner 
Date:   Tue Jul 23 11:14:51 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 21 +
 1 file changed, 21 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index e1a07e54c56c..d50a89e9c876 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,24 @@
+ Branch work173, patch #2 
+
+Remove -mpower10 and -mpower8-internal
+
+2024-07-23  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove internal
+   options -mpower8-internal, -mpower10, and -mpower11.
+   (ISA_3_1_MASKS_SERVER): Likewise.
+   (POWER11_MASKS_SERVER): Likewise.
+   (POWERPC_MASKS): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_opt_masks): Likewise.
+   * config/rs6000/rs6000.h (TARGET_POWER8): Define in terms of hardware
+   flags.
+   (TARGET_POWER10): Likewise.
+   * config/rs6000/rs6000.opt (-mpower8-internal): Do not create ISA bit.
+   (-mpower10): Likewise.
+   (-mpower11): Delete.
+
  Branch work173, patch #1 
 
 Move architecture flags from isa flags

[gcc(refs/users/meissner/heads/work173)] Remove -mpower10 and -mpower8-internal

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d64c5ffbfe1f13536d8cc5f6ffd2fbbdc3e1873c

commit d64c5ffbfe1f13536d8cc5f6ffd2fbbdc3e1873c
Author: Michael Meissner 
Date:   Tue Jul 23 11:14:05 2024 -0400

Remove -mpower10 and -mpower8-internal

2024-07-23  Michael Meissner  

gcc/

* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove 
internal
options -mpower8-internal, -mpower10, and -mpower11.
(ISA_3_1_MASKS_SERVER): Likewise.
(POWER11_MASKS_SERVER): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (TARGET_POWER8): Define in terms of 
hardware
flags.
(TARGET_POWER10): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Do not create ISA 
bit.
(-mpower10): Likewise.
(-mpower11): Delete.

Diff:
---
 gcc/config/rs6000/rs6000-cpus.def |  8 +---
 gcc/config/rs6000/rs6000.cc   |  2 --
 gcc/config/rs6000/rs6000.h|  5 +
 gcc/config/rs6000/rs6000.opt  | 11 ++-
 4 files changed, 8 insertions(+), 18 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index 84fac8bdac1d..a3568898b0b6 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,7 +47,6 @@
fusion here, instead set it in rs6000.cc if we are tuning for a power8
system.  */
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER   \
-| OPTION_MASK_POWER8   \
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
@@ -83,11 +82,9 @@
 | OPTION_MASK_PREFIXED)
 
 #define ISA_3_1_MASKS_SERVER   (ISA_3_0_MASKS_SERVER   \
-| OPTION_MASK_POWER10  \
 | OTHER_POWER10_MASKS)
 
-#define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
- | OPTION_MASK_POWER11)
+#define POWER11_MASKS_SERVER   ISA_3_1_MASKS_SERVER
 
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX\
@@ -125,8 +122,6 @@
 | OPTION_MASK_FLOAT128_HW  \
 | OPTION_MASK_FLOAT128_KEYWORD \
 | OPTION_MASK_FPRND\
-| OPTION_MASK_POWER10  \
-| OPTION_MASK_POWER11  \
 | OPTION_MASK_P10_FUSION   \
 | OPTION_MASK_HTM  \
 | OPTION_MASK_ISEL \
@@ -135,7 +130,6 @@
 | OPTION_MASK_MODULO   \
 | OPTION_MASK_MULHW\
 | OPTION_MASK_NO_UPDATE\
-| OPTION_MASK_POWER8   \
 | OPTION_MASK_P8_FUSION\
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_P9_MINMAX\
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 381d439c0cf3..4550fd44036e 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -24526,8 +24526,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
   { "float128",OPTION_MASK_FLOAT128_KEYWORD,   false, 
true  },
   { "float128-hardware",   OPTION_MASK_FLOAT128_HW,false, true  },
   { "fprnd",   OPTION_MASK_FPRND,  false, true  },
-  { "power10", OPTION_MASK_POWER10,false, true  },
-  { "power11", OPTION_MASK_POWER11,false, false },
   { "hard-dfp",OPTION_MASK_DFP,false, 
true  },
   { "htm", OPTION_MASK_HTM,false, true  },
   { "isel",OPTION_MASK_ISEL,   false, true  },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 2053de1fc176..548ef9c0fa50 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2517,3 +2517,8 @@ enum arch_bits {
 #define ARCH_FLAGS_POWER9  (ARCH_FLAGS_POWER8  | ARCH_MASK_POWER9)
 #define ARCH_FLAGS_POWER10 (ARCH_FLAGS_POWER9  | ARCH_MASK_POWER10)
 #define ARCH_FLAGS_POWER11 (ARCH_FLAGS_POWER10 | ARCH_MASK_POWER11)
+
+/* We used to use -mpower8-internal and 

[gcc(refs/users/meissner/heads/work173)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:191fcce31172349eacedc462c47cd76893cb437e

commit 191fcce31172349eacedc462c47cd76893cb437e
Author: Michael Meissner 
Date:   Tue Jul 23 10:13:09 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 4 
 1 file changed, 4 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 00e2e045c60b..e1a07e54c56c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -25,10 +25,14 @@ gcc/
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): Likewise.
(rs6000_pragma_target_parse): Likewise.
+   (rs6000_function_specific_save): Likewise.
+   (rs6000_function_specific_restore): Likewise.
(rs6000_function_specific_print): Likewise.
(rs6000_print_options_internal): Likewise.
(rs6000_print_isa_options): Likewise.
(rs6000_clone_priority): Switch to using architecture flags.
+   (rs6000_can_inline_p): Check if the arch flags match along with the isa
+   flags.
* config/rs6000/rs6000.h (enum arch_bits): New enumeration.
(ARCH_MASK_*): New architecture masks for a specific processor.
(ARCH_FLAGS_*): New architecture masks for all of the architecture masks

[gcc(refs/users/meissner/heads/work173)] Move architecture flags from isa flags

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:5021a6c04765ed9f06013827155f7c65b9d785fe

commit 5021a6c04765ed9f06013827155f7c65b9d785fe
Author: Michael Meissner 
Date:   Tue Jul 23 10:11:54 2024 -0400

Move architecture flags from isa flags

2024-07-22  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Add
support for separating the architecture flags from the ISA flags.
(rs6000_cpu_cpp_builtins): Likewise.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture flags instead of isa flags.
(rs6000_clone_map): Likewise.
(rs6000_target_modify_macros_ptr): Update declaration.
(get_arch_flags): New function.
(rs6000_debug_reg_global): Add support for separating architecture
flags from the ISA flags.
(rs6000_print_isa_options):Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): Likewise.
(rs6000_pragma_target_parse): Likewise.
(rs6000_function_specific_save): Likewise.
(rs6000_function_specific_restore): Likewise.
(rs6000_function_specific_print): Likewise.
(rs6000_print_options_internal): Likewise.
(rs6000_print_isa_options): Likewise.
(rs6000_clone_priority): Switch to using architecture flags.
(rs6000_can_inline_p): Check if the arch flags match along with the 
isa
flags.
* config/rs6000/rs6000.h (enum arch_bits): New enumeration.
(ARCH_MASK_*): New architecture masks for a specific processor.
(ARCH_FLAGS_*): New architecture masks for all of the architecture 
masks
set for a specific processor.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New target save area.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc |  23 ++---
 gcc/config/rs6000/rs6000-protos.h |   5 +-
 gcc/config/rs6000/rs6000.cc   | 188 +-
 gcc/config/rs6000/rs6000.h|  36 
 gcc/config/rs6000/rs6000.opt  |   8 ++
 5 files changed, 205 insertions(+), 55 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 68519e1397f1..2ffaee165885 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -421,21 +422,21 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
   if ((flags & OPTION_MASK_MFCRF) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((flags & OPTION_MASK_POPCNTD) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_MASK_POWER8) != 0)
+  if ((arch_flags & ARCH_MASK_POWER8) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
-  if ((flags & OPTION_MASK_MODULO) != 0)
+  if ((arch_flags & ARCH_MASK_POWER9) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
-  if ((flags & OPTION_MASK_POWER10) != 0)
+  if ((arch_flags & ARCH_MASK_POWER10) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
-  if ((flags & OPTION_MASK_POWER11) != 0)
+  if ((arch_flags &