RE: [PATCH, ARM] Backport fix for PR59593 (minipool of small values on big endian targets)
> From: Ramana Radhakrishnan [mailto:ramana@googlemail.com]
> Sent: Tuesday, February 17, 2015 4:08 PM
> To: Thomas Preud'homme
> Cc: gcc-patches; Richard Earnshaw; Ramana Radhakrishnan; Marcus
> Shawcroft; Richard Biener; Jakub Jelinek
> Subject: Re: [PATCH, ARM] Backport fix for PR59593 (minipool of small
> values on big endian targets)
>
> On Tue, Jan 20, 2015 at 5:06 AM, Thomas Preud'homme
> wrote:
> > Currently on GCC 4.8 and 4.9, constant pool entries for QImode,
> HImode and SImode values are filled as 32-bit quantities. This works fine
> for little endian system but gives some incorrect results for big endian
> system when the value is accessed with a mode smaller than 32-bit in
> size. Suppose the case of the value 0x1234 that is accessed as an HImode
> value. It would be output as 0x0 0x0 0x12 0x34 in a constant pool entry
> and the 16-bit load that would be done would lead to the value 0x0 in
> register.
> >
> > This patch makes the consttable_1 and consttable_2 pattern available
> to ARM as well so that values are output according to their mode.
> >
> > This is a backport of commit r218118.
> >
> > *** gcc/ChangeLog ***
> >
> > 2015-01-14 Thomas Preud'homme
> >
> > Backport from mainline
> > 2014-11-27 Thomas Preud'homme
> >
> > PR target/59593
> > * config/arm/arm.c (dump_minipool): dispatch to consttable pattern
> > based on mode size.
> > * config/arm/arm.md (consttable_1): Make it TARGET_EITHER.
> > (consttable_2): Make it TARGET_EITHER and move HFmode handling
> from
> > consttable_4 to it.
> > (consttable_4): Move HFmode handling to consttable_2 pattern.
> >
> >
> > *** gcc/testsuite/ChangeLog ***
> >
> > 2015-01-14 Thomas Preud'homme
> >
> > Backport from mainline
> > 2014-11-27 Thomas Preud'homme
> >
> > PR target/59593
> > * gcc.target/arm/constant-pool.c: New test.
> >
> >
> > diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> > index 85372e5..eeaece8 100644
> > --- a/gcc/ChangeLog
> > +++ b/gcc/ChangeLog
> > @@ -1,3 +1,16 @@
> > +2015-01-14 Thomas Preud'homme
>
> > +
> > + Backport from mainline
> > + 2014-11-27 Thomas Preud'homme
>
> > +
> > + PR target/59593
> > + * config/arm/arm.c (dump_minipool): dispatch to consttable
> pattern
> > + based on mode size.
> > + * config/arm/arm.md (consttable_1): Make it TARGET_EITHER.
> > + (consttable_2): Make it TARGET_EITHER and move HFmode
> handling from
> > + consttable_4 to it.
> > + (consttable_4): Move HFmode handling to consttable_2 pattern.
> > +
> > 2015-01-14 Marek Polacek
> >
> > Backport from mainline
> > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> > index 5e2571c..67ef80b 100644
> > --- a/gcc/config/arm/arm.c
> > +++ b/gcc/config/arm/arm.c
> > @@ -16274,7 +16274,7 @@ dump_minipool (rtx scan)
> > fputc ('\n', dump_file);
> > }
> >
> > - switch (mp->fix_size)
> > + switch (GET_MODE_SIZE (mp->mode))
> > {
> > #ifdef HAVE_consttable_1
> > case 1:
> > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
> > index 8119387..93b25e9 100644
> > --- a/gcc/config/arm/arm.md
> > +++ b/gcc/config/arm/arm.md
> > @@ -12224,7 +12224,7 @@
> >
> > (define_insn "consttable_1"
> >[(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_1)]
> > - "TARGET_THUMB1"
> > + "TARGET_EITHER"
> >"*
> >making_const_table = TRUE;
> >assemble_integer (operands[0], 1, BITS_PER_WORD, 1);
> > @@ -12237,14 +12237,23 @@
> >
> > (define_insn "consttable_2"
> >[(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_2)]
> > - "TARGET_THUMB1"
> > + "TARGET_EITHER"
> >"*
> > - making_const_table = TRUE;
> > - gcc_assert (GET_MODE_CLASS (GET_MODE (operands[0])) !=
> MODE_FLOAT);
> > - assemble_integer (operands[0], 2, BITS_PER_WORD, 1);
> > - assemble_zeros (2);
> > - return \"\";
> > - "
> > + {
> > +rtx x = operands[0];
> > +making_const_table = TRUE;
> > +switch (GET_MODE_CLASS (GET_MODE (x)))
> > + {
> > + case MODE_FLOAT:
> > + arm_emit_fp16_const (x);
> > + break;
> > + default:
> > + assemble_integer (operands[0], 2, BITS_PER_WORD, 1);
> > + assemble_zeros (2);
> > + break;
> > + }
> > +return \"\";
> > + }"
> >[(set_attr "length" "4")
> > (set_attr "type" "no_insn")]
> > )
> > @@ -12259,15 +12268,12 @@
> > switch (GET_MODE_CLASS (GET_MODE (x)))
> >{
> >case MODE_FLOAT:
> > - if (GET_MODE (x) == HFmode)
> > - arm_emit_fp16_const (x);
> > - else
> > - {
> > - REAL_VALUE_TYPE r;
> > - REAL_VALUE_FROM_CONST_DOUBLE (r, x);
> > - assemble_real (r, GET_MODE (x), BITS_PER_WORD);
> > - }
> > - break;
> > + {
> > + REAL_VALUE_TYPE r;
> > + REAL_VALUE_FROM_CONST_DOUBLE (r, x);
> > + assemble_real (r, GET_MODE (x), BITS_PER_WORD);
Re: [patch/committed] PR middle-end/65233 make walk-ssa_copies handle empty PHIs
On 03/02/15 01:38, Richard Biener wrote: On Mon, Mar 2, 2015 at 6:34 AM, Aldy Hernandez wrote: As I mention in the PR... What's happening here is that the ipa_polymorphic_call_context constructor is calling walk_ssa_copies on a PHI node that has no arguments. This happens because finalize_jump_threads eventually removes some PHI arguments as it's redirecting some edges, leaving a PHI with no arguments: SR.33_23 = PHI <> This should get cleaned up later, but the IPA polymorphic code gets called during the actual CFG clean-up, and walk_ssa_copies cannot handle an empty PHI. Approved by Honza. Fully tested on x86-64 Linux and verified that the patch fixes the ICE on an x86-64 Linux cross aarch64-linux-gnu cc1plus. Committed to mainline. I think the real issue is that the walking code is executed via fold_stmt when called with an API that tells you not to walk SSA use-def chains. ? We have something that tells us not to walk the chains? I don't see it in an API for fold_stmt. How is the ipa-polymorphic code supposed to know when it can't follow the chains? The restrictions on what we can do while we're in the inconsistent state prior to updating the ssa graph aren't defined anywhere and I doubt anyone really knows what they are. That's obviously concerning. We might consider trying to narrow the window in which these inconsistencies are allowed. To do that I think we need to split cfgcleanup into two distinct parts. First is unreachable block removal (which is needed so that we can compute the dominators). Second is everything else. The order of operations would be something like remove unreachable blocks ssa graph update rest of cfg_cleanup That just feels too intrusive to try at this stage though. jeff
Fix ICE on thunks in tree-sra
Hi,
fix for comdat sections I am going to send incrementally triggers bug in
tree-sra that is trying to access a non-existing call statement in thunk.
While theoretically tree-sra can handle thunks - simply turn them into
wrappers when doing the transformation, I just hardened a check to disable
it on all functions with thunks.
Bootstrapped/regtested x86_64-linux. Comitted.
Honza
* tree-sra.c (convert_callers): Use call_for_symbol_and_aliases.
(struct ipa_sra_check_caller_data): Add has_thunk field.
(ipa_sra_check_caller): Check for thunk.
(ipa_sra_preliminary_function_checks): Give up on function with
thunks.
(ipa_early_sra): Use call_for_symbol_and_aliases.
Index: tree-sra.c
===
--- tree-sra.c (revision 221155)
+++ tree-sra.c (working copy)
@@ -4947,8 +4947,8 @@ convert_callers (struct cgraph_node *nod
{
basic_block this_block;
- node->call_for_symbol_thunks_and_aliases (convert_callers_for_node,
- &adjustments, false);
+ node->call_for_symbol_and_aliases (convert_callers_for_node,
+&adjustments, false);
if (!encountered_recursive_call)
return;
@@ -5016,6 +5016,7 @@ struct ipa_sra_check_caller_data
{
bool has_callers;
bool bad_arg_alignment;
+ bool has_thunk;
};
/* If NODE has a caller, mark that fact in DATA which is pointer to
@@ -5035,6 +5036,11 @@ ipa_sra_check_caller (struct cgraph_node
for (cgraph_edge *cs = node->callers; cs; cs = cs->next_caller)
{
+ if (cs->caller->thunk.thunk_p)
+ {
+ iscc->has_thunk = true;
+ return true;
+ }
gimple call_stmt = cs->call_stmt;
unsigned count = gimple_call_num_args (call_stmt);
for (unsigned i = 0; i < count; i++)
@@ -5131,7 +5137,7 @@ ipa_sra_preliminary_function_checks (str
struct ipa_sra_check_caller_data iscc;
memset (&iscc, 0, sizeof(iscc));
- node->call_for_symbol_thunks_and_aliases (ipa_sra_check_caller, &iscc, true);
+ node->call_for_symbol_and_aliases (ipa_sra_check_caller, &iscc, true);
if (!iscc.has_callers)
{
if (dump_file)
@@ -5148,6 +5154,14 @@ ipa_sra_preliminary_function_checks (str
return false;
}
+ if (iscc.has_thunk)
+{
+ if (dump_file)
+ fprintf (dump_file,
+"A has thunk.\n");
+ return false;
+}
+
return true;
}
@@ -5173,7 +5187,7 @@ ipa_early_sra (void)
goto simple_out;
}
- if (node->call_for_symbol_thunks_and_aliases
+ if (node->call_for_symbol_and_aliases
(some_callers_have_mismatched_arguments_p, NULL, true))
{
if (dump_file)
@@ -5182,7 +5196,7 @@ ipa_early_sra (void)
goto simple_out;
}
- if (node->call_for_symbol_thunks_and_aliases
+ if (node->call_for_symbol_and_aliases
(some_callers_have_no_vuse_p, NULL, true))
{
if (dump_file)
Re: [PATCH] PR target/65248: [5 Regression] Copy relocation in PIE against protected symbol
On Tue, Mar 03, 2015 at 06:20:05AM -0800, H.J. Lu wrote: > For x86-64, protected data symbols are impossible. Impossible? This is not even true currently since -fPIC emits code that looks like it would fully support protected visibiliy variables in shared libraries. If you meant to say it is impossible with non-PIC, then even that statement is going too far. All you'd need to do is have GNU ld emit dynamic text relocations and possibly add some reloc support to ld.so, and you'd have support so long as shared libraries loaded within 2G of the executable. A little horrible, but quite possible. With some more work, GNU ld could edit the current code sequences emitted by gcc for non-PIC, to a branch to a patch area where you use a PIC code sequence. See also Cary's suggestion at https://groups.google.com/forum/#!msg/generic-abi/9JX9vdstoVA/g4UGTmRdXJcJ Or you could just acknowledge that non-PIC has limitations. Another similar one (same root cause of no GOT indirection) is with weak symbols, where extern int foo () __attribute__ ((weak)); if (foo) foo (); just doesn't work for foo in a shared library. The non-PIC "if (foo)" effectively becomes either "if (0)" or "if (1)" at link time, unless you emit dynamic text relocations or edit the code. -- Alan Modra Australia Development Lab, IBM
Re: [PATCH][ARM]Automatically add -mthumb for thumb-only target when mode isn't specified
On Wed, Mar 4, 2015 at 10:44 AM, Terry Guo wrote:
> On Mon, Mar 2, 2015 at 9:08 PM, Maxim Kuvyrkov
> wrote:
>>> On Mar 2, 2015, at 4:44 AM, Terry Guo wrote:
>>>
>>> Hi there,
>>>
>>> If target mode isn't specified via either gcc configuration option
>>> --with-mode or command line, this patch intends to improve gcc driver to
>>> automatically add option -mthumb for thumb-only target. Tested with gcc
>>> regression test for various arm targets, no regression. Is it OK?
>>>
>>> BR,
>>> Terry
>>>
>>> gcc/ChangeLog:
>>>
>>> 2015-03-02 Terry Guo
>>>
>>>* common/config/arm/arm-common.c (arm_is_target_thumb_only): New
>>> function.
>>>* config/arm/arm-protos.h (FL_ Macros): Move to ...
>>>* config/arm/arm-opts.h (FL_ Macros): ... here.
>>>(struct arm_arch_core_flag): New struct.
>>>(arm_arch_core_flags): New array for arch/core and flag map.
>>>* config/arm/arm.h (MODE_SET_SPEC_FUNCTIONS): Define new SPEC
>>> function.
>>>(EXTRA_SPEC_FUNCTIONS): Include new SPEC function.
>>>(MODE_SET_SPECS): New SPEC.
>>>(DRIVER_SELF_SPECS): Include new SPEC.
>>
>> Did you consider approach of implementing this purely inside cc1 rather than
>> driver?
>>
>> We do not seem to need to pass -mthumb to assembler or linker since those
>> will pick up ARM-ness / Thumb-ness from function annotations. Therefore we
>> need to handle -marm / -mthumb for cc1 only. What am I missing?
>>
>> Also, what's the significance of moving FL_* flags to arm-opts.h? If you
>> had to separate FL_* definitions from the rest of arm-protos.h, then a new
>> dedicated file (e.g., arm-fl.h) would be a better choice for new home of
>> FL_* definitions.
>>
>
> Please find my answers in another email. The attached patch tries to
> follow your idea that puts those FL_* into separate file named
> arm-flags.h. Does it look good to you?
>
> BR,
> Terry
Sorry for missing patch.
diff --git a/gcc/common/config/arm/arm-common.c
b/gcc/common/config/arm/arm-common.c
index 86673b7..e17ee03 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -97,6 +97,28 @@ arm_rewrite_mcpu (int argc, const char **argv)
return arm_rewrite_selected_cpu (argv[argc - 1]);
}
+/* Called by driver to check whether the target denoted by current
+ command line options is thumb-only target. If -march present,
+ check the last -march option. If no -march, check the last -mcpu
+ option. */
+const char *
+arm_is_target_thumb_only (int argc, const char **argv)
+{
+ unsigned int opt;
+
+ if (argc)
+{
+ for (opt = 0; opt < (ARRAY_SIZE (arm_arch_core_flags) - 1); opt++)
+ if ((strcmp (argv[argc - 1], arm_arch_core_flags[opt].name) == 0)
+ && ((arm_arch_core_flags[opt].flags & FL_NOTM) == 0))
+ return "-mthumb";
+
+ return NULL;
+}
+ else
+return NULL;
+}
+
#undef ARM_CPU_NAME_LENGTH
diff --git a/gcc/config/arm/arm-flags.h b/gcc/config/arm/arm-flags.h
new file mode 100644
index 000..fe3a723
--- /dev/null
+++ b/gcc/config/arm/arm-flags.h
@@ -0,0 +1,92 @@
+/* Flags used to identify the presence of processor capabilities.
+
+ Copyright (C) 2015 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+
Re: Strengthen ICF hash
03.03.2015 10:25, Jan Hubicka writes:
>>>
>>> The hash itself is quite simple (borrowing incremental hash for constants
>>> adding
>>> very simple match for other stuff + logic to skip things that may match
>>> even if
>>> they are syntactticaly different). The hash can be strenghtened
>>> significantly,
>>> but I suppose we may do it based on actual profiling. It also is loosely
>>> based
>>> on varasm.c constant pool hash implementation that was OK for years.
>>
>> FWIW i have some older patches to use a stronger/faster spooky hash for
>> incremential hash. But I never submitted them because I wasn't able
>> to show clear gains for the type hashing (that was the original
>> motivator) since you fixed it.
>>
>> But if you're interested I can update them to the latest tree.
>> spooky is very good at dealing with a lot of input data quickly.
>
> You are my expert on modern hashing functions - my knowledge is very 1970's
> with some random insights of papers I read. I still think it may be
> interesting
> to get bit more up to date.
>
When I read your conversation, I recalled that one of my colleagues has
quite good experience in using and evaluating hash functions, so I asked
him for advice.
Yura gave me the link to his repo on github, it contains an
implementation of his own hash function (you are free to use it, it's in
public domain):
https://github.com/funny-falcon/funny_hash
Even if you are not interested in it (I understand that you are probably
looking for something well-known), this repo is worth looking at,
because it contains the benchmark of several popular hash functions.
Noticeably, they include "lookup3" (the function used in libiberty and
inchash.c is based on it's predecessor, "lookup2"), "Murmurhash" (which
is also used in GCC, in libstdc++-v3/libsupc++/hash_bytes.cc) and spooky
hash mentioned by Andi.
I also ran the benchmark on GCC trunk and a recent version of clang
(results are attached). If you are interested in more detailed studying
of hash functions, SMHasher
https://code.google.com/p/smhasher/wiki/SMHasher
is probably a good framework for their analysis and benchmarking.
> So I think main problem is not the actual strength of the incremental hash,
> but the fact that we do not hash enough.
>
> Whe following WIP patch makes situation bit better by properly hashing
> some type properties that are known to be stable and also moving some checkes
> from 4) to 2).
I have some idea. Unfortunately, I did not study the layout of GIMPLE
nodes in detail, so it might be useless... But suppose, that we can
extract the information which is relevant to ICF in the same way
gengtype extracts pointers for garbage collection. If the fields are
located close enough to each other, we could simply use bitwise "and"
with a constant mask to extract them. I.e. we use some tool to get the
fields of tree nodes which will be used when calculating the hash. At
compile time this tool will generate a lookup table (TREE_CODE will be
an index in it). Each element of the table can either contain a pair
(bitmask, length) - in this case we copy the tree node into temporary
buffer and do bitwise "and", or, perhaps, a list of (offset, length)
pairs, corresponding to some fields of the node (and possibly another
bit mask). In this case we copy the fields.
When we have enough data in the buffer, we perform hashing (that would
probably be faster than element-wise hashing, especially if we use SIMD).
Depending on how sparse the information inside tree nodes is, we could
fall back to something we already have:
> + else if (VECTOR_TYPE_P (type))
> +{
> + hstate.add_int (VECTOR_TYPE);
> + hstate.add_int (TYPE_PRECISION (type));
> + sem_item::add_type (TREE_TYPE (type), hstate);
> +}
> + else if (TREE_CODE (type) == ARRAY_TYPE)
> +{
> + hstate.add_int (ARRAY_TYPE);
> + sem_item::add_type (TREE_TYPE (type), hstate);
> + sem_item::add_expr (TYPE_SIZE (type), hstate);
> + hstate.add_int (POINTER_TYPE_P (type));
Note that this code can also be generated automatically, based on
gengtype-like annotations or, better, some separate description like
match.pd.
--
Regards,
Mikhail Maltsev
Exact options: "-O3 -march=native -mtune=native"
Run on: "Intel(R) Core(TM) i7-5820K CPU @ 3.30GHz"
We are probably more interested in "substrings" mode,
strictly speaking, it's not incremental, but deals with
small chunks of data, rather than 300 MiBs at once.
Siphash is perhaps not appropriate, because it's design heavily
relies on 64-bit architecture (it involves 64-bit rotations),
besides it's somewhat slower because it's designed to be
resistant against hash-flooding (i.e. collision attacks).
The result is time in seconds (i.e. lower is better)
x86_64
--
By 1-20 byte substrings twice
function | gcc -O3 | clang -O3
--|-|--
funny32 | 0.79 | 0.93
funny64 | 0.84 | 0.94
murmur32 | 0.91 | 0.95
murmur128 | 1.33 | 1.24
s
Re: [PATCH][ARM]Automatically add -mthumb for thumb-only target when mode isn't specified
On Mon, Mar 2, 2015 at 9:08 PM, Maxim Kuvyrkov wrote: >> On Mar 2, 2015, at 4:44 AM, Terry Guo wrote: >> >> Hi there, >> >> If target mode isn't specified via either gcc configuration option >> --with-mode or command line, this patch intends to improve gcc driver to >> automatically add option -mthumb for thumb-only target. Tested with gcc >> regression test for various arm targets, no regression. Is it OK? >> >> BR, >> Terry >> >> gcc/ChangeLog: >> >> 2015-03-02 Terry Guo >> >>* common/config/arm/arm-common.c (arm_is_target_thumb_only): New >> function. >>* config/arm/arm-protos.h (FL_ Macros): Move to ... >>* config/arm/arm-opts.h (FL_ Macros): ... here. >>(struct arm_arch_core_flag): New struct. >>(arm_arch_core_flags): New array for arch/core and flag map. >>* config/arm/arm.h (MODE_SET_SPEC_FUNCTIONS): Define new SPEC >> function. >>(EXTRA_SPEC_FUNCTIONS): Include new SPEC function. >>(MODE_SET_SPECS): New SPEC. >>(DRIVER_SELF_SPECS): Include new SPEC. > > Did you consider approach of implementing this purely inside cc1 rather than > driver? > > We do not seem to need to pass -mthumb to assembler or linker since those > will pick up ARM-ness / Thumb-ness from function annotations. Therefore we > need to handle -marm / -mthumb for cc1 only. What am I missing? > > Also, what's the significance of moving FL_* flags to arm-opts.h? If you had > to separate FL_* definitions from the rest of arm-protos.h, then a new > dedicated file (e.g., arm-fl.h) would be a better choice for new home of FL_* > definitions. > Please find my answers in another email. The attached patch tries to follow your idea that puts those FL_* into separate file named arm-flags.h. Does it look good to you? BR, Terry
RE: [PATCH, ARM] Fix PR64453: live high register not saved in function prolog with -Os
Done for backport to 4.8. Best regards, Thomas > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme > Sent: Tuesday, March 03, 2015 5:35 PM > To: Ramana Radhakrishnan > Cc: gcc-patches; Richard Biener; Jakub Jelinek > Subject: RE: [PATCH, ARM] Fix PR64453: live high register not saved in > function prolog with -Os > > Just committed to 4.9 branch, 4.8 to follow once regression testsuite for > 4.8 backport finishes running (backport was done quite some time ago > now). > > Best regards, > > Thomas > > > -Original Message- > > From: Ramana Radhakrishnan [mailto:ramana@googlemail.com] > > Sent: Tuesday, February 17, 2015 4:07 PM > > To: Thomas Preud'homme > > Cc: Ramana Radhakrishnan; gcc-patches; Richard Biener; Jakub Jelinek > > Subject: Re: [PATCH, ARM] Fix PR64453: live high register not saved in > > function prolog with -Os > > > > On Fri, Jan 23, 2015 at 8:23 AM, Thomas Preud'homme > > wrote: > > > Hi Ramana, > > > > > >> From: Ramana Radhakrishnan [mailto:ramana@googlemail.com] > > >> Sent: Wednesday, January 14, 2015 7:21 PM > > >> On Wed, Jan 14, 2015 at 10:20 AM, Thomas Preud'homme > > >> wrote: > > >> > When compiling for size, live high registers are not saved in > function > > >> prolog in ARM backend in Thumb mode. The problem comes from > > >> arm_conditional_register_usage setting call_used_regs for all high > > >> register to avoid them being allocated. However, this cause prolog > to > > not > > >> save these register even if they are used. This patch marks high > > registers > > >> as really needing to be saved in prolog if live, no matter what is the > > >> content of call_used_regs. > > >> > > > >> > ChangeLog entries are as follows: > > >> > > > >> > gcc/ChangeLog > > >> > > > >> > 2015-01-12 Thomas Preud'homme > thomas.preudho...@arm.com > > >> > > > >> > PR target/64453 > > >> > * config/arm/arm.c (callee_saved_reg_p): Define. > > >> > (arm_compute_save_reg0_reg12_mask): Use > > callee_saved_reg_p > > >> to check if > > >> > register is callee saved instead of !call_used_regs[reg]. > > >> > (thumb1_compute_save_reg_mask): Likewise. > > >> > > > >> > > > >> > gcc/testsuite/ChangeLog > > >> > > > >> > 2014-12-31 Thomas Preud'homme > thomas.preudho...@arm.com > > >> > > > >> > * gcc.target/arm/pr64453.c: New. > > >> > > > >> > > > >> > > > >> > > >> OK. > > >> > > >> Ramana > > > > > > The patch applies cleanly on GCC 4.8 and 4.9 branches when omitting > > the cosmetic change > > > in arm_conditional_register_usage () which was unintended. I > > compiled an arm-none-eabi > > > GCC cross compiler and ran the testsuite for both backport without > any > > regression. > > > > > > Is this ok for the 4.8 and 4.9 branches? > > > > > > > OK for the branches if no RM objects in 24 hours. > > > > Ramana > > > > > Best regards, > > > > > > Thomas > > > > > > > > > > > > >
[PATCH] target/65286 - Disable multilib for ppc64le
The attached patch resolves PR 65286 by adding --disable-multilib
when configuring for a ppc64le target.
Martin
diff --git a/ChangeLog b/ChangeLog
index bd43281..46ec13d 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2015-03-03 Martin Sebor
+
+ PR target/65286
+ * configure.ac (powerpc64le-*): Disable multilib.
+ * configure: Regenerate.
+
2015-03-13 Jeff Law
* MAINTAINERS: Remove Paul Brook as a Fortran and ARM
diff --git a/configure b/configure
index 9de7295..168bf4c 100755
--- a/configure
+++ b/configure
@@ -7378,6 +7378,15 @@ if test x${is_cross_compiler} = xyes ; then
target_configargs="--with-cross-host=${host_noncanonical} ${target_configargs}"
fi
+# There is no multilib support on ppc64le. Disable it unless it's
+# explicitly enabled.
+case "$target:$have_compiler:$enable_multilib" in
+ powerpc64le-*:yes:)
+target_configargs="--disable-multilib ${target_configargs}"
+enable_multilib=no
+;;
+esac
+
# Special user-friendly check for native x86_64-linux build, if
# multilib is not explicitly enabled.
case "$target:$have_compiler:$host:$target:$enable_multilib" in
diff --git a/configure.ac b/configure.ac
index 00f7452..5ad3211 100644
--- a/configure.ac
+++ b/configure.ac
@@ -3021,6 +3021,15 @@ if test x${is_cross_compiler} = xyes ; then
target_configargs="--with-cross-host=${host_noncanonical} ${target_configargs}"
fi
+# There is no multilib support on ppc64le. Disable it unless it's
+# explicitly enabled.
+case "$target:$have_compiler:$enable_multilib" in
+ powerpc64le-*:yes:)
+target_configargs="--disable-multilib ${target_configargs}"
+enable_multilib=no
+;;
+esac
+
# Special user-friendly check for native x86_64-linux build, if
# multilib is not explicitly enabled.
case "$target:$have_compiler:$host:$target:$enable_multilib" in
[patch committed SH] Fix PR target/65249
The attached patches are to fix PR target/65249 which is a 4.9/5
regression. It avoids yet another R0_REGS spill failure with
pre-allocating R0 reg in symGOT_load when the loading symbol is
__stack_chk_guard. Although the problem went away with -mlra
and LRA would be the real fix for this issue, SH is still in
transition to LRA and we have no chance for 4.9.
Tested with sh4-unknown-linux-gnu on trunk and 4.9 branch.
Committed on trunk and 4.9.
Regards,
kaz
--
2015-03-03 Kaz Kojima
PR target/65249
* config/sh/sh.md (symGOT_load): Use R0 reg for operands[2] when
called for __stack_chk_guard symbol.
[trunk/gcc]
diff --git a/config/sh/sh.md b/config/sh/sh.md
index 2435ec9..24ddc9e 100644
--- a/config/sh/sh.md
+++ b/config/sh/sh.md
@@ -10690,10 +10690,26 @@ label:
""
{
rtx mem;
+ bool stack_chk_guard_p = false;
operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ if (!TARGET_SHMEDIA
+ && flag_stack_protect
+ && GET_CODE (operands[1]) == CONST
+ && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
+ && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
+ && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
+"__stack_chk_guard") == 0)
+stack_chk_guard_p = true;
+
+ /* Use R0 to avoid long R0 liveness which stack-protector tends to
+ produce. */
+ if (! sh_lra_flag
+ && stack_chk_guard_p && ! reload_in_progress && ! reload_completed)
+operands[2] = gen_rtx_REG (Pmode, R0_REG);
+
if (TARGET_SHMEDIA)
{
rtx reg = operands[2];
@@ -10721,13 +10737,7 @@ label:
insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
when rX is a GOT address for the guard symbol. Ugly but doesn't
matter because this is a rare situation. */
- if (!TARGET_SHMEDIA
- && flag_stack_protect
- && GET_CODE (operands[1]) == CONST
- && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
- && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
- && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
-"__stack_chk_guard") == 0)
+ if (stack_chk_guard_p)
emit_insn (gen_chk_guard_add (operands[3], operands[2]));
else
emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
[gcc-4_9-branch/gcc]
diff --git a/config/sh/sh.md b/config/sh/sh.md
index 00bbf3e..f75f5a2 100644
--- a/config/sh/sh.md
+++ b/config/sh/sh.md
@@ -10164,10 +10164,25 @@ label:
""
{
rtx mem;
+ bool stack_chk_guard_p = false;
operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ if (!TARGET_SHMEDIA
+ && flag_stack_protect
+ && GET_CODE (operands[1]) == CONST
+ && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
+ && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
+ && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
+"__stack_chk_guard") == 0)
+stack_chk_guard_p = true;
+
+ /* Use R0 to avoid long R0 liveness which stack-protector tends to
+ produce. */
+ if (stack_chk_guard_p && ! reload_in_progress && ! reload_completed)
+operands[2] = gen_rtx_REG (Pmode, R0_REG);
+
if (TARGET_SHMEDIA)
{
rtx reg = operands[2];
@@ -10195,13 +10210,7 @@ label:
insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
when rX is a GOT address for the guard symbol. Ugly but doesn't
matter because this is a rare situation. */
- if (!TARGET_SHMEDIA
- && flag_stack_protect
- && GET_CODE (operands[1]) == CONST
- && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
- && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
- && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
-"__stack_chk_guard") == 0)
+ if (stack_chk_guard_p)
emit_insn (gen_chk_guard_add (operands[3], operands[2]));
else
emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
[rl78] more far addr edge cases
More edge cases regarding far addresses. Committed.
* config/rl78/rl78-real.md (*addqi_real): Allow SADDR types for
inc/dec.
(*addhi3_real): Likewise.
* config/rl78/rl78-virt.md (*inc3_virt): Additional
pattern to match incrementing memory.
* config/rl78/predicates.md (rl78_1_2_operand): New.
* config/rl78/rl78.c (rl78_force_nonfar_3): Allow far mem-mem if
it's the same and only mem.
(rl78_alloc_physical_registers_op2): If there's effectively only
one MEM, transcode it into HL.
(rl78_far_p): Reject addresses that aren't legitimate.
Index: config/rl78/predicates.md
===
--- config/rl78/predicates.md (revision 221163)
+++ config/rl78/predicates.md (working copy)
@@ -58,6 +58,21 @@
(and (match_code "const_int")
(match_test "IN_RANGE (INTVAL (op), 0, 255)")))
+(define_predicate "rl78_incdec_memory_operand"
+ (and (match_code "mem")
+ (match_test "rl78_far_p (op)
+|| satisfies_constraint_Wsa (op)
+|| satisfies_constraint_Whl (op)
+|| satisfies_constraint_Wh1 (op)
+|| satisfies_constraint_Wab (op)")
+ )
+)
+
+(define_predicate "rl78_1_2_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), 1, 2)
+ || IN_RANGE (INTVAL (op), -2, -1)")))
+
(define_predicate "rl78_24_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) == 2 || INTVAL (op) == 4")))
Index: config/rl78/rl78-real.md
===
--- config/rl78/rl78-real.md(revision 221163)
+++ config/rl78/rl78-real.md(working copy)
@@ -113,14 +113,14 @@
;;-- Arithmetic
(define_insn "*addqi3_real"
- [(set (match_operand:QI 0 "rl78_nonimmediate_operand"
"=rvWabWhlWh1,rvWabWhlWh1,a,*bcdehl,Wsa")
+ [(set (match_operand:QI 0 "rl78_nonimmediate_operand"
"=rvWabWhlWh1Wsa,rvWabWhlWh1Wsa,a,*bcdehl,Wsa")
(plus:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0,0,0")
(match_operand:QI 2 "rl78_general_operand"
"K,L,RWhlWh1Wabi,a,i")))
]
"rl78_real_insns_ok ()"
"@
-inc\t%0
-dec\t%0
+inc\t%p0
+dec\t%p0
add\t%0, %2
add\t%0, %2
add\t%0, %2"
@@ -128,7 +128,7 @@
)
(define_insn "*addhi3_real"
- [(set (match_operand:HI 0 "rl78_nonimmediate_operand"
"=vABDTWh1Wab,vABDTWh1Wab,v,v,A,S,S,A")
+ [(set (match_operand:HI 0 "rl78_nonimmediate_operand"
"=vABDTWhlWh1WabWsa,vABDTWhlWh1WabWsa,v,v,A,S,S,A")
(plus:HI (match_operand:HI 1 "rl78_general_operand" "%0,0,0,0,0,0,0,S")
(match_operand:HI 2 "" "K,L,N,O,RWh1WhlWabiv,Int8Qs8,J,Ri")))
]
Index: config/rl78/rl78-virt.md
===
--- config/rl78/rl78-virt.md(revision 221163)
+++ config/rl78/rl78-virt.md(working copy)
@@ -85,6 +85,15 @@
;;-- Arithmetic
+(define_insn "*inc3_virt"
+ [(set (match_operand:QHI 0 "rl78_incdec_memory_operand" "=vm")
+ (plus:QHI (match_operand:QHI 1 "rl78_incdec_memory_operand" "0")
+ (match_operand:QHI 2 "rl78_1_2_operand" "KLNO")))
+ ]
+ "rl78_virt_insns_ok ()"
+ "v.inc\t%0, %1, %2"
+)
+
(define_insn "*add3_virt"
[(set (match_operand:QHI 0 "rl78_nonfar_nonimm_operand" "=vY,S")
(plus:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "viY,0")
Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c (revision 221163)
+++ config/rl78/rl78.c (working copy)
@@ -579,6 +579,13 @@
int did = 0;
rtx temp_reg = NULL;
+ /* As an exception, we allow two far operands if they're identical
+ and the third operand is not a MEM. This allows global variables
+ to be incremented, for example. */
+ if (rtx_equal_p (operands[0], operands[1])
+ && ! MEM_P (operands[2]))
+return 0;
+
/* FIXME: Likewise. */
if (rl78_far_p (operands[1]))
{
@@ -970,6 +977,12 @@
fprintf (stderr, "\033[35mrl78_far_p: "); debug_rtx (x);
fprintf (stderr, " = %d\033[0m\n", MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR);
#endif
+
+ /* Not all far addresses are legitimate, because the devirtualizer
+ can't handle them. */
+ if (! rl78_as_legitimate_address (GET_MODE (x), XEXP (x, 0), false,
ADDR_SPACE_FAR))
+return 0;
+
return GET_MODE_BITSIZE (rl78_addr_space_address_mode (MEM_ADDR_SPACE (x)))
== 32;
}
@@ -3007,9 +3020,18 @@
if (rtx_equal_p (OP (0), OP (1)))
{
- OP (0) =
- OP (1) = transcode_memory_rtx (OP (1), DE, insn);
- OP (2) = transcode_memory_rtx (OP (2), HL, insn);
+ if (MEM_P (OP (2)))
+ {
+ OP (0) =
+ OP (1) = transcode_memory_rtx (OP (1), DE, insn);
+ OP (2) = transcode_memory_rtx (OP (2), HL, insn);
+ }
+ else
+ {
+
[PATCH] PR 65138, Fix PowerPC little endian -flto bugs, GCC 4.9 backport
This is the backport of the fixes for PR 65138/target (not using --with-cpu
during configuration means that several lto tests fail on little endian 64-bit
PowerPC systems). I found in doing the patches, I also needed to apply the
changes on January 19th to properly set the TARGET_DEFAULT on 64-bit Linux
systems.
These patches passed bootstrap (for C/C++) and there were no tests that failed
due to the use of -flto. I'll check these patches in on January 4th, unless
there is an objection.
[branches/gcc-4_9-patch/gcc]
2015-03-03 Michael Meissner
Backport from trunk
2015-03-03 Michael Meissner
PR 65138/target
* config/rs6000/rs6000-cpus.def (powerpc64le): Add new generic
processor type for 64-bit little endian PowerPC.
* config/rs6000/rs6000.c (rs6000_option_override_internal): If
-mdebug=reg, print TARGET_DEFAULT. Fix logic to use
TARGET_DEFAULT if there is no default cpu. Fix -mdebug=reg
printing built-in mask so it does not pass NULL pointers.
* config/rs6000/rs6000-tables.opt: Regenerate.
* doc/invoke.texi (IBM RS/6000 and PowerPC options): Document
-mcpu=powerpc64le.
Backport from trunk
2015-01-19 David Edelsohn
* config/rs6000/default64.h: Include rs6000-cpus.def.
(TARGET_DEFAULT) [LITTLE_ENDIAN]: Use ISA 2.7 (POWER8).
(TARGET_DEFAULT) [BIG_ENDIAN]: Use POWER4.
* config/rs6000/driver-rs6000.c (detect_processor_aix): Add POWER7
and POWER8.
* config/rs6000/linux64.h (PROCESSOR_DEFAULT64): Always default to
POWER8.
* config/rs6000/rs6000.c (rs6000_file_start): Emit .machine
pseudo-op to specify assembler dialect.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000-tables.opt
===
--- gcc/config/rs6000/rs6000-tables.opt (revision 221158)
+++ gcc/config/rs6000/rs6000-tables.opt (working copy)
@@ -186,5 +186,8 @@ EnumValue
Enum(rs6000_cpu_opt_value) String(powerpc64) Value(52)
EnumValue
-Enum(rs6000_cpu_opt_value) String(rs64) Value(53)
+Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(53)
+
+EnumValue
+Enum(rs6000_cpu_opt_value) String(rs64) Value(54)
Index: gcc/config/rs6000/rs6000-cpus.def
===
--- gcc/config/rs6000/rs6000-cpus.def (revision 221158)
+++ gcc/config/rs6000/rs6000-cpus.def (working copy)
@@ -1,5 +1,5 @@
/* IBM RS/6000 CPU names..
- Copyright (C) 1991-2014 Free Software Foundation, Inc.
+ Copyright (C) 1991-2015 Free Software Foundation, Inc.
Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
This file is part of GCC.
@@ -189,4 +189,5 @@ RS6000_CPU ("power7", PROCESSOR_POWER7,
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 |
ISA_2_7_MASKS_SERVER)
RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
Index: gcc/config/rs6000/default64.h
===
--- gcc/config/rs6000/default64.h (revision 221158)
+++ gcc/config/rs6000/default64.h (working copy)
@@ -1,6 +1,6 @@
/* Definitions of target machine for GNU compiler,
for 64 bit powerpc linux defaulting to -m64.
- Copyright (C) 2003-2014 Free Software Foundation, Inc.
+ Copyright (C) 2003-2015 Free Software Foundation, Inc.
This file is part of GCC.
@@ -18,10 +18,14 @@ You should have received a copy of the G
along with GCC; see the file COPYING3. If not see
Re: [google/gcc-4_9] Minor changes to -ftwo-level-line-tables
ok for google branch.
Dehao
On Tue, Mar 3, 2015 at 12:26 PM, Cary Coutant wrote:
>>> @@ -21817,22 +21823,39 @@ out_subprog_directive (subprog_entry *su
>>> {
>>>tree decl = subprog->decl;
>>>tree decl_name = DECL_NAME (decl);
>>> - const char *name;
>>> + tree origin;
>>
>> Explicitly initialize origin to NULL_TREE;
>
> Done.
>
>>> + /* For inlined subroutines, use the linkage name.
>>> + If -ftwo-level-all-subprogs is set, use the linkage name
>>> + for all subroutines. */
>>> + if (subprog->is_inlined || flag_two_level_all_subprogs)
>>> {
>>> - name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
>>> - if (name[0] == '*')
>>> -name++;
>>> + if (DECL_ASSEMBLER_NAME (origin))
>>> + {
>>> + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (origin));
>>> + if (name[0] == '*')
>>> + name++;
>>> + }
>>> + else
>>> + name = dwarf2_name (origin, 0);
>>> }
>>>else
>>> -name = dwarf2_name (decl, 0);
>>> +{
>>> + /* To save space, we don't emit the name for non-inlined
>>> + subroutines, whose linkage names are available from the
>>> + object file's symbol table. */
>>
>> flag_two_level_all_subprogs will be 1 by default. This mean "else"
>> branch is not the default behavior?
>
> No, I changed the default in common.opt:
>
> ftwo-level-all-subprogs
> -Common Report Var(flag_two_level_all_subprogs) Init(1)
> +Common Report Var(flag_two_level_all_subprogs) Init(0)
> When generating two-level line tables in DWARF (experimental),
> -generate subprogram table entries for all functions.
> +add linkage names for all functions (not just inlined functions).
>
> -cary
Re: [google/gcc-4_9] Minor changes to -ftwo-level-line-tables
>> @@ -21817,22 +21823,39 @@ out_subprog_directive (subprog_entry *su
>> {
>>tree decl = subprog->decl;
>>tree decl_name = DECL_NAME (decl);
>> - const char *name;
>> + tree origin;
>
> Explicitly initialize origin to NULL_TREE;
Done.
>> + /* For inlined subroutines, use the linkage name.
>> + If -ftwo-level-all-subprogs is set, use the linkage name
>> + for all subroutines. */
>> + if (subprog->is_inlined || flag_two_level_all_subprogs)
>> {
>> - name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
>> - if (name[0] == '*')
>> -name++;
>> + if (DECL_ASSEMBLER_NAME (origin))
>> + {
>> + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (origin));
>> + if (name[0] == '*')
>> + name++;
>> + }
>> + else
>> + name = dwarf2_name (origin, 0);
>> }
>>else
>> -name = dwarf2_name (decl, 0);
>> +{
>> + /* To save space, we don't emit the name for non-inlined
>> + subroutines, whose linkage names are available from the
>> + object file's symbol table. */
>
> flag_two_level_all_subprogs will be 1 by default. This mean "else"
> branch is not the default behavior?
No, I changed the default in common.opt:
ftwo-level-all-subprogs
-Common Report Var(flag_two_level_all_subprogs) Init(1)
+Common Report Var(flag_two_level_all_subprogs) Init(0)
When generating two-level line tables in DWARF (experimental),
-generate subprogram table entries for all functions.
+add linkage names for all functions (not just inlined functions).
-cary
Re: [patch/committed] PR middle-end/65233 make walk-ssa_copies handle empty PHIs
> On Mon, Mar 2, 2015 at 6:34 AM, Aldy Hernandez wrote: > > As I mention in the PR... > > > > What's happening here is that the ipa_polymorphic_call_context constructor > > is calling walk_ssa_copies on a PHI node that has no arguments. This > > happens because finalize_jump_threads eventually removes some PHI arguments > > as it's redirecting some edges, leaving a PHI with no arguments: > > > > SR.33_23 = PHI <> > > > > This should get cleaned up later, but the IPA polymorphic code gets called > > during the actual CFG clean-up, and walk_ssa_copies cannot handle an empty > > PHI. > > > > Approved by Honza. > > > > Fully tested on x86-64 Linux and verified that the patch fixes the ICE on an > > x86-64 Linux cross aarch64-linux-gnu cc1plus. > > > > Committed to mainline. > > I think the real issue is that the walking code is executed via fold_stmt when > called with an API that tells you not to walk SSA use-def chains. OK, adding arugment to ipa_polymorphic_call_context disabling use-def walks on request is easy. How does one say what uses of fold_stmt are not supposed to walk use-def chains? Honza
New German PO file for 'gcc' (version 5.1-b20150208)
Hello, gentle maintainer. This is a message from the Translation Project robot. A revised PO file for textual domain 'gcc' has been submitted by the German team of translators. The file is available at: http://translationproject.org/latest/gcc/de.po (This file, 'gcc-5.1-b20150208.de.po', has just now been sent to you in a separate email.) All other PO files for your package are available in: http://translationproject.org/latest/gcc/ Please consider including all of these in your next release, whether official or a pretest. Whenever you have a new distribution with a new version number ready, containing a newer POT file, please send the URL of that distribution tarball to the address below. The tarball may be just a pretest or a snapshot, it does not even have to compile. It is just used by the translators when they need some extra translation context. The following HTML page has been updated: http://translationproject.org/domain/gcc.html If any question arises, please contact the translation coordinator. Thank you for all your work, The Translation Project robot, in the name of your translation coordinator.
Re: ipa-icf::merge TLC
> > Hi, > > > > I built with r221117. I see errors while building following targets: > > aarch64_be-none-linux-gnu, aarch64_be-none-linux-gnu, > > arm-none-linux-gnueabihf, arm-none-linux-gnueabi. > > Indeed, it's broken again since r221099. Accidentally I reverted the var->alias check (probably while merging patches from mainline). It should be fixed again now by: 2015-03-03 Martin Liska PR ipa/65287 * ipa-icf.c (sem_variable::parse): Skip all alias variables. Sorry for that. Honza
Re: RFA: RL78: Add muladdhi3 pattern
> The problem appears to be that GCC will create a multiply-plus-add
> instruction to access the table regardless of whether the backend
> supports such an instruction. I could not work out where in the
> middle end this was occurring, so instead I created the patch below
> which contains a splitter to separate out the multiply and addition
> operations.
I've seen this before. The root of the problem is in
expand_expr_real_1() where convert_to_mode() is called (around line
10262 in my tree) to change the address's mode from HImode to SImode,
but this happens *before* the address itself is legitimized (I think).
So we have an invalid address causing the problem, at a point were we
don't care if the address is valid or not.
Either the address must be legitimized before that point, or some
other conversion needs to be used. Either way, I think adding a
pattern for this particular address is only hiding the problem, not
fixing it.
if (offset)
{
machine_mode address_mode;
rtx offset_rtx = expand_expr (offset, NULL_RTX, VOIDmode,
EXPAND_SUM);
gcc_assert (MEM_P (op0));
address_mode = get_address_mode (op0);
if (GET_MODE (offset_rtx) != address_mode)
--> offset_rtx = convert_to_mode (address_mode, offset_rtx, 0);
Re: [google/gcc-4_9] Minor changes to -ftwo-level-line-tables
On Tue, Mar 3, 2015 at 11:25 AM, Cary Coutant wrote:
> This patch is for the google/gcc-4_9 branch.
>
> With this patch, we output an empty name for non-inlined functions,
> and change the -ftwo-level-all-subprogs option to override this
> behavior to output linkage names instead. The consumer can obtain
> the linkage name for non-inlined functions from the ELF symbol table,
> so we can save quite a bit of space in the line tables by omitting
> those names.
>
> This patch also fixes a case where we output the linkage name for
> a clone rather than for the ultimate origin.
>
> OK for google/gcc-4_9?
>
> -cary
>
>
> 2015-03-03 Cary Coutant
>
> * common.opt (ftwo-level-all-subprogs): Default to off;
> update help text.
> * dwarf2out.c (add_subprog_entry): Clear subprog_num if the
> subprogram is inlined, but was already output as non-inlined.
> (out_subprog_directive): Get name from decl_ultimate_origin.
> Output empty name for non-inlined subprograms.
> (out_logical_entry): Output subprog entries for all subprograms.
>
> Index: common.opt
> ===
> --- common.opt (revision 221069)
> +++ common.opt (working copy)
> @@ -1214,9 +1214,9 @@ Common Report Var(flag_dwarf2_cfi_asm) I
> Enable CFI tables via GAS assembler directives.
>
> ftwo-level-all-subprogs
> -Common Report Var(flag_two_level_all_subprogs) Init(1)
> +Common Report Var(flag_two_level_all_subprogs) Init(0)
> When generating two-level line tables in DWARF (experimental),
> -generate subprogram table entries for all functions.
> +add linkage names for all functions (not just inlined functions).
>
> ftwo-level-line-tables
> Common Report Var(flag_two_level_line_tables) Init(0)
> Index: dwarf2out.c
> ===
> --- dwarf2out.c (revision 221069)
> +++ dwarf2out.c (working copy)
> @@ -21506,8 +21506,14 @@ add_subprog_entry (tree decl, bool is_in
>entry->subprog_num = 0;
>*slot = entry;
> }
> - else if (is_inlined)
> -(*slot)->is_inlined = true;
> + else if (is_inlined && !(*slot)->is_inlined)
> +{
> + /* If we've already output this subprogram entry as a non-inlined
> + subprogram, make sure it gets output again, so that we include
> + its linkage name. */
> + (*slot)->is_inlined = true;
> + (*slot)->subprog_num = 0;
> +}
>return *slot;
> }
>
> @@ -21817,22 +21823,39 @@ out_subprog_directive (subprog_entry *su
> {
>tree decl = subprog->decl;
>tree decl_name = DECL_NAME (decl);
> - const char *name;
> + tree origin;
Explicitly initialize origin to NULL_TREE;
> + const char *name = NULL;
>unsigned int file_num = 0;
>unsigned int line_num = 0;
>
>if (decl_name == NULL || IDENTIFIER_POINTER (decl_name) == NULL)
> return;
>
> - /* For inlined subroutines, use the linkage name. */
> - if (subprog->is_inlined && DECL_ASSEMBLER_NAME (decl))
> + origin = decl_ultimate_origin (decl);
> + if (origin == NULL_TREE)
> +origin = decl;
> +
> + /* For inlined subroutines, use the linkage name.
> + If -ftwo-level-all-subprogs is set, use the linkage name
> + for all subroutines. */
> + if (subprog->is_inlined || flag_two_level_all_subprogs)
> {
> - name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
> - if (name[0] == '*')
> -name++;
> + if (DECL_ASSEMBLER_NAME (origin))
> + {
> + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (origin));
> + if (name[0] == '*')
> + name++;
> + }
> + else
> + name = dwarf2_name (origin, 0);
> }
>else
> -name = dwarf2_name (decl, 0);
> +{
> + /* To save space, we don't emit the name for non-inlined
> + subroutines, whose linkage names are available from the
> + object file's symbol table. */
flag_two_level_all_subprogs will be 1 by default. This mean "else"
branch is not the default behavior?
Dehao
> + name = "";
> +}
>
>if (LOCATION_LOCUS (DECL_SOURCE_LOCATION (decl)) != UNKNOWN_LOCATION)
> {
> @@ -21881,8 +21904,7 @@ out_logical_entry (dw_line_info_table *t
>/* Declare the subprogram if it hasn't already been declared. */
>if (block != NULL)
> subprog = block->subprog;
> - if (subprog != NULL && subprog->subprog_num == 0
> - && (context != NULL || flag_two_level_all_subprogs))
> + if (subprog != NULL && subprog->subprog_num == 0)
> out_subprog_directive (subprog);
>if (subprog != NULL)
> subprog_num = subprog->subprog_num;
Re: RFA: RL78: Fix register constraints in rl78-real.md
> OK to apply ? Ok.
RE: [PATCH][AArch64] Make aarch64_min_divisions_for_recip_mul configurable
> Andrew Pinski wrote: > On Tue, Mar 3, 2015 at 10:06 AM, Wilco Dijkstra wrote: > > This patch makes aarch64_min_divisions_for_recip_mul configurable for float > > and double. This > allows > > CPUs with really fast or multiple dividers to return 3 (or even 4) if that > > happens to be > faster > > overall. No code generation change - bootstrap & regression OK. > > Are you planing on doing the optimization where you turn the divide > into recip est followed by a few steps? > Because if so then this should be changed to be handle that case too. No I don't think that will be faster. Wilco
Re: [PATCH][AArch64] Make aarch64_min_divisions_for_recip_mul configurable
On Tue, Mar 3, 2015 at 10:06 AM, Wilco Dijkstra wrote:
> This patch makes aarch64_min_divisions_for_recip_mul configurable for float
> and double. This allows
> CPUs with really fast or multiple dividers to return 3 (or even 4) if that
> happens to be faster
> overall. No code generation change - bootstrap & regression OK.
Are you planing on doing the optimization where you turn the divide
into recip est followed by a few steps?
Because if so then this should be changed to be handle that case too.
Thanks,
Andrew
>
> ChangeLog:
> 2015-03-03 Wilco Dijkstra
>
> * gcc/config/aarch64/aarch64-protos.h (tune_params):
> Add min_div_recip_mul_sf and min_div_recip_mul_df fields.
> * gcc/config/aarch64/aarch64.c (aarch64_min_divisions_for_recip_mul):
> Return value depending on target.
> (generic_tunings): Initialize new target settings.
> (cortexa53_tunings): Likewise.
> (cortexa57_tunings): Likewise.
> (thunderx_tunings): Likewise.
> (xgene1_tunings): Likewise.
>
> ---
> gcc/config/aarch64/aarch64-protos.h | 2 ++
> gcc/config/aarch64/aarch64.c| 26 +++---
> 2 files changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64-protos.h
> b/gcc/config/aarch64/aarch64-protos.h
> index 59c5824..4331e5c 100644
> --- a/gcc/config/aarch64/aarch64-protos.h
> +++ b/gcc/config/aarch64/aarch64-protos.h
> @@ -177,6 +177,8 @@ struct tune_params
>const int int_reassoc_width;
>const int fp_reassoc_width;
>const int vec_reassoc_width;
> + const int min_div_recip_mul_sf;
> + const int min_div_recip_mul_df;
> };
>
> HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index e22d72e..42a96f6 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -353,7 +353,9 @@ static const struct tune_params generic_tunings =
>4, /* loop_align. */
>2, /* int_reassoc_width. */
>4, /* fp_reassoc_width. */
> - 1/* vec_reassoc_width. */
> + 1, /* vec_reassoc_width. */
> + 2, /* min_div_recip_mul_sf. */
> + 2/* min_div_recip_mul_df. */
> };
>
> static const struct tune_params cortexa53_tunings =
> @@ -371,7 +373,9 @@ static const struct tune_params cortexa53_tunings =
>4, /* loop_align. */
>2, /* int_reassoc_width. */
>4, /* fp_reassoc_width. */
> - 1/* vec_reassoc_width. */
> + 1, /* vec_reassoc_width. */
> + 2, /* min_div_recip_mul_sf. */
> + 2/* min_div_recip_mul_df. */
> };
>
> static const struct tune_params cortexa57_tunings =
> @@ -389,7 +393,9 @@ static const struct tune_params cortexa57_tunings =
>4, /* loop_align. */
>2, /* int_reassoc_width. */
>4, /* fp_reassoc_width. */
> - 1/* vec_reassoc_width. */
> + 1, /* vec_reassoc_width. */
> + 2, /* min_div_recip_mul_sf. */
> + 2/* min_div_recip_mul_df. */
> };
>
> static const struct tune_params thunderx_tunings =
> @@ -406,7 +412,9 @@ static const struct tune_params thunderx_tunings =
>8, /* loop_align. */
>2, /* int_reassoc_width. */
>4, /* fp_reassoc_width. */
> - 1/* vec_reassoc_width. */
> + 1, /* vec_reassoc_width. */
> + 2, /* min_div_recip_mul_sf. */
> + 2/* min_div_recip_mul_df. */
> };
>
> static const struct tune_params xgene1_tunings =
> @@ -423,7 +431,9 @@ static const struct tune_params xgene1_tunings =
>16, /* loop_align. */
>2, /* int_reassoc_width. */
>4, /* fp_reassoc_width. */
> - 1/* vec_reassoc_width. */
> + 1, /* vec_reassoc_width. */
> + 2, /* min_div_recip_mul_sf. */
> + 2/* min_div_recip_mul_df. */
> };
>
> /* A processor implementing AArch64. */
> @@ -512,9 +522,11 @@ static const char * const aarch64_condition_codes[] =
> };
>
> static unsigned int
> -aarch64_min_divisions_for_recip_mul (enum machine_mode mode ATTRIBUTE_UNUSED)
> +aarch64_min_divisions_for_recip_mul (enum machine_mode mode)
> {
> - return 2;
> + if (GET_MODE_UNIT_SIZE (mode) == 4)
> +return aarch64_tune_params->min_div_recip_mul_sf;
> + return aarch64_tune_params->min_div_recip_mul_df;
> }
>
> static int
> --
> 1.9.1
>
>
>
>
Re: [patch] Fix ICE on unaligned record field
On Wed, Feb 25, 2015 at 7:43 AM, Martin Jambor wrote: > Hi Eric and Richard, > > On Tue, Jan 06, 2015 at 06:07:12PM +0100, Eric Botcazou wrote: >> Martin, >> >> > I suppose that could be done by something like the following, which I >> > have tested only very mildly so far, in particular I have not double >> > checked that get_inner_reference is cfun-agnostic. >> >> The patch introduces no regressions on x86-64/Linux and makes the testcase >> (gnat.dg/specs/pack12.ads attached to the first message) pass. >> >> Do you plan to install it (along with the testcase)? >> > > for various reasons I was not able to do it earlier, but today I have > re-bootstrapped the following (the only change is the added testcase) > on x86_64-linux and it passes OK. Should I commit it to trunk then? > > Thanks, > > Martin > > > 2015-02-25 Martin Jambor > Eric Botcazou > > gcc/ > * tree-sra.c (ipa_sra_check_caller_data): New type. > (has_caller_p): Removed. > (ipa_sra_check_caller): New function. > (ipa_sra_preliminary_function_checks): Use it. > This caused: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65305 -- H.J.
Re: [patch] Fix invalid attributes in libstdc++
On 03/02/15 10:37 +, Iain Sandoe wrote: the following additional tweaks provide further work-arounds. ... checked on darwin12 and darwin14. Also checked on x86_64-linux, committed to trunk.
[patch] PR c++/65295: Allow return-value optimization for constexpr's
In constexpr handling, we can request an rval for a return-value both by
an invisible reference and by virtue of named return value optimization.
Fixed by removing the assert.
Approved by Jason off-line.
Committed to mainline.
commit 1a8fdc708eeab70adc237193febf5f8db1eab995
Author: Aldy Hernandez
Date: Tue Mar 3 10:13:14 2015 -0800
PR c++/65295
* constexpr.c (cxx_eval_constant_expression): Remove assert in
RESULT_DECL handling.
diff --git a/gcc/cp/constexpr.c b/gcc/cp/constexpr.c
index f7e8ce9..1b5f50c 100644
--- a/gcc/cp/constexpr.c
+++ b/gcc/cp/constexpr.c
@@ -2955,8 +2955,8 @@ cxx_eval_constant_expression (const constexpr_ctx *ctx,
tree t,
if (lval)
return t;
/* We ask for an rvalue for the RESULT_DECL when indirecting
-through an invisible reference. */
- gcc_assert (DECL_BY_REFERENCE (t));
+through an invisible reference, or in named return value
+optimization. */
return (*ctx->values->get (t));
case VAR_DECL:
diff --git a/gcc/testsuite/g++.dg/pr65295.C b/gcc/testsuite/g++.dg/pr65295.C
new file mode 100644
index 000..c189ee1
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pr65295.C
@@ -0,0 +1,20 @@
+// { dg-do compile }
+// { dg-options "-std=c++1y" }
+
+struct arr {
+constexpr arr() : elem() { }
+char elem[17];
+};
+
+constexpr
+arr f()
+{
+arr result;
+return result;
+}
+
+constexpr arr a { f() };
+
+int main()
+{
+}
[PATCH][AArch64] Make aarch64_min_divisions_for_recip_mul configurable
This patch makes aarch64_min_divisions_for_recip_mul configurable for float and
double. This allows
CPUs with really fast or multiple dividers to return 3 (or even 4) if that
happens to be faster
overall. No code generation change - bootstrap & regression OK.
ChangeLog:
2015-03-03 Wilco Dijkstra
* gcc/config/aarch64/aarch64-protos.h (tune_params):
Add min_div_recip_mul_sf and min_div_recip_mul_df fields.
* gcc/config/aarch64/aarch64.c (aarch64_min_divisions_for_recip_mul):
Return value depending on target.
(generic_tunings): Initialize new target settings.
(cortexa53_tunings): Likewise.
(cortexa57_tunings): Likewise.
(thunderx_tunings): Likewise.
(xgene1_tunings): Likewise.
---
gcc/config/aarch64/aarch64-protos.h | 2 ++
gcc/config/aarch64/aarch64.c| 26 +++---
2 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-protos.h
b/gcc/config/aarch64/aarch64-protos.h
index 59c5824..4331e5c 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -177,6 +177,8 @@ struct tune_params
const int int_reassoc_width;
const int fp_reassoc_width;
const int vec_reassoc_width;
+ const int min_div_recip_mul_sf;
+ const int min_div_recip_mul_df;
};
HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index e22d72e..42a96f6 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -353,7 +353,9 @@ static const struct tune_params generic_tunings =
4, /* loop_align. */
2, /* int_reassoc_width. */
4, /* fp_reassoc_width. */
- 1/* vec_reassoc_width. */
+ 1, /* vec_reassoc_width. */
+ 2, /* min_div_recip_mul_sf. */
+ 2/* min_div_recip_mul_df. */
};
static const struct tune_params cortexa53_tunings =
@@ -371,7 +373,9 @@ static const struct tune_params cortexa53_tunings =
4, /* loop_align. */
2, /* int_reassoc_width. */
4, /* fp_reassoc_width. */
- 1/* vec_reassoc_width. */
+ 1, /* vec_reassoc_width. */
+ 2, /* min_div_recip_mul_sf. */
+ 2/* min_div_recip_mul_df. */
};
static const struct tune_params cortexa57_tunings =
@@ -389,7 +393,9 @@ static const struct tune_params cortexa57_tunings =
4, /* loop_align. */
2, /* int_reassoc_width. */
4, /* fp_reassoc_width. */
- 1/* vec_reassoc_width. */
+ 1, /* vec_reassoc_width. */
+ 2, /* min_div_recip_mul_sf. */
+ 2/* min_div_recip_mul_df. */
};
static const struct tune_params thunderx_tunings =
@@ -406,7 +412,9 @@ static const struct tune_params thunderx_tunings =
8, /* loop_align. */
2, /* int_reassoc_width. */
4, /* fp_reassoc_width. */
- 1/* vec_reassoc_width. */
+ 1, /* vec_reassoc_width. */
+ 2, /* min_div_recip_mul_sf. */
+ 2/* min_div_recip_mul_df. */
};
static const struct tune_params xgene1_tunings =
@@ -423,7 +431,9 @@ static const struct tune_params xgene1_tunings =
16, /* loop_align. */
2, /* int_reassoc_width. */
4, /* fp_reassoc_width. */
- 1/* vec_reassoc_width. */
+ 1, /* vec_reassoc_width. */
+ 2, /* min_div_recip_mul_sf. */
+ 2/* min_div_recip_mul_df. */
};
/* A processor implementing AArch64. */
@@ -512,9 +522,11 @@ static const char * const aarch64_condition_codes[] =
};
static unsigned int
-aarch64_min_divisions_for_recip_mul (enum machine_mode mode ATTRIBUTE_UNUSED)
+aarch64_min_divisions_for_recip_mul (enum machine_mode mode)
{
- return 2;
+ if (GET_MODE_UNIT_SIZE (mode) == 4)
+return aarch64_tune_params->min_div_recip_mul_sf;
+ return aarch64_tune_params->min_div_recip_mul_df;
}
static int
--
1.9.1
RE: [PATCH][ARM] PR target/64600 Fix another ICE with -mtune=xscale: properly sign-extend mask during constant splitting
> -Original Message-
> From: Kyrylo Tkachov
> Sent: 27 February 2015 14:30
> To: Kyrylo Tkachov; GCC Patches
> Cc: Ramana Radhakrishnan; Richard Earnshaw
> Subject: RE: [PATCH][ARM] PR target/64600 Fix another ICE with -
> mtune=xscale: properly sign-extend mask during constant splitting
>
> On 03/02/15 15:18, Kyrill Tkachov wrote:
> > Hi all,
> >
> > The ICE in this PR occurs when -mtune=xscale triggers a particular
> > path through arm_gen_constant during expand that creates a 0xf00f
> > mask but for a 64-bit HOST_WIDE_INT doesn't sign extend it into
> > 0xf00f that signifies the required -4081. It leaves it as
> > 0xf00f (4294963215) that breaks when later combine tries to
> > perform an SImode bitwise AND using the wide-int machinery.
> >
> > I think the correct approach here is to use trunc_int_for_mode that
> > correctly sign-extends the constant so that it is properly represented
> > by a HOST_WIDE_INT for the required mode.
> >
> > Bootstrapped and tested arm-none-linux-gnueabihf with -mtune=xscale in
> > BOOT_CFLAGS.
> >
> > The testcase triggers for -mcpu=xscale and all slowmul targets because
> > they are the only ones that have the constant_limit tune parameter set
> > to anything >1 which is required to follow this particular path
> > through arm_split_constant. Also, the rtx costs can hide this ICE
> > sometimes.
> >
> > Ok for trunk?
> >
> > Thanks,
> > Kyrill
> >
> > 2015-02-03 Kyrylo Tkachov
> >
> > PR target/64600
> > * config/arm/arm.c (arm_gen_constant, AND case): Call
> > trunc_int_for_mode when constructing AND mask.
> >
> > 2015-02-03 Kyrylo Tkachov
> >
> > PR target/64600
> > * gcc.target/arm/pr64600_1.c: New test.
> > arm-xscale-wide.patch
> > commit 52388a359dd65276bccfac499a2fd9e406fbe1a8
> > Author: Kyrylo Tkachov
> > Date: Tue Jan 20 11:21:34 2015 +
> >
> > [ARM] Fix ICE due to arm_gen_constant not sign_extending
> >
> > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index
> > db4834b..d0f3a52 100644
> > --- a/gcc/config/arm/arm.c
> > +++ b/gcc/config/arm/arm.c
> > @@ -4709,19 +4709,20 @@ arm_gen_constant (enum rtx_code code,
> > machine_mode mode, rtx cond,
> >
> > if ((remainder | shift_mask) != 0x)
> > {
> > + HOST_WIDE_INT new_val
> > + = trunc_int_for_mode (remainder | shift_mask, mode);
>
> Offlist, Richard mentioned that trunc_int_for_mode may pessimize codegen
> for HImode values due to excessive setting of bits and using
> ARM_SIGN_EXTEND might be preferable.
> I've tried that and it does fix the ICE and goes through testing ok. Bootstrap
> still ongoing.
> I didn't perform any code quality investigation. Richard, are there any
> particular code sequences that you'd like us to investigate here?
>
Here's the alternative version using ARM_SIGN_EXTEND if you want to have a
look.
Thanks,
Kyrill
2015-03-03 Kyrylo Tkachov
PR target/64600
* config/arm/arm.c (arm_gen_constant, AND case): Use
ARM_SIGN_EXTEND when constructing AND mask.
2015-03-03 Kyrylo Tkachov
PR target/64600
* gcc.target/arm/pr64600_1.c: New test.
> Thanks,
> Kyrill
>
> >
> > +
> > if (generate)
> > {
> > rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
> > - insns = arm_gen_constant (AND, mode, cond,
> > - remainder | shift_mask,
> > + insns = arm_gen_constant (AND, SImode, cond, new_val,
> > new_src, source, subtargets, 1);
> > source = new_src;
> > }
> > else
> > {
> > rtx targ = subtargets ? NULL_RTX : target;
> > - insns = arm_gen_constant (AND, mode, cond,
> > - remainder | shift_mask,
> > + insns = arm_gen_constant (AND, mode, cond, new_val,
> > targ, source, subtargets, 0);
> > }
> > }
> > @@ -4744,12 +4745,13 @@ arm_gen_constant (enum rtx_code code,
> > machine_mode mode, rtx cond,
> >
> > if ((remainder | shift_mask) != 0x)
> > {
> > + HOST_WIDE_INT new_val
> > + = trunc_int_for_mode (remainder | shift_mask, mode);
> > if (generate)
> > {
> > rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
> >
> > - insns = arm_gen_constant (AND, mode, cond,
> > - remainder | shift_mask,
> > + insns = arm_gen_constant (AND, mode, cond, new_val,
> > new_src, source, subtargets, 1);
> > source = new_src;
> > }
> > @@ -4757,8 +4759,7 @@ arm_gen_constant (enum rtx_code code,
> machine_mode mode, rtx cond,
> > {
> > rtx targ = subtargets ? NULL_RTX : target;
> >
> > - insns = arm
Fix oversight in round_up_loc change
The fix for PR c/60226
https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=212346
changed the type of the 'divisor' parameter of the round_up_loc function from
'int' to 'unsigned int'. Now the function does the usual masking dance with
powers of two, in particular:
t = build_int_cst (TREE_TYPE (value), -divisor);
The 2nd parameter of build_int_cst being HOST_WIDE_INT, the argument is now
zero-extended from 'unsigned int' to HOST_WIDE_INT instead of sign-extended.
This is harmless in most cases, but not if you're manipulating huge sizes
because the upper 32-bit part is wrongly masked out, which for example causes
a warning to disappear for the attached Ada testcase.
Tested on x86_64-suse-linux, applied on the mainline as obvious.
There might be a similar issue in the block of code just above:
wide_int val = value;
bool overflow_p;
if ((val & (divisor - 1)) == 0)
return value;
overflow_p = TREE_OVERFLOW (value);
val &= ~(divisor - 1);
but I don't have a testcase and don't know enough of wide_int to assert it.
2015-03-03 Eric Botcazou
* fold-const.c (round_up_loc): Cast divisor to HOST_WIDE_INT before
negating it.
* tree-sra.c (pa_sra_preliminary_function_checks): Fix typo in message.
2015-03-03 Eric Botcazou
* gnat.dg/object_overflow5.adb: New test.
--
Eric BotcazouIndex: fold-const.c
===
--- fold-const.c (revision 221132)
+++ fold-const.c (working copy)
@@ -16032,7 +16032,7 @@ round_up_loc (location_t loc, tree value
t = build_int_cst (TREE_TYPE (value), divisor - 1);
value = size_binop_loc (loc, PLUS_EXPR, value, t);
- t = build_int_cst (TREE_TYPE (value), -divisor);
+ t = build_int_cst (TREE_TYPE (value), - (HOST_WIDE_INT) divisor);
value = size_binop_loc (loc, BIT_AND_EXPR, value, t);
}
}
Index: tree-sra.c
===
--- tree-sra.c (revision 221150)
+++ tree-sra.c (working copy)
@@ -5144,7 +5144,7 @@ ipa_sra_preliminary_function_checks (str
{
if (dump_file)
fprintf (dump_file,
- "A function call has an argument with non-unit alignemnt.\n");
+ "A function call has an argument with non-unit alignment.\n");
return false;
}
-- { dg-do compile }
procedure Object_Overflow5 is
procedure Proc (c : Character) is begin null; end;
type Index is new Long_Integer range 0 .. Long_Integer'Last;
type Arr is array(Index range <>) of Character;
type Rec (Size: Index := 6) is record -- { dg-warning "Storage_Error" }
A: Arr (0..Size);
end record;
Obj : Rec; -- { dg-warning "Storage_Error" }
begin
Obj.A(1) := 'a';
Proc (Obj.A(1));
end;
Re: [RFC 2/2] Implement call0 ABI for xtensa
On Tue, Mar 3, 2015 at 7:13 PM, augustine.sterl...@gmail.com wrote: > On Sat, Feb 28, 2015 at 10:14 AM, Max Filippov wrote: >> call0 is an ABI that doesn't use register windows. > > This is OK for xtensa. Applied to trunk. Thanks! -- Max
Re: [PATCH] Fix PR ipa/65282
> Hello. > > There's suggested patch for the issue, where regression test have been > running on x86_64-linux-pc. > > Ready for trunk after tests will be finished? > Thanks, > Martin > >From a186fc97c5f192b94cc571f611a50eb0f4f8a354 Mon Sep 17 00:00:00 2001 > From: mliska > Date: Tue, 3 Mar 2015 11:33:30 +0100 > Subject: [PATCH] Fix PR ipa/65282. > > gcc/testsuite/ChangeLog: > > 2015-03-03 Martin Liska > > * gcc.dg/ipa/PR65282.c: New test. > > gcc/ChangeLog: > > 2015-03-03 Martin Liska > > PR ipa/65282 > * ipa-icf.c (sem_variable::equals): Fix wrong condition. OK, Honza
Re: [PATCH] Fix PR ipa/65287
> gcc/testsuite/ChangeLog: > > 2015-03-03 Martin Liska > > * gcc.dg/ipa/pr65287.c: New test. > > gcc/ChangeLog: > > 2015-03-03 Martin Liska > > PR ipa/65287 > * ipa-icf.c (sem_variable::parse): Skip all alias variables. OK Sorry, I must have inadverty reverted this. Honza
Re: [PATCH] Fix PR ipa/65282
> Hello. > > There's suggested patch for the issue, where regression test have been > running on x86_64-linux-pc. > > Ready for trunk after tests will be finished? > Thanks, > Martin > >From a186fc97c5f192b94cc571f611a50eb0f4f8a354 Mon Sep 17 00:00:00 2001 > From: mliska > Date: Tue, 3 Mar 2015 11:33:30 +0100 > Subject: [PATCH] Fix PR ipa/65282. > > gcc/testsuite/ChangeLog: > > 2015-03-03 Martin Liska > > * gcc.dg/ipa/PR65282.c: New test. > > gcc/ChangeLog: > > 2015-03-03 Martin Liska > > PR ipa/65282 > * ipa-icf.c (sem_variable::equals): Fix wrong condition. OK. Honza
Re: [PATCH] Turn RETURN_ADDR_IN_PREVIOUS_FRAME into C expression
On Tue, Mar 3, 2015 at 6:52 PM, H.J. Lu wrote: > On Tue, Mar 3, 2015 at 7:05 AM, Max Filippov wrote: >> On Tue, Mar 3, 2015 at 5:51 PM, Richard Henderson wrote: >>> On 03/02/2015 10:42 PM, Max Filippov wrote: gcc/ * builtins.c (expand_builtin_return_addr): Add RETURN_ADDR_IN_PREVIOUS_FRAME to 'if' condition, remove surrounding #ifdef. * config/sparc/sparc.h (RETURN_ADDR_IN_PREVIOUS_FRAME): Change definition to 1. * config/xtensa/xtensa.h (RETURN_ADDR_IN_PREVIOUS_FRAME): Likewise. * defaults.h (RETURN_ADDR_IN_PREVIOUS_FRAME): Define to 0 if undefined. doc/tm.texi.in (RETURN_ADDR_IN_PREVIOUS_FRAME): Update paragraph. >>> >>> Ok. >> >> Applied to trunk. Thanks! >> > > I checked in this to fix bootstrap. > > Index: ChangeLog > === > --- ChangeLog (revision 221150) > +++ ChangeLog (working copy) > @@ -1,3 +1,7 @@ > +2015-03-03 H.J. Lu > + > + * doc/tm.texi: Regenerated. > + Oops. Sorry about that. -- Thanks. -- Max
Minor MAINTAINERS updates
It's been reported that Paul's address is no longer active and Paul hasn't been active in some time. Obviously if he returns to GCC development, we'd welcome him with open arms. But in the mean time, listing him as a maintainer doesn't make much sense. Separately, I've had a conversation with Richard Henderson WRT x86 port maintenance. He's stepping down from that position to better reflect reality of what he's working on and expects to work on. Committed. diff --git a/ChangeLog b/ChangeLog index 56737c5..bd43281 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,9 @@ +2015-03-13 Jeff Law + + * MAINTAINERS: Remove Paul Brook as a Fortran and ARM + maintainer. + Remove Richard Henderson as a maintainer for the x86 port. + 2015-03-03 Joern Rennecke * MAINTAINERS (CPU Port Maintainers): Update my email address. diff --git a/MAINTAINERS b/MAINTAINERS index e4ac16b..24312f3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -47,7 +47,6 @@ alpha portRichard Henderson arc port Joern Rennecke arm port Nick Clifton arm port Richard Earnshaw -arm port Paul Brook arm port Ramana Radhakrishnan avr port Denis Chertykov bfin port Bernd Schmidt @@ -62,7 +61,6 @@ h8 port Jeff Law h8 portKazu Hirata hppa port Jeff Law hppa port John David Anglin -i386 port Richard Henderson i386 port Jan Hubicka i386 port Uros Bizjak ia64 port Jim Wilson @@ -151,7 +149,6 @@ Ada front end Geert Bosch Ada front end Robert Dewar Ada front end Arnaud Charlet Ada front end Eric Botcazou -FortranPaul Brook c++Jason Merrill c++Nathan Sidwell go Ian Lance Taylor
Re: [PATCH, alpha]: Fix PR/47230 [4.6/4.7 Regression] gcc fails to bootstrap on alpha in stage2 with "relocation truncated to fit: GPREL16 against ..."
On Tue, Mar 3, 2015 at 3:14 PM, Uros Bizjak wrote: > On Mon, Mar 2, 2015 at 7:23 PM, Richard Henderson wrote: > >>> Unfortunately, while "normal" bootstrap works OK with alpha-linux-gnu >>> and alphaev68-linux-gnu, the bootstrap still fails when configured >>> --with-build-config=bootstrap-lto: >>> >>> libbackend.a(tree-data-ref.o): In function `non_affine_dependence_relation': >>> /space/uros/gcc-build-profiled/gcc/../../gcc-svn/trunk/gcc/tree-data-ref.c:1661:(.text+0x1b8): >>> relocation truncated to fit: GPREL16 against symbol `dump_file' >>> defined in .sbss section in libbackend.a(dumpfile.o) >> >> Interesting. And using bootstrap-lto works with --no-relax? I don't believe >> I've ever tried it... > > Yes, I can re-confirm, that Rev: 221041 can bootstrap with > -Wl,--no-relax patch on alphaev68-linux-gnu, when configured with > "--with-build-config=bootstrap-lto --disable-werror > --enable-languages=c,c++,fortran" with binutils 2.25. I will post > testresults when bootstrap+regression test finish. Results are here [1]. [1] https://gcc.gnu.org/ml/gcc-testresults/2015-03/msg00346.html Uros.
[COMMITTED][DOC]Fix an obvious typo in md.texi
Hi all,
I have just committed this simple and obvious patch to fix a typo for
"^" multiple alternative constraints in md.texi.
Doc builds Okay.
SVN revision link:
https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=221152
ChangeLog:
2015-03-03 Renlin Li
* gcc/doc/md.texi (@item ^): Change ? into ^.diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index f2c25c2..bc1ec9d 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -1512,7 +1512,7 @@ but if reloading is needed, some other alternative will be used.
@cindex caret
@item ^
This constraint is analogous to @samp{?} but it disparages slightly
-the alternative only if the operand with the @samp{?} needs a reload.
+the alternative only if the operand with the @samp{^} needs a reload.
@cindex @samp{$} in constraint
@cindex dollar sign
[PATCH][AArch64] Use conditional negate for abs expansion
Expand abs into a compare and conditional negate. This is the most obvious
expansion, enables
merging of the comparison into ALU instructions and is faster on all
implementations. Bootstrapped &
regression tested.
int f(int x) { return abs (x + 1); }
Before:
add w0, w0, 1
sxtwx0, w0
eor x1, x0, x0, asr 63
sub x1, x1, x0, asr 63
mov x0, x1
ret
After:
addsw0, w0, 1
csneg w0, w0, w0, pl
ret
ChangeLog:
2015-03-03 Wilco Dijkstra
* gcc/config/aarch64/aarch64.md (absdi2): optimize abs expansion.
(csneg3_insn): enable expansion of pattern.
* gcc/testsuite/gcc.target/aarch64/abs_1.c (abs64): update test
for new abs expansion. (abs64_in_dreg): likewise.
---
gcc/config/aarch64/aarch64.md| 33 +++-
gcc/testsuite/gcc.target/aarch64/abs_1.c | 5 ++---
2 files changed, 9 insertions(+), 29 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 1f4169e..46b7a63 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2172,35 +2172,16 @@
[(set_attr "type" "alu_ext")]
)
-(define_insn_and_split "absdi2"
- [(set (match_operand:DI 0 "register_operand" "=&r,w")
- (abs:DI (match_operand:DI 1 "register_operand" "r,w")))]
+(define_expand "abs2"
+ [(match_operand:GPI 0 "register_operand" "")
+ (match_operand:GPI 1 "register_operand" "")]
""
- "@
- #
- abs\\t%d0, %d1"
- "reload_completed
- && GP_REGNUM_P (REGNO (operands[0]))
- && GP_REGNUM_P (REGNO (operands[1]))"
- [(const_int 0)]
{
-emit_insn (gen_rtx_SET (VOIDmode, operands[0],
- gen_rtx_XOR (DImode,
-gen_rtx_ASHIFTRT (DImode,
- operands[1],
- GEN_INT (63)),
-operands[1])));
-emit_insn (gen_rtx_SET (VOIDmode,
- operands[0],
- gen_rtx_MINUS (DImode,
- operands[0],
- gen_rtx_ASHIFTRT (DImode,
-operands[1],
-GEN_INT (63);
+rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
+rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
+emit_insn (gen_csneg3_insn (operands[0], x, operands[1],
operands[1]));
DONE;
}
- [(set_attr "type" "alu_sreg")
- (set_attr "simd" "no,yes")]
)
(define_insn "neg2"
@@ -2879,7 +2860,7 @@
[(set_attr "type" "csel")]
)
-(define_insn "*csneg3_insn"
+(define_insn "csneg3_insn"
[(set (match_operand:GPI 0 "register_operand" "=r")
(if_then_else:GPI
(match_operand 1 "aarch64_comparison_operation" "")
diff --git a/gcc/testsuite/gcc.target/aarch64/abs_1.c
b/gcc/testsuite/gcc.target/aarch64/abs_1.c
index 938bc84..11f1095 100644
--- a/gcc/testsuite/gcc.target/aarch64/abs_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/abs_1.c
@@ -7,15 +7,14 @@ extern void abort (void);
long long
abs64 (long long a)
{
- /* { dg-final { scan-assembler "eor\t" } } */
- /* { dg-final { scan-assembler "sub\t" } } */
+ /* { dg-final { scan-assembler "csneg\t" } } */
return llabs (a);
}
long long
abs64_in_dreg (long long a)
{
- /* { dg-final { scan-assembler "abs\td\[0-9\]+, d\[0-9\]+" } } */
+ /* { dg-final { scan-assembler "csneg\t" } } */
register long long x asm ("d8") = a;
register long long y asm ("d9");
asm volatile ("" : : "w" (x));
--
1.9.1
Re: [RFC 2/2] Implement call0 ABI for xtensa
On Sat, Feb 28, 2015 at 10:14 AM, Max Filippov wrote:
> call0 is an ABI that doesn't use register windows.
>
> 2015-02-28 Max Filippov
>
> gcc/
> * config/xtensa/constraints.md ("a" constraint): Include stack
> pointer in case of call0 ABI.
> ("q" constraint): Make empty in case of call0 ABI.
> ("D" constraint): Include stack pointer in case of call0 ABI.
>
> * config/xtensa/xtensa-protos.h (xtensa_set_return_address,
> xtensa_expand_epilogue, xtensa_regno_to_class): Add new function
> prototypes.
>
> * config/xtensa/xtensa.c (xtensa_callee_save_size): New
> variable.
> (xtensa_regno_to_class): Make it a local variable in the
> function xtensa_regno_to_class.
> (xtensa_function_epilogue, TARGET_ASM_FUNCTION_EPILOGUE): Remove
> macro, function prototype and implementation.
> (reg_nonleaf_alloc_order): Make it a local variable in the
> function order_regs_for_local_alloc.
> (xtensa_conditional_register_usage): New function.
> (TARGET_CONDITIONAL_REGISTER_USAGE): Define macro.
> (xtensa_valid_move): Allow direct moves to stack pointer
> register in call0 ABI.
> (xtensa_setup_frame_addresses): Only spill register windows in
> windowed ABI.
> (xtensa_emit_call): Emit call(x)8 or call(x)0 in windowed and
> call0 ABI respectively.
> (xtensa_function_arg_1): Only mark a7 register for copying in
> windowed ABI.
> (xtensa_call_save_reg): New function.
> (compute_frame_size): Add space for callee saved register
> storage to the frame size in call0 ABI.
> (xtensa_expand_prologue): Generate code to set up stack frame
> and save callee-saved registers in call0 ABI.
> (xtensa_expand_epilogue): New function.
> (xtensa_set_return_address): New function.
> (xtensa_return_addr): Calculate return address in call0 ABI.
> (xtensa_builtin_saveregs): Only mark a7 register for copying and
> emit copying code in windowed ABI.
> (order_regs_for_local_alloc): Add preferred register allocation
> order for non-leaf function in call0 ABI.
> (xtensa_static_chain): Add atatic chain passing for call0 ABI.
> (xtensa_asm_trampoline_template): Add trampoline generation for
> call0 ABI.
> (xtensa_trampoline_init): Add trampoline initialization for
> call0 ABI.
> (xtensa_conditional_register_usage, xtensa_regno_to_class): New
> functions.
>
> * config/xtensa/xtensa.h (TARGET_WINDOWED_ABI): New macro.
> (TARGET_CPU_CPP_BUILTINS): Add built-in define for call0 ABI.
> (CALL_USED_REGISTERS): Modify to encode both windowed and call0
> ABI call-used registers.
> (HARD_FRAME_POINTER_REGNUM): Add frame pointer for call0 ABI.
> (INCOMING_REGNO, OUTGOING_REGNO): Use argument unchanged in
> call0 ABI.
> (REG_CLASS_CONTENTS): Include all registers into the preferred
> reload registers set, adjust the set in the
> xtensa_conditional_register_usage.
> (xtensa_regno_to_class): Drop variable declaration.
> (REGNO_REG_CLASS): Redefine to use xtensa_regno_to_class
> function.
> (WINDOW_SIZE): Define as 8 or 0 for windowed and call0 ABI
> respectively.
> (FUNCTION_PROFILER): Add _mcount call for call0 ABI.
> (TRAMPOLINE_SIZE): Define trampoline size for call0 ABI.
> (RETURN_ADDR_IN_PREVIOUS_FRAME): Define to 0 in call0 ABI.
> (ASM_OUTPUT_POOL_PROLOGUE): Always generate literal pool
> location in call0 ABI.
> (EH_RETURN_STACKADJ_RTX): New definition, use a10 for passing
> stack adjustment size when handling exception.
> (CRT_CALL_STATIC_FUNCTION): Add definition for call0 ABI.
>
> * config/xtensa/xtensa.md (A9_REG, UNSPECV_BLOCKAGE): New
> definitions.
> ("return" pattern): Generate ret.n/ret in call0 ABI.
> ("epilogue" pattern): Expand epilogue.
> ("nonlocal_goto" pattern): Use default in call0 ABI.
> ("eh_return" pattern): Move implementation to eh_set_a0_windowed,
> emit eh_set_a0_* depending on ABI.
> ("eh_set_a0_windowed" pattern): Former eh_return pattern.
> ("eh_set_a0_call0", "blockage"): New patterns.
>
> libgcc/
> * config/xtensa/lib2funcs.S (__xtensa_libgcc_window_spill,
> __xtensa_nonlocal_goto): Don't compile for call0 ABI.
> (__xtensa_sync_caches): Only use entry and retw in windowed ABI,
> use ret in call0 ABI.
>
> * config/xtensa/t-windowed: New file.
>
> * libgcc/config/xtensa/t-xtensa (LIB2ADDEH): Move to t-windowed.
>
> * libgcc/configure: Regenerated.
>
> * libgcc/configure.ac: Check if xtensa target is configured for
> windowed ABI and thus needs to use custom unwind code.
Re: [PATCH] PR rtl-optimization/32219: optimizer causees wrong code in pic/hidden/weak symbol checking
On 19/02/15 17:26, Richard Henderson wrote:
On 02/19/2015 09:08 AM, Alex Velenko wrote:
Your suggestion seem to fix gcc.target/arm/long-calls-1.c, but has to be
thoroughly tested.
Before you do complete testing, please also delete the TREE_STATIC test.
That bit should never be relevant to functions, as it indicates not that
it is in the compilation unit, but that it has static (as opposed to
automatic) storage duration. Thus it is only relevant to variables.
r~
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 7bf5b4d..777230e 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -6392,14 +6392,8 @@ arm_set_default_type_attributes (tree type)
static bool
arm_function_in_section_p (tree decl, section *section)
{
- /* We can only be certain about functions defined in the same
- compilation unit. */
- if (!TREE_STATIC (decl))
-return false;
-
- /* Make sure that SYMBOL always binds to the definition in this
- compilation unit. */
- if (!targetm.binds_local_p (decl))
+ /* We can only be certain about the prevailing symbol definition. */
+ if (!decl_binds_to_current_def_p (decl))
return false;
/* If DECL_SECTION_NAME is set, assume it is trustworthy. */
Hi,
Did a bootstrap and a full regression run on arm-none-linux-gnueabihf,
No new regressions found. Some previously failing tests in libstdc++
started to fail differently, for example:
< ERROR: 22_locale/num_get/get/wchar_t/2.cc: can't read
"additional_sources": no such variable for " dg-do 22 run { xfail
lax_strtof\
p } "
< UNRESOLVED: 22_locale/num_get/get/wchar_t/2.cc: can't read
"additional_sources": no such variable for " dg-do 22 run { xfail lax_s\
trtofp } "
---
> ERROR: 22_locale/num_get/get/wchar_t/2.cc: can't read
"et_cache(uclibc,value)": no such element in array for " dg-do 22 run {
xfai\
l lax_strtofp } "
> UNRESOLVED: 22_locale/num_get/get/wchar_t/2.cc: can't read
"et_cache(uclibc,value)": no such element in array for " dg-do 22 run {\
xfail lax_strtofp } "
But I think it is okay.
Kind regards,
Alex
Re: [PATCH] Turn RETURN_ADDR_IN_PREVIOUS_FRAME into C expression
On Tue, Mar 3, 2015 at 7:05 AM, Max Filippov wrote:
> On Tue, Mar 3, 2015 at 5:51 PM, Richard Henderson wrote:
>> On 03/02/2015 10:42 PM, Max Filippov wrote:
>>> gcc/
>>> * builtins.c (expand_builtin_return_addr): Add
>>> RETURN_ADDR_IN_PREVIOUS_FRAME to 'if' condition, remove
>>> surrounding #ifdef.
>>> * config/sparc/sparc.h (RETURN_ADDR_IN_PREVIOUS_FRAME): Change
>>> definition to 1.
>>> * config/xtensa/xtensa.h (RETURN_ADDR_IN_PREVIOUS_FRAME):
>>> Likewise.
>>> * defaults.h (RETURN_ADDR_IN_PREVIOUS_FRAME): Define to 0 if
>>> undefined.
>>> doc/tm.texi.in (RETURN_ADDR_IN_PREVIOUS_FRAME): Update
>>> paragraph.
>>
>> Ok.
>
> Applied to trunk. Thanks!
>
I checked in this to fix bootstrap.
--
H.J.
---
Index: ChangeLog
===
--- ChangeLog (revision 221150)
+++ ChangeLog (working copy)
@@ -1,3 +1,7 @@
+2015-03-03 H.J. Lu
+
+ * doc/tm.texi: Regenerated.
+
2015-03-03 Max Filippov
* builtins.c (expand_builtin_return_addr): Add
Index: doc/tm.texi
===
--- doc/tm.texi (revision 221150)
+++ doc/tm.texi (working copy)
@@ -3045,7 +3045,7 @@ A C expression whose value is RTL repres
address for the frame @var{count} steps up from the current frame, after
the prologue. @var{frameaddr} is the frame pointer of the @var{count}
frame, or the frame pointer of the @var{count} @minus{} 1 frame if
-@code{RETURN_ADDR_IN_PREVIOUS_FRAME} is defined.
+@code{RETURN_ADDR_IN_PREVIOUS_FRAME} is nonzero.
The value of the expression must always be the correct address when
@var{count} is zero, but may be @code{NULL_RTX} if there is no way to
@@ -3053,8 +3053,9 @@ determine the return address of other fr
@end defmac
@defmac RETURN_ADDR_IN_PREVIOUS_FRAME
-Define this if the return address of a particular stack frame is accessed
-from the frame pointer of the previous stack frame.
+Define this macro to nonzero value if the return address of a particular
+stack frame is accessed from the frame pointer of the previous stack
+frame. The zero default for this macro is suitable for most ports.
@end defmac
@defmac INCOMING_RETURN_ADDR_RTX
RFA: RL78: Add muladdhi3 pattern
Hi DJ,
Compiling this test case with the RL78 toolchain results in an ICE:
unsigned char g_X;
unsigned char g_Y;
const __far unsigned char TabA[2][2] = { { 3, 0 }, { 4, 5 } };
void main (void) { g_X = 1; g_Y = TabA[g_X][g_X]; }
The problem appears to be that GCC will create a multiply-plus-add
instruction to access the table regardless of whether the backend
supports such an instruction. I could not work out where in the
middle end this was occurring, so instead I created the patch below
which contains a splitter to separate out the multiply and addition
operations.
Tested with no regressions on an rl78-elf toolchain.
OK to apply ?
Cheers
Nick
gcc/ChangeLog
2015-03-03 Nick Clifton
* config/rl78/rl78.md (muladdhi4): New splitter.
Index: gcc/config/rl78/rl78.md
===
--- gcc/config/rl78/rl78.md (revision 221150)
+++ gcc/config/rl78/rl78.md (working copy)
@@ -441,3 +441,15 @@
""
""
)
+
+(define_insn_and_split "muladdhi4"
+ [(set (match_operand:HI 0 "register_operand" "=&v")
+ (plus:HI (mult:HI (match_operand:HI 1 "general_operand" "vi")
+ (match_operand:HI 2 "general_operand" "vi"))
+(match_operand:HI 3 "register_operand" "v")))]
+ "! RL78_MUL_NONE"
+ "#"
+ ""
+ [(set (match_dup 0) (mult:HI (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (plus:HI (match_dup 0) (match_dup 3)))]
+)
RFA: RL78: Fix register constraints in rl78-real.md
Hi DJ,
Compiling a program with one of the real RL78 registers marked as
call-used (eg via -fcall-used-ax), can trigger an internal compiler
error. Although modifying the ABI in this way may not be a good idea,
it is still wrong that the compiler generates an ICE.
The patch below fixes the problem by removing real RL78 registers from
the "general" register class, so that they can only be allocated
explicitly by the RL78 backend. It also updates the patterns in
rl78-real.md so that where before they used the "r" general register
constraint they now use the "R" and "v" register constraints.
Tested with no regressions on an rl78-elf toolchain.
OK to apply ?
Cheers
Nick
gcc/ChangeLog
2015-03-03 Nick Clifton
* config/rl78/rl78.h (enum reg_class): Remove real registers from
General register class.
* config/rl78/rl78-real.md: Replace general register constraints
with real+virtual register constraints.
Index: gcc/config/rl78/rl78-real.md
===
--- gcc/config/rl78/rl78-real.md(revision 221150)
+++ gcc/config/rl78/rl78-real.md(working copy)
@@ -59,7 +59,7 @@
)
(define_insn "*movqi_real"
- [(set (match_operand:QI 0 "rl78_nonimmediate_operand"
"=g,RaxbcWab,RaxbcWab,a, bcx,R,
WabWd2WhlWh1WhbWbcWs1v, bcx,WsaWsf")
+ [(set (match_operand:QI 0 "rl78_nonimmediate_operand"
"=Rv,RaxbcWab,RaxbcWab,a, bcx,R,
WabWd2WhlWh1WhbWbcWs1v, bcx,WsaWsf")
(match_operand1 "rl78_general_operand" "0,K,M,
RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a, R, i"))]
"rl78_real_insns_ok ()"
"@
@@ -75,7 +75,7 @@
)
(define_insn "*movhi_real"
- [(set (match_operand:HI 0 "rl78_nonimmediate_operand"
"=g,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v")
+ [(set (match_operand:HI 0 "rl78_nonimmediate_operand"
"=Rv,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v")
(match_operand:HI 1 "rl78_general_operand" " 0,K, M, i,
BDTvSWabWd2WdeWh1WhlWbcWs1,A, BDT,vS, ABDT"))]
"rl78_real_insns_ok ()"
"@
@@ -93,7 +93,7 @@
;;-- Conversions
(define_insn "*zero_extendqihi2_real"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rv,A")
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=Rv,A")
(zero_extend:HI (match_operand:QI 1 "general_operand" "0,a")))]
"rl78_real_insns_ok ()"
"@
@@ -113,7 +113,7 @@
;;-- Arithmetic
(define_insn "*addqi3_real"
- [(set (match_operand:QI 0 "rl78_nonimmediate_operand"
"=rvWabWhlWh1,rvWabWhlWh1,a,*bcdehl,Wsa")
+ [(set (match_operand:QI 0 "rl78_nonimmediate_operand"
"=RvWabWhlWh1,RvWabWhlWh1,a,*bcdehl,Wsa")
(plus:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0,0,0")
(match_operand:QI 2 "rl78_general_operand"
"K,L,RWhlWh1Wabi,a,i")))
]
@@ -146,8 +146,8 @@
)
(define_insn "*addqihi3a_real"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+ [(set (match_operand:HI 0 "register_operand" "=R")
+ (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "R"))
(match_operand:HI 2 "register_operand" "0")))
]
"rl78_real_insns_ok ()"
@@ -381,7 +381,7 @@
[(set (pc) (if_then_else
(match_operator 0 "rl78_cmp_operator_real"
[(match_operand:QI 1 "rl78_general_operand"
"Wabvaxbc,a, vWsaWab,bcdehl")
- (match_operand:QI 2 "rl78_general_operand" "M,
irvWabWhlWh1Whb,i,a")])
+ (match_operand:QI 2 "rl78_general_operand" "M,
iRvWabWhlWh1Whb,i,a")])
(label_ref (match_operand 3 "" ""))
(pc)))]
"rl78_real_insns_ok ()"
Index: gcc/config/rl78/rl78.h
===
--- gcc/config/rl78/rl78.h (revision 221150)
+++ gcc/config/rl78/rl78.h (working copy)
@@ -266,7 +266,7 @@
{ 0x0c00, 0x }, /* R10 - HImode */ \
{ 0xff00, 0x }, /* INT - HImode */ \
{ 0xff7fff00, 0x }, /* Virtual registers. */ \
- { 0xff7f, 0x0002 }, /* General registers. */ \
+ { 0xff7fff00, 0x0002 }, /* General registers. */ \
{ 0x0400, 0x0004 }, /* PSW. */ \
{ 0xff7f, 0x001f } /* All registers. */ \
}
Committed: update my email address
2015-03-03 Joern Rennecke * MAINTAINERS (CPU Port Maintainers): Update my email address. 2015-03-03 Joern Rennecke * MAINTAINERS (CPU Port Maintainers): Update my email address. Index: MAINTAINERS === --- MAINTAINERS (revision 221147) +++ MAINTAINERS (working copy) @@ -44,7 +44,7 @@ aarch64 port Marcus Shawcroft aarch64 port Richard Earnshaw alpha port Richard Henderson -arc port Joern Rennecke +arc port Joern Rennecke arm port Nick Clifton arm port Richard Earnshaw arm port Paul Brook @@ -54,7 +54,7 @@ bfin port Jie Zhang c6x port Bernd Schmidt cris port Hans-Peter Nilsson -epiphany port Joern Rennecke +epiphany port Joern Rennecke fr30 port Nick Clifton frv port Nick Clifton frv port Alexandre Oliva
Re: ipa-icf::merge TLC
On 3 March 2015 at 13:44, Alex Velenko wrote: > On 02/03/15 22:04, Christophe Lyon wrote: >> >> On 2 March 2015 at 21:21, Jan Hubicka wrote: On 01/03/15 16:47, Christophe Lyon wrote: > > On 27 February 2015 at 21:49, Jan Hubicka wrote: >>> >>> >>> ../sysdeps/gnu/siglist.c:72:1: internal compiler error: in >>> address_matters_p, at symtab.c:1908 >>> versioned_symbol (libc, __new_sys_sigabbrev, sys_sigabbrev, >>> GLIBC_2_3_3); >>> ^ >>> 0x66a080 symtab_node::address_matters_p() >>> /scratch/sellcey/repos/bootstrap/src/gcc/gcc/symtab.c:1908 >>> 0xe7cbe5 ipa_icf::sem_variable::merge(ipa_icf::sem_item*) >>> /scratch/sellcey/repos/bootstrap/src/gcc/gcc/ipa-icf.c:1443 >> >> >> Indeed, the ipa-icf should not try to analyze aliases - just prove >> ekvialence of >> definitions they are attached to. It already does that for functions >> (bit by accident; >> it gives up when there is no gimple body), but it does not do that for >> variables because >> it gets into ctor_for_folding. For that reason it sometimes decides to >> try to make two >> variable aliases alias of each other that is not a good idea, because >> of possible creation >> of loops. >> >> I am just discussing with Martin the fix. >> >> Honza > > > For the record, I have noticed similar errors on ARM and AArch64 > targets, when building glibc. > > Christophe. > I confirm ARM and AArch64 failing to build with this patch: chmod a-w /work/build-aarch64-none-linux-gnu/obj/glibc/stdio-common/errlist-compat.cT 0x6b9100 symtab_node::address_matters_p() /work/src/gcc/gcc/symtab.c:1908 0xedb4e5 ipa_icf::sem_variable::merge(ipa_icf::sem_item*) /work/src/gcc/gcc/ipa-icf.c:1723 0xee03f9 ipa_icf::sem_item_optimizer::merge_classes(unsigned int) /work/src/gcc/gcc/ipa-icf.c:2955 0xee6d31 ipa_icf::sem_item_optimizer::execute() /work/src/gcc/gcc/ipa-icf.c:2217 0xee8df1 ipa_icf_driver /work/src/gcc/gcc/ipa-icf.c:3034 0xee8df1 ipa_icf::pass_ipa_icf::execute(function*) /work/src/gcc/gcc/ipa-icf.c:3081 >>> >>> >>> I commited patch for the alias merging yesterda night, so it should be >>> fixed >>> now. If it still fails, please fill in a PR with preprocessed testcase >>> so I >>> can reproduce it in a cross. >>> >> >> On my side, I saw builds complete again starting with r221090, I guess >> that's the commit you are referring to? > > Hi, > > I built with r221117. I see errors while building following targets: > aarch64_be-none-linux-gnu, aarch64_be-none-linux-gnu, > arm-none-linux-gnueabihf, arm-none-linux-gnueabi. Indeed, it's broken again since r221099. > > For aarch64_be-none-linux-gnu I reproduce the error like this: > > /work/build-aarch64-none-linux-gnu/install//bin/aarch64-none-linux-gnu-gcc > /work/src/glibc/sysdeps/gnu/siglist.c -c -std=gnu99 -fgnu89-inline -O2 > -Wall -Winline -Wundef -Wwrite-strings -fmerge-all-constants -frounding-math > -g -Wstrict-prototypes -fno-toplevel-reorder -fno-section-anchors > -I/work/src/glibc/include > -I/work/build-aarch64-none-linux-gnu/obj/glibc/stdio-common > -I/work/build-aarch64-none-linux-gnu/obj/glibc > -I/work/src/glibc/sysdeps/unix/sysv/linux/aarch64 > -I/work/src/glibc/sysdeps/aarch64/nptl > -I/work/src/glibc/sysdeps/unix/sysv/linux/generic > -I/work/src/glibc/sysdeps/unix/sysv/linux/wordsize-64 > -I/work/src/glibc/sysdeps/unix/sysv/linux/include > -I/work/src/glibc/sysdeps/unix/sysv/linux -I/work/src/glibc/sysdeps/nptl > -I/work/src/glibc/sysdeps/pthread -I/work/src/glibc/sysdeps/gnu > -I/work/src/glibc/sysdeps/unix/inet -I/work/src/glibc/sysdeps/unix/sysv > -I/work/src/glibc/sysdeps/unix -I/work/src/glibc/sysdeps/posix > -I/work/src/glibc/sysdeps/aarch64/fpu -I/work/src/glibc/sysdeps/aarch64 > -I/work/src/glibc/sysdeps/wordsize-64 > -I/work/src/glibc/sysdeps/ieee754/ldbl-128 > -I/work/src/glibc/sysdeps/ieee754/dbl-64/wordsize-64 > -I/work/src/glibc/sysdeps/ieee754/dbl-64 > -I/work/src/glibc/sysdeps/ieee754/flt-32 > -I/work/src/glibc/sysdeps/aarch64/soft-fp -I/work/src/glibc/sysdeps/ieee754 > -I/work/src/glibc/sysdeps/generic -I/work/src/glibc -I/work/src/glibc/libio > -I. -nostdinc -isystem > /work/build-aarch64-none-linux-gnu/install/bin/../lib/gcc/aarch64-none-linux-gnu/5.0.0/include > -isystem > /work/build-aarch64-none-linux-gnu/install/bin/../lib/gcc/aarch64-none-linux-gnu/5.0.0/include-fixed > -isystem > /work/build-aarch64-none-linux-gnu/install//aarch64-none-linux-gnu/libc/usr/include > -D_LIBC_REENTRANT -include > /work/build-aarch64-none-linux-gnu/obj/glibc/libc-modules.h > -DMODULE_NAME=libc -include /work/src/glibc/include/libc-symbols.h > -D_IO_MTSAFE_IO -o > /work/build-aarch64-none-linux-gnu/obj/glibc/stdio-common/siglist.o -MD -MP > -MF /work/build-aarch64-none-linux-gnu/obj/glibc/stdio-com
Re: [PATCH] Turn RETURN_ADDR_IN_PREVIOUS_FRAME into C expression
On Tue, Mar 3, 2015 at 5:51 PM, Richard Henderson wrote: > On 03/02/2015 10:42 PM, Max Filippov wrote: >> gcc/ >> * builtins.c (expand_builtin_return_addr): Add >> RETURN_ADDR_IN_PREVIOUS_FRAME to 'if' condition, remove >> surrounding #ifdef. >> * config/sparc/sparc.h (RETURN_ADDR_IN_PREVIOUS_FRAME): Change >> definition to 1. >> * config/xtensa/xtensa.h (RETURN_ADDR_IN_PREVIOUS_FRAME): >> Likewise. >> * defaults.h (RETURN_ADDR_IN_PREVIOUS_FRAME): Define to 0 if >> undefined. >> doc/tm.texi.in (RETURN_ADDR_IN_PREVIOUS_FRAME): Update >> paragraph. > > Ok. Applied to trunk. Thanks! -- Max
Re: [PATCH] Turn RETURN_ADDR_IN_PREVIOUS_FRAME into C expression
On 03/02/2015 10:42 PM, Max Filippov wrote: > gcc/ > * builtins.c (expand_builtin_return_addr): Add > RETURN_ADDR_IN_PREVIOUS_FRAME to 'if' condition, remove > surrounding #ifdef. > * config/sparc/sparc.h (RETURN_ADDR_IN_PREVIOUS_FRAME): Change > definition to 1. > * config/xtensa/xtensa.h (RETURN_ADDR_IN_PREVIOUS_FRAME): > Likewise. > * defaults.h (RETURN_ADDR_IN_PREVIOUS_FRAME): Define to 0 if > undefined. > doc/tm.texi.in (RETURN_ADDR_IN_PREVIOUS_FRAME): Update > paragraph. Ok. r~
Re: [PATCH] PR target/65248: [5 Regression] Copy relocation in PIE against protected symbol
On Tue, Mar 3, 2015 at 12:12 AM, Alan Modra wrote: > On Mon, Mar 02, 2015 at 05:36:24AM -0800, H.J. Lu wrote: >> On Sun, Mar 1, 2015 at 11:48 PM, Uros Bizjak wrote: >> > On Sat, Feb 28, 2015 at 5:42 PM, H.J. Lu wrote: >> >> Ue copy relocation in PIE improves performance. But copy relocation >> >> can't be used to access protected symbols defined in shared libaries >> >> and linker in binutils 2.26 enforces doesn't allow it. GCC doesn't >> >> know if an external definition is protected or not. This option adds >> >> -mcopyreloc-in-pie to give user an option to turn it off to avoid problem >> >> at link-time. OK for trunk? >> > >> > If the option does not work universally for all cases, then the >> > default should be off. >> >> This optimization isn't the real issue. The issue here is protected >> symbol in shared library. It can never be referenced from a normal >> executable and works correctly, as Alan explained. It doesn't matter >> if this option is off or not since it only applies to PIE. You can try >> the testcase in PR 65248 without -fPIE -pie. > > I see things differently. We have an old linker hack to avoid dynamic > text relocations in non-PIC executables. This hack doesn't work > properly with protected visibility variables in shared libraries. > Rather than blaming protected visibility variables, I say the hack is > broken. > > Since you rely on the linker hack for your optimization, you've > extended the problem from non-PIC executables to PIEs.. > To make it clear, protected data symbols defined in shared library can never be accessed from normal executables on x86-64 since R_X86_64_PC32 relocation is used to reach externally defined symbols in small and medium models and it will overflow at run-time. On x86-64, R_X86_64_COPY relocation is required to access externally defined data symbols in normal executables unless small and medium models are removed from x86-64 psABI. For x86-64, protected data symbols are impossible. -- H.J.
Re: [PATCH, alpha]: Fix PR/47230 [4.6/4.7 Regression] gcc fails to bootstrap on alpha in stage2 with "relocation truncated to fit: GPREL16 against ..."
On Mon, Mar 2, 2015 at 7:23 PM, Richard Henderson wrote: >> Unfortunately, while "normal" bootstrap works OK with alpha-linux-gnu >> and alphaev68-linux-gnu, the bootstrap still fails when configured >> --with-build-config=bootstrap-lto: >> >> libbackend.a(tree-data-ref.o): In function `non_affine_dependence_relation': >> /space/uros/gcc-build-profiled/gcc/../../gcc-svn/trunk/gcc/tree-data-ref.c:1661:(.text+0x1b8): >> relocation truncated to fit: GPREL16 against symbol `dump_file' >> defined in .sbss section in libbackend.a(dumpfile.o) > > Interesting. And using bootstrap-lto works with --no-relax? I don't believe > I've ever tried it... Yes, I can re-confirm, that Rev: 221041 can bootstrap with -Wl,--no-relax patch on alphaev68-linux-gnu, when configured with "--with-build-config=bootstrap-lto --disable-werror --enable-languages=c,c++,fortran" with binutils 2.25. I will post testresults when bootstrap+regression test finish. Uros.
Re: [Ada] convert GNAT doc to sphinx
As discussed last year, we've converted the GNAT main documentation (gnat_rm.texi and gnat_ugn.texi) to reST/sphinx, so the master doc can now be found under gcc/ada/doc. there is an empty directory left in SVN: gcc/ada/doc/share/_static ok to remove? No, this (empty currently) directory is needed to run sphinx. Feel free to e.g. add a .cvsignore or .gitignore file if it can help. Arno
Re: [patch,avr]: Fix various problems with specs and specs file generation.
On Mon, Mar 02, 2015 at 08:40:17PM +0100, Georg-Johann Lay wrote:
> The new specs file generation introduces several problems. This patch
>
> - Fix build warnings
>
> - Clean up unused code and the old, now dead specs definitions.
>
> - Removes unused files and adjust build scripts / rules.
>
> - Issues with avr-libc awareness:
>
> -- Makes specs-generation aware of avr-libc (include tm.h in build script
> and depend on WITH_AVRLIBC).
>
> -- avr-libc implements functions in libm.a which usually live in libgcc,
> hence add -lm to libgcc_spec, cf. PR54461.
>
> -- The new libdev.a is a feature of avr-libc and not available with, e.g.,
> newlib. Hence remove it from lib_spec if the compiler is not configured for
> avr-libc (--with-avrlibc=no).
>
> - Many minor issues with option propagation.
>
> - -march had been added to multilib generation some time ago, but
> driver_self_spec was not aware of that option.
>
>
> Ok for trunk?
>
>
> BTW, anyone knows what -march= is good for? It allows all kinds of silly
> option combinations like "-march=avrtiny -mmcu=atmega8" without any
> complaints.
IIRC, -march was added because replacing -mmcu= to
-mmcu= in the driver's self specs broke multilib selection - the
driver always acted as if no -mmcu was specified. Adding
a new option (-march), translating mmcu= to march= and then
basing t-multilib on that worked ok.
>
> What's wrong with -mmcu=avr* ? All architecture names start with "avr", and
> /no/ device name starts /with/ "avr", hence -mmcu= should be fine and work
> as smooth as in the last 10 years.
>
> Why that -march= option? If there is not a good reason for -march=, I'd
> propose to clean it up and use -mmcu=avr* instead.
>
>
> Johann
>
>
> gcc/
> Fix various problems with specs file generation.
>
> * config.gcc (extra_gcc_objs) [avr]: Remove.
>
> * config/avr/driver-avr.c: Remove file.
> * config/avr/t-avr (driver-avr.o): Remove rule.
> (gen-avr-mmcu-specs): Use CXX_FOR_BUILD, CXXFLAGS_FOR_BUILD and
> INCLUDES to build. Depend on TM_H.
> * config/avr/gen-avr-mmcu-specs.c: Tidy up code. Fix various
> build warnings. Fix non-matching types and non-existing %-codes.
> (tm.h): Include.
> (*lib) [!WITH_AVRLIBC]: Don't link libdev.a.
> (*libgcc) [WITH_AVRLIBC]: Add "-lm".
> * config/avr/avrlibc.h (LIBGCC_SPEC): Remove definition.
> * config/avr/avr.h (DRIVER_SELF_SPECS): Fix handling of -march=.
> (CPP_SPEC, CC1PLUS_SPEC, ASM_SPEC, LINK_SPEC, LIB_SPEC)
> (LIBGCC_SPEC): Remove definitions.
>
> Index: config.gcc
> ===
> --- config.gcc(revision 220854)
> +++ config.gcc(working copy)
> @@ -1103,7 +1103,6 @@ avr-*-*)
> fi
> tmake_file="${tmake_file} avr/t-avr avr/t-multilib"
> use_gcc_stdint=wrap
> - extra_gcc_objs="driver-avr.o avr-devices.o"
> extra_objs="avr-devices.o avr-log.o"
> ;;
> bfin*-elf*)
> Index: config/avr/t-avr
> ===
> --- config/avr/t-avr (revision 221028)
> +++ config/avr/t-avr (working copy)
> @@ -16,10 +16,6 @@
> # along with GCC; see the file COPYING3. If not see
> #
Re: ipa-icf::merge TLC
On 02/03/15 22:04, Christophe Lyon wrote: On 2 March 2015 at 21:21, Jan Hubicka wrote: On 01/03/15 16:47, Christophe Lyon wrote: On 27 February 2015 at 21:49, Jan Hubicka wrote: ../sysdeps/gnu/siglist.c:72:1: internal compiler error: in address_matters_p, at symtab.c:1908 versioned_symbol (libc, __new_sys_sigabbrev, sys_sigabbrev, GLIBC_2_3_3); ^ 0x66a080 symtab_node::address_matters_p() /scratch/sellcey/repos/bootstrap/src/gcc/gcc/symtab.c:1908 0xe7cbe5 ipa_icf::sem_variable::merge(ipa_icf::sem_item*) /scratch/sellcey/repos/bootstrap/src/gcc/gcc/ipa-icf.c:1443 Indeed, the ipa-icf should not try to analyze aliases - just prove ekvialence of definitions they are attached to. It already does that for functions (bit by accident; it gives up when there is no gimple body), but it does not do that for variables because it gets into ctor_for_folding. For that reason it sometimes decides to try to make two variable aliases alias of each other that is not a good idea, because of possible creation of loops. I am just discussing with Martin the fix. Honza For the record, I have noticed similar errors on ARM and AArch64 targets, when building glibc. Christophe. I confirm ARM and AArch64 failing to build with this patch: chmod a-w /work/build-aarch64-none-linux-gnu/obj/glibc/stdio-common/errlist-compat.cT 0x6b9100 symtab_node::address_matters_p() /work/src/gcc/gcc/symtab.c:1908 0xedb4e5 ipa_icf::sem_variable::merge(ipa_icf::sem_item*) /work/src/gcc/gcc/ipa-icf.c:1723 0xee03f9 ipa_icf::sem_item_optimizer::merge_classes(unsigned int) /work/src/gcc/gcc/ipa-icf.c:2955 0xee6d31 ipa_icf::sem_item_optimizer::execute() /work/src/gcc/gcc/ipa-icf.c:2217 0xee8df1 ipa_icf_driver /work/src/gcc/gcc/ipa-icf.c:3034 0xee8df1 ipa_icf::pass_ipa_icf::execute(function*) /work/src/gcc/gcc/ipa-icf.c:3081 I commited patch for the alias merging yesterda night, so it should be fixed now. If it still fails, please fill in a PR with preprocessed testcase so I can reproduce it in a cross. On my side, I saw builds complete again starting with r221090, I guess that's the commit you are referring to? Hi, I built with r221117. I see errors while building following targets: aarch64_be-none-linux-gnu, aarch64_be-none-linux-gnu, arm-none-linux-gnueabihf, arm-none-linux-gnueabi. For aarch64_be-none-linux-gnu I reproduce the error like this: /work/build-aarch64-none-linux-gnu/install//bin/aarch64-none-linux-gnu-gcc /work/src/glibc/sysdeps/gnu/siglist.c -c -std=gnu99 -fgnu89-inline -O2 -Wall -Winline -Wundef -Wwrite-strings -fmerge-all-constants -frounding-math -g -Wstrict-prototypes -fno-toplevel-reorder -fno-section-anchors -I/work/src/glibc/include -I/work/build-aarch64-none-linux-gnu/obj/glibc/stdio-common -I/work/build-aarch64-none-linux-gnu/obj/glibc -I/work/src/glibc/sysdeps/unix/sysv/linux/aarch64 -I/work/src/glibc/sysdeps/aarch64/nptl -I/work/src/glibc/sysdeps/unix/sysv/linux/generic -I/work/src/glibc/sysdeps/unix/sysv/linux/wordsize-64 -I/work/src/glibc/sysdeps/unix/sysv/linux/include -I/work/src/glibc/sysdeps/unix/sysv/linux -I/work/src/glibc/sysdeps/nptl -I/work/src/glibc/sysdeps/pthread -I/work/src/glibc/sysdeps/gnu -I/work/src/glibc/sysdeps/unix/inet -I/work/src/glibc/sysdeps/unix/sysv -I/work/src/glibc/sysdeps/unix -I/work/src/glibc/sysdeps/posix -I/work/src/glibc/sysdeps/aarch64/fpu -I/work/src/glibc/sysdeps/aarch64 -I/work/src/glibc/sysdeps/wordsize-64 -I/work/src/glibc/sysdeps/ieee754/ldbl-128 -I/work/src/glibc/sysdeps/ieee754/dbl-64/wordsize-64 -I/work/src/glibc/sysdeps/ieee754/dbl-64 -I/work/src/glibc/sysdeps/ieee754/flt-32 -I/work/src/glibc/sysdeps/aarch64/soft-fp -I/work/src/glibc/sysdeps/ieee754 -I/work/src/glibc/sysdeps/generic -I/work/src/glibc -I/work/src/glibc/libio -I. -nostdinc -isystem /work/build-aarch64-none-linux-gnu/install/bin/../lib/gcc/aarch64-none-linux-gnu/5.0.0/include -isystem /work/build-aarch64-none-linux-gnu/install/bin/../lib/gcc/aarch64-none-linux-gnu/5.0.0/include-fixed -isystem /work/build-aarch64-none-linux-gnu/install//aarch64-none-linux-gnu/libc/usr/include -D_LIBC_REENTRANT -include /work/build-aarch64-none-linux-gnu/obj/glibc/libc-modules.h -DMODULE_NAME=libc -include /work/src/glibc/include/libc-symbols.h -D_IO_MTSAFE_IO -o /work/build-aarch64-none-linux-gnu/obj/glibc/stdio-common/siglist.o -MD -MP -MF /work/build-aarch64-none-linux-gnu/obj/glibc/stdio-common/siglist.o.dt -MT /work/build-aarch64-none-linux-gnu/obj/glibc/stdio-common/siglist.o /work/src/glibc/sysdeps/gnu/siglist.c:77:1: internal compiler error: in address_matters_p, at symtab.c:1908 versioned_symbol (libc, __new_sys_sigabbrev, sys_sigabbrev, GLIBC_2_1); ^ 0x6b9140 symtab_node::address_matters_p() /work/src/gcc/gcc/symtab.c:1908 0xedb685 ipa_icf::sem_variable::merge(ipa_icf::sem_item*) /work/src/gcc/gcc/ipa-icf.c:1740 0xee05b1 ipa_icf::sem_item_optimizer::merge_class
[PATCH] [PR tree-optimization/65241] Do not modify DOM's hash table if ! inserting
As outlined in the PR, a relatively recent change to DOM unconditionally
modifies the available expression hash table after a partial hit, but a
failure by the alias walker to find an available expression.
This interacts badly with jump threading which modifies gimple
statements in-place, tries to look them up in the hash table (without
changing the state of the hash table), then restores the statements to
their original state.
This patch makes the code which updates the hash table in
lookup_avail_expr only do so if INSERT is true.
Bootstrapped and regression tested on x86_64-unknown-linux-gnu. Applied
on the trunk.
Jeff
commit 99dddeb179c56e8876f6d266829db394c950e2ee
Author: Jeff Law
Date: Tue Mar 3 04:51:50 2015 -0700
PR tree-optimization/65241
* tree-ssa-dom.c (lookup_avail_expr): Only modify the avail_expr
hash table if INSERT is true.
PR tree-optimization/65241
* gcc.c-torture/compile/pr65241.c: New test.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 55c106c..cb42917 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2015-03-23 Jeff Law
+
+ PR tree-optimization/65241
+ * tree-ssa-dom.c (lookup_avail_expr): Only modify the avail_expr
+ hash table if INSERT is true.
+
2015-03-03 Georg-Johann Lay
PR target/65296
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ecc4cc4..824d256 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-03-13 Jeff Law
+
+ PR tree-optimization/65241
+ * gcc.c-torture/compile/pr65241.c: New test.
+
2015-03-03 Georg-Johann Lay
PR target/64331
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr65241.c
b/gcc/testsuite/gcc.c-torture/compile/pr65241.c
new file mode 100644
index 000..dd76ac5
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr65241.c
@@ -0,0 +1,26 @@
+enum E { A, B, C, D };
+void fn4 (void);
+
+int
+fn1 (enum E p1)
+{
+ static int w[D];
+ if (w[p1])
+switch (p1)
+ case C:
+ w[p1] = 0;
+}
+
+void
+fn2 (p1)
+{
+ fn1 (p1);
+}
+
+void
+fn3 (enum E p1)
+{
+ fn2 (p1);
+ fn4 ();
+ fn2 (p1);
+}
diff --git a/gcc/tree-ssa-dom.c b/gcc/tree-ssa-dom.c
index 096e471..d230ce1 100644
--- a/gcc/tree-ssa-dom.c
+++ b/gcc/tree-ssa-dom.c
@@ -2649,19 +2649,22 @@ lookup_avail_expr (gimple stmt, bool insert)
&& walk_non_aliased_vuses (&ref, vuse2,
vuse_eq, NULL, NULL, vuse1) != NULL))
{
- struct expr_hash_elt *element2 = XNEW (struct expr_hash_elt);
- *element2 = element;
- element2->stamp = element2;
-
- /* Insert the expr into the hash by replacing the current
-entry and recording the value to restore in the
-aval_exprs_stack. */
- avail_exprs_stack.safe_push (std::make_pair (element2, *slot));
- *slot = element2;
- if (dump_file && (dump_flags & TDF_DETAILS))
+ if (insert)
{
- fprintf (dump_file, "2>>> ");
- print_expr_hash_elt (dump_file, *slot);
+ struct expr_hash_elt *element2 = XNEW (struct expr_hash_elt);
+ *element2 = element;
+ element2->stamp = element2;
+
+ /* Insert the expr into the hash by replacing the current
+entry and recording the value to restore in the
+avail_exprs_stack. */
+ avail_exprs_stack.safe_push (std::make_pair (element2, *slot));
+ *slot = element2;
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ {
+ fprintf (dump_file, "2>>> ");
+ print_expr_hash_elt (dump_file, *slot);
+ }
}
return NULL_TREE;
}
Re: [PATCH] Fix PR ipa/65282
On Tue, Mar 3, 2015 at 11:40 AM, Martin Liška wrote: > Hello. > > There's suggested patch for the issue, where regression test have been > running on x86_64-linux-pc. > > Ready for trunk after tests will be finished? Ok. Thanks, Richard. > Thanks, > Martin
Re: [Ada] convert GNAT doc to sphinx
On 02/20/2015 10:17 AM, Arnaud Charlet wrote: > As discussed last year, we've converted the GNAT main documentation > (gnat_rm.texi and gnat_ugn.texi) to reST/sphinx, so the master doc > can now be found under gcc/ada/doc. there is an empty directory left in SVN: gcc/ada/doc/share/_static ok to remove? Matthias
[PATCH] Fix PR ipa/65282
Hello.
There's suggested patch for the issue, where regression test have been running
on x86_64-linux-pc.
Ready for trunk after tests will be finished?
Thanks,
Martin
>From a186fc97c5f192b94cc571f611a50eb0f4f8a354 Mon Sep 17 00:00:00 2001
From: mliska
Date: Tue, 3 Mar 2015 11:33:30 +0100
Subject: [PATCH] Fix PR ipa/65282.
gcc/testsuite/ChangeLog:
2015-03-03 Martin Liska
* gcc.dg/ipa/PR65282.c: New test.
gcc/ChangeLog:
2015-03-03 Martin Liska
PR ipa/65282
* ipa-icf.c (sem_variable::equals): Fix wrong condition.
---
gcc/ipa-icf.c | 2 +-
gcc/testsuite/gcc.dg/ipa/PR65282.c | 20
2 files changed, 21 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.dg/ipa/PR65282.c
diff --git a/gcc/ipa-icf.c b/gcc/ipa-icf.c
index 14ccea5..08ee979 100644
--- a/gcc/ipa-icf.c
+++ b/gcc/ipa-icf.c
@@ -1638,7 +1638,7 @@ sem_variable::equals (tree t1, tree t2)
tree y1 = TREE_OPERAND (t1, 1);
tree y2 = TREE_OPERAND (t2, 1);
- if (!sem_variable::equals (x1, x2) && sem_variable::equals (y1, y2))
+ if (!sem_variable::equals (x1, x2) || !sem_variable::equals (y1, y2))
return false;
if (!sem_variable::equals (array_ref_low_bound (t1),
array_ref_low_bound (t2)))
diff --git a/gcc/testsuite/gcc.dg/ipa/PR65282.c b/gcc/testsuite/gcc.dg/ipa/PR65282.c
new file mode 100644
index 000..58e1c55
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/ipa/PR65282.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -fdump-ipa-icf" } */
+
+int a[2];
+static int *b = &a[0], *c = &a[1];
+
+int
+main ()
+{
+ *c = 1;
+ *b = 0;
+
+ if (a[1] != 1)
+__builtin_abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-ipa-dump "Equal symbols: 0" "icf" } } */
+/* { dg-final { cleanup-ipa-dump "icf" } } */
--
2.1.2
[PATCH] Fix PR ipa/65287
Hello.
There's suggested patch for the issue that survives regression tests on
x86_64-linux-pc.
Ready for trunk?
Thanks,
Martin
>From d4e9d2906a90151d1239e7b32b00f7cb46b045fa Mon Sep 17 00:00:00 2001
From: mliska
Date: Tue, 3 Mar 2015 10:36:59 +0100
Subject: [PATCH] Fix PR ipa/65287.
gcc/testsuite/ChangeLog:
2015-03-03 Martin Liska
* gcc.dg/ipa/pr65287.c: New test.
gcc/ChangeLog:
2015-03-03 Martin Liska
PR ipa/65287
* ipa-icf.c (sem_variable::parse): Skip all alias variables.
---
gcc/ipa-icf.c | 3 ++-
gcc/testsuite/gcc.dg/ipa/pr65287.c | 14 ++
2 files changed, 16 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.dg/ipa/pr65287.c
diff --git a/gcc/ipa-icf.c b/gcc/ipa-icf.c
index 155b96b..14ccea5 100644
--- a/gcc/ipa-icf.c
+++ b/gcc/ipa-icf.c
@@ -1681,7 +1681,8 @@ sem_variable::equals (tree t1, tree t2)
sem_variable *
sem_variable::parse (varpool_node *node, bitmap_obstack *stack)
{
- if (TREE_THIS_VOLATILE (node->decl) || DECL_HARD_REGISTER (node->decl))
+ if (TREE_THIS_VOLATILE (node->decl) || DECL_HARD_REGISTER (node->decl)
+ || node->alias)
return NULL;
sem_variable *v = new sem_variable (node, 0, stack);
diff --git a/gcc/testsuite/gcc.dg/ipa/pr65287.c b/gcc/testsuite/gcc.dg/ipa/pr65287.c
new file mode 100644
index 000..9292984
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/ipa/pr65287.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+const int __new_sys_siglist[] = {};
+
+extern __typeof(__new_sys_siglist) _new_sys_siglist
+__attribute__((alias("__new_sys_siglist")));
+extern __typeof(__new_sys_siglist) _sys_siglist
+__attribute__((alias("__new_sys_siglist")));
+
+int main()
+{
+ return 0;
+}
--
2.1.2
Re: [PATCH] Fix PR ipa/65087
On 03/03/2015 10:50 AM, Marek Polacek wrote: On Tue, Mar 03, 2015 at 10:31:17AM +0100, Martin Liška wrote: @@ -2952,9 +2959,12 @@ sem_item_optimizer::merge_classes (unsigned int prev_class_count) alias->dump_to_file (dump_file); } - source->merge (alias); + if (source->merge (alias)) + merged_p = true; I thinks it's better to write this as merged_p |= source->merge (alias); Marek Good point, I hope following patch can be installed as obvious. Martin >From d8c3312e36813dd6ccd02567e5effc0dc44bb212 Mon Sep 17 00:00:00 2001 From: mliska Date: Tue, 3 Mar 2015 11:03:35 +0100 Subject: [PATCH] ICF: Use bit or instead of if branch. gcc/ChangeLog: 2015-03-03 Martin Liska * ipa-icf.c (sem_item_optimizer::merge_classes): Use bit or instead of if branch. --- gcc/ipa-icf.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/gcc/ipa-icf.c b/gcc/ipa-icf.c index 9cdd73e..41c2304 100644 --- a/gcc/ipa-icf.c +++ b/gcc/ipa-icf.c @@ -2959,8 +2959,7 @@ sem_item_optimizer::merge_classes (unsigned int prev_class_count) alias->dump_to_file (dump_file); } - if (source->merge (alias)) - merged_p = true; + merged_p |= source->merge (alias); } } -- 2.1.2
Re: [PATCH] Fix PR ipa/65087
On Tue, Mar 03, 2015 at 10:31:17AM +0100, Martin Liška wrote: > @@ -2952,9 +2959,12 @@ sem_item_optimizer::merge_classes (unsigned int > prev_class_count) > alias->dump_to_file (dump_file); > } > > - source->merge (alias); > + if (source->merge (alias)) > + merged_p = true; I thinks it's better to write this as merged_p |= source->merge (alias); Marek
Re: [IA-64] Fix gcc.dg/torture/vshuf-v8qi.c
On Tue, Mar 3, 2015 at 9:56 AM, Eric Botcazou wrote: > Hi, > > the test fails at -O2 because of the assertion recently added to gen_reg_rtx > that crtl->emit.regno_pointer_align_length is non-zero. Now the function > expand_vec_perm_interleave_2 can be invoked at the GIMPLE level in "testing" > mode and crtl->emit is not initialized by that time. > > Tested on ia64-linux-gnu, OK for mainline and 4.9 branch? Ok. Thanks, Richard. > > 2015-03-03 Eric Botcazou > > * config/ia64/ia64.c (expand_vec_perm_interleave_2): Use gen_raw_REG > to create a register in testing mode. > > > -- > Eric Botcazou
RE: [PATCH, ARM] Fix PR64453: live high register not saved in function prolog with -Os
And I forgot to update the date in the rush so I committed the fix as obvious: diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ed8ca31..809f5cf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,4 @@ -2015-01-23 Thomas Preud'homme +2015-03-03 Thomas Preud'homme Backport from mainline 2015-01-14 Thomas Preud'homme diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 40b2ac5..bb5d545 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,4 +1,4 @@ -2015-01-23 Thomas Preud'homme +2015-03-03 Thomas Preud'homme Backport from mainline 2015-01-14 Thomas Preud'homme Sorry for the mistake. Best regards, Thomas > -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme > Sent: Tuesday, March 03, 2015 5:35 PM > To: Ramana Radhakrishnan > Cc: gcc-patches; Richard Biener; Jakub Jelinek > Subject: RE: [PATCH, ARM] Fix PR64453: live high register not saved in > function prolog with -Os > > Just committed to 4.9 branch, 4.8 to follow once regression testsuite for > 4.8 backport finishes running (backport was done quite some time ago > now). > > Best regards, > > Thomas > > > -Original Message- > > From: Ramana Radhakrishnan [mailto:ramana@googlemail.com] > > Sent: Tuesday, February 17, 2015 4:07 PM > > To: Thomas Preud'homme > > Cc: Ramana Radhakrishnan; gcc-patches; Richard Biener; Jakub Jelinek > > Subject: Re: [PATCH, ARM] Fix PR64453: live high register not saved in > > function prolog with -Os > > > > On Fri, Jan 23, 2015 at 8:23 AM, Thomas Preud'homme > > wrote: > > > Hi Ramana, > > > > > >> From: Ramana Radhakrishnan [mailto:ramana@googlemail.com] > > >> Sent: Wednesday, January 14, 2015 7:21 PM > > >> On Wed, Jan 14, 2015 at 10:20 AM, Thomas Preud'homme > > >> wrote: > > >> > When compiling for size, live high registers are not saved in > function > > >> prolog in ARM backend in Thumb mode. The problem comes from > > >> arm_conditional_register_usage setting call_used_regs for all high > > >> register to avoid them being allocated. However, this cause prolog > to > > not > > >> save these register even if they are used. This patch marks high > > registers > > >> as really needing to be saved in prolog if live, no matter what is the > > >> content of call_used_regs. > > >> > > > >> > ChangeLog entries are as follows: > > >> > > > >> > gcc/ChangeLog > > >> > > > >> > 2015-01-12 Thomas Preud'homme > thomas.preudho...@arm.com > > >> > > > >> > PR target/64453 > > >> > * config/arm/arm.c (callee_saved_reg_p): Define. > > >> > (arm_compute_save_reg0_reg12_mask): Use > > callee_saved_reg_p > > >> to check if > > >> > register is callee saved instead of !call_used_regs[reg]. > > >> > (thumb1_compute_save_reg_mask): Likewise. > > >> > > > >> > > > >> > gcc/testsuite/ChangeLog > > >> > > > >> > 2014-12-31 Thomas Preud'homme > thomas.preudho...@arm.com > > >> > > > >> > * gcc.target/arm/pr64453.c: New. > > >> > > > >> > > > >> > > > >> > > >> OK. > > >> > > >> Ramana > > > > > > The patch applies cleanly on GCC 4.8 and 4.9 branches when omitting > > the cosmetic change > > > in arm_conditional_register_usage () which was unintended. I > > compiled an arm-none-eabi > > > GCC cross compiler and ran the testsuite for both backport without > any > > regression. > > > > > > Is this ok for the 4.8 and 4.9 branches? > > > > > > > OK for the branches if no RM objects in 24 hours. > > > > Ramana > > > > > Best regards, > > > > > > Thomas > > > > > > > > > > > > >
RE: [Patch, MIPS] Fix PR 58158 - ICE on MIPS Loongson
Steve Ellcey writes: > On Mon, 2015-03-02 at 15:54 -0800, Matthew Fortune wrote: > > Thanks for looking through and catching this. > > > > I had conflicting thoughts on whether the new condition should > > reference both !ISA_HAS_FP_CONDMOVE || ISA_HAS_SEL but if we take it > > that FP_CONDMOVE is the only way to get an integer conditional move > > based on an FP condition then that's fine. > > > > > 2015-03-02 Steve Ellcey > > > > > > PR target/58158 > > > * config/mips/mips.md (movcc): Change ISA_HAS_SEL check to > > > !ISA_HAS_FP_CONDMOVE. > > > > OK. > > > > Are you planning on doing any backports of this patch to release > > branches? > > > > Thanks, > > Matthew > > Given that it is very small and safe I think backporting it would make > sense. I will check it in on the main line today and if there are no > problems after a few days I could check it in on the 4.8 and 4.9 > branches if that sounds good to you. Sounds good. Thanks, Matthew
RE: [PATCH, ARM] Fix PR64453: live high register not saved in function prolog with -Os
Just committed to 4.9 branch, 4.8 to follow once regression testsuite for 4.8 backport finishes running (backport was done quite some time ago now). Best regards, Thomas > -Original Message- > From: Ramana Radhakrishnan [mailto:ramana@googlemail.com] > Sent: Tuesday, February 17, 2015 4:07 PM > To: Thomas Preud'homme > Cc: Ramana Radhakrishnan; gcc-patches; Richard Biener; Jakub Jelinek > Subject: Re: [PATCH, ARM] Fix PR64453: live high register not saved in > function prolog with -Os > > On Fri, Jan 23, 2015 at 8:23 AM, Thomas Preud'homme > wrote: > > Hi Ramana, > > > >> From: Ramana Radhakrishnan [mailto:ramana@googlemail.com] > >> Sent: Wednesday, January 14, 2015 7:21 PM > >> On Wed, Jan 14, 2015 at 10:20 AM, Thomas Preud'homme > >> wrote: > >> > When compiling for size, live high registers are not saved in function > >> prolog in ARM backend in Thumb mode. The problem comes from > >> arm_conditional_register_usage setting call_used_regs for all high > >> register to avoid them being allocated. However, this cause prolog to > not > >> save these register even if they are used. This patch marks high > registers > >> as really needing to be saved in prolog if live, no matter what is the > >> content of call_used_regs. > >> > > >> > ChangeLog entries are as follows: > >> > > >> > gcc/ChangeLog > >> > > >> > 2015-01-12 Thomas Preud'homme thomas.preudho...@arm.com > >> > > >> > PR target/64453 > >> > * config/arm/arm.c (callee_saved_reg_p): Define. > >> > (arm_compute_save_reg0_reg12_mask): Use > callee_saved_reg_p > >> to check if > >> > register is callee saved instead of !call_used_regs[reg]. > >> > (thumb1_compute_save_reg_mask): Likewise. > >> > > >> > > >> > gcc/testsuite/ChangeLog > >> > > >> > 2014-12-31 Thomas Preud'homme thomas.preudho...@arm.com > >> > > >> > * gcc.target/arm/pr64453.c: New. > >> > > >> > > >> > > >> > >> OK. > >> > >> Ramana > > > > The patch applies cleanly on GCC 4.8 and 4.9 branches when omitting > the cosmetic change > > in arm_conditional_register_usage () which was unintended. I > compiled an arm-none-eabi > > GCC cross compiler and ran the testsuite for both backport without any > regression. > > > > Is this ok for the 4.8 and 4.9 branches? > > > > OK for the branches if no RM objects in 24 hours. > > Ramana > > > Best regards, > > > > Thomas > > > > > >
Re: [PATCH] Fix PR ipa/65087
On 03/02/2015 06:20 PM, Jan Hubicka wrote:
Hello.
Following one line patch is fix for PR ipa/65087. No regression has been
seen on x86_64-linux-pc.
OK, it won't happend large programs, but can you arrange its execute method to
return TODO_remove_functions only if some merging actually happened?
Patch is preapproved with this change.
Honza
Yes.
Attached patch is the one I've just installed, where TODO_remove_functions is
returned
just for cases where we merge an item.
Thanks,
Martin
Ready for trunk?
Thanks,
Martin
>From f39be56c66387c698546c498550d38512ddeb477 Mon Sep 17 00:00:00 2001
From: mliska
Date: Mon, 2 Mar 2015 16:56:42 +0100
Subject: [PATCH] Fix PR ipa/65087.
gcc/ChangeLog:
2015-03-02 Martin Liska
Martin Jambor
PR ipa/65087
* ipa-icf.c: Add TODO_remove_functions to the IPA pass.
---
gcc/ipa-icf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/ipa-icf.c b/gcc/ipa-icf.c
index 31fcbec..56f59a9 100644
--- a/gcc/ipa-icf.c
+++ b/gcc/ipa-icf.c
@@ -3049,7 +3049,7 @@ const pass_data pass_data_ipa_icf =
0,/* properties_provided */
0,/* properties_destroyed */
0,/* todo_flags_start */
- 0,/* todo_flags_finish */
+ TODO_remove_functions,/* todo_flags_finish */
};
class pass_ipa_icf : public ipa_opt_pass_d
--
2.1.2
>From 3a3bc6bda4ab1c47e8fa74e9a46cbd7abe612cc1 Mon Sep 17 00:00:00 2001
From: mliska
Date: Mon, 2 Mar 2015 16:56:42 +0100
Subject: [PATCH] Fix PR ipa/65087.
gcc/ChangeLog:
2015-03-02 Martin Liska
Martin Jambor
PR ipa/65087
* ipa-icf.c (sem_item_optimizer::execute): Change function
return value to boolean.
(sem_item_optimizer::merge_classes): Likewise.
(ipa_icf_driver): Return TODO_remove_functions in case there's
a merge operation processed.
* ipa-icf.h: Change function return value to boolean.
---
gcc/ipa-icf.c | 26 ++
gcc/ipa-icf.h | 11 +++
2 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/gcc/ipa-icf.c b/gcc/ipa-icf.c
index 31fcbec..9cdd73e 100644
--- a/gcc/ipa-icf.c
+++ b/gcc/ipa-icf.c
@@ -2167,9 +2167,11 @@ sem_item_optimizer::filter_removed_items (void)
m_items.safe_push (filtered[i]);
}
-/* Optimizer entry point. */
+/* Optimizer entry point which returns true in case it processes
+ a merge operation. True is returned if there's a merge operation
+ processed. */
-void
+bool
sem_item_optimizer::execute (void)
{
filter_removed_items ();
@@ -2214,10 +2216,12 @@ sem_item_optimizer::execute (void)
process_cong_reduction ();
dump_cong_classes ();
verify_classes ();
- merge_classes (prev_class_count);
+ bool merged_p = merge_classes (prev_class_count);
if (dump_file && (dump_flags & TDF_DETAILS))
symtab_node::dump_table (dump_file);
+
+ return merged_p;
}
/* Function responsible for visiting all potential functions and
@@ -2870,9 +2874,10 @@ sem_item_optimizer::dump_cong_classes (void)
/* After reduction is done, we can declare all items in a group
to be equal. PREV_CLASS_COUNT is start number of classes
- before reduction. */
+ before reduction. True is returned if there's a merge operation
+ processed. */
-void
+bool
sem_item_optimizer::merge_classes (unsigned int prev_class_count)
{
unsigned int item_count = m_items.length ();
@@ -2882,6 +2887,8 @@ sem_item_optimizer::merge_classes (unsigned int prev_class_count)
unsigned int non_singular_classes_count = 0;
unsigned int non_singular_classes_sum = 0;
+ bool merged_p = false;
+
for (hash_table::iterator it = m_classes.begin ();
it != m_classes.end (); ++it)
for (unsigned int i = 0; i < (*it)->classes.length (); i++)
@@ -2952,9 +2959,12 @@ sem_item_optimizer::merge_classes (unsigned int prev_class_count)
alias->dump_to_file (dump_file);
}
- source->merge (alias);
+ if (source->merge (alias))
+ merged_p = true;
}
}
+
+ return merged_p;
}
/* Dump function prints all class members to a FILE with an INDENT. */
@@ -3031,12 +3041,12 @@ ipa_icf_driver (void)
{
gcc_assert (optimizer);
- optimizer->execute ();
+ bool merged_p = optimizer->execute ();
delete optimizer;
optimizer = NULL;
- return 0;
+ return merged_p ? TODO_remove_functions : 0;
}
const pass_data pass_data_ipa_icf =
diff --git a/gcc/ipa-icf.h b/gcc/ipa-icf.h
index e3582db..1481353 100644
--- a/gcc/ipa-icf.h
+++ b/gcc/ipa-icf.h
@@ -470,8 +470,10 @@ public:
read-only variables that can be merged. */
void parse_funcs_and_vars (void);
- /* Optimizer entry point. */
- void execute (void);
+ /* Optimizer entry point which returns true in case it processes
+ a merge operation. True is returned if there's a merge operation
+ processed. */
+ bool execute (void);
/* Dump function. */
void dump (void);
@@ -545,8 +547,9 @@ private:
/* Aft
[IA-64] Fix gcc.dg/torture/vshuf-v8qi.c
Hi, the test fails at -O2 because of the assertion recently added to gen_reg_rtx that crtl->emit.regno_pointer_align_length is non-zero. Now the function expand_vec_perm_interleave_2 can be invoked at the GIMPLE level in "testing" mode and crtl->emit is not initialized by that time. Tested on ia64-linux-gnu, OK for mainline and 4.9 branch? 2015-03-03 Eric Botcazou * config/ia64/ia64.c (expand_vec_perm_interleave_2): Use gen_raw_REG to create a register in testing mode. -- Eric BotcazouIndex: config/ia64/ia64.c === --- config/ia64/ia64.c (revision 221132) +++ config/ia64/ia64.c (working copy) @@ -11570,7 +11570,10 @@ expand_vec_perm_interleave_2 (struct exp gcc_assert (e < nelt); dfinal.perm[i] = e; } - dfinal.op0 = gen_reg_rtx (dfinal.vmode); + if (d->testing_p) +dfinal.op0 = gen_raw_REG (dfinal.vmode, LAST_VIRTUAL_REGISTER + 1); + else +dfinal.op0 = gen_reg_rtx (dfinal.vmode); dfinal.op1 = dfinal.op0; dfinal.one_operand_p = true; dremap.target = dfinal.op0;
Re: Avoid cycles in the inline plan
On Mon, 2 Mar 2015, Jan Hubicka wrote:
> Hi,
> in the testcase bellow we manage to produce cycle in inline plan because
> there is
> indirectly recrusive function that appears called once.
>
> I am having problems with the testcase. The second file outht to be compiled
> with
> -O2, but it is not. Is the dg-options in the LTO testsuite broken now or did
> I missed
> something obvious?
It works for me:
spawn /home/abuild/rguenther/trunk-g/gcc/testsuite/g++/../../xg++
-B/home/abuild/rguenther/trunk-g/gcc/testsuite/g++/../../
-fno-diagnostics-show-caret -fdiagnostics-color=never -nostdinc++
-I/abuild/rguenther/trunk-g/x86_64-unknown-linux-gnu/libstdc++-v3/include/x86_64-unknown-linux-gnu
-I/abuild/rguenther/trunk-g/x86_64-unknown-linux-gnu/libstdc++-v3/include
-I/space/rguenther/src/svn/trunk/libstdc++-v3/libsupc++
-I/space/rguenther/src/svn/trunk/libstdc++-v3/include/backward
-I/space/rguenther/src/svn/trunk/libstdc++-v3/testsuite/util
-fmessage-length=0 -flto -O0 -std=c++11 -O2 -c -o cp_lto_pr65276_1.o
/space/rguenther/src/svn/trunk/gcc/testsuite/g++.dg/lto/pr65276_1.C^M
(it just appends -O2)
Richard.
> The testcase excercises the new paths anyway (just does not ice) so I decided
> to commit it as it is for now.
>
> Bootstrapped/regtested x86_64-linux, commited.
>
> Honza
>
> PR ipa/65130
> * ipa-inline.c (check_callers): Looks for recursion.
> (inline_to_all_callers): Give up on uninlinable or recursive edges.
> * ipa-inline-analysis.c (inline_summary_t::duplicate): Do not update
> summary of inline clones.
> (do_estimate_growth_1): Fix recursion check.
>
> * gcc.dg/lto/pr65130_0.c: New testcase.
> * gcc.dg/lto/pr65130_1.c: New testcase.
> Index: ipa-inline.c
> ===
> --- ipa-inline.c (revision 221122)
> +++ ipa-inline.c (working copy)
> @@ -952,6 +952,8 @@ check_callers (struct cgraph_node *node,
>return true;
> if (!can_inline_edge_p (e, true))
> return true;
> + if (e->recursive_p ())
> + return true;
> if (!(*(bool *)has_hot_call) && e->maybe_hot_p ())
>*(bool *)has_hot_call = true;
> }
> @@ -2094,6 +2096,15 @@ inline_to_all_callers (struct cgraph_nod
> {
>struct cgraph_node *caller = node->callers->caller;
>
> + if (!can_inline_edge_p (node->callers, true)
> + || node->callers->recursive_p ())
> + {
> + if (dump_file)
> + fprintf (dump_file, "Uninlinable call found; giving up.\n");
> + *num_calls = 0;
> + return false;
> + }
> +
>if (dump_file)
> {
> fprintf (dump_file,
> Index: testsuite/gcc.dg/lto/pr65130_0.c
> ===
> --- testsuite/gcc.dg/lto/pr65130_0.c (revision 0)
> +++ testsuite/gcc.dg/lto/pr65130_0.c (revision 0)
> @@ -0,0 +1,19 @@
> +/* { dg-lto-do link } */
> +/* { dg-lto-options { { -flto -O1 -fdevirtualize } } } */
> +extern void fn3 (void);
> +
> +void fn2(void)
> +{
> + fn3();
> +}
> +
> +void fn1(void)
> +{
> + fn2();
> +}
> +
> +void fn4(void)
> +{
> + fn2();
> +}
> +
> Index: testsuite/gcc.dg/lto/pr65130_1.c
> ===
> --- testsuite/gcc.dg/lto/pr65130_1.c (revision 0)
> +++ testsuite/gcc.dg/lto/pr65130_1.c (revision 0)
> @@ -0,0 +1,17 @@
> +/* { dg-options "-O2 -fdevirtualize" } */
> +extern void fn1(void);
> +extern void fn4 (void);
> +
> +int a;
> +
> +void fn3(void)
> +{
> + for (; a;)
> +fn4();
> +}
> +
> +int main() {
> + fn1();
> + return 0;
> +}
> +
> Index: ipa-inline-analysis.c
> ===
> --- ipa-inline-analysis.c (revision 221122)
> +++ ipa-inline-analysis.c (working copy)
> @@ -1291,7 +1291,8 @@ inline_summary_t::duplicate (cgraph_node
> set_hint_predicate (&info->array_index, p);
> }
> }
> - inline_update_overall_summary (dst);
> + if (!dst->global.inlined_to)
> +inline_update_overall_summary (dst);
> }
>
>
> @@ -3924,10 +3925,11 @@ do_estimate_growth_1 (struct cgraph_node
>continue;
> }
>
> - if (e->caller == d->node
> - || (e->caller->global.inlined_to
> - && e->caller->global.inlined_to == d->node))
> - d->self_recursive = true;
> + if (e->recursive_p ())
> + {
> + d->self_recursive = true;
> + continue;
> + }
>d->growth += estimate_edge_growth (e);
> }
>return false;
>
>
--
Richard Biener
SUSE LINUX GmbH, GF: Felix Imendoerffer, Jane Smithard, Jennifer Guild,
Dilip Upmanyu, Graham Norton HRB 21284 (AG Nuernberg)
[Ping v3] [PATCH PR64820] Fix ASan UAR detection fails on 32-bit targets if SSP is enabled.
On 02/25/2015 05:40 PM, Maxim Ostapenko wrote:
On 02/16/2015 10:58 AM, Maxim Ostapenko wrote:
Hi,
when testing I noticed, that if compile with both -fsanitize=address and
-fstack-protector for 32-bit architectures and run with
ASAN_OPTIONS=detect_stack_use_after_return=1, libsanitizer fails with:
==7299==AddressSanitizer CHECK failed:
/home/max/workspace/downloads/gcc/libsanitizer/asan/asan_poisoning.cc:25
"((AddrIsAlignedByGranularity(addr + size))) != (0)" (0x0, 0x0)
#0 0xf72d8afc in AsanCheckFailed
/home/max/workspace/downloads/gcc/libsanitizer/asan/asan_rtl.cc:68
#1 0xf72dda89 in __sanitizer::CheckFailed(char const*, int, char
const*, unsigned long long, unsigned long long)
/home/max/workspace/downloads/gcc/libsanitizer/sanitizer_common/sanitizer_common.cc:72
This happens because ssp inserts a stack guard into a function, that
confuses asan_emit_stack_protection to calculate right size parameter
for asan_stack_malloc.
This tiny patch resolves the issue.
Regtested with make -j12 -k check
RUNTESTFLAGS='--target_board=unix\{-m32,-m64\}' on
x86_64-unknown-linux-gnu.
Bootstrapped, ASan-bootstrapped on x86_64-unknown-linux-gnu.
Ok to commit?
-Maxim
Ping.
-Maxim
Ping.
-Maxim
gcc/ChangeLog:
2015-03-03 Max Ostapenko
PR sanitizer/64820
* cfgexpand.c (align_base): New function.
(alloc_stack_frame_space): Call it.
(expand_stack_vars): Align prev_frame to be sure
data->asan_vec elements aligned properly.
gcc/testsuite/ChangeLog:
2015-03-03 Max Ostapenko
PR sanitizer/64820
* c-c++-common/asan/pr64820.c: New test.
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index 7dfe1f6..7845a17 100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -282,6 +282,15 @@ align_local_variable (tree decl)
return align / BITS_PER_UNIT;
}
+/* Align given offset BASE with ALIGN. Truncate up if ALIGN_UP is true,
+ down otherwise. Return truncated BASE value. */
+
+static inline unsigned HOST_WIDE_INT
+align_base (HOST_WIDE_INT base, unsigned HOST_WIDE_INT align, bool align_up)
+{
+ return align_up ? (base + align - 1) & -align : base & -align;
+}
+
/* Allocate SIZE bytes at byte alignment ALIGN from the stack frame.
Return the frame offset. */
@@ -293,17 +302,15 @@ alloc_stack_frame_space (HOST_WIDE_INT size, unsigned HOST_WIDE_INT align)
new_frame_offset = frame_offset;
if (FRAME_GROWS_DOWNWARD)
{
- new_frame_offset -= size + frame_phase;
- new_frame_offset &= -align;
- new_frame_offset += frame_phase;
+ new_frame_offset
+ = align_base (frame_offset - frame_phase - size,
+ align, false) + frame_phase;
offset = new_frame_offset;
}
else
{
- new_frame_offset -= frame_phase;
- new_frame_offset += align - 1;
- new_frame_offset &= -align;
- new_frame_offset += frame_phase;
+ new_frame_offset
+ = align_base (frame_offset - frame_phase, align, true) + frame_phase;
offset = new_frame_offset;
new_frame_offset += size;
}
@@ -1031,13 +1038,16 @@ expand_stack_vars (bool (*pred) (size_t), struct stack_vars_data *data)
base = virtual_stack_vars_rtx;
if ((flag_sanitize & SANITIZE_ADDRESS) && ASAN_STACK && pred)
{
- HOST_WIDE_INT prev_offset = frame_offset;
+ HOST_WIDE_INT prev_offset
+ = align_base (frame_offset,
+ MAX (alignb, ASAN_RED_ZONE_SIZE),
+ FRAME_GROWS_DOWNWARD);
tree repr_decl = NULL_TREE;
-
offset
= alloc_stack_frame_space (stack_vars[i].size
+ ASAN_RED_ZONE_SIZE,
MAX (alignb, ASAN_RED_ZONE_SIZE));
+
data->asan_vec.safe_push (prev_offset);
data->asan_vec.safe_push (offset + stack_vars[i].size);
/* Find best representative of the partition.
diff --git a/gcc/testsuite/c-c++-common/asan/pr64820.c b/gcc/testsuite/c-c++-common/asan/pr64820.c
new file mode 100644
index 000..885a662
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/asan/pr64820.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fstack_protector } */
+/* { dg-options "-fstack-protector-strong" } */
+/* { dg-set-target-env-var ASAN_OPTIONS "detect_stack_use_after_return=1" } */
+/* { dg-shouldfail "asan" } */
+
+__attribute__((noinline))
+char *Ident(char *x) {
+ return x;
+}
+
+__attribute__((noinline))
+char *Func1() {
+ char local[1 << 12];
+ return Ident(local);
+}
+
+__attribute__((noinline))
+void Func2(char *x) {
+ *x = 1;
+}
+int main(int argc, char **argv) {
+ Func2(Func1());
+ return 0;
+}
+
+/* { dg-output "AddressSanitizer: stack-use-after-return on address 0x\[0-9a-f\]+\[^\n\r]*(\n|\r\n|\r)" } */
+/* { dg-output "WRITE of size 1 at .* thread T0.*" } */
+/* { dg-output "#0.*(Func2)?.*pr64820.(c:21)?.*" } */
+/* { dg-output "is located in stack of thread T0 at offset.*" } */
Re: [PATCH] PR target/65248: [5 Regression] Copy relocation in PIE against protected symbol
On Mon, Mar 02, 2015 at 05:36:24AM -0800, H.J. Lu wrote: > On Sun, Mar 1, 2015 at 11:48 PM, Uros Bizjak wrote: > > On Sat, Feb 28, 2015 at 5:42 PM, H.J. Lu wrote: > >> Ue copy relocation in PIE improves performance. But copy relocation > >> can't be used to access protected symbols defined in shared libaries > >> and linker in binutils 2.26 enforces doesn't allow it. GCC doesn't > >> know if an external definition is protected or not. This option adds > >> -mcopyreloc-in-pie to give user an option to turn it off to avoid problem > >> at link-time. OK for trunk? > > > > If the option does not work universally for all cases, then the > > default should be off. > > This optimization isn't the real issue. The issue here is protected > symbol in shared library. It can never be referenced from a normal > executable and works correctly, as Alan explained. It doesn't matter > if this option is off or not since it only applies to PIE. You can try > the testcase in PR 65248 without -fPIE -pie. I see things differently. We have an old linker hack to avoid dynamic text relocations in non-PIC executables. This hack doesn't work properly with protected visibility variables in shared libraries. Rather than blaming protected visibility variables, I say the hack is broken. Since you rely on the linker hack for your optimization, you've extended the problem from non-PIC executables to PIEs.. If you want the optimization enabled by default then it probably would have been better to do the optimization entirely in the linker, similar to the way we optimize TLS sequences. Certainly a switch that enables the optimization in the compiler is reasonable if that gives better code, but I can see distros turning it off if you manage to convince Uros and others that the default should be on. -- Alan Modra Australia Development Lab, IBM
