Re: [PATCH, libiberty]: Avoid "enum conversion when passing argument 1 of ‘getrusage’ is invalid in C++" warning

[Uros Bizjak]

On Wed, Jul 1, 2015 at 12:07 PM, Uros Bizjak  wrote:

> This patch avoids "enum conversion when passing argument 1 of
> ‘getrusage’ is invalid in C++" warning when compiling getruntime.c.
> The condition is copied from sys/resource.h.
>
> 2015-07-01  Uros Bizjak  
>
> * getruntime.c (get_run_time) [__USE_GNU]: Use RUSAGE_SELF as
> argument 1 of getrusage call.
>
> Bootstrapped on x86_64-linux-gnu.
>
> OK for mainline?

I went ahead and committed the patch to mainline as obvious.

Uros.

[PATCH] Fix fold_widened_comparison typo

[Richard Biener]

I once wondered why fold didn't optimize (long)int-val > INT_MAX
when niter analysis tried to fold this.  Now when moving
fold_widened_comparison to match.pd I noticed that a bogus
condition on the limit folding causes it to only apply in the
case when it won't simplify anything...

Thus, fixed.  C testcase notoriously hard because of the frontend
already shortening the compare (and doing the desired simplification).

Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk.

Richard.

2015-07-08  Richard Biener  

* fold-const.c (fold_widened_comparison): Fix inverted comparison.

Index: gcc/fold-const.c
===
--- gcc/fold-const.c(revision 225501)
+++ gcc/fold-const.c(working copy)
@@ -6794,7 +6794,7 @@ fold_widened_comparison (location_t loc,
 
   if (TREE_CODE (arg1_unw) != INTEGER_CST
   || TREE_CODE (shorter_type) != INTEGER_TYPE
-  || !int_fits_type_p (arg1_unw, shorter_type))
+  || int_fits_type_p (arg1_unw, shorter_type))
 return NULL_TREE;
 
   /* If we are comparing with the integer that does not fit into the range

Re: [PATCH][ARM] Add debug dumping of cost table fields

[Kyrill Tkachov]

Ping.
https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01064.html

Thanks,
Kyrill

On 16/06/15 09:36, Kyrill Tkachov wrote:

On 27/05/15 09:39, Andrew Pinski wrote:

On Wed, May 27, 2015 at 4:38 PM, Kyrill Tkachov  wrote:

Ping.
https://gcc.gnu.org/ml/gcc-patches/2015-05/msg00054.html

This and the one in AARCH64 is too noisy.  Can we have an option to
turn this on and default to turning them off.

How about this? The new undocumented option can be used to turn on verbose 
costs dumping.
It is off by default.

Tested arm-none-eabi.

Ok for trunk?

Thanks,
Kyrill

2015-06-16  Kyrylo Tkachov  

  * config/arm/arm.c (DBG_COST): New macro.
  (arm_new_rtx_costs): Use above.
  * config/arm/arm.opt (mdebug-rtx-costs): New option.


Thanks,
Andrew


Thanks,
Kyrill

On 01/05/15 15:31, Kyrill Tkachov wrote:

Hi all,

This patch adds a macro to wrap cost field accesses into a helpful debug
dump,
saying which field is being accessed at what line and with what values.
This helped me track down cases where the costs were doing the wrong thing
by allowing me to see which path in arm_new_rtx_costs was taken.
For example, the combine log might now contain:

Trying 2 -> 6:
Successfully matched this instruction:
(set (reg:SI 115 [ D.5348 ])
(neg:SI (reg:SI 0 r0 [ a ])))
using extra_cost->alu.arith with cost 0 from line 10506

which can be useful in debugging the rtx costs.

Bootstrapped and tested on arm.

Ok for trunk?

Thanks,
Kyrill


2015-05-01  Kyrylo Tkachov  

* config/arm/arm.c (DBG_COST): New macro.
(arm_new_rtx_costs): Use above.

Re: [PATCH][ARM][stage-1] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs

[Kyrill Tkachov]

Ping.

Thanks,
Kyrill

On 17/06/15 11:16, Kyrill Tkachov wrote:

Ping^5.

https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01130.html

Thanks,
Kyrill

On 02/06/15 09:16, Kyrill Tkachov wrote:

Ping^4.

Thanks,
Kyrill

On 21/05/15 18:00, Kyrill Tkachov wrote:

Ping^3.

Thanks,
Kyrill

On 12/05/15 10:09, Kyrill Tkachov wrote:

Ping^2.

Thanks,
Kyrill

On 30/04/15 13:00, Kyrill Tkachov wrote:

Ping.
https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01130.html

Thanks,
Kyrill

On 21/04/15 10:11, Kyrill Tkachov wrote:

Hi all,

This is the first of a series to clean up and simplify the arm rtx costs 
function.
This patch initialises the cost to COSTS_N_INSNS (1) at the top and increments 
it when appropriate
in the rest of the function. This makes it more similar to the aarch64 rtx 
costs function and saves
us the trouble of having to remember to initialise the cost to COSTS_N_INSNS 
(1) in each case of the
switch statement.

Bootstrapped and tested arm-none-linux-gnueabihf.
Compiled some large programs with no codegen difference, except some DIV 
synthesis algorithms were changed,
presumably due to the cost of SDIV/UDIV, which is now being correctly 
calculated (before it was missing the
baseline COSTS_N_INSNS (1)).

Ok for trunk?

Thanks,
Kyrill

2015-04-21  Kyrylo Tkachov  

   * config/arm/arm.c (arm_new_rtx_costs): Initialise cost to
   COSTS_N_INSNS (1) and increment it appropriately throughout the
   function.

[PATCH] Fix for PR bootstrap/66744

[Martin Liška]

Hello.

Following small patch does what is described in $subject.
Patch can boostrap on ppc64-linux-unknown-pc and on i686-w64-mingw32.

Ready for trunk?
Thanks,
Martin
>From 0b3f863ff9806ed9f802b18aabe0276830a3c38e Mon Sep 17 00:00:00 2001
From: mliska 
Date: Fri, 3 Jul 2015 17:48:01 +0200
Subject: [PATCH] Fix PR bootstrap/66744.

gcc/ChangeLog:

2015-07-03  Martin Liska  

	PR bootstrap/66744
	* tree-sra.c (create_access_1): Can ctor without brackets.
	(create_artificial_child_access): Likewise.
---
 gcc/tree-sra.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/tree-sra.c b/gcc/tree-sra.c
index 7f242f7..77c00b2 100644
--- a/gcc/tree-sra.c
+++ b/gcc/tree-sra.c
@@ -872,7 +872,7 @@ mark_parm_dereference (tree base, HOST_WIDE_INT dist, gimple stmt)
 static struct access *
 create_access_1 (tree base, HOST_WIDE_INT offset, HOST_WIDE_INT size)
 {
-  struct access *access = new struct access ();
+  struct access *access = new struct access;
 
   memset (access, 0, sizeof (struct access));
   access->base = base;
@@ -2407,7 +2407,7 @@ create_artificial_child_access (struct access *parent, struct access *model,
 
   gcc_assert (!model->grp_unscalarizable_region);
 
-  struct access *access = new struct access ();
+  struct access *access = new struct access;
   memset (access, 0, sizeof (struct access));
   if (!build_user_friendly_ref_for_offset (&expr, TREE_TYPE (expr), new_offset,
 	   model->type))
-- 
2.4.3

Re: [PATCH 3/16][ARM] Add float16x4_t intrinsics

[Ramana Radhakrishnan]

I haven't seen the patch yet but here are my thoughts on where this should be 
going.

On 07/07/15 18:17, Alan Lawrence wrote:
> Kyrill Tkachov wrote:
>> On 07/07/15 17:34, Alan Lawrence wrote:
>>> Kyrill Tkachov wrote:
 On 07/07/15 14:09, Kyrill Tkachov wrote:
> Hi Alan,
>
> On 07/07/15 13:34, Alan Lawrence wrote:
>> As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01335.html
> For some context, the reference for these is at:
> http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf
>
> This patch is ok once you and Charles decide on how to proceed with the 
> two prerequisites.
 On second thought, the ACLE document at 
 http://infocenter.arm.com/help/topic/com.arm.doc.ihi0053c/IHI0053C_acle_2_0.pdf

 says in 12.2.1:
 "float16 types are only available when the __fp16 type is defined, i.e. 
 when supported by the hardware"
>>> However, we support __fp16 whenever the user specifies -mfp16-format=ieee or
>>> -mfp16-format=alternative, regardless of whether we have hardware support 
>>> or not.
>>>
>>> (Without hardware support, gcc generates calls to  __gnu_f2h_ieee or
>>> __gnu_f2h_alternative instead of vcvtb.f16.f32, and  __gnu_h2f_ieee or
>>> __gnu_h2f_alternative instead of vcvtb.f32.f16. However, there is no way to
>>> support __fp16 just using those hardware instructions without caring about 
>>> which
>>> format is in use.)
>>
>> Hmmm... In my opinion intrinsics should aim to map to instructions rather 
>> than go away and
>> call library functions, but this is the existing functionality
>> that current users might depend on :(
> 
> Sorry - to clarify: currently we generate __gnu_f2h_ieee / __gnu_h2f_ieee, to 
> convert between single __fp16 and 'float' values, when there is no HW. 
> General operations on scalar __fp16 values are performed by converting to 
> float, performing operations on float, and converting back. The __fp16 type 
> is available and "usable" without HW support, but only when -mfp16-format is 
> specified.
> 
> (The existing) intrinsics operating on float16x[48] vectors (converting 
> to/from float32x4) are *not* available without hardware support; these 
> intrinsics *are* available without specifying -mfp16-format.
> 
> ACLE (4.1.2) allows toolchains to provide __fp16 when not implemented in HW, 
> even if this is not required.

The type should exist with the presence of the SIMD unit and all the intrinsics 
that treat this as a bag of bits should just work (TM). The only intrinsics to 
be guarded by mfpu=neon-fp16 should really be the intrinsics for the 
instructions that interpret the 16 bits as float16 types.

> 
>> CC'ing the ARM maintainers and Tejas for an ACLE perspective.
>> I think that we'd want to gate the definition of __fp16 on hardware 
>> availability as well
>> (the -mfpu option) rather than just arm_fp16_format but I'm not sure of the 
>> impact this will have
>> on existing users.

This is just a storage format in the scalar world and the ACLE allows folks to 
have fp16 support without hardware. There are helper routines for that which 
were put in in the first place for this purpose.

> 
> Surebut do we require -mfpu *and* -mfp16-format? s/and/or/ ?   Do we 
> require -mfp16-format for float16x[48] intrinsics, or allow format-agnostic 
> code (as HW support allows us to!)?
> 

I'd say we require the mfpu option for the intrinsics that interpret the 
float16 type but there is no bearing on the float16 format being chosen for 
this purpose, the reason being that the actual instruction being emitted takes 
care of doing the right thing as per the format specified by the AHP bit in the 
FPSCR - This is unlike the scalar case where the compiler *needs* to know the 
fp16-format that the user intended to use in order to call the correct 
emulation function.

Thus in summary - 

1. -mfpu=neon implies the presence of the float16x(4/8) types and all the 
intrinsics that treat these values as bags of bits.
2. -mfpu=neon-fp16 implies the presence of the vcvt* intrinsics that are needed 
for the float16 types.

Thoughts ?

regards
Ramana





> 
> Cheers, Alan
> 

Re: [PATCH][ARM][stage-1] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs

[Ramana Radhakrishnan]

On 21/04/15 10:11, Kyrill Tkachov wrote:
> Hi all,
> 
> This is the first of a series to clean up and simplify the arm rtx costs 
> function.
> This patch initialises the cost to COSTS_N_INSNS (1) at the top and 
> increments it when appropriate
> in the rest of the function. This makes it more similar to the aarch64 rtx 
> costs function and saves
> us the trouble of having to remember to initialise the cost to COSTS_N_INSNS 
> (1) in each case of the
> switch statement.
> 
> Bootstrapped and tested arm-none-linux-gnueabihf.
> Compiled some large programs with no codegen difference, except some DIV 
> synthesis algorithms were changed,
> presumably due to the cost of SDIV/UDIV, which is now being correctly 
> calculated (before it was missing the
> baseline COSTS_N_INSNS (1)).
> 
> Ok for trunk?
> 
> Thanks,
> Kyrill
> 
> 2015-04-21  Kyrylo Tkachov  
> 
> * config/arm/arm.c (arm_new_rtx_costs): Initialise cost to
> COSTS_N_INSNS (1) and increment it appropriately throughout the
> function.


OK  - (shudder at ping ^ 6), sorry about the delay.

Ramana

RE: [PATCH] MIPS: Update stack-1.c testcase to match micromips jraddiusp instruction.

[Andrew Bennett]

> Yes, this is OK.

Committed as SVN 225536.

Regards,


Andrew

Drop -Wswitch-bool warning in function.c

[Kito Cheng]

Bootstrapped & regression-tested on x86_64-linux-gnu :)

2015-07-08  Kito Cheng  

* function.c (stack_protect_epilogue): Use if rather than switch for
check targetm.have_stack_protect_test().
From 0306990aac578167872a80ab55085d335e2bea14 Mon Sep 17 00:00:00 2001
From: Kito Cheng 
Date: Wed, 8 Jul 2015 15:20:01 +0800
Subject: [PATCH] Drop -Wswitch-bool warning in function.c

---
 gcc/function.c | 20 ++--
 1 file changed, 6 insertions(+), 14 deletions(-)

diff --git a/gcc/function.c b/gcc/function.c
index 972cdc8..b87aef6 100644
--- a/gcc/function.c
+++ b/gcc/function.c
@@ -4874,26 +4874,18 @@ stack_protect_epilogue (void)
   tree guard_decl = targetm.stack_protect_guard ();
   rtx_code_label *label = gen_label_rtx ();
   rtx x, y, tmp;
+  rtx_insn *seq;
 
   x = expand_normal (crtl->stack_protect_guard);
   y = expand_normal (guard_decl);
 
   /* Allow the target to compare Y with X without leaking either into
  a register.  */
-  switch (targetm.have_stack_protect_test ())
-{
-case 1:
-  if (rtx_insn *seq = targetm.gen_stack_protect_test (x, y, label))
-	{
-	  emit_insn (seq);
-	  break;
-	}
-  /* FALLTHRU */
-
-default:
-  emit_cmp_and_jump_insns (x, y, EQ, NULL_RTX, ptr_mode, 1, label);
-  break;
-}
+  if (targetm.have_stack_protect_test ()
+  && ((seq = targetm.gen_stack_protect_test (x, y, label)) != NULL_RTX))
+emit_insn (seq);
+  else
+emit_cmp_and_jump_insns (x, y, EQ, NULL_RTX, ptr_mode, 1, label);
 
   /* The noreturn predictor has been moved to the tree level.  The rtl-level
  predictors estimate this branch about 20%, which isn't enough to get
-- 
2.3.5

Re: fix PR46029: reimplement if conversion of loads and stores

[Alan Lawrence]

Abe wrote:


I`m uncertain to what that is intended to refer, but I believe Sebastian would 
agree that the new if converter is safer than the old one in terms of 
correctness at the time of running the code being compiled.

>

even if they take us a step backwards from a performance standpoint.


For now, we have a few performance regressions, and so far we have found that 
it`s non-trivial to remove all of those regressions.
We may be better off pushing the current patch to trunk and having the 
performance regressions currently introduced by the new if converter be fixed 
by later patches.
Pushing to trunk gives us excellent "visibility" amongst GCC hackers, so the code will 
get more "eyeballs" than if it lingers in an uncommitted patch or in a branch.
I, for one, would love some help in fixing these performance regressions. ;-)

If fixing the performance regressions winds up taking too long, perhaps the 
current imperfect patch could be undone on trunk just before a release is 
tagged,
and then we`ll push it in again when trunk goes back to being allowed to be unstable? 


TBH my two cents would be that a performance-regressed, but correct, compiler, 
is far better to release, than a performance-"improved" one that generates 
unsafe code (e.g. with extra faults in the straightforward single-threaded case!)...


--Alan

Re: [PATCH, i386]: Generate BT with immedate operand

[Uros Bizjak]

On Tue, Jul 7, 2015 at 8:35 PM, Uros Bizjak  wrote:

> BT has *slightly* higher latency than TEST (0.33 vs. 0.25 cycles on a
> modern processor), so I have limited the conversion to -Os in case the
> bit-test is in the low 32 bits.

A small update, in case of -Os, unpatched compiler generates andb for
0 <= n <= 7 with:

  0:   83 e7 20and$0x20,%edi

vs.

  0:   0f ba e7 05 bt $0x5,%edi

Attached patch updated the splitter condition to reflect the above.

2015-07-08  Uros Bizjak  

* config/i386/i386.md (*jcc_bt): Only allow const_int values
more than or equal 8 and less than 32 when optimizing for size.

Tested on x86_64-linux-gnu {,-m32} and committed to mainline SVN.

Uros.

Index: config/i386/i386.md
===
--- config/i386/i386.md (revision 225533)
+++ config/i386/i386.md (working copy)
@@ -10811,7 +10811,7 @@
   && (CONST_INT_P (operands[2])
   ? (INTVAL (operands[2]) < GET_MODE_BITSIZE (mode)
 && INTVAL (operands[2])
-  >= (optimize_function_for_size_p (cfun) ? 0 : 32))
+  >= (optimize_function_for_size_p (cfun) ? 8 : 32))
   : register_operand (operands[2], SImode))
   && can_create_pseudo_p ()"
  "#"

Re: [PATCH 15/16][fold-const.c] Fix bigendian HFmode in native_interpret_real

[Richard Biener]

On Wed, Jul 8, 2015 at 12:07 AM, Jeff Law  wrote:
> On 07/07/2015 06:37 AM, Alan Lawrence wrote:
>>
>> As per https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01346.html. Fixes
>> FAIL of advsimd-intrinsics vcreate.c on aarch64_be-none-elf from
>> previous patch.
>>
>> 15_native_interpret_real.patch
>>
>>
>> commit e2e7ca148960a82fc88128820f17e7cbd14173cb
>> Author: Alan Lawrence
>> Date:   Thu Apr 9 10:54:40 2015 +0100
>>
>>  Fix native_interpret_real for HFmode floats on Bigendian with
>> UNITS_PER_WORD>=4
>>
>>  (with missing space)
>
> OK with ChangeLog in proper form.

Err - but now offset can become negative?  Shouldn't it rather error out
before as it requires at least 4 bytes for big-endian?

That said - the whole thing looks it doesn't expect GET_MODE_SIZE < 4
and your "fix" is just very obfuscated (if it really is a fix).

So, please cleanup the thing properly instead or at least add a big fat
comment.  There is the magic '3' in the line following yours as well.

Thanks,
Richard.

> jeff
>

Re: [PATCH] Fix for PR bootstrap/66744

[Richard Biener]

On Wed, Jul 8, 2015 at 10:23 AM, Martin Liška  wrote:
> Hello.
>
> Following small patch does what is described in $subject.
> Patch can boostrap on ppc64-linux-unknown-pc and on i686-w64-mingw32.
>
> Ready for trunk?

Ok.

Richard.

> Thanks,
> Martin

Re: [PATCH] Fix for PR bootstrap/66744

[Marek Polacek]

On Wed, Jul 08, 2015 at 10:23:43AM +0200, Martin Liška wrote:
>   PR bootstrap/66744
>   * tree-sra.c (create_access_1): Can ctor without brackets.
>   (create_artificial_child_access): Likewise.

When committing this, please s/Can/Call/ or something similar.

Marek

Re: fix PR46029: reimplement if conversion of loads and stores

[Richard Biener]

On Tue, Jul 7, 2015 at 11:23 PM, Abe  wrote:
>> (if-conversion could directly generate masked load/stores
>>  of course and not use a scratch-pad at all in that case).
>
>
> IMO that`s a great idea, but I don`t know how to do it.  Hints would be
> welcome.  In particular, how does one "generate masked load/stores" at the
> GIMPLE level?

It already does that, see predicate_mem_writes.  You should definitely
preserve that path (I think it does that only when versioning the loop
for if-conversion, non-vectorized loops will then not be if-converted).

>
>> But are we correctly handling these cases in the current if conversion
>> code?
>
>
> I`m uncertain to what that is intended to refer, but I believe Sebastian
> would agree that the new if converter is safer than the old one in terms of
> correctness at the time of running the code being compiled.
>
>
>> Abe's changes would seem like a step forward from a correctness standpoint
>
>
> Not to argue, but as a point of humility: Sebastian did by far the most work
> on this patch.  I just modernized it and helped move it along.  Even _that_
> was done with Sebastian`s help.
>
>
>> even if they take us a step backwards from a performance standpoint.
>
>
> For now, we have a few performance regressions, and so far we have found
> that it`s non-trivial to remove all of those regressions.

On what hardware did you test?

> We may be better off pushing the current patch to trunk and having the
> performance regressions currently introduced by the new if converter be
> fixed by later patches.
> Pushing to trunk gives us excellent "visibility" amongst GCC hackers, so the
> code will get more "eyeballs" than if it lingers in an uncommitted patch or
> in a branch.
> I, for one, would love some help in fixing these performance regressions.
> ;-)
>
> If fixing the performance regressions winds up taking too long, perhaps the
> current imperfect patch could be undone on trunk just before a release is
> tagged,
> and then we`ll push it in again when trunk goes back to being allowed to be
> unstable?  According to my analysis of the data near the end of the page at
> , we have until roughly April of 2016 to
> work on not-yet-perfect patches in trunk.
>
>
>>> So the question is whether we get more non-vectorized if-converted
>>> code out of this (and thus whether we want to use --param
>>> allow-store-data-races to get the old code back which is nicer to less
>>> capable CPUs and probably faster than using scatter/gather or masked
>>> loads/stores).
>
>
>> I do think conditionalizing some of this on the allow-store-data-races
>> makes sense.
>
>
> I think having both the old if-converter and the new one "live on" in GCC is
> nontrivial, but not impossible.  I also don`t think it`s the best long-term
> goal,
> but only a short-term workaround.  In the long run, IMO there should be only
> one if converter, albeit perhaps with tweaking flags [e.g.
> "-fallow-unsafe-if-conversion"].
>
>
>> I also wonder if we should really care about load data races (not sure
>> your patch does).
>
>
> According to a recent long discussion I had with Sebastian, our current
> patch does not have the flaw I was concerned it might have in terms of loads
> because:
>
>   [1] the scratchpad is only being used to if-convert assignments to
> thread-local scalars, never to globals/statics, and because...
>
>   [2] the gimplifier is supposed to detect "the address of this scalar has
> been taken" and when such is detected in the code being compiled,
>   it causes the scalar to no longer look like a scalar in GIMPLE so that
> we are also safe from stale-data problems that could come from
>   corner-case code that takes the address of a thread-local variable and
> gives that address to another thread [which then proceeds to
>   overwrite the value in the supposedly-thread-local scalar that belongs
> to a different thread from the one doing the writing]
>
>
> Regards,
>
> Abe
>
>

Re: [PATCH] Make SSA propagator iteration order consistent

[Markus Trippelsdorf]

On 2015.07.06 at 14:40 +0200, Richard Biener wrote:
> 
> The intent (as I read it) of the iteration order in ssa_propagate is
> to process stmts in the following order:
> 
>  1) complete simulation of BBs from making one of their entries executable
>  2) simulation of stmts fed by stmts that changed to VARYING
>  3) simulation of the rest of stmts fed by stmts that changed their 
> lattice value
> 
> but the current implementation fails to enforce this order because it
> drains the full worklists before considering entries added to the
> others by simulating a statement.  This leads to quite some extra
> simulation with too optimistic values from not yet executable edges
> (just run into this while debugging PR66733).
> 
> The current state is that of the original propagator implementation
> in this area.
> 
> The patch cuts the number of visited stmts for the testcase in PR66773
> from 23 to 20 (it visits PHI nodes 3 times less).

This patch breaks LTO/PGO bootstrap, see:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66801

-- 
Markus

Re: [PATCH, 2/2][PR66642] Add empty loop exit block in transform_to_exit_first_loop_alt

[Andreas Schwab]

Tom de Vries  writes:

>   * testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c (main): Test low
>   iteration count case.

../../../../libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c: In 
function 'main':
../../../../libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c:40:9: 
error: too few arguments to function 'f'
../../../../libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c:13:1: 
note: declared here

Andreas.

-- 
Andreas Schwab, SUSE Labs, sch...@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."

[PATCH, MIPS] Support interrupt handlers with hard-float

[Robert Suchanek]

Hi Matthew/Catherine,

The attached patch removes the restriction to compile a TU with an ISR with 
-mhard-float. Instead of forcing -msoft-float, the coprocessor 1 is disabled in 
an ISR for -mhard-float. 

Ok to apply?

Regards,
Robert

gcc/
* config/mips/mips.c (mips_compute_frame_info): Allow -mhard-float in
interrupt attribute.
(mips_expand_prologue): Disable the floating point unit in an ISR for
-mhard-float.
* config/mips/mips.h (SR_COP1): New define.
---
 gcc/config/mips/mips.c | 10 --
 gcc/config/mips/mips.h |  2 ++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index b6ad7db..18cb2bc 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -10424,8 +10424,6 @@ mips_compute_frame_info (void)
 {
   if (mips_isa_rev < 2)
error ("the % attribute requires a MIPS32r2 processor or 
greater");
-  else if (TARGET_HARD_FLOAT)
-   error ("the % attribute requires %<-msoft-float%>");
   else if (TARGET_MIPS16)
error ("interrupt handlers cannot be MIPS16 functions");
   else
@@ -11676,6 +11674,14 @@ mips_expand_prologue (void)
   GEN_INT (5),
   GEN_INT (SR_IE),
   gen_rtx_REG (SImode, GP_REG_FIRST)));
+
+ if (TARGET_HARD_FLOAT)
+   /* Disable COP1 for hard-float.  This will lead to an exception
+  if floating-point code is executed in an ISR.  */
+   emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
+  GEN_INT (1),
+  GEN_INT (SR_COP1),
+  gen_rtx_REG (SImode, GP_REG_FIRST)));
}
  else
{
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 0e14f90..24cf65c 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1807,6 +1807,8 @@ FP_ASM_SPEC "\
 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
the cause register for the EIC interrupt mode.  */
 #define CAUSE_IPL  10
+/* COP1 Enable is at bit 29 of the status register.  */
+#define SR_COP1 29
 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register.  
*/
 #define SR_IPL 10
 /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status
-- 
2.2.2

[PATCH, MIPS] Support new interrupt handler options

[Robert Suchanek]

Hi,

This patch adds support for optional arguments for interrupt and 
use_shadow_register_set attributes.  The patch also fixes an ICE if both 
interrupt and use_shadow_register_set are enabled and compiled with -mips64r2 
-mabi=64 discovered during testing of the attached test.

The interrupt attribute accepts new arguments: "eic" and 
"vector=[sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5]".  The former is the default if no 
argument is given and the latter changes the behaviour of GCC and masks 
interrupts from sw0 up to and including the specified vector.  As part of this 
change, the EPC is now saved and restored unconditionally to recover the state 
in nested interrupts.  Only K1 register is clobbered for masked interrupts but 
for non-masked interrupts K0 is still used.

The use_shadow_register_set attribute has a new option, "intstack", to indicate 
that the shadow register set has a valid stack pointer.  With this option 
"rdpgpr $sp, $sp" will not be generated for an ISR.

Tested with mips-img-elf, mips-img-linux-gnu and mips64el-linux-gnu cross 
compilers. Ok to apply?

Regards,
Robert

2015-07-07  Matthew Fortune  
Robert Suchanek  

gcc/
* config/mips/mips.c (mips_int_mask): New enum.
(mips_shadow_set): Likewise.
(int_mask): New variable.
(use_shadow_register_set_p): Change type to enum mips_shadow_set.
(machine_function): Add int_mask and use_shadow_register_set.
(mips_attribute_table): Add attribute handlers for interrupt and
use_shadow_register_set.
(mips_interrupt_mask): New static function.
(mips_handle_interrupt_attr): Likewise.
(mips_handle_use_shadow_register_set_attr): Likewise.
(mips_use_shadow_register_set): Change return type to enum
mips_shadow_set.  Add argument handling for use_shadow_register_set
attribute.
(mips_interrupt_extra_called_saved_reg_p): Update the conditional to
compare with mips_shadow_set enum.
(mips_compute_frame_info): Add interrupt mask and
use_shadow_register_set to per-function information structure.
Add a stack slot for EPC unconditionally.
(mips_expand_prologue): Compare use_shadow_register_set value
with mips_shadow_set enum.  Save EPC always in K1, clobber only K1 for
masked interrupt register but in EIC mode use K0 and save Cause in K0.
EPC saved and restored unconditionally.  Use PMODE_INSN macro when
copying the stack pointer from the shadow register set.
* config/mips/mips.h (SR_IM0): New define.
* config/mips/mips.md (mips_rdpgpr): Rename to...
(mips_rdpgpr_): ...this.  Use the Pmode iterator.
* doc/extend.texi (Declaring Attributes of Functions): Document
optional arguments for interrupt and use_shadow_register_set
attributes.

gcc/testsuite/
* gcc.target/mips/interrupt_handler-4.c: New test.
---
 gcc/config/mips/mips.c | 276 +
 gcc/config/mips/mips.h |   3 +
 gcc/config/mips/mips.md|  10 +-
 gcc/doc/extend.texi|  22 +-
 .../gcc.target/mips/interrupt_handler-4.c  |  31 +++
 5 files changed, 281 insertions(+), 61 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/interrupt_handler-4.c

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index ce21a0f..b6ad7db 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -390,6 +390,30 @@ struct GTY(())  mips_frame_info {
   HOST_WIDE_INT hard_frame_pointer_offset;
 };
 
+/* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts.  */
+enum mips_int_mask
+{
+  INT_MASK_EIC = -1,
+  INT_MASK_SW0 = 0,
+  INT_MASK_SW1 = 1,
+  INT_MASK_HW0 = 2,
+  INT_MASK_HW1 = 3,
+  INT_MASK_HW2 = 4,
+  INT_MASK_HW3 = 5,
+  INT_MASK_HW4 = 6,
+  INT_MASK_HW5 = 7
+};
+
+/* Enumeration to mark the existence of the shadow register set.
+   SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack
+   pointer.  */
+enum mips_shadow_set
+{
+  SHADOW_SET_NO,
+  SHADOW_SET_YES,
+  SHADOW_SET_INTSTACK
+};
+
 struct GTY(())  machine_function {
   /* The next floating-point condition-code register to allocate
  for ISA_HAS_8CC targets, relative to ST_REG_FIRST.  */
@@ -442,8 +466,12 @@ struct GTY(())  machine_function {
   /* True if this is an interrupt handler.  */
   bool interrupt_handler_p;
 
-  /* True if this is an interrupt handler that uses shadow registers.  */
-  bool use_shadow_register_set_p;
+  /* Records the way in which interrupts should be masked.  Only used if
+ interrupts are not kept masked.  */
+  enum mips_int_mask int_mask;
+
+  /* Records if this is an interrupt handler that uses shadow registers.  */
+  enum mips_shadow_set use_shadow_register_set;
 
   /* True if this is an interrupt handler that should keep interrupts
  masked.  */
@@ -725,6 +753,10 @@ const enum 

[PATCH, MIPS] Fix restoration of hi/lo in MIPS64R2 interrupt handlers

[Robert Suchanek]

Hi,

The attached patch fixes an ICE (unrecognizable insn) when accumulators are 
used in interrupt handlers for MIPS64R2. There was just a typo in the function 
name.

Ok to apply?

Regards,
Robert

gcc/
* config/mips/mips.c (mips_emit_save_slot_move): Fix typo.

gcc/testsuite/
* gcc.target/mips/20150707.c: New test.
---
 gcc/config/mips/mips.c   | 2 +-
 gcc/testsuite/gcc.target/mips/20150707.c | 7 +++
 2 files changed, 8 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/20150707.c

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index ef8b0c7..1f247cf 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -10961,7 +10961,7 @@ mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
{
  mips_emit_move (temp, src);
  if (TARGET_64BIT)
-   emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
+   emit_insn (gen_mthidi_ti (gen_rtx_REG (TImode, MD_REG_FIRST),
  temp, gen_rtx_REG (DImode, LO_REGNUM)));
  else
emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
diff --git a/gcc/testsuite/gcc.target/mips/20150707.c 
b/gcc/testsuite/gcc.target/mips/20150707.c
new file mode 100644
index 000..434b3b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/20150707.c
@@ -0,0 +1,7 @@
+/* { dg-do assemble } */
+/* { dg-options "-mips64r2" } */
+_Accum a;
+__attribute__((interrupt))
+void foo () {
+  a = a*a;
+}
-- 
2.2.2

Re: [PATCH 15/16][fold-const.c] Fix bigendian HFmode in native_interpret_real

[Alan Lawrence]

Richard Biener wrote:

On Wed, Jul 8, 2015 at 12:07 AM, Jeff Law  wrote:

On 07/07/2015 06:37 AM, Alan Lawrence wrote:

[snip]

 Fix native_interpret_real for HFmode floats on Bigendian with
UNITS_PER_WORD>=4

 (with missing space)

OK with ChangeLog in proper form.


Err - but now offset can become negative?  Shouldn't it rather error out
before as it requires at least 4 bytes for big-endian?


I don't think the offset can ever be negative; my reasoning is:

total_bytes = GET_MODE_SIZE (TYPE_MODE (type)) [set just before loop]
bitpos < total_bytes * BITS_PER_UNIT [condition of for loop]
byte = (bitpos / BITS_PER_UNIT) & 3 [first statement inside for loop]

==> byte < 3 && byte < total_bytes
==> byte < MIN (3, total_bytes)
==> byte <= MIN (3, total_bytes - 1)


That said - the whole thing looks it doesn't expect GET_MODE_SIZE < 4
and your "fix" is just very obfuscated (if it really is a fix).

So, please cleanup the thing properly instead or at least add a big fat
comment.  There is the magic '3' in the line following yours as well.


Ok, I'll try to cleanup, I admit I'm not sure what all that code does 
(particularly if UNITS_PER_WORD < 4 !)...


--Alan

Re: [PATCH 4/7] Fix int overflow

[Ian Lance Taylor]

On Mon, Jul 6, 2015 at 12:36 PM, Mikhail Maltsev  wrote:
>
> diff --git a/libiberty/cp-demangle.c b/libiberty/cp-demangle.c
> index 44a0a9b..befa6b6 100644
> --- a/libiberty/cp-demangle.c
> +++ b/libiberty/cp-demangle.c
> @@ -103,6 +103,7 @@
>  #include "config.h"
>  #endif
>
> +#include 

All existing uses of limits.h in libiberty are inside #ifdef
HAVE_LIMITS_H.  See other files in the directory.


> @@ -1599,7 +1600,7 @@ d_source_name (struct d_info *di)
>struct demangle_component *ret;
>
>len = d_number (di);
> -  if (len <= 0)
> +  if (len <= 0 || len > INT_MAX)
>  return NULL;

This is not, in my opinion, the best way to write this kind of thing.
Instead, write something like

int ilen;


ilen = (int) len:
if ((long) ilen != len)
  return NULL;


But better still is to consider the larger context.  We want the
demangler to work the same on all hosts, if at all possible.
d_identifier is called exactly once.  Change it to take a parameter of
type long.  Don't worry about changing d_source_name.

Then look at the fact that d_number does not check for overflow.  We
should consider changing d_number to limit itself to 32-bit integers,
and to return an error indication on overflow.  From a quick glance I
don't see any need for the demangler to support numbers larger than 32
bits.  I think it's OK if we fail to demangle symbol names that are
more than 2 billion characters long.

Ian

Re: [PATCH 3/7] Fix trinary op

[Ian Lance Taylor]

On Tue, Jul 7, 2015 at 3:40 PM, Jeff Law  wrote:
>
> And a generic question on the testsuite -- presumably it turns on type
> demangling?I wanted to verify the flow through d_expression_1 was what I
> expected it to be and it took a while to realize that c++filt doesn't
> demangle types by default, thus Av32_f would demangle to Av32_f without ever
> getting into d_expression_1.

The testsuite passes DMGL_TYPES to the demangler (see
libiberty/testsuite/test-demangle.c).  The c++filt program does not
use DMGL_TYPES by defaut (you can turn it on with the -t option).

I don't know of anybody who actually uses the DMGL_TYPES support.  I
don't know why anybody would.

Ian

[Committed] S/390: Remove assertion in s390_init_frame_layout

[Andreas Krebbel]

Hi,

since r225260 the backend register elimination hooks also get invoked
after reload is completed e.g. from sched2. During register
elimination we call s390_init_frame_layout which is not supposed to be
invoked after reload.  We had an assertion here to make sure this does
not happen.  This got triggered and currently breaks bootstrap on
S/390.  With the attached patch s390_init_frame_layout just becomes a
NOP when invoked after reload is completed.

Committed to mainline.

Bye,

-Andreas-


gcc/ChangeLog:

2015-07-08  Andreas Krebbel  

* config/s390/s390.c (s390_init_frame_layout): Replace assertion
with early exit.

diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 4ef8e42..5715d89 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -9351,7 +9351,10 @@ s390_init_frame_layout (void)
   HOST_WIDE_INT frame_size;
   int base_used;
 
-  gcc_assert (!reload_completed);
+  /* After LRA the frame layout is supposed to be read-only and should
+ not be re-computed.  */
+  if (reload_completed)
+return;
 
   /* On S/390 machines, we may need to perform branch splitting, which
  will require both base and return address register.  We have no

Re: [PATCH, testcase, committed] Exit with zero status from g++.dg/ipa/pr61160-3.C

[Martin Jambor]

Hi,

apparently I have forgot to backport this to the 4.9 branch which was
now pointed out in a separate PR 61820.  The patch is obvious and
testcase-only, so I have done the backport now, after some basic
testing, so that I can close the bug.

Thanks,

Martin


On Tue, Jul 22, 2014 at 06:31:32PM +0200, Martin Jambor wrote:
> Hi,
> 
> in order to avoid spurious testsuite failures, I've checked in the
> following obvious patch so that the testcase always returns zero.  I
> have verified it still properly tests for non-existence of the bug.
> 
> Thanks,
> 
> Martin
> 
> 2014-07-22  Martin Jambor  
> 
>   PR ipa/61160
>   * g++.dg/ipa/pr61160-3.C (main): Return zero.
> 
> Index: gcc/testsuite/g++.dg/ipa/pr61160-3.C
> ===
> --- gcc/testsuite/g++.dg/ipa/pr61160-3.C  (revision 212914)
> +++ gcc/testsuite/g++.dg/ipa/pr61160-3.C  (working copy)
> @@ -33,5 +33,6 @@ void *test (MMixin & anExample)
>  int main ()
>  {
>CExample c;
> -  return (test (c) != &c);
> +  test (c);
> +  return 0;
>  }

[PATCH] PR target/66806: Don't pass/return vectors in registers for IAMCU

[H.J. Lu]

Vectors should be passed in memory for IAMCU.

OK for trunk?

H.J.
---
gcc/

PR target/66806
* config/i386/i386.c (function_arg_advance_32): Don't pass
vectors in registers for IAMCU.
(function_arg_32): Likewise.
(ix86_return_in_memory): Don't return vectors in registers for
IAMCU.

gcc/testsuite/

PR target/66806
* gcc.target/i386/pr66806.c: New test.
---
 gcc/config/i386/i386.c  |  6 +++---
 gcc/testsuite/gcc.target/i386/pr66806.c | 23 +++
 2 files changed, 26 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr66806.c

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 112eb1c..ca192a2 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -7552,7 +7552,7 @@ function_arg_advance_32 (CUMULATIVE_ARGS *cum, 
machine_mode mode,
 {
   /* Intel MCU psABI passes scalars and aggregates no larger than 8
 bytes in registers.  */
-  if (bytes <= 8)
+  if (!VECTOR_MODE_P (mode) && bytes <= 8)
goto pass_in_reg;
   return res;
 }
@@ -7809,7 +7809,7 @@ function_arg_32 (CUMULATIVE_ARGS *cum, machine_mode mode,
 {
   /* Intel MCU psABI passes scalars and aggregates no larger than 8
 bytes in registers.  */
-  if (bytes <= 8)
+  if (!VECTOR_MODE_P (mode) && bytes <= 8)
goto pass_in_reg;
   return NULL_RTX;
 }
@@ -8679,7 +8679,7 @@ ix86_return_in_memory (const_tree type, const_tree fntype 
ATTRIBUTE_UNUSED)
   /* Intel MCU psABI returns scalars and aggregates no larger than 8
 bytes in registers.  */
   if (TARGET_IAMCU)
-   return size > 8;
+   return VECTOR_MODE_P (mode) || size > 8;
 
   if (mode == BLKmode)
return true;
diff --git a/gcc/testsuite/gcc.target/i386/pr66806.c 
b/gcc/testsuite/gcc.target/i386/pr66806.c
new file mode 100644
index 000..211a04f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr66806.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-miamcu -mno-sse -mno-mmx -miamcu -Wno-psabi" } */
+
+typedef unsigned int V2SImode __attribute__((vector_size(8)));
+extern V2SImode data_V2SImode;
+
+V2SImode
+r_V2SImode (V2SImode x)
+{
+  return x;
+}
+
+void
+p_V2SImode (V2SImode x)
+{
+  data_V2SImode = x;
+}
+
+void 
+s_V2SImode (void)
+{
+  p_V2SImode (data_V2SImode);
+}
-- 
2.4.3

Re: [PATCH] PR target/66806: Don't pass/return vectors in registers for IAMCU

[Uros Bizjak]

On Wed, Jul 8, 2015 at 1:41 PM, H.J. Lu  wrote:
> Vectors should be passed in memory for IAMCU.
>
> OK for trunk?

Bootstrapped and regression tested?

Uros.

[PATCH] Fix PR66794

[Richard Biener]

Passes do not expect post-dominators being around and thus forget
to invalidate them properly.  Thus passes computing them have to
free them.  The patch fixes path-isolation and adds an assert so
this doesn't happen again.

Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk.

Richard.

2015-07-08  Richard Biener  

PR tree-optimization/66794
* passes.c (execute_function_todo): Assert that post-dominators
are not computed.
* gimple-ssa-isolate-paths.c (gimple_ssa_isolate_erroneous_paths):
Free post-dominators.

* gcc.dg/torture/pr66794.c: New testcase.

Index: gcc/passes.c
===
--- gcc/passes.c(revision 225534)
+++ gcc/passes.c(working copy)
@@ -1929,6 +1929,7 @@ execute_function_todo (function *fn, voi
   if (flags & TODO_rebuild_cgraph_edges)
 cgraph_edge::rebuild_edges ();
 
+  gcc_assert (dom_info_state (fn, CDI_POST_DOMINATORS) == DOM_NONE);
   /* If we've seen errors do not bother running any verifiers.  */
   if (!seen_error ())
 {
Index: gcc/gimple-ssa-isolate-paths.c
===
--- gcc/gimple-ssa-isolate-paths.c  (revision 225534)
+++ gcc/gimple-ssa-isolate-paths.c  (working copy)
@@ -488,10 +488,10 @@ gimple_ssa_isolate_erroneous_paths (void
   /* We scramble the CFG and loop structures a bit, clean up
  appropriately.  We really should incrementally update the
  loop structures, in theory it shouldn't be that hard.  */
+  free_dominance_info (CDI_POST_DOMINATORS);
   if (cfg_altered)
 {
   free_dominance_info (CDI_DOMINATORS);
-  free_dominance_info (CDI_POST_DOMINATORS);
   loops_state_set (LOOPS_NEED_FIXUP);
   return TODO_cleanup_cfg | TODO_update_ssa;
 }
Index: gcc/testsuite/gcc.dg/torture/pr66794.c
===
--- gcc/testsuite/gcc.dg/torture/pr66794.c  (revision 0)
+++ gcc/testsuite/gcc.dg/torture/pr66794.c  (working copy)
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-w" } */
+
+int a, *b, e;
+static int **c = &b;
+
+struct
+{
+  int f0;
+} d;
+
+int *
+fn1 ()
+{
+  int f, **g = &b;
+  e = a;
+  for (; a;)
+for (; d.f0; d.f0++)
+  ;
+  *g = &f;
+  return *c;
+}

Re: [PATCH] PR target/66806: Don't pass/return vectors in registers for IAMCU

[Uros Bizjak]

On Wed, Jul 8, 2015 at 1:41 PM, H.J. Lu  wrote:
> Vectors should be passed in memory for IAMCU.
>
> OK for trunk?
>
> H.J.
> ---
> gcc/
>
> PR target/66806
> * config/i386/i386.c (function_arg_advance_32): Don't pass
> vectors in registers for IAMCU.
> (function_arg_32): Likewise.
> (ix86_return_in_memory): Don't return vectors in registers for
> IAMCU.
>
> gcc/testsuite/
>
> PR target/66806
> * gcc.target/i386/pr66806.c: New test.

> +/* { dg-do compile { target ia32 } } */
> +/* { dg-options "-miamcu -mno-sse -mno-mmx -miamcu -Wno-psabi" } */

Double -miamcu.

Also, why Wno-psabi? We can check for the warning here, too.

Uros.

[PATCH] Fix PR66793

[Richard Biener]

The following fixes path-isolation to properly split the block
if it inserts a trap after a stmt ending a BB (in this case a noreturn 
stmt).

Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk.

Richard.

2015-07-08  Richard Biener  

PR tree-optimization/66793
* gimple-ssa-isolate-paths.c (insert_trap_and_remove_trailing_statemen):
Properly split the block after stmts ending it.

* gcc.dg/torture/pr66793.c: New testcase.

Index: gcc/gimple-ssa-isolate-paths.c
===
--- gcc/gimple-ssa-isolate-paths.c  (revision 225534)
+++ gcc/gimple-ssa-isolate-paths.c  (working copy)
@@ -103,7 +103,14 @@ insert_trap_and_remove_trailing_statemen
   if (walk_stmt_load_store_ops (stmt, (void *)op,
check_loadstore,
check_loadstore))
-gsi_insert_after (si_p, seq, GSI_NEW_STMT);
+{
+  gsi_insert_after (si_p, seq, GSI_NEW_STMT);
+  if (stmt_ends_bb_p (stmt))
+   {
+ split_block (gimple_bb (stmt), stmt);
+ return;
+   }
+}
   else
 gsi_insert_before (si_p, seq, GSI_NEW_STMT);
 
Index: gcc/testsuite/gcc.dg/torture/pr66793.c
===
--- gcc/testsuite/gcc.dg/torture/pr66793.c  (revision 0)
+++ gcc/testsuite/gcc.dg/torture/pr66793.c  (working copy)
@@ -0,0 +1,26 @@
+/* { dg-do link } */
+
+int a, b, c; 
+
+struct S0
+{
+  int f1;
+} *d; 
+
+void
+fn1 (struct S0 p)
+{
+  for (p.f1 = 0; p.f1 < 1; p.f1++)
+c = a && b ? a && b : 1; 
+  for (; c;)
+;
+}
+
+int
+main ()
+{
+  struct S0 **f = &d;
+  d = 0; 
+  fn1 (**f); 
+  return 0;
+}

[PATCH] Fix PR66805 - #pragma pack affecting gcov_info_type layout

[Richard Biener]

The following fixes #pragma pack effect leaking to all types built
from the middle-end (so possibly even vector types built by the
vectorizer?).  The PR in question is about gcov_info_type where
layout is affected and inconsistency between that and the libgcov.a
copy causes libgcov to crash.

As the way to communicate #pragma pack to stor-layout.c is already
a hack I couldn't think of a better solution like that below.

Bootstrap and regtest running on x86_64-unknown-linux-gnu.

Ok?

Thanks,
Richard.

2015-07-08  Richard Biener  

* stor-layout.h (reset_maximum_field_alignment): Declare.
* stor-layout.c (reset_maximum_field_alignment): New function.
* toplev.c: Include stor-layout.h.
(compile_file): Reset maximum_field_alignment after parsing.

Index: gcc/stor-layout.c
===
--- gcc/stor-layout.c   (revision 225534)
+++ gcc/stor-layout.c   (working copy)
@@ -59,6 +59,12 @@ tree sizetype_tab[(int) stk_type_kind_la
The value is measured in bits.  */
 unsigned int maximum_field_alignment = TARGET_DEFAULT_PACK_STRUCT * 
BITS_PER_UNIT;
 
+void
+reset_maximum_field_alignment (void)
+{
+  maximum_field_alignment = TARGET_DEFAULT_PACK_STRUCT * BITS_PER_UNIT;
+}
+
 /* Nonzero if all REFERENCE_TYPEs are internal and hence should be allocated
in the address spaces' address_mode, not pointer_mode.   Set only by
internal_reference_types called only by a front end.  */
Index: gcc/stor-layout.h
===
--- gcc/stor-layout.h   (revision 225534)
+++ gcc/stor-layout.h   (working copy)
@@ -118,4 +118,7 @@ extern tree variable_size (tree);
 /* Vector types need to check target flags to determine type.  */
 extern machine_mode vector_type_mode (const_tree);
 
+/* Reset maximum_field_alignment to its default.  */
+extern void reset_maximum_field_alignment (void);
+
 #endif  // GCC_STOR_LAYOUT_H
Index: gcc/toplev.c
===
--- gcc/toplev.c(revision 225534)
+++ gcc/toplev.c(working copy)
@@ -90,6 +90,7 @@ along with GCC; see the file COPYING3.
 #include "optabs.h"
 #include "tree-chkp.h"
 #include "omp-low.h"
+#include "stor-layout.h"
 
 #if defined(DBX_DEBUGGING_INFO) || defined(XCOFF_DEBUGGING_INFO)
 #include "dbxout.h"
@@ -553,6 +554,11 @@ compile_file (void)
 
   if (flag_syntax_only || flag_wpa)
 return;
+ 
+  /* Reset maximum_field_alignment, it can be adjusted by #pragma pack
+ and this shouldn't influence any types built by the middle-end
+ from now on (like gcov_info_type).  */
+  reset_maximum_field_alignment ();
 
   ggc_protect_identifiers = false;
 

[patch] Simplify signatures of std::list members: merge, splice, insert, erase

[Jonathan Wakely]

C++0x changed the signature of std::list::merge to take an rvalue
reference, and then LWG DR 1133 [1] added the lvalue reference
signature back as an overload. Our implementation follows that history
rather literally, as we changed list::merge to take an rvalue in C++0x
mode, then later [2] added back an overload taking an lvalue and
calling merge(std::move(__x)).

It seems to me that it would be simpler to consistently have the
lvalue version do all the work, and just make the rvalue one forward
to that. That's what patch1.txt does (the same change can be done to
debug and profile mode lists).

Any objections to this change?

patch2.txt then does the same thing for splice(), introducing a
__const_iterator typedef [3] to make the signatures consistent for
different language modes.

I think this makes the code more maintainable, as there are fewer #if
blocks with subtly different signatures.

Any objections to this one too, including doing the same for debug
mode and profile mode?


[1] http://cplusplus.github.io/LWG/lwg-defects.html#1133
[2] https://gcc.gnu.org/ml/gcc-patches/2009-12/msg00699.html
[3] https://gcc.gnu.org/ml/libstdc++/2014-08/msg00151.html
commit d37a4ae4a9e4883978f1817b01995c2608624070
Author: Jonathan Wakely 
Date:   Wed Jul 8 12:15:36 2015 +0100

* include/bits/list.tcc (list::merge): Always define lvalue overload.
* include/bits/stl_list.h (list::merge): Make rvalue overload forward
to lvalue overload.

diff --git a/libstdc++-v3/include/bits/list.tcc 
b/libstdc++-v3/include/bits/list.tcc
index 714d9b5..4b8418e 100644
--- a/libstdc++-v3/include/bits/list.tcc
+++ b/libstdc++-v3/include/bits/list.tcc
@@ -370,11 +370,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CONTAINER
   template
 void
 list<_Tp, _Alloc>::
-#if __cplusplus >= 201103L
-merge(list&& __x)
-#else
 merge(list& __x)
-#endif
 {
   // _GLIBCXX_RESOLVE_LIB_DEFECTS
   // 300. list::merge() specification incomplete
@@ -407,11 +403,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CONTAINER
 template 
   void
   list<_Tp, _Alloc>::
-#if __cplusplus >= 201103L
-  merge(list&& __x, _StrictWeakOrdering __comp)
-#else
   merge(list& __x, _StrictWeakOrdering __comp)
-#endif
   {
// _GLIBCXX_RESOLVE_LIB_DEFECTS
// 300. list::merge() specification incomplete
diff --git a/libstdc++-v3/include/bits/stl_list.h 
b/libstdc++-v3/include/bits/stl_list.h
index 409f1fc..d0f0fd6 100644
--- a/libstdc++-v3/include/bits/stl_list.h
+++ b/libstdc++-v3/include/bits/stl_list.h
@@ -1611,16 +1611,13 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
*  sorted order, leaving @a __x empty when complete.  Elements in
*  this list precede elements in @a __x that are equal.
*/
-#if __cplusplus >= 201103L
   void
-  merge(list&& __x);
+  merge(list&);
 
+#if __cplusplus >= 201103L
   void
-  merge(list& __x)
-  { merge(std::move(__x)); }
-#else
-  void
-  merge(list& __x);
+  merge(list&& __x)
+  { merge(__x); }
 #endif
 
   /**
@@ -1636,19 +1633,15 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
*  in this list precede elements in @a __x that are equivalent
*  according to StrictWeakOrdering().
*/
-#if __cplusplus >= 201103L
   template
 void
-merge(list&& __x, _StrictWeakOrdering __comp);
+merge(list&, _StrictWeakOrdering);
 
+#if __cplusplus >= 201103L
   template
 void
-merge(list& __x, _StrictWeakOrdering __comp)
-{ merge(std::move(__x), __comp); }
-#else
-  template
-void
-merge(list& __x, _StrictWeakOrdering __comp);
+merge(list&& __x, _StrictWeakOrdering __comp)
+{ merge(__x, __comp); }
 #endif
 
   /**
commit 682940254cdb55b30b76ce28d3910897bba6673a
Author: Jonathan Wakely 
Date:   Wed Jul 8 12:50:10 2015 +0100

* include/bits/list.tcc (list::insert, list::erase): Use
__const_iterator to make declarations consistent for C++98 and C++11.
* include/bits/stl_list.h (list::__const_iterator): Define.
(list::insert, list::erase): Use __const_iterator to make declarations
consistent for C++98 and C++11.
(list::splice): Likewise, and forward from the overloads taking
lvalues to the overloads taking rvalues, instead of vice versa.

diff --git a/libstdc++-v3/include/bits/list.tcc 
b/libstdc++-v3/include/bits/list.tcc
index 4b8418e..7421e02 100644
--- a/libstdc++-v3/include/bits/list.tcc
+++ b/libstdc++-v3/include/bits/list.tcc
@@ -98,11 +98,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CONTAINER
   template
 typename list<_Tp, _Alloc>::iterator
 list<_Tp, _Alloc>::
-#if __cplusplus >= 201103L
-insert(const_iterator __position, const value_type& __x)
-#else
-insert(iterator __position, const value_type& __x)
-#endif
+insert(__const_iterator __position, const value_type& __x)
 {
   _Node* __tmp = _M_create_node(__x);
   __tmp->_M_hook(__position._M_const_cast()._M_node);
@@ -147,11 +14

Re: [PATCH] Fix PR66805 - #pragma pack affecting gcov_info_type layout

[Richard Biener]

On Wed, 8 Jul 2015, Richard Biener wrote:

> 
> The following fixes #pragma pack effect leaking to all types built
> from the middle-end (so possibly even vector types built by the
> vectorizer?).  The PR in question is about gcov_info_type where
> layout is affected and inconsistency between that and the libgcov.a
> copy causes libgcov to crash.
> 
> As the way to communicate #pragma pack to stor-layout.c is already
> a hack I couldn't think of a better solution like that below.
> 
> Bootstrap and regtest running on x86_64-unknown-linux-gnu.
> 
> Ok?

Ok, so I found initial_max_fld_align and instead propose the following
simpler.

2015-07-08  Richard Biener  

* toplev.c (compile_file): Reset maximum_field_alignment after parsing.

Index: gcc/toplev.c
===
--- gcc/toplev.c(revision 225534)
+++ gcc/toplev.c(working copy)
@@ -553,6 +553,11 @@ compile_file (void)
 
   if (flag_syntax_only || flag_wpa)
 return;
+ 
+  /* Reset maximum_field_alignment, it can be adjusted by #pragma pack
+ and this shouldn't influence any types built by the middle-end
+ from now on (like gcov_info_type).  */
+  maximum_field_alignment = initial_max_fld_align * BITS_PER_UNIT;
 
   ggc_protect_identifiers = false;
 

Re: [PATCH] Fix PR66805 - #pragma pack affecting gcov_info_type layout

[Jakub Jelinek]

On Wed, Jul 08, 2015 at 01:58:38PM +0200, Richard Biener wrote:
> 
> The following fixes #pragma pack effect leaking to all types built
> from the middle-end (so possibly even vector types built by the
> vectorizer?).  The PR in question is about gcov_info_type where
> layout is affected and inconsistency between that and the libgcov.a
> copy causes libgcov to crash.
> 
> As the way to communicate #pragma pack to stor-layout.c is already
> a hack I couldn't think of a better solution like that below.
> 
> Bootstrap and regtest running on x86_64-unknown-linux-gnu.
> 
> Ok?
> 
> Thanks,
> Richard.
> 
> 2015-07-08  Richard Biener  
> 
>   * stor-layout.h (reset_maximum_field_alignment): Declare.
>   * stor-layout.c (reset_maximum_field_alignment): New function.
>   * toplev.c: Include stor-layout.h.
>   (compile_file): Reset maximum_field_alignment after parsing.

toplev.c already sets maximum_field_alignment directly, and to a different
value:
maximum_field_alignment = initial_max_fld_align * BITS_PER_UNIT;
so I'm not sure you need a new function.  And, shouldn't you reset to
maximum_field_alignment = initial_max_fld_align * BITS_PER_UNIT;
?  -fpack-struct= is an ABI changing option, so IMHO it should affect
even gcov_info_type etc.

Jakub

Re: [patch] Simplify signatures of std::list members: merge, splice, insert, erase

[Jonathan Wakely]

On 08/07/15 13:00 +0100, Jonathan Wakely wrote:

patch2.txt then does the same thing for splice(), introducing a
__const_iterator typedef [3] to make the signatures consistent for
different language modes.

I think this makes the code more maintainable, as there are fewer #if
blocks with subtly different signatures.

Any objections to this one too, including doing the same for debug
mode and profile mode?


Oops, I only tested the first patch, and the second one was a bit
over-eager and changed a return type unintentionally.

Here's the working (tested) version of the second patch.


commit dce62cc677adde73be0c1566492da4cd6df3e04d
Author: Jonathan Wakely 
Date:   Wed Jul 8 12:50:10 2015 +0100

* include/bits/list.tcc (list::insert, list::erase): Use
__const_iterator to make declarations consistent for C++98 and C++11.
* include/bits/stl_list.h (list::__const_iterator): Define.
(list::insert, list::erase): Use __const_iterator to make declarations
consistent for C++98 and C++11.
(list::splice): Likewise, and forward from the overloads taking
lvalues to the overloads taking rvalues, instead of vice versa.

diff --git a/libstdc++-v3/include/bits/list.tcc 
b/libstdc++-v3/include/bits/list.tcc
index 4b8418e..7421e02 100644
--- a/libstdc++-v3/include/bits/list.tcc
+++ b/libstdc++-v3/include/bits/list.tcc
@@ -98,11 +98,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CONTAINER
   template
 typename list<_Tp, _Alloc>::iterator
 list<_Tp, _Alloc>::
-#if __cplusplus >= 201103L
-insert(const_iterator __position, const value_type& __x)
-#else
-insert(iterator __position, const value_type& __x)
-#endif
+insert(__const_iterator __position, const value_type& __x)
 {
   _Node* __tmp = _M_create_node(__x);
   __tmp->_M_hook(__position._M_const_cast()._M_node);
@@ -147,11 +143,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CONTAINER
   template
 typename list<_Tp, _Alloc>::iterator
 list<_Tp, _Alloc>::
-#if __cplusplus >= 201103L
-erase(const_iterator __position) noexcept
-#else
-erase(iterator __position)
-#endif
+erase(__const_iterator __position) _GLIBCXX_NOEXCEPT
 {
   iterator __ret = iterator(__position._M_node->_M_next);
   _M_erase(__position._M_const_cast());
diff --git a/libstdc++-v3/include/bits/stl_list.h 
b/libstdc++-v3/include/bits/stl_list.h
index d0f0fd6..89fe404 100644
--- a/libstdc++-v3/include/bits/stl_list.h
+++ b/libstdc++-v3/include/bits/stl_list.h
@@ -537,6 +537,13 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
   using _Base::_M_get_node;
   using _Base::_M_get_Node_allocator;
 
+  // type used for positions in insert, erase etc.
+#if __cplusplus < 201103L
+  typedef iterator __const_iterator;
+#else
+  typedef const_iterator __const_iterator;
+#endif
+
   /**
*  @param  __args  An instance of user data.
*
@@ -1139,23 +1146,10 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
   template
 iterator
 emplace(const_iterator __position, _Args&&... __args);
+#endif
 
   /**
*  @brief  Inserts given value into %list before specified iterator.
-   *  @param  __position  A const_iterator into the %list.
-   *  @param  __x  Data to be inserted.
-   *  @return  An iterator that points to the inserted data.
-   *
-   *  This function will insert a copy of the given value before
-   *  the specified location.  Due to the nature of a %list this
-   *  operation can be done in constant time, and does not
-   *  invalidate iterators and references.
-   */
-  iterator
-  insert(const_iterator __position, const value_type& __x);
-#else
-  /**
-   *  @brief  Inserts given value into %list before specified iterator.
*  @param  __position  An iterator into the %list.
*  @param  __x  Data to be inserted.
*  @return  An iterator that points to the inserted data.
@@ -1166,8 +1160,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
*  invalidate iterators and references.
*/
   iterator
-  insert(iterator __position, const value_type& __x);
-#endif
+  insert(__const_iterator __position, const value_type& __x);
 
 #if __cplusplus >= 201103L
   /**
@@ -1304,11 +1297,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
*  any way.  Managing the pointer is the user's responsibility.
*/
   iterator
-#if __cplusplus >= 201103L
-  erase(const_iterator __position) noexcept;
-#else
-  erase(iterator __position);
-#endif
+  erase(__const_iterator __position) _GLIBCXX_NOEXCEPT;
 
   /**
*  @brief  Remove a range of elements.
@@ -1329,11 +1318,8 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
*  is the user's responsibility.
*/
   iterator
-#if __cplusplus >= 201103L
-  erase(const_iterator __first, const_iterator __last) noexcept
-#else
-  erase(iterator __first, iterator __last)
-#endif
+  erase(__const_iterator __first, __const_iterator __last)
+  _GLIBCXX_NOEXCEPT

Re: [PATCH] Fix PR66805 - #pragma pack affecting gcov_info_type layout

[Alexander Monakov]

The same bug was earlier reported as PR gcov-profile/43341:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=43341

Alexander

Re: [PATCH] Fix PR66805 - #pragma pack affecting gcov_info_type layout

[Richard Biener]

On Wed, 8 Jul 2015, Jakub Jelinek wrote:

> On Wed, Jul 08, 2015 at 01:58:38PM +0200, Richard Biener wrote:
> > 
> > The following fixes #pragma pack effect leaking to all types built
> > from the middle-end (so possibly even vector types built by the
> > vectorizer?).  The PR in question is about gcov_info_type where
> > layout is affected and inconsistency between that and the libgcov.a
> > copy causes libgcov to crash.
> > 
> > As the way to communicate #pragma pack to stor-layout.c is already
> > a hack I couldn't think of a better solution like that below.
> > 
> > Bootstrap and regtest running on x86_64-unknown-linux-gnu.
> > 
> > Ok?
> > 
> > Thanks,
> > Richard.
> > 
> > 2015-07-08  Richard Biener  
> > 
> > * stor-layout.h (reset_maximum_field_alignment): Declare.
> > * stor-layout.c (reset_maximum_field_alignment): New function.
> > * toplev.c: Include stor-layout.h.
> > (compile_file): Reset maximum_field_alignment after parsing.
> 
> toplev.c already sets maximum_field_alignment directly, and to a different
> value:
> maximum_field_alignment = initial_max_fld_align * BITS_PER_UNIT;
> so I'm not sure you need a new function.  And, shouldn't you reset to
> maximum_field_alignment = initial_max_fld_align * BITS_PER_UNIT;
> ?  -fpack-struct= is an ABI changing option, so IMHO it should affect
> even gcov_info_type etc.

That would support the 2nd patch variant.  Note that -fpack-struct
can be specified in optimize attributes...

Richard.

-- 
Richard Biener 
SUSE LINUX GmbH, GF: Felix Imendoerffer, Jane Smithard, Dilip Upmanyu, Graham 
Norton, HRB 21284 (AG Nuernberg)

Re: [PATCH] Fix PR66805 - #pragma pack affecting gcov_info_type layout

[Jakub Jelinek]

On Wed, Jul 08, 2015 at 02:40:33PM +0200, Richard Biener wrote:
> > toplev.c already sets maximum_field_alignment directly, and to a different
> > value:
> > maximum_field_alignment = initial_max_fld_align * BITS_PER_UNIT;
> > so I'm not sure you need a new function.  And, shouldn't you reset to
> > maximum_field_alignment = initial_max_fld_align * BITS_PER_UNIT;
> > ?  -fpack-struct= is an ABI changing option, so IMHO it should affect
> > even gcov_info_type etc.
> 
> That would support the 2nd patch variant.  Note that -fpack-struct
> can be specified in optimize attributes...

Yeah, the second patch LGTM.

Jakub

Re: [PATCH 15/16][fold-const.c] Fix bigendian HFmode in native_interpret_real

[Richard Biener]

On Wed, Jul 8, 2015 at 12:51 PM, Alan Lawrence  wrote:
> Richard Biener wrote:
>>
>> On Wed, Jul 8, 2015 at 12:07 AM, Jeff Law  wrote:
>>>
>>> On 07/07/2015 06:37 AM, Alan Lawrence wrote:
>
> [snip]

  Fix native_interpret_real for HFmode floats on Bigendian with
 UNITS_PER_WORD>=4

  (with missing space)
>>>
>>> OK with ChangeLog in proper form.
>>
>>
>> Err - but now offset can become negative?  Shouldn't it rather error out
>> before as it requires at least 4 bytes for big-endian?
>
>
> I don't think the offset can ever be negative; my reasoning is:
>
> total_bytes = GET_MODE_SIZE (TYPE_MODE (type)) [set just before loop]
> bitpos < total_bytes * BITS_PER_UNIT [condition of for loop]
> byte = (bitpos / BITS_PER_UNIT) & 3 [first statement inside for loop]
>
> ==> byte < 3 && byte < total_bytes
> ==> byte < MIN (3, total_bytes)
> ==> byte <= MIN (3, total_bytes - 1)
>
>> That said - the whole thing looks it doesn't expect GET_MODE_SIZE < 4
>> and your "fix" is just very obfuscated (if it really is a fix).
>>
>> So, please cleanup the thing properly instead or at least add a big fat
>> comment.  There is the magic '3' in the line following yours as well.
>
>
> Ok, I'll try to cleanup, I admit I'm not sure what all that code does
> (particularly if UNITS_PER_WORD < 4 !)...

Yeah, me neither - but I'm trying to at least make sure it doesn't get worse ;)

Richard.

> --Alan
>

Re: [PATCH, 2/2][PR66642] Add empty loop exit block in transform_to_exit_first_loop_alt

[Tom de Vries]

On 08/07/15 12:40, Andreas Schwab wrote:

Tom de Vries  writes:


* testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c (main): Test low
iteration count case.


../../../../libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c: In 
function 'main':
../../../../libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c:40:9: 
error: too few arguments to function 'f'
../../../../libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c:13:1: 
note: declared here



Hi,

Thanks for letting me know.

The failure is due to interference with the test-case bit of patch 'Use 
max_loop_iterations in transform_to_exit_first_loop_alt'.


Fixed and committed as obvious in attached patch.

Thanks,
- Tom

Fix libgomp.c/parloops-exit-first-loop-alt{,-3}.c testcases

2015-07-08  Tom de Vries  

	* testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c (main): Fix
	second call to f.
	* testsuite/libgomp.c/parloops-exit-first-loop-alt.c: Same.
---
 libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c | 2 +-
 libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c b/libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c
index 958e554..78365e8 100644
--- a/libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c
+++ b/libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt-3.c
@@ -37,7 +37,7 @@ main (void)
 abort ();
 
   /* Test low iteration count case.  */
-  res = f (10);
+  res = f (10, a);
   if (res != 25)
 abort ();
 
diff --git a/libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt.c b/libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt.c
index 557764d..9d94cf8 100644
--- a/libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt.c
+++ b/libgomp/testsuite/libgomp.c/parloops-exit-first-loop-alt.c
@@ -59,7 +59,7 @@ main (void)
 
   init ();
 
-  f (10);
+  f (10, a, b, c);
 
   for (i = 0; i < N; i++)
 {
-- 
1.9.1

Re: Tests for libgomp based on OpenMP Examples 4.0.2.

[Maxim Blumental]

Updated the attached files:  renamed also libgomp.c++ tests, corrected
ChangeLog.

2015-07-07 21:29 GMT+03:00 Ilya Verbin :
> On Tue, Jul 07, 2015 at 20:17:48 +0200, Jakub Jelinek wrote:
>> On Tue, Jul 07, 2015 at 08:08:16PM +0300, Maxim Blumental wrote:
>> > > Added 16 tests for simd construct and 10 for depend clause.
>>
>> Any new tests that aren't in Examples 4.0.* document should go one level
>> higher, to libgomp.{c,c++,fortran}/ directly.
>
> Actually, the examples 4.0.2 document contains simd-* and task_dep-* tests, 
> they
> are new in terms of examples-4 directory.
>
>   -- Ilya



-- 


-
Sincerely yours,
Maxim Blumental
2015-07-06 Maxim  Blumenthal  

* testsuite/libgomp.c++/examples-4/e.53.2.C: Renamed to...
* testsuite/libgomp.c++/examples-4/declare_target-2.C: ...this.
* testsuite/libgomp.c++/examples-4/e.51.5.C: Renamed to...
* testsuite/libgomp.c++/examples-4/target_data-5.C: ...this.
* testsuite/libgomp.c/examples-4/e.56.3.c: Renamed to...
* testsuite/libgomp.c/examples-4/array_sections-3.c: ...this.
* testsuite/libgomp.c/examples-4/e.56.4.c: Renamed to...
* testsuite/libgomp.c/examples-4/array_sections-4.c: ...this.
* testsuite/libgomp.c/examples-4/e.55.1.c: Renamed to...
* testsuite/libgomp.c/examples-4/async_target-1.c: ...this.
* testsuite/libgomp.c/examples-4/e.55.2.c: Renamed to...
* testsuite/libgomp.c/examples-4/async_target-2.c: ...this.
* testsuite/libgomp.c/examples-4/e.53.1.c: Renamed to...
* testsuite/libgomp.c/examples-4/declare_target-1.c: ...this.
* testsuite/libgomp.c/examples-4/e.53.3.c: Renamed to...
* testsuite/libgomp.c/examples-4/declare_target-3.c: ...this.
* testsuite/libgomp.c/examples-4/e.53.4.c: Renamed to...
* testsuite/libgomp.c/examples-4/declare_target-4.c: ...this.
* testsuite/libgomp.c/examples-4/e.53.5.c: Renamed to...
* testsuite/libgomp.c/examples-4/declare_target-5.c: ...this.
* testsuite/libgomp.c/examples-4/e.57.1.c: Renamed to...
* testsuite/libgomp.c/examples-4/device-1.c: ...this.
* testsuite/libgomp.c/examples-4/e.57.2.c: Renamed to...
* testsuite/libgomp.c/examples-4/device-2.c: ...this.
* testsuite/libgomp.c/examples-4/e.57.3.c: Renamed to...
* testsuite/libgomp.c/examples-4/device-3.c: ...this.
* testsuite/libgomp.c/examples-4/simd-1.c: A test for simd construct.
* testsuite/libgomp.c/examples-4/simd-2.c: Same.
* testsuite/libgomp.c/examples-4/simd-3.c: Same.
* testsuite/libgomp.c/examples-4/simd-4.c: Same.
* testsuite/libgomp.c/examples-4/simd-5.c: Same.
* testsuite/libgomp.c/examples-4/simd-6.c: Same.
* testsuite/libgomp.c/examples-4/simd-7.c: Same.
* testsuite/libgomp.c/examples-4/simd-8.c: Same.
* testsuite/libgomp.c/examples-4/e.50.1.c: Renamed to...
* testsuite/libgomp.c/examples-4/target-1.c: ...this.
* testsuite/libgomp.c/examples-4/e.50.2.c: Renamed to...
* testsuite/libgomp.c/examples-4/target-2.c: ...this.
* testsuite/libgomp.c/examples-4/e.50.3.c: Renamed to...
* testsuite/libgomp.c/examples-4/target-3.c: ...this.
* testsuite/libgomp.c/examples-4/e.50.4.c: Renamed to...
* testsuite/libgomp.c/examples-4/target-4.c: ...this.
* testsuite/libgomp.c/examples-4/e.50.5.c: Renamed to...
* testsuite/libgomp.c/examples-4/target-5.c: ...this.
* testsuite/libgomp.c/examples-4/e.51.1.c: Renamed to...
* testsuite/libgomp.c/examples-4/target_data-1.c: ...this.
* testsuite/libgomp.c/examples-4/e.51.2.c: Renamed to...
* testsuite/libgomp.c/examples-4/target_data-2.c: ...this.
* testsuite/libgomp.c/examples-4/e.51.3.c: Renamed to...
* testsuite/libgomp.c/examples-4/target_data-3.c: ...this.
* testsuite/libgomp.c/examples-4/e.51.4.c: Renamed to...
* testsuite/libgomp.c/examples-4/target_data-4.c: ...this.
* testsuite/libgomp.c/examples-4/e.51.6.c: Renamed to...
* testsuite/libgomp.c/examples-4/target_data-6.c: ...this.
* testsuite/libgomp.c/examples-4/e.51.7.c: Renamed to...
* testsuite/libgomp.c/examples-4/target_data-7.c: ...this.
* testsuite/libgomp.c/examples-4/e.52.1.c: Renamed to...
* testsuite/libgomp.c/examples-4/target_update-1.c: ...this.
* testsuite/libgomp.c/examples-4/e.52.2.c: Renamed to...
* testsuite/libgomp.c/examples-4/target_update-2.c: ...this.
* testsuite/libgomp.c/examples-4/task_dep-1.c: A test for task 
dependencies.
* testsuite/libgomp.c/examples-4/task_dep-2.c: Same.
* testsuite/libgomp.c/examples-4/task_dep-3.c: Same.
* testsuite/libgomp.c/examples-4/task_dep-4.c: Same.
* testsuite/libgomp.c/examples-4/task_dep-5.c: Same.
* testsuite/libgomp.c/examples-4/e.54.2.c: Renamed to...
* testsuite/libgomp.c/examples-4/teams-2.c: ...this.
* testsuite/libgomp.c/examples-4/e.54.3.c: Renamed to...
* testsuite/libgomp.c/examples-4/teams-3.c: ...this.
* testsuite/libgomp.c/examples-4/e.54.4.c: Renamed to...
* testsuite/libgomp.c/exampl

Re: Tests for libgomp based on OpenMP Examples 4.0.2.

[Maxim Blumental]

>The Examples-4/
>directory is supposed to only contain the tests from the 4.0.* examples
>document and no other tests.
All right: everything I added in it was only tests from the examples
document. Renamings were made in accordance with filenames from
GitHub.
> Any new tests that aren't in Examples 4.0.* document should go one level
> higher, to libgomp.{c,c++,fortran}/ directly.
There are no any such tests.

2015-07-08 15:50 GMT+03:00 Maxim Blumental :
> Updated the attached files:  renamed also libgomp.c++ tests, corrected
> ChangeLog.
>
> 2015-07-07 21:29 GMT+03:00 Ilya Verbin :
>> On Tue, Jul 07, 2015 at 20:17:48 +0200, Jakub Jelinek wrote:
>>> On Tue, Jul 07, 2015 at 08:08:16PM +0300, Maxim Blumental wrote:
>>> > > Added 16 tests for simd construct and 10 for depend clause.
>>>
>>> Any new tests that aren't in Examples 4.0.* document should go one level
>>> higher, to libgomp.{c,c++,fortran}/ directly.
>>
>> Actually, the examples 4.0.2 document contains simd-* and task_dep-* tests, 
>> they
>> are new in terms of examples-4 directory.
>>
>>   -- Ilya
>
>
>
> --
>
>
> -
> Sincerely yours,
> Maxim Blumental



-- 


-
Sincerely yours,
Maxim Blumental

[gomp4, committed] Add rewrite_virtuals_into_loop_closed_ssa

[Tom de Vries]

[ was: Re: [PING][PATCH, 1/2] Merge 
rewrite_virtuals_into_loop_closed_ssa from gomp4 branch ]


On 07/07/15 17:58, Tom de Vries wrote:

Bootstrapped reg-tested on x86_64.

Committed to trunk as attached.



Reverted related patches on gomp-4_0-branch, and committed this patch 
instead.


Thanks,
- Tom




+  add_phi_arg (nphi, final_loop, exit, UNKNOWN_LOCATION);
+}
+
   /* Check invariants of the loop closed ssa form for the USE in
BB.  */

   static void
diff --git a/gcc/tree-ssa-loop-manip.h b/gcc/tree-ssa-loop-manip.h
index ad0c381..9285718 100644
--- a/gcc/tree-ssa-loop-manip.h
+++ b/gcc/tree-ssa-loop-manip.h
@@ -25,6 +25,7 @@ typedef void (*transform_callback)(struct loop *,
void *);
   extern void create_iv (tree, tree, tree, struct loop *,
gimple_stmt_iterator *,
  bool, tree *, tree *);
   extern void rewrite_into_loop_closed_ssa (bitmap, unsigned);
+extern void rewrite_virtuals_into_loop_closed_ssa (struct loop *);
   extern void verify_loop_closed_ssa (bool);
   extern basic_block split_loop_exit_edge (edge);
   extern basic_block ip_end_pos (struct loop *);
-- 1.9.1









0001-Add-rewrite_virtuals_into_loop_closed_ssa.patch


Add rewrite_virtuals_into_loop_closed_ssa

2015-07-07  Tom de Vries

* tree-cfg.c (get_virtual_phi): New function.
* tree-cfg.h (get_virtual_phi): Declare.
* tree-ssa-loop-manip.c (replace_uses_in_dominated_bbs)
(rewrite_virtuals_into_loop_closed_ssa): New function.
* tree-ssa-loop-manip.h (rewrite_virtuals_into_loop_closed_ssa):
Declare.
* tree-parloops.c (replace_uses_in_bbs_by): Remove.
(transform_to_exit_first_loop_alt): Use
rewrite_virtuals_into_loop_closed_ssa.
---
  gcc/tree-cfg.c| 17 
  gcc/tree-cfg.h|  1 +
  gcc/tree-parloops.c   | 43 ---
  gcc/tree-ssa-loop-manip.c | 51 +++
  gcc/tree-ssa-loop-manip.h |  1 +
  5 files changed, 78 insertions(+), 35 deletions(-)

diff --git a/gcc/tree-cfg.c b/gcc/tree-cfg.c
index 94ed957..3ab3ab4 100644
--- a/gcc/tree-cfg.c
+++ b/gcc/tree-cfg.c
@@ -2623,6 +2623,23 @@ delete_tree_cfg_annotations (void)
vec_free (label_to_block_map_for_fn (cfun));
  }

+/* Return the virtual phi in BB.  */
+
+gphi *
+get_virtual_phi (basic_block bb)
+{
+  for (gphi_iterator gsi = gsi_start_phis (bb);
+   !gsi_end_p (gsi);
+   gsi_next (&gsi))
+{
+  gphi *phi = gsi.phi ();
+
+  if (virtual_operand_p (PHI_RESULT (phi)))
+   return phi;
+}
+
+  return NULL;
+}

  /* Return the first statement in basic block BB.  */

diff --git a/gcc/tree-cfg.h b/gcc/tree-cfg.h
index 2fc1e88..af58c80 100644
--- a/gcc/tree-cfg.h
+++ b/gcc/tree-cfg.h
@@ -59,6 +59,7 @@ extern bool simple_goto_p (gimple);
  extern bool stmt_ends_bb_p (gimple);
  extern bool assert_unreachable_fallthru_edge_p (edge);
  extern void delete_tree_cfg_annotations (void);
+extern gphi *get_virtual_phi (basic_block);
  extern gimple first_stmt (basic_block);
  extern gimple last_stmt (basic_block);
  extern gimple last_and_only_stmt (basic_block);
diff --git a/gcc/tree-parloops.c b/gcc/tree-parloops.c
index 21ed17b..4a2757d 100644
--- a/gcc/tree-parloops.c
+++ b/gcc/tree-parloops.c
@@ -1492,25 +1492,6 @@ replace_uses_in_bb_by (tree name, tree val, basic_block 
bb)
  }
  }

-/* Replace uses of NAME by VAL in blocks BBS.  */
-
-static void
-replace_uses_in_bbs_by (tree name, tree val, bitmap bbs)
-{
-  gimple use_stmt;
-  imm_use_iterator imm_iter;
-
-  FOR_EACH_IMM_USE_STMT (use_stmt, imm_iter, name)
-{
-  if (!bitmap_bit_p (bbs, gimple_bb (use_stmt)->index))
-   continue;
-
-  use_operand_p use_p;
-  FOR_EACH_IMM_USE_ON_STMT (use_p, imm_iter)
-   SET_USE (use_p, val);
-}
-}
-
  /* Do transformation from:

   :
@@ -1631,18 +1612,11 @@ transform_to_exit_first_loop_alt (struct loop *loop,
tree control = gimple_cond_lhs (cond_stmt);
edge e;

-  /* Gather the bbs dominated by the exit block.  */
-  bitmap exit_dominated = BITMAP_ALLOC (NULL);
-  bitmap_set_bit (exit_dominated, exit_block->index);
-  vec exit_dominated_vec
-= get_dominated_by (CDI_DOMINATORS, exit_block);
-
-  int i;
-  basic_block dom_bb;
-  FOR_EACH_VEC_ELT (exit_dominated_vec, i, dom_bb)
-bitmap_set_bit (exit_dominated, dom_bb->index);
-
-  exit_dominated_vec.release ();
+  /* Rewriting virtuals into loop-closed ssa normal form makes this
+ transformation simpler.  It also ensures that the virtuals are in
+ loop-closed ssa normal from after the transformation, which is required by
+ create_parallel_loop.  */
+  rewrite_virtuals_into_loop_closed_ssa (loop);

/* Create the new_header block.  */
basic_block new_header = split_block_before_cond_jump (exit->src);
@@ -1675,6 +1649,7 @@ transform_to_exit_first_loop_alt (struct loop *loop,
vec *v = redirect_edge_var_map_vector (post_inc_edge);
edge_var_map *vm;
gphi_i

Re: Drop -Wswitch-bool warning in function.c

[Marek Polacek]

On Wed, Jul 08, 2015 at 04:49:19PM +0800, Kito Cheng wrote:
> Bootstrapped & regression-tested on x86_64-linux-gnu :)
> 
> 2015-07-08  Kito Cheng  
> 
> * function.c (stack_protect_epilogue): Use if rather than switch for
> check targetm.have_stack_protect_test().

Do you really need this?  This should be just non-fatal warning in stage1,
and only if you compile with gcc-5, right?
You could also just cast the controlling expression of the switch to int to
suppress the warning.

Marek

Re: [PING][PATCH, 1/2] Merge rewrite_virtuals_into_loop_closed_ssa from gomp4 branch

[Richard Biener]

On Tue, 7 Jul 2015, Tom de Vries wrote:

> On 06/07/15 15:44, Richard Biener wrote:
> > Please add this to tree-cfg.[ch] instead, there are multiple places
> > in GCC that would benefit from it
> 
> Done.
> 
> A lot of calls to mark_virtual_phi_result_for_renaming look like they could be
> rewritten using get_virtual_phi.

Yeah - patches to make use of get_virtual_phi are pre-approved if they
look obvious enough.

Richard.

Re: [PATCH 3/7] Fix trinary op

[Tom Tromey]

> "Ian" == Ian Lance Taylor  writes:

Ian> I don't know of anybody who actually uses the DMGL_TYPES support.  I
Ian> don't know why anybody would.

It's used in gdb's DWARF reader, though I no longer remember why.

Tom

Re: [PATCH 3/7] Fix trinary op

[Ian Lance Taylor]

On Wed, Jul 8, 2015 at 6:42 AM, Tom Tromey  wrote:
>> "Ian" == Ian Lance Taylor  writes:
>
> Ian> I don't know of anybody who actually uses the DMGL_TYPES support.  I
> Ian> don't know why anybody would.
>
> It's used in gdb's DWARF reader, though I no longer remember why.

Looking at the code briefly, I bet everything would keep working if
the DMGL_TYPES were simply removed.

Ian

Re: [PATCH 3/4] Add libgomp plugin for Intel MIC

[Thomas Schwinge]

Hi!

On Tue, 21 Oct 2014 21:24:13 +0400, Ilya Verbin  wrote:
> This patch contains a plugin for libgomp and appropriate changes for 
> makefiles.
> 
> The plugin uses liboffloadmic_host.so to interact with the device (or with an
> emulator).  Also the patch contains offload_target_main executable, which is 
> the
> corresponding target side part of a libgomp plugin, and it uses
> liboffloadmic_target.so.
> 
> The plugin builds automatically with liboffloadmic.

With recent GCC trunk sources, builds of the Intel MIC Offload Plugin
fail as follows:

libtool: compile:  [...]/build-gcc/./gcc/xg++ [...] 
-I[...]/install/offload-x86_64-intelmicemul-linux-gnu/x86_64-intelmicemul-linux-gnu/liboffloadmic/plugin
 
-I[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include
 -c [...]/source-gcc/liboffloadmic/plugin/libgomp-plugin-intelmic.cpp  -fPIC 
-DPIC -o .libs/libgomp_plugin_intelmic_la-libgomp-plugin-intelmic.o
In file included from 
[...]/source-gcc/liboffloadmic/plugin/libgomp-plugin-intelmic.cpp:40:0:

[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1:
 error: narrowing conversion of '192' from 'int' to 'char' inside { } 
[-Wnarrowing]
 };
 ^

[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1:
 error: narrowing conversion of '192' from 'int' to 'char' inside { } 
[-Wnarrowing]

[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1:
 error: narrowing conversion of '164' from 'int' to 'char' inside { } 
[-Wnarrowing]
[many more]

Apart from the actual compilation error, it is surprising for me to see
the GCC build reference/depend on the Intel MIC offloading compiler's
installation directory (which I built and installed earlier),
[...]/install/offload-x86_64-intelmicemul-linux-gnu/ -- is that the
correct thing to do?  Shouldn't the GCC build be self-contained?  (I have
not yet made an attempt to understand how the target and device
liboffloadmic builds work together.)

This main_target_image.h file is coming from here:

> --- /dev/null
> +++ b/liboffloadmic/plugin/Makefile.am
> @@ -0,0 +1,123 @@
> +# Plugin for offload execution on Intel MIC devices.

> +main_target_image.h: offload_target_main
> + @echo -n "const int image_size = " > $@
> + @stat -c '%s' $< >> $@
> + @echo ";" >> $@
> + @echo "struct MainTargetImage {" >> $@
> + @echo "  int64_t size;" >> $@
> + @echo "  char name[sizeof \"offload_target_main\"];" >> $@
> + @echo "  char data[image_size];" >> $@
> + @echo "};" >> $@
> + @echo "extern \"C\" const MainTargetImage main_target_image = {" >> $@
> + @echo "  image_size, \"offload_target_main\"," >> $@
> + @cat $< | xxd -include >> $@
> + @echo "};" >> $@
> +
> +offload_target_main: $(liboffload_dir)/ofldbegin.o offload_target_main.o 
> $(liboffload_dir)/ofldend.o
> + $(CXX) $(AM_LDFLAGS) $^ -o $@
> +
> +offload_target_main.o: offload_target_main.cpp
> + $(CXX) $(AM_CXXFLAGS) $(AM_CPPFLAGS) -c $< -o $@

Here, I note that the xxd tool is being used, which in my distribution is
part of the Vim editor's package, which -- as far as I know -- is not
currently declared as a build dependency of GCC?

Anyway, all that aside for the moment -- OK to commit the following?

--- liboffloadmic/plugin/Makefile.am
+++ liboffloadmic/plugin/Makefile.am
@@ -69,7 +69,7 @@ main_target_image.h: offload_target_main
@echo "struct MainTargetImage {" >> $@
@echo "  int64_t size;" >> $@
@echo "  char name[sizeof \"offload_target_main\"];" >> $@
-   @echo "  char data[image_size];" >> $@
+   @echo "  uint8_t data[image_size];" >> $@
@echo "};" >> $@
@echo "extern \"C\" const MainTargetImage main_target_image = {" >> $@
@echo "  image_size, \"offload_target_main\"," >> $@


Grüße,
 Thomas


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Description: PGP signature

[PATCH] Teach genmatch.c to generate single-use restrictions from flags

[Richard Biener]

This introduces a :s flag to match expressions which enforces
the expression to have a single-use if(!) the simplified
expression is larger than one statement.

Thus with that we for example allow

  tem = a + 1;
  x = tem - 3;
  foo (tem);

to simplify to

  tem = a + 1;
  x = a - 2;
  foo (tem);

and more importantly not require "hacks" like

  /* Associate (p +p off1) +p off2 as (p +p (off1 + off2)).  */
  (simplify
!   (pointer_plus (pointer_plus@2 @0 @1) @3)
!   (if (single_use (@2)
!|| (TREE_CODE (@1) == INTEGER_CST && TREE_CODE (@3) == 
INTEGER_CST))
!(pointer_plus @0 (plus @1 @3

to allow the simplification if (plus @1 @3) will simplify further.

The trick is that generated code is changed like

 tree captures[4] ATTRIBUTE_UNUSED = {};
 captures[0] = op0;
 captures[1] = o20;
 captures[2] = o21;
 captures[3] = op1;
-/* #line 659 "/space/rguenther/tramp3d/trunk/gcc/match.pd" */
-if (single_use (captures[0]) || (TREE_CODE (captures[2]) == INTEGER_CST 
&& TREE
_CODE (captures[3]) == INTEGER_CST))
-{
+gimple_seq *lseq = seq;
+if (!single_use (captures[0])) lseq = NULL;
...

so in particular it disables all single-use restrictions if seq is NULL
anyway (that is enough of a restriction already).

Bootstrap / regtest running on x86_64-unknown-linux-gnu.

Richard.

2015-07-08  Richard Biener  

* genmatch.c (struct expr): Add force_single_use flag.
(capture_info::walk_match): Gather force_single_use captures.
(expr::gen_transform): Use possibly NULLified sequence.
(dt_simplify::gen): Apply single-use restrictions by NULLifying
seq if any constrained expr is not single-use.
(parser::parse_expr): Refactor to allow multiple flags.  Handle
's' flag to force an expression have a single-use if the pattern
simplifies to more than one statement.
* match.pd: Convert some single_use conditionals to :s flags.

Index: gcc/genmatch.c
===
*** gcc/genmatch.c  (revision 225556)
--- gcc/genmatch.c  (working copy)
*** struct expr : public operand
*** 491,497 
expr (id_base *operation_, bool is_commutative_ = false)
  : operand (OP_EXPR), operation (operation_),
ops (vNULL), expr_type (NULL), is_commutative (is_commutative_),
!   is_generic (false) {}
void append_op (operand *op) { ops.safe_push (op); }
/* The operator and its operands.  */
id_base *operation;
--- 491,497 
expr (id_base *operation_, bool is_commutative_ = false)
  : operand (OP_EXPR), operation (operation_),
ops (vNULL), expr_type (NULL), is_commutative (is_commutative_),
!   is_generic (false), force_single_use (false) {}
void append_op (operand *op) { ops.safe_push (op); }
/* The operator and its operands.  */
id_base *operation;
*** struct expr : public operand
*** 503,508 
--- 503,511 
bool is_commutative;
/* Whether the expression is expected to be in GENERIC form.  */
bool is_generic;
+   /* Whether pushing any stmt to the sequence should be conditional
+  on this expression having a single-use.  */
+   bool force_single_use;
virtual void gen_transform (FILE *f, const char *, bool, int,
  const char *, capture_info *,
  dt_operand ** = 0, bool = true);
*** commutate (operand *op)
*** 748,753 
--- 751,757 
for (unsigned i = 0; i < result.length (); ++i)
  {
expr *ne = new expr (e->operation);
+   ne->force_single_use = e->force_single_use;
for (unsigned j = 0; j < result[i].length (); ++j)
ne->append_op (result[i][j]);
ret.safe_push (ne);
*** commutate (operand *op)
*** 759,764 
--- 763,769 
for (unsigned i = 0; i < result.length (); ++i)
  {
expr *ne = new expr (e->operation);
+   ne->force_single_use = e->force_single_use;
// result[i].length () is 2 since e->operation is binary
for (unsigned j = result[i].length (); j; --j)
ne->append_op (result[i][j-1]);
*** lower_opt_convert (operand *o, enum tree
*** 812,822 
--- 817,829 
expr *ne = new expr (to_oper == CONVERT_EXPR
   ? get_operator ("CONVERT_EXPR")
   : get_operator ("VIEW_CONVERT_EXPR"));
+   ne->force_single_use = e->force_single_use;
ne->append_op (lower_opt_convert (e->ops[0], oper, to_oper, strip));
return ne;
  }
  
expr *ne = new expr (e->operation, e->is_commutative);
+   ne->force_single_use = e->force_single_use;
for (unsigned i = 0; i < e->ops.length (); ++i)
  ne->append_op (lower_opt_convert (e->ops[i], oper, to_oper, strip));
  
*** lower_cond (operand *o)
*** 952,957 
--- 959,965 
for (unsigned i = 0; i < result.length (); ++i)
  {
expr *ne = new expr (e->operation);
+   n

[PATCH, committed] PR jit/66783: improve error messages

[David Malcolm]

Tested with "make check-jit"; jit.sum remains at 8494 passes.

Committed to trunk as r225557.

gcc/jit/ChangeLog:
PR jit/66783
* libgccjit.c (gcc_jit_context_new_field): Show name of field in
"unknown size" error message.
(gcc_jit_struct_set_fields): Show name of struct in error message.
(gcc_jit_context_new_global): Show name of global in
"unknown size" error message.
(gcc_jit_function_new_local): Likewise for local.

gcc/testsuite/ChangeLog:
PR jit/66783
* jit.dg/test-error-gcc_jit_context_new_field-opaque-struct.c
(verify_code): Update expected error message.
* jit.dg/test-error-gcc_jit_context_new_global-opaque-struct.c
(verify_code): Likewise.
* jit.dg/test-error-gcc_jit_function_new_local-opaque-struct.c
(verify_code): Likewise.
---
 gcc/jit/libgccjit.c| 22 +++---
 ...error-gcc_jit_context_new_field-opaque-struct.c |  2 +-
 ...rror-gcc_jit_context_new_global-opaque-struct.c |  2 +-
 ...rror-gcc_jit_function_new_local-opaque-struct.c |  2 +-
 4 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/gcc/jit/libgccjit.c b/gcc/jit/libgccjit.c
index 85d9f62..eee513f 100644
--- a/gcc/jit/libgccjit.c
+++ b/gcc/jit/libgccjit.c
@@ -543,10 +543,11 @@ gcc_jit_context_new_field (gcc_jit_context *ctxt,
   /* LOC can be NULL.  */
   RETURN_NULL_IF_FAIL (type, ctxt, loc, "NULL type");
   RETURN_NULL_IF_FAIL (name, ctxt, loc, "NULL name");
-  RETURN_NULL_IF_FAIL_PRINTF1 (
+  RETURN_NULL_IF_FAIL_PRINTF2 (
 type->has_known_size (),
 ctxt, loc,
-"type has unknown size (type: %s)",
+"unknown size for field \"%s\" (type: %s)",
+name,
 type->get_debug_string ());
 
   return (gcc_jit_field *)ctxt->new_field (loc, type, name);
@@ -662,7 +663,12 @@ gcc_jit_struct_set_fields (gcc_jit_struct *struct_type,
 RETURN_IF_FAIL (fields, ctxt, loc, "NULL fields ptr");
   for (int i = 0; i < num_fields; i++)
 {
-  RETURN_IF_FAIL (fields[i], ctxt, loc, "NULL field ptr");
+  RETURN_IF_FAIL_PRINTF2 (
+   fields[i],
+   ctxt, loc,
+   "%s: NULL field ptr at index %i",
+   struct_type->get_debug_string (),
+   i);
   RETURN_IF_FAIL_PRINTF2 (
NULL == fields[i]->get_container (),
ctxt, loc,
@@ -1038,10 +1044,11 @@ gcc_jit_context_new_global (gcc_jit_context *ctxt,
 kind);
   RETURN_NULL_IF_FAIL (type, ctxt, loc, "NULL type");
   RETURN_NULL_IF_FAIL (name, ctxt, loc, "NULL name");
-  RETURN_NULL_IF_FAIL_PRINTF1 (
+  RETURN_NULL_IF_FAIL_PRINTF2 (
 type->has_known_size (),
 ctxt, loc,
-"type has unknown size (type: %s)",
+"unknown size for global \"%s\" (type: %s)",
+name,
 type->get_debug_string ());
 
   return (gcc_jit_lvalue *)ctxt->new_global (loc, kind, type, name);
@@ -1839,10 +1846,11 @@ gcc_jit_function_new_local (gcc_jit_function *func,
   "Cannot add locals to an imported function");
   RETURN_NULL_IF_FAIL (type, ctxt, loc, "NULL type");
   RETURN_NULL_IF_FAIL (name, ctxt, loc, "NULL name");
-  RETURN_NULL_IF_FAIL_PRINTF1 (
+  RETURN_NULL_IF_FAIL_PRINTF2 (
 type->has_known_size (),
 ctxt, loc,
-"type has unknown size (type: %s)",
+"unknown size for local \"%s\" (type: %s)",
+name,
 type->get_debug_string ());
 
   return (gcc_jit_lvalue *)func->new_local (loc, type, name);
diff --git 
a/gcc/testsuite/jit.dg/test-error-gcc_jit_context_new_field-opaque-struct.c 
b/gcc/testsuite/jit.dg/test-error-gcc_jit_context_new_field-opaque-struct.c
index c4e1448..fb4e54d 100644
--- a/gcc/testsuite/jit.dg/test-error-gcc_jit_context_new_field-opaque-struct.c
+++ b/gcc/testsuite/jit.dg/test-error-gcc_jit_context_new_field-opaque-struct.c
@@ -27,5 +27,5 @@ verify_code (gcc_jit_context *ctxt, gcc_jit_result *result)
   /* Verify that the correct error message was emitted.  */
   CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt),
  "gcc_jit_context_new_field:"
- " type has unknown size (type: struct opaque)");
+ " unknown size for field \"f_opaque\" (type: struct 
opaque)");
 }
diff --git 
a/gcc/testsuite/jit.dg/test-error-gcc_jit_context_new_global-opaque-struct.c 
b/gcc/testsuite/jit.dg/test-error-gcc_jit_context_new_global-opaque-struct.c
index 5f096af..539b94e 100644
--- a/gcc/testsuite/jit.dg/test-error-gcc_jit_context_new_global-opaque-struct.c
+++ b/gcc/testsuite/jit.dg/test-error-gcc_jit_context_new_global-opaque-struct.c
@@ -28,5 +28,5 @@ verify_code (gcc_jit_context *ctxt, gcc_jit_result *result)
   /* Verify that the correct error message was emitted.  */
   CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt),
  "gcc_jit_context_new_global:"
- " type has unknown size (type: struct opaque)");
+ " unknown size for global \"instance_of_opaque\" (type: 
struct opaque)");
 }
diff --git 
a/gcc/testsui

Re: [gomp] Move openacc vector& worker single handling to RTL

[Nathan Sidwell]

On 07/07/15 10:22, Jakub Jelinek wrote:


I agree that fork/join might be less confusing.


this version is the great renaming.  I've added fork & join internal fns.  In 
the PTX backend I've added 4 new unspecs:


fork -- the final single mode insn
forked -- the first partitioned mode insn
joining -- the last partitioned mode insn
join -- the first single mode insn

Not all partitionings need all four markers.  I've renamed the loop data 
structures to 'parallel' and similar, because that's actually what they are 
representing -- parallel regions.  The fact those regions contain loops is 
irrelevant to the task at hand.




nathan

2015-07-08  Nathan Sidwell  

Infrastructure:
* gimple.h (gimple_call_internal_unique_p): Declare.
* gimple.c (gimple_call_same_target_p): Add check for
gimple_call_internal_unique_p.
* internal-fn.c (gimple_call_internal_unique_p): New.
* omp-low.h (OACC_LOOP_MASK): Define here...
* omp-low.c (OACC_LOOP_MASK): ... not here.
* tree-ssa-threadedge.c (record_temporary_equivalences_from_stmts):
Add check for gimple_call_internal_unique_p.
* tree-ssa-tail-merge.c (same_succ_def::equal): Add EQ check for
the gimple statements.

Additions:
* internal-fn.def (GOACC_MODES, GOACC_FORK, GOACC_JOIN): New.
* internal-fn.c (gimple_call_internal_unique_p): Add check for
IFN_GOACC_FORK, IFN_GOACC_JOIN.
(expand_GOACC_MODES, expand_GOACC_FORK, expand_GOACC_JOIN): New.
* omp-low.c (gen_oacc_fork, gen_oacc_join): New.
(expand_omp_for_static_nochunk): Add oacc loop fork & join calls.
(expand_omp_for_static_chunk): Likewise.
* config/nvptx/nvptx-protos.h (nvptx_expand_oacc_fork,
nvptx_expand_oacc_join): Declare.
* config/nvptx/nvptx.md (UNSPEC_BIT_CONV, UNSPEC_BROADCAST,
UNSPEC_BR_UNIFIED): New unspecs.
(UNSPECV_MODES, UNSPECV_FORK, UNSPECV_FORKED, UNSPECV_JOINING,
UNSPECV_JOIN, UNSPECV_BR_HIDDEN): New.
(BITS, BITD): New mode iterators.
(br_true_hidden, br_false_hidden, br_uni_true, br_uni_false): New
branches.
(oacc_modes, nvptx_fork, nvptx_forked, nvptx_joining, nvptx_join):
New insns.
(oacc_fork, oacc_join): New expand
(nvptx_broadcast): New insn.
(unpacksi2, packsi2): New insns.
(worker_load, worker_store): New insns.
(nvptx_barsync): Renamed from ...
(threadbarrier_insn): ... here.
* config/nvptx/nvptx.c: Include hash-map,h, dominance.h, cfg.h &
omp-low.h.
(worker_bcast_hwm, worker_bcast_align, worker_bcast_name,
worker_bcast_sym): New.
(nvptx_option_override): Initialize worker_bcast_sym.
(nvptx_expand_oacc_fork, nvptx_expand_oacc_join): New.
(nvptx_gen_unpack, nvptx_gen_pack): New.
(struct wcast_data_t, propagate_mask): New types.
(nvptx_gen_vcast, nvptx_gen_wcast): New.
(nvptx_print_operand):  Change 'U' specifier to look at operand
itself.
(struct parallel): New structs.
(parallel::parallel, parallel::~parallel): Ctor & dtor.
(bb_insn_map_t): New map.
(insn_bb_t, insn_bb_vec_t): New tuple & vector of.
(nvptx_split_blocks, nvptx_discover_pre): New.
(bb_par_t, bb_par_vec_t); New tuple & vector of.
(nvptx_dump_pars,nvptx_discover_pars): New.
(nvptx_propagate, vprop_gen, nvptx_vpropagate, wprop_gen,
nvptx_wpropagate): New.
(nvptx_wsync): New.
(nvptx_single, nvptx_skip_par): New.
(nvptx_process_pars): New.
(nvptx_neuter_pars): New.
(nvptx_reorg): Add liveness DF problem.  Call nvptx_split_blocks,
nvptx_discover_pars, nvptx_process_pars & nvptx_neuter_pars.
(nvptx_cannot_copy_insn): Check for broadcast, sync, fork& join insns.
(nvptx_file_end): Output worker broadcast array definition.

Deletions:
* builtins.c (expand_oacc_thread_barrier): Delete.
(expand_oacc_thread_broadcast): Delete.
(expand_builtin): Adjust.
* gimple.c (struct gimple_statement_omp_parallel_layout): Remove
broadcast_array member.
(gimple_omp_target_broadcast_array): Delete.
(gimple_omp_target_set_broadcast_array): Delete.
* omp-low.c (omp_region): Remove broadcast_array member.
(oacc_broadcast): Delete.
(build_oacc_threadbarrier): Delete.
(oacc_loop_needs_threadbarrier_p): Delete.
(oacc_alloc_broadcast_storage): Delete.
(find_omp_target_region): Remove call to
gimple_omp_target_broadcast_array.
(enclosing_target_region, required_predication_mask,
generate_vector_broadcast, generate_oacc_broadcast,
make_predication_test, predicate_bb, find_predicatable_bbs,
predicate_omp_regions): Delete.
(use, gen, live_in): Delete.
(populate_loop_live_in, oacc_populate_live

Re: [PATCH 2/4 v2: part 2] libcpp: Replace macro usage with C++ constructs

[Thomas Schwinge]

Hi!

On Tue,  5 May 2015 14:21:13 -0400, David Malcolm  wrote:
> libcpp/ChangeLog:
>   * include/line-map.h (MAX_SOURCE_LOCATION): Convert from a macro
>   to a const source_location.
>   (RESERVED_LOCATION_COUNT): Likewise.
>   [...]

> --- a/libcpp/include/line-map.h
> +++ b/libcpp/include/line-map.h

>  /* This is the highest possible source location encoded within an
> ordinary or macro map.  */
> -#define MAX_SOURCE_LOCATION 0x7FFF
> +const source_location MAX_SOURCE_LOCATION = 0x7FFF;

>  /* source_location values from 0 to RESERVED_LOCATION_COUNT-1 will
> be reserved for libcpp user as special values, no token from libcpp
> will contain any of those locations.  */
> -#define RESERVED_LOCATION_COUNT  2
> +const int RESERVED_LOCATION_COUNT = 2;

That's not quite what the ChangeLog says ;-) -- now committed in r225558,
as obvious:

commit a5ea4da319fa2c7e9dd28e86bb69637a82e8e551
Author: tschwinge 
Date:   Wed Jul 8 14:48:11 2015 +

Address -Wsign-compare diagnostics

... which have been introduced in r223152, for example hundreds of:

[...]/gcc/input.h:37:12: warning: comparison between signed and 
unsigned integer expressions [-Wsign-compare]

libcpp/
* include/line-map.h (RESERVED_LOCATION_COUNT): Change type to
source_location.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225558 
138bc75d-0d04-0410-961f-82ee72b054a4
---
 libcpp/ChangeLog  |5 +
 libcpp/include/line-map.h |2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git libcpp/ChangeLog libcpp/ChangeLog
index 2d2893e..e72b535 100644
--- libcpp/ChangeLog
+++ libcpp/ChangeLog
@@ -1,3 +1,8 @@
+2015-07-08  Thomas Schwinge  
+
+   * include/line-map.h (RESERVED_LOCATION_COUNT): Change type to
+   source_location.
+
 2015-07-02  Paolo Carlini  
 
PR preprocessor/53690
diff --git libcpp/include/line-map.h libcpp/include/line-map.h
index 4155156..bc747c1 100644
--- libcpp/include/line-map.h
+++ libcpp/include/line-map.h
@@ -870,7 +870,7 @@ bool linemap_location_from_macro_expansion_p (const struct 
line_maps *,
 /* source_location values from 0 to RESERVED_LOCATION_COUNT-1 will
be reserved for libcpp user as special values, no token from libcpp
will contain any of those locations.  */
-const int RESERVED_LOCATION_COUNT = 2;
+const source_location RESERVED_LOCATION_COUNT = 2;
 
 /* Converts a map and a source_location to source line.  */
 inline linenum_type


Grüße,
 Thomas


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Description: PGP signature

Re: [C++/66443] virtual base of abstract class

[Nathan Sidwell]

On 06/30/15 19:21, Nathan Sidwell wrote:

On 06/30/15 00:19, Jason Merrill wrote:

On 06/29/2015 06:57 PM, Nathan Sidwell wrote:

* method.c (synthesized_method_walk): Skip virtual bases of
abstract classes in C++14 mode.


Let's not limit this to C++14 mode; most DRs apply to earlier standards as well.


curiously opening it up leads to some test failures related to determining the 
exception specifier for implicit ctors and dtors.  Not had time to investigate 
that yet ...


nathan

Patch to make dwarf2 tests pass when dwarf-2 is not default

[Carlos Sánchez de La Lama]

Currently, most tests in g++.dg/debug/dwarf2 include a "dg-options" line
which passes "-g" to the compiler. This overrides the "-gdwarf-2" that
appears in DEFAULT_CFLAGS in dwarf2.exp.

As a consequence, default debug information is generated, which in
systems when dwarf-2 is not the default makes al these tests fail.
IMHO, "dg-options" should include "-gdwarf-2" instead of plain "-g".

I detected this wile running "make check" on my
powerpc-apple-darwin8.11.0 for gcc-4.8.4. Patch is for trunk, however.

Carlos

2015-07-08  Carlos Sánchez de La Lama  

* g++.dg/debug/dwarf2/*.C: generate dwarf-2 debug information
even when dwarf-2 is not the default.

*** gcc/testsuite/g++.dg/debug/dwarf2/accessibility1.C
--- gcc/testsuite/g++.dg/debug/dwarf2/accessibility1.C	2015-07-08 14:21:09.0 +0200
***
*** 1,6 
  // PR debug/44668
  // { dg-do compile }
! // { dg-options "-g -dA" }
  
  struct C
  {
--- 1,6 
  // PR debug/44668
  // { dg-do compile }
! // { dg-options "-gdwarf-2 -dA" }
  
  struct C
  {
*** gcc/testsuite/g++.dg/debug/dwarf2/auto1.C
--- gcc/testsuite/g++.dg/debug/dwarf2/auto1.C	2015-07-08 15:56:07.0 +0200
***
*** 1,6 
  // PR c++/53756
  // { dg-do compile { target c++14 } }
! // { dg-options "-g -dA -fno-debug-types-section" }
  // We're looking for something like
  
  // .uleb128 0x3# (DIE (0x33) DW_TAG_subprogram)
--- 1,6 
  // PR c++/53756
  // { dg-do compile { target c++14 } }
! // { dg-options "-gdwarf-2 -dA -fno-debug-types-section" }
  // We're looking for something like
  
  // .uleb128 0x3# (DIE (0x33) DW_TAG_subprogram)
*** gcc/testsuite/g++.dg/debug/dwarf2/block.C
--- gcc/testsuite/g++.dg/debug/dwarf2/block.C	2015-07-08 15:56:24.0 +0200
***
*** 1,6 
  // Compiler should not generate too many lexical blocks for this function.
  // { dg-do compile { target { i?86-*-* x86_64-*-* } } }
! // { dg-options "-O0 -fno-exceptions -g -dA" }
  
  union UElement {
  void* pointer;
--- 1,6 
  // Compiler should not generate too many lexical blocks for this function.
  // { dg-do compile { target { i?86-*-* x86_64-*-* } } }
! // { dg-options "-O0 -fno-exceptions -gdwarf-2 -dA" }
  
  union UElement {
  void* pointer;
*** gcc/testsuite/g++.dg/debug/dwarf2/cdtor-1.C
--- gcc/testsuite/g++.dg/debug/dwarf2/cdtor-1.C	2015-07-08 14:21:09.0 +0200
***
*** 1,5 
  // origin PR debug/49047
! // { dg-options "-g -dA -fno-merge-debug-strings" }
  // { dg-do compile }
  
  struct K
--- 1,5 
  // origin PR debug/49047
! // { dg-options "-gdwarf-2 -dA -fno-merge-debug-strings" }
  // { dg-do compile }
  
  struct K
*** gcc/testsuite/g++.dg/debug/dwarf2/deallocator.C
--- gcc/testsuite/g++.dg/debug/dwarf2/deallocator.C	2015-07-08 15:56:38.0 +0200
***
*** 5,11 
  // FE generated debug info, without losing generality, only x86
  // assembly is scanned in this test.
  // { dg-do compile { target { i?86-*-* x86_64-*-* } } }
! // { dg-options "-O2 -fno-exceptions -g -dA" }
  
  struct t {
t ();
--- 5,11 
  // FE generated debug info, without losing generality, only x86
  // assembly is scanned in this test.
  // { dg-do compile { target { i?86-*-* x86_64-*-* } } }
! // { dg-options "-O2 -fno-exceptions -gdwarf-2 -dA" }
  
  struct t {
t ();
*** gcc/testsuite/g++.dg/debug/dwarf2/enum1.C
--- gcc/testsuite/g++.dg/debug/dwarf2/enum1.C	2015-07-08 15:27:41.0 +0200
***
*** 1,5 
  // { dg-do compile { target c++11 } }
! // { dg-options "-g -dA -gno-strict-dwarf" }
  // { dg-final { scan-assembler-times "DIE\[^\n\r\]*DW_TAG_enumeration_type" 3 } }
  // { dg-final { scan-assembler-times " DW_AT_enum_class" 2 } }
  
--- 1,5 
  // { dg-do compile { target c++11 } }
! // { dg-options "-gdwarf-2 -dA -gno-strict-dwarf" }
  // { dg-final { scan-assembler-times "DIE\[^\n\r\]*DW_TAG_enumeration_type" 3 } }
  // { dg-final { scan-assembler-times " DW_AT_enum_class" 2 } }
  
*** gcc/testsuite/g++.dg/debug/dwarf2/explicit-constructor.C
--- gcc/testsuite/g++.dg/debug/dwarf2/explicit-constructor.C	2015-07-08 15:28:38.0 +0200
***
*** 1,7 
  // Contributed by Dodji Seketeli 
  // Origin: PR c++
  // { dg-do compile }
! // { dg-options "-O -g -dA -gno-strict-dwarf -fno-debug-types-section" }
  // { dg-final { scan-assembler-times "DW_AT_explicit" 2 } }
  
  struct Foo
--- 1,7 
  // Contributed by Dodji Seketeli 
  // Origin: PR c++
  // { dg-do compile }
! // { dg-options "-O -gdwarf-2 -dA -gno-strict-dwarf -fno-debug-types-section" }
  // { dg-final { scan-assembler-times "DW_AT_explicit" 2 } }
  
  struct Foo
*** gcc/testsuite/g++.dg/debug/dwarf2/global-used-types-1.C
--- gcc/testsuite/g++.dg/debug/dwarf2/global-used-types-1.C	2015-07-08 15:29:44.0 +0200
***
*** 1,5 
  // Contributed by Dodji Seketeli 
! // { dg-options "-g -dA -fno-merge-debug-strings -fno-debug-types-section" }
  // { dg-do com

[PATCH, committed] fix comments in a jit testcase

[David Malcolm]

Fix a copy-and-paste error.

Tested with "make check-jit"; jit.sum remains at 8494 passes.

Committed to trunk as r225559.

gcc/testsuite/ChangeLog:
* jit.dg/test-error-gcc_jit_block_end_with_switch-NULL-case.c: Fix
comments.
---
 ...t-error-gcc_jit_block_end_with_switch-NULL-case.c | 20 
 1 file changed, 4 insertions(+), 16 deletions(-)

diff --git 
a/gcc/testsuite/jit.dg/test-error-gcc_jit_block_end_with_switch-NULL-case.c 
b/gcc/testsuite/jit.dg/test-error-gcc_jit_block_end_with_switch-NULL-case.c
index 07a9848..009ad66 100644
--- a/gcc/testsuite/jit.dg/test-error-gcc_jit_block_end_with_switch-NULL-case.c
+++ b/gcc/testsuite/jit.dg/test-error-gcc_jit_block_end_with_switch-NULL-case.c
@@ -6,25 +6,12 @@
 
 #include "harness.h"
 
+/* Try to create a switch statement with a NULL case, so that
+   we can verify that we get a sane error message.  */
+
 void
 create_code (gcc_jit_context *ctxt, void *user_data)
 {
-  /* Let's try to inject the equivalent of:
-  int
-  test_switch (int x)
-  {
-   switch (x)
- {
- case x:
-return 3;
-
- default:
-return 10;
- }
-  }
-  and verify that we get a sane error about the non-const
-  case.
-   */
   gcc_jit_type *t_int =
 gcc_jit_context_get_type (ctxt, GCC_JIT_TYPE_INT);
   gcc_jit_type *return_type = t_int;
@@ -44,6 +31,7 @@ create_code (gcc_jit_context *ctxt, void *user_data)
   gcc_jit_block *b_default =
 gcc_jit_function_new_block (func, "default");
 
+  /* Erroneous NULL case.  */
   gcc_jit_case *cases[1] = {
 NULL
   };
-- 
1.8.5.3

Re: [PATCH] PR target/66806: Don't pass/return vectors in registers for IAMCU

[H.J. Lu]

On Wed, Jul 8, 2015 at 4:49 AM, Uros Bizjak  wrote:
> On Wed, Jul 8, 2015 at 1:41 PM, H.J. Lu  wrote:
>> Vectors should be passed in memory for IAMCU.
>>
>> OK for trunk?
>>
>> H.J.
>> ---
>> gcc/
>>
>> PR target/66806
>> * config/i386/i386.c (function_arg_advance_32): Don't pass
>> vectors in registers for IAMCU.
>> (function_arg_32): Likewise.
>> (ix86_return_in_memory): Don't return vectors in registers for
>> IAMCU.
>>
>> gcc/testsuite/
>>
>> PR target/66806
>> * gcc.target/i386/pr66806.c: New test.
>
>> +/* { dg-do compile { target ia32 } } */
>> +/* { dg-options "-miamcu -mno-sse -mno-mmx -miamcu -Wno-psabi" } */
>
> Double -miamcu.
>
> Also, why Wno-psabi? We can check for the warning here, too.
>

Here is the updated patch.  Since IA MCU won't change ABI for vectors,
we shouldn't issue any warnings.

Tested on Linux/x86-64.  OK for trunk?

Thanks.


-- 
H.J.
From cf0466a657aeaf924fb07d6c9d83c5875b62e932 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" 
Date: Wed, 8 Jul 2015 04:36:43 -0700
Subject: [PATCH] Don't pass/return vectors in registers for IAMCU

Vectors should be passed in memory for IAMCU.  No warning for vector ABI
change for IAMCU since IAMCU ABI won't change.

gcc/

	PR target/66806
	* config/i386/i386.c (type_natural_mode): Don't warn vector ABI
	change for IAMCU.
	(function_arg_advance_32): Don't pass vectors in registers for
	IAMCU.
	(function_arg_32): Likewise.
	(ix86_return_in_memory): Don't return vectors in registers for
	IAMCU.

gcc/testsuite/

	PR target/66806
	* gcc.target/i386/pr66806.c: New test.
---
 gcc/config/i386/i386.c  | 17 +
 gcc/testsuite/gcc.target/i386/pr66806.c | 65 +
 2 files changed, 75 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr66806.c

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 112eb1c..55a32ac 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -6685,7 +6685,7 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,
 	if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
 		&& GET_MODE_INNER (mode) == innermode)
 	  {
-		if (size == 64 && !TARGET_AVX512F)
+		if (size == 64 && !TARGET_AVX512F && !TARGET_IAMCU)
 		  {
 		static bool warnedavx512f;
 		static bool warnedavx512f_ret;
@@ -6705,7 +6705,7 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,
 
 		return TYPE_MODE (type);
 		  }
-		else if (size == 32 && !TARGET_AVX)
+		else if (size == 32 && !TARGET_AVX && !TARGET_IAMCU)
 		  {
 		static bool warnedavx;
 		static bool warnedavx_ret;
@@ -6726,7 +6726,8 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,
 		return TYPE_MODE (type);
 		  }
 		else if (((size == 8 && TARGET_64BIT) || size == 16)
-			 && !TARGET_SSE)
+			 && !TARGET_SSE
+			 && !TARGET_IAMCU)
 		  {
 		static bool warnedsse;
 		static bool warnedsse_ret;
@@ -6744,7 +6745,9 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,
 			  warnedsse_ret = true;
 		  }
 		  }
-		else if ((size == 8 && !TARGET_64BIT) && !TARGET_MMX)
+		else if ((size == 8 && !TARGET_64BIT)
+			 && !TARGET_MMX
+			 && !TARGET_IAMCU)
 		  {
 		static bool warnedmmx;
 		static bool warnedmmx_ret;
@@ -7552,7 +7555,7 @@ function_arg_advance_32 (CUMULATIVE_ARGS *cum, machine_mode mode,
 {
   /* Intel MCU psABI passes scalars and aggregates no larger than 8
 	 bytes in registers.  */
-  if (bytes <= 8)
+  if (!VECTOR_MODE_P (mode) && bytes <= 8)
 	goto pass_in_reg;
   return res;
 }
@@ -7809,7 +7812,7 @@ function_arg_32 (CUMULATIVE_ARGS *cum, machine_mode mode,
 {
   /* Intel MCU psABI passes scalars and aggregates no larger than 8
 	 bytes in registers.  */
-  if (bytes <= 8)
+  if (!VECTOR_MODE_P (mode) && bytes <= 8)
 	goto pass_in_reg;
   return NULL_RTX;
 }
@@ -8679,7 +8682,7 @@ ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
   /* Intel MCU psABI returns scalars and aggregates no larger than 8
 	 bytes in registers.  */
   if (TARGET_IAMCU)
-	return size > 8;
+	return VECTOR_MODE_P (mode) || size > 8;
 
   if (mode == BLKmode)
 	return true;
diff --git a/gcc/testsuite/gcc.target/i386/pr66806.c b/gcc/testsuite/gcc.target/i386/pr66806.c
new file mode 100644
index 000..2486c5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr66806.c
@@ -0,0 +1,65 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-mno-sse -mno-mmx -miamcu" } */
+
+/* AVX512F and AVX512BW modes.  */
+typedef unsigned char V64QImode __attribute__((vector_size(64)));
+typedef unsigned short V32HImode __attribute__((vector_size(64)));
+typedef unsigned int V16SImode __attribute__((vector_size(64)));
+typedef unsigned long long V8DImode __attribute__((vector_size(64)));
+typedef float V16SFmode __attribute__((vector_size(64)));
+typedef double V8DFmode __attri

Re: [gomp] Move openacc vector& worker single handling to RTL

[Jakub Jelinek]

On Wed, Jul 08, 2015 at 10:47:56AM -0400, Nathan Sidwell wrote:
> +/* Generate loop head markers in outer->inner order.  */
> +
> +static void
> +gen_oacc_fork (gimple_seq *seq, unsigned mask)
> +{
> +  {
> +// TODDO: Determine this information from the parallel region itself

TODO ?

> +// and emit it once in the offload function.  Currently the target
> +// geometry definition is being extracted early.  For now inform
> +// the backend we're using all axes of parallelism, which is a
> +// safe default.
> +gcall *call = gimple_build_call_internal
> +  (IFN_GOACC_MODES, 1, 
> +   build_int_cst (unsigned_type_node,
> +   OACC_LOOP_MASK (OACC_gang)
> +   | OACC_LOOP_MASK (OACC_vector)
> +   | OACC_LOOP_MASK (OACC_worker)));

The formatting is too ugly.  I'd say you just want

tree arg = build_int_cst (unsigned_type_node,
  OACC_LOOP_MASK (OACC_gang)
  | OACC_LOOP_MASK (OACC_vector)
  | OACC_LOOP_MASK (OACC_worker));
gcall *call = gimple_build_call_internal (IFN_GOACC_MODES, 1, arg);
> +   | OACC_LOOP_MASK (OACC_vector)   

> +  for (level = OACC_gang; level != OACC_HWM; level++)
> +if (mask & OACC_LOOP_MASK (level))
> +  {
> + tree arg = build_int_cst (unsigned_type_node, level);
> + gcall *call = gimple_build_call_internal
> +   (IFN_GOACC_FORK, 1, arg);

Why the line-break?  That should fit into 80 columns just fine.

> + gimple_seq_add_stmt (seq, call);
> +  }
> +}
> +
> +/* Generate loop tail markers in inner->outer order.  */
> +
> +static void
> +gen_oacc_join (gimple_seq *seq, unsigned mask)
> +{
> +  unsigned level;
> +
> +  for (level = OACC_HWM; level-- != OACC_gang; )
> +if (mask & OACC_LOOP_MASK (level))
> +  {
> + tree arg = build_int_cst (unsigned_type_node, level);
> + gcall *call = gimple_build_call_internal
> +   (IFN_GOACC_JOIN, 1, arg);
> + gimple_seq_add_stmt (seq, call);
> +  }
> +}
>  
>  /* Find the mapping for DECL in CTX or the immediately enclosing
> context that has a mapping for DECL.
> @@ -6777,21 +6808,6 @@ expand_omp_for_generic (struct omp_regio
>  }
>  }
>  
> -
> -/* True if a barrier is needed after a loop partitioned over
> -   gangs/workers/vectors as specified by GWV_BITS.  OpenACC semantics specify
> -   that a (conceptual) barrier is needed after worker and vector-partitioned
> -   loops, but not after gang-partitioned loops.  Currently we are relying on
> -   warp reconvergence to synchronise threads within a warp after vector 
> loops,
> -   so an explicit barrier is not helpful after those.  */
> -
> -static bool
> -oacc_loop_needs_threadbarrier_p (int gwv_bits)
> -{
> -  return !(gwv_bits & OACC_LOOP_MASK (OACC_gang))
> -&& (gwv_bits & OACC_LOOP_MASK (OACC_worker));
> -}
> -
>  /* A subroutine of expand_omp_for.  Generate code for a parallel
> loop with static schedule and no specified chunk size.  Given
> parameters:
> @@ -6800,6 +6816,7 @@ oacc_loop_needs_threadbarrier_p (int gwv
>  
> where COND is "<" or ">", we generate pseudocode
>  
> +  OACC_FORK
>   if ((__typeof (V)) -1 > 0 && N2 cond N1) goto L2;
>   if (cond is <)
> adj = STEP - 1;
> @@ -6827,6 +6844,11 @@ oacc_loop_needs_threadbarrier_p (int gwv
>   V += STEP;
>   if (V cond e) goto L1;
>  L2:
> + OACC_JOIN
> +
> + It'd be better to place the OACC_LOOP markers just inside the outer
> + conditional, so they can be entirely eliminated if the loop is
> + unreachable.

Putting OACC_FORK/OACC_JOIN unconditionally into the comment is very
confusing.  The expand_omp_for_static_nochunk routine is used for
#pragma omp for schedule(static), #pragma omp distribute etc. which
certainly don't want to emit such markers in there.  So perhaps mention
somewhere that you wrap all the above sequence in between
OACC_FORK/OACC_JOIN markers.

> @@ -7220,6 +7249,7 @@ find_phi_with_arg_on_edge (tree arg, edg
>  
> where COND is "<" or ">", we generate pseudocode
>  
> +OACC_FORK
>   if ((__typeof (V)) -1 > 0 && N2 cond N1) goto L2;
>   if (cond is <)
> adj = STEP - 1;
> @@ -7230,6 +7260,7 @@ find_phi_with_arg_on_edge (tree arg, edg
>   else
> n = (adj + N2 - N1) / STEP;
>   trip = 0;
> +
>   V = threadid * CHUNK * STEP + N1;  -- this extra definition of V is
> here so that V is defined
> if the loop is not entered
> @@ -7248,6 +7279,7 @@ find_phi_with_arg_on_edge (tree arg, edg
>   trip += 1;
>   goto L0;
>  L4:
> +OACC_JOIN
>  */

Likewise.
>  
>  static void
> @@ -7281,10 +7313,6 @@ expand_omp_for_static_chunk (struct omp_
>gcc_assert (EDGE_COUNT (iter_part_bb->succs) == 2);
>fin_bb = BRANCH_EDGE (iter_part_bb)->dest;
>  
> -  /* Broadcast variables to OpenACC threads.  */
> -  entry_bb =

Re: [PATCH] Fix PR66794

[H.J. Lu]

On Wed, Jul 8, 2015 at 4:46 AM, Richard Biener  wrote:
>
> Passes do not expect post-dominators being around and thus forget
> to invalidate them properly.  Thus passes computing them have to
> free them.  The patch fixes path-isolation and adds an assert so
> this doesn't happen again.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk.
>
> Richard.
>
> 2015-07-08  Richard Biener  
>
> PR tree-optimization/66794
> * passes.c (execute_function_todo): Assert that post-dominators
> are not computed.
> * gimple-ssa-isolate-paths.c (gimple_ssa_isolate_erroneous_paths):
> Free post-dominators.
>

This caused:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66807

-- 
H.J.

[nvptx offloading] Only 64-bit configurations are currently supported (was: nvptx-tools and nvptx-newlib)

[Thomas Schwinge]

Hi!

On Wed, 18 Feb 2015 09:50:15 +0100, I wrote:
> So far, we have concentrated only on the 64-bit x86_64 configuration;
> 32-bit has several known issues to be resolved.
>  filed.

I have committed the following patch in r225560.  This gets us rid of the
lots of "expected FAILs" in the 32-bit part of
RUNTESTFLAGS='--target_board=unix\{-m64,-m32\}' testing, for example.

commit fe265ad3c9624da88f43be349137696449148f4f
Author: tschwinge 
Date:   Wed Jul 8 14:59:59 2015 +

[nvptx offloading] Only 64-bit configurations are currently supported

PR libgomp/65099
gcc/
* config/nvptx/mkoffload.c (main): Create an offload image only in
64-bit configurations.
libgomp/
* plugin/plugin-nvptx.c (nvptx_get_num_devices): Return 0 if not
in a 64-bit configuration.
* testsuite/libgomp.oacc-c++/c++.exp: Don't attempt nvidia
offloading testing if no such device is available.
* testsuite/libgomp.oacc-c/c.exp: Likewise.
* testsuite/libgomp.oacc-fortran/fortran.exp: Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225560 
138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog  |6 +++
 gcc/config/nvptx/mkoffload.c   |   56 +++-
 libgomp/ChangeLog  |   10 
 libgomp/plugin/plugin-nvptx.c  |5 ++
 libgomp/testsuite/libgomp.oacc-c++/c++.exp |6 +++
 libgomp/testsuite/libgomp.oacc-c/c.exp |6 +++
 libgomp/testsuite/libgomp.oacc-fortran/fortran.exp |6 +++
 7 files changed, 70 insertions(+), 25 deletions(-)

diff --git gcc/ChangeLog gcc/ChangeLog
index 33a2fa0..4c83723 100644
--- gcc/ChangeLog
+++ gcc/ChangeLog
@@ -1,3 +1,9 @@
+2015-07-08  Thomas Schwinge  
+
+   PR libgomp/65099
+   * config/nvptx/mkoffload.c (main): Create an offload image only in
+   64-bit configurations.
+
 2015-07-08  Martin Liska  
 
PR bootstrap/66744
diff --git gcc/config/nvptx/mkoffload.c gcc/config/nvptx/mkoffload.c
index 8687154..8bc08bf 100644
--- gcc/config/nvptx/mkoffload.c
+++ gcc/config/nvptx/mkoffload.c
@@ -993,37 +993,43 @@ main (int argc, char **argv)
obstack_ptr_grow (&argv_obstack, argv[ix]);
 }
 
-  ptx_name = make_temp_file (".mkoffload");
-  obstack_ptr_grow (&argv_obstack, "-o");
-  obstack_ptr_grow (&argv_obstack, ptx_name);
-  obstack_ptr_grow (&argv_obstack, NULL);
-  const char **new_argv = XOBFINISH (&argv_obstack, const char **);
-
-  char *execpath = getenv ("GCC_EXEC_PREFIX");
-  char *cpath = getenv ("COMPILER_PATH");
-  char *lpath = getenv ("LIBRARY_PATH");
-  unsetenv ("GCC_EXEC_PREFIX");
-  unsetenv ("COMPILER_PATH");
-  unsetenv ("LIBRARY_PATH");
-
-  fork_execute (new_argv[0], CONST_CAST (char **, new_argv), true);
-  obstack_free (&argv_obstack, NULL);
-
-  xputenv (concat ("GCC_EXEC_PREFIX=", execpath, NULL));
-  xputenv (concat ("COMPILER_PATH=", cpath, NULL));
-  xputenv (concat ("LIBRARY_PATH=", lpath, NULL));
-
-  in = fopen (ptx_name, "r");
-  if (!in)
-fatal_error (input_location, "cannot open intermediate ptx file");
-
   ptx_cfile_name = make_temp_file (".c");
 
   out = fopen (ptx_cfile_name, "w");
   if (!out)
 fatal_error (input_location, "cannot open '%s'", ptx_cfile_name);
 
-  process (in, out);
+  /* PR libgomp/65099: Currently, we only support offloading in 64-bit
+ configurations.  */
+  if (!target_ilp32)
+{
+  ptx_name = make_temp_file (".mkoffload");
+  obstack_ptr_grow (&argv_obstack, "-o");
+  obstack_ptr_grow (&argv_obstack, ptx_name);
+  obstack_ptr_grow (&argv_obstack, NULL);
+  const char **new_argv = XOBFINISH (&argv_obstack, const char **);
+
+  char *execpath = getenv ("GCC_EXEC_PREFIX");
+  char *cpath = getenv ("COMPILER_PATH");
+  char *lpath = getenv ("LIBRARY_PATH");
+  unsetenv ("GCC_EXEC_PREFIX");
+  unsetenv ("COMPILER_PATH");
+  unsetenv ("LIBRARY_PATH");
+
+  fork_execute (new_argv[0], CONST_CAST (char **, new_argv), true);
+  obstack_free (&argv_obstack, NULL);
+
+  xputenv (concat ("GCC_EXEC_PREFIX=", execpath, NULL));
+  xputenv (concat ("COMPILER_PATH=", cpath, NULL));
+  xputenv (concat ("LIBRARY_PATH=", lpath, NULL));
+
+  in = fopen (ptx_name, "r");
+  if (!in)
+   fatal_error (input_location, "cannot open intermediate ptx file");
+
+  process (in, out);
+}
+
   fclose (out);
 
   compile_native (ptx_cfile_name, outname, collect_gcc);
diff --git libgomp/ChangeLog libgomp/ChangeLog
index 8839397..34f3a1c 100644
--- libgomp/ChangeLog
+++ libgomp/ChangeLog
@@ -1,3 +1,13 @@
+2015-07-08  Thomas Schwinge  
+
+   PR libgomp/65099
+   * plugin/plugin-nvptx.c (nvptx_get_num_devices): Return 0 if not
+   in a 64-bit configuration.
+   * testsuite/libgomp.oacc-c++/c++.exp: Don't attempt nvidia
+   offloading testing if no such device 

[PATCH]Fix PR66556. Don't drop side-effect in simplify_const_relational_operation function.

[Renlin Li]

Hi all,

In simplify_const_relational_operation function, there are cases a const rtx
will be returned.

Three cases are considered in this function:
1, comparisons with upper and lower bounds.
2, Integer comparisons with zero.
3, comparison of ABS with zero.

It's fine to to the optimization if the operands have no side-effects.

For example, I am currently fixing a code generation bug for armv7-a 
bigendian.

It turns out that, the following rtx is simplified into a const, and the
side-effect with it is ignored.

(ltu:SI (lshiftrt:SI (subreg:SI (mem/c:HI (post_modify:SI (reg/f:SI 156)
(plus:SI (reg/f:SI 156)
(const_int 20 [0x14]))) [5 g+4 S2 A32]) 0)
(const_int 1 [0x1]))
(const_int -1 [0x]))

>>

(const_int 1 [0x1])

This particular case falls into category 1 mentioned above. -1, when 
regarded
as unsigned integer, is the largest unsigned integer. So the result is 
always

a const_true_rtx in this case. However, the first operand of the comparison
has POST_MODIFY side-effect.

In this case, the simplifications should be checked against side-effect.

x86_64 bootstrapping is Okay and arm-none-eabi regression test runs 
without any new issues.


Okay to commit and backport to branch 5?

Regards,
Renlin Li

gcc/ChangeLog:

2015-07-08  Renlin Li  

PR rtl/66556
* simplify-rtx.c (simplify_const_relational_operation): Add
side_effects_p check.

gcc/testsuite/ChangeLog:

2015-07-08  Renlin Li  

PR rtl/66556
* gcc.c-torture/execute/pr66556.c: New.
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index ca8310d..936a144 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -4930,7 +4930,8 @@ simplify_const_relational_operation (enum rtx_code code,
 
   /* Optimize comparisons with upper and lower bounds.  */
   if (HWI_COMPUTABLE_MODE_P (mode)
-  && CONST_INT_P (trueop1))
+  && CONST_INT_P (trueop1)
+  && !side_effects_p (trueop0))
 {
   int sign;
   unsigned HOST_WIDE_INT nonzero = nonzero_bits (trueop0, mode);
@@ -5043,7 +5044,7 @@ simplify_const_relational_operation (enum rtx_code code,
 }
 
   /* Optimize integer comparisons with zero.  */
-  if (trueop1 == const0_rtx)
+  if (trueop1 == const0_rtx && !side_effects_p (trueop0))
 {
   /* Some addresses are known to be nonzero.  We don't know
 	 their sign, but equality comparisons are known.  */
@@ -5094,7 +5095,7 @@ simplify_const_relational_operation (enum rtx_code code,
 }
 
   /* Optimize comparison of ABS with zero.  */
-  if (trueop1 == CONST0_RTX (mode)
+  if (trueop1 == CONST0_RTX (mode) && !side_effects_p (trueop0)
   && (GET_CODE (trueop0) == ABS
 	  || (GET_CODE (trueop0) == FLOAT_EXTEND
 	  && GET_CODE (XEXP (trueop0, 0)) == ABS)))
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr66556.c b/gcc/testsuite/gcc.c-torture/execute/pr66556.c
new file mode 100644
index 000..f7acf1c
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr66556.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+
+extern void abort (void);
+
+struct {
+  unsigned f2;
+  unsigned f3 : 15;
+  unsigned f5 : 3;
+  short f6;
+} b = {0x7f8000, 6, 5, 0}, g = {8, 0, 5, 0};
+
+short d, l;
+int a, c, h = 8;
+volatile char e[237] = {4};
+short *f = &d;
+short i[5] = {3};
+char j;
+int *k = &c;
+
+int
+fn1 (unsigned p1) { return -p1; }
+
+void
+fn2 (char p1)
+{
+  a = p1;
+  e[0];
+}
+
+short
+fn3 ()
+{
+  *k = 4;
+  return *f;
+}
+
+int
+main ()
+{
+
+  unsigned m;
+  short *n = &i[4];
+
+  m = fn1 ((h && j) <= b.f5);
+  l = m > g.f3;
+  *n = 3;
+  fn2 (b.f2 >> 15);
+  if ((a & 0xff) != 0xff)
+abort ();
+
+  return 0;
+}

Patch to fix PR66334

[Vladimir Makarov]

  The following patch fixes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66334

  The patch was bootstrapped and tested on x86/x86-64.

  Committed as rev. 225561.

2015-07-08  Vladimir Makarov  

PR middle-end/66334
* ira-lives.c (process_bb_node_lives): Make conflicts with PIC
hard regno live at the start of BB with incoming abnormal edges.
* lra-lives.c (process_bb_lives): Ditto.

2015-07-08  Vladimir Makarov  

PR middle-end/66334
* gcc.target/i386/pr66334.c: New.


Index: ira-lives.c
===
--- ira-lives.c	(revision 225559)
+++ ira-lives.c	(working copy)
@@ -1344,7 +1344,21 @@ process_bb_node_lives (ira_loop_tree_nod
 	 allocate such regs in this case.  */
 	  if (!cfun->has_nonlocal_label && bb_has_abnormal_call_pred (bb))
 	for (px = 0; px < FIRST_PSEUDO_REGISTER; px++)
-	  if (call_used_regs[px])
+	  if (call_used_regs[px]
+#ifdef REAL_PIC_OFFSET_TABLE_REGNUM
+		  /* We should create a conflict of PIC pseudo with
+		 PIC hard reg as PIC hard reg can have a wrong
+		 value after jump described by the abnormal edge.
+		 In this case we can not allocate PIC hard reg to
+		 PIC pseudo as PIC pseudo will also have a wrong
+		 value.  This code is not critical as LRA can fix
+		 it but it is better to have the right allocation
+		 earlier.  */
+		  || (px == REAL_PIC_OFFSET_TABLE_REGNUM
+		  && pic_offset_table_rtx != NULL_RTX
+		  && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
+#endif
+		  )
 		make_hard_regno_born (px);
 	}
 
Index: lra-lives.c
===
--- lra-lives.c	(revision 225559)
+++ lra-lives.c	(working copy)
@@ -953,7 +953,18 @@ process_bb_lives (basic_block bb, int &c
 	 allocate such regs in this case.  */
   if (!cfun->has_nonlocal_label && bb_has_abnormal_call_pred (bb))
 	for (px = 0; px < FIRST_PSEUDO_REGISTER; px++)
-	  if (call_used_regs[px])
+	  if (call_used_regs[px]
+#ifdef REAL_PIC_OFFSET_TABLE_REGNUM
+	  /* We should create a conflict of PIC pseudo with PIC
+		 hard reg as PIC hard reg can have a wrong value after
+		 jump described by the abnormal edge.  In this case we
+		 can not allocate PIC hard reg to PIC pseudo as PIC
+		 pseudo will also have a wrong value.  */
+	  || (px == REAL_PIC_OFFSET_TABLE_REGNUM
+		  && pic_offset_table_rtx != NULL_RTX
+		  && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
+#endif
+	  )
 	make_hard_regno_born (px, false);
 }
 
Index: testsuite/gcc.target/i386/pr66334.c
===
--- testsuite/gcc.target/i386/pr66334.c	(revision 0)
+++ testsuite/gcc.target/i386/pr66334.c	(working copy)
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -fpic -fexceptions -fasynchronous-unwind-tables" } */
+/* { dg-final { scan-assembler "movl\[ \\t\].+, %ebx" } } */
+extern int foo (int);
+extern void exit (int __status) __attribute__ ((__nothrow__ )) __attribute__ ((__noreturn__));
+struct __pthread_cleanup_frame
+{
+  void (*__cancel_routine) (void *);
+  void *__cancel_arg;
+  int __do_it;
+  int __cancel_type;
+};
+extern __inline void
+__pthread_cleanup_routine (struct __pthread_cleanup_frame *__frame)
+{
+  if (__frame->__do_it)
+__frame->__cancel_routine (__frame->__cancel_arg);
+}
+static int cl_called;
+
+static void
+cl (void *arg)
+{
+  ++cl_called;
+}
+
+
+void *
+tf_usleep (void *arg)
+{
+
+  do { struct __pthread_cleanup_frame __clframe __attribute__ ((__cleanup__ (__pthread_cleanup_routine))) = { .__cancel_routine = (cl), .__cancel_arg = (
+			 ((void *)0)), .__do_it = 1 };;
+
+foo (arg == ((void *)0) ? (0x7fffL * 2UL + 1UL) : 0);
+
+__clframe.__do_it = (0); } while (0);
+
+  exit (1);
+}

Re: [PATCH 3/4] Add libgomp plugin for Intel MIC

[Ilya Verbin]

> On 8 июля 2015 г., at 17:16, Thomas Schwinge  wrote:
> 
> Hi!
> 
>> On Tue, 21 Oct 2014 21:24:13 +0400, Ilya Verbin  wrote:
>> This patch contains a plugin for libgomp and appropriate changes for 
>> makefiles.
>> 
>> The plugin uses liboffloadmic_host.so to interact with the device (or with an
>> emulator).  Also the patch contains offload_target_main executable, which is 
>> the
>> corresponding target side part of a libgomp plugin, and it uses
>> liboffloadmic_target.so.
>> 
>> The plugin builds automatically with liboffloadmic.
> 
> With recent GCC trunk sources, builds of the Intel MIC Offload Plugin
> fail as follows:
> 
>libtool: compile:  [...]/build-gcc/./gcc/xg++ [...] 
> -I[...]/install/offload-x86_64-intelmicemul-linux-gnu/x86_64-intelmicemul-linux-gnu/liboffloadmic/plugin
>  
> -I[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include
>  -c [...]/source-gcc/liboffloadmic/plugin/libgomp-plugin-intelmic.cpp  -fPIC 
> -DPIC -o .libs/libgomp_plugin_intelmic_la-libgomp-plugin-intelmic.o
>In file included from 
> [...]/source-gcc/liboffloadmic/plugin/libgomp-plugin-intelmic.cpp:40:0:
>
> [...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1:
>  error: narrowing conversion of '192' from 'int' to 'char' inside { } 
> [-Wnarrowing]
> };
> ^
>
> [...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1:
>  error: narrowing conversion of '192' from 'int' to 'char' inside { } 
> [-Wnarrowing]
>
> [...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1:
>  error: narrowing conversion of '164' from 'int' to 'char' inside { } 
> [-Wnarrowing]
>[many more]
> 
> Apart from the actual compilation error, it is surprising for me to see
> the GCC build reference/depend on the Intel MIC offloading compiler's
> installation directory (which I built and installed earlier),
> [...]/install/offload-x86_64-intelmicemul-linux-gnu/ -- is that the
> correct thing to do?  Shouldn't the GCC build be self-contained?  (I have
> not yet made an attempt to understand how the target and device
> liboffloadmic builds work together.)
> 
> This main_target_image.h file is coming from here:
> 
>> --- /dev/null
>> +++ b/liboffloadmic/plugin/Makefile.am
>> @@ -0,0 +1,123 @@
>> +# Plugin for offload execution on Intel MIC devices.
> 
>> +main_target_image.h: offload_target_main
>> +@echo -n "const int image_size = " > $@
>> +@stat -c '%s' $< >> $@
>> +@echo ";" >> $@
>> +@echo "struct MainTargetImage {" >> $@
>> +@echo "  int64_t size;" >> $@
>> +@echo "  char name[sizeof \"offload_target_main\"];" >> $@
>> +@echo "  char data[image_size];" >> $@
>> +@echo "};" >> $@
>> +@echo "extern \"C\" const MainTargetImage main_target_image = {" >> $@
>> +@echo "  image_size, \"offload_target_main\"," >> $@
>> +@cat $< | xxd -include >> $@
>> +@echo "};" >> $@
>> +
>> +offload_target_main: $(liboffload_dir)/ofldbegin.o offload_target_main.o 
>> $(liboffload_dir)/ofldend.o
>> +$(CXX) $(AM_LDFLAGS) $^ -o $@
>> +
>> +offload_target_main.o: offload_target_main.cpp
>> +$(CXX) $(AM_CXXFLAGS) $(AM_CPPFLAGS) -c $< -o $@
> 
> Here, I note that the xxd tool is being used, which in my distribution is
> part of the Vim editor's package, which -- as far as I know -- is not
> currently declared as a build dependency of GCC?
> 
> Anyway, all that aside for the moment -- OK to commit the following?
> 
> --- liboffloadmic/plugin/Makefile.am
> +++ liboffloadmic/plugin/Makefile.am
> @@ -69,7 +69,7 @@ main_target_image.h: offload_target_main
>@echo "struct MainTargetImage {" >> $@
>@echo "  int64_t size;" >> $@
>@echo "  char name[sizeof \"offload_target_main\"];" >> $@
> -@echo "  char data[image_size];" >> $@
> +@echo "  uint8_t data[image_size];" >> $@
>@echo "};" >> $@
>@echo "extern \"C\" const MainTargetImage main_target_image = {" >> $@
>@echo "  image_size, \"offload_target_main\"," >> $@
> 
> 
> Grüße,
> Thomas

Ok to me, thanks.

The plugin consists of 2 parts: offload_target_main is a target part, which is 
embedded into the host part (libgomp plugin itself). Target part is linked with 
liboffloadmic_target.so and host part is linked with liboffloadmic_host.so. 
Both offload_target_main and liboffloadmic_target.so are compiled by the target 
compiler during its build.

As for xxd, I've found its usage in some Makefile inside gcc tree, so I thought 
it's ok to use it.

  -- Ilya

Re: [PATCH 2/4 v2: part 2] libcpp: Replace macro usage with C++ constructs

[David Malcolm]

On Wed, 2015-07-08 at 16:50 +0200, Thomas Schwinge wrote:
> Hi!
> 
> On Tue,  5 May 2015 14:21:13 -0400, David Malcolm  wrote:
> > libcpp/ChangeLog:
> > * include/line-map.h (MAX_SOURCE_LOCATION): Convert from a macro
> > to a const source_location.
> > (RESERVED_LOCATION_COUNT): Likewise.
> > [...]
> 
> > --- a/libcpp/include/line-map.h
> > +++ b/libcpp/include/line-map.h
> 
> >  /* This is the highest possible source location encoded within an
> > ordinary or macro map.  */
> > -#define MAX_SOURCE_LOCATION 0x7FFF
> > +const source_location MAX_SOURCE_LOCATION = 0x7FFF;
> 
> >  /* source_location values from 0 to RESERVED_LOCATION_COUNT-1 will
> > be reserved for libcpp user as special values, no token from libcpp
> > will contain any of those locations.  */
> > -#define RESERVED_LOCATION_COUNT2
> > +const int RESERVED_LOCATION_COUNT = 2;
> 
> That's not quite what the ChangeLog says ;-) -- now committed in r225558,
> as obvious

Oops; thanks!

RE: [PATCH] MIPS: fix failing branch range checks for micromips

[Andrew Bennett]

> > testsuite/
> > * gcc.target/mips/branch-2.c: Change NOMIPS16 to
> > NOCOMPRESSION.
> > * gcc.target/mips/branch-3.c: Ditto
> > * gcc.target/mips/branch-4.c: Ditto.
> > * gcc.target/mips/branch-5.c: Ditto.
> > * gcc.target/mips/branch-6.c: Ditto.
> > * gcc.target/mips/branch-7.c: Ditto.
> > * gcc.target/mips/branch-8.c: Ditto.
> > * gcc.target/mips/branch-9.c: Ditto.
> > * gcc.target/mips/branch-10.c: Ditto.
> > * gcc.target/mips/branch-11.c: Ditto.
> > * gcc.target/mips/branch-12.c: Ditto.
> > * gcc.target/mips/branch-13.c: Ditto.
> 
> These are OK, except for the splitting of the scan-assembler statements.
> 
> Please change occurrences of:
> > +/* { dg-final { scan-assembler
> > +"\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */
> to:
> +/* { dg-final { scan-assembler
> "\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */
> 
> before committing.

I think this might be a problem with your email client, as these issues do 
not occur in my patch submission.

https://gcc.gnu.org/ml/gcc-patches/2015-07/msg00529.html


> > * gcc.target/mips/branch-14.c: Ditto.
> > * gcc.target/mips/branch-15.c: Ditto.
> 
> The modifications for these two files need to be removed.   These are
> execution tests and the multilib that is used to link them is important.   If
> the libraries are not compatible with the NOCOMPRESSION attribute, then the
> link step will fail.  You could work around this problem by enabling
> interlinking, but I think the best approach is to leave these two tests alone.

Firstly, I have committed a patch which does not include the branch-[14,15].c 
and
umips-branch-[17,18].c changes (SVN 225540).  However, I am keen to get these 
changes committed purely so that we have an in-range micromips branch execution 
test (which none of the current tests provide).  I need to look at the mips.exp 
file 
in more detail, but I was wondering if you would be happy to keep these tests 
in, 
but downgrade them to assemble tests if the required multilib support does not 
exist?


Regards,



Andrew

[C++ Patch] PR 66644

[Paolo Carlini]

Hi,

this is about the anonymous struct extension, but I think submitter is 
right that we should accept the testcase (indeed both clang and edg 
already do): in the below I propose to simply add a test of 
ANON_AGGR_TYPE_P (DECL_CONTEXT (field)). Note that, given the definition 
of ANON_AGGR_TYPE_P, should not be necessary to take care explicitly of 
anonymous unions: to be safe I'm adding a negative test for those.


Tested x86_64-linux.

Thanks,
Paolo.

/
/cp
2015-07-08  Paolo Carlini  

PR c++/66644
* class.c (check_field_decl): Do not reject multiple initialized
fields in anonymous struct.

/testsuite
2015-07-08  Paolo Carlini  

PR c++/66644
* g++.dg/cpp0x/anon-struct1.C: New.
Index: cp/class.c
===
--- cp/class.c  (revision 225556)
+++ cp/class.c  (working copy)
@@ -3568,7 +3568,8 @@ check_field_decl (tree field,
 {
   /* `build_class_init_list' does not recognize
 non-FIELD_DECLs.  */
-  if (TREE_CODE (t) == UNION_TYPE && *any_default_members != 0)
+  if (TREE_CODE (t) == UNION_TYPE && *any_default_members != 0
+ && !ANON_AGGR_TYPE_P (DECL_CONTEXT (field)))
error ("multiple fields in union %qT initialized", t);
   *any_default_members = 1;
 }
Index: testsuite/g++.dg/cpp0x/anon-struct1.C
===
--- testsuite/g++.dg/cpp0x/anon-struct1.C   (revision 0)
+++ testsuite/g++.dg/cpp0x/anon-struct1.C   (working copy)
@@ -0,0 +1,21 @@
+// PR c++/66644
+// { dg-do compile { target c++11 } }
+// { dg-options "" }
+
+struct testP
+{
+  union U
+  {
+struct { char a=0, b=0; };
+char buffer[16];
+  };
+};
+
+struct testN
+{
+  union U
+  {
+union { char a=0, b=0; };  // { dg-error "multiple fields" }
+char buffer[16];
+  };
+};

Re: [PATCH] fix PR46029: reimplement if conversion of loads and stores [2nd submitted version of patch]

[Abe]

[Alan wrote:]


Where can I find info on what the different flag values mean?
(I had thought they were booleans [...]



[Abe wrote:]


Sorry; I don`t know if that is documented anywhere yet.



In this case, (-1) simply means "defaulted": on if the vectorizer is on, and 
off if it is off.
(0) means "user specified no if conversion" and (1) means "user specified [yes] if 
conversion".



[Alan wrote:]


Ah, right, that makes sense now. Obviously I would like to see this written in 
doc/ .


Is the following sufficient?  From "doc/invoke.texi", I propose to replace:

  This is enabled by default if vectorization is enabled.

... with:

  This is enabled by default when vectorization is  enabled
  anddisabled by default when vectorization is disabled.


Regards,

Abe

[PATCH] Limit alignment on error_mark_node variable

[H.J. Lu]

There is no need to try different alignment on variable of
error_mark_node.

OK for trunk if there is no regression?

Thanks.

H.J.
--
gcc/

PR target/66810
* varasm.c (align_variable): Don't try different alignment on
variable of error_mark_node.

gcc/testsuite/

PR target/66810
* gcc.target/i386/pr66810.c: New test.
---
 gcc/testsuite/gcc.target/i386/pr66810.c | 10 ++
 gcc/varasm.c|  3 ++-
 2 files changed, 12 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr66810.c

diff --git a/gcc/testsuite/gcc.target/i386/pr66810.c 
b/gcc/testsuite/gcc.target/i386/pr66810.c
new file mode 100644
index 000..4778b37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr66810.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-mno-sse -mno-mmx -miamcu" } */
+
+int vv;
+
+void
+i (void)
+{
+  static int a[vv]; /* { dg-error "storage size" } */
+}
diff --git a/gcc/varasm.c b/gcc/varasm.c
index b69b3a3..be33cb4 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -1016,7 +1016,8 @@ align_variable (tree decl, bool dont_output_data)
   align = MAX_OFILE_ALIGNMENT;
 }
 
-  if (! DECL_USER_ALIGN (decl))
+  /* Don't try different alignment for error_mark_node.  */
+  if (! DECL_USER_ALIGN (decl) && TREE_TYPE (decl) != error_mark_node)
 {
 #ifdef DATA_ABI_ALIGNMENT
   unsigned int data_abi_align
-- 
2.4.3

Re: fix PR46029: reimplement if conversion of loads and stores

[Abe]

[Abe wrote:]

I believe Sebastian would agree that the new if converter  is safer than the 
old one

>> in terms of correctness at the time of running the code being compiled.
[...]

For now, we have a few performance regressions

[snip]


[Alan wrote:]

TBH my two cents would be that a performance-regressed, but correct, compiler, 
is far better to release,  than a

> performance-"improved" one that generates unsafe code (e.g. with extra faults 
in the straightforward single-threaded case!)...

I strongly agree that -- by default -- correctness trumps performance.  The 
only times it is allowable to reverse that relationship, IMO,
is when the user* of the compiler has explicitly specified flags [e.g. "-ffast-math", 
"-Ofast"] that tell the compiler that the user*
currently cares more about performance than about 
{correctness-according-to-spec and/or safety in all conditions including null 
pointers}.

['*': or Makefiles, build scripts, etc.]

FYI: TTBOMK, the old if converter was not unsafe with default flags or with only "big 
knobs" like "-O3"; I`m unsure what it did
under "-ffast-math" and "-Ofast", if anything of interest.  The main advantage 
of the new if converter over the old one is that
the new one is safe in certain situations wherein the old one is unsafe, e.g. 
the old one may cause the vectorized code to segfault
where the non-if-converted code would have run just fine all the way to program 
completion with the same inputs.  This additional
safety allows the new converter to be used under more conditions, which in turn 
allows it to be enabled by default.  We intend
for all the safe if-conversions to be done by default whenever the vectorizer 
is on.  If there are any unsafe conversions left,
which I`m not sure there are, then we will enable them only when the user* specifies 
something like "-fif-conversion=allow-unsafe".
The "allows it to be enabled by default" property should help the code that GCC generates 
under "-O3" w/o any additional
flags to be faster than it currently is, for the relevant targets, *without 
sacrificing even _one_ _bit_ of correctness*.

Regards,

Abe

Re: [PATCH 3/4] Add libgomp plugin for Intel MIC

[Thomas Schwinge]

Hi!

On Wed, 8 Jul 2015 18:13:56 +0300, Ilya Verbin  wrote:
> 
> > On 8 июля 2015 г., at 17:16, Thomas Schwinge  
> > wrote:
> > With recent GCC trunk sources, builds of the Intel MIC Offload Plugin
> > fail as follows: [...]

> > [...] -- OK to commit the following?

> Ok to me, thanks.

Committed in r225562:

commit cacef506e4205bac13a0dd1de238d1a8cc78af28
Author: tschwinge 
Date:   Wed Jul 8 15:47:59 2015 +

liboffloadmic plugin: Address -Wnarrowing diagnostics

libtool: compile:  [...]/build-gcc/./gcc/xg++ [...] -c 
[...]/source-gcc/liboffloadmic/plugin/libgomp-plugin-intelmic.cpp [...]
In file included from 
[...]/source-gcc/liboffloadmic/plugin/libgomp-plugin-intelmic.cpp:40:0:

[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1:
 error: narrowing conversion of '192' from 'int' to 'char' inside { } 
[-Wnarrowing]
 };
 ^

[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1:
 error: narrowing conversion of '192' from 'int' to 'char' inside { } 
[-Wnarrowing]

[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1:
 error: narrowing conversion of '164' from 'int' to 'char' inside { } 
[-Wnarrowing]
[many more]

liboffloadmic/
* plugin/Makefile.am (main_target_image.h): Change type of data
member in struct MainTargetImage to uint8_t.
* plugin/Makefile.in: Regenerate.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225562 
138bc75d-0d04-0410-961f-82ee72b054a4
---
 liboffloadmic/ChangeLog  |6 ++
 liboffloadmic/plugin/Makefile.am |2 +-
 liboffloadmic/plugin/Makefile.in |2 +-
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git liboffloadmic/ChangeLog liboffloadmic/ChangeLog
index 01fb9f4..b0f9e90 100644
--- liboffloadmic/ChangeLog
+++ liboffloadmic/ChangeLog
@@ -1,3 +1,9 @@
+2015-07-08  Thomas Schwinge  
+
+   * plugin/Makefile.am (main_target_image.h): Change type of data
+   member of struct MainTargetImage to uint8_t.
+   * plugin/Makefile.in: Regenerate.
+
 2015-05-13  Michael Haubenwallner  
 
* Makefile.in: Regenerated with automake-1.11.6.
diff --git liboffloadmic/plugin/Makefile.am liboffloadmic/plugin/Makefile.am
index a814f0c..19d69ab 100644
--- liboffloadmic/plugin/Makefile.am
+++ liboffloadmic/plugin/Makefile.am
@@ -69,7 +69,7 @@ main_target_image.h: offload_target_main
@echo "struct MainTargetImage {" >> $@
@echo "  int64_t size;" >> $@
@echo "  char name[sizeof \"offload_target_main\"];" >> $@
-   @echo "  char data[image_size];" >> $@
+   @echo "  uint8_t data[image_size];" >> $@
@echo "};" >> $@
@echo "extern \"C\" const MainTargetImage main_target_image = {" >> $@
@echo "  image_size, \"offload_target_main\"," >> $@
diff --git liboffloadmic/plugin/Makefile.in liboffloadmic/plugin/Makefile.in
index 6f7eec9..19a1a96 100644
--- liboffloadmic/plugin/Makefile.in
+++ liboffloadmic/plugin/Makefile.in
@@ -715,7 +715,7 @@ main_target_image.h: offload_target_main
@echo "struct MainTargetImage {" >> $@
@echo "  int64_t size;" >> $@
@echo "  char name[sizeof \"offload_target_main\"];" >> $@
-   @echo "  char data[image_size];" >> $@
+   @echo "  uint8_t data[image_size];" >> $@
@echo "};" >> $@
@echo "extern \"C\" const MainTargetImage main_target_image = {" >> $@
@echo "  image_size, \"offload_target_main\"," >> $@


Thanks for the explanation:

> The plugin consists of 2 parts: offload_target_main is a target part, which 
> is embedded into the host part (libgomp plugin itself). Target part is linked 
> with liboffloadmic_target.so and host part is linked with 
> liboffloadmic_host.so. Both offload_target_main and liboffloadmic_target.so 
> are compiled by the target compiler during its build.
> 
> As for xxd, I've found its usage in some Makefile inside gcc tree, so I 
> thought it's ok to use it.


Grüße,
 Thomas


pgpIlKlIO2UeJ.pgp
Description: PGP signature

Re: [PATCH] PR target/66806: Don't pass/return vectors in registers for IAMCU

[Uros Bizjak]

On Wed, Jul 8, 2015 at 4:57 PM, H.J. Lu  wrote:

>>> Vectors should be passed in memory for IAMCU.
>>>
>>> OK for trunk?
>>>
>>> H.J.
>>> ---
>>> gcc/
>>>
>>> PR target/66806
>>> * config/i386/i386.c (function_arg_advance_32): Don't pass
>>> vectors in registers for IAMCU.
>>> (function_arg_32): Likewise.
>>> (ix86_return_in_memory): Don't return vectors in registers for
>>> IAMCU.
>>>
>>> gcc/testsuite/
>>>
>>> PR target/66806
>>> * gcc.target/i386/pr66806.c: New test.
>>
>>> +/* { dg-do compile { target ia32 } } */
>>> +/* { dg-options "-miamcu -mno-sse -mno-mmx -miamcu -Wno-psabi" } */
>>
>> Double -miamcu.
>>
>> Also, why Wno-psabi? We can check for the warning here, too.
>>
>
> Here is the updated patch.  Since IA MCU won't change ABI for vectors,
> we shouldn't issue any warnings.
>
> Tested on Linux/x86-64.  OK for trunk?

OK for mainline with updated ChangeLogs.

Thanks,
Uros.

RE: [PATCH] MIPS: fix failing branch range checks for micromips

[Moore, Catherine]

> -Original Message-
> From: Andrew Bennett [mailto:andrew.benn...@imgtec.com]
> Sent: Wednesday, July 08, 2015 11:17 AM
> To: Moore, Catherine; gcc-patches@gcc.gnu.org
> Cc: Matthew Fortune
> Subject: RE: [PATCH] MIPS: fix failing branch range checks for micromips
> 
> > > testsuite/
> > >   * gcc.target/mips/branch-2.c: Change NOMIPS16 to
> NOCOMPRESSION.
> > >   * gcc.target/mips/branch-3.c: Ditto
> > >   * gcc.target/mips/branch-4.c: Ditto.
> > >   * gcc.target/mips/branch-5.c: Ditto.
> > >   * gcc.target/mips/branch-6.c: Ditto.
> > >   * gcc.target/mips/branch-7.c: Ditto.
> > >   * gcc.target/mips/branch-8.c: Ditto.
> > >   * gcc.target/mips/branch-9.c: Ditto.
> > >   * gcc.target/mips/branch-10.c: Ditto.
> > >   * gcc.target/mips/branch-11.c: Ditto.
> > >   * gcc.target/mips/branch-12.c: Ditto.
> > >   * gcc.target/mips/branch-13.c: Ditto.
> >
> > These are OK, except for the splitting of the scan-assembler statements.
> >
> > Please change occurrences of:
> > > +/* { dg-final { scan-assembler
> > > +"\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */
> > to:
> > +/* { dg-final { scan-assembler
> > "\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */
> >
> > before committing.
> 
> I think this might be a problem with your email client, as these issues do not
> occur in my patch submission.
> 
Yes, it would appear that way.  Sorry for the noise.

> 
> 
> > >   * gcc.target/mips/branch-14.c: Ditto.
> > >   * gcc.target/mips/branch-15.c: Ditto.
> >
> > The modifications for these two files need to be removed.   These are
> > execution tests and the multilib that is used to link them is important.   
> > If
> > the libraries are not compatible with the NOCOMPRESSION attribute,
> > then the link step will fail.  You could work around this problem by
> > enabling interlinking, but I think the best approach is to leave these two
> tests alone.
> 
> Firstly, I have committed a patch which does not include the branch-[14,15].c
> and umips-branch-[17,18].c changes (SVN 225540).  However, I am keen to
> get these changes committed purely so that we have an in-range micromips
> branch execution test (which none of the current tests provide).  I need to
> look at the mips.exp file in more detail, but I was wondering if you would be
> happy to keep these tests in, but downgrade them to assemble tests if the
> required multilib support does not exist?
> 
How about adding the interlinking option to the umips-branch-[17,18].c tests 
instead?
Ie.  /* { dg-options "(-mmicromips) -minterlink-compressed" } */


 

Re: Drop -Wswitch-bool warning in function.c

[Kito Cheng]

Hi Marek:

Yes, I know it's non-fatal warning, but I think gcc should build with
--enable-werror-always by it's self
and it's the *ONLY* warning in trunk now.

Of cause, cast to int can suppress the warning,
but it's not good solution so gcc complain that switch condition has
bool type :)

On Wed, Jul 8, 2015 at 9:30 PM, Marek Polacek  wrote:
> On Wed, Jul 08, 2015 at 04:49:19PM +0800, Kito Cheng wrote:
>> Bootstrapped & regression-tested on x86_64-linux-gnu :)
>>
>> 2015-07-08  Kito Cheng  
>>
>> * function.c (stack_protect_epilogue): Use if rather than switch for
>> check targetm.have_stack_protect_test().
>
> Do you really need this?  This should be just non-fatal warning in stage1,
> and only if you compile with gcc-5, right?
> You could also just cast the controlling expression of the switch to int to
> suppress the warning.
>
> Marek

Re: fix PR46029: reimplement if conversion of loads and stores

[Abe]

(if-conversion could directly generate masked load/stores
  of course and not use a scratch-pad at all in that case).


[Abe wrote:]

IMO that`s a great idea, but I don`t know how to do it.
Hints would be welcome.  In particular, how does one

>> "generate masked load/stores" at the GIMPLE level?

[Richard Biener wrote:]

It already does that, see predicate_mem_writes.

> You should definitely preserve that path

Thanks.  Yes, we have not intentionally disabled that.



On what hardware did you test?


AMD64 arch., Intel implementation.  Nothing fancy AFAIK in the flags to make it 
super-specific,
e.g. "-march=nocona" or "-march=native".  Occasionally using AVX-2 flags as 
specified by some test cases.

Regards,

Abe

darwin fix for gcc-5 (RM please)

[Mike Stump]

I’d like to merge in the fix from https://gcc.gnu.org/PR66523 into the 
gcc-5-branch.

RM Ok?

https://gcc.gnu.org/bugzilla/attachment.cgi?id=35773:
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 40804b8..0080299 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -1259,6 +1259,11 @@ darwin_encode_section_info (tree decl, rtx rtl, int 
first ATTRIBUTE_UNUSED)
 void
 darwin_mark_decl_preserved (const char *name)
 {
+  /* Actually we shouldn't mark any local symbol this way, but for now
+ this only happens with ObjC meta-data.  */
+  if (darwin_label_is_anonymous_local_objc_name (name))
+return;
+
   fprintf (asm_out_file, "\t.no_dead_strip ");
   assemble_name (asm_out_file, name);
   fputc ('\n', asm_out_file);

Re: [AArch64][2/2] Define TARGET_UNSPEC_MAY_TRAP_P for AArch64

[James Greenhalgh]

On Tue, Jul 07, 2015 at 01:52:29PM +0100, Jiong Wang wrote:
> 
> A second patch to improve rtl loop iv on AArch64.
> 
> We should define this to tell gcc the pattern hidden by these GOT unspec
> is safe from trap, so gcc could make more positive decision when
> handling them, for example in RTL loop iv pass, when deciding whether
> one instruction is invariant candidate, may_trap_or_fault_p will be
> invoked which will call this target hook.
> 
> OK for trunk?
> 
> 2015-07-07  Jiong Wang  
> 
> gcc/
>   * config/aarch64/aarch64.c (aarch64_unspec_may_trap_p): New function.
>   (TARGET_UNSPEC_MAY_TRAP_P): Define as aarch64_unspec_may_trap_p.

OK.

Thanks,
James

>   
> -- 
> Regards,
> Jiong
> 

> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index e180daa..c7c12ee 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -11943,6 +11943,24 @@ aarch64_use_pseudo_pic_reg (void)
>return aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC;
>  }
>  
> +/* Implement TARGET_UNSPEC_MAY_TRAP_P.  */
> +
> +static int
> +aarch64_unspec_may_trap_p (const_rtx x, unsigned flags)
> +{
> +  switch (XINT (x, 1))
> +{
> +case UNSPEC_GOTSMALLPIC:
> +case UNSPEC_GOTSMALLPIC28K:
> +case UNSPEC_GOTTINYPIC:
> +  return 0;
> +default:
> +  break;
> +}
> +
> +  return default_unspec_may_trap_p (x, flags);
> +}
> +
>  #undef TARGET_ADDRESS_COST
>  #define TARGET_ADDRESS_COST aarch64_address_cost
>  
> @@ -12221,6 +12239,9 @@ aarch64_use_pseudo_pic_reg (void)
>  #undef TARGET_SCHED_FUSION_PRIORITY
>  #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
>  
> +#undef TARGET_UNSPEC_MAY_TRAP_P
> +#define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
> +
>  #undef TARGET_USE_PSEUDO_PIC_REG
>  #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
>  

Re: [PATCH]Fix PR66556. Don't drop side-effect in simplify_const_relational_operation function.

[Segher Boessenkool]

On Wed, Jul 08, 2015 at 04:03:47PM +0100, Renlin Li wrote:
> PR rtl/66556
> * simplify-rtx.c (simplify_const_relational_operation): Add
> side_effects_p check.

"checks"?

The patch looks good to me, but someone else will need to approve.


Segher

Re: [PATCH] PR target/66746: Failure to compile #include with -miamcu

[H.J. Lu]

On Thu, Jul 2, 2015 at 11:16 PM, Uros Bizjak  wrote:
> On Fri, Jul 3, 2015 at 5:53 AM, H.J. Lu  wrote:
>> x86intrin.h has useful intrinsics for instructions for IA MCU.  This
>> patch adds __iamcu__ check to x86intrin.h and ia32intrin.h.
>>
>> OK for trunk?
>>
>> H.J.
>> ---
>> gcc/
>>
>> PR target/66746
>> * config/i386/ia32intrin.h (__crc32b): Don't define if __iamcu__
>> is defined.
>> (__crc32w): Likewise.
>> (__crc32d): Likewise.
>> (__rdpmc): Likewise.
>> (__rdtscp): Likewise.
>> (_rdpmc): Likewise.
>> (_rdtscp): Likewise.
>> * config/i386/x86intrin.h: Only include ia32intrin.h if __iamcu__
>> is defined.
>>
>> gcc/testsuite/
>>
>> PR target/66746
>> * gcc.target/i386/pr66746.c: New file.
>
> OK.
>

It is OK to include  for IA MCU since GCC can generate ADX
intrinsics with alternative instuctions if ADX isn't enabled.

OK for trunk?

H.J.
---
PR target/66746
* config/i386/x86intrin.h: Include  if
__iamcu__ is defined.
From b1c38ef504f92ce6b085a1faace7d85566335654 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" 
Date: Wed, 8 Jul 2015 09:36:27 -0700
Subject: [PATCH] Allow  for IA MCU

It is OK to include  for IA MCU since GCC can generate ADX
intrinsics with alternative instuctions if ADX isn't enabled.

	PR target/66746
	* config/i386/x86intrin.h: Include  if
	__iamcu__ is defined.
---
 gcc/config/i386/x86intrin.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/gcc/config/i386/x86intrin.h b/gcc/config/i386/x86intrin.h
index be0a1a1..3ff571d 100644
--- a/gcc/config/i386/x86intrin.h
+++ b/gcc/config/i386/x86intrin.h
@@ -75,8 +75,12 @@
 
 #include 
 
+#endif /* __iamcu__ */
+
 #include 
 
+#ifndef __iamcu__
+
 #include 
 
 #include 
-- 
2.4.3

Re: [RS6000 7/7] Address cost

[Segher Boessenkool]

On Wed, Jun 24, 2015 at 10:25:46AM +0930, Alan Modra wrote:
> @@ -30720,14 +30721,20 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int 
> outer_code,
> - (outer_code == SET ? 1 : 0));
>return true;
>  
> -case CONST:
> -case HIGH:
> -case SYMBOL_REF:
>  case MEM:
>/* When optimizing for size, MEM should be slightly more expensive
>than generating address, e.g., (plus (reg) (const)).
>L1 cache latency is about two instructions.  */
>*total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
> +  *total += COSTS_N_INSNS (rs6000_address_cost (XEXP (x, 0), mode,
> + 0, speed));

So the unit of address cost is whole insns?  Eww.

> +  return true;
> +
> +case CONST:
> +case HIGH:
> +case LO_SUM:
> +case SYMBOL_REF:
> +  *total = COSTS_N_INSNS (1);
>return true;

Why is the cost of CONST only one insn?  Shouldn't you take the (address)
cost of whatever is inside it?


Segher

Re: [PATCH] fix PR46029: reimplement if conversion of loads and stores [2nd submitted version of patch]

[Alan Lawrence]

Abe wrote:

[Alan wrote:]


Where can I find info on what the different flag values mean?
(I had thought they were booleans [...]



[Abe wrote:]


Sorry; I don`t know if that is documented anywhere yet.



In this case, (-1) simply means "defaulted": on if the vectorizer is on, and 
off if it is off.
(0) means "user specified no if conversion" and (1) means "user specified [yes] if 
conversion".



[Alan wrote:]


Ah, right, that makes sense now. Obviously I would like to see this written in 
doc/ .


Is the following sufficient?  From "doc/invoke.texi", I propose to replace:

   This is enabled by default if vectorization is enabled.

... with:

   This is enabled by default when vectorization is  enabled
   anddisabled by default when vectorization is disabled.



That would be helpful - but has the syntax not changed? I was thinking it'd be 
useful to document somewher the meanings of 1/0/-1, as you explained them to me:


> In this case, (-1) simply means "defaulted": on if the vectorizer is on, and 
off if it is off.
> (0) means "user specified no if conversion" and (1) means "user specified 
[yes] if conversion".


Perhaps in the gate() function if not in the doc.

Thanks, Alan

[committed, PATCH] Add abort prototype to readeflags-1.c/writeeflags-1.c

[H.J. Lu]

Index: ChangeLog
===
--- ChangeLog   (revision 225565)
+++ ChangeLog   (working copy)
@@ -1,3 +1,8 @@
+2015-07-08  H.J. Lu  
+
+   * gcc.target/i386/readeflags-1.c (abort): New prototype.
+   * gcc.target/i386/writeeflags-1.c (abort): Likewise.
+
 2015-07-08  Paolo Carlini  
 
PR c++/66421
Index: gcc.target/i386/readeflags-1.c
===
--- gcc.target/i386/readeflags-1.c  (revision 225565)
+++ gcc.target/i386/readeflags-1.c  (working copy)
@@ -3,6 +3,8 @@
 
 #include 
 
+extern void abort (void);
+
 #ifdef __x86_64__
 #define EFLAGS_TYPE unsigned long long int
 #else
Index: gcc.target/i386/writeeflags-1.c
===
--- gcc.target/i386/writeeflags-1.c (revision 225565)
+++ gcc.target/i386/writeeflags-1.c (working copy)
@@ -3,6 +3,8 @@
 
 #include 
 
+extern void abort (void);
+
 #ifdef __x86_64__
 #define EFLAGS_TYPE unsigned long long int
 #else

Re: [committed] Flags outputs for asms

[H.J. Lu]

On Mon, Jun 29, 2015 at 7:44 AM, Richard Henderson  wrote:
> Sorry for the delay, but here's the third and final version.
> This includes the requested cpp symbol and updated documentation.

gcc.target/i386/asm-flag-5.c failed with -march=pentium:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66813

-- 
H.J.

Re: RFC: Add ADDR_EXPR lowering (PR tree-optimization/66718)

[Marek Polacek]

On Sun, Jul 05, 2015 at 11:10:14AM +0800, Bin.Cheng wrote:
> > Just FYI, while bootstrapping/regtesting your patch together with the one
> > I've posted and another one to vectorize pr59984.c better, I've noticed 
> > there
> > is another regression with your patch (reverting my patches doesn't help,
> > disabling your gate does help):
> >
> > +FAIL: libgomp.c/simd-3.c execution test
> > +FAIL: libgomp.c++/simd-3.C execution test
> >
> > on both x86_64-linux and i686-linux (at least on AVX capable box).
> > Most likely hitting another latent vectorizer issue, haven't analyzed it
> > yet.
> Bootstrap and test the patch on aarch64.  Also saw these two failures,
> plus below one

Thanks for testing.

> FAIL: libgomp.fortran/target6.f90   -Os  execution test
> 
> Maybe the same cause with above two.  I will test later with Jakub's patch.

I suppose these are fixed now.
 
> Another problem is the added test failed on aarch64.  I attacked the dump 
> here.

That's because on aarch64 we aren't able to vectorize as much as on x86_64.
I'll post a new version of the patch in a bit with the test restricted to
x86_64/i?86.

Marek

Re: RFC: Add ADDR_EXPR lowering (PR tree-optimization/66718)

[Marek Polacek]

On Fri, Jul 03, 2015 at 03:41:29PM +0200, Richard Biener wrote:
> On Fri, 3 Jul 2015, Marek Polacek wrote:
> 
> > This patch implements a new pass, called laddress, which deals with
> > lowering ADDR_EXPR assignments.  Such lowering ought to help the
> > vectorizer, but it also could expose more CSE opportunities, maybe
> > help reassoc, etc.  It's only active when optimize != 0.
> > 
> > So e.g.
> >   _1 = (sizetype) i_9;
> >   _7 = _1 * 4;
> >   _4 = &b + _7;
> > instead of
> >   _4 = &b[i_9];
> > 
> > This triggered 14105 times during the regtest and 6392 times during
> > the bootstrap.
> > 
> > The fallout (at least on x86_64) is surprisingly small, i.e. none, just
> > gcc.dg/vect/pr59984.c test (using -fopenmp-simd) ICEs, but that is due
> > to a bug in the vectorizer.  Jakub has a patch and knows the details.
> > As the test shows, we're now able to vectorize ADDR_EXPR of non-invariants
> > (that was the motivation of this pass).
> > 
> > This doesn't introduce any kind of verification nor PROP_laddress.
> > Don't know if we want that, but hopefully it can be done as a follow-up
> > if we do.
> 
> Yes.  At the moment nothing requires lowered address form so this is
> merely an optimization (and not a bug for some later pass to
> re-introduce un-lowered non-invariant addresses).  I can imagine
> that for example IVOPTs could be simplified if we didn't have this
> kind of addresses in the IL.
> 
> > Do we want to move some optimizations into this new pass, e.g.
> > from fwprop?
> 
> I think we might want to re-try forwprop_into_addr_expr before lowering
> the address.  Well, but that's maybe just over-cautionous.
> 
> > Thoughts?
> 
> Please move the pass before crited, crited and pre are supposed to
> go together.

Done.
 
> Otherwise looks ok to me.

I renamed the file to gimple-laddress.c then and adjusted the timevar.
Another change is that for x86_64 we don't need -mavx at all, so I dropped
that.  The test is now restricted to x86_64/i?86; on aarch64/ppc64 we aren't
able to vectorize all the functions.

Bootstrapped/regtested on x86_64-linux + ppc64-linux, ok for trunk?

2015-07-08  Marek Polacek  

PR tree-optimization/66718
* Makefile.in (OBJS): Add gimple-laddress.o. 
* passes.def: Schedule pass_laddress.
* timevar.def (DEFTIMEVAR): Add TV_GIMPLE_LADDRESS.
* tree-pass.h (make_pass_laddress): Declare.
* gimple-laddress.c: New file.

* gcc.dg/vect/vect-126.c: New test.

diff --git gcc/Makefile.in gcc/Makefile.in
index 89eda96..1817025 100644
--- gcc/Makefile.in
+++ gcc/Makefile.in
@@ -1255,6 +1255,7 @@ OBJS = \
gimple-expr.o \
gimple-iterator.o \
gimple-fold.o \
+   gimple-laddress.o \
gimple-low.o \
gimple-match.o \
generic-match.o \
diff --git gcc/gimple-laddress.c gcc/gimple-laddress.c
index e69de29..c8036b9 100644
--- gcc/gimple-laddress.c
+++ gcc/gimple-laddress.c
@@ -0,0 +1,137 @@
+/* Lower and optimize address expressions.
+   Copyright (C) 2015 Free Software Foundation, Inc.
+   Contributed by Marek Polacek 
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "alias.h"
+#include "predict.h"
+#include "tm.h"
+#include "function.h"
+#include "dominance.h"
+#include "cfg.h"
+#include "basic-block.h"
+#include "tree-ssa-alias.h"
+#include "symtab.h"
+#include "tree.h"
+#include "stringpool.h"
+#include "tree-ssanames.h"
+#include "fold-const.h"
+#include "gimple-expr.h"
+#include "gimple.h"
+#include "gimplify.h"
+#include "gimple-iterator.h"
+#include "gimplify-me.h"
+#include "tree-pass.h"
+
+
+namespace {
+
+const pass_data pass_data_laddress =
+{
+  GIMPLE_PASS, /* type */
+  "laddress", /* name */
+  OPTGROUP_NONE, /* optinfo_flags */
+  TV_GIMPLE_LADDRESS, /* tv_id */
+  ( PROP_cfg | PROP_ssa ), /* properties_required */
+  0, /* properties_provided */
+  0, /* properties_destroyed */
+  0, /* todo_flags_start */
+  0, /* todo_flags_finish */
+};
+
+class pass_laddress : public gimple_opt_pass
+{
+public:
+  pass_laddress (gcc::context *ctxt)
+: gimple_opt_pass (pass_data_laddress, ctxt)
+  {}
+
+  /* opt_pass methods: */
+  opt_pass * clone () { return new pass_laddress (m_ctxt); }
+  virtual bool gate (function *) { return optimize != 0; }
+  virtual unsigned int execute (function *);
+
+}; // class pass_laddress
+
+unsig

Re: [PATCH] PR target/66746: Failure to compile #include with -miamcu

[Uros Bizjak]

On Wed, Jul 8, 2015 at 6:43 PM, H.J. Lu  wrote:

>>> x86intrin.h has useful intrinsics for instructions for IA MCU.  This
>>> patch adds __iamcu__ check to x86intrin.h and ia32intrin.h.
>>>
>>> OK for trunk?
>>>
>>> H.J.
>>> ---
>>> gcc/
>>>
>>> PR target/66746
>>> * config/i386/ia32intrin.h (__crc32b): Don't define if __iamcu__
>>> is defined.
>>> (__crc32w): Likewise.
>>> (__crc32d): Likewise.
>>> (__rdpmc): Likewise.
>>> (__rdtscp): Likewise.
>>> (_rdpmc): Likewise.
>>> (_rdtscp): Likewise.
>>> * config/i386/x86intrin.h: Only include ia32intrin.h if __iamcu__
>>> is defined.
>>>
>>> gcc/testsuite/
>>>
>>> PR target/66746
>>> * gcc.target/i386/pr66746.c: New file.
>>
>> OK.
>>
>
> It is OK to include  for IA MCU since GCC can generate ADX
> intrinsics with alternative instuctions if ADX isn't enabled.
>
> OK for trunk?
>
> H.J.
> ---
> PR target/66746
> * config/i386/x86intrin.h: Include  if
> __iamcu__ is defined.

Ok if tested properly.

Thanks,
Uros.

[gomp4] Handle Fortran deviceptr clause.

[James Norris]

Hi,

This patch adds handling of the deviceptr clause when
used within a Fortran program.


Committed to gomp-4_0-branch

Jim
diff --git a/libgomp/ChangeLog.gomp b/libgomp/ChangeLog.gomp
index 418474d..1949d78 100644
--- a/libgomp/ChangeLog.gomp
+++ b/libgomp/ChangeLog.gomp
@@ -1,3 +1,8 @@
+2015-07-08  James Norris  
+
+	* oacc-parallel.c (GOACC_parallel GOACC_data_start): Handle Fortran
+	deviceptr clause.
+
 2015-07-07  Thomas Schwinge  
 
 	* testsuite/libgomp.oacc-c++/c++.exp (check_effective_target_c):
diff --git a/libgomp/oacc-parallel.c b/libgomp/oacc-parallel.c
index 70758bc..eeb08c4 100644
--- a/libgomp/oacc-parallel.c
+++ b/libgomp/oacc-parallel.c
@@ -211,6 +211,21 @@ GOACC_parallel (int device, void (*fn) (void *),
   thr = goacc_thread ();
   acc_dev = thr->dev;
 
+  for (i = 0; i < mapnum; i++)
+{
+  unsigned short kind1 = kinds[i] & 0xff;
+  unsigned short kind2 = kinds[i+1] & 0xff;
+
+  if ((kind1 == GOMP_MAP_FORCE_DEVICEPTR && kind2 == GOMP_MAP_POINTER)
+	   && (sizes[i + 1] == 0)
+	   && (hostaddrs[i] == *(void **)hostaddrs[i + 1]))
+	{
+	  kinds[i+1] = kinds[i];
+	  sizes[i+1] = sizeof (void *);
+	  hostaddrs[i] = NULL;
+	}
+}
+
   /* Host fallback if "if" clause is false or if the current device is set to
  the host.  */
   if (host_fallback)
@@ -263,8 +278,13 @@ GOACC_parallel (int device, void (*fn) (void *),
 
   devaddrs = gomp_alloca (sizeof (void *) * mapnum);
   for (i = 0; i < mapnum; i++)
-devaddrs[i] = (void *) (tgt->list[i]->tgt->tgt_start
-			+ tgt->list[i]->tgt_offset);
+{
+  if (tgt->list[i] != NULL)
+	devaddrs[i] = (void *) (tgt->list[i]->tgt->tgt_start
++ tgt->list[i]->tgt_offset);
+  else
+	devaddrs[i] = NULL;
+}
 
   acc_dev->openacc.exec_func (tgt_fn, mapnum, hostaddrs, devaddrs, sizes, kinds,
 			  num_gangs, num_workers, vector_length, async,
@@ -291,6 +311,7 @@ GOACC_data_start (int device, size_t mapnum,
 {
   bool host_fallback = device == GOMP_DEVICE_HOST_FALLBACK;
   struct target_mem_desc *tgt;
+  int i;
 
 #ifdef HAVE_INTTYPES_H
   gomp_debug (0, "%s: mapnum=%"PRIu64", hostaddrs=%p, sizes=%p, kinds=%p\n",
@@ -305,6 +326,21 @@ GOACC_data_start (int device, size_t mapnum,
   struct goacc_thread *thr = goacc_thread ();
   struct gomp_device_descr *acc_dev = thr->dev;
 
+  for (i = 0; i < mapnum; i++)
+{
+  unsigned short kind1 = kinds[i] & 0xff;
+  unsigned short kind2 = kinds[i+1] & 0xff;
+
+  if ((kind1 == GOMP_MAP_FORCE_DEVICEPTR && kind2 == GOMP_MAP_POINTER)
+	   && (sizes[i + 1] == 0)
+	   && (hostaddrs[i] == *(void **)hostaddrs[i + 1]))
+	{
+	  kinds[i+1] = kinds[i];
+	  sizes[i+1] = sizeof (void *);
+	  hostaddrs[i] = NULL;
+	}
+}
+
   /* Host fallback or 'do nothing'.  */
   if ((acc_dev->capabilities & GOMP_OFFLOAD_CAP_SHARED_MEM)
   || host_fallback)
@@ -673,8 +709,6 @@ GOACC_register_static (void *addr, int size, unsigned int mask)
oacc_statics = s;
 }
 
-#include 
-
 void
 GOACC_declare (int device, size_t mapnum,
 	   void **hostaddrs, size_t *sizes, unsigned short *kinds)

Re: [PATCH] fix PR46029: reimplement if conversion of loads and stores [2nd submitted version of patch]

[Abe]

[Abe wrote:]

Is the following sufficient?  From "doc/invoke.texi", I propose to replace:



   This is enabled by default if vectorization is enabled.



... with:



   This is enabled by default when vectorization is  enabled
   anddisabled by default when vectorization is disabled.




[Alan wrote:]


That would be helpful - but has the syntax not changed?


AFAIK & IIRC, not yet.  We plan to change the flags later.


[Alan wrote:]

I was thinking it'd be useful to document somewher the meanings of 1/0/-1, as 
you explained them to me:

[snip]

Perhaps in the gate() function if not in the doc.


OK.  It seemed like the doc files was not the right place to document internal 
values that flags influence.

Regards,

Abe

Re: [GOOGLE] Only save command-line options for LIPO

[Teresa Johnson]

Resending in plain text mode.

On Wed, Jul 8, 2015 at 11:34 AM, Teresa Johnson  wrote:
> This patch avoids saving optimization pragma or function level attributes in
> the list of command line options saved in the LIPO module info structure.
> Passes regression and internal testing. Ok for google/4_9?
>
> Thanks,
> Teresa
>
> 2015-07-08  Teresa Johnson  
>
> * gcc/c-family/c-common.c (parse_optimize_options): New parameter.
> * gcc/opts-global.c (read_cmdline_options): Use new parameter to
> guard saving of LIPO command line options.
> (decode_options): New parameter.
> * gcc/opts.h (extern void decode_options): Ditto.
> * gcc/toplev.c (toplev_main): Ditto.
>
> Index: gcc/c-family/c-common.c
> ===
> --- gcc/c-family/c-common.c (revision 225521)
> +++ gcc/c-family/c-common.c (working copy)
> @@ -9200,7 +9200,7 @@ parse_optimize_options (tree args, bool attr_p)
> &decoded_options_count);
>decode_options (&global_options, &global_options_set,
>   decoded_options, decoded_options_count,
> - input_location, global_dc);
> + input_location, global_dc, false);
>
>targetm.override_options_after_change();
>
> Index: gcc/opts-global.c
> ===
> --- gcc/opts-global.c   (revision 225521)
> +++ gcc/opts-global.c   (working copy)
> @@ -299,7 +299,9 @@ lipo_save_cl_args (struct cl_decoded_option *decod
> the results of processing DECODED_OPTIONS and DECODED_OPTIONS_COUNT
> in OPTS and OPTS_SET and using DC for diagnostic state.  LANG_MASK
> contains has a single bit set representing the current language.
> -   HANDLERS describes what functions to call for the options.  */
> +   HANDLERS describes what functions to call for the options.
> +   If COMMAND_LINE is true, this is being invoked for file level command
> +   line options, otherwise for an optimize pragma or function attribute.
> */
>
>  static void
>  read_cmdline_options (struct gcc_options *opts, struct gcc_options
> *opts_set,
> @@ -308,7 +310,8 @@ read_cmdline_options (struct gcc_options *opts, st
>   location_t loc,
>   unsigned int lang_mask,
>   const struct cl_option_handlers *handlers,
> - diagnostic_context *dc)
> + diagnostic_context *dc,
> +  bool command_line)
>  {
>unsigned int i;
>int force_multi_module = 0;
> @@ -341,7 +344,8 @@ read_cmdline_options (struct gcc_options *opts, st
>read_cmdline_option (opts, opts_set,
>decoded_options + i, loc, lang_mask, handlers,
>dc);
> -  lipo_save_cl_args (decoded_options + i);
> +  if (command_line)
> +lipo_save_cl_args (decoded_options + i);
>  }
>  }
>
> @@ -393,12 +397,14 @@ set_default_handlers (struct cl_option_handlers *h
>  /* Parse command line options and set default flag values.  Do minimal
> options processing.  The decoded options are in *DECODED_OPTIONS
> and *DECODED_OPTIONS_COUNT; settings go in OPTS, OPTS_SET and DC;
> -   the options are located at LOC.  */
> +   the options are located at LOC.  If COMMAND_LINE is true, this is
> +   being invoked for file level command line options, otherwise for
> +   an optimize pragma or function attribute.  */
>  void
>  decode_options (struct gcc_options *opts, struct gcc_options *opts_set,
> struct cl_decoded_option *decoded_options,
> unsigned int decoded_options_count,
> -   location_t loc, diagnostic_context *dc)
> +   location_t loc, diagnostic_context *dc, bool command_line)
>  {
>struct cl_option_handlers handlers;
>
> @@ -415,7 +421,7 @@ decode_options (struct gcc_options *opts, struct g
>read_cmdline_options (opts, opts_set,
> decoded_options, decoded_options_count,
> loc, lang_mask,
> -   &handlers, dc);
> +   &handlers, dc, command_line);
>
>finish_options (opts, opts_set, loc);
>  }
> Index: gcc/opts.h
> ===
> --- gcc/opts.h  (revision 225521)
> +++ gcc/opts.h  (working copy)
> @@ -344,7 +344,8 @@ extern void decode_options (struct gcc_options *op
> struct cl_decoded_option *decoded_options,
> unsigned int decoded_options_count,
> location_t loc,
> -   diagnostic_context *dc);
> +   diagnostic_context *dc,
> +bool command_line);
>  extern int option_enabled (int opt_idx, void *opts);
>  extern bool get_option_state (struct gcc_options *, int,
>   

[committed, PATCH] Compile pr37870.c with -mlong-double-80

[H.J. Lu]

On x86, the "long double" type is platforma specific, which may be the
same as double or __float128.  Since pr37870.c requires 80-bit floating
point type, it should be compiled with -mlong-double-80.

* gcc.target/i386/pr37870.c (dg-options): Add -mlong-double-80.
---
 gcc/testsuite/gcc.target/i386/pr37870.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/i386/pr37870.c 
b/gcc/testsuite/gcc.target/i386/pr37870.c
index 19cfb20..bc78ed7 100644
--- a/gcc/testsuite/gcc.target/i386/pr37870.c
+++ b/gcc/testsuite/gcc.target/i386/pr37870.c
@@ -1,6 +1,6 @@
 /* PR middle-end/37870 */
 /* { dg-do run } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -mlong-double-80" } */
 
 unsigned int
 foo (long double x)
-- 
2.4.3

Re: [PATCH] S390: Support -mtune=native and -march=native.

[DJ Delorie]

> Version 2 of the patch to enable the configure options
> --with-arch=native and --with-tune=native.

This patch broke cross-compiling with --target=s390-*

s390_host_detect_local_cpu is only defined if the --host is s390-*

but EXTRA_SPEC_FUNCTIONS refers to it when --target is s390-*

[committed] Fix -fopenmp-simd C++ handling and one declare simd error recovery fix

[Jakub Jelinek]

Hi!

While hacking on gomp-4.1 branch, I've noticed that -fopenmp-simd
is broken for C++ for #pragma omp declare simd, and there is also an
error recovery issue in c_omp_declare_simd_clauses_to_numbers.
Additionally, tree-vect.h had some issues when included from C++ testcases,
fixed those too so that I can include the new C++ testcase.

Bootstrapped/regtested on x86_64-linux and i686-linux, committed to trunk.

2015-07-08  Jakub Jelinek  

* c-omp.c (c_omp_declare_simd_clauses_to_numbers): If all clauses
are to be removed, return NULL rather than original clauses list.

* decl.c (grokfndecl): Handle flag_openmp_simd like flag_openmp.
* pt.c (apply_late_template_attributes): Likewise.

* g++.dg/vect/vect.exp: Run also simd* tests.
* gcc.dg/vect/tree-vect.h (abort, exit): For C++ use extern "C".
(check_vect): Fix up get_cpuid call for C++.
* g++.dg/vect/simd-clone-1.cc: New test.

--- gcc/c-family/c-omp.c.jj 2015-06-30 14:24:33.0 +0200
+++ gcc/c-family/c-omp.c2015-07-08 19:45:22.681603168 +0200
@@ -1092,6 +1092,8 @@ c_omp_declare_simd_clauses_to_numbers (t
   for (i = 0; i < len; i++)
OMP_CLAUSE_CHAIN (clvec[i]) = (i < len - 1) ? clvec[i + 1] : NULL_TREE;
 }
+  else
+clauses = NULL_TREE;
   clvec.release ();
   return clauses;
 }
--- gcc/cp/decl.c.jj2015-06-30 14:25:15.0 +0200
+++ gcc/cp/decl.c   2015-07-08 18:31:02.591975136 +0200
@@ -7905,7 +7905,7 @@ grokfndecl (tree ctype,
   if (TYPE_NOTHROW_P (type) || nothrow_libfn_p (decl))
 TREE_NOTHROW (decl) = 1;
 
-  if (flag_openmp || flag_cilkplus)
+  if (flag_openmp || flag_openmp_simd || flag_cilkplus)
 {
   /* Adjust "omp declare simd" attributes.  */
   tree ods = lookup_attribute ("omp declare simd", *attrlist);
--- gcc/cp/pt.c.jj  2015-07-06 13:23:11.0 +0200
+++ gcc/cp/pt.c 2015-07-08 18:31:22.988688810 +0200
@@ -9065,7 +9065,7 @@ apply_late_template_attributes (tree *de
{
  *p = TREE_CHAIN (t);
  TREE_CHAIN (t) = NULL_TREE;
- if ((flag_openmp || flag_cilkplus)
+ if ((flag_openmp || flag_openmp_simd || flag_cilkplus)
  && is_attribute_p ("omp declare simd",
 get_attribute_name (t))
  && TREE_VALUE (t))
--- gcc/testsuite/g++.dg/vect/vect.exp.jj   2015-04-24 12:31:59.0 
+0200
+++ gcc/testsuite/g++.dg/vect/vect.exp  2015-07-08 18:24:16.799688191 +0200
@@ -58,7 +58,7 @@ lappend VECT_SLP_CFLAGS "-fdump-tree-slp
 dg-init
 
 # Main loop.
-g++-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/pr*.{c,cc,S} ]] \
+g++-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/{pr,simd}*.{c,cc,S} ]] 
\
 "" $DEFAULT_VECTCFLAGS
 g++-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/slp-pr*.{c,cc,S} ]] \
 "" $VECT_SLP_CFLAGS
--- gcc/testsuite/gcc.dg/vect/tree-vect.h.jj2015-04-24 12:31:56.0 
+0200
+++ gcc/testsuite/gcc.dg/vect/tree-vect.h   2015-07-08 18:33:40.066764526 
+0200
@@ -5,8 +5,14 @@
 # include "cpuid.h"
 #endif
 
+#ifdef __cplusplus
+extern "C" {
+#endif
 extern void abort (void);
 extern void exit (int);
+#ifdef __cplusplus
+}
+#endif
 
 static void
 sig_ill_handler (int sig)
@@ -26,7 +32,7 @@ check_vect (void)
   asm volatile (".long 0x1484");
 #elif defined(__i386__) || defined(__x86_64__)
   {
-int a, b, c, d, want_level, want_c, want_d;
+unsigned int a, b, c, d, want_level, want_c, want_d;
 
 /* Determine what instruction set we've been compiled for, and detect
that we're running with it.  This allows us to at least do a compile
--- gcc/testsuite/g++.dg/vect/simd-clone-1.cc.jj2015-07-08 
18:37:39.905397704 +0200
+++ gcc/testsuite/g++.dg/vect/simd-clone-1.cc   2015-07-08 18:41:13.577398206 
+0200
@@ -0,0 +1,55 @@
+// { dg-require-effective-target vect_simd_clones }
+// { dg-additional-options "-fopenmp-simd -fno-inline" }
+// { dg-additional-options "-mavx" { target avx_runtime } }
+
+#include "../../gcc.dg/vect/tree-vect.h"
+
+struct S
+{
+  int s;
+  #pragma omp declare simd notinbranch linear(x)
+  int f (int x);
+};
+
+#pragma omp declare simd notinbranch linear(x)
+int
+S::f (int x)
+{
+  return x;
+}
+
+template 
+struct T
+{
+  int t;
+  #pragma omp declare simd notinbranch linear(x)
+  int f (int x);
+};
+
+#pragma omp declare simd notinbranch linear(x)
+template 
+int
+T::f (int x)
+{
+  return x;
+}
+
+void
+do_main ()
+{
+  int i, r = 0;
+  S s;
+  T<0> t;
+  #pragma omp simd reduction(+:r)
+  for (i = 0; i < 64; i++)
+r += s.f (i) + t.f (i);
+  if (r != 64 * 63)
+abort ();
+}
+
+int
+main ()
+{
+  check_vect ();
+  do_main ();
+}

Jakub

Re: [PATCH] PR target/35514: Gcc shoud generate symbol type for undefined symbol

[H.J. Lu]

On Sun, Jul 5, 2015 at 2:54 PM, H.J. Lu  wrote:
> On Sun, Jul 5, 2015 at 11:14 AM, H.J. Lu  wrote:
>> Update default_elf_asm_output_external to also output symbol type to
>> help ELF linker to properly issue diagnostic message.  We don't output
>> symbol type for reference to external TLS symbol since assembler will
>> generate TLS symbol type based on TLS relocation and Solaris assembler
>> only supports the @tls_obj type directive, not the @tls_object type
>> directive used by GNU assmbler, which doesn't understand the @tls_obj
>> type directive.
>>
>> Tested on Linux/x86-64.  OK for trunk?
>>
>> Thanks.
>>
>>
>> H.J.
>> ---
>> gcc/
>>
>> PR target/35514
>> * varasm.c (default_elf_asm_output_external): Also output symbol
>> type.
>>
>> gcc/testsuite/
>>
>> PR target/35514
>> * lib/target-supports.exp (check_effective_target_elf): New.
>> * gcc.dg/pr35514-1.c: New file.
>> * gcc.dg/pr35514-2.c: Likewise.
>> ---
>>  gcc/testsuite/gcc.dg/pr35514-1.c  | 16 
>>  gcc/testsuite/gcc.dg/pr35514-2.c  | 14 ++
>>  gcc/testsuite/lib/target-supports.exp | 20 
>>  gcc/varasm.c  | 22 +-
>>  4 files changed, 67 insertions(+), 5 deletions(-)
>>  create mode 100644 gcc/testsuite/gcc.dg/pr35514-1.c
>>  create mode 100644 gcc/testsuite/gcc.dg/pr35514-2.c
>>
>> diff --git a/gcc/testsuite/gcc.dg/pr35514-1.c 
>> b/gcc/testsuite/gcc.dg/pr35514-1.c
>> new file mode 100644
>> index 000..8a1d99d
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.dg/pr35514-1.c
>> @@ -0,0 +1,16 @@
>> +/* { dg-do compile { target { elf } } } */
>> +/* { dg-options "-O2" } */
>> +/* { dg-final { scan-assembler ".type\[^\\n\]*object, (%|@)object" } } */
>> +/* { dg-final { scan-assembler ".type\[^\\n\]*function, (%|@)function" } } 
>> */
>> +
>> +/* Verify that we generate proper symbol types for external reference.  */
>> +
>> +extern int object;
>> +void function (void);
>> +
>> +int
>> +foo (void)
>> +{
>> +  function ();
>> +  return object;
>> +}
>> diff --git a/gcc/testsuite/gcc.dg/pr35514-2.c 
>> b/gcc/testsuite/gcc.dg/pr35514-2.c
>> new file mode 100644
>> index 000..f67af5a
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.dg/pr35514-2.c
>> @@ -0,0 +1,14 @@
>> +/* { dg-do compile { target { elf } } } */
>> +/* { dg-require-effective-target tls } */
>> +/* { dg-options "-O2" } */
>> +/* { dg-final { scan-assembler-not ".type\[^\\n\]*object, (%|@)object" } } 
>> */
>> +
>> +/* Verify that we generate proper symbol types for external reference.  */
>> +
>> +extern __thread int object;
>> +
>> +int
>> +foo (void)
>> +{
>> +  return object;
>> +}
>> diff --git a/gcc/testsuite/lib/target-supports.exp 
>> b/gcc/testsuite/lib/target-supports.exp
>> index bf512e9..c3ec209 100644
>> --- a/gcc/testsuite/lib/target-supports.exp
>> +++ b/gcc/testsuite/lib/target-supports.exp
>> @@ -6349,3 +6349,23 @@ proc check_effective_target_comdat_group {} {
>> int (*fn) () = foo;
>>  }]
>>  }
>> +
>> +# Returns 1 if the target is ELF.
>> +
>> +proc check_effective_target_elf { } {
>> +global check_effective_target_elf_saved
>> +global tool
>> +
>> +if [info exists check_effective_target_elf_saved] {
>> +verbose "check_effective_target_elf returning saved 
>> $check_effective_target_elf_saved" 2
>> +} else {
>> +   set objformat [gcc_target_object_format]
>> +   if { $objformat == "elf" } {
>> +   set check_effective_target_elf_saved 1
>> +   } else {
>> +   set check_effective_target_elf_saved 0
>> +   }
>> +verbose "check_effective_target_elf returning 
>> $check_effective_target_elf_saved" 2
>> +}
>> +return $check_effective_target_elf_saved
>> +}
>> diff --git a/gcc/varasm.c b/gcc/varasm.c
>> index 3e76032..12f36f3 100644
>> --- a/gcc/varasm.c
>> +++ b/gcc/varasm.c
>> @@ -7509,7 +7509,7 @@ elf_record_gcc_switches (print_switch_type type, const 
>> char * name)
>>  }
>>
>>  /* Emit text to declare externally defined symbols. It is needed to
>> -   properly support non-default visibility.  */
>> +   properly support non-default visibility and specify symbol type.  */
>>  void
>>  default_elf_asm_output_external (FILE *file ATTRIBUTE_UNUSED,
>>  tree decl,
>> @@ -7518,10 +7518,22 @@ default_elf_asm_output_external (FILE *file 
>> ATTRIBUTE_UNUSED,
>>/* We output the name if and only if TREE_SYMBOL_REFERENCED is
>>   set in order to avoid putting out names that are never really
>>   used.  Always output visibility specified in the source.  */
>> -  if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))
>> -  && (DECL_VISIBILITY_SPECIFIED (decl)
>> - || targetm.binds_local_p (decl)))
>> -maybe_assemble_visibility (decl);
>> +  if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
>> +{
>> +  if (DECL_VISIBILITY_SPECIFIED (decl)
>> + || targetm.binds_local_p (de

Re: [PATCH]Fix PR66556. Don't drop side-effect in simplify_const_relational_operation function.

[Jeff Law]

On 07/08/2015 09:03 AM, Renlin Li wrote:

Hi all,

In simplify_const_relational_operation function, there are cases a const
rtx
will be returned.

Three cases are considered in this function:
1, comparisons with upper and lower bounds.
2, Integer comparisons with zero.
3, comparison of ABS with zero.

It's fine to to the optimization if the operands have no side-effects.

For example, I am currently fixing a code generation bug for armv7-a
bigendian.
It turns out that, the following rtx is simplified into a const, and the
side-effect with it is ignored.

(ltu:SI (lshiftrt:SI (subreg:SI (mem/c:HI (post_modify:SI (reg/f:SI 156)
 (plus:SI (reg/f:SI 156)
 (const_int 20 [0x14]))) [5 g+4 S2 A32]) 0)
 (const_int 1 [0x1]))
 (const_int -1 [0x]))

>>

(const_int 1 [0x1])

This particular case falls into category 1 mentioned above. -1, when
regarded
as unsigned integer, is the largest unsigned integer. So the result is
always
a const_true_rtx in this case. However, the first operand of the comparison
has POST_MODIFY side-effect.

In this case, the simplifications should be checked against side-effect.

x86_64 bootstrapping is Okay and arm-none-eabi regression test runs
without any new issues.

Okay to commit and backport to branch 5?

Regards,
Renlin Li

gcc/ChangeLog:

2015-07-08  Renlin Li  

 PR rtl/66556
 * simplify-rtx.c (simplify_const_relational_operation): Add
 side_effects_p check.

gcc/testsuite/ChangeLog:

2015-07-08  Renlin Li  

 PR rtl/66556
 * gcc.c-torture/execute/pr66556.c: New.

OK.

It may be worth looking at the .optimized dump for the new test and see 
if there's something we can/should be optimizing better before we start 
generating RTL.  That can obviously be a follow-up.


jeff

Re: Drop -Wswitch-bool warning in function.c

[Jeff Law]

On 07/08/2015 02:49 AM, Kito Cheng wrote:

Bootstrapped & regression-tested on x86_64-linux-gnu :)

2015-07-08  Kito Cheng  

 * function.c (stack_protect_epilogue): Use if rather than switch for
 check targetm.have_stack_protect_test().

OK.  Not necessarily because avoid the warning is really all that 
important, but because the if-else is just as easy to read as the switch 
and dramatically more compact.


Jeff

[PATCH] PR target/66817: Check int_size_in_bytes in ix86_return_in_memory

[H.J. Lu]

ix86_return_in_memory should check negative return from int_size_in_bytes,
similar to other ports.

Tested on Linux/x86-64. OK for trunk?

Thanks.


H.J.
---
gcc/

PR target/66817
* config/i386/i386.c (ix86_return_in_memory): Return true
if int_size_in_bytes returns negative for IA MCU.

gcc/testsuite/

PR target/66817
* gcc.target/i386/pr66817.c: New test.
---
 gcc/config/i386/i386.c  |  2 +-
 gcc/testsuite/gcc.target/i386/pr66817.c | 27 +++
 2 files changed, 28 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr66817.c

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 55a32ac..54ee6f3 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -8682,7 +8682,7 @@ ix86_return_in_memory (const_tree type, const_tree fntype 
ATTRIBUTE_UNUSED)
   /* Intel MCU psABI returns scalars and aggregates no larger than 8
 bytes in registers.  */
   if (TARGET_IAMCU)
-   return VECTOR_MODE_P (mode) || size > 8;
+   return VECTOR_MODE_P (mode) || size < 0 || size > 8;
 
   if (mode == BLKmode)
return true;
diff --git a/gcc/testsuite/gcc.target/i386/pr66817.c 
b/gcc/testsuite/gcc.target/i386/pr66817.c
new file mode 100644
index 000..7ec18b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr66817.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-O2 -mno-sse -mno-mmx -miamcu" } */
+
+extern void abort (void);
+int
+main (int argc, char **argv)
+{
+  int size = 10;
+  typedef struct
+{
+  char val[size];
+}
+  block;
+  block a, b;
+  block __attribute__((noinline))
+  retframe_block ()
+{
+  return *(block *) &b;
+}
+  b.val[0] = 1;
+  b.val[9] = 2;
+  a=retframe_block ();
+  if (a.val[0] != 1
+  || a.val[9] != 2)
+abort ();
+  return 0;
+}
-- 
2.4.3

Re: [gomp] Move openacc vector& worker single handling to RTL

[Nathan Sidwell]

On 07/08/15 10:58, Jakub Jelinek wrote:

On Wed, Jul 08, 2015 at 10:47:56AM -0400, Nathan Sidwell wrote:

+/* Generate loop head markers in outer->inner order.  */
+
+static void
+gen_oacc_fork (gimple_seq *seq, unsigned mask)
+{
+  {
+// TODDO: Determine this information from the parallel region itself


TODO ?


I want to clean this up with the offloading launch API.  As it happens, I did 
manage to have the PTX  backend DTRT if it doesn't encounter this internal fn. 
I'm dropping it fromm this patch (it'd undoubtedly need moving around anyway).



+   gcall *call = gimple_build_call_internal
+ (IFN_GOACC_FORK, 1, arg);


Why the line-break?  That should fit into 80 columns just fine.


oh, it does now I've changed the name of the internal function.


+ It'd be better to place the OACC_LOOP markers just inside the outer
+ conditional, so they can be entirely eliminated if the loop is
+ unreachable.


Putting OACC_FORK/OACC_JOIN unconditionally into the comment is very
confusing.  The expand_omp_for_static_nochunk routine is used for
#pragma omp for schedule(static), #pragma omp distribute etc. which
certainly don't want to emit such markers in there.  So perhaps mention
somewhere that you wrap all the above sequence in between
OACC_FORK/OACC_JOIN markers.


Done. (at both sites)


Please avoid such whitespace changes.


Fixed (& searched others).


In any case, as it is a gomp-4_0-branch patch, I'll defer full review to the
branch maintainers.


Thanks for your review!

nathan
2015-07-08  Nathan Sidwell  

Infrastructure:
* gimple.h (gimple_call_internal_unique_p): Declare.
* gimple.c (gimple_call_same_target_p): Add check for
gimple_call_internal_unique_p.
* internal-fn.c (gimple_call_internal_unique_p): New.
* omp-low.h (OACC_LOOP_MASK): Define here...
* omp-low.c (OACC_LOOP_MASK): ... not here.
* tree-ssa-threadedge.c (record_temporary_equivalences_from_stmts):
Add check for gimple_call_internal_unique_p.
* tree-ssa-tail-merge.c (same_succ_def::equal): Add EQ check for
the gimple statements.

Additions:
* internal-fn.def (GOACC_FORK, GOACC_JOIN): New.
* internal-fn.c (gimple_call_internal_unique_p): Add check for
IFN_GOACC_FORK, IFN_GOACC_JOIN.
(expand_GOACC_FORK, expand_GOACC_JOIN): New.
* omp-low.c (gen_oacc_fork, gen_oacc_join): New.
(expand_omp_for_static_nochunk): Add oacc loop fork & join calls.
(expand_omp_for_static_chunk): Likewise.
* config/nvptx/nvptx-protos.h (nvptx_expand_oacc_fork,
nvptx_expand_oacc_join): Declare.
* config/nvptx/nvptx.md (UNSPEC_BIT_CONV, UNSPEC_BROADCAST,
UNSPEC_BR_UNIFIED): New unspecs.
(UNSPECV_FORK, UNSPECV_FORKED, UNSPECV_JOINING, UNSPECV_JOIN,
UNSPECV_BR_HIDDEN): New.
(BITS, BITD): New mode iterators.
(br_true_hidden, br_false_hidden, br_uni_true, br_uni_false): New
branches.
(nvptx_fork, nvptx_forked, nvptx_joining, nvptx_join): New insns.
(oacc_fork, oacc_join): New expand
(nvptx_broadcast): New insn.
(unpacksi2, packsi2): New insns.
(worker_load, worker_store): New insns.
(nvptx_barsync): Renamed from ...
(threadbarrier_insn): ... here.
* config/nvptx/nvptx.c: Include hash-map,h, dominance.h, cfg.h &
omp-low.h.
(worker_bcast_hwm, worker_bcast_align, worker_bcast_name,
worker_bcast_sym): New.
(nvptx_option_override): Initialize worker_bcast_sym.
(nvptx_expand_oacc_fork, nvptx_expand_oacc_join): New.
(nvptx_gen_unpack, nvptx_gen_pack): New.
(struct wcast_data_t, propagate_mask): New types.
(nvptx_gen_vcast, nvptx_gen_wcast): New.
(nvptx_print_operand):  Change 'U' specifier to look at operand
itself.
(struct parallel): New structs.
(parallel::parallel, parallel::~parallel): Ctor & dtor.
(bb_insn_map_t): New map.
(insn_bb_t, insn_bb_vec_t): New tuple & vector of.
(nvptx_split_blocks, nvptx_discover_pre): New.
(bb_par_t, bb_par_vec_t); New tuple & vector of.
(nvptx_dump_pars,nvptx_discover_pars): New.
(nvptx_propagate, vprop_gen, nvptx_vpropagate, wprop_gen,
nvptx_wpropagate): New.
(nvptx_wsync): New.
(nvptx_single, nvptx_skip_par): New.
(nvptx_process_pars): New.
(nvptx_neuter_pars): New.
(nvptx_reorg): Add liveness DF problem.  Call nvptx_split_blocks,
nvptx_discover_pars, nvptx_process_pars & nvptx_neuter_pars.
(nvptx_cannot_copy_insn): Check for broadcast, sync, fork & join insns.
(nvptx_file_end): Output worker broadcast array definition.

Deletions:
* builtins.c (expand_oacc_thread_barrier): Delete.
(expand_oacc_thread_broadcast): Delete.
(expand_builtin): Adjust.
* gimple.c (struct gimple_statement_omp_paral

Adjust -fdump-ada-spec to C++14 switch (2)

[Eric Botcazou]

We need to skip the constexpr default constructors.

Tested on x86_64-suse-linux, applied on the mainline as obvious.


2015-07-08  Eric Botcazou  

c-family/
* c-ada-spec.h (cpp_operation): Add IS_CONSTEXPR.
* c-ada-spec.c (print_ada_declaration): Skip constexpr constructors.
cp/
* decl2.c (cpp_check): Deal with IS_CONSTEXPR.


2015-07-08  Eric Botcazou  

* g++.dg/other/dump-ada-spec-9.C: New test.

-- 
Eric BotcazouIndex: c-family/c-ada-spec.h
===
--- c-family/c-ada-spec.h	(revision 225533)
+++ c-family/c-ada-spec.h	(working copy)
@@ -27,6 +27,7 @@ along with GCC; see the file COPYING3.
 typedef enum {
   HAS_DEPENDENT_TEMPLATE_ARGS,
   IS_ABSTRACT,
+  IS_CONSTEXPR,
   IS_CONSTRUCTOR,
   IS_DESTRUCTOR,
   IS_COPY_CONSTRUCTOR,
Index: c-family/c-ada-spec.c
===
--- c-family/c-ada-spec.c	(revision 225533)
+++ c-family/c-ada-spec.c	(working copy)
@@ -2887,6 +2887,7 @@ print_ada_declaration (pretty_printer *b
   bool is_method = TREE_CODE (TREE_TYPE (t)) == METHOD_TYPE;
   tree decl_name = DECL_NAME (t);
   bool is_abstract = false;
+  bool is_constexpr = false;
   bool is_constructor = false;
   bool is_destructor = false;
   bool is_copy_constructor = false;
@@ -2898,6 +2899,7 @@ print_ada_declaration (pretty_printer *b
   if (cpp_check)
 	{
 	  is_abstract = cpp_check (t, IS_ABSTRACT);
+	  is_constexpr = cpp_check (t, IS_CONSTEXPR);
 	  is_constructor = cpp_check (t, IS_CONSTRUCTOR);
 	  is_destructor = cpp_check (t, IS_DESTRUCTOR);
 	  is_copy_constructor = cpp_check (t, IS_COPY_CONSTRUCTOR);
@@ -2911,6 +2913,10 @@ print_ada_declaration (pretty_printer *b
 
   if (is_constructor || is_destructor)
 	{
+	  /* Skip constexpr default constructors.  */
+	  if (is_constexpr)
+	return 0;
+
 	  /* Only consider constructors/destructors for complete objects.  */
 	  if (strncmp (IDENTIFIER_POINTER (decl_name), "__comp", 6) != 0)
 	return 0;
Index: cp/decl2.c
===
--- cp/decl2.c	(revision 225533)
+++ cp/decl2.c	(working copy)
@@ -4070,6 +4070,8 @@ cpp_check (tree t, cpp_operation op)
 	}
   case IS_ABSTRACT:
 	return DECL_PURE_VIRTUAL_P (t);
+  case IS_CONSTEXPR:
+	return DECL_DECLARED_CONSTEXPR_P (t);
   case IS_CONSTRUCTOR:
 	return DECL_CONSTRUCTOR_P (t);
   case IS_DESTRUCTOR:
/* { dg-do compile } */
/* { dg-options "-fdump-ada-spec" } */

class Base {
  public:
 virtual void Primitive ();

};

void Base::Primitive () {

}

void Dispatch (Base * B) {
  B->Primitive ();
}

/* { dg-final { scan-ada-spec-not "CPP_Constructor" } } */
/* { dg-final { cleanup-ada-spec } } */

Re: RFC: Add ADDR_EXPR lowering (PR tree-optimization/66718)

[Marek Polacek]

On Wed, Jul 08, 2015 at 07:37:41PM +0200, Marek Polacek wrote:
>  DEFTIMEVAR (TV_INITIALIZE_RTL, "initialize rtl")
> +DEFTIMEVAR (TV_GIMPLE_LADDRESS , "address lowering")

Consider this whitespace issue fixed.

Marek

[PATCH] Fix pr 66796, testsuite failure on hppa-linux

[Jeff Law]

As detailed in the PR notes, this test behaves differently on linux vs 
hpux targets due to differences in how they handle the space/segment 
registers.


By changing the test slightly we can remove that difference in behaviour 
across the platforms without compromising the test.


Installed on the trunk after verifying hppa.exp passes with crosses to 
hpux and linux.


Jeff

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d2d51ae..37f3724 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2015-07-08  Jeff Law  
+
+   PR testsuite/66796
+   * gcc.target/hppa/shadd-1.c: Avoid the read-modify-write so as
+   to have a single memory reference.
+
 2015-07-08  Eric Botcazou  
 
* g++.dg/other/dump-ada-spec-9.C: New test.
diff --git a/gcc/testsuite/gcc.target/hppa/shadd-1.c 
b/gcc/testsuite/gcc.target/hppa/shadd-1.c
index de4776b..55115b4 100644
--- a/gcc/testsuite/gcc.target/hppa/shadd-1.c
+++ b/gcc/testsuite/gcc.target/hppa/shadd-1.c
@@ -12,5 +12,5 @@ __sigaddset (__sigset_t * __set, int __sig, int __stuff)
 {
   unsigned long int __word =
 (((__sig) - 1) / (8 * sizeof (unsigned long int)));
-  return __set->__val[__word] |= __stuff;
+  return __set->__val[__word] = __stuff;
 }

Re: [patch 0/9] Flattening and initial module rebuilding

[Jeff Law]

On 07/07/2015 05:53 PM, Andrew MacLeod wrote:

yes, with a bit of tweaking and enhancement they can be generally
useful.  They are all in python.  And no one is allowed to make comments
like "OMG thats so inefficient" or "what a horrible way to do that"
:-)   My goal was getting things done and sometimes the brute force
approach works great when the machine sare fast enough :_)
Works for me...  I'm sure Martin S. is cringing at my python scripts 
right now, so I completely understand.



It's a bit of a shame that function.h is in backend.h, along with
predict (which is presumably needed by basic-block/cfg?).



Yeah,once things settle down someone could tweak things more. If I make
the tools available, people can do their own analysis and adjusting.

function.h provides cfun which is used all over the place..9 backend
header files use it,and a few like gimple.h actually require struct
function to be defined.
Right.  I suspect that we may want to look at cleaning that up a bit in 
the future.  There's bits in there that are relatively backend specific, 
some bits that look like front-end things, and cfun which is a context 
container.  Untangling that mess is likely to be painful.







predict.h is actually required by gimple.h for a few reasons, enum
be_predictor is used in parameter lists and a few inlines use the TAKEN,
NOT_TAKEN macros
Its also needed by cfghooks.h, and betwen those 2 files, its just needed
by  a very good chunk of the backend. .. 219 of the 263 files which
include backend.h need it.
We could move the 2 enums and TAKEN/NOT_TAKEN to coretypes or something
like that and it would probably cut the requirements for it by a *lot*.

Might be something for a follow-up (moving the enums).

Jeff

[PATCH] PR target/66818: Define ATTRIBUTE_ALIGNED_VALUE to 32 for IA MCU

[H.J. Lu]

attribute ((aligned)) should align to the minimum of BIGGEST_ALIGNMENT,
which is 4 bytes for -miamcu.

Tested on Linux/x86-64.  OK for trunk?

Thanks.

H.J.
---
gcc/

PR target/66818
* config/i386/i386.h (ATTRIBUTE_ALIGNED_VALUE): Defined to 32
for IA MCU.

gcc/testsuite/

PR target/66818
* gcc.target/i386/pr66818.c: New test.
---
 gcc/config/i386/i386.h  | 2 +-
 gcc/testsuite/gcc.target/i386/pr66818.c | 5 +
 2 files changed, 6 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr66818.c

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index f357e79..74334ff 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -811,7 +811,7 @@ extern const char *host_detect_local_cpu (int argc, const 
char **argv);
 
 /* Alignment value for attribute ((aligned)).  It is a constant since
it is the part of the ABI.  We shouldn't change it with -mavx.  */
-#define ATTRIBUTE_ALIGNED_VALUE 128
+#define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128)
 
 /* Decide whether a variable of mode MODE should be 128 bit aligned.  */
 #define ALIGN_MODE_128(MODE) \
diff --git a/gcc/testsuite/gcc.target/i386/pr66818.c 
b/gcc/testsuite/gcc.target/i386/pr66818.c
new file mode 100644
index 000..d90394c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr66818.c
@@ -0,0 +1,5 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-O2 -mno-sse -mno-mmx -miamcu" } */
+
+struct dummy { int x __attribute__((aligned)); };
+int array[__alignof__(struct dummy) == 4 ? 1 : -1];
-- 
2.4.3