Re: [PATCH] i386: simplify cpu_feature handling
On 12/16/21 21:58, Stefan Kneifel wrote: Am 15.12.21 um 10:57 schrieb Martin Liška: On 12/14/21 17:12, Jakub Jelinek wrote: I'd use INT_TYPE_SIZE - 1 instead of 31. Otherwise LGTM. Installed with that change, thanks. Moreover, I'm suggesting a simplification: The patch removes unneeded loops for cpu_features2 and CONVERT_EXPR that can be simplified with NOP_EXPR. Survives i386.exp tests, may I install the patch after testing or is it a stage1 material? Thanks, Martin The loops indeed seem to be unnecessary. For safety reasons: what would you think about throwing an ICE if (index >= SIZE_OF_CPU_FEATURES) ? This should not happen - however, a lot of things shouldn't happen... and it might facilitiate locating a potential bug at a later time. Hello. Well, I see your point, but I don't think it's necessary as the macro is well defined. Note we have a ASAN and UBSAN bootstrap that would caught such an error. Cheers, Martin Regards, Stefan
[pushed] Darwin, ppc: Additional change for r12-5974.
This adds a missed change from r12-5974-g926d64906af.
The builin_decls array has been renamed to drop the trailing
_x that was used during the main changes to the builtins.
This fixes bootstrap for powerpc-darwin9, tested there, pushed
to master, thanks,
Iain
Signed-off-by: Iain Sandoe
gcc/ChangeLog:
* config/rs6000/darwin.h: Drop trailing _x from the
builtin_decls array name.
---
gcc/config/rs6000/darwin.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index 7bc1009a523..8288003038e 100644
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -507,7 +507,7 @@
#define SUBTARGET_INIT_BUILTINS
\
do { \
darwin_patch_builtins ();\
- rs6000_builtin_decls_x[(unsigned) (RS6000_BIF_CFSTRING)] \
+ rs6000_builtin_decls[(unsigned) (RS6000_BIF_CFSTRING)] \
= darwin_init_cfstring_builtins ((unsigned) (RS6000_BIF_CFSTRING)); \
} while(0)
--
2.24.3 (Apple Git-128)
[pushed] Darwin, Driver: Avoid a link line for empty commands.
We were pushing a spec value for weak_reference_mismatches unconditionally
which is not needed (the value was the default) and the side-effect of
this was that we appeared to need to drive a link command; leading to
unexpected diagnostics for cases where gcc was invoked with an empty
command line.
Also we were pushing flags for sysroot, os minimum version and controls
even if the command line was empty.
tested on x86_64, i686 and powerpc-darwin, pushed to master, thanks
Iain
Signed-off-by: Iain Sandoe
gcc/ChangeLog:
* config/darwin-driver.c (darwin_driver_init): Exit from the
option handling early if the command line is definitely enpty.
* config/darwin.h (SUBTARGET_DRIVER_SELF_SPECS): Remove
setting for the default content of weak_reference_mismatches.
---
gcc/config/darwin-driver.c | 8 ++--
gcc/config/darwin.h| 5 -
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/gcc/config/darwin-driver.c b/gcc/config/darwin-driver.c
index 7fa80abc314..688fe8fabc0 100644
--- a/gcc/config/darwin-driver.c
+++ b/gcc/config/darwin-driver.c
@@ -416,6 +416,10 @@ darwin_driver_init (unsigned int *decoded_options_count,
}
#endif
+ /* If there is nothing else on the command line, do not add sysroot etc. */
+ if (*decoded_options_count <= 1)
+return;
+
if (appendM32 || appendM64)
{
++*decoded_options_count;
@@ -426,7 +430,7 @@ darwin_driver_init (unsigned int *decoded_options_count,
&(*decoded_options)[*decoded_options_count - 1]);
}
- if (! seen_sysroot_p)
+ if (!seen_sysroot_p)
{
/* We will pick up an SDKROOT if we didn't specify a sysroot and treat
it as overriding any configure-time --with-sysroot. */
@@ -445,7 +449,7 @@ darwin_driver_init (unsigned int *decoded_options_count,
/* We will need to know the OS X version we're trying to build for here
so that we can figure out the mechanism and source for the sysroot to
be used. */
- if (! seen_version_min && *decoded_options_count > 1)
+ if (!seen_version_min)
/* Not set by the User, try to figure it out. */
vers_string = darwin_default_min_version ();
diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h
index 0ce13207ad6..75b688ebf9e 100644
--- a/gcc/config/darwin.h
+++ b/gcc/config/darwin.h
@@ -268,11 +268,6 @@ extern GTY(()) int darwin_ms_struct;
"%{unexported_symbols_list*:\
-Xlinker -unexported_symbols_list -Xlinker %*} \
%
Re: [gcc r12-6020] Fixed typo
On 12/16/21 19:43, Joseph Myers wrote: On Thu, 16 Dec 2021, Martin Liška wrote: Hello. Oh, sorry, it was me and I forgot to send the patch to the mailing list. I've basically taken it as: https://github.com/gcc-mirror/gcc/pull/57. Should I revert the change? Updating both config.sub and config.guess to the latest config.git versions (2021-10-27 and 2021-11-30) is probably the right thing to do now. All right, I've reverted the original patch and I'm going to do sync from upstream. Installed. Martin From 8e8abbe7f2107a16abd034813e3fb4956b6afe32 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Fri, 17 Dec 2021 09:56:21 +0100 Subject: [PATCH] Sync config.sub: 2021-10-27 ChangeLog: * config.sub: Sync from master. --- config.sub | 81 +++--- 1 file changed, 53 insertions(+), 28 deletions(-) mode change 100755 => 100644 config.sub diff --git a/config.sub b/config.sub old mode 100755 new mode 100644 index 63c1f1c8b5e..38f3d037a78 --- a/config.sub +++ b/config.sub @@ -2,7 +2,9 @@ # Configuration validation subroutine script. # Copyright 1992-2021 Free Software Foundation, Inc. -timestamp='2021-01-08' +# shellcheck disable=SC2006,SC2268 # see below for rationale + +timestamp='2021-10-27' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by @@ -50,7 +52,14 @@ timestamp='2021-01-08' # CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM # It is wrong to echo any other type of specification. -me=$(echo "$0" | sed -e 's,.*/,,') +# The "shellcheck disable" line above the timestamp inhibits complaints +# about features and limitations of the classic Bourne shell that were +# superseded or lifted in POSIX. However, this script identifies a wide +# variety of pre-POSIX systems that do not have POSIX shells at all, and +# even some reasonably current systems (Solaris 10 as case-in-point) still +# have a pre-POSIX /bin/sh. + +me=`echo "$0" | sed -e 's,.*/,,'` usage="\ Usage: $0 [OPTION] CPU-MFR-OPSYS or ALIAS @@ -112,9 +121,11 @@ esac # Split fields of configuration type # shellcheck disable=SC2162 +saved_IFS=$IFS IFS="-" read field1 field2 field3 field4 <&2 -- 2.34.1
[1/2] PR96463 - aarch64 specific changes
Hi,
The patch folds:
lhs = svld1rq ({-1, -1, -1, ...}, &v[0])
into:
lhs = vec_perm_expr
and expands above vec_perm_expr using aarch64_expand_sve_dupq.
With patch, for following test:
#include
#include
svint32_t
foo (int32x4_t x)
{
return svld1rq (svptrue_b8 (), &x[0]);
}
it generates following code:
foo:
.LFB4350:
dup z0.q, z0.q[0]
ret
and passes bootstrap+test on aarch64-linux-gnu.
But I am not sure if the changes to aarch64_evpc_sve_tbl
are correct.
Thanks,
Prathamesh
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index 02e42a71e5e..e21bbec360c 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -1207,6 +1207,56 @@ public:
insn_code icode = code_for_aarch64_sve_ld1rq (e.vector_mode (0));
return e.use_contiguous_load_insn (icode);
}
+
+ gimple *
+ fold (gimple_folder &f) const OVERRIDE
+ {
+tree arg0 = gimple_call_arg (f.call, 0);
+tree arg1 = gimple_call_arg (f.call, 1);
+
+/* Transform:
+ lhs = svld1rq ({-1, -1, ... }, &v[0])
+ into:
+ lhs = vec_perm_expr.
+ on little endian target. */
+
+if (!BYTES_BIG_ENDIAN
+ && integer_all_onesp (arg0)
+ && TREE_CODE (arg1) == ADDR_EXPR)
+ {
+ tree t = TREE_OPERAND (arg1, 0);
+ if (TREE_CODE (t) == ARRAY_REF)
+ {
+ tree index = TREE_OPERAND (t, 1);
+ t = TREE_OPERAND (t, 0);
+ if (integer_zerop (index) && TREE_CODE (t) == VIEW_CONVERT_EXPR)
+ {
+ t = TREE_OPERAND (t, 0);
+ tree vectype = TREE_TYPE (t);
+ if (VECTOR_TYPE_P (vectype)
+ && known_eq (TYPE_VECTOR_SUBPARTS (vectype), 4u)
+ && wi::to_wide (TYPE_SIZE (vectype)) == 128)
+ {
+ tree lhs = gimple_call_lhs (f.call);
+ tree lhs_type = TREE_TYPE (lhs);
+ int source_nelts = TYPE_VECTOR_SUBPARTS
(vectype).to_constant ();
+ vec_perm_builder sel (TYPE_VECTOR_SUBPARTS (lhs_type),
source_nelts, 1);
+ for (int i = 0; i < source_nelts; i++)
+ sel.quick_push (i);
+
+ vec_perm_indices indices (sel, 1, source_nelts);
+ if (!can_vec_perm_const_p (TYPE_MODE (lhs_type), indices))
+ return NULL;
+
+ tree mask = vec_perm_indices_to_tree (lhs_type, indices);
+ return gimple_build_assign (lhs, VEC_PERM_EXPR, t, t, mask);
+ }
+ }
+ }
+ }
+
+return NULL;
+ }
};
class svld1ro_impl : public load_replicate
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index f07330cff4f..af27f550be3 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -23002,8 +23002,32 @@ aarch64_evpc_sve_tbl (struct expand_vec_perm_d *d)
machine_mode sel_mode = related_int_vector_mode (d->vmode).require ();
rtx sel = vec_perm_indices_to_rtx (sel_mode, d->perm);
+
if (d->one_vector_p)
-emit_unspec2 (d->target, UNSPEC_TBL, d->op0, force_reg (sel_mode, sel));
+{
+ bool use_dupq = false;
+ /* Check if sel is dup vector with encoded elements {0, 1, 2, ... nelts}
*/
+ if (GET_CODE (sel) == CONST_VECTOR
+ && !GET_MODE_NUNITS (GET_MODE (sel)).is_constant ()
+ && CONST_VECTOR_DUPLICATE_P (sel))
+ {
+ unsigned nelts = const_vector_encoded_nelts (sel);
+ unsigned i;
+ for (i = 0; i < nelts; i++)
+ {
+ rtx elem = CONST_VECTOR_ENCODED_ELT(sel, i);
+ if (!(CONST_INT_P (elem) && INTVAL(elem) == i))
+ break;
+ }
+ if (i == nelts)
+ use_dupq = true;
+ }
+
+ if (use_dupq)
+ aarch64_expand_sve_dupq (d->target, GET_MODE (d->target), d->op0);
+ else
+ emit_unspec2 (d->target, UNSPEC_TBL, d->op0, force_reg (sel_mode, sel));
+}
else
aarch64_expand_sve_vec_perm (d->target, d->op0, d->op1, sel);
return true;
[PATCH]middle-end slp: check that the operation we're combing is a boolean operation [PR103741]
Hi All,
It seems I forgot to check that the operation we're combing when masking the
predicated together are actually predicates types.
Without it we end up accidentally trying to combine a value and a mask.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
PR tree-optimization/103741
* tree-vect-stmts.c (vectorizable_operation): Check for boolean.
gcc/testsuite/ChangeLog:
PR tree-optimization/103741
* gcc.target/aarch64/pr103741.c: New test.
--- inline copy of patch --
diff --git a/gcc/testsuite/gcc.target/aarch64/pr103741.c
b/gcc/testsuite/gcc.target/aarch64/pr103741.c
new file mode 100644
index
..ef3ae66ebe5e5a44e7bea7be22b6378bc23cc538
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr103741.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+sve -O1" } */
+
+long int m, n;
+
+int
+qux (int z)
+{
+ return 4 >> z ? z : 0;
+}
+
+int
+bar (long int y)
+{
+ return y ? 3 : 2;
+}
+
+__attribute__ ((simd)) int
+foo (int x)
+{
+ long int a = x & m;
+ int b = bar (x) / n;
+
+ return qux (b) == a;
+}
+
diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c
index
8c427174b37e6c03c2f914c90332bcc4eac54130..ad90cdb0473a337207d6ba54c1dd0a2ecc50ab8d
100644
--- a/gcc/tree-vect-stmts.c
+++ b/gcc/tree-vect-stmts.c
@@ -6361,7 +6361,9 @@ vectorizable_operation (vec_info *vinfo,
/* When combining two masks check if either of them is elsewhere
combined with a loop mask, if that's the case we can mark that the
new combined mask doesn't need to be combined with a loop mask. */
- if (masked_loop_p && code == BIT_AND_EXPR)
+ if (masked_loop_p
+ && code == BIT_AND_EXPR
+ && VECTOR_BOOLEAN_TYPE_P (vectype))
{
if (loop_vinfo->scalar_cond_masked_set.contains ({ op0,
ncopies}))
--
diff --git a/gcc/testsuite/gcc.target/aarch64/pr103741.c b/gcc/testsuite/gcc.target/aarch64/pr103741.c
new file mode 100644
index ..ef3ae66ebe5e5a44e7bea7be22b6378bc23cc538
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr103741.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8-a+sve -O1" } */
+
+long int m, n;
+
+int
+qux (int z)
+{
+ return 4 >> z ? z : 0;
+}
+
+int
+bar (long int y)
+{
+ return y ? 3 : 2;
+}
+
+__attribute__ ((simd)) int
+foo (int x)
+{
+ long int a = x & m;
+ int b = bar (x) / n;
+
+ return qux (b) == a;
+}
+
diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c
index 8c427174b37e6c03c2f914c90332bcc4eac54130..ad90cdb0473a337207d6ba54c1dd0a2ecc50ab8d 100644
--- a/gcc/tree-vect-stmts.c
+++ b/gcc/tree-vect-stmts.c
@@ -6361,7 +6361,9 @@ vectorizable_operation (vec_info *vinfo,
/* When combining two masks check if either of them is elsewhere
combined with a loop mask, if that's the case we can mark that the
new combined mask doesn't need to be combined with a loop mask. */
- if (masked_loop_p && code == BIT_AND_EXPR)
+ if (masked_loop_p
+ && code == BIT_AND_EXPR
+ && VECTOR_BOOLEAN_TYPE_P (vectype))
{
if (loop_vinfo->scalar_cond_masked_set.contains ({ op0,
ncopies}))
[2/2] PR96463 -- changes to type checking vec_perm_expr in middle end
Hi,
The attached patch rearranges order of type-check for vec_perm_expr
and relaxes type checking for
lhs = vec_perm_expr
when:
rhs1 == rhs2,
lhs is variable length vector,
rhs1 is fixed length vector,
TREE_TYPE (lhs) == TREE_TYPE (rhs1)
I am not sure tho if this check is correct ? My intent was to capture
case when vec_perm_expr is used to "extend" fixed length vector to
it's VLA equivalent.
Thanks,
Prathamesh
diff --git a/gcc/tree-cfg.c b/gcc/tree-cfg.c
index 672e384ef09..9f91878c468 100644
--- a/gcc/tree-cfg.c
+++ b/gcc/tree-cfg.c
@@ -4325,10 +4325,11 @@ verify_gimple_assign_ternary (gassign *stmt)
break;
case VEC_PERM_EXPR:
- if (!useless_type_conversion_p (lhs_type, rhs1_type)
- || !useless_type_conversion_p (lhs_type, rhs2_type))
+ if (TREE_CODE (rhs1_type) != VECTOR_TYPE
+ || TREE_CODE (rhs2_type) != VECTOR_TYPE
+ || TREE_CODE (rhs3_type) != VECTOR_TYPE)
{
- error ("type mismatch in %qs", code_name);
+ error ("vector types expected in %qs", code_name);
debug_generic_expr (lhs_type);
debug_generic_expr (rhs1_type);
debug_generic_expr (rhs2_type);
@@ -4336,11 +4337,14 @@ verify_gimple_assign_ternary (gassign *stmt)
return true;
}
- if (TREE_CODE (rhs1_type) != VECTOR_TYPE
- || TREE_CODE (rhs2_type) != VECTOR_TYPE
- || TREE_CODE (rhs3_type) != VECTOR_TYPE)
+ if (TREE_CODE (TREE_TYPE (rhs3_type)) != INTEGER_TYPE
+ || (TREE_CODE (rhs3) != VECTOR_CST
+ && (GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE
+ (TREE_TYPE (rhs3_type)))
+ != GET_MODE_BITSIZE (SCALAR_TYPE_MODE
+ (TREE_TYPE (rhs1_type))
{
- error ("vector types expected in %qs", code_name);
+ error ("invalid mask type in %qs", code_name);
debug_generic_expr (lhs_type);
debug_generic_expr (rhs1_type);
debug_generic_expr (rhs2_type);
@@ -4348,15 +4352,18 @@ verify_gimple_assign_ternary (gassign *stmt)
return true;
}
- if (maybe_ne (TYPE_VECTOR_SUBPARTS (rhs1_type),
- TYPE_VECTOR_SUBPARTS (rhs2_type))
- || maybe_ne (TYPE_VECTOR_SUBPARTS (rhs2_type),
- TYPE_VECTOR_SUBPARTS (rhs3_type))
- || maybe_ne (TYPE_VECTOR_SUBPARTS (rhs3_type),
- TYPE_VECTOR_SUBPARTS (lhs_type)))
+ /* Accept lhs = vec_perm_expr if lhs is vector length
agnostic,
+and has same element type as v. */
+ if (!TYPE_VECTOR_SUBPARTS (lhs_type).is_constant ()
+ && operand_equal_p (rhs1, rhs2, 0)
+ && TYPE_VECTOR_SUBPARTS (rhs1_type).is_constant ()
+ && TREE_TYPE (lhs_type) == TREE_TYPE (rhs1_type))
+ return false;
+
+ if (!useless_type_conversion_p (lhs_type, rhs1_type)
+ || !useless_type_conversion_p (lhs_type, rhs2_type))
{
- error ("vectors with different element number found in %qs",
-code_name);
+ error ("type mismatch in %qs", code_name);
debug_generic_expr (lhs_type);
debug_generic_expr (rhs1_type);
debug_generic_expr (rhs2_type);
@@ -4364,21 +4371,21 @@ verify_gimple_assign_ternary (gassign *stmt)
return true;
}
- if (TREE_CODE (TREE_TYPE (rhs3_type)) != INTEGER_TYPE
- || (TREE_CODE (rhs3) != VECTOR_CST
- && (GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE
- (TREE_TYPE (rhs3_type)))
- != GET_MODE_BITSIZE (SCALAR_TYPE_MODE
- (TREE_TYPE (rhs1_type))
+ if (maybe_ne (TYPE_VECTOR_SUBPARTS (rhs1_type),
+ TYPE_VECTOR_SUBPARTS (rhs2_type))
+ || maybe_ne (TYPE_VECTOR_SUBPARTS (rhs2_type),
+ TYPE_VECTOR_SUBPARTS (rhs3_type))
+ || maybe_ne (TYPE_VECTOR_SUBPARTS (rhs3_type),
+ TYPE_VECTOR_SUBPARTS (lhs_type)))
{
- error ("invalid mask type in %qs", code_name);
+ error ("vectors with different element number found in %qs",
+code_name);
debug_generic_expr (lhs_type);
debug_generic_expr (rhs1_type);
debug_generic_expr (rhs2_type);
debug_generic_expr (rhs3_type);
return true;
}
-
return false;
case SAD_EXPR:
[pushed] libgcc, Darwin: Add missing build dependencies.
There was a race condition where the link for the new shared EH library
(only used on earlier Darwin) could fail because the new crts had not been
copied to the gcc directory. This can cause a build failure (although
currently only seen on powerpc-darwin).
Fixed by adding specific dependency on the crts and on the multi target.
We also add the declaration header for the Darwin10 unwinder shim to the
powerpc cases, since we build that there for Rosetta use.
tested on i686, x86_64 and on several cycles of powerpc-darwin, pushed
to master, thanks,
Iain
Signed-off-by: Iain Sandoe
libgcc/ChangeLog:
* config.host: Add shim declaration header to powerpc*-darwin builds.
* config/rs6000/t-darwin-ehs: Remove dependency on the powerpc end
file.
* config/t-darwin-ehs: Add dependencies to the shared unwinder
objects.
* config/t-slibgcc-darwin: Add extra_parts to the dependencies for
the shared EH lib. Add all-multi to the dependencies for the
libgcc_s.1.dylib redirections.
---
libgcc/config.host| 4
libgcc/config/rs6000/t-darwin-ehs | 4 +---
libgcc/config/t-darwin-ehs| 3 +++
libgcc/config/t-slibgcc-darwin| 8
4 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/libgcc/config.host b/libgcc/config.host
index 1bac57c82ae..ad0cdb284c7 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1140,10 +1140,14 @@ powerpc-*-darwin*)
md_unwind_header=rs6000/darwin-unwind.h
;;
esac
+ # We build the darwin10 EH shim for Rosetta (running on x86 machines).
+ tm_file="$tm_file i386/darwin-lib.h"
tmake_file="$tmake_file rs6000/t-ppc64-fp rs6000/t-ibm-ldouble"
extra_parts="$extra_parts crt2.o crt3_2.o libef_ppc.a dw_ppc.o"
;;
powerpc64-*-darwin*)
+ # We build the darwin10 EH shim for Rosetta (running on x86 machines).
+ tm_file="$tm_file i386/darwin-lib.h"
tmake_file="$tmake_file rs6000/t-darwin64 rs6000/t-ibm-ldouble"
extra_parts="$extra_parts crt2.o crt3_2.o libef_ppc.a dw_ppc.o"
;;
diff --git a/libgcc/config/rs6000/t-darwin-ehs
b/libgcc/config/rs6000/t-darwin-ehs
index 3047f53cb70..42f521411af 100644
--- a/libgcc/config/rs6000/t-darwin-ehs
+++ b/libgcc/config/rs6000/t-darwin-ehs
@@ -1,5 +1,3 @@
# We need the save_world code for the EH library.
-LIBEHSOBJS += darwin-world_s.o
-
-$(LIBEHSOBJS): libef_ppc.a
+LIBEHSOBJS += darwin-world_s.o
diff --git a/libgcc/config/t-darwin-ehs b/libgcc/config/t-darwin-ehs
index 8481898d98a..95275023dac 100644
--- a/libgcc/config/t-darwin-ehs
+++ b/libgcc/config/t-darwin-ehs
@@ -2,3 +2,6 @@
# libgcc_s.1 on systems that used the unwinder in libgcc_s.
LIBEHSOBJS = unwind-dw2_s.o unwind-dw2-fde-darwin_s.o unwind-c_s.o
+
+unwind-dw2_s.o: gthr-default.h md-unwind-support.h
+$(LIBEHSOBJS): libgcc_tm.h
diff --git a/libgcc/config/t-slibgcc-darwin b/libgcc/config/t-slibgcc-darwin
index 7349b87468a..a8f69666a82 100644
--- a/libgcc/config/t-slibgcc-darwin
+++ b/libgcc/config/t-slibgcc-darwin
@@ -59,9 +59,8 @@ ifneq ($(LIBEHSOBJS),)
EHS_INSTNAME = libgcc_ehs.$(SHLIB_SOVERSION)$(SHLIB_EXT)
# multilib build for a shared EH lib.
-$(LIBEHSOBJS): libgcc_tm.h
-libgcc_ehs$(SHLIB_EXT): $(LIBEHSOBJS)
+libgcc_ehs$(SHLIB_EXT): $(LIBEHSOBJS) $(extra-parts)
mkdir -p $(MULTIDIR)
$(CC) $(LIBGCC2_CFLAGS) $(LDFLAGS) -dynamiclib -nodefaultlibs \
-install_name $(SHLIB_INSTALL_DIR)/$(EHS_INSTNAME) \
@@ -113,7 +112,8 @@ libgcc_ehs.$(SHLIB_SOVERSION)$(SHLIB_EXT): all-multi
libgcc_ehs$(SHLIB_EXT)
rm libgcc_ehs.$(SHLIB_SOVERSION)$(SHLIB_EXT)_T*
-libgcc_s.1.dylib: libgcc_s.$(SHLIB_SOVERSION)$(SHLIB_EXT)
libgcc_ehs.$(SHLIB_SOVERSION)$(SHLIB_EXT)
+libgcc_s.1.dylib: all-multi libgcc_s.$(SHLIB_SOVERSION)$(SHLIB_EXT) \
+ libgcc_ehs.$(SHLIB_SOVERSION)$(SHLIB_EXT)
MLIBS=`$(CC) --print-multi-lib | sed -e 's/;.*$$//'` ; \
for mlib in $$MLIBS ; do \
cp ../$${mlib}/libgcc/$${mlib}/libgcc_s$(SHLIB_EXT) \
@@ -134,7 +134,7 @@ libgcc_s.1.dylib: libgcc_s.$(SHLIB_SOVERSION)$(SHLIB_EXT)
libgcc_ehs.$(SHLIB_SOV
else
-libgcc_s.1.dylib: libgcc_s.$(SHLIB_SOVERSION)$(SHLIB_EXT)
+libgcc_s.1.dylib: all-multi libgcc_s.$(SHLIB_SOVERSION)$(SHLIB_EXT)
MLIBS=`$(CC) --print-multi-lib | sed -e 's/;.*$$//'` ; \
for mlib in $$MLIBS ; do \
cp ../$${mlib}/libgcc/$${mlib}/libgcc_s$(SHLIB_EXT) \
--
2.24.3 (Apple Git-128)
Re: [PATCH]middle-end slp: check that the operation we're combing is a boolean operation [PR103741]
Tamar Christina writes:
> Hi All,
>
> It seems I forgot to check that the operation we're combing when masking the
> predicated together are actually predicates types.
>
> Without it we end up accidentally trying to combine a value and a mask.
>
> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
>
> Ok for master?
>
> Thanks,
> Tamar
>
> gcc/ChangeLog:
>
> PR tree-optimization/103741
> * tree-vect-stmts.c (vectorizable_operation): Check for boolean.
>
> gcc/testsuite/ChangeLog:
>
> PR tree-optimization/103741
> * gcc.target/aarch64/pr103741.c: New test.
>
> --- inline copy of patch --
> diff --git a/gcc/testsuite/gcc.target/aarch64/pr103741.c
> b/gcc/testsuite/gcc.target/aarch64/pr103741.c
> new file mode 100644
> index
> ..ef3ae66ebe5e5a44e7bea7be22b6378bc23cc538
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/pr103741.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-march=armv8-a+sve -O1" } */
> +
> +long int m, n;
> +
> +int
> +qux (int z)
> +{
> + return 4 >> z ? z : 0;
> +}
> +
> +int
> +bar (long int y)
> +{
> + return y ? 3 : 2;
> +}
> +
> +__attribute__ ((simd)) int
> +foo (int x)
> +{
> + long int a = x & m;
> + int b = bar (x) / n;
> +
> + return qux (b) == a;
> +}
> +
> diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c
> index
> 8c427174b37e6c03c2f914c90332bcc4eac54130..ad90cdb0473a337207d6ba54c1dd0a2ecc50ab8d
> 100644
> --- a/gcc/tree-vect-stmts.c
> +++ b/gcc/tree-vect-stmts.c
> @@ -6361,7 +6361,9 @@ vectorizable_operation (vec_info *vinfo,
> /* When combining two masks check if either of them is elsewhere
>combined with a loop mask, if that's the case we can mark that the
>new combined mask doesn't need to be combined with a loop mask. */
> - if (masked_loop_p && code == BIT_AND_EXPR)
> + if (masked_loop_p
> + && code == BIT_AND_EXPR
> + && VECTOR_BOOLEAN_TYPE_P (vectype))
> {
> if (loop_vinfo->scalar_cond_masked_set.contains ({ op0,
>ncopies}))
Ah, so the reason that scalar_cond_masked_set.contains is not robust
against non-boolean op0 (despite looking like it might be) is that
we previously entered:
cmp = X != 0
into the set as . Then looking up X implicitly becomes
too.
So yeah, the patch is OK, thanks.
Richard
Re: [2/2] PR96463 -- changes to type checking vec_perm_expr in middle end
Prathamesh Kulkarni writes:
> Hi,
> The attached patch rearranges order of type-check for vec_perm_expr
> and relaxes type checking for
> lhs = vec_perm_expr
>
> when:
> rhs1 == rhs2,
> lhs is variable length vector,
> rhs1 is fixed length vector,
> TREE_TYPE (lhs) == TREE_TYPE (rhs1)
>
> I am not sure tho if this check is correct ? My intent was to capture
> case when vec_perm_expr is used to "extend" fixed length vector to
> it's VLA equivalent.
VLAness isn't really the issue. We want the same thing to work for
-msve-vector-bits=256, -msve-vector-bits=512, etc., even though the
vectors are fixed-length in that case.
The principle is that for:
A = VEC_PERM_EXPR ;
the requirements are:
- A, B, C and D must be vectors
- A, B and C must have the same element type
- D must have an integer element type
- A and D must have the same number of elements (NA)
- B and C must have the same number of elements (NB)
The semantics are that we create a joined vector BC (all elements of B
followed by all element of C) and that:
A[i] = BC[D[i] % (NB+NB)]
for 0 ≤ i < NA.
This operation makes sense even if NA != NB.
Thanks,
Richard
>
> Thanks,
> Prathamesh
>
> diff --git a/gcc/tree-cfg.c b/gcc/tree-cfg.c
> index 672e384ef09..9f91878c468 100644
> --- a/gcc/tree-cfg.c
> +++ b/gcc/tree-cfg.c
> @@ -4325,10 +4325,11 @@ verify_gimple_assign_ternary (gassign *stmt)
>break;
>
> case VEC_PERM_EXPR:
> - if (!useless_type_conversion_p (lhs_type, rhs1_type)
> - || !useless_type_conversion_p (lhs_type, rhs2_type))
> + if (TREE_CODE (rhs1_type) != VECTOR_TYPE
> + || TREE_CODE (rhs2_type) != VECTOR_TYPE
> + || TREE_CODE (rhs3_type) != VECTOR_TYPE)
> {
> - error ("type mismatch in %qs", code_name);
> + error ("vector types expected in %qs", code_name);
> debug_generic_expr (lhs_type);
> debug_generic_expr (rhs1_type);
> debug_generic_expr (rhs2_type);
> @@ -4336,11 +4337,14 @@ verify_gimple_assign_ternary (gassign *stmt)
> return true;
> }
>
> - if (TREE_CODE (rhs1_type) != VECTOR_TYPE
> - || TREE_CODE (rhs2_type) != VECTOR_TYPE
> - || TREE_CODE (rhs3_type) != VECTOR_TYPE)
> + if (TREE_CODE (TREE_TYPE (rhs3_type)) != INTEGER_TYPE
> + || (TREE_CODE (rhs3) != VECTOR_CST
> + && (GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE
> + (TREE_TYPE (rhs3_type)))
> + != GET_MODE_BITSIZE (SCALAR_TYPE_MODE
> +(TREE_TYPE (rhs1_type))
> {
> - error ("vector types expected in %qs", code_name);
> + error ("invalid mask type in %qs", code_name);
> debug_generic_expr (lhs_type);
> debug_generic_expr (rhs1_type);
> debug_generic_expr (rhs2_type);
> @@ -4348,15 +4352,18 @@ verify_gimple_assign_ternary (gassign *stmt)
> return true;
> }
>
> - if (maybe_ne (TYPE_VECTOR_SUBPARTS (rhs1_type),
> - TYPE_VECTOR_SUBPARTS (rhs2_type))
> - || maybe_ne (TYPE_VECTOR_SUBPARTS (rhs2_type),
> -TYPE_VECTOR_SUBPARTS (rhs3_type))
> - || maybe_ne (TYPE_VECTOR_SUBPARTS (rhs3_type),
> -TYPE_VECTOR_SUBPARTS (lhs_type)))
> + /* Accept lhs = vec_perm_expr if lhs is vector length
> agnostic,
> + and has same element type as v. */
> + if (!TYPE_VECTOR_SUBPARTS (lhs_type).is_constant ()
> + && operand_equal_p (rhs1, rhs2, 0)
> + && TYPE_VECTOR_SUBPARTS (rhs1_type).is_constant ()
> + && TREE_TYPE (lhs_type) == TREE_TYPE (rhs1_type))
> + return false;
> +
> + if (!useless_type_conversion_p (lhs_type, rhs1_type)
> + || !useless_type_conversion_p (lhs_type, rhs2_type))
> {
> - error ("vectors with different element number found in %qs",
> - code_name);
> + error ("type mismatch in %qs", code_name);
> debug_generic_expr (lhs_type);
> debug_generic_expr (rhs1_type);
> debug_generic_expr (rhs2_type);
> @@ -4364,21 +4371,21 @@ verify_gimple_assign_ternary (gassign *stmt)
> return true;
> }
>
> - if (TREE_CODE (TREE_TYPE (rhs3_type)) != INTEGER_TYPE
> - || (TREE_CODE (rhs3) != VECTOR_CST
> - && (GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE
> - (TREE_TYPE (rhs3_type)))
> - != GET_MODE_BITSIZE (SCALAR_TYPE_MODE
> -(TREE_TYPE (rhs1_type))
> + if (maybe_ne (TYPE_VECTOR_SUBPARTS (rhs1_type),
> + TYPE_VECTOR_SUBPARTS (rhs2_type))
> + || maybe_ne (TYPE_VECTOR_SUBPARTS (rhs2_type),
> +TYPE_VECTOR_SUBPARTS (rhs3_type))
> + || maybe_ne (TYPE_VECTOR_SUBPARTS (rhs3_type),
> +TYPE_VECTOR_SUBPARTS (lhs_type)))
> {
> - error ("invalid mask type in %qs", code_name);
> + error ("vectors with different element number found in %qs",
> + co
[PING] Fix size of static array in gcc.dg/vect/vect-simd-20.c
Hello, Ping for https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583222.html please ? Thanks in advance! With Kind Regards, Olivier > On 3 Nov 2021, at 15:54, Olivier Hainque wrote: > > Hello, > > This fixes the definition of the "p" static array in > gcc.dg/vect/vect-simd-20.c to accommodate the number of > strides performed by foo() for s == 78, which will be > 129 and not 128 since 1 / 78 > 128. > > This fixes a failure of the test we first observed in-house > on a x86_64-elf run, where the first call to foo() was clobbering > part of a static object we provide to __register_frame_info, > causing an abort() from __deregister_frame_info at termination time. > > Ok to commit? > > Thanks in advance, > > With Kind Regards, > > Olivier > > > 2021-11-02 Olivier Hainque > > testsuite/ > > * gcc.dg/vect/vect-simd-20.c: Fix size of p[] >to accommodate the number of strides performed >by foo() for s == 78. > >
Re: [1/2] PR96463 - aarch64 specific changes
Prathamesh Kulkarni writes:
> Hi,
> The patch folds:
> lhs = svld1rq ({-1, -1, -1, ...}, &v[0])
> into:
> lhs = vec_perm_expr
> and expands above vec_perm_expr using aarch64_expand_sve_dupq.
>
> With patch, for following test:
> #include
> #include
>
> svint32_t
> foo (int32x4_t x)
> {
> return svld1rq (svptrue_b8 (), &x[0]);
> }
>
> it generates following code:
> foo:
> .LFB4350:
> dup z0.q, z0.q[0]
> ret
>
> and passes bootstrap+test on aarch64-linux-gnu.
> But I am not sure if the changes to aarch64_evpc_sve_tbl
> are correct.
Just in case: I was only using int32x4_t in the PR as an example.
The same thing should work for all element types.
>
> Thanks,
> Prathamesh
>
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
> b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
> index 02e42a71e5e..e21bbec360c 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
> +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
> @@ -1207,6 +1207,56 @@ public:
> insn_code icode = code_for_aarch64_sve_ld1rq (e.vector_mode (0));
> return e.use_contiguous_load_insn (icode);
>}
> +
> + gimple *
> + fold (gimple_folder &f) const OVERRIDE
> + {
> +tree arg0 = gimple_call_arg (f.call, 0);
> +tree arg1 = gimple_call_arg (f.call, 1);
> +
> +/* Transform:
> + lhs = svld1rq ({-1, -1, ... }, &v[0])
> + into:
> + lhs = vec_perm_expr.
> + on little endian target. */
> +
> +if (!BYTES_BIG_ENDIAN
> + && integer_all_onesp (arg0)
> + && TREE_CODE (arg1) == ADDR_EXPR)
> + {
> + tree t = TREE_OPERAND (arg1, 0);
> + if (TREE_CODE (t) == ARRAY_REF)
> + {
> + tree index = TREE_OPERAND (t, 1);
> + t = TREE_OPERAND (t, 0);
> + if (integer_zerop (index) && TREE_CODE (t) == VIEW_CONVERT_EXPR)
> + {
> + t = TREE_OPERAND (t, 0);
> + tree vectype = TREE_TYPE (t);
> + if (VECTOR_TYPE_P (vectype)
> + && known_eq (TYPE_VECTOR_SUBPARTS (vectype), 4u)
> + && wi::to_wide (TYPE_SIZE (vectype)) == 128)
> + {
Since this is quite a specific pattern match, and since we now lower
arm_neon.h vld1* to normal gimple accesses, I think we should try the
“more generally” approach mentioned in the PR and see what the fallout
is. That is, keep:
if (!BYTES_BIG_ENDIAN
&& integer_all_onesp (arg0)
If those conditions pass, create an Advanced SIMD access at address arg1,
using similar code to the handling of:
BUILTIN_VALL_F16 (LOAD1, ld1, 0, LOAD)
BUILTIN_VDQ_I (LOAD1_U, ld1, 0, LOAD)
BUILTIN_VALLP_NO_DI (LOAD1_P, ld1, 0, LOAD)
in aarch64_general_gimple_fold_builtin. (Would be good to move the
common code to aarch64.c so that both files can use it.)
> + tree lhs = gimple_call_lhs (f.call);
> + tree lhs_type = TREE_TYPE (lhs);
> + int source_nelts = TYPE_VECTOR_SUBPARTS
> (vectype).to_constant ();
> + vec_perm_builder sel (TYPE_VECTOR_SUBPARTS (lhs_type),
> source_nelts, 1);
> + for (int i = 0; i < source_nelts; i++)
> + sel.quick_push (i);
> +
> + vec_perm_indices indices (sel, 1, source_nelts);
> + if (!can_vec_perm_const_p (TYPE_MODE (lhs_type), indices))
> + return NULL;
I don't think we need to check this: it should always be true.
Probably worth keeping as a gcc_checking_assert though.
> +
> + tree mask = vec_perm_indices_to_tree (lhs_type, indices);
> + return gimple_build_assign (lhs, VEC_PERM_EXPR, t, t, mask);
> + }
> + }
> + }
> + }
> +
> +return NULL;
> + }
> };
>
> class svld1ro_impl : public load_replicate
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index f07330cff4f..af27f550be3 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -23002,8 +23002,32 @@ aarch64_evpc_sve_tbl (struct expand_vec_perm_d *d)
>
>machine_mode sel_mode = related_int_vector_mode (d->vmode).require ();
>rtx sel = vec_perm_indices_to_rtx (sel_mode, d->perm);
> +
>if (d->one_vector_p)
> -emit_unspec2 (d->target, UNSPEC_TBL, d->op0, force_reg (sel_mode, sel));
> +{
> + bool use_dupq = false;
> + /* Check if sel is dup vector with encoded elements {0, 1, 2, ...
> nelts} */
> + if (GET_CODE (sel) == CONST_VECTOR
> + && !GET_MODE_NUNITS (GET_MODE (sel)).is_constant ()
> + && CONST_VECTOR_DUPLICATE_P (sel))
> + {
> + unsigned nelts = const_vector_encoded_nelts (sel);
> + unsigned i;
> + for (i = 0; i < nelts; i++)
> + {
> + rtx elem = CONST_VECTOR_ENCODED_ELT(sel, i);
> + if (!(CONST_INT_P (elem) && INTVAL(elem) == i))
> + break;
> + }
> + if (i == nelts)
> + use_dupq = true;
[PATCH] Add -mdejagnu-cpu=power9 to dg-options for pr97142.c
Hello, gcc.target/powerpc/pr97142.c scans the output assembly for specific instructions which our toolchain configured to default to -mcpu=604 doesn't produce. The PR refers to a power9 configuration for the original report, so the attached patch is a suggestion to add a -mdejagnu-cpu=power9 to dg-options, which gets the test to pass for us. Ok to commit? Thanks in advance, Olivier 0001-Add-mdejagnu-cpu-power9-to-dg-options-for-pr97142.c.diff Description: Binary data
[PATCH] Adjust VxWorks fixincludes hack for mkdir to work for C++
Hello, The attached patch adjusts a very old fixincludes hack for VxWorks, to expose a varargs function prototype for "mkdir" instead of a varargs macro (!). The function version is more amenable to calls from C++ like std::mkdir(arg1, arg2). This helps libstdc++ build failures for old versions of VxWorks, 6.9 in particular for which we were able to get a successful complete build after this and a couple of other fixincludes changes which I'll send separately. Also bootstrapped and regression tested ok for x86_64-linux, just in case. Ok to commit? Thanks in advance, With Kind Regards, Olivier 2021-12-16 Olivier Hainque fixincludes/ * inclhack.def (vxworks_posix_mkdir): Refine to expose a varargs interface. * tests/base/sys/stat.h: Update expected results. * fixinc.x: Regenerate. 0001-Adjust-VxWorks-fixincludes-hack-for-mkdir-to-work-fo.patch Description: Binary data
[PATCH] Add VxWorks fixincludes hack, open posix API
Hello, The attach patch adds a fixincludes "hack" for VxWorks to expose a more flexible (varargs) function prototype for 'open', able to accept calls with 2 or 3 arguments as we observe during libraries builds for powerpc vxworks 6.9. We have been using this for a while in-house. I could still observe related failures with mainline sources without the change and get a complete successful with it (plus a couple of others). Also bootstrapped and regression tested ok for x86_64-linux, just in case. Ok to commit? Thanks in advance, With Kind Regards, Olivier 2021-12-16 Olivier Hainque fixincludes/ * inclhack.def (vxworks_posix_open): New Hack. * tests/base/ioLib.h: Update expected results. * fixinc.x: Regenerate. 0002-Add-VxWorks-fixincludes-hack-open-posix-API.patch Description: Binary data
[PATCH] Add VxWorks fixincludes hack, kernel math.h FP_ constants
Hello, The attached patch adds a fixincludes add for VxWorks to add missing FP_ constant definition to math.h, intended for old versions of the kernel math.h header. As the other patches in the series, this helps libstdc++ build failures for old versions of VxWorks, 6.9 in particular for which we were able to get a successful complete build after this. Also bootstrapped and regression tested ok for x86_64-linux, just in case. Ok to commit? Thanks in advance, With Kind Regards, Olivier 2021-12-16 Olivier Hainque fixincludes/ * inclhack.def (vxworks_math_h_FP_macros): New hack. * tests/base/math.h: Update expected results. * fixinc.x: Regenerate. 0003-Add-VxWorks-fixincludes-hack-kernel-math.h-FP_-const.patch Description: Binary data
[PATCH] Add VxWworks fixincludes hack, prevent #include_next yvals.h
Hello, yvals.h on VxWorks expects the toolchain to provide its own version of the header, which we don't do. The attached patch adds a fixincludes hack to arrange to fallback on the common system definitions instead. We were able to get a successful complete build with c++ and libstdc++ after this. Also bootstrapped and regression tested ok for x86_64-linux, just in case. Ok to commit? Thanks in advance, With Kind Regards, Olivier 2021-12-16 Olivier Hainque fixincludes/ * inclhack.def (vxworks_next_yvals): New hack. * tests/base/yvals.h: New expected test result. * fixinc.x: Regenerate. 0004-Add-VxWworks-fixincludes-hack-prevent-include_next-y.patch Description: Binary data
Re: [AArch64] Enable generation of FRINTNZ instructions
"Andre Vieira (lists) via Gcc-patches" writes:
> On 22/11/2021 11:41, Richard Biener wrote:
>>
>>> On 18/11/2021 11:05, Richard Biener wrote:
This is a good shout and made me think about something I hadn't before... I
thought I could handle the vector forms later, but the problem is if I add
support for the scalar, it will stop the vectorizer. It seems
vectorizable_call expects all arguments to have the same type, which
doesn't
work with passing the integer type as an operand work around.
>> We already special case some IFNs there (masked load/store and gather)
>> to ignore some args, so that would just add to this set.
>>
>> Richard.
> Hi,
>
> Reworked it to add support of the new IFN to the vectorizer. Was
> initially trying to make vectorizable_call and
> vectorizable_internal_function handle IFNs with different inputs more
> generically, using the information we have in the _direct structs
> regarding what operands to get the modes from. Unfortunately, that
> wasn't straightforward because of how vectorizable_call assumes operands
> have the same type and uses the type of the DEF_STMT_INFO of the
> non-constant operands (either output operand or non-constant inputs) to
> determine the type of constants. I assume there is some reason why we
> use the DEF_STMT_INFO and not always use get_vectype_for_scalar_type on
> the argument types. That is why I ended up with this sort of half-way
> mix of both, which still allows room to add more IFNs that don't take
> inputs of the same type, but require adding a bit of special casing
> similar to the IFN_FTRUNC_INT and masking ones.
>
> Bootstrapped on aarch64-none-linux.
Still leaving the match.pd stuff to Richard, but otherwise:
> index
> bdc8ba3576cf2c9b4ae96b45a382234e4e25b13f..51f00344b02d0d1d4adf97463f6a46f9fd0fb43f
> 100644
> --- a/gcc/config/aarch64/iterators.md
> +++ b/gcc/config/aarch64/iterators.md
> @@ -160,7 +160,11 @@ (define_mode_iterator VHSDF_HSDF [(V4HF
> "TARGET_SIMD_F16INST")
> SF DF])
>
> ;; Scalar and vetor modes for SF, DF.
> -(define_mode_iterator VSFDF [V2SF V4SF V2DF DF SF])
> +(define_mode_iterator VSFDF [ (V2SF "TARGET_SIMD")
Nit: excess space between [ and (.
> + (V4SF "TARGET_SIMD")
> + (V2DF "TARGET_SIMD")
> + (DF "TARGET_FLOAT")
> + (SF "TARGET_FLOAT")])
>
> ;; Advanced SIMD single Float modes.
> (define_mode_iterator VDQSF [V2SF V4SF])
> […]
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index
> 41f1850bf6e95005647ca97a495a97d7e184d137..d50d09b0ae60d98537b9aece4396a490f33f174c
> 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -6175,6 +6175,15 @@ operands; otherwise, it may not.
>
> This pattern is not allowed to @code{FAIL}.
>
> +@cindex @code{ftrunc@var{m}@var{n}2} instruction pattern
> +@item @samp{ftrunc@var{m}@var{n}2}
> +Truncate operand 1 to a @var{n} mode signed integer, towards zero, and store
> +the result in operand 0. Both operands have mode @var{m}, which is a scalar
> or
> +vector floating-point mode. Exception must be thrown if operand 1 does not
> fit
Maybe “An exception must be raised”? “thrown” makes it sound like a
signal must be raised or C++ exception thrown.
> +in a @var{n} mode signed integer as it would have if the truncation happened
> +through separate floating point to integer conversion.
> +
> +
> @cindex @code{round@var{m}2} instruction pattern
> @item @samp{round@var{m}2}
> Round operand 1 to the nearest integer, rounding away from zero in the
> […]
> @@ -3688,6 +3712,15 @@ multi_vector_optab_supported_p (convert_optab optab,
> tree_pair types,
> != CODE_FOR_nothing);
> }
>
> +static bool direct_ftrunc_int_optab_supported_p (convert_optab optab,
> + tree_pair types,
> + optimization_type opt_type)
Formatting nit: should be a line break after “bool”
> +{
> + return (convert_optab_handler (optab, TYPE_MODE (types.first),
> + TYPE_MODE (element_type (types.second)),
> + opt_type) != CODE_FOR_nothing);
> +}
> +
> #define direct_unary_optab_supported_p direct_optab_supported_p
> #define direct_binary_optab_supported_p direct_optab_supported_p
> #define direct_ternary_optab_supported_p direct_optab_supported_p
> […]
> diff --git a/gcc/testsuite/gcc.target/aarch64/frintnz_vec.c
> b/gcc/testsuite/gcc.target/aarch64/frintnz_vec.c
> new file mode 100644
> index
> ..b93304eb2acb3d3d954eebee51d77ff23fee68ac
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/frintnz_vec.c
> @@ -0,0 +1,47 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O3 -march=armv8.5-a" } */
> +/* { dg-require-effective-target aarch64_frintnzx_ok } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +
Re: [PATCH] Add VxWorks fixincludes hack, open posix API
On 17/12/2021 13.01, Olivier Hainque wrote:
> Hello,
>
> The attach patch adds a fixincludes "hack" for VxWorks
> to expose a more flexible (varargs) function prototype for 'open',
> able to accept calls with 2 or 3 arguments as we observe
> during libraries builds for powerpc vxworks 6.9.
>
> We have been using this for a while in-house. I could
> still observe related failures with mainline sources without
> the change and get a complete successful with it (plus a couple
> of others).
>
> Also bootstrapped and regression tested ok for x86_64-linux,
> just in case.
>
> Ok to commit?
I had proposed more-or-less the same patch to my customer, just being
done to the vxworks 5.5 headers directly.
We then looked at the part of the kernel source we do have available
(and which gets rebuilt when they build their OS kernel). That happens
to include the open() implementation. We could modify the open()
implementation accordingly, fetching a mode argument iff there's O_CREAT
in flags, and otherwise setting it to 0. Unfortunately, looking down the
call tree from open(), it turns out that there are some weird uses of
the mode argument even when O_CREAT was not given (I don't remember the
details, but I think one case was looking at a non-mode bit, S_IFDIR. It
was somewhat hard to follow due to several levels of indirect calls, and
I don't even think we had the code for all the possible callbacks).
Unconditionally fetching the third argument [1] isn't really an option
either as that would be garbage for any two-argument call site.
In the end, we ended up adding a two-argument overload for C++ only, as
this is/was only relevant for getting libstdc++ (more specifically, the
new filesystem abstraction stuff) to build. That is, we added
+#if __GNUC__ > 6 && defined(__cplusplus)
+extern "C++" {
+extern int open (const char *name, int flags);
+}
+#endif
+
to fcntl.h, and added a trivial definition of that (which calls the
tree-argument form with a 0 for mode) to the OS build. I guess it could
also have been an inline.
Another option we considered was inspired the fortified definition of
open() in glibc, which checks that when flags is compile-time known and
O_CREAT is there, there is a mode argument. We would not do that check,
but simply use __va_arg_pack_len() to decide whether the caller had
given a mode argument, and if not, pass a 0. That would also provide C
code with the ability to use both two- and three-arg open().
I'm not sure what to do. But this patch will definitely break our build
- primarily because we've done a private workaround.
Rasmus
[1] Instead of making the open() definition variadic, we could probably
also play a trick like renaming it at C level, and then re-renaming at
asm level, i.e. something like
-int open(const char *path, int flags, int mode) {
+int vxworks_open(const char *path, int flags, int mode) asm("open") {
...
but that would still make mode contain garbage when called with two
arguments.
Re: [PATCH] Add -mdejagnu-cpu=power9 to dg-options for pr97142.c
Hi Olivier, On Fri, Dec 17, 2021 at 12:43:32PM +0100, Olivier Hainque wrote: > gcc.target/powerpc/pr97142.c scans the output assembly > for specific instructions which our toolchain configured > to default to -mcpu=604 doesn't produce. > > The PR refers to a power9 configuration for the original > report, so the attached patch is a suggestion to add a > -mdejagnu-cpu=power9 to dg-options, which gets the test > to pass for us. Thanks for the patch! Please use p7 instead of p9. Also, you attached some binary, so I cannot reply to it easily. Thanks, Segher
Re: [PATCH] Add VxWorks fixincludes hack, kernel math.h FP_ constants
On 17/12/2021 13.10, Olivier Hainque wrote: > Hello, > > The attached patch adds a fixincludes add for VxWorks > to add missing FP_ constant definition to math.h, intended > for old versions of the kernel math.h header. Don't you also need to add an fpclassify() macro? There's a checking for ISO C99 support in for C++98 which checks whether math.h supplies (among others) fpclassify(). We've patched our math.h to supply those constants as well as an fpclassify() macro. So I suppose the 'bypass = "FP_INFINITE"' would mean that this fixinclude would just be skipped for our case(?). Rasmus
Re: [PATCH] Add VxWworks fixincludes hack, prevent #include_next yvals.h
On 17/12/2021 13.14, Olivier Hainque wrote: > Hello, > > yvals.h on VxWorks expects the toolchain to provide its own > version of the header, which we don't do. > > The attached patch adds a fixincludes hack to arrange to fallback > on the common system definitions instead. > > We were able to get a successful complete build with c++ and > libstdc++ after this. > > Also bootstrapped and regression tested ok for x86_64-linux, > just in case. There's no yvals.h header in VxWorks 5.5, so I'm not sure I need to have an opinion on this one. Rasmus
[PATCH][pushed] docs: Fix spelling issues in -fipa-strict-aliasing.
Installed as obvious.
gcc/ChangeLog:
* doc/invoke.texi: Fix spelling issues.
---
gcc/doc/invoke.texi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 37836a7d614..8f69e53e68e 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12425,10 +12425,10 @@ The @option{-fstrict-aliasing} option is enabled at
levels
@item -fipa-strict-aliasing
@opindex fipa-strict-aliasing
-Constrols whether rules of @option{-fstrict-aliasing} are applied across
+Controls whether rules of @option{-fstrict-aliasing} are applied across
function boundaries. Note that if multiple functions gets inlined into a
-signle function the memory accesses are no longer considred to be crossing a
-function bounday.
+single function the memory accesses are no longer considered to be crossing a
+function boundary.
The @option{-fipa-strict-aliasing} option is enabled by default and is
effective only in combination with @option{-fstrict-aliasing}.
--
2.34.1
Re: [pushed] Darwin, ppc: Additional change for r12-5974.
Iain, thanks very much for fixing this, and I'm very sorry for the oversight!
Bill
On 12/17/21 3:46 AM, Iain Sandoe via Gcc-patches wrote:
> This adds a missed change from r12-5974-g926d64906af.
> The builin_decls array has been renamed to drop the trailing
> _x that was used during the main changes to the builtins.
>
> This fixes bootstrap for powerpc-darwin9, tested there, pushed
> to master, thanks,
> Iain
>
> Signed-off-by: Iain Sandoe
>
> gcc/ChangeLog:
>
> * config/rs6000/darwin.h: Drop trailing _x from the
> builtin_decls array name.
> ---
> gcc/config/rs6000/darwin.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
> index 7bc1009a523..8288003038e 100644
> --- a/gcc/config/rs6000/darwin.h
> +++ b/gcc/config/rs6000/darwin.h
> @@ -507,7 +507,7 @@
> #define SUBTARGET_INIT_BUILTINS
> \
> do { \
>darwin_patch_builtins (); \
> - rs6000_builtin_decls_x[(unsigned) (RS6000_BIF_CFSTRING)] \
> + rs6000_builtin_decls[(unsigned) (RS6000_BIF_CFSTRING)] \
> = darwin_init_cfstring_builtins ((unsigned) (RS6000_BIF_CFSTRING)); \
> } while(0)
>
Re: [PATCH] Add -mdejagnu-cpu=power9 to dg-options for pr97142.c
> On 17 Dec 2021, at 13:58, Segher Boessenkool
> wrote:
>
> Hi Olivier,
>
> Thanks for the patch!
>
> Please use p7 instead of p9.
Sure.
> Also, you attached some binary, so I cannot reply to it easily.
Ah, sorry. I did remember you told me this in the past
and renamed the file .diff to "circumvent" that, which
used to work. I'll check again.
In this instance, it's simple enough to be quoted directly:
--- a/gcc/testsuite/gcc.target/powerpc/pr97142.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr97142.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-Ofast" } */
+/* { dg-options "-Ofast -mdejagnu-cpu=power9" } */
I'll change to power7 and commit.
Thanks for your feedback!
Cheers,
Olivier
Re: [PATCH] Add VxWorks fixincludes hack, open posix API
Hi Rasmus > On 17 Dec 2021, at 13:49, Rasmus Villemoes wrote: > I'm not sure what to do. But this patch will definitely break our build > - primarily because we've done a private workaround. I don't think we can reasonably cope with private changes to system headers. Can't you just undo your workaround and use this (very simple) "fix" instead? Otherwise, add a local patch to your tree to remove this fix? Thanks in advance, Olivier
Re: [PATCH] Add VxWworks fixincludes hack, prevent #include_next yvals.h
> On 17 Dec 2021, at 14:16, Rasmus Villemoes wrote: > > There's no yvals.h header in VxWorks 5.5, so I'm not sure I need to have > an opinion on this one. I wasn't sure about the situation on 5.5 but the fix just wont apply if there's no yvals.h around anyway. Cheers, Olivier
Re: [PATCH] middle-end/57245 - honor -frounding-math in real truncation
On Thu, Oct 28, 2021 at 2:23 AM Jakub Jelinek via Gcc-patches wrote: > > On Thu, Oct 28, 2021 at 10:11:36AM +0200, Richard Biener wrote: > > 2021-10-27 Richard Biener > > > > PR middle-end/57245 > > * fold-const.c (fold_convert_const_real_from_real): Honor > > -frounding-math if the conversion is not exact. > > * simplify-rtx.c (simplify_const_unary_operation): Do not > > simplify FLOAT_TRUNCATE with sign dependent rounding. > > > > * gcc.dg/torture/fp-double-convert-float-1.c: New testcase. > > LGTM, thanks. > > Jakub > This miscompiled libm in glibc: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103735 -- H.J.
Re: [GCC-10 PATCH] aarch64: enable Ampere-1 CPU
Philipp Tomsich writes:
> This adds support and a basic tuning model for the Ampere Computing
> "Ampere-1" CPU.
>
> The Ampere-1 implements the ARMv8.6 architecture in A64 mode and is
> modelled as a 4-wide issue (as with all modern micro-architectures,
> the chosen issue rate is a compromise between the maximum dispatch
> rate and the maximum rate of uops issued to the scheduler).
>
> This adds the -mcpu=ampere1 command-line option and the relevant cost
> information/tuning tables for the Ampere-1.
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-cores.def (AARCH64_CORE): New Ampere-1
> core.
> * config/aarch64/aarch64-tune.md: Regenerate.
> * config/aarch64/aarch64-cost-tables.h: Add extra costs for
> Ampere-1.
> * config/aarch64/aarch64.c: Add tuning structures for Ampere-1.
> * doc/invoke.texi: Add documentation for Ampere-1 core.
OK, thanks.
Richard
> (cherry picked from commit 67b0d47e20e655c0dd53a76ea88aab60fafb2059)
>
> ---
> This is a backport from master and only affects the AArch64 backend.
> A similar change is already backported to GCC-11.
>
> OK for GCC-10?
>
> gcc/config/aarch64/aarch64-cores.def | 3 +-
> gcc/config/aarch64/aarch64-cost-tables.h | 103 +++
> gcc/config/aarch64/aarch64-tune.md | 2 +-
> gcc/config/aarch64/aarch64.c | 59 +
> gcc/doc/invoke.texi | 2 +-
> 5 files changed, 166 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64-cores.def
> b/gcc/config/aarch64/aarch64-cores.def
> index fc60e2ae1ac..3c858160cef 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -68,7 +68,8 @@ AARCH64_CORE("octeontx83",octeontxt83, thunderx, 8A,
> AARCH64_FL_FOR_ARCH
> AARCH64_CORE("thunderxt81", thunderxt81, thunderx, 8A,
> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43,
> 0x0a2, -1)
> AARCH64_CORE("thunderxt83", thunderxt83, thunderx, 8A,
> AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43,
> 0x0a3, -1)
>
> -/* Ampere Computing cores. */
> +/* Ampere Computing ('\xC0') cores. */
> +AARCH64_CORE("ampere1", ampere1, cortexa57, 8_6A, AARCH64_FL_FOR_ARCH8_6,
> ampere1, 0xC0, 0xac3, -1)
> /* Do not swap around "emag" and "xgene1",
> this order is required to handle variant correctly. */
> AARCH64_CORE("emag",emag, xgene1,8A, AARCH64_FL_FOR_ARCH8
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, emag, 0x50, 0x000, 3)
> diff --git a/gcc/config/aarch64/aarch64-cost-tables.h
> b/gcc/config/aarch64/aarch64-cost-tables.h
> index c6805717f6e..9f9627b864e 100644
> --- a/gcc/config/aarch64/aarch64-cost-tables.h
> +++ b/gcc/config/aarch64/aarch64-cost-tables.h
> @@ -644,4 +644,107 @@ const struct cpu_cost_table a64fx_extra_costs =
>}
> };
>
> +const struct cpu_cost_table ampere1_extra_costs =
> +{
> + /* ALU */
> + {
> +0, /* arith. */
> +0, /* logical. */
> +0, /* shift. */
> +COSTS_N_INSNS (1), /* shift_reg. */
> +0, /* arith_shift. */
> +COSTS_N_INSNS (1), /* arith_shift_reg. */
> +0, /* log_shift. */
> +COSTS_N_INSNS (1), /* log_shift_reg. */
> +0, /* extend. */
> +COSTS_N_INSNS (1), /* extend_arith. */
> +0, /* bfi. */
> +0, /* bfx. */
> +0, /* clz. */
> +0, /* rev. */
> +0, /* non_exec. */
> +true /* non_exec_costs_exec. */
> + },
> + {
> +/* MULT SImode */
> +{
> + COSTS_N_INSNS (3), /* simple. */
> + COSTS_N_INSNS (3), /* flag_setting. */
> + COSTS_N_INSNS (3), /* extend. */
> + COSTS_N_INSNS (4), /* add. */
> + COSTS_N_INSNS (4), /* extend_add. */
> + COSTS_N_INSNS (18) /* idiv. */
> +},
> +/* MULT DImode */
> +{
> + COSTS_N_INSNS (3), /* simple. */
> + 0, /* flag_setting (N/A). */
> + COSTS_N_INSNS (3), /* extend. */
> + COSTS_N_INSNS (4), /* add. */
> + COSTS_N_INSNS (4), /* extend_add. */
> + COSTS_N_INSNS (34) /* idiv. */
> +}
> + },
> + /* LD/ST */
> + {
> +COSTS_N_INSNS (4), /* load. */
> +COSTS_N_INSNS (4), /* load_sign_extend. */
> +0, /* ldrd (n/a). */
> +0, /* ldm_1st. */
> +0, /* ldm_regs_per_insn_1st. */
> +0, /* ldm_regs_per_insn_subsequent. */
> +COSTS_N_INSNS (5), /* loadf. */
> +COSTS_N_INSNS (5), /* loadd. */
> +COSTS_N_INSNS (5), /* load_unaligned. */
> +0, /* store. */
> +0, /* strd. */
> +
Re: [PATCH] Add VxWorks fixincludes hack, open posix API
On 17/12/2021 15.12, Olivier Hainque wrote:
> Hi Rasmus
>
>> On 17 Dec 2021, at 13:49, Rasmus Villemoes
>> wrote:
>
>> I'm not sure what to do. But this patch will definitely break our build
>> - primarily because we've done a private workaround.
>
> I don't think we can reasonably cope with private changes
> to system headers.
Of course not. And I'm more than willing to undo that private change if
a suitable fix can be worked out.
> Can't you just undo your workaround and use this (very simple)
> "fix" instead?
No, because as I explained, the open() implementation on vxworks 5.5
must not be called as a two-arg function with garbage in r5. Do you have
access to any of the kernel source code for the other vxworks versions
with a three-arg-only open() in fcntl.h? If not, how can you know that
those kernels do not make use of the mode argument even if O_CREAT is
not in flags? (For example, I could actually imagine an implementation
where non-zero mode would imply O_CREAT. Then 'open("foo", O_RDWR)'
could result in foo being created with a more-or-less random mode, where
it should have resulted in ENOENT.)
I'm sure libstdc++ builds with this change, as I said I had the same
thing initially, but after looking at the open() implementation we were
worried about the implications.
> Otherwise, add a local patch to your tree to remove this fix?
Always an option, of course.
Rasmus
Re: [PATCH] Add VxWorks fixincludes hack, open posix API
> On 17 Dec 2021, at 15:33, Rasmus Villemoes wrote:
>
> On 17/12/2021 15.12, Olivier Hainque wrote:
>> Hi Rasmus
>>
>>> On 17 Dec 2021, at 13:49, Rasmus Villemoes
>>> wrote:
>>
>>> I'm not sure what to do. But this patch will definitely break our build
>>> - primarily because we've done a private workaround.
>>
>> I don't think we can reasonably cope with private changes
>> to system headers.
>
> Of course not. And I'm more than willing to undo that private change if
> a suitable fix can be worked out.
>
>> Can't you just undo your workaround and use this (very simple)
>> "fix" instead?
>
> No, because as I explained, the open() implementation on vxworks 5.5
> must not be called as a two-arg function with garbage in r5.
> Do you have
> access to any of the kernel source code for the other vxworks versions
> with a three-arg-only open() in fcntl.h? If not, how can you know that
> those kernels do not make use of the mode argument even if O_CREAT is
> not in flags? (For example, I could actually imagine an implementation
> where non-zero mode would imply O_CREAT. Then 'open("foo", O_RDWR)'
> could result in foo being created with a more-or-less random mode, where
> it should have resulted in ENOENT.)
>
> I'm sure libstdc++ builds with this change, as I said I had the same
> thing initially, but after looking at the open() implementation we were
> worried about the implications.
Ah, I see. Sorry, I misunderstood the point you were making.
Let me check and think about it some more.
Cheers,
Olivier
Re: [PATCH] Add -mdejagnu-cpu=power9 to dg-options for pr97142.c
On Fri, Dec 17, 2021 at 03:04:19PM +0100, Olivier Hainque wrote:
> > On 17 Dec 2021, at 13:58, Segher Boessenkool
> > wrote:
> > Please use p7 instead of p9.
>
> Sure.
>
> > Also, you attached some binary, so I cannot reply to it easily.
>
> Ah, sorry. I did remember you told me this in the past
> and renamed the file .diff to "circumvent" that, which
> used to work. I'll check again.
It was sent as application/octet-stream. It should just be text/plain
(all the x-* that people use are undefined as well fwiw).
> In this instance, it's simple enough to be quoted directly:
You may want to look into git send-email :-)
> --- a/gcc/testsuite/gcc.target/powerpc/pr97142.c
> +++ b/gcc/testsuite/gcc.target/powerpc/pr97142.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-Ofast" } */
> +/* { dg-options "-Ofast -mdejagnu-cpu=power9" } */
>
> I'll change to power7 and commit.
Okay for trunk like that. Thanks!
Segher
[1/3 PATCH]middle-end vect: Simplify and extend the complex numbers validation routines.
Hi All,
This patch boosts the analysis for complex mul,fma and fms in order to ensure
that it doesn't create an incorrect output.
Essentially it adds an extra verification to check that the two nodes it's going
to combine do the same operations on compatible values. The reason it needs to
do this is that if one computation differs from the other then with the current
implementation we have no way to deal with it since we have to remove the
permute.
When we can keep the permute around we can probably handle these by unrolling.
While implementing this since I have to do the traversal anyway I took advantage
of it by simplifying the code a bit. Previously we would determine whether
something is a conjugate and then try to figure out which conjugate it is and
then try to see if the permutes match what we expect.
Now the code that does the traversal will detect this in one go and return to us
whether the operation is something that can be combined and whether a conjugate
is present.
Secondly because it does this I can now simplify the checking code itself to
essentially just try to apply fixed patterns to each operation.
The patterns represent the order operations should appear in. For instance a
complex MUL operation combines :
Left 1 + Right 1
Left 2 + Right 2
with a permute on the nodes consisting of:
{ Even, Even } + { Odd, Odd }
{ Even, Odd } + { Odd, Even }
By abstracting over these patterns the checking code becomes quite simple.
As part of this I was checking the order of the operands which was left in
"slp" order. as in, the same order they showed up in during SLP, which means
that the accumulator is first. However it looks like I didn't document this
and the x86 optab was implemented assuming the same order as FMA, i.e. that
the accumulator is last.
I have this changed the order to match that of FMA and FMS which corrects the
x86 codegen and will update the Arm targets. This has now also been
documented.
Bootstrapped Regtested on aarch64-none-linux-gnu,
x86_64-pc-linux-gnu and no regressions.
Ok for master? and backport to GCC 11 after some stew?
Thanks,
Tamar
gcc/ChangeLog:
PR tree-optimization/102819
PR tree-optimization/103169
* doc/md.texi: Update docs for cfms, cfma.
* tree-data-ref.h (same_data_refs): Accept optional offset.
* tree-vect-slp-patterns.c (is_linear_load_p): Fix issue with repeating
patterns.
(vect_normalize_conj_loc): Remove.
(is_eq_or_top): Change to take two nodes.
(enum _conj_status, compatible_complex_nodes_p,
vect_validate_multiplication): New.
(class complex_add_pattern, complex_add_pattern::matches,
complex_add_pattern::recognize, class complex_mul_pattern,
complex_mul_pattern::recognize, class complex_fms_pattern,
complex_fms_pattern::recognize, class complex_operations_pattern,
complex_operations_pattern::recognize, addsub_pattern::recognize): Pass
new cache.
(complex_fms_pattern::matches, complex_mul_pattern::matches): Pass new
cache and use new validation code.
* tree-vect-slp.c (vect_match_slp_patterns_2, vect_match_slp_patterns,
vect_analyze_slp): Pass along cache.
(compatible_calls_p): Expose.
* tree-vectorizer.h (compatible_calls_p, slp_node_hash,
slp_compat_nodes_map_t): New.
(class vect_pattern): Update signatures include new cache.
gcc/testsuite/ChangeLog:
PR tree-optimization/102819
PR tree-optimization/103169
* g++.dg/vect/pr99149.cc: xfail for now.
* gcc.dg/vect/complex/pr102819-1.c: New test.
* gcc.dg/vect/complex/pr102819-2.c: New test.
* gcc.dg/vect/complex/pr102819-3.c: New test.
* gcc.dg/vect/complex/pr102819-4.c: New test.
* gcc.dg/vect/complex/pr102819-5.c: New test.
* gcc.dg/vect/complex/pr102819-6.c: New test.
* gcc.dg/vect/complex/pr102819-7.c: New test.
* gcc.dg/vect/complex/pr102819-8.c: New test.
* gcc.dg/vect/complex/pr102819-9.c: New test.
* gcc.dg/vect/complex/pr103169.c: New test.
--- inline copy of patch --
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index
9ec051e94e10cca9eec2773e1b8c01b74b6ea4db..60dc5b3ea6087c2824ad1467bc66e9cfebe9dcfc
100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -6325,12 +6325,12 @@ Perform a vector multiply and accumulate that is
semantically the same as
a multiply and accumulate of complex numbers.
@smallexample
- complex TYPE c[N];
- complex TYPE a[N];
- complex TYPE b[N];
+ complex TYPE op0[N];
+ complex TYPE op1[N];
+ complex TYPE op2[N];
for (int i = 0; i < N; i += 1)
@{
- c[i] += a[i] * b[i];
+ op2[i] += op1[i] * op2[i];
@}
@end smallexample
@@ -6348,12 +6348,12 @@ the same as a multiply and accumulate of complex
numbers where the second
multiply arguments is conjugated.
@smallexample
- complex TYPE c[N];
- complex TYPE a[N];
- compl
[2/3 PATCH]AArch64 use canonical ordering for complex mul, fma and fms
Hi All,
After the first patch in the series this updates the optabs to expect the
canonical sequence.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master? and backport along with the first patch?
Thanks,
Tamar
gcc/ChangeLog:
PR tree-optimization/102819
PR tree-optimization/103169
* config/aarch64/aarch64-simd.md (cml4,
cmul3): Use canonical order.
* config/aarch64/aarch64-sve.md (cml4,
cmul3): Likewise.
--- inline copy of patch --
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index
f95a7e1d91c97c9e981d75e71f0b49c02ef748ba..875896ee71324712c8034eeff9cfb5649f9b0e73
100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -556,17 +556,17 @@ (define_insn "aarch64_fcmlaq_lane"
;; remainder. Because of this, expand early.
(define_expand "cml4"
[(set (match_operand:VHSDF 0 "register_operand")
- (plus:VHSDF (match_operand:VHSDF 1 "register_operand")
- (unspec:VHSDF [(match_operand:VHSDF 2 "register_operand")
- (match_operand:VHSDF 3 "register_operand")]
- FCMLA_OP)))]
+ (plus:VHSDF (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand")
+ (match_operand:VHSDF 2 "register_operand")]
+ FCMLA_OP)
+ (match_operand:VHSDF 3 "register_operand")))]
"TARGET_COMPLEX && !BYTES_BIG_ENDIAN"
{
rtx tmp = gen_reg_rtx (mode);
- emit_insn (gen_aarch64_fcmla (tmp, operands[1],
-operands[3], operands[2]));
+ emit_insn (gen_aarch64_fcmla (tmp, operands[3],
+operands[1], operands[2]));
emit_insn (gen_aarch64_fcmla (operands[0], tmp,
-operands[3], operands[2]));
+operands[1], operands[2]));
DONE;
})
@@ -583,9 +583,9 @@ (define_expand "cmul3"
rtx tmp = force_reg (mode, CONST0_RTX (mode));
rtx res1 = gen_reg_rtx (mode);
emit_insn (gen_aarch64_fcmla (res1, tmp,
-operands[2], operands[1]));
+operands[1], operands[2]));
emit_insn (gen_aarch64_fcmla (operands[0], res1,
-operands[2], operands[1]));
+operands[1], operands[2]));
DONE;
})
diff --git a/gcc/config/aarch64/aarch64-sve.md
b/gcc/config/aarch64/aarch64-sve.md
index
9ef968840c20a3049901b3f8a919cf27ded1da3e..96a57442c7eb5f1080c8014a2f0311b2350de852
100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -7278,11 +7278,11 @@ (define_expand "cml4"
rtx tmp = gen_reg_rtx (mode);
emit_insn
(gen_aarch64_pred_fcmla (tmp, operands[4],
-operands[3], operands[2],
-operands[1], operands[5]));
+operands[1], operands[2],
+operands[3], operands[5]));
emit_insn
(gen_aarch64_pred_fcmla (operands[0], operands[4],
-operands[3], operands[2],
+operands[1], operands[2],
tmp, operands[5]));
DONE;
})
@@ -7305,11 +7305,11 @@ (define_expand "cmul3"
rtx tmp = gen_reg_rtx (mode);
emit_insn
(gen_aarch64_pred_fcmla (tmp, pred_reg,
-operands[2], operands[1],
+operands[1], operands[2],
accum, gp_mode));
emit_insn
(gen_aarch64_pred_fcmla (operands[0], pred_reg,
-operands[2], operands[1],
+operands[1], operands[2],
tmp, gp_mode));
DONE;
})
--
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index f95a7e1d91c97c9e981d75e71f0b49c02ef748ba..875896ee71324712c8034eeff9cfb5649f9b0e73 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -556,17 +556,17 @@ (define_insn "aarch64_fcmlaq_lane"
;; remainder. Because of this, expand early.
(define_expand "cml4"
[(set (match_operand:VHSDF 0 "register_operand")
- (plus:VHSDF (match_operand:VHSDF 1 "register_operand")
- (unspec:VHSDF [(match_operand:VHSDF 2 "register_operand")
- (match_operand:VHSDF 3 "register_operand")]
- FCMLA_OP)))]
+ (plus:VHSDF (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand")
+ (match_operand:VHSDF 2 "register_operand")]
+ FCMLA_OP)
+ (match
[3/3 PATCH][AArch32] use canonical ordering for complex mul, fma and fms
Hi All,
After the first patch in the series this updates the optabs to expect the
canonical sequence.
Bootstrapped Regtested on arm-none-linux-gnueabihf and no issues.
Ok for master? and backport along with the first patch?
Thanks,
Tamar
gcc/ChangeLog:
PR tree-optimization/102819
PR tree-optimization/103169
* config/arm/neon.md (cmul3): Use canon order.
* config/arm/vec-common.md (cmul3,
cml4): Likewise.
--- inline copy of patch --
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index
8b0a396947cc8e7345f178b926128d7224fb218a..2b6ae67a7ec6bef505c2eaef0ec495d14c656495
100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2859,9 +2859,9 @@ (define_expand "cmul3"
rtx res1 = gen_reg_rtx (mode);
rtx tmp = force_reg (mode, CONST0_RTX (mode));
emit_insn (gen_neon_vcmla (res1, tmp,
- operands[2], operands[1]));
+ operands[1], operands[2]));
emit_insn (gen_neon_vcmla (operands[0], res1,
- operands[2], operands[1]));
+ operands[1], operands[2]));
DONE;
})
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index
e71d9b3811fde62159f5c21944fef9fe3f97b4bd..0940e987de53e191f4abdd248c654aed69f016f7
100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -239,14 +239,14 @@ (define_expand "cmul3"
{
rtx tmp = force_reg (mode, CONST0_RTX (mode));
emit_insn (gen_arm_vcmla (res1, tmp,
-operands[2], operands[1]));
+operands[1], operands[2]));
}
else
emit_insn (gen_arm_vcmla (res1, CONST0_RTX (mode),
- operands[2], operands[1]));
+ operands[1], operands[2]));
emit_insn (gen_arm_vcmla (operands[0], res1,
-operands[2], operands[1]));
+operands[1], operands[2]));
DONE;
})
@@ -265,18 +265,18 @@ (define_expand "arm_vcmla"
;; remainder. Because of this, expand early.
(define_expand "cml4"
[(set (match_operand:VF 0 "register_operand")
- (plus:VF (match_operand:VF 1 "register_operand")
-(unspec:VF [(match_operand:VF 2 "register_operand")
-(match_operand:VF 3 "register_operand")]
- VCMLA_OP)))]
+ (plus:VF (unspec:VF [(match_operand:VF 1 "register_operand")
+(match_operand:VF 2 "register_operand")]
+ VCMLA_OP)
+(match_operand:VF 3 "register_operand")))]
"(TARGET_COMPLEX || (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT
&& ARM_HAVE__ARITH)) && !BYTES_BIG_ENDIAN"
{
rtx tmp = gen_reg_rtx (mode);
- emit_insn (gen_arm_vcmla (tmp, operands[1],
-operands[3], operands[2]));
+ emit_insn (gen_arm_vcmla (tmp, operands[3],
+operands[1], operands[2]));
emit_insn (gen_arm_vcmla (operands[0], tmp,
-operands[3], operands[2]));
+operands[1], operands[2]));
DONE;
})
--
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 8b0a396947cc8e7345f178b926128d7224fb218a..2b6ae67a7ec6bef505c2eaef0ec495d14c656495 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2859,9 +2859,9 @@ (define_expand "cmul3"
rtx res1 = gen_reg_rtx (mode);
rtx tmp = force_reg (mode, CONST0_RTX (mode));
emit_insn (gen_neon_vcmla (res1, tmp,
- operands[2], operands[1]));
+ operands[1], operands[2]));
emit_insn (gen_neon_vcmla (operands[0], res1,
- operands[2], operands[1]));
+ operands[1], operands[2]));
DONE;
})
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index e71d9b3811fde62159f5c21944fef9fe3f97b4bd..0940e987de53e191f4abdd248c654aed69f016f7 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -239,14 +239,14 @@ (define_expand "cmul3"
{
rtx tmp = force_reg (mode, CONST0_RTX (mode));
emit_insn (gen_arm_vcmla (res1, tmp,
- operands[2], operands[1]));
+ operands[1], operands[2]));
}
else
emit_insn (gen_arm_vcmla (res1, CONST0_RTX (mode),
- operands[2], operands[1]));
+ operands[1], operands[2]));
emit_insn (gen_arm_vcmla (operands[0], res1,
- operands[2], operands[1]));
+ operands[1], operands[2]));
DONE;
})
@@ -265,18 +265,18 @@ (define_expand "arm_vcmla"
;; remainder. Because of this, expand early.
(define_expand "cml4"
[(set (match_operand:VF 0 "register_opera
Re: [PATCH] [1/2] arm: Implement cortex-M return signing address codegen
Hi Richard,
thanks for reviewing! Some comments inline.
Richard Earnshaw writes:
> On 05/11/2021 08:52, Andrea Corallo via Gcc-patches wrote:
>> Hi all,
>> this patch enables address return signature and verification based
>> on
>> Armv8.1-M Pointer Authentication [1].
>> To sign the return address, we use the PAC R12, LR, SP instruction
>> upon function entry. This is signing LR using SP and storing the
>> result in R12. R12 will be pushed into the stack.
>> During function epilogue R12 will be popped and AUT R12, LR, SP will
>> be used to verify that the content of LR is still valid before return.
>> Here an example of PAC instrumented function prologue and epilogue:
>> pac r12, lr, sp
>> push{r3, r7, lr}
>> push{r12}
>> sub sp, sp, #4
>
> Which, as shown here, generates a stack which does not preserve 8-byte
> alignment.
I'm probably catastrofically wrong but shouldn't the stack be "all times
be aligned to a word boundary" [1]?
> Also, what's wrong with
>
> pac r12, lr, sp
> push{r3, r7, ip, lr}
> ?
AFAIK the AAPCS32 defines the Frame Record to be 2 consecutive 32-bit
values of LR and FP on the stack so that's the reason.
> Which saves 2 bytes in the prologue and ...
>
>> [...] function body
>> add sp, sp, #4
>> pop {r12}
>> pop {r3, r7, lr}
>> aut r12, lr, sp
>> bx lr
>
> pop {r3, r7, ip, lr}
> aut r12, lr, sp
> bx lr
>
> which saves 4 bytes in the epilogue (repeated for each instance of the
> epilogue).
>
>> The patch also takes care of generating a PACBTI instruction in
>> place
>> of the sequence BTI+PAC when Branch Target Identification is enabled
>> contextually.
>>
>
> What about variadic functions?
>
> What about functions where lr is live on entry (where it's used for
> passing the closure in nested functions)?
>
>> These two patches apply on top of Tejas series posted here [2].
>> Regressioned and arm-linux-gnu aarch64-linux-gnu bootstraped.
>> Best Regards
>>Andrea
>> [1]
>>
>> [2]
>>
>
>
> +static bool arm_pac_enabled_for_curr_function_p (void);
>
> I really don't like that name. There are a lot of functions with
> variations of 'current function' in the name already and this creates
> yet another variant. Something like
> arm_current_function_pac_enabled_p() would be preferable; or, if that
> really is too long, use 'current_func' which already has usage within
> the compiler.
Ack
> +(define_insn "pac_ip_lr_sp"
> + [(set (reg:DI IP_REGNUM)
> + (unspec:DI [(reg:DI SP_REGNUM) (reg:DI LR_REGNUM)]
> + UNSPEC_PAC_IP_LR_SP))]
> + ""
> + "pac\tr12, lr, sp")
> +
> +(define_insn "pacbti_ip_lr_sp"
> + [(set (reg:DI IP_REGNUM)
> + (unspec:DI [(reg:DI SP_REGNUM) (reg:DI LR_REGNUM)]
> + UNSPEC_PACBTI_IP_LR_SP))]
> + ""
> + "pacbti\tr12, lr, sp")
> +
> +(define_insn "aut_ip_lr_sp"
> + [(unspec:DI [(reg:DI IP_REGNUM) (reg:DI SP_REGNUM) (reg:DI LR_REGNUM)]
> + UNSPEC_AUT_IP_LR_SP)]
> + ""
> + "aut\tr12, lr, sp")
> +
>
> I think all these need a length attribute. Also, they should only be
> enabled for thumb2 (certainly not in Arm state).
> And when using explicit register names in an asm, prefix each name
> with '%|', just in case the assembler dialect has a register name
> prefix.
Ack
> The names are somewhat unweildy, can't we use something more usefully
> descriptive, like 'pac_nop', 'pacbti_nop' and 'aut_nop', since all
> these instructions are using the architectural NOP space.
>
> Finally, I think we need some more tests that cover the various
> frame-pointer flavours when used in combination with this feature and
> for various corners of the PCS.
Could you give some more indications of the falvors we what to have tests
for?
Thanks
Andrea
[1]
[PATCH] config.gcc: Obsolete m32c-rtems target
---
gcc/config.gcc | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index c8824367b13..fe93a72a16c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -252,6 +252,7 @@ case ${target} in
| cr16-*-*\
| hppa[12]*-*-hpux10* \
| hppa[12]*-*-hpux11* \
+ | m32c-*-rtems* \
)
if test "x$enable_obsolete" != xyes; then
echo "*** Configuration ${target} is obsolete." >&2
--
2.24.4
Re: [1/3 PATCH]middle-end vect: Simplify and extend the complex numbers validation routines.
Just a comment on the documentation:
Tamar Christina via Gcc-patches writes:
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index
> 9ec051e94e10cca9eec2773e1b8c01b74b6ea4db..60dc5b3ea6087c2824ad1467bc66e9cfebe9dcfc
> 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -6325,12 +6325,12 @@ Perform a vector multiply and accumulate that is
> semantically the same as
> a multiply and accumulate of complex numbers.
>
> @smallexample
> - complex TYPE c[N];
> - complex TYPE a[N];
> - complex TYPE b[N];
> + complex TYPE op0[N];
> + complex TYPE op1[N];
> + complex TYPE op2[N];
>for (int i = 0; i < N; i += 1)
> @{
> - c[i] += a[i] * b[i];
> + op2[i] += op1[i] * op2[i];
> @}
I think this should be:
op0[i] = op1[i] * op2[i] + op3[i];
since operand 0 is the output and operand 3 is the accumulator input.
Same idea for the others. For:
> @@ -6415,12 +6415,12 @@ Perform a vector multiply that is semantically the
> same as multiply of
> complex numbers.
>
> @smallexample
> - complex TYPE c[N];
> - complex TYPE a[N];
> - complex TYPE b[N];
> + complex TYPE op0[N];
> + complex TYPE op1[N];
> + complex TYPE op2[N];
>for (int i = 0; i < N; i += 1)
> @{
> - c[i] = a[i] * b[i];
> + op2[i] = op0[i] * op1[i];
…this I think it should be:
op0[i] = op1[i] * op2[i];
Thanks,
Richard
Re: [2/3 PATCH]AArch64 use canonical ordering for complex mul, fma and fms
Tamar Christina writes:
> Hi All,
>
> After the first patch in the series this updates the optabs to expect the
> canonical sequence.
>
> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
>
> Ok for master? and backport along with the first patch?
>
> Thanks,
> Tamar
>
> gcc/ChangeLog:
>
> PR tree-optimization/102819
> PR tree-optimization/103169
> * config/aarch64/aarch64-simd.md (cml4,
> cmul3): Use canonical order.
> * config/aarch64/aarch64-sve.md (cml4,
> cmul3): Likewise.
>
> --- inline copy of patch --
> diff --git a/gcc/config/aarch64/aarch64-simd.md
> b/gcc/config/aarch64/aarch64-simd.md
> index
> f95a7e1d91c97c9e981d75e71f0b49c02ef748ba..875896ee71324712c8034eeff9cfb5649f9b0e73
> 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -556,17 +556,17 @@ (define_insn "aarch64_fcmlaq_lane"
> ;; remainder. Because of this, expand early.
> (define_expand "cml4"
>[(set (match_operand:VHSDF 0 "register_operand")
> - (plus:VHSDF (match_operand:VHSDF 1 "register_operand")
> - (unspec:VHSDF [(match_operand:VHSDF 2 "register_operand")
> -(match_operand:VHSDF 3 "register_operand")]
> -FCMLA_OP)))]
> + (plus:VHSDF (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand")
> +(match_operand:VHSDF 2 "register_operand")]
> +FCMLA_OP)
> + (match_operand:VHSDF 3 "register_operand")))]
>"TARGET_COMPLEX && !BYTES_BIG_ENDIAN"
> {
>rtx tmp = gen_reg_rtx (mode);
> - emit_insn (gen_aarch64_fcmla (tmp, operands[1],
> - operands[3], operands[2]));
> + emit_insn (gen_aarch64_fcmla (tmp, operands[3],
> + operands[1], operands[2]));
>emit_insn (gen_aarch64_fcmla (operands[0], tmp,
> - operands[3], operands[2]));
> + operands[1], operands[2]));
>DONE;
> })
>
> @@ -583,9 +583,9 @@ (define_expand "cmul3"
>rtx tmp = force_reg (mode, CONST0_RTX (mode));
>rtx res1 = gen_reg_rtx (mode);
>emit_insn (gen_aarch64_fcmla (res1, tmp,
> - operands[2], operands[1]));
> + operands[1], operands[2]));
>emit_insn (gen_aarch64_fcmla (operands[0], res1,
> - operands[2], operands[1]));
> + operands[1], operands[2]));
This doesn't look right. Going from the documentation, patch 1 isn't
changing the operand order for CMUL: the conjugated operand (if there
is one) is still operand 2. The FCMLA sequences use the opposite order,
where the conjugated operand (if there is one) is operand 1. So I think
the reversal here is still needed.
Same for the multiplication operands in CML* above.
Thanks,
Richard
Re: [vect] Re-analyze all modes for epilogues
Made the suggested changes.
Regarding the name change to partial vectors, I agree in the name change
since that is the terminology we are using in the loop_vinfo members
too, but is there an actual difference between predication/masking and
partial vectors that I am missing?
OK for trunk?
gcc/ChangeLog:
* tree-vect-loop.c (vect_better_loop_vinfo_p): Round factors up
for epilogue costing.
(vect_analyze_loop): Re-analyze all modes for epilogues, unless
we are guaranteed that we can't
have partial vectors.
(genopinit.c) (partial_vectors_supported): Generate new function.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/masked_epilogue.c: New test.
diff --git a/gcc/genopinit.c b/gcc/genopinit.c
index
195ddf74fa2b7d89760622073dcec9d5d339a097..2bc7cdbf53337beae181afd7bb05b366ab068c6a
100644
--- a/gcc/genopinit.c
+++ b/gcc/genopinit.c
@@ -321,6 +321,7 @@ main (int argc, const char **argv)
" bool supports_vec_scatter_store_cached;\n"
"};\n"
"extern void init_all_optabs (struct target_optabs *);\n"
+ "extern bool partial_vectors_supported_p (void);\n"
"\n"
"extern struct target_optabs default_target_optabs;\n"
"extern struct target_optabs *this_fn_optabs;\n"
@@ -373,6 +374,33 @@ main (int argc, const char **argv)
fprintf (s_file, " ena[%u] = HAVE_%s;\n", i, p->name);
fprintf (s_file, "}\n\n");
+ fprintf (s_file,
+ "/* Returns TRUE if the target supports any of the partial vector\n"
+ " optabs: while_ult_optab, len_load_optab or len_store_optab,\n"
+ " for any mode. */\n"
+ "bool\npartial_vectors_supported_p (void)\n{\n");
+ bool any_match = false;
+ fprintf (s_file, "\treturn");
+ bool first = true;
+ for (i = 0; patterns.iterate (i, &p); ++i)
+{
+#define CMP_NAME(N) !strncmp (p->name, (N), strlen ((N)))
+ if (CMP_NAME("while_ult") || CMP_NAME ("len_load")
+ || CMP_NAME ("len_store"))
+ {
+ if (first)
+ fprintf (s_file, " HAVE_%s", p->name);
+ else
+ fprintf (s_file, " || HAVE_%s", p->name);
+ first = false;
+ any_match = true;
+ }
+}
+ if (!any_match)
+fprintf (s_file, " false");
+ fprintf (s_file, ";\n}\n");
+
+
/* Perform a binary search on a pre-encoded optab+mode*2. */
/* ??? Perhaps even better to generate a minimal perfect hash.
Using gperf directly is awkward since it's so geared to working
diff --git a/gcc/testsuite/gcc.target/aarch64/masked_epilogue.c
b/gcc/testsuite/gcc.target/aarch64/masked_epilogue.c
new file mode 100644
index
..286a7be236f337fee4c4650f42da72000855c5e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/masked_epilogue.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details
-march=armv8-a+sve -msve-vector-bits=scalable" } */
+
+void f(unsigned char y[restrict],
+ unsigned char x[restrict], int n) {
+ for (int i = 0; i < n; ++i)
+y[i] = (y[i] + x[i] + 1) >> 1;
+}
+
+/* { dg-final { scan-tree-dump {LOOP EPILOGUE VECTORIZED \(MODE=VNx} "vect" }
} */
diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c
index
a28bb6321d76b8222bc8cfdade151ca9b4dca406..5af98a36678ae61e99f93beb90920e2d0940c53a
100644
--- a/gcc/tree-vect-loop.c
+++ b/gcc/tree-vect-loop.c
@@ -2824,11 +2824,13 @@ vect_better_loop_vinfo_p (loop_vec_info new_loop_vinfo,
{
unsigned HOST_WIDE_INT main_vf_max
= estimated_poly_value (main_poly_vf, POLY_VALUE_MAX);
+ unsigned HOST_WIDE_INT old_vf_max
+ = estimated_poly_value (old_vf, POLY_VALUE_MAX);
+ unsigned HOST_WIDE_INT new_vf_max
+ = estimated_poly_value (new_vf, POLY_VALUE_MAX);
- old_factor = main_vf_max / estimated_poly_value (old_vf,
- POLY_VALUE_MAX);
- new_factor = main_vf_max / estimated_poly_value (new_vf,
- POLY_VALUE_MAX);
+ old_factor = CEIL (main_vf_max, old_vf_max);
+ new_factor = CEIL (main_vf_max, new_vf_max);
/* If the loop is not using partial vectors then it will iterate one
time less than one that does. It is safe to subtract one here,
@@ -3069,8 +3071,6 @@ vect_analyze_loop (class loop *loop, vec_info_shared
*shared)
machine_mode autodetected_vector_mode = VOIDmode;
opt_loop_vec_info first_loop_vinfo = opt_loop_vec_info::success (NULL);
unsigned int mode_i = 0;
- unsigned int first_loop_i = 0;
- unsigned int first_loop_next_i = 0;
unsigned HOST_WIDE_INT simdlen = loop->simdlen;
/* First determine the main loop vectorization mode, either the first
@@ -3079,7 +3079,6 @@ vect_analyze_loop (class loop *loop, vec_info_shared
*shared)
lowest cost if pick_lowest_cost_p. */
while (1)
{
- unsigned
[COMMITTED] rs6000: Fix fake vec_promote overload
Hi! rs6000-overload.def defines one instance of vec_promote so that it can be registered with the front end. Actual expansion of the vec_promote overload is done with special-case code in rs6000-c.c. During another cleanup, I observed that the fake instance has the wrong number of arguments. Fix that. This has no effect other than to avoid confusion. Bootstrapped and tested on powerpc64le-linux-gnu, committed as obvious in r12-6043. Thanks! Bill diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def index 531a4fcd1af..2b2853918c0 100644 --- a/gcc/config/rs6000/rs6000-overload.def +++ b/gcc/config/rs6000/rs6000-overload.def @@ -3021,7 +3021,7 @@ ; is replaced by a constructor. The single overload here causes ; __builtin_vec_promote to be registered with the front end so that can happen. [VEC_PROMOTE, vec_promote, __builtin_vec_promote] - vsi __builtin_vec_promote (vsi); + vsi __builtin_vec_promote (vsi, const int); ABS_V4SI PROMOTE_FAKERY [VEC_RE, vec_re, __builtin_vec_re]
Re: [2/3 PATCH]AArch64 use canonical ordering for complex mul, fma and fms
Richard Sandiford writes:
> Tamar Christina writes:
>> Hi All,
>>
>> After the first patch in the series this updates the optabs to expect the
>> canonical sequence.
>>
>> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
>>
>> Ok for master? and backport along with the first patch?
>>
>> Thanks,
>> Tamar
>>
>> gcc/ChangeLog:
>>
>> PR tree-optimization/102819
>> PR tree-optimization/103169
>> * config/aarch64/aarch64-simd.md (cml4,
>> cmul3): Use canonical order.
>> * config/aarch64/aarch64-sve.md (cml4,
>> cmul3): Likewise.
>>
>> --- inline copy of patch --
>> diff --git a/gcc/config/aarch64/aarch64-simd.md
>> b/gcc/config/aarch64/aarch64-simd.md
>> index
>> f95a7e1d91c97c9e981d75e71f0b49c02ef748ba..875896ee71324712c8034eeff9cfb5649f9b0e73
>> 100644
>> --- a/gcc/config/aarch64/aarch64-simd.md
>> +++ b/gcc/config/aarch64/aarch64-simd.md
>> @@ -556,17 +556,17 @@ (define_insn "aarch64_fcmlaq_lane"
>> ;; remainder. Because of this, expand early.
>> (define_expand "cml4"
>>[(set (match_operand:VHSDF 0 "register_operand")
>> -(plus:VHSDF (match_operand:VHSDF 1 "register_operand")
>> -(unspec:VHSDF [(match_operand:VHSDF 2 "register_operand")
>> - (match_operand:VHSDF 3 "register_operand")]
>> - FCMLA_OP)))]
>> +(plus:VHSDF (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand")
>> + (match_operand:VHSDF 2 "register_operand")]
>> + FCMLA_OP)
>> +(match_operand:VHSDF 3 "register_operand")))]
>>"TARGET_COMPLEX && !BYTES_BIG_ENDIAN"
>> {
>>rtx tmp = gen_reg_rtx (mode);
>> - emit_insn (gen_aarch64_fcmla (tmp, operands[1],
>> - operands[3], operands[2]));
>> + emit_insn (gen_aarch64_fcmla (tmp, operands[3],
>> + operands[1], operands[2]));
>>emit_insn (gen_aarch64_fcmla (operands[0], tmp,
>> - operands[3], operands[2]));
>> + operands[1], operands[2]));
>>DONE;
>> })
>>
>> @@ -583,9 +583,9 @@ (define_expand "cmul3"
>>rtx tmp = force_reg (mode, CONST0_RTX (mode));
>>rtx res1 = gen_reg_rtx (mode);
>>emit_insn (gen_aarch64_fcmla (res1, tmp,
>> - operands[2], operands[1]));
>> + operands[1], operands[2]));
>>emit_insn (gen_aarch64_fcmla (operands[0], res1,
>> - operands[2], operands[1]));
>> + operands[1], operands[2]));
>
> This doesn't look right. Going from the documentation, patch 1 isn't
> changing the operand order for CMUL: the conjugated operand (if there
> is one) is still operand 2. The FCMLA sequences use the opposite order,
> where the conjugated operand (if there is one) is operand 1. So I think
I meant “the first multiplication operand” rather than “operand 1” here.
> the reversal here is still needed.
>
> Same for the multiplication operands in CML* above.
>
> Thanks,
> Richard
Re: [PATCH] [1/2] arm: Implement cortex-M return signing address codegen
On 17/12/2021 15:52, Andrea Corallo wrote:
Hi Richard,
thanks for reviewing! Some comments inline.
Richard Earnshaw writes:
On 05/11/2021 08:52, Andrea Corallo via Gcc-patches wrote:
Hi all,
this patch enables address return signature and verification based
on
Armv8.1-M Pointer Authentication [1].
To sign the return address, we use the PAC R12, LR, SP instruction
upon function entry. This is signing LR using SP and storing the
result in R12. R12 will be pushed into the stack.
During function epilogue R12 will be popped and AUT R12, LR, SP will
be used to verify that the content of LR is still valid before return.
Here an example of PAC instrumented function prologue and epilogue:
pac r12, lr, sp
push{r3, r7, lr}
push{r12}
sub sp, sp, #4
Which, as shown here, generates a stack which does not preserve 8-byte
alignment.
I'm probably catastrofically wrong but shouldn't the stack be "all times
be aligned to a word boundary" [1]?
At a function boundary it must be 8-byte aligned (same reference). I
don't think GCC really optimizes leaf functions to permit sub 8-byte
alignment, but since you omitted the body of your function I might be
wrong in this case.
Also, what's wrong with
pac r12, lr, sp
push{r3, r7, ip, lr}
?
AFAIK the AAPCS32 defines the Frame Record to be 2 consecutive 32-bit
values of LR and FP on the stack so that's the reason.
GCC does not currently support AAPCS frame chains as that's a relatively
new feature in the AAPCS; so it's not something you need to be concerned
about right now. The AAPCS frame chain uses R11 as the frame-chain
register anyway. However, you are right that this does affect
-mtpcs-frame and will become relevant when we do add support for AAPCS
frame chains.
Which saves 2 bytes in the prologue and ...
[...] function body
add sp, sp, #4
pop {r12}
pop {r3, r7, lr}
aut r12, lr, sp
bx lr
pop {r3, r7, ip, lr}
aut r12, lr, sp
bx lr
which saves 4 bytes in the epilogue (repeated for each instance of the
epilogue).
The patch also takes care of generating a PACBTI instruction in
place
of the sequence BTI+PAC when Branch Target Identification is enabled
contextually.
What about variadic functions?
What about functions where lr is live on entry (where it's used for
passing the closure in nested functions)?
These two patches apply on top of Tejas series posted here [2].
Regressioned and arm-linux-gnu aarch64-linux-gnu bootstraped.
Best Regards
Andrea
[1]
[2]
+static bool arm_pac_enabled_for_curr_function_p (void);
I really don't like that name. There are a lot of functions with
variations of 'current function' in the name already and this creates
yet another variant. Something like
arm_current_function_pac_enabled_p() would be preferable; or, if that
really is too long, use 'current_func' which already has usage within
the compiler.
Ack
+(define_insn "pac_ip_lr_sp"
+ [(set (reg:DI IP_REGNUM)
+ (unspec:DI [(reg:DI SP_REGNUM) (reg:DI LR_REGNUM)]
+ UNSPEC_PAC_IP_LR_SP))]
+ ""
+ "pac\tr12, lr, sp")
+
+(define_insn "pacbti_ip_lr_sp"
+ [(set (reg:DI IP_REGNUM)
+ (unspec:DI [(reg:DI SP_REGNUM) (reg:DI LR_REGNUM)]
+ UNSPEC_PACBTI_IP_LR_SP))]
+ ""
+ "pacbti\tr12, lr, sp")
+
+(define_insn "aut_ip_lr_sp"
+ [(unspec:DI [(reg:DI IP_REGNUM) (reg:DI SP_REGNUM) (reg:DI LR_REGNUM)]
+ UNSPEC_AUT_IP_LR_SP)]
+ ""
+ "aut\tr12, lr, sp")
+
I think all these need a length attribute. Also, they should only be
enabled for thumb2 (certainly not in Arm state).
And when using explicit register names in an asm, prefix each name
with '%|', just in case the assembler dialect has a register name
prefix.
Ack
The names are somewhat unweildy, can't we use something more usefully
descriptive, like 'pac_nop', 'pacbti_nop' and 'aut_nop', since all
these instructions are using the architectural NOP space.
Finally, I think we need some more tests that cover the various
frame-pointer flavours when used in combination with this feature and
for various corners of the PCS.
Could you give some more indications of the falvors we what to have tests
for?
I'm thinking mostly about test cases for the additional situations I've
described above. But there's also testing that the code does the right
thing with -mtpcs-frame.
It might be that we want to declare -mtpcs-frame and branch protection
incompatible, which would save a lot of complicated validation. That's
probably acceptable because -mtpcs-frame is essentially deprecated
anyway (and will hopefully be supe
Re: [PATCH] coroutines, c++: Find lambda-ness from the ramp function [PR 96517].
Hi Jason, > On 5 Nov 2021, at 21:53, Jason Merrill wrote: > > On 11/5/21 17:16, Iain Sandoe wrote: >> Hi Jason, >>> On 5 Nov 2021, at 20:50, Jason Merrill via Gcc-patches >>> wrote: >>> >>> On 11/5/21 12:01, Iain Sandoe wrote: +|| (DECL_DECLARES_FUNCTION_P (DECL_CONTEXT (decl)) +&& DECL_COROUTINE_P (DECL_CONTEXT (decl)) +&& DECL_RAMP_FN (DECL_CONTEXT (decl)) +&& LAMBDA_FUNCTION_P (DECL_RAMP_FN (DECL_CONTEXT (decl)); >>> >>> Are there other places that want to look through DECL_RAMP_FN like this, >>> such that this should be factored into e.g. >>> >>> LAMBDA_FUNCTION_P (non_coroutine (DECL_CONTEXT (decl))) >> At present, I am not aware of another use (there are none in my WIP fixes) - >> but that stack of macros is a bit of a mouthful - maybe a function would be >> neater anyway. >> non_coroutine () doesn’t convey its meaning to me - what we are trying to >> say “get me the ramp context” but that’s very detailed. > > I figured what we want is the user-written function corresponding to the > argument. Hmm, the coroutine helpers don't use DECL_ABSTRACT_ORIGIN, do they? You fixed this PR with r12-5255-gdaa9c6b015, so my patch is not needed. I pushed the testcase as r12-6044-g39d2ec41509e. thanks Iain
Re: [PATCH] [1/2] arm: Implement cortex-M return signing address codegen
Richard Earnshaw writes:
> On 17/12/2021 15:52, Andrea Corallo wrote:
>> Hi Richard,
>> thanks for reviewing! Some comments inline.
>> Richard Earnshaw writes:
>>> On 05/11/2021 08:52, Andrea Corallo via Gcc-patches wrote:
Hi all,
this patch enables address return signature and verification based
on
Armv8.1-M Pointer Authentication [1].
To sign the return address, we use the PAC R12, LR, SP instruction
upon function entry. This is signing LR using SP and storing the
result in R12. R12 will be pushed into the stack.
During function epilogue R12 will be popped and AUT R12, LR, SP will
be used to verify that the content of LR is still valid before return.
Here an example of PAC instrumented function prologue and epilogue:
pac r12, lr, sp
push{r3, r7, lr}
push{r12}
sub sp, sp, #4
>>>
>>> Which, as shown here, generates a stack which does not preserve 8-byte
>>> alignment.
>> I'm probably catastrofically wrong but shouldn't the stack be "all
>> times
>> be aligned to a word boundary" [1]?
>
> At a function boundary it must be 8-byte aligned (same reference). I
> don't think GCC really optimizes leaf functions to permit sub 8-byte
> alignment, but since you omitted the body of your function I might be
> wrong in this case.
I see thanks.
>>
>>> Also, what's wrong with
>>>
>>> pac r12, lr, sp
>>> push{r3, r7, ip, lr}
>>> ?
>> AFAIK the AAPCS32 defines the Frame Record to be 2 consecutive
>> 32-bit
>> values of LR and FP on the stack so that's the reason.
>
> GCC does not currently support AAPCS frame chains as that's a
> relatively new feature in the AAPCS; so it's not something you need to
> be concerned about right now. The AAPCS frame chain uses R11 as the
> frame-chain register anyway. However, you are right that this does
> affect -mtpcs-frame and will become relevant when we do add support
> for AAPCS frame chains.
Do you think would be better to go for the "push {r3, r7, ip, lr}"
solution even if we decide -mtpcs-frame is not compatible with pac
instrumentation or we want to stay with the proposed approach for future
compatibility?
Thanks
Andrea
[PATCH 1/2] rs6000: Redo darn (PR103624)
The builtins now all return "long". The patterns have :GPR as the
output mode, so they can be 32-bit as well (the instruction makes sense
in 32 bit just fine). The builtins expand to the DImode version
normally, but to the SImode if {32bit} is true.
2021-12-17 Segher Boessenkool
PR target/103624
* config/rs6000/rs6000-builtins.def (__builtin_darn): Expand to
darn_64_di. Add {32bit} attribute. Return long.
(__builtin_darn_32): Expand to darn_32_di. Add {32bit} attribute.
Return long.
(__builtin_darn_raw): Expand to darn_raw_di. Add {32bit} attribute.
Return long.
* config/rs6000/rs6000-call.c (rs6000_expand_builtin): Expand the darn
builtins to the _si variants for -m32.
* config/rs6000/rs6000.md (UNSPECV_DARN_32, UNSPECV_DARN_RAW): Delete.
(UNSPECV_DARN): Update comment.
(darn_32, darn_raw, darn): Delete.
(darn_32_, darn_64_, darn_raw_ for GPR): New.
(@darn for GPR): New.
---
gcc/config/rs6000/rs6000-builtins.def | 12 -
gcc/config/rs6000/rs6000-call.c | 6 +
gcc/config/rs6000/rs6000.md | 47 +--
3 files changed, 40 insertions(+), 25 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 45ce160bd421..3ad5a135eaec 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2798,14 +2798,14 @@
; Miscellaneous P9 functions
[power9]
- signed long long __builtin_darn ();
-DARN darn {}
+ signed long __builtin_darn ();
+DARN darn_64_di {32bit}
- signed int __builtin_darn_32 ();
-DARN_32 darn_32 {}
+ signed long __builtin_darn_32 ();
+DARN_32 darn_32_di {32bit}
- signed long long __builtin_darn_raw ();
-DARN_RAW darn_raw {}
+ signed long __builtin_darn_raw ();
+DARN_RAW darn_raw_di {32bit}
const signed int __builtin_dtstsfi_eq_dd (const int<6>, _Decimal64);
TSTSFI_EQ_DD dfptstsfi_eq_dd {}
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index b98f4a4c97f7..cc55174c6b72 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -5631,6 +5631,12 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
subtarget */,
icode = CODE_FOR_rs6000_mftb_si;
else if (fcode == RS6000_BIF_BPERMD)
icode = CODE_FOR_bpermd_si;
+ else if (fcode == RS6000_BIF_DARN)
+ icode = CODE_FOR_darn_64_si;
+ else if (fcode == RS6000_BIF_DARN_32)
+ icode = CODE_FOR_darn_32_si;
+ else if (fcode == RS6000_BIF_DARN_RAW)
+ icode = CODE_FOR_darn_raw_si;
else
gcc_unreachable ();
}
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4122acb98cfd..9be484c7cf83 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -172,9 +172,7 @@ (define_c_enum "unspecv"
UNSPECV_EH_RR ; eh_reg_restore
UNSPECV_ISYNC ; isync instruction
UNSPECV_MFTB; move from time base
- UNSPECV_DARN; darn 1 (deliver a random number)
- UNSPECV_DARN_32 ; darn 2
- UNSPECV_DARN_RAW; darn 0
+ UNSPECV_DARN; darn (deliver a random number)
UNSPECV_NLGR; non-local goto receiver
UNSPECV_MFFS; Move from FPSCR
UNSPECV_MFFSL ; Move from FPSCR light instruction version
@@ -15065,25 +15063,36 @@ (define_insn "*cmp_hw"
;; Miscellaneous ISA 3.0 (power9) instructions
-(define_insn "darn_32"
- [(set (match_operand:SI 0 "register_operand" "=r")
-(unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))]
+(define_expand "darn_32_"
+ [(use (match_operand:GPR 0 "register_operand"))]
"TARGET_P9_MISC"
- "darn %0,0"
- [(set_attr "type" "integer")])
+{
+ emit_insn (gen_darn (mode, operands[0], const0_rtx));
+ DONE;
+})
-(define_insn "darn_raw"
- [(set (match_operand:DI 0 "register_operand" "=r")
-(unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))]
- "TARGET_P9_MISC && TARGET_64BIT"
- "darn %0,2"
- [(set_attr "type" "integer")])
+(define_expand "darn_64_"
+ [(use (match_operand:GPR 0 "register_operand"))]
+ "TARGET_P9_MISC"
+{
+ emit_insn (gen_darn (mode, operands[0], const1_rtx));
+ DONE;
+})
-(define_insn "darn"
- [(set (match_operand:DI 0 "register_operand" "=r")
-(unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))]
- "TARGET_P9_MISC && TARGET_64BIT"
- "darn %0,1"
+(define_expand "darn_raw_"
+ [(use (match_operand:GPR 0 "register_operand"))]
+ "TARGET_P9_MISC"
+{
+ emit_insn (gen_darn (mode, operands[0], const2_rtx));
+ DONE;
+})
+
+(define_insn "@darn"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+(unspec_volatile:GPR [(match_operand 1 "const_int_operand" "n")]
+UNSPECV_DARN))]
+ "TARGET_P9_MI
[PATCH 2/2] rs6000: Update darn testcases
Make the darn testcases work (and be tested) in 32-bit mode as well.
They used to ICE, but they no longer do.
2021-12-17 Segher Boessenkool
gcc/testsuite/
PR target/103624
* gcc.target/powerpc/darn-0.c: Remove target clause.
* gcc.target/powerpc/darn-1.c: Remove target clause. Remove lp64
requirement. Change return type to long.
* gcc.target/powerpc/darn-2.c: Ditto.
* gcc.target/powerpc/darn-3.c: Remove target clause.
---
gcc/testsuite/gcc.target/powerpc/darn-0.c | 2 +-
gcc/testsuite/gcc.target/powerpc/darn-1.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/darn-2.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/darn-3.c | 2 +-
4 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/darn-0.c
b/gcc/testsuite/gcc.target/powerpc/darn-0.c
index f446f494b06d..64d98f5f91d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/darn-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/darn-0.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "" { powerpc*-*-aix* } } */
/* { dg-options "-mdejagnu-cpu=power9" } */
diff --git a/gcc/testsuite/gcc.target/powerpc/darn-1.c
b/gcc/testsuite/gcc.target/powerpc/darn-1.c
index 0938718a5ad6..f483a89862d0 100644
--- a/gcc/testsuite/gcc.target/powerpc/darn-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/darn-1.c
@@ -1,12 +1,11 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-require-effective-target lp64 } */
/* { dg-skip-if "" { powerpc*-*-aix* } } */
/* { dg-options "-mdejagnu-cpu=power9" } */
#include
-long long get_conditioned_random ()
+long get_conditioned_random ()
{
return __builtin_darn ();
}
diff --git a/gcc/testsuite/gcc.target/powerpc/darn-2.c
b/gcc/testsuite/gcc.target/powerpc/darn-2.c
index 64e44b244c4b..56a9ffb677b4 100644
--- a/gcc/testsuite/gcc.target/powerpc/darn-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/darn-2.c
@@ -1,12 +1,11 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-require-effective-target lp64 } */
/* { dg-skip-if "" { powerpc*-*-aix* } } */
/* { dg-options "-mdejagnu-cpu=power9" } */
#include
-long long get_raw_random ()
+long get_raw_random ()
{
return __builtin_darn_raw ();
}
diff --git a/gcc/testsuite/gcc.target/powerpc/darn-3.c
b/gcc/testsuite/gcc.target/powerpc/darn-3.c
index 477901fde70d..4c68fad80d5d 100644
--- a/gcc/testsuite/gcc.target/powerpc/darn-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/darn-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile } */
/* { dg-skip-if "" { powerpc*-*-aix* } } */
/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
--
1.8.3.1
[PATCH v2] c++: Improve diagnostic for class tmpl/class redecl [PR103749]
On Thu, Dec 16, 2021 at 08:13:01PM -0500, Jason Merrill wrote:
> On 12/16/21 17:36, Marek Polacek wrote:
> > + if (DECL_CLASS_TEMPLATE_P (decl)
> > + && !template_header_p
> > + && how == TAG_how::CURRENT_ONLY)
> > +{
> > + error ("%qD was declared as template but no template header
> > provided",
> > +name);
>
> Maybe "class template %qD redeclared as non-template" ?
>
> OK with that change.
Thanks. For the record:
Tested x86_64-pc-linux-gnu, applying to trunk.
-- >8 --
For code like
template
struct bar;
struct bar {
int baz;
};
bar var;
we emit a fairly misleading and unwieldy diagnostic:
~
$ g++ -c u.cc
u.cc:6:8: error: template argument required for 'struct bar'
6 | struct bar {
|^~~
u.cc:10:5: error: class template argument deduction failed:
10 | bar var;
| ^~~
u.cc:10:5: error: no matching function for call to 'bar()'
u.cc:3:17: note: candidate: 'template bar()-> bar<
>'
3 | friend struct bar;
| ^~~
u.cc:3:17: note: template argument deduction/substitution failed:
u.cc:10:5: note: couldn't deduce template parameter ''
10 | bar var;
| ^~~
u.cc:3:17: note: candidate: 'template bar(bar<
>)-> bar< >'
3 | friend struct bar;
| ^~~
u.cc:3:17: note: template argument deduction/substitution failed:
u.cc:10:5: note: candidate expects 1 argument, 0 provided
10 | bar var;
| ^~~
~
but with this patch we get:
~
z.C:4:10: error: class template 'bar' redeclared as non-template
4 | struct bar {
| ^~~
z.C:2:10: note: previous declaration here
2 | struct bar;
| ^~~
z.C:8:7: error: 'bar<...auto...> var' has incomplete type
8 | bar var;
| ^~~
~
which is clearer about what the problem is.
I thought it'd be nice to avoid printing the messages about failed CTAD,
too. To that end, I'm using CLASSTYPE_ERRONEOUS to suppress CTAD. Not
sure if that's entirely kosher.
The other direction (first a non-template class declaration followed by
a class template definition) we handle quite well:
~
z.C:11:8: error: 'bar' is not a template
11 | struct bar {};
|^~~
z.C:8:8: note: previous declaration here
8 | struct bar;
|^~~
~
PR c++/103749
gcc/cp/ChangeLog:
* decl.c (lookup_and_check_tag): Give an error when a class was
declared as template but no template header has been provided.
* pt.c (do_class_deduction): Don't deduce CLASSTYPE_ERRONEOUS
types.
gcc/testsuite/ChangeLog:
* g++.dg/template/redecl4.C: Adjust dg-error.
* g++.dg/diagnostic/redeclaration-2.C: New test.
---
gcc/cp/decl.c | 10 ++
gcc/cp/pt.c | 7 +++
.../g++.dg/diagnostic/redeclaration-2.C | 19 +++
gcc/testsuite/g++.dg/template/redecl4.C | 2 +-
4 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/g++.dg/diagnostic/redeclaration-2.C
diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c
index 7ca8770bd02..982fca8983d 100644
--- a/gcc/cp/decl.c
+++ b/gcc/cp/decl.c
@@ -15438,6 +15438,16 @@ lookup_and_check_tag (enum tag_types tag_code, tree
name,
return error_mark_node;
}
+ if (DECL_CLASS_TEMPLATE_P (decl)
+ && !template_header_p
+ && how == TAG_how::CURRENT_ONLY)
+{
+ error ("class template %qD redeclared as non-template", name);
+ inform (location_of (decl), "previous declaration here");
+ CLASSTYPE_ERRONEOUS (TREE_TYPE (decl)) = true;
+ return error_mark_node;
+}
+
if (DECL_CLASS_TEMPLATE_P (decl)
/* If scope is TAG_how::CURRENT_ONLY we're defining a class,
so ignore a template template parameter. */
diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c
index 18c6f118ae6..4f0ae6d5851 100644
--- a/gcc/cp/pt.c
+++ b/gcc/cp/pt.c
@@ -29601,6 +29601,13 @@ do_class_deduction (tree ptype, tree tmpl, tree init,
if (DECL_TEMPLATE_TEMPLATE_PARM_P (tmpl))
return ptype;
+ /* If the class was erroneous, don't try to deduce, because that
+ can generate a lot of diagnostic. */
+ if (TREE_TYPE (tmpl)
+ && TYPE_LANG_SPECIFIC (TREE_TYPE (tmpl))
+ && CLASSTYPE_ERRONEOUS (TREE_TYPE (tmpl)))
+return ptype;
+
/* Wait until the enclosing scope is non-dependent. */
if (DECL_CLASS_SCOPE_P (tmpl)
&& dependent_type_p (DECL_CONTEXT (tmpl)))
diff --git a/gcc/testsuite/g++.dg/diagnostic/redeclaration-2.C
b/gcc/testsuite/g++.dg/diagnostic/redeclaration-2.C
new file mode 100644
index 000..4423e12b0b1
--- /dev/null
+++ b/gcc
Re: [PATCH] Add -mdejagnu-cpu=power9 to dg-options for pr97142.c
> On 17 Dec 2021, at 16:17, Segher Boessenkool
> wrote:
>
>> In this instance, it's simple enough to be quoted directly:
>
> You may want to look into git send-email :-)
Eh, indeed.
>> --- a/gcc/testsuite/gcc.target/powerpc/pr97142.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/pr97142.c
>> @@ -1,5 +1,5 @@
>> /* { dg-do compile } */
>> -/* { dg-options "-Ofast" } */
>> +/* { dg-options "-Ofast -mdejagnu-cpu=power9" } */
>>
>> I'll change to power7 and commit.
>
> Okay for trunk like that. Thanks!
Sure, done. Thanks for your prompt feedback.
Cheers,
Olivier
[PATCH v3] attribs: Fix wrong error with -Wno-attribute=A::b [PR103649]
On Thu, Dec 16, 2021 at 08:06:43PM -0500, Jason Merrill wrote:
> On 12/16/21 19:52, Marek Polacek wrote:
> > --- /dev/null
> > +++ b/gcc/testsuite/c-c++-common/Wno-attributes-6.c
> > @@ -0,0 +1,14 @@
> > +/* PR c/103649 */
> > +/* { dg-do compile { target { c || c++11 } } } */
> > +/* { dg-additional-options "-Wno-attributes=foo::bar" } */
> > +/* { dg-additional-options "-Wno-attributes=baz::" } */
> > +/* { dg-additional-options "-Wno-attributes=womp::womp" } */
> > +/* { dg-additional-options "-Wno-attributes=qux::foo" } */
> > +
> > +[[foo::bar(1, 2)]]; /* { dg-warning "attribute ignored" } */
> > +[[baz::bar(1, 2)]]; /* { dg-warning "attribute ignored" } */
> > +[[foo::bar(1, 2)]] void f1();
> > +[[baz::bar(1, 2)]] void f2();
> > +[[qux::foo({t})]] void f3();
> > +[[womp::womp (another::directive (threadprivate (t)))]] void f4();
> > +[[womp::womp (another::directive (threadprivate (t)))]]; /* { dg-warning
> > "attribute ignored" } */
>
> If we're ignoring these attributes, we should ignore them everywhere;
> perhaps using them for an attribute-declaration is meaningful in another
> compiler.
Sounds good. Reminds me of P177, Portable assumptions...
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?
-- >8 --
My patch to implement -Wno-attribute=A::b caused a bogus error when
parsing
[[foo::bar(1, 2)]];
when -Wno-attributes=foo::bar was specified on the command line, because
when we create a fake foo::bar attribute and insert it into our attribute
table, it is created with max_length == 0 which doesn't allow any args.
That is wrong -- we know nothing about the attribute, so we shouldn't
require any specific number of arguments. And since unknown attributes
can be rather complex (see for example omp::{directive,sequence}), we
must skip parsing their arguments. To that end, I'm using max_length
with value -2.
Also let's not warn about things like
[[vendor::assume(true)]];
because they may have some meaning (this is reminiscent of C++ Portable
Assumptions).
PR c/103649
gcc/ChangeLog:
* attribs.c (handle_ignored_attributes_option): Create the fake
attribute with max_length == -2.
(attribute_ignored_p): New function.
* attribs.h (attribute_ignored_p): Declare.
* tree-core.h (struct attribute_spec): Document that max_length
can be -2.
gcc/c/ChangeLog:
* c-decl.c (c_warn_unused_attributes): Don't warn for
attribute_ignored_p.
* c-parser.c (c_parser_std_attribute): Skip parsing of the attribute
arguments when max_length == -2.
gcc/cp/ChangeLog:
* parser.c (cp_parser_declaration): Don't warn for attribute_ignored_p.
(cp_parser_std_attribute): Skip parsing of the attribute
arguments when max_length == -2.
gcc/testsuite/ChangeLog:
* c-c++-common/Wno-attributes-6.c: New test.
---
gcc/attribs.c | 20 ++-
gcc/attribs.h | 1 +
gcc/c/c-decl.c| 2 +-
gcc/c/c-parser.c | 4 +++-
gcc/cp/parser.c | 6 --
gcc/testsuite/c-c++-common/Wno-attributes-6.c | 16 +++
gcc/tree-core.h | 4 +++-
7 files changed, 47 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/c-c++-common/Wno-attributes-6.c
diff --git a/gcc/attribs.c b/gcc/attribs.c
index 29703e75fba..82527869093 100644
--- a/gcc/attribs.c
+++ b/gcc/attribs.c
@@ -304,7 +304,7 @@ handle_ignored_attributes_option (vec *v)
We can't free it here, so squirrel away the pointers. */
attribute_spec *table = new attribute_spec[2];
ignored_attributes_table.safe_push (table);
- table[0] = { attr, 0, 0, false, false, false, false, nullptr, nullptr };
+ table[0] = { attr, 0, -2, false, false, false, false, nullptr, nullptr };
table[1] = { nullptr, 0, 0, false, false, false, false, nullptr,
nullptr };
register_scoped_attributes (table, IDENTIFIER_POINTER (vendor_id),
!attr);
@@ -569,6 +569,24 @@ attr_namespace_ignored_p (tree ns)
return r && r->ignored_p;
}
+/* Return true if the attribute ATTR should not be warned about. */
+
+bool
+attribute_ignored_p (tree attr)
+{
+ if (!cxx11_attribute_p (attr))
+return false;
+ if (tree ns = get_attribute_namespace (attr))
+{
+ if (attr_namespace_ignored_p (ns))
+ return true;
+ const attribute_spec *as = lookup_attribute_spec (TREE_PURPOSE (attr));
+ if (as && as->max_length == -2)
+ return true;
+}
+ return false;
+}
+
/* Process the attributes listed in ATTRIBUTES and install them in *NODE,
which is either a DECL (including a TYPE_DECL) or a TYPE. If a DECL,
it should be modified in place; if a TYPE, a copy should be created
diff --git a/gcc/attribs.h b/gcc/attribs.h
index f5899d83c0b..d3449d5bd1d 100644
--- a/gcc/attribs.h
+++ b/gcc/attrib
Re: [PATCH 1/2] rs6000: Redo darn (PR103624)
Hi!
On 12/17/21 11:36 AM, Segher Boessenkool wrote:
> The builtins now all return "long". The patterns have :GPR as the
> output mode, so they can be 32-bit as well (the instruction makes sense
> in 32 bit just fine). The builtins expand to the DImode version
> normally, but to the SImode if {32bit} is true.
>
> 2021-12-17 Segher Boessenkool
>
> PR target/103624
> * config/rs6000/rs6000-builtins.def (__builtin_darn): Expand to
> darn_64_di. Add {32bit} attribute. Return long.
> (__builtin_darn_32): Expand to darn_32_di. Add {32bit} attribute.
> Return long.
> (__builtin_darn_raw): Expand to darn_raw_di. Add {32bit} attribute.
> Return long.
> * config/rs6000/rs6000-call.c (rs6000_expand_builtin): Expand the darn
> builtins to the _si variants for -m32.
> * config/rs6000/rs6000.md (UNSPECV_DARN_32, UNSPECV_DARN_RAW): Delete.
> (UNSPECV_DARN): Update comment.
> (darn_32, darn_raw, darn): Delete.
> (darn_32_, darn_64_, darn_raw_ for GPR): New.
> (@darn for GPR): New.
Patch LGTM. Thanks for doing the legwork on this!
Bill
>
> ---
> gcc/config/rs6000/rs6000-builtins.def | 12 -
> gcc/config/rs6000/rs6000-call.c | 6 +
> gcc/config/rs6000/rs6000.md | 47
> +--
> 3 files changed, 40 insertions(+), 25 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000-builtins.def
> b/gcc/config/rs6000/rs6000-builtins.def
> index 45ce160bd421..3ad5a135eaec 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -2798,14 +2798,14 @@
>
> ; Miscellaneous P9 functions
> [power9]
> - signed long long __builtin_darn ();
> -DARN darn {}
> + signed long __builtin_darn ();
> +DARN darn_64_di {32bit}
>
> - signed int __builtin_darn_32 ();
> -DARN_32 darn_32 {}
> + signed long __builtin_darn_32 ();
> +DARN_32 darn_32_di {32bit}
>
> - signed long long __builtin_darn_raw ();
> -DARN_RAW darn_raw {}
> + signed long __builtin_darn_raw ();
> +DARN_RAW darn_raw_di {32bit}
>
>const signed int __builtin_dtstsfi_eq_dd (const int<6>, _Decimal64);
> TSTSFI_EQ_DD dfptstsfi_eq_dd {}
> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
> index b98f4a4c97f7..cc55174c6b72 100644
> --- a/gcc/config/rs6000/rs6000-call.c
> +++ b/gcc/config/rs6000/rs6000-call.c
> @@ -5631,6 +5631,12 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /*
> subtarget */,
> icode = CODE_FOR_rs6000_mftb_si;
>else if (fcode == RS6000_BIF_BPERMD)
> icode = CODE_FOR_bpermd_si;
> + else if (fcode == RS6000_BIF_DARN)
> + icode = CODE_FOR_darn_64_si;
> + else if (fcode == RS6000_BIF_DARN_32)
> + icode = CODE_FOR_darn_32_si;
> + else if (fcode == RS6000_BIF_DARN_RAW)
> + icode = CODE_FOR_darn_raw_si;
>else
> gcc_unreachable ();
> }
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 4122acb98cfd..9be484c7cf83 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -172,9 +172,7 @@ (define_c_enum "unspecv"
> UNSPECV_EH_RR ; eh_reg_restore
> UNSPECV_ISYNC ; isync instruction
> UNSPECV_MFTB ; move from time base
> - UNSPECV_DARN ; darn 1 (deliver a random number)
> - UNSPECV_DARN_32 ; darn 2
> - UNSPECV_DARN_RAW ; darn 0
> + UNSPECV_DARN ; darn (deliver a random number)
> UNSPECV_NLGR ; non-local goto receiver
> UNSPECV_MFFS ; Move from FPSCR
> UNSPECV_MFFSL ; Move from FPSCR light instruction version
> @@ -15065,25 +15063,36 @@ (define_insn "*cmp_hw"
>
> ;; Miscellaneous ISA 3.0 (power9) instructions
>
> -(define_insn "darn_32"
> - [(set (match_operand:SI 0 "register_operand" "=r")
> -(unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))]
> +(define_expand "darn_32_"
> + [(use (match_operand:GPR 0 "register_operand"))]
>"TARGET_P9_MISC"
> - "darn %0,0"
> - [(set_attr "type" "integer")])
> +{
> + emit_insn (gen_darn (mode, operands[0], const0_rtx));
> + DONE;
> +})
>
> -(define_insn "darn_raw"
> - [(set (match_operand:DI 0 "register_operand" "=r")
> -(unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))]
> - "TARGET_P9_MISC && TARGET_64BIT"
> - "darn %0,2"
> - [(set_attr "type" "integer")])
> +(define_expand "darn_64_"
> + [(use (match_operand:GPR 0 "register_operand"))]
> + "TARGET_P9_MISC"
> +{
> + emit_insn (gen_darn (mode, operands[0], const1_rtx));
> + DONE;
> +})
>
> -(define_insn "darn"
> - [(set (match_operand:DI 0 "register_operand" "=r")
> -(unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))]
> - "TARGET_P9_MISC && TARGET_64BIT"
> - "darn %0,1"
> +(define_expand "darn_raw_"
> + [(use (match_operand:GPR 0 "register_operand"))]
> + "
Re: [PATCH 2/2] rs6000: Update darn testcases
Hi!
On 12/17/21 11:36 AM, Segher Boessenkool wrote:
> Make the darn testcases work (and be tested) in 32-bit mode as well.
> They used to ICE, but they no longer do.
>
>
> 2021-12-17 Segher Boessenkool
>
> gcc/testsuite/
> PR target/103624
> * gcc.target/powerpc/darn-0.c: Remove target clause.
> * gcc.target/powerpc/darn-1.c: Remove target clause. Remove lp64
> requirement. Change return type to long.
> * gcc.target/powerpc/darn-2.c: Ditto.
> * gcc.target/powerpc/darn-3.c: Remove target clause.
LGTM.
Thanks!
Bill
>
> ---
> gcc/testsuite/gcc.target/powerpc/darn-0.c | 2 +-
> gcc/testsuite/gcc.target/powerpc/darn-1.c | 5 ++---
> gcc/testsuite/gcc.target/powerpc/darn-2.c | 5 ++---
> gcc/testsuite/gcc.target/powerpc/darn-3.c | 2 +-
> 4 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/darn-0.c
> b/gcc/testsuite/gcc.target/powerpc/darn-0.c
> index f446f494b06d..64d98f5f91d7 100644
> --- a/gcc/testsuite/gcc.target/powerpc/darn-0.c
> +++ b/gcc/testsuite/gcc.target/powerpc/darn-0.c
> @@ -1,4 +1,4 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> +/* { dg-do compile } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> /* { dg-skip-if "" { powerpc*-*-aix* } } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
> diff --git a/gcc/testsuite/gcc.target/powerpc/darn-1.c
> b/gcc/testsuite/gcc.target/powerpc/darn-1.c
> index 0938718a5ad6..f483a89862d0 100644
> --- a/gcc/testsuite/gcc.target/powerpc/darn-1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/darn-1.c
> @@ -1,12 +1,11 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> +/* { dg-do compile } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-skip-if "" { powerpc*-*-aix* } } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
>
> #include
>
> -long long get_conditioned_random ()
> +long get_conditioned_random ()
> {
>return __builtin_darn ();
> }
> diff --git a/gcc/testsuite/gcc.target/powerpc/darn-2.c
> b/gcc/testsuite/gcc.target/powerpc/darn-2.c
> index 64e44b244c4b..56a9ffb677b4 100644
> --- a/gcc/testsuite/gcc.target/powerpc/darn-2.c
> +++ b/gcc/testsuite/gcc.target/powerpc/darn-2.c
> @@ -1,12 +1,11 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> +/* { dg-do compile } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-skip-if "" { powerpc*-*-aix* } } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
>
> #include
>
> -long long get_raw_random ()
> +long get_raw_random ()
> {
>return __builtin_darn_raw ();
> }
> diff --git a/gcc/testsuite/gcc.target/powerpc/darn-3.c
> b/gcc/testsuite/gcc.target/powerpc/darn-3.c
> index 477901fde70d..4c68fad80d5d 100644
> --- a/gcc/testsuite/gcc.target/powerpc/darn-3.c
> +++ b/gcc/testsuite/gcc.target/powerpc/darn-3.c
> @@ -1,4 +1,4 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> +/* { dg-do compile } */
> /* { dg-skip-if "" { powerpc*-*-aix* } } */
> /* { dg-options "-O2 -mdejagnu-cpu=power9" } */
>
Re: [PATCH] config.gcc: Obsolete m32c-rtems target
On Fri, Dec 17, 2021 at 11:11 AM Joel Sherrill wrote:
>
> ---
> gcc/config.gcc | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index c8824367b13..fe93a72a16c 100644
> --- a/gcc/config.gcc
> +++ b/gcc/config.gcc
> @@ -252,6 +252,7 @@ case ${target} in
> | cr16-*-*\
> | hppa[12]*-*-hpux10* \
> | hppa[12]*-*-hpux11* \
> + | m32c-*-rtems* \
> )
> if test "x$enable_obsolete" != xyes; then
>echo "*** Configuration ${target} is obsolete." >&2
> --
> 2.24.4
>
Hi, be sure to note this obsoletion in the Caveats section of
gcc-12/changes.html; thanks.
Re: [PATCH] Add VxWorks fixincludes hack, kernel math.h FP_ constants
Hi again Rasmus, > On 17 Dec 2021, at 14:03, Rasmus Villemoes wrote: > > On 17/12/2021 13.10, Olivier Hainque wrote: >> Hello, >> >> The attached patch adds a fixincludes add for VxWorks >> to add missing FP_ constant definition to math.h, intended >> for old versions of the kernel math.h header. > > Don't you also need to add an fpclassify() macro? There's a > > checking for ISO C99 support in for C++98 > > which checks whether math.h supplies (among others) fpclassify(). We have a separate "fix" for a set of such functions indeed. > We've patched our math.h to supply those constants as well as an > fpclassify() macro. So I suppose the 'bypass = "FP_INFINITE"' would mean > that this fixinclude would just be skipped for our case(?). That's my understanding, yes.
Re: [PATCH v4 0/6] __builtin_dynamic_object_size
Siddhesh, This patch series seems to have caused testsuite regressions for memcpy-chk, etc. in 32 bit mode (i386, x86-64 -m32 and -mx32, AIX 32 bit). I have opened PR 103759. Thanks, David
Re: [PATCH v3] attribs: Fix wrong error with -Wno-attribute=A::b [PR103649]
On 12/17/21 13:14, Marek Polacek wrote:
On Thu, Dec 16, 2021 at 08:06:43PM -0500, Jason Merrill wrote:
On 12/16/21 19:52, Marek Polacek wrote:
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/Wno-attributes-6.c
@@ -0,0 +1,14 @@
+/* PR c/103649 */
+/* { dg-do compile { target { c || c++11 } } } */
+/* { dg-additional-options "-Wno-attributes=foo::bar" } */
+/* { dg-additional-options "-Wno-attributes=baz::" } */
+/* { dg-additional-options "-Wno-attributes=womp::womp" } */
+/* { dg-additional-options "-Wno-attributes=qux::foo" } */
+
+[[foo::bar(1, 2)]]; /* { dg-warning "attribute ignored" } */
+[[baz::bar(1, 2)]]; /* { dg-warning "attribute ignored" } */
+[[foo::bar(1, 2)]] void f1();
+[[baz::bar(1, 2)]] void f2();
+[[qux::foo({t})]] void f3();
+[[womp::womp (another::directive (threadprivate (t)))]] void f4();
+[[womp::womp (another::directive (threadprivate (t)))]]; /* { dg-warning "attribute
ignored" } */
If we're ignoring these attributes, we should ignore them everywhere;
perhaps using them for an attribute-declaration is meaningful in another
compiler.
Sounds good. Reminds me of P177, Portable assumptions...
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?
-- >8 --
My patch to implement -Wno-attribute=A::b caused a bogus error when
parsing
[[foo::bar(1, 2)]];
when -Wno-attributes=foo::bar was specified on the command line, because
when we create a fake foo::bar attribute and insert it into our attribute
table, it is created with max_length == 0 which doesn't allow any args.
That is wrong -- we know nothing about the attribute, so we shouldn't
require any specific number of arguments. And since unknown attributes
can be rather complex (see for example omp::{directive,sequence}), we
must skip parsing their arguments. To that end, I'm using max_length
with value -2.
Also let's not warn about things like
[[vendor::assume(true)]];
because they may have some meaning (this is reminiscent of C++ Portable
Assumptions).
PR c/103649
gcc/ChangeLog:
* attribs.c (handle_ignored_attributes_option): Create the fake
attribute with max_length == -2.
(attribute_ignored_p): New function.
* attribs.h (attribute_ignored_p): Declare.
* tree-core.h (struct attribute_spec): Document that max_length
can be -2.
gcc/c/ChangeLog:
* c-decl.c (c_warn_unused_attributes): Don't warn for
attribute_ignored_p.
* c-parser.c (c_parser_std_attribute): Skip parsing of the attribute
arguments when max_length == -2.
gcc/cp/ChangeLog:
* parser.c (cp_parser_declaration): Don't warn for attribute_ignored_p.
(cp_parser_std_attribute): Skip parsing of the attribute
arguments when max_length == -2.
gcc/testsuite/ChangeLog:
* c-c++-common/Wno-attributes-6.c: New test.
---
gcc/attribs.c | 20 ++-
gcc/attribs.h | 1 +
gcc/c/c-decl.c| 2 +-
gcc/c/c-parser.c | 4 +++-
gcc/cp/parser.c | 6 --
gcc/testsuite/c-c++-common/Wno-attributes-6.c | 16 +++
gcc/tree-core.h | 4 +++-
7 files changed, 47 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/c-c++-common/Wno-attributes-6.c
diff --git a/gcc/attribs.c b/gcc/attribs.c
index 29703e75fba..82527869093 100644
--- a/gcc/attribs.c
+++ b/gcc/attribs.c
@@ -304,7 +304,7 @@ handle_ignored_attributes_option (vec *v)
We can't free it here, so squirrel away the pointers. */
attribute_spec *table = new attribute_spec[2];
ignored_attributes_table.safe_push (table);
- table[0] = { attr, 0, 0, false, false, false, false, nullptr, nullptr };
+ table[0] = { attr, 0, -2, false, false, false, false, nullptr, nullptr };
table[1] = { nullptr, 0, 0, false, false, false, false, nullptr,
nullptr };
register_scoped_attributes (table, IDENTIFIER_POINTER (vendor_id),
!attr);
@@ -569,6 +569,24 @@ attr_namespace_ignored_p (tree ns)
return r && r->ignored_p;
}
+/* Return true if the attribute ATTR should not be warned about. */
+
+bool
+attribute_ignored_p (tree attr)
+{
+ if (!cxx11_attribute_p (attr))
+return false;
+ if (tree ns = get_attribute_namespace (attr))
+{
+ if (attr_namespace_ignored_p (ns))
+ return true;
+ const attribute_spec *as = lookup_attribute_spec (TREE_PURPOSE (attr));
+ if (as && as->max_length == -2)
+ return true;
+}
+ return false;
+}
+
/* Process the attributes listed in ATTRIBUTES and install them in *NODE,
which is either a DECL (including a TYPE_DECL) or a TYPE. If a DECL,
it should be modified in place; if a TYPE, a copy should be created
diff --git a/gcc/attribs.h b/gcc/attribs.h
index f5899d83c0b..d3449d5bd1d 100644
--- a/gcc/attribs.h
+++ b/gcc/attribs.h
@@ -39,6 +
[GCC-WWWDocs v1] htdocs/gcc-12/changes.html: Obsolete m32c-*-rtems*
--- htdocs/gcc-12/changes.html | 4 1 file changed, 4 insertions(+) diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html index b1c88670..c69b301e 100644 --- a/htdocs/gcc-12/changes.html +++ b/htdocs/gcc-12/changes.html @@ -66,6 +66,10 @@ a work-in-progress. The hppa[12]*-*-hpux10* and hppa[12]*-*-hpux11* configurations targeting 32-bit PA-RISC with HP-UX have been obsoleted and will be removed in a future release. + + +The m32c*-*-rtems* configuration has been obsoleted and will +be removed in a future release. The support for the m32r-*-linux*, m32rle-*-linux*, m68k*-*-openbsd* and vax-*-openbsd* configurations -- 2.24.4
Re: [PATCH v4 0/6] __builtin_dynamic_object_size
On 12/18/21 00:59, David Edelsohn wrote: Siddhesh, This patch series seems to have caused testsuite regressions for memcpy-chk, etc. in 32 bit mode (i386, x86-64 -m32 and -mx32, AIX 32 bit). I have opened PR 103759. Thanks, I've assigned it to myself. I'll take a look. Siddhesh
[r12-6031 Regression] FAIL: gcc.dg/builtin-dynamic-object-size-2.c execution test on Linux/x86_64
On Linux/x86_64,
79a89108dd352cd9288f5de35481b1280c7588a5 is the first bad commit
commit 79a89108dd352cd9288f5de35481b1280c7588a5
Author: Siddhesh Poyarekar
Date: Fri Dec 17 09:34:44 2021 +0530
__builtin_dynamic_object_size: Recognize builtin
caused
FAIL: gcc.dg/builtin-dynamic-object-size-1.c execution test
FAIL: gcc.dg/builtin-dynamic-object-size-2.c execution test
with GCC configured with
../../gcc/configure
--prefix=/local/skpandey/gccwork/toolwork/gcc-bisect-master/master/r12-6031/usr
--enable-clocale=gnu --with-system-zlib --with-demangler-in-ld
--with-fpmath=sse --enable-languages=c,c++,fortran --enable-cet --without-isl
--enable-libmpx x86_64-linux --disable-bootstrap
To reproduce:
$ cd {build_dir}/gcc && make check
RUNTESTFLAGS="dg.exp=gcc.dg/builtin-dynamic-object-size-1.c
--target_board='unix{-m32}'"
$ cd {build_dir}/gcc && make check
RUNTESTFLAGS="dg.exp=gcc.dg/builtin-dynamic-object-size-1.c
--target_board='unix{-m32\ -march=cascadelake}'"
$ cd {build_dir}/gcc && make check
RUNTESTFLAGS="dg.exp=gcc.dg/builtin-dynamic-object-size-2.c
--target_board='unix{-m32}'"
$ cd {build_dir}/gcc && make check
RUNTESTFLAGS="dg.exp=gcc.dg/builtin-dynamic-object-size-2.c
--target_board='unix{-m32\ -march=cascadelake}'"
(Please do not reply to this email, for question about this report, contact me
at skpgkp2 at gmail dot com)
[r12-6030 Regression] FAIL: gcc.dg/builtin-object-size-2.c execution test on Linux/x86_64
On Linux/x86_64,
422f9eb7011b76c12ff00ffaee2bcc9cdddf16d5 is the first bad commit
commit 422f9eb7011b76c12ff00ffaee2bcc9cdddf16d5
Author: Siddhesh Poyarekar
Date: Fri Dec 17 07:07:18 2021 +0530
tree-object-size: Use trees and support negative offsets
caused
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c execution, -O1
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c execution, -O2
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c execution, -O2 -flto
-fno-use-linker-plugin -flto-partition=none
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c execution, -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c execution, -O3
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c execution, -O3 -g
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c execution, -Og -g
FAIL: gcc.c-torture/execute/builtins/memcpy-chk.c execution, -Os
FAIL: gcc.c-torture/execute/builtins/memmove-chk.c execution, -O1
FAIL: gcc.c-torture/execute/builtins/memmove-chk.c execution, -O2
FAIL: gcc.c-torture/execute/builtins/memmove-chk.c execution, -O2 -flto
-fno-use-linker-plugin -flto-partition=none
FAIL: gcc.c-torture/execute/builtins/memmove-chk.c execution, -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects
FAIL: gcc.c-torture/execute/builtins/memmove-chk.c execution, -O3
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions
FAIL: gcc.c-torture/execute/builtins/memmove-chk.c execution, -O3 -g
FAIL: gcc.c-torture/execute/builtins/memmove-chk.c execution, -Og -g
FAIL: gcc.c-torture/execute/builtins/memmove-chk.c execution, -Os
FAIL: gcc.c-torture/execute/builtins/mempcpy-chk.c execution, -O1
FAIL: gcc.c-torture/execute/builtins/mempcpy-chk.c execution, -O2
FAIL: gcc.c-torture/execute/builtins/mempcpy-chk.c execution, -O2 -flto
-fno-use-linker-plugin -flto-partition=none
FAIL: gcc.c-torture/execute/builtins/mempcpy-chk.c execution, -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects
FAIL: gcc.c-torture/execute/builtins/mempcpy-chk.c execution, -O3
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions
FAIL: gcc.c-torture/execute/builtins/mempcpy-chk.c execution, -O3 -g
FAIL: gcc.c-torture/execute/builtins/mempcpy-chk.c execution, -Og -g
FAIL: gcc.c-torture/execute/builtins/mempcpy-chk.c execution, -Os
FAIL: gcc.c-torture/execute/builtins/memset-chk.c execution, -O1
FAIL: gcc.c-torture/execute/builtins/memset-chk.c execution, -O2
FAIL: gcc.c-torture/execute/builtins/memset-chk.c execution, -O2 -flto
-fno-use-linker-plugin -flto-partition=none
FAIL: gcc.c-torture/execute/builtins/memset-chk.c execution, -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects
FAIL: gcc.c-torture/execute/builtins/memset-chk.c execution, -O3
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions
FAIL: gcc.c-torture/execute/builtins/memset-chk.c execution, -O3 -g
FAIL: gcc.c-torture/execute/builtins/memset-chk.c execution, -Og -g
FAIL: gcc.c-torture/execute/builtins/memset-chk.c execution, -Os
FAIL: gcc.c-torture/execute/builtins/stpcpy-chk.c execution, -O1
FAIL: gcc.c-torture/execute/builtins/stpcpy-chk.c execution, -O2
FAIL: gcc.c-torture/execute/builtins/stpcpy-chk.c execution, -O2 -flto
-fno-use-linker-plugin -flto-partition=none
FAIL: gcc.c-torture/execute/builtins/stpcpy-chk.c execution, -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects
FAIL: gcc.c-torture/execute/builtins/stpcpy-chk.c execution, -O3
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions
FAIL: gcc.c-torture/execute/builtins/stpcpy-chk.c execution, -O3 -g
FAIL: gcc.c-torture/execute/builtins/stpcpy-chk.c execution, -Og -g
FAIL: gcc.c-torture/execute/builtins/stpcpy-chk.c execution, -Os
FAIL: gcc.dg/builtin-object-size-1.c execution test
FAIL: gcc.dg/builtin-object-size-2.c execution test
with GCC configured with
../../gcc/configure
--prefix=/local/skpandey/gccwork/toolwork/gcc-bisect-master/master/r12-6030/usr
--enable-clocale=gnu --with-system-zlib --with-demangler-in-ld
--with-fpmath=sse --enable-languages=c,c++,fortran --enable-cet --without-isl
--enable-libmpx x86_64-linux --disable-bootstrap
To reproduce:
$ cd {build_dir}/gcc && make check
RUNTESTFLAGS="builtins.exp=gcc.c-torture/execute/builtins/memcpy-chk.c
--target_board='unix{-m32}'"
$ cd {build_dir}/gcc && make check
RUNTESTFLAGS="builtins.exp=gcc.c-torture/execute/builtins/memcpy-chk.c
--target_board='unix{-m32\ -march=cascadelake}'"
$ cd {build_dir}/gcc && make check
RUNTESTFLAGS="builtins.exp=gcc.c-torture/execute/builtins/memmove-chk.c
--target_board='unix{-m32}'"
$ cd {build_dir}/gcc && make check
RUNTESTFLAGS="builtins.exp=gcc.c-torture/execute/builtins/memmove-chk.c
--target_board='unix{-m32\ -march=cascadelake}'"
$ cd {build_dir}/gcc && make check
RUNTESTFLAGS="builtins.exp=gcc.c-torture/execute/bui
Re: [PATCH] config.gcc: Obsolete m32c-rtems target
On Fri, Dec 17, 2021 at 12:53 PM Eric Gallager wrote:
>
> On Fri, Dec 17, 2021 at 11:11 AM Joel Sherrill wrote:
> >
> > ---
> > gcc/config.gcc | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/gcc/config.gcc b/gcc/config.gcc
> > index c8824367b13..fe93a72a16c 100644
> > --- a/gcc/config.gcc
> > +++ b/gcc/config.gcc
> > @@ -252,6 +252,7 @@ case ${target} in
> > | cr16-*-*\
> > | hppa[12]*-*-hpux10* \
> > | hppa[12]*-*-hpux11* \
> > + | m32c-*-rtems* \
> > )
> > if test "x$enable_obsolete" != xyes; then
> >echo "*** Configuration ${target} is obsolete." >&2
> > --
> > 2.24.4
> >
>
> Hi, be sure to note this obsoletion in the Caveats section of
> gcc-12/changes.html; thanks.
Thanks for reminding me. Patch for that posted also.
--joel
Ping^2: [PATCH, rs6000 V2] rotate and mask constants [PR94393]
Ping. On 11/22/21 1:38 PM, Pat Haugen via Gcc-patches wrote: > Updated version of the patch. Changes made from original are updated > commentary to hopefully aid readability, no functional changes. > > > Implement more two insn constants. rotate_and_mask_constant covers > 64-bit constants that can be formed by rotating a 16-bit signed > constant, rotating a 16-bit signed constant masked on left or right > (rldicl and rldicr), rotating a 16-bit signed constant masked by > rldic, and unusual "lis; rldicl" and "lis; rldicr" patterns. All the > values possible for DImode rs6000_is_valid_and_mask are covered. > > Bootstrapped and regression tested on powerpc64(32/64) and powerpc64le. > Ok for master? > > -Pat > > > 2021-11-22 Alan Modra > Pat Haugen > > PR 94393 > gcc/ > * config/rs6000/rs6000.c (rotate_di, is_rotate_positive_constant, > is_rotate_negative_constant, rotate_and_mask_constant): New functions. > (num_insns_constant_multi, rs6000_emit_set_long_const): Use it here. > * config/rs6000/rs6000.md (*movdi_internal64+1 splitter): Delete. > gcc/testsuite/ > * gcc.target/powerpc/rot_cst.h, > * gcc.target/powerpc/rot_cst1.c, > * gcc.target/powerpc/rot_cst2.c: New tests. >
Re: [PATCH] Add VxWorks fixincludes hack, kernel math.h FP_ constants
> On 17 Dec 2021, at 20:16, Olivier Hainque wrote: > >> Don't you also need to add an fpclassify() macro? There's a >> >> checking for ISO C99 support in for C++98 >> >> which checks whether math.h supplies (among others) fpclassify(). > > We have a separate "fix" for a set of such functions indeed. I probably can merge the two, actually. I'll do that. >> We've patched our math.h to supply those constants as well as an >> fpclassify() macro. So I suppose the 'bypass = "FP_INFINITE"' would mean >> that this fixinclude would just be skipped for our case(?). > > That's my understanding, yes.
Re: [PATCH] c++: don't ICE on NAMESPACE_DECL inside FUNCTION_DECL
On 12/15/21 03:53, Matthias Kretz wrote:
OK for trunk? This fixes several modules.exp failures for me.
OK.
── ✂ ──
Code like
void swap() {
namespace __variant = __detail::__variant;
...
}
create a NAMESPACE_DECL where the CP_DECL_CONTEXT is a FUNCTION_DECL.
DECL_TEMPLATE_INFO fails on NAMESPACE_DECL and therefore must be handled
first in the assertion.
Signed-off-by: Matthias Kretz
gcc/cp/ChangeLog:
* module.cc (trees_out::get_merge_kind): NAMESPACE_DECLs also
cannot have a DECL_TEMPLATE_INFO.
---
gcc/cp/module.cc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--
──
Dr. Matthias Kretz https://mattkretz.github.io
GSI Helmholtz Centre for Heavy Ion Research https://gsi.de
stdₓ::simd
──
[PATCH] tree-optimization/103759: Truncate unknown to sizetype on compare
Since all computations in tree-object-size are now done in sizetype and
not HOST_WIDE_INT, comparisons after conversion to HOST_WIDE_INT would
be incorrect. Instead, truncate unknown (object_size_type) to sizetype
to compare with the computed size to evaluate if it is unknown.
gcc/ChangeLog:
PR tree-optimization/103759
* tree-object-size (size_unknown_p): Construct a size_unknown
and compare with VAL.
Signed-off-by: Siddhesh Poyarekar
---
This fixes all the 32-bit torture failures on i686, tested with
configuration:
--enable-clocale=gnu --with-system-zlib --enable-shared --enable-cet
--with-demangler-in-ld --enable-libmpx i686-linux --with-fpmath=sse
--enable-languages=c,c++,lto --disable-bootstrap
and also with x86_64 to ensure I didn't regress there. I have a full
bootstrap build and test run in progress.
gcc/tree-object-size.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/tree-object-size.c b/gcc/tree-object-size.c
index 71f6b747d05..71c7935cb07 100644
--- a/gcc/tree-object-size.c
+++ b/gcc/tree-object-size.c
@@ -100,15 +100,6 @@ unknown (int object_size_type)
return ~initval (object_size_type);
}
-/* Return true if VAL is represents an unknown size for OBJECT_SIZE_TYPE. */
-
-static inline bool
-size_unknown_p (tree val, int object_size_type)
-{
- return (tree_fits_uhwi_p (val)
- && tree_to_uhwi (val) == unknown (object_size_type));
-}
-
/* Return a tree with initial value for OBJECT_SIZE_TYPE. */
static inline tree
@@ -125,6 +116,15 @@ size_unknown (int object_size_type)
return size_int (unknown (object_size_type));
}
+/* Return true if VAL is represents an unknown size for OBJECT_SIZE_TYPE. */
+
+static inline bool
+size_unknown_p (tree val, int object_size_type)
+{
+ return (TREE_CODE (val) == INTEGER_CST
+ && tree_int_cst_compare (val, size_unknown (object_size_type)));
+}
+
/* Grow object_sizes[OBJECT_SIZE_TYPE] to num_ssa_names. */
static inline void
--
2.31.1
[PATCH v2] tree-optimization/103759: Truncate unknown to sizetype on compare
Since all computations in tree-object-size are now done in sizetype and
not HOST_WIDE_INT, comparisons after conversion to HOST_WIDE_INT would
be incorrect. Instead, truncate unknown (object_size_type) to sizetype
to compare with the computed size to evaluate if it is unknown.
gcc/ChangeLog:
PR tree-optimization/103759
* tree-object-size (unknown, initval): Change to arrays. Adjust
all uses.
(init_limits): Rename from init_offset_limit. Initialize
UNKNOWN and INITVAL. Adjust all uses.
Signed-off-by: Siddhesh Poyarekar
---
Changes from v1:
Alternative approach that doesn't result in unnecessary construction of
trees.
gcc/tree-object-size.c | 36 +---
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/gcc/tree-object-size.c b/gcc/tree-object-size.c
index 71f6b747d05..fc5f82e7c36 100644
--- a/gcc/tree-object-size.c
+++ b/gcc/tree-object-size.c
@@ -64,7 +64,7 @@ static void expr_object_size (struct object_size_info *,
tree, tree);
static bool merge_object_sizes (struct object_size_info *, tree, tree);
static bool plus_stmt_object_size (struct object_size_info *, tree, gimple *);
static bool cond_expr_object_size (struct object_size_info *, tree, gimple *);
-static void init_offset_limit (void);
+static void init_limits (void);
static void check_for_plus_in_loops (struct object_size_info *, tree);
static void check_for_plus_in_loops_1 (struct object_size_info *, tree,
unsigned int);
@@ -85,20 +85,10 @@ static unsigned HOST_WIDE_INT offset_limit;
/* Initial value of object sizes; zero for maximum and SIZE_MAX for minimum
object size. */
-
-static inline unsigned HOST_WIDE_INT
-initval (int object_size_type)
-{
- return (object_size_type & OST_MINIMUM) ? HOST_WIDE_INT_M1U : 0;
-}
+static unsigned HOST_WIDE_INT initval[OST_END];
/* Unknown object size value; it's the opposite of initval. */
-
-static inline unsigned HOST_WIDE_INT
-unknown (int object_size_type)
-{
- return ~initval (object_size_type);
-}
+static unsigned HOST_WIDE_INT unknown[OST_END];
/* Return true if VAL is represents an unknown size for OBJECT_SIZE_TYPE. */
@@ -106,7 +96,7 @@ static inline bool
size_unknown_p (tree val, int object_size_type)
{
return (tree_fits_uhwi_p (val)
- && tree_to_uhwi (val) == unknown (object_size_type));
+ && tree_to_uhwi (val) == unknown[object_size_type]);
}
/* Return a tree with initial value for OBJECT_SIZE_TYPE. */
@@ -114,7 +104,7 @@ size_unknown_p (tree val, int object_size_type)
static inline tree
size_initval (int object_size_type)
{
- return size_int (initval (object_size_type));
+ return size_int (initval[object_size_type]);
}
/* Return a tree with unknown value for OBJECT_SIZE_TYPE. */
@@ -122,7 +112,7 @@ size_initval (int object_size_type)
static inline tree
size_unknown (int object_size_type)
{
- return size_int (unknown (object_size_type));
+ return size_int (unknown[object_size_type]);
}
/* Grow object_sizes[OBJECT_SIZE_TYPE] to num_ssa_names. */
@@ -202,13 +192,21 @@ object_sizes_set (struct object_size_info *osi, unsigned
varno, tree val,
/* Initialize OFFSET_LIMIT variable. */
static void
-init_offset_limit (void)
+init_limits (void)
{
if (tree_fits_uhwi_p (TYPE_MAX_VALUE (sizetype)))
offset_limit = tree_to_uhwi (TYPE_MAX_VALUE (sizetype));
else
offset_limit = -1;
offset_limit /= 2;
+
+ for (int i = 0; i < OST_END; i++)
+{
+ if (i & OST_MINIMUM)
+ initval[i] = tree_to_uhwi (size_int (HOST_WIDE_INT_M1U));
+ else
+ unknown[i] = tree_to_uhwi (size_int (HOST_WIDE_INT_M1U));
+}
}
/* Bytes at end of the object with SZ from offset OFFSET. If WHOLESIZE is not
@@ -705,7 +703,7 @@ compute_builtin_object_size (tree ptr, int object_size_type,
*psize = size_unknown (object_size_type);
if (! offset_limit)
-init_offset_limit ();
+init_limits ();
if (TREE_CODE (ptr) == ADDR_EXPR)
return addr_object_size (NULL, ptr, object_size_type, psize);
@@ -1374,7 +1372,7 @@ init_object_sizes (void)
computed[object_size_type] = BITMAP_ALLOC (NULL);
}
- init_offset_limit ();
+ init_limits ();
}
--
2.31.1
Re: [PATCH] tree-optimization/103759: Truncate unknown to sizetype on compare
On Sat, Dec 18, 2021 at 02:53:47AM +0530, Siddhesh Poyarekar wrote: > Since all computations in tree-object-size are now done in sizetype and > not HOST_WIDE_INT, comparisons after conversion to HOST_WIDE_INT would > be incorrect. Instead, truncate unknown (object_size_type) to sizetype > to compare with the computed size to evaluate if it is unknown. > > gcc/ChangeLog: > > PR tree-optimization/103759 > * tree-object-size (size_unknown_p): Construct a size_unknown > and compare with VAL. I think you should instead drop initval and unknown inlines and rewrite size_unknown, size_initval and size_unknown_p to work directly on trees. size_initval to return ((object_size_type & OST_MINIMUM) ? TYPE_MAX_VALUE (sizetype) : size_zero_node); size_unknown to return ((object_size_type & OST_MINIMUM) ? size_zero_node : TYPE_MAX_VALUE (sizetype)); and size_unknown_p to: return ((object_size_type & OST_MINIMUM) ? integer_zerop (val) : integer_all_onesp (val)); Jakub
[patch] Future-proof and homogenise handling of darwin versions
The current GCC branch will become 12.1.0, which will be the stable version of GCC when the next macOS version is released. There are some places in GCC that don’t handle darwin22 as a version, so we need to future-proof it (gcc/config.gcc and gcc/config/darwin-driver.c). We align that code with what Apple clang does, i.e. accept all potential major macOS versions until 99. This patch also homogenises the handling of darwin version numbers, where the majority of places use darwin2*, but some used darwin2[0-9]*. Since there never was a darwin2.x version, the two are equivalent, and we prefer the simpler darwin2* Bootstrapped and regtested on x86_64-apple-darwin21. OK to commit? FX darwin.patch Description: Binary data
[GCC-11] [PATCH] libsanitizer: Cherry-pick LLVM release/13.x commit d96358a28193
OK for release branches?
H.J.
---
Cherry-pick from LLVM release/13.x branch:
commit d96358a2819399a2abb60ad3b26444ab7b4409cf
Author: Michał Górny
Date: Mon Dec 13 22:28:26 2021 +0100
[compiler-rt] Increase kDlsymAllocPoolSize to fix test failures
Increase kDlsymAllocPoolSize on the release branch as discussed on bug
51620, as an alternative to backporting
cb0e14ce6dcdd614a7207f4ce6fcf81a164471ab and its dependencies.
The minimum size is 8192, as needed for the following test to pass:
AddressSanitizer-i386-linux :: TestCases/Linux/long-object-path.cpp
Fixes #51620
PR sanitizer/102911
* asan/asan_malloc_linux.cpp (kDlsymAllocPoolSize): Set it to
8192 on Linux.
---
libsanitizer/asan/asan_malloc_linux.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libsanitizer/asan/asan_malloc_linux.cpp
b/libsanitizer/asan/asan_malloc_linux.cpp
index 9c3f0a5338e..7a5776b29ed 100644
--- a/libsanitizer/asan/asan_malloc_linux.cpp
+++ b/libsanitizer/asan/asan_malloc_linux.cpp
@@ -31,7 +31,7 @@ using namespace __asan;
static uptr allocated_for_dlsym;
static uptr last_dlsym_alloc_size_in_words;
-static const uptr kDlsymAllocPoolSize = SANITIZER_RTEMS ? 4096 : 1024;
+static const uptr kDlsymAllocPoolSize = SANITIZER_RTEMS ? 4096 : 8192;
static uptr alloc_memory_for_dlsym[kDlsymAllocPoolSize];
static inline bool IsInDlsymAllocPool(const void *ptr) {
--
2.33.1
[PATCH v4] attribs: Fix wrong error with -Wno-attribute=A::b [PR103649]
On Fri, Dec 17, 2021 at 02:33:01PM -0500, Jason Merrill wrote:
> On 12/17/21 13:14, Marek Polacek wrote:
> > @@ -28979,7 +28979,9 @@ cp_parser_std_attribute (cp_parser *parser, tree
> > attr_ns)
> > /* A GNU attribute that takes an identifier in parameter. */
> > attr_flag = id_attr;
> > -if (as == NULL)
> > +/* When MAX_LENGTH is -2, this is a fake attribute created to
> > + handle -Wno-attributes, and we must skip parsing the arguments. */
> > +if (as == NULL || as->max_length == -2)
>
> Rather than require multiple places to know about the magic -2, could we
> have an overload of attribute_ignored_p that takes an attribute_spec*? OK
> with that change.
Sure, here's what I'm pushing:
Tested x86_64-pc-linux-gnu, applying to trunk.
-- >8 --
My patch to implement -Wno-attribute=A::b caused a bogus error when
parsing
[[foo::bar(1, 2)]];
when -Wno-attributes=foo::bar was specified on the command line, because
when we create a fake foo::bar attribute and insert it into our attribute
table, it is created with max_length == 0 which doesn't allow any args.
That is wrong -- we know nothing about the attribute, so we shouldn't
require any specific number of arguments. And since unknown attributes
can be rather complex (see for example omp::{directive,sequence}), we
must skip parsing their arguments. To that end, I'm using max_length
with value -2.
Also let's not warn about things like
[[vendor::assume(true)]];
because they may have some meaning (this is reminiscent of C++ Portable
Assumptions).
PR c/103649
gcc/ChangeLog:
* attribs.c (handle_ignored_attributes_option): Create the fake
attribute with max_length == -2.
(attribute_ignored_p): New overloads.
* attribs.h (attribute_ignored_p): Declare them.
* tree-core.h (struct attribute_spec): Document that max_length
can be -2.
gcc/c/ChangeLog:
* c-decl.c (c_warn_unused_attributes): Don't warn for
attribute_ignored_p.
* c-parser.c (c_parser_std_attribute): Skip parsing of the attribute
arguments when the attribute is ignored.
gcc/cp/ChangeLog:
* parser.c (cp_parser_declaration): Don't warn for attribute_ignored_p.
(cp_parser_std_attribute): Skip parsing of the attribute
arguments when the attribute is ignored.
gcc/testsuite/ChangeLog:
* c-c++-common/Wno-attributes-6.c: New test.
---
gcc/attribs.c | 28 ++-
gcc/attribs.h | 2 ++
gcc/c/c-decl.c| 2 +-
gcc/c/c-parser.c | 4 ++-
gcc/cp/parser.c | 6 ++--
gcc/testsuite/c-c++-common/Wno-attributes-6.c | 16 +++
gcc/tree-core.h | 4 ++-
7 files changed, 56 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/c-c++-common/Wno-attributes-6.c
diff --git a/gcc/attribs.c b/gcc/attribs.c
index 29703e75fba..9e7b7c1abd2 100644
--- a/gcc/attribs.c
+++ b/gcc/attribs.c
@@ -304,7 +304,7 @@ handle_ignored_attributes_option (vec *v)
We can't free it here, so squirrel away the pointers. */
attribute_spec *table = new attribute_spec[2];
ignored_attributes_table.safe_push (table);
- table[0] = { attr, 0, 0, false, false, false, false, nullptr, nullptr };
+ table[0] = { attr, 0, -2, false, false, false, false, nullptr, nullptr };
table[1] = { nullptr, 0, 0, false, false, false, false, nullptr,
nullptr };
register_scoped_attributes (table, IDENTIFIER_POINTER (vendor_id),
!attr);
@@ -569,6 +569,32 @@ attr_namespace_ignored_p (tree ns)
return r && r->ignored_p;
}
+/* Return true if the attribute ATTR should not be warned about. */
+
+bool
+attribute_ignored_p (tree attr)
+{
+ if (!cxx11_attribute_p (attr))
+return false;
+ if (tree ns = get_attribute_namespace (attr))
+{
+ if (attr_namespace_ignored_p (ns))
+ return true;
+ const attribute_spec *as = lookup_attribute_spec (TREE_PURPOSE (attr));
+ if (as && as->max_length == -2)
+ return true;
+}
+ return false;
+}
+
+/* Like above, but takes an attribute_spec AS, which must be nonnull. */
+
+bool
+attribute_ignored_p (const attribute_spec *const as)
+{
+ return as->max_length == -2;
+}
+
/* Process the attributes listed in ATTRIBUTES and install them in *NODE,
which is either a DECL (including a TYPE_DECL) or a TYPE. If a DECL,
it should be modified in place; if a TYPE, a copy should be created
diff --git a/gcc/attribs.h b/gcc/attribs.h
index f5899d83c0b..4928b126f59 100644
--- a/gcc/attribs.h
+++ b/gcc/attribs.h
@@ -39,6 +39,8 @@ extern tree get_attribute_name (const_tree);
extern tree get_attribute_namespace (const_tree);
extern void apply_tm_attr (tree, tree);
extern tree make_attribute (const char *, const char *, tree);
+extern bool attribute_ignored_p (tree);
[PATCH] c++: Avoid narrowing in make_char_string_pack
This fixes
gcc/cp/parser.c:4618:41: warning: narrowing conversion of '(char)(*(str +
((sizetype)i)))' from 'char' to 'unsigned char' [-Wnarrowing]
4618 | unsigned char s[3] = { '\'', str[i], '\'' };
|~^
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?
gcc/cp/ChangeLog:
* parser.c (make_char_string_pack): Add a cast to const unsigned
char *.
---
gcc/cp/parser.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
index 44eed7ea638..56232ab029f 100644
--- a/gcc/cp/parser.c
+++ b/gcc/cp/parser.c
@@ -4607,7 +4607,8 @@ make_char_string_pack (tree value)
{
tree charvec;
tree argpack = make_node (NONTYPE_ARGUMENT_PACK);
- const char *str = TREE_STRING_POINTER (value);
+ const unsigned char *str
+= (const unsigned char *) TREE_STRING_POINTER (value);
int i, len = TREE_STRING_LENGTH (value) - 1;
tree argvec = make_tree_vec (1);
base-commit: d7ca2a79b82c6500ead6ab983d14c609e2124eee
--
2.33.1
[PATCH] c-family: Have -Wformat-diag accept "decl-specifier" [PR103758]
I'm tired of seeing
cp/parser.c:15923:55: warning: misspelled term 'decl' in format; use
'declaration' instead [-Wformat-diag]
cp/parser.c:15925:57: warning: misspelled term 'decl' in format; use
'declaration' instead [-Wformat-diag]
every time I compile cp/parser.c, which happens...a lot. I'd like my
compilation to be free of warnings, otherwise I'm going to miss some
important ones.
"decl-specifiers" is a C++ grammar term; it is not actual code, so
should not be wrapped with %< %>. I hope we can accept it as an exception
in check_tokens.
It was surrounded by %< %> in cp_parser_decl_specifier_seq, so fix that.
In passing, fix a misspelling in missspellings.
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?
In fact, I think I'd like to backport to 11 too, so that eventually
even my system compiler stops warning about this.
PR c++/103758
gcc/c-family/ChangeLog:
* c-format.c (check_tokens): Accept "decl-specifier*".
gcc/cp/ChangeLog:
* parser.c (cp_parser_decl_specifier_seq): Replace %
with %qD.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/constexpr-condition.C: Adjust dg-error.
---
gcc/c-family/c-format.c | 10 +-
gcc/cp/parser.c | 2 +-
gcc/testsuite/g++.dg/cpp0x/constexpr-condition.C | 2 +-
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/gcc/c-family/c-format.c b/gcc/c-family/c-format.c
index 617fb5ea626..e1b1d6ba31e 100644
--- a/gcc/c-family/c-format.c
+++ b/gcc/c-family/c-format.c
@@ -3194,7 +3194,7 @@ check_tokens (const token_t *tokens, unsigned ntoks,
wlen, format_chars);
else
{
- /* Diagnose some common missspellings. */
+ /* Diagnose some common misspellings. */
for (unsigned i = 0; i != sizeof badwords / sizeof *badwords; ++i)
{
unsigned badwlen = strspn (badwords[i].name, " -");
@@ -3215,6 +3215,14 @@ check_tokens (const token_t *tokens, unsigned ntoks,
plural = "s";
}
+ /* As an exception, don't warn about "decl-specifier*" since
+it's a C++ grammar production. */
+ {
+ const size_t l = strlen ("decl-specifier");
+ if (!strncmp (format_chars, "decl-specifier", l))
+ return format_chars + l - 1;
+ }
+
format_warning_substr (format_string_loc, format_string_cst,
fmtchrpos, fmtchrpos + badwords[i].len,
opt,
diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c
index 44eed7ea638..3b33ae0cc21 100644
--- a/gcc/cp/parser.c
+++ b/gcc/cp/parser.c
@@ -15820,7 +15820,7 @@ cp_parser_decl_specifier_seq (cp_parser* parser,
if (found_decl_spec
&& (flags & CP_PARSER_FLAGS_ONLY_TYPE_OR_CONSTEXPR)
&& token->keyword != RID_CONSTEXPR)
- error ("% invalid in condition");
+ error ("%qD invalid in condition", ridpointers[token->keyword]);
if (found_decl_spec
&& (flags & CP_PARSER_FLAGS_ONLY_MUTABLE_OR_CONSTEXPR)
diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-condition.C
b/gcc/testsuite/g++.dg/cpp0x/constexpr-condition.C
index 733d494c4d7..e81acba68ae 100644
--- a/gcc/testsuite/g++.dg/cpp0x/constexpr-condition.C
+++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-condition.C
@@ -5,5 +5,5 @@ constexpr int something() { return 3; }
int main() {
if (constexpr long v = something()) {}
- if (static long v = something()) { } // { dg-error "'decl-specifier'
invalid" }
+ if (static long v = something()) { } // { dg-error "'static' invalid" }
}
base-commit: d7ca2a79b82c6500ead6ab983d14c609e2124eee
--
2.33.1
Re: [patch] Future-proof and homogenise handling of darwin versions
Hi FX, thanks for the patch > On 17 Dec 2021, at 22:23, FX wrote: > > The current GCC branch will become 12.1.0, which will be the stable version > of GCC when the next macOS version is released. There are some places in GCC > that don’t handle darwin22 as a version, so we need to future-proof it > (gcc/config.gcc and gcc/config/darwin-driver.c). We align that code with what > Apple clang does, i.e. accept all potential major macOS versions until 99. > > This patch also homogenises the handling of darwin version numbers, where the > majority of places use darwin2*, but some used darwin2[0-9]*. Since there > never was a darwin2.x version, the two are equivalent, and we prefer the > simpler darwin2* > > Bootstrapped and regtested on x86_64-apple-darwin21. > OK to commit? Yes, but please put this ^^ explanation into the git commit log, and prepend the title line with Darwin: the latter helps locate things that might need backporting, and the former means that we have an easy-to-find rationale for the patch (one of the nicer things about this new system!). thanks Iain > > FX > >
Re: [PATCH, rs6000] Implement mffscrni pattern
On Thu, Dec 16, 2021 at 9:43 PM HAO CHEN GUI wrote:
>
> Hi,
>This patch defines a pattern for mffscrni. If the RN is a constant, it can
> call
> gen_rs6000_mffscrni directly. The "rs6000-builtin-new.def" defines prototype
> for builtin arguments.
> The pattern "rs6000_set_fpscr_rn" is then broken as the mode of its argument
> is DI while its
> corresponding builtin has a const int argument. The patch also fixed it.
>
>Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
> Is this okay for trunk?
> Any recommendations? Thanks a lot.
Hi, Haochen
I have a question about the mode of the input operand in the new pattern below.
>
> ChangeLog
> 2021-12-17 Haochen Gui
>
> gcc/
> * config/rs6000/predicates.md (u2bit_cint_operand): Defined.
> * config/rs6000/rs6000-call.c
> (rs6000_expand_set_fpscr_rn_builtin): Not copy argument to a reg if
> it's a constant. The pattern for constant can be recognized now.
> * config/rs6000/rs6000.md (UNSPECV_MFFSCRNI): Defined.
> (rs6000_mffscrni): Defined.
> (rs6000_set_fpscr_rn): Change the type of operand[0] form DI to SI.
> Call gen_rs6000_mffscrni when operand[0] is a const int[0,3].
>
> gcc/testsuite/
> * gcc.target/powerpc/mffscrni_p9.c: New testcase for mffscrni.
> * gcc.target/powerpc/test_fpscr_rn_builtin.c: Modify the test cases to
> test mffscrn and mffscrni separately.
>
> patch.diff
> diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
> index f216ffd..b10b4ce 100644
> --- a/gcc/config/rs6000/predicates.md
> +++ b/gcc/config/rs6000/predicates.md
> @@ -219,6 +219,11 @@ (define_predicate "u1bit_cint_operand"
>(and (match_code "const_int")
> (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1")))
>
> +;; Return 1 if op is an unsigned 2-bit constant integer.
> +(define_predicate "u2bit_cint_operand"
> + (and (match_code "const_int")
> + (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 3")))
> +
> ;; Return 1 if op is a unsigned 3-bit constant integer.
> (define_predicate "u3bit_cint_operand"
>(and (match_code "const_int")
> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
> index d9736ea..81261a0 100644
> --- a/gcc/config/rs6000/rs6000-call.c
> +++ b/gcc/config/rs6000/rs6000-call.c
> @@ -9610,13 +9610,15 @@ rs6000_expand_set_fpscr_rn_builtin (enum insn_code
> icode, tree exp)
> compile time if the argument is a variable. The least significant two
> bits of the argument, regardless of type, are used to set the rounding
> mode. All other bits are ignored. */
> - if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode))
> + if (CONST_INT_P (op0))
> {
> - error ("Argument must be a value between 0 and 3.");
> - return const0_rtx;
> + if (!const_0_to_3_operand (op0, VOIDmode))
> + {
> + error ("Argument must be a value between 0 and 3.");
> + return const0_rtx;
> + }
> }
> -
> - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
> + else if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
> op0 = copy_to_mode_reg (mode0, op0);
>
>pat = GEN_FCN (icode) (op0);
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 6bec2bd..291396c 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -177,6 +177,7 @@ (define_c_enum "unspecv"
> UNSPECV_MFFS; Move from FPSCR
> UNSPECV_MFFSL ; Move from FPSCR light instruction version
> UNSPECV_MFFSCRN ; Move from FPSCR float rounding mode
> + UNSPECV_MFFSCRNI; Move from FPSCR float rounding mode with imm
> UNSPECV_MFFSCDRN; Move from FPSCR decimal float rounding mode
> UNSPECV_MTFSF ; Move to FPSCR Fields 8 to 15
> UNSPECV_MTFSF_HI; Move to FPSCR Fields 0 to 7
> @@ -6315,6 +6316,14 @@ (define_insn "rs6000_mffscrn"
> "mffscrn %0,%1"
>[(set_attr "type" "fp")])
>
> +(define_insn "rs6000_mffscrni"
> + [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + (unspec_volatile:DF [(match_operand:DF 1 "u2bit_cint_operand" "n")]
Why is this input operand 1 DFmode? This is a 2 bit integer value.
This pattern is called from rs6000_set_fpscr_rn with an SImode
operand, and it seems that this should be SImode as well.
Thanks, David
> + UNSPECV_MFFSCRNI))]
> + "TARGET_P9_MISC"
> + "mffscrni %0,%1"
> + [(set_attr "type" "fp")])
> +
> (define_insn "rs6000_mffscdrn"
>[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFSCDRN))
> @@ -6324,7 +6333,7 @@ (define_insn "rs6000_mffscdrn"
>[(set_attr "type" "fp")])
>
> (define_expand "rs6000_set_fpscr_rn"
> - [(match_operand:DI 0 "reg_or_cint_operand")]
> + [(match_operand:SI 0 "reg_or_cint_operand")]
>"TARGET_HARD_FLOAT"
>
Re: [PATCH] config.gcc: Obsolete m32c-rtems target
On 12/17/2021 9:10 AM, Joel Sherrill wrote:
---
gcc/config.gcc | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index c8824367b13..fe93a72a16c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -252,6 +252,7 @@ case ${target} in
| cr16-*-* \
| hppa[12]*-*-hpux10*\
| hppa[12]*-*-hpux11*\
+ | m32c-*-rtems* \
)
if test "x$enable_obsolete" != xyes; then
echo "*** Configuration ${target} is obsolete." >&2
OK. Given that last time I tried, I couldn't even get m32c to build
newlib, I'm not terribly surprised you're deprecating it from rtems.
I would support deprecation of m32c-*.
jeff
[PATCH v3] tree-optimization/103759: Use sizetype everywhere for object sizes
Since all computations in tree-object-size are now done in sizetype and
not HOST_WIDE_INT, comparisons with HOST_WIDE_INT based unknown and
initval would be incorrect. Instead, use the sizetype trees directly to
generate and evaluate initval and unknown size values.
gcc/ChangeLog:
PR tree-optimization/103759
* tree-object-size (unknown, initval): Remove functions.
(size_unknown, size_initval, size_unknown_p): Operate directly
on trees.
Signed-off-by: Siddhesh Poyarekar
---
Tested a full bootstrap on x86_64, config=ubsan-bootstrap and i686.
Changes from v2:
- Operate directly on trees as per Jakub's suggestion.
gcc/tree-object-size.c | 27 ++-
1 file changed, 6 insertions(+), 21 deletions(-)
diff --git a/gcc/tree-object-size.c b/gcc/tree-object-size.c
index 71f6b747d05..ee9ea1bfbfd 100644
--- a/gcc/tree-object-size.c
+++ b/gcc/tree-object-size.c
@@ -83,30 +83,13 @@ static bitmap computed[OST_END];
/* Maximum value of offset we consider to be addition. */
static unsigned HOST_WIDE_INT offset_limit;
-/* Initial value of object sizes; zero for maximum and SIZE_MAX for minimum
- object size. */
-
-static inline unsigned HOST_WIDE_INT
-initval (int object_size_type)
-{
- return (object_size_type & OST_MINIMUM) ? HOST_WIDE_INT_M1U : 0;
-}
-
-/* Unknown object size value; it's the opposite of initval. */
-
-static inline unsigned HOST_WIDE_INT
-unknown (int object_size_type)
-{
- return ~initval (object_size_type);
-}
-
/* Return true if VAL is represents an unknown size for OBJECT_SIZE_TYPE. */
static inline bool
size_unknown_p (tree val, int object_size_type)
{
- return (tree_fits_uhwi_p (val)
- && tree_to_uhwi (val) == unknown (object_size_type));
+ return ((object_size_type & OST_MINIMUM)
+ ? integer_zerop (val) : integer_all_onesp (val));
}
/* Return a tree with initial value for OBJECT_SIZE_TYPE. */
@@ -114,7 +97,8 @@ size_unknown_p (tree val, int object_size_type)
static inline tree
size_initval (int object_size_type)
{
- return size_int (initval (object_size_type));
+ return ((object_size_type & OST_MINIMUM)
+ ? TYPE_MAX_VALUE (sizetype) : size_zero_node);
}
/* Return a tree with unknown value for OBJECT_SIZE_TYPE. */
@@ -122,7 +106,8 @@ size_initval (int object_size_type)
static inline tree
size_unknown (int object_size_type)
{
- return size_int (unknown (object_size_type));
+ return ((object_size_type & OST_MINIMUM)
+ ? size_zero_node : TYPE_MAX_VALUE (sizetype));
}
/* Grow object_sizes[OBJECT_SIZE_TYPE] to num_ssa_names. */
--
2.31.1
