Re:[pushed] [PATCH] LoongArch: gcc12: Implement option save/restore.

2024-03-31 Thread chenglulu 

Pushed to r12-10303.

在 2024/3/17 上午10:02, Lulu Cheng 写道:

LTO option streaming and target attributes both require per-function
target configuration, which is achieved via option save/restore.

We implement TARGET_OPTION_{SAVE,RESTORE} to switch the la_target
context in addition to other automatically maintained option states
(via the "Save" option property in the .opt files).

PR target/113233

gcc/ChangeLog:

* config/loongarch/genopts/loongarch.opt.in: Mark options with
the "Save" property.
* config/loongarch/loongarch-opts.cc
(loongarch_update_gcc_opt_status): Update the value of the
la_target to global_options.
* config/loongarch/loongarch-opts.h
(loongarch_update_gcc_opt_status): Add a function declaration.
* config/loongarch/loongarch.cc
(loongarch_option_override_internal): Call the function
loongarch_update_gcc_opt_status.
(loongarch_option_save): New functions.
(loongarch_option_restore): Likewise.
(TARGET_OPTION_SAVE): Define macro.
(TARGET_OPTION_RESTORE): Likewise.
* config/loongarch/loongarch.opt: Regenerate.
---
  gcc/config/loongarch/genopts/loongarch.opt.in | 22 ++--
  gcc/config/loongarch/loongarch-opts.cc| 22 
  gcc/config/loongarch/loongarch-opts.h |  6 
  gcc/config/loongarch/loongarch.cc | 34 +--
  gcc/config/loongarch/loongarch.opt| 22 ++--
  5 files changed, 82 insertions(+), 24 deletions(-)

diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in 
b/gcc/config/loongarch/genopts/loongarch.opt.in
index 420a3941b3b..a3107cb2294 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -58,7 +58,7 @@ EnumValue
  Enum(isa_ext_fpu) String(@@STR_ISA_EXT_FPU64@@) Value(ISA_EXT_FPU64)
  
  m@@OPTSTR_ISA_EXT_FPU@@=

-Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) 
Init(M_OPTION_NOT_SEEN) Save
  -m@@OPTSTR_ISA_EXT_FPU@@=FPU  Generate code for the given FPU.
  
  m@@OPTSTR_ISA_EXT_FPU@@=@@STR_ISA_EXT_FPU0@@

@@ -92,11 +92,11 @@ EnumValue
  Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464)
  
  m@@OPTSTR_ARCH@@=

-Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) 
Init(M_OPTION_NOT_SEEN) Save
  -m@@OPTSTR_ARCH@@=PROCESSOR   Generate code for the given PROCESSOR ISA.
  
  m@@OPTSTR_TUNE@@=

-Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) 
Init(M_OPTION_NOT_SEEN) Save
  -m@@OPTSTR_TUNE@@=PROCESSOR   Generate optimized code for PROCESSOR.
  
  
@@ -127,31 +127,31 @@ int la_opt_abi_ext = M_OPTION_NOT_SEEN
  
  
  mbranch-cost=

-Target RejectNegative Joined UInteger Var(loongarch_branch_cost)
+Target RejectNegative Joined UInteger Var(loongarch_branch_cost) Save
  -mbranch-cost=COSTSet the cost of branches to roughly COST instructions.
  
  mcheck-zero-division

-Target Mask(CHECK_ZERO_DIV)
+Target Mask(CHECK_ZERO_DIV) Save
  Trap on integer divide by zero.
  
  mcond-move-int

-Target Var(TARGET_COND_MOVE_INT) Init(1)
+Target Var(TARGET_COND_MOVE_INT) Init(1) Save
  Conditional moves for integral are enabled.
  
  mcond-move-float

-Target Var(TARGET_COND_MOVE_FLOAT) Init(1)
+Target Var(TARGET_COND_MOVE_FLOAT) Init(1) Save
  Conditional moves for float are enabled.
  
  mmemcpy

-Target Mask(MEMCPY)
+Target Mask(MEMCPY) Save
  Prevent optimizing block moves, which is also the default behavior of -Os.
  
  mstrict-align

-Target Var(TARGET_STRICT_ALIGN) Init(0)
+Target Var(TARGET_STRICT_ALIGN) Init(0) Save
  Do not generate unaligned memory accesses.
  
  mmax-inline-memcpy-size=

-Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) 
Init(1024)
+Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) 
Init(1024) Save
  -mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default 
is 1024.
  
  ; The code model option names for -mcmodel.

@@ -175,7 +175,7 @@ EnumValue
  Enum(cmodel) String(@@STR_CMODEL_EXTREME@@) Value(CMODEL_EXTREME)
  
  mcmodel=

-Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) 
Init(CMODEL_NORMAL)
+Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) 
Init(CMODEL_NORMAL) Save
  Specify the code model.
  
  mrelax

diff --git a/gcc/config/loongarch/loongarch-opts.cc 
b/gcc/config/loongarch/loongarch-opts.cc
index eb9c2a52f9e..b55baeccd2f 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -575,3 +575,25 @@ multilib_enabled_abi_list ()
  
return XOBFINISH (_obstack, const char *);

  }
+
+/* option status feedback for "gcc --help=target

Re: [pushed][PATCH] LoongArch: gcc13: Implement option save/restore.

2024-03-31 Thread chenglulu 

Pushed to r13-8545.

在 2024/3/17 上午10:02, Lulu Cheng 写道:

LTO option streaming and target attributes both require per-function
target configuration, which is achieved via option save/restore.

We implement TARGET_OPTION_{SAVE,RESTORE} to switch the la_target
context in addition to other automatically maintained option states
(via the "Save" option property in the .opt files).

PR target/113233

gcc/ChangeLog:

* config/loongarch/genopts/loongarch.opt.in: Mark options with
the "Save" property.
* config/loongarch/loongarch-opts.cc
(loongarch_update_gcc_opt_status): Update the value of the
la_target to global_options.
* config/loongarch/loongarch-opts.h
(loongarch_update_gcc_opt_status): Add a function declaration.
* config/loongarch/loongarch.cc
(loongarch_option_override_internal): Call the function
loongarch_update_gcc_opt_status.
(loongarch_option_save): New functions.
(loongarch_option_restore): Likewise.
(TARGET_OPTION_SAVE): Define macro.
(TARGET_OPTION_RESTORE): Likewise.
* config/loongarch/loongarch.opt: Regenerate.
---
  gcc/config/loongarch/genopts/loongarch.opt.in | 24 ++---
  gcc/config/loongarch/loongarch-opts.cc| 22 
  gcc/config/loongarch/loongarch-opts.h |  6 
  gcc/config/loongarch/loongarch.cc | 34 +--
  gcc/config/loongarch/loongarch.opt| 24 ++---
  5 files changed, 84 insertions(+), 26 deletions(-)

diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in 
b/gcc/config/loongarch/genopts/loongarch.opt.in
index 76acd35d39c..aea4f2a4f61 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -58,7 +58,7 @@ EnumValue
  Enum(isa_ext_fpu) String(@@STR_ISA_EXT_FPU64@@) Value(ISA_EXT_FPU64)
  
  m@@OPTSTR_ISA_EXT_FPU@@=

-Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) 
Init(M_OPTION_NOT_SEEN) Save
  -m@@OPTSTR_ISA_EXT_FPU@@=FPU  Generate code for the given FPU.
  
  m@@OPTSTR_ISA_EXT_FPU@@=@@STR_ISA_EXT_FPU0@@

@@ -92,11 +92,11 @@ EnumValue
  Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464)
  
  m@@OPTSTR_ARCH@@=

-Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) 
Init(M_OPTION_NOT_SEEN) Save
  -m@@OPTSTR_ARCH@@=PROCESSOR   Generate code for the given PROCESSOR ISA.
  
  m@@OPTSTR_TUNE@@=

-Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) 
Init(M_OPTION_NOT_SEEN)
+Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) 
Init(M_OPTION_NOT_SEEN) Save
  -m@@OPTSTR_TUNE@@=PROCESSOR   Generate optimized code for PROCESSOR.
  
  
@@ -127,31 +127,31 @@ int la_opt_abi_ext = M_OPTION_NOT_SEEN
  
  
  mbranch-cost=

-Target RejectNegative Joined UInteger Var(loongarch_branch_cost)
+Target RejectNegative Joined UInteger Var(loongarch_branch_cost) Save
  -mbranch-cost=COSTSet the cost of branches to roughly COST instructions.
  
  mcheck-zero-division

-Target Mask(CHECK_ZERO_DIV)
+Target Mask(CHECK_ZERO_DIV) Save
  Trap on integer divide by zero.
  
  mcond-move-int

-Target Var(TARGET_COND_MOVE_INT) Init(1)
+Target Var(TARGET_COND_MOVE_INT) Init(1) Save
  Conditional moves for integral are enabled.
  
  mcond-move-float

-Target Var(TARGET_COND_MOVE_FLOAT) Init(1)
+Target Var(TARGET_COND_MOVE_FLOAT) Init(1) Save
  Conditional moves for float are enabled.
  
  mmemcpy

-Target Mask(MEMCPY)
+Target Mask(MEMCPY) Save
  Prevent optimizing block moves, which is also the default behavior of -Os.
  
  mstrict-align

-Target Var(TARGET_STRICT_ALIGN) Init(0)
+Target Var(TARGET_STRICT_ALIGN) Init(0) Save
  Do not generate unaligned memory accesses.
  
  mmax-inline-memcpy-size=

-Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) 
Init(1024)
+Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) 
Init(1024) Save
  -mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default 
is 1024.
  
  mexplicit-relocs

@@ -182,11 +182,11 @@ EnumValue
  Enum(cmodel) String(@@STR_CMODEL_EXTREME@@) Value(CMODEL_EXTREME)
  
  mcmodel=

-Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) 
Init(CMODEL_NORMAL)
+Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) 
Init(CMODEL_NORMAL) Save
  Specify the code model.
  
  mdirect-extern-access

-Target Var(TARGET_DIRECT_EXTERN_ACCESS) Init(0)
+Target Var(TARGET_DIRECT_EXTERN_ACCESS) Init(0) Save
  Avoid using the GOT to access external symbols.
  
  mrelax

diff --git a/gcc/config/loongarch/loongarch-opts.cc 
b/gcc/config/loongarch/loongarch-opts.cc
index a52e25236ea..e158de9a12f 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc

[PATCH] Regenerate loongarch.opt.urls.

2024-03-31 Thread Lulu Cheng 
Fixes: d28ea8e5a704 ("LoongArch: Split loongarch_option_override_internal
  into smaller procedures")

gcc/ChangeLog:

* config/loongarch/loongarch.opt.urls: Regenerate.
---
 gcc/config/loongarch/loongarch.opt.urls | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.opt.urls 
b/gcc/config/loongarch/loongarch.opt.urls
index c78bbfea2da..8e16304b66a 100644
--- a/gcc/config/loongarch/loongarch.opt.urls
+++ b/gcc/config/loongarch/loongarch.opt.urls
@@ -51,10 +51,10 @@ 
UrlSuffix(gcc/LoongArch-Options.html#index-mexplicit-relocs-1)
 mexplicit-relocs
 UrlSuffix(gcc/LoongArch-Options.html#index-mexplicit-relocs-1)
 
-mrecip
+mrecip=
 UrlSuffix(gcc/LoongArch-Options.html#index-mrecip)
 
-mrecip=
+mrecip
 UrlSuffix(gcc/LoongArch-Options.html#index-mrecip)
 
 ; skipping UrlSuffix for 'mcmodel=' due to finding no URLs
@@ -64,3 +64,18 @@ 
UrlSuffix(gcc/LoongArch-Options.html#index-mdirect-extern-access)
 
 ; skipping UrlSuffix for 'mrelax' due to finding no URLs
 
+mfrecipe
+UrlSuffix(gcc/LoongArch-Options.html#index-mfrecipe)
+
+mdiv32
+UrlSuffix(gcc/LoongArch-Options.html#index-mdiv32)
+
+mlam-bh
+UrlSuffix(gcc/LoongArch-Options.html#index-mlam-bh)
+
+mlamcas
+UrlSuffix(gcc/LoongArch-Options.html#index-mlamcas)
+
+mld-seq-sa
+UrlSuffix(gcc/LoongArch-Options.html#index-mld-seq-sa)
+
-- 
2.39.3

Re: [PATCH] LoongArch: Increase division costs

2024-03-31 Thread Xi Ruoyao 
On Mon, 2024-04-01 at 10:22 +0800, chenglulu wrote:
> 
> 在 2024/4/1 上午9:29, Xi Ruoyao 写道:
> > On Fri, 2024-03-29 at 09:23 +0800, chenglulu wrote:
> > 
> > > I tested spec2006. In the floating-point program, the test items with 
> > > large
> > > 
> > > fluctuations are removed, and the rest is basically unchanged.
> > > 
> > > The fixed-point 464.h264ref (10,10) was 6.7% higher than (5,5) and 
> > > (10,22).
> > So IIUC (10,10) is better than (5,5), (10,22), and the originally
> > proposed (14,22)?  Then should I make a change to make all 4 costs (SF,
> > DF, SI, DI) 10?
> 
> I think this may require the analysis of the spec's test case. I took a 
> look at the test results again,
> 
> where the scores of SPEC INT 462.libquantum fluctuated greatly, but the 
> combination of (10,22)
> 
> showed an overall upward trend compared to the scores of the other two
> combinations.
> 
> I don't know if (10,22) this combination happens to have the kind of 
> test cases in the changelog.
> 
> So can we change it together in GCC15?

Ok.  Abandoning this patch then.

-- 
Xi Ruoyao 
School of Aerospace Science and Technology, Xidian University

Re: [PATCH] LoongArch: Increase division costs

2024-03-31 Thread chenglulu 



在 2024/4/1 上午9:29, Xi Ruoyao 写道:

On Fri, 2024-03-29 at 09:23 +0800, chenglulu wrote:


I tested spec2006. In the floating-point program, the test items with large

fluctuations are removed, and the rest is basically unchanged.

The fixed-point 464.h264ref (10,10) was 6.7% higher than (5,5) and (10,22).

So IIUC (10,10) is better than (5,5), (10,22), and the originally
proposed (14,22)?  Then should I make a change to make all 4 costs (SF,
DF, SI, DI) 10?


I think this may require the analysis of the spec's test case. I took a 
look at the test results again,


where the scores of SPEC INT 462.libquantum fluctuated greatly, but the 
combination of (10,22)


showed an overall upward trend compared to the scores of the other two 
combinations.


I don't know if (10,22) this combination happens to have the kind of 
test cases in the changelog.


So can we change it together in GCC15?



I'd still want DI % 17 to be reduced as reciprocal sequence (but
not SI % 17) since DI % (smaller const) is quite important for
some workloads like competitive programming.  However "adapting with
different modulos" is not possible w/o refactoring generic code so it
must be deferred to at least GCC 15.

Re: [PATCH] LoongArch: Increase division costs

2024-03-31 Thread Xi Ruoyao 
On Fri, 2024-03-29 at 09:23 +0800, chenglulu wrote:

> I tested spec2006. In the floating-point program, the test items with large
> 
> fluctuations are removed, and the rest is basically unchanged.
> 
> The fixed-point 464.h264ref (10,10) was 6.7% higher than (5,5) and (10,22).

So IIUC (10,10) is better than (5,5), (10,22), and the originally
proposed (14,22)?  Then should I make a change to make all 4 costs (SF,
DF, SI, DI) 10?

I'd still want DI % 17 to be reduced as reciprocal sequence (but
not SI % 17) since DI % (smaller const) is quite important for
some workloads like competitive programming.  However "adapting with
different modulos" is not possible w/o refactoring generic code so it
must be deferred to at least GCC 15.

-- 
Xi Ruoyao 
School of Aerospace Science and Technology, Xidian University

Re: [pushed][PATCH v4] LoongArch: Split loongarch_option_override_internal into smaller procedures

2024-03-31 Thread chenglulu 

Pushed to r14-9737.

在 2024/3/30 下午4:43, Yang Yujie 写道:

gcc/ChangeLog:

* config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]recip as
aliases to -mrecip={all,none}, respectively.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-def.h (ABI_FPU_64): Rename to...
(ABI_FPU64_P): ...this.
(ABI_FPU_32): Rename to...
(ABI_FPU32_P): ...this.
(ABI_FPU_NONE): Rename to...
(ABI_NOFPU_P): ...this.
(ABI_LP64_P): Define.
* config/loongarch/loongarch.cc (loongarch_init_print_operand_punct):
Merged into loongarch_global_init.
(loongarch_cpu_option_override): Renamed to
loongarch_target_option_override.
(loongarch_option_override_internal): Move the work after
loongarch_config_target into loongarch_target_option_override.
(loongarch_global_init): Define.
(INIT_TARGET_FLAG): Move to loongarch-opts.cc.
(loongarch_option_override): Call loongarch_global_init
separately.
* config/loongarch/loongarch-opts.cc (loongarch_parse_mrecip_scheme):
Split the parsing of -mrecip= from
loongarch_option_override_internal.
(loongarch_generate_mrecip_scheme): Define. Split from
loongarch_option_override_internal.
(loongarch_target_option_override): Define. Renamed from
loongarch_cpu_option_override.
(loongarch_init_misc_options): Define. Split from
loongarch_option_override_internal.
(INIT_TARGET_FLAG): Move from loongarch.cc.
* config/loongarch/loongarch-opts.h (loongarch_target_option_override):
New prototype.
(loongarch_parse_mrecip_scheme): New prototype.
(loongarch_init_misc_options): New prototype.
(TARGET_ABI_LP64): Simplify with ABI_LP64_P.
* config/loongarch/loongarch.h (TARGET_RECIP_DIV): Simplify.
Do not reference specific CPU architecture (LA664).
(TARGET_RECIP_SQRT): Same.
(TARGET_RECIP_RSQRT): Same.
(TARGET_RECIP_VEC_DIV): Same.
(TARGET_RECIP_VEC_SQRT): Same.
(TARGET_RECIP_VEC_RSQRT): Same.
---
  gcc/config/loongarch/genopts/loongarch.opt.in |   8 +-
  gcc/config/loongarch/loongarch-def.h  |  11 +-
  gcc/config/loongarch/loongarch-opts.cc| 253 ++
  gcc/config/loongarch/loongarch-opts.h |  27 +-
  gcc/config/loongarch/loongarch.cc | 253 +++---
  gcc/config/loongarch/loongarch.h  |  18 +-
  gcc/config/loongarch/loongarch.opt|   8 +-
  7 files changed, 342 insertions(+), 236 deletions(-)

diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in 
b/gcc/config/loongarch/genopts/loongarch.opt.in
index 02f918053f5..a77893d31d9 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -197,14 +197,14 @@ mexplicit-relocs
  Target Alias(mexplicit-relocs=, always, none)
  Use %reloc() assembly operators (for backward compatibility).
  
-mrecip

-Target RejectNegative Var(la_recip) Save
-Generate approximate reciprocal divide and square root for better throughput.
-
  mrecip=
  Target RejectNegative Joined Var(la_recip_name) Save
  Control generation of reciprocal estimates.
  
+mrecip

+Target Alias(mrecip=, all, none)
+Generate approximate reciprocal divide and square root for better throughput.
+
  ; The code model option names for -mcmodel.
  Enum
  Name(cmodel) Type(int)
diff --git a/gcc/config/loongarch/loongarch-def.h 
b/gcc/config/loongarch/loongarch-def.h
index 2dbf006d013..0cbf9476690 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -90,11 +90,16 @@ extern loongarch_def_array
  
  #define TO_LP64_ABI_BASE(C) (C)
  
-#define ABI_FPU_64(abi_base) \

+#define ABI_LP64_P(abi_base) \
+  (abi_base == ABI_BASE_LP64D \
+   || abi_base == ABI_BASE_LP64F \
+   || abi_base == ABI_BASE_LP64S)
+
+#define ABI_FPU64_P(abi_base) \
(abi_base == ABI_BASE_LP64D)
-#define ABI_FPU_32(abi_base) \
+#define ABI_FPU32_P(abi_base) \
(abi_base == ABI_BASE_LP64F)
-#define ABI_FPU_NONE(abi_base) \
+#define ABI_NOFPU_P(abi_base) \
(abi_base == ABI_BASE_LP64S)
  
  
diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc

index 627f9148adf..e600f08f03b 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3.  If not see
  #include "coretypes.h"
  #include "tm.h"
  #include "obstack.h"
+#include "opts.h"
  #include "diagnostic-core.h"
  
  #include "loongarch-cpu.h"

@@ -32,8 +33,12 @@ along with GCC; see the file COPYING3.  If not see
  #include "loongarch-str.h"
  #include "loongarch-def.h"
  
+/* Target configuration */

  struct loongarch_target la_target;
  
+/* RTL cost information */

+const struct loongarch_rtx_cost_data *loongarch_cost;
+
  /* ABI-related

Re:[pushed] [PATCH] LoongArch: Add descriptions of the compilation options.

2024-03-31 Thread chenglulu 

Pushed to r14-9736.

在 2024/3/30 下午3:58, Lulu Cheng 写道:

Add descriptions for the compilation options '-mfrecipe' '-mdiv32'
'-mlam-bh' '-mlamcas' and '-mld-seq-sa'.

gcc/ChangeLog:

* doc/invoke.texi: Add descriptions for the compilation
options.
---
  gcc/doc/invoke.texi | 45 +++--
  1 file changed, 43 insertions(+), 2 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c584664e168..942103c23f5 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1058,8 +1058,9 @@ Objective-C and Objective-C++ Dialects}.
  -mmax-inline-memcpy-size=@var{n}
  -mexplicit-relocs=@var{style} -mexplicit-relocs -mno-explicit-relocs
  -mdirect-extern-access -mno-direct-extern-access
--mcmodel=@var{code-model} -mrelax -mpass-mrelax-to-as}
--mrecip  -mrecip=@var{opt}
+-mcmodel=@var{code-model} -mrelax -mpass-mrelax-to-as
+-mrecip  -mrecip=@var{opt} -mfrecipe -mno-frecipe -mdiv32 -mno-div32
+-mlam-bh -mno-lam-bh -mlamcas -mno-lamcas -mld-seq-sa -mno-ld-seq-sa}
  
  @emph{M32R/D Options}

  @gccoptlist{-m32r2  -m32rx  -m32r
@@ -27095,6 +27096,46 @@ Enable the approximation for vectorized reciprocal 
square root.
  So, for example, @option{-mrecip=all,!sqrt} enables
  all of the reciprocal approximations, except for scalar square root.
  
+@opindex mfrecipe

+@opindex mno-frecipe
+@item -mfrecipe
+@itemx -mno-frecipe
+Use (do not use) @code{frecipe.@{s/d@}} and @code{frsqrte.@{s/d@}}
+instructions.  When build with @option{-march=la664}, it is enabled by default.
+The default is @option{-mno-frecipe}.
+
+@opindex mdiv32
+@opindex mno-div32
+@item -mdiv32
+@itemx -mno-div32
+Use (do not use) @code{div.w[u]} and @code{mod.w[u]} instructions with input
+not sign-extended.  When build with @option{-march=la664}, it is enabled by
+default.  The default is @option{-mno-div32}.
+
+@opindex mlam-bh
+@opindex mno-lam-bh
+@item -mlam-bh
+@itemx -mno-lam-bh
+Use (do not use) @code{am@{swap/add@}[_db].@{b/h@}} instructions.  When build
+with @option{-march=la664}, it is enabled by default.  The default is
+@option{-mno-lam-bh}.
+
+@opindex mlamcas
+@opindex mno-lamcas
+@item -mlamcas
+@itemx -mno-lamcas
+Use (do not use) @code{amcas[_db].@{b/h/w/d@}} instructions.  When build with
+@option{-march=la664}, it is enabled by default.  The default is
+@option{-mno-lamcas}.
+
+@opindex mld-seq-sa
+@opindex mno-ld-seq-sa
+@item -mld-seq-sa
+@itemx -mno-ld-seq-sa
+Whether a load-load barrier (@code{dbar 0x700}) is needed.  When build with
+@option{-march=la664}, it is enabled by default.  The default is
+@option{-mno-ld-seq-sa}, the load-load barrier is needed.
+
  @item loongarch-vect-unroll-limit
  The vectorizer will use available tuning information to determine whether it
  would be beneficial to unroll the main vectorized loop and by how much.  This

Re: [committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler model

2024-03-31 Thread Palmer Dabbelt 

On Sun, 31 Mar 2024 09:53:46 PDT (-0700), Jeff Law wrote:

The test for the recently added XiangShan Nanhu microarchitecture is
failing because the scheduler description does not have entries for
certain insn types.

I'm adding  branch, jalr, ret and sfb_alu to the scheduler description,
that's enough to get the trivial test to pass.  However, I strongly
suspect running any significant code through the compiler when
scheduling for this microarchitecture will trigger faults.


We should probably add a build with this a the default pipeline model to 
the lists of tests, even if it's just something we run every few weeks 
it'd still be good.



Basically we have checking now that will fault if we have an insn in the
IL without an associated type or if we have an insn in the IL that does
not map to an insn reservation in the scheduler model.  We were tripping
the latter assertion for one of those branch types.  My suspicion is
many insn types aren't handled by that DFA.

The branch insns were pretty obvious and easy to fix.  But someone with
more experience with the uarch needs to do an audit to ensure that all
insn types map to an insn reservation.

Pushing this to the trunk.

Jeff



commit 08eaafadd5beaa56beb2d1fceca9f97eeb0219ba
Author: Jeff Law 
Date:   Sun Mar 31 10:51:17 2024 -0600

[committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler 
model

The test for the recently added XiangShan Nanhu microarchitecture is failing
because the scheduler description does not have entries for certain insn 
types.

I'm adding  branch, jalr, ret and sfb_alu to the scheduler description, 
that's
enough to get the trivial test to pass.  However, I strongly suspect running
any significant code through the compiler when scheduling for this
microarchitecture will trigger faults.

Basically we have checking now that will fault if we have an insn in the IL
without an associated type or if we have an insn in the IL that does not 
map to
an insn reservation in the scheduler model.  We were tripping the latter
assertion for one of those branch types.  My suspicion is many insn types
aren't handled by that DFA.

The branch insns were pretty obvious and easy to fix.  But someone with more
experience with the uarch needs to do an audit to ensure that all insn types
map to an insn reservation.

gcc/
* config/riscv/xiangshan.md (xiangshan_jump): Add branch, jalr, ret
and sfb_alu.

diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md
index 381c3ce1428..76539d332b8 100644
--- a/gcc/config/riscv/xiangshan.md
+++ b/gcc/config/riscv/xiangshan.md
@@ -70,7 +70,7 @@ (define_insn_reservation "xiangshan_fpstore" 1

 (define_insn_reservation "xiangshan_jump" 1
   (and (eq_attr "tune" "xiangshan")
-   (eq_attr "type" "jump,call,auipc,unknown"))
+   (eq_attr "type" "jump,call,auipc,unknown,branch,jalr,ret,sfb_alu"))
   "xs_jmp_rs")

 (define_insn_reservation "xiangshan_i2f" 3

[committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler model

2024-03-31 Thread Jeff Law 
The test for the recently added XiangShan Nanhu microarchitecture is 
failing because the scheduler description does not have entries for 
certain insn types.


I'm adding  branch, jalr, ret and sfb_alu to the scheduler description, 
that's enough to get the trivial test to pass.  However, I strongly 
suspect running any significant code through the compiler when 
scheduling for this microarchitecture will trigger faults.


Basically we have checking now that will fault if we have an insn in the 
IL without an associated type or if we have an insn in the IL that does 
not map to an insn reservation in the scheduler model.  We were tripping 
the latter assertion for one of those branch types.  My suspicion is 
many insn types aren't handled by that DFA.


The branch insns were pretty obvious and easy to fix.  But someone with 
more experience with the uarch needs to do an audit to ensure that all 
insn types map to an insn reservation.


Pushing this to the trunk.

Jeff



commit 08eaafadd5beaa56beb2d1fceca9f97eeb0219ba
Author: Jeff Law 
Date:   Sun Mar 31 10:51:17 2024 -0600

[committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler 
model

The test for the recently added XiangShan Nanhu microarchitecture is failing
because the scheduler description does not have entries for certain insn 
types.

I'm adding  branch, jalr, ret and sfb_alu to the scheduler description, 
that's
enough to get the trivial test to pass.  However, I strongly suspect running
any significant code through the compiler when scheduling for this
microarchitecture will trigger faults.

Basically we have checking now that will fault if we have an insn in the IL
without an associated type or if we have an insn in the IL that does not 
map to
an insn reservation in the scheduler model.  We were tripping the latter
assertion for one of those branch types.  My suspicion is many insn types
aren't handled by that DFA.

The branch insns were pretty obvious and easy to fix.  But someone with more
experience with the uarch needs to do an audit to ensure that all insn types
map to an insn reservation.

gcc/
* config/riscv/xiangshan.md (xiangshan_jump): Add branch, jalr, ret
and sfb_alu.

diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md
index 381c3ce1428..76539d332b8 100644
--- a/gcc/config/riscv/xiangshan.md
+++ b/gcc/config/riscv/xiangshan.md
@@ -70,7 +70,7 @@ (define_insn_reservation "xiangshan_fpstore" 1
 
 (define_insn_reservation "xiangshan_jump" 1
   (and (eq_attr "tune" "xiangshan")
-   (eq_attr "type" "jump,call,auipc,unknown"))
+   (eq_attr "type" "jump,call,auipc,unknown,branch,jalr,ret,sfb_alu"))
   "xs_jmp_rs")
 
 (define_insn_reservation "xiangshan_i2f" 3

[Patch, fortran] PR106999 [11/12/13/14 Regression] ICE tree check: expected record_type or union_type or qual_union_type, have function_type in gfc_class_data_get, at fortran/trans-expr.cc:233

2024-03-31 Thread Paul Richard Thomas 
This regression has a relatively simple fix. The passing of a subroutine
procedure pointer component to a dummy variable was being missed
completely. The error has been added. Conversely, an error was generated
for a procedure pointer variable but no use was being made of the
interface, if one was available. This has been corrected.

OK for mainline and backporting in a couple of weeks?

Paul

Fortran: Add error for subroutine passed to a variable dummy [PR106999]

2024-03-31  Paul Thomas  

gcc/fortran
PR fortran/106999
*interface.cc (gfc_compare_interfaces): Add error for a
subroutine proc pointer passed to a variable formal.
(compare_parameter): If a procedure pointer is being passed to
a non-procedure formal arg, and there is an an interface, use
gfc_compare_interfaces to check and provide a more useful error
message.

gcc/testsuite/
PR fortran/106999
* gfortran.dg/pr106999.f90: New test.
diff --git a/gcc/fortran/interface.cc b/gcc/fortran/interface.cc
index 7b86a338bc1..bf151dae743 100644
--- a/gcc/fortran/interface.cc
+++ b/gcc/fortran/interface.cc
@@ -1789,6 +1789,14 @@ gfc_compare_interfaces (gfc_symbol *s1, gfc_symbol *s2, const char *name2,
   return false;
 }

+  if (s2->attr.subroutine && s1->attr.flavor == FL_VARIABLE)
+{
+  if (errmsg != NULL)
+	snprintf (errmsg, err_len, "subroutine proc pointer '%s' passed "
+		  "to dummy variable '%s'", name2, s1->name);
+  return false;
+}
+
   /* Do strict checks on all characteristics
  (for dummy procedures and procedure pointer assignments).  */
   if (!generic_flag && strict_flag)
@@ -2425,12 +2433,22 @@ compare_parameter (gfc_symbol *formal, gfc_expr *actual,
 {
   gfc_symbol *act_sym = actual->symtree->n.sym;

-  if (formal->attr.flavor != FL_PROCEDURE)
+  if (formal->attr.flavor != FL_PROCEDURE && !act_sym->ts.interface)
 	{
 	  if (where)
 	gfc_error ("Invalid procedure argument at %L", >where);
 	  return false;
 	}
+  else if (act_sym->ts.interface
+	   && !gfc_compare_interfaces (formal, act_sym->ts.interface,
+	   act_sym->name, 0, 1, err,
+	   sizeof(err),NULL, NULL))
+	{
+	  if (where)
+	gfc_error_opt (0, "Interface mismatch in dummy procedure %qs at %L:"
+			   " %s", formal->name, >where, err);
+	  return false;
+	}

   if (!gfc_compare_interfaces (formal, act_sym, act_sym->name, 0, 1, err,
    sizeof(err), NULL, NULL))
diff --git a/gcc/testsuite/gfortran.dg/pr106999.f90 b/gcc/testsuite/gfortran.dg/pr106999.f90
new file mode 100644
index 000..b3f1d7741f3
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr106999.f90
@@ -0,0 +1,33 @@
+! { dg-do compile }
+! Test the fix for PR106999
+! Contributed by Gerhard Steinmetz  
+program p
+   type t
+  integer :: i
+  procedure(g), pointer :: f
+   end type
+   class(t), allocatable :: y, z
+   procedure(g), pointer :: ff
+   allocate (z)
+   z%i = 42
+   z%f => g
+   ff => g
+   call r(z%f)
+   call s(z%f) ! { dg-error "Interface mismatch in dummy procedure" }
+   call s(ff)  ! { dg-error "Interface mismatch in dummy procedure" }
+contains
+   subroutine g(x)
+  class(t) :: x
+  x%i = 84
+   end
+   subroutine r(x)
+  procedure(g) :: x
+  print *, "in r"
+  allocate (y)
+  call x(y)
+  print *, y%i
+   end
+   subroutine s(x)
+  class(*) :: x
+   end subroutine
+end

Re: [Patch, fortran] PR112407 - [13/14 Regression] Fix for PR37336 triggers an ICE in gfc_format_decoder while constructing a vtab

2024-03-31 Thread Paul Richard Thomas 
Hi Harald,

>
> I had only a quick glance at your patch.  I guess you unintentionally
> forgot to remove those parts that you already committed for PR110987,
> along with the finalize-testcases.
>

Guilty as charged. I guess I got out of the wrong side of the bed :-)

>
> I am still trying to find the precise paragraph in the standard
> you refer to regarding INTENT(OUT) and default initialization.
>

Page 114 of the draft F2023 standard:
"The INTENT (OUT) attribute for a nonpointer dummy argument specifies that
the dummy argument becomes undefined on invocation of the procedure, except
for any subcomponents that are default-initialized (7.5.4.6)."
With the fix, gfortran behaves in the same way as ifort and nagfor.

On rereading the patch, I think that s/"and use the passed value"/"and
leave undefined"/ or some such is in order.


> While at it, I think I found a minor nit in testcase pr112407a.f90:
> component x%i appears undefined the first time it is printed.
>

Fixed - thanks for pointing it out.

A correct patch is attached.

Thanks for looking at the previous, overloaded version.

Paul



>
> > 2024-03-30  Paul Thomas  
> >
> > gcc/fortran
> > PR fortran/112407
> > *resolve.cc (resolve_procedure_expression): Change the test for
> > for recursion in the case of hidden procedures from modules.
> > (resolve_typebound_static): Add warning for possible recursive
> > calls to typebound procedures.
> > * trans-expr.cc (gfc_trans_class_init_assign): Do not apply
> > default initializer to class dummy where component initializers
> > are all null.
> >
> > gcc/testsuite/
> > PR fortran/112407
> > * gfortran.dg/pr112407a.f90: New test.
> > * gfortran.dg/pr112407b.f90: New test.
> >
>
>
diff --git a/gcc/fortran/resolve.cc b/gcc/fortran/resolve.cc
index 50d51b06c92..43315a6a550 100644
--- a/gcc/fortran/resolve.cc
+++ b/gcc/fortran/resolve.cc
@@ -1963,12 +1963,20 @@ resolve_procedure_expression (gfc_expr* expr)
   || (sym->attr.function && sym->result == sym))
 return true;

-  /* A non-RECURSIVE procedure that is used as procedure expression within its
+   /* A non-RECURSIVE procedure that is used as procedure expression within its
  own body is in danger of being called recursively.  */
   if (is_illegal_recursion (sym, gfc_current_ns))
-gfc_warning (0, "Non-RECURSIVE procedure %qs at %L is possibly calling"
-		 " itself recursively.  Declare it RECURSIVE or use"
-		 " %<-frecursive%>", sym->name, >where);
+{
+  if (sym->attr.use_assoc && expr->symtree->name[0] == '@')
+	gfc_warning (0, "Non-RECURSIVE procedure %qs from module %qs is "
+		 " possibly calling itself recursively in procedure %qs. "
+		 " Declare it RECURSIVE or use %<-frecursive%>",
+		 sym->name, sym->module, gfc_current_ns->proc_name->name);
+  else
+	gfc_warning (0, "Non-RECURSIVE procedure %qs at %L is possibly calling"
+		 " itself recursively.  Declare it RECURSIVE or use"
+		 " %<-frecursive%>", sym->name, >where);
+}

   return true;
 }
@@ -6820,6 +6828,13 @@ resolve_typebound_static (gfc_expr* e, gfc_symtree** target,
   if (st)
 	*target = st;
 }
+
+  if (is_illegal_recursion ((*target)->n.sym, gfc_current_ns)
+  && !e->value.compcall.tbp->deferred)
+gfc_warning (0, "Non-RECURSIVE procedure %qs at %L is possibly calling"
+		 " itself recursively.  Declare it RECURSIVE or use"
+		 " %<-frecursive%>", (*target)->n.sym->name, >where);
+
   return true;
 }

diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 76bed9830c4..f3fcba2bd59 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -1719,6 +1719,7 @@ gfc_trans_class_init_assign (gfc_code *code)
   tree tmp;
   gfc_se dst,src,memsz;
   gfc_expr *lhs, *rhs, *sz;
+  gfc_component *cmp;

   gfc_start_block ();

@@ -1735,6 +1736,21 @@ gfc_trans_class_init_assign (gfc_code *code)
   /* The _def_init is always scalar.  */
   rhs->rank = 0;

+  /* Check def_init for initializers.  If this is a dummy with all default
+ initializer components NULL, return NULL_TREE and use the passed value as
+ required by F2018(8.5.10).  */
+  if (!lhs->ref && lhs->symtree->n.sym->attr.dummy)
+{
+  cmp = rhs->ref->next->u.c.component->ts.u.derived->components;
+  for (; cmp; cmp = cmp->next)
+	{
+	  if (cmp->initializer)
+	break;
+	  else if (!cmp->next)
+	return build_empty_stmt (input_location);
+	}
+}
+
   if (code->expr1->ts.type == BT_CLASS
   && CLASS_DATA (code->expr1)->attr.dimension)
 {
diff --git a/gcc/testsuite/gfortran.dg/pr112407a.f90 b/gcc/testsuite/gfortran.dg/pr112407a.f90
new file mode 100644
index 000..470f4191611
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr112407a.f90
@@ -0,0 +1,71 @@
+! { dg-do run }
+! Test of an issue found in the investigation of PR112407
+! Contributed by Tomas Trnka  
+!
+module m
+  private new_t
+
+  type s
+procedure(),pointer,nopass :: op
+  end type
+
+  type :: t
+integer :: i
+type (s) :: s
+

RE: [PATCH] RISC-V: Fix misspelled term builtin in error message

2024-03-31 Thread Li, Pan2 
Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Sunday, March 31, 2024 9:05 AM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang 

Subject: Re: [PATCH] RISC-V: Fix misspelled term builtin in error message

lgtm

On Sat, Mar 30, 2024 at 8:07 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to fix below misspelled term in error message.
>
> ../../gcc/config/riscv/riscv-vector-builtins.cc:4592:16: error:
> misspelled term 'builtin function' in format; use 'built-in function' instead 
> [-Werror=format-diag]
>  4592 |   "builtin function %qE requires the V ISA extension", 
> exp);
>
> The below tests are passed for this patch.
> * The riscv regression test on rvv.exp and riscv.exp.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
> the term built-in over builtin.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c:
> Adjust test dg-error.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c:
> Ditto.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-vector-builtins.cc   | 2 +-
>  .../riscv/rvv/base/target_attribute_v_with_intrinsic-7.c| 2 +-
>  .../riscv/rvv/base/target_attribute_v_with_intrinsic-8.c| 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index e07373d8b57..db9246eed2d 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -4589,7 +4589,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
>
>if (!TARGET_VECTOR)
>  error_at (EXPR_LOCATION (exp),
> - "builtin function %qE requires the V ISA extension", exp);
> + "built-in function %qE requires the V ISA extension", exp);
>
>return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
>  }
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
>  
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> index 520b2e59fae..a4cd67f4f95 100644
> --- 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> +++ 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> @@ -5,5 +5,5 @@
>
>  size_t test_1 (size_t vl)
>  {
> -  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> +  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
>  }
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
>  
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> index 9032d9d0b43..06ed9a9eddc 100644
> --- 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> +++ 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> @@ -19,5 +19,5 @@ test_2 ()
>  size_t
>  test_3 (size_t vl)
>  {
> -  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> +  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
>  }
> --
> 2.34.1
>

RE: [PATCH] RISC-V: Fix one unused varable in riscv_subset_list::parse

2024-03-31 Thread Li, Pan2 
Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Sunday, March 31, 2024 8:54 AM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang 

Subject: Re: [PATCH] RISC-V: Fix one unused varable in riscv_subset_list::parse

LGTM

On Sat, Mar 30, 2024 at 9:35 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to fix one unused variable as below:
>
> ../../gcc/common/config/riscv/riscv-common.cc: In static member function
> 'static riscv_subset_list* riscv_subset_list::parse(const char*, location_t)':
> ../../gcc/common/config/riscv/riscv-common.cc:1501:19: error: unused variable 
> 'itr'
>   [-Werror=unused-variable]
>  1501 |   riscv_subset_t *itr;
>
> The variable consume code was removed but missed the var itself in
> previous.  Thus, we have unused variable here.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
> Remove unused var decl.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/common/config/riscv/riscv-common.cc | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 7095f303cbb..43b7549e3ec 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -1498,7 +1498,6 @@ riscv_subset_list::parse (const char *arch, location_t 
> loc)
>  return NULL;
>
>riscv_subset_list *subset_list = new riscv_subset_list (arch, loc);
> -  riscv_subset_t *itr;
>const char *p = arch;
>p = subset_list->parse_base_ext (p);
>if (p == NULL)
> --
> 2.34.1
>