Re: [PATCH] Remove x86 pcommit instruction

[Andrew Senkevich]

2017-02-25 18:10 GMT+01:00 Gerald Pfeifer <ger...@pfeifer.com>:
> On Wed, 7 Dec 2016, Andrew Senkevich wrote:
>>>> But how to update changes for upcoming GCC 6.3 (and future GCC 5.5)?
>>> There are corresponding documents at  [1] and [2], please add a "GCC
>>> 6.3" or "GCC 5.5" entry with "Target Specific Changes" at the end of
>>> the documents.
>>>
>>> [1] https://gcc.gnu.org/gcc-6/changes.html
>>> [2] https://gcc.gnu.org/gcc-5/changes.html
>> Attached patches, who will apply them?
>
> I noticed nobody so far, so I took this.  The patch for GCC 6
> required some tweaking (and you can't use the some id for two
> different headings).
>
> Below is what I just applied.
>
> Gerald
>
> Index: gcc-6/changes.html
> ===
> RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v
> retrieving revision 1.93
> diff -u -r1.93 changes.html
> --- gcc-6/changes.html  18 Feb 2017 22:15:41 -  1.93
> +++ gcc-6/changes.html  25 Feb 2017 17:06:27 -
> @@ -879,5 +879,15 @@
>  complete (that is, it is possible that some PRs that have been fixed
>  are not listed here).
>
> +Target Specific Changes
> +
> +IA-32/x86-64
> +  
> +Support for the  +
> href="https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction;>deprecated
> +pcommit instruction has been removed.
> +  
> +
> + 
>  
>  

Thanks Gerald!

Could you please add the same statement for gcc-7 changes?


--
WBR,
Andrew

Re: [PATCH][x86_64] Enable AVX512 VPOPCNTD/VPOPCNTQ instructions

[Andrew Senkevich]

2017-01-10 13:58 GMT+01:00 Kirill Yukhin <kirill.yuk...@gmail.com>:
> On 10 Jan 15:00, Andrew Senkevich wrote:
>> 2017-01-10 13:31 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>> > On Tue, Jan 10, 2017 at 11:21 AM, Andrew Senkevich
>> > <andrew.n.senkev...@gmail.com> wrote:
>> >> 2017-01-10 13:04 GMT+03:00 Kirill Yukhin <kirill.yuk...@gmail.com>:
>> >>> Hi,
>> >>> In addition to Uroš's inputs:
>> >>>> diff --git a/gcc/config/i386/avx512vpopcntdqintrin.h
>> >>>> b/gcc/config/i386/avx512vpopcntdqintrin.h
>> >>>> new file mode 100644
>> >>>> index 000..28305f6
>> >>>> --- /dev/null
>> >>>> +++ b/gcc/config/i386/avx512vpopcntdqintrin.h
>> >>>> @@ -0,0 +1,90 @@
>> >>>> +/* Copyright (C) 2016 Free Software Foundation, Inc.
>> >>> Pls, fix year.
>> >>>
>> >>> Pattern should perfectly fit into subst infra.
>> >>
>> >> Indeed, patch attached.
>> >> Changelogs will be fixed accordingly.
>> >
>> > Patch is OK for mainline.
>>
>> Thanks!
>>
>> Attached with updated ChangeLogs.
>> Kirill, could you commit please?
> Done.
>
> Also, could you pls implement runtime test cases for new intrinsics.

Hi,

those tests are attached, are they Ok?
ChangLog:

gcc/testsuite/

* gcc.target/i386/avx512vpopcntdq-check.h: New.
* gcc.target/i386/avx512vpopcntdq-vpopcntd-1.c: Ditto.
* gcc.target/i386/avx512vpopcntdq-vpopcntq-1.c: Ditto.
* gcc.target/i386/avx512f-helper.h: Add avx512vpopcntdq-check.h.
* gcc.target/i386/i386.exp (check_effective_target_avx512vpopcntdq): New.


--
WBR,
Andrew


avx512vpopcntdq_rt_tests.patch
Description: Binary data

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2017-01-20 20:08 GMT+03:00 Kirill Yukhin <kirill.yuk...@gmail.com>:
> Hi,
> On 20 Jan 14:46, Uros Bizjak wrote:
>> On Fri, Jan 20, 2017 at 2:32 PM, Andrew Senkevich
>> <andrew.n.senkev...@gmail.com> wrote:
>>
>> > here is intrinsics for ktest{b,w,d,q} and kortest{b,w,d,q}. Is it Ok?
>> >
>> > gcc/
>> > * config/i386/avx512bwintrin.h: Add k-mask test, kortest intrinsics.
>> > * config/i386/avx512dqintrin.h: Ditto.
>> > * config/i386/avx512fintrin.h: Ditto.
>> > * gcc/config/i386/i386.c: Handle new builtins.
>> > * config/i386/i386-builtin.def: Add new builtins.
>> > * config/i386/sse.md (ktest, kortest): New.
>> > (UNSPEC_KORTEST, UNSPEC_KTEST): New.
>> >
>> > gcc/testsuite/
>> > * gcc.target/i386/avx512bw-ktestd-1.c: New test.
>> > * gcc.target/i386/avx512bw-ktestq-1.c: Ditto.
>> > * gcc.target/i386/avx512dq-ktestb-1.c: Ditto.
>> > * gcc.target/i386/avx512f-ktestw-1.c: Ditto.
>> > * gcc.target/i386/avx512bw-kortestd-1.c: Ditto.
>> > * gcc.target/i386/avx512bw-kortestq-1.c: Ditto.
>> > * gcc.target/i386/avx512dq-kortestb-1.c: Ditto.
>> > * gcc.target/i386/avx512f-kortestw-1.c: Ditto.
>>
>> IMO, you should add some runtime tests.
> +1
>
>> Otherwise, the patch LGTM, but I'l leave the final approval to Kirill.
> Anyway trunk is frozen, so I suppose you'll need OK from RM.

Kirill, attached with runtime tests.

Richard, are you OK to approve commit of this patch?
It is last part of k-mask intrinsics, it would be great to have all
intrinsics of this type available in single GCC release..

Updated changelog:

gcc/
* config/i386/avx512bwintrin.h: Add k-mask test, kortest intrinsics.
* config/i386/avx512dqintrin.h: Ditto.
* config/i386/avx512fintrin.h: Ditto.
* gcc/config/i386/i386.c: Handle new builtins.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/sse.md (ktest, kortest): New.
(UNSPEC_KORTEST, UNSPEC_KTEST): New.

gcc/testsuite/
* gcc.target/i386/avx512bw-ktestd-1.c: New test.
* gcc.target/i386/avx512bw-ktestq-1.c: Ditto.
* gcc.target/i386/avx512dq-ktestb-1.c: Ditto.
* gcc.target/i386/avx512f-ktestw-1.c: Ditto.
* gcc.target/i386/avx512bw-kortestd-1.c: Ditto.
* gcc.target/i386/avx512bw-kortestq-1.c: Ditto.
* gcc.target/i386/avx512dq-kortestb-1.c: Ditto.
* gcc.target/i386/avx512f-kortestw-1.c: Ditto.
* gcc.target/i386/avx512bw-ktestd-2.c: Ditt
* gcc.target/i386/avx512bw-ktestq-2.c: Ditto.
* gcc.target/i386/avx512dq-ktestb-2.c: Ditto.
* gcc.target/i386/avx512f-ktestw-2.c: Ditto.
* gcc.target/i386/avx512bw-kortestd-2.c: Ditto.
* gcc.target/i386/avx512bw-kortestq-2.c: Ditto.
* gcc.target/i386/avx512dq-kortestb-2.c: Ditto.
* gcc.target/i386/avx512f-kortestw-2.c: Ditto.


--
WBR,
Andrew


avx512-kmask-intrin-part5.patch
Description: Binary data

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2017-01-19 20:55 GMT+03:00 Kirill Yukhin <kirill.yuk...@gmail.com>:
> On 19 Jan 19:42, Andrew Senkevich wrote:
>> 2017-01-19 13:39 GMT+03:00 Kirill Yukhin <kirill.yuk...@gmail.com>:
>> > Hi Andrew,
>> > On 18 Jan 15:45, Andrew Senkevich wrote:
>> >> 2017-01-17 16:51 GMT+03:00 Jakub Jelinek <ja...@redhat.com>:
>> >> > On Tue, Jan 17, 2017 at 04:03:08PM +0300, Andrew Senkevich wrote:
>> >> >> > I've played a bit w/ SDE. And looks like operands are not early 
>> >> >> > clobber:
>> >> >> > TID0: INS 0x004003ee AVX512VEX kmovd k0, eax
>> >> >> > TID0:   k0 := _
>> >> >> > ...
>> >> >> > TID0: INS 0x004003f4 AVX512VEX kshiftlw k0, k0, 
>> >> >> > 0x3
>> >> >> > TID0:   k0 := _fff8
>> >> >> >
>> >> >> > You can see that same dest and source works just fine.
>> >> >>
>> >> >> Hmm, I looked only on what ICC generates, and it was not correct way.
>> >> >
>> >> > I've just tried
>> >> > int
>> >> > main ()
>> >> > {
>> >> >   unsigned int a = 0x;
>> >> >   asm volatile ("kmovw %1, %%k6; kshiftlw $1, %%k6, %%k6; kmovw %%k6, 
>> >> > %0" : "=r" (a) : "r" (a) : "k6");
>> >> >   __builtin_printf ("%x\n", a);
>> >> >   return 0;
>> >> > }
>> >> > on KNL and got 0x.
>> >> > Are you going to report to the SDM authors so that they fix it up?
>> >> > E.g. using TEMP <- SRC1[0:...] before DEST[...] <- 0 and using TEMP
>> >> > instead of SRC1[0:...] would fix it, or filling up TEMP first and only
>> >> > at the end assigning DEST <- TEMP etc. would do.
>> >>
>> >> Yes, we will work on it.
>> >>
>> >> Attached patch refactored in part of builtints declarations and tests, is 
>> >> it Ok?
>> >
>> > Could you please add runtime tests for new intrinsics as well?
>>
>> Attached with runtime tests.
> Great! Thanks. Patch is OK for main trunk.
>
> --
> Thanks, K
>>
>> gcc/
>> * config/i386/avx512bwintrin.h: Add k-mask registers shift intrinsics.
>> * config/i386/avx512dqintrin.h: Ditto.
>> * config/i386/avx512fintrin.h: Ditto.
>> * config/i386/i386-builtin-types.def: Add new types.
>> * gcc/config/i386/i386.c: Handle new types.
>> * config/i386/i386-builtin.def (__builtin_ia32_kshiftliqi,
>> __builtin_ia32_kshiftlihi, __builtin_ia32_kshiftlisi,
>> __builtin_ia32_kshiftlidi, __builtin_ia32_kshiftriqi,
>> __builtin_ia32_kshiftrihi, __builtin_ia32_kshiftrisi,
>> __builtin_ia32_kshiftridi): New.
>> * config/i386/sse.md (k): Rename *k.
>>
>> gcc/testsuite/
>> * gcc.target/i386/avx512bw-kshiftld-1.c: New test.
>> * gcc.target/i386/avx512bw-kshiftlq-1.c: Ditto.
>> * gcc.target/i386/avx512dq-kshiftlb-1.c: Ditto.
>> * gcc.target/i386/avx512f-kshiftlw-1.c: Ditto.
>> * gcc.target/i386/avx512bw-kshiftrd-1.c: Ditto.
>> * gcc.target/i386/avx512bw-kshiftrq-1.c: Ditto.
>> * gcc.target/i386/avx512dq-kshiftrb-1.c: Ditto.
>> * gcc.target/i386/avx512f-kshiftrw-1.c: Ditto.
>> * gcc.target/i386/avx512bw-kshiftld-2.c: Ditto.
>> * gcc.target/i386/avx512bw-kshiftlq-2.c: Ditto.
>> * gcc.target/i386/avx512bw-kshiftrd-2.c: Ditto.
>> * gcc.target/i386/avx512bw-kshiftrq-2.c: Ditto.
>> * gcc.target/i386/avx512dq-kshiftlb-2.c: Ditto.
>> * gcc.target/i386/avx512dq-kshiftrb-2.c: Ditto.
>> * gcc.target/i386/avx512f-kshiftlw-2.c: Ditto.
>> * gcc.target/i386/avx512f-kshiftrw-2.c: Ditto.
>> * gcc.target/i386/avx-1.c: Test new intrinsics.
>> * gcc.target/i386/sse-13.c: Ditto.
>> * gcc.target/i386/sse-23.c: Ditto.

Hi,

here is intrinsics for ktest{b,w,d,q} and kortest{b,w,d,q}. Is it Ok?

gcc/
* config/i386/avx512bwintrin.h: Add k-mask test, kortest intrinsics.
* config/i386/avx512dqintrin.h: Ditto.
* config/i386/avx512fintrin.h: Ditto.
* gcc/config/i386/i386.c: Handle new builtins.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/sse.md (ktest, kortest): New.
(UNSPEC_KORTEST, UNSPEC_KTEST): New.

gcc/testsuite/
* gcc.target/i386/avx512bw-ktestd-1.c: New test.
* gcc.target/i386/avx512bw-ktestq-1.c: Ditto.
* gcc.target/i386/avx512dq-ktestb-1.c: Ditto.
* gcc.target/i386/avx512f-ktestw-1.c: Ditto.
* gcc.target/i386/avx512bw-kortestd-1.c: Ditto.
* gcc.target/i386/avx512bw-kortestq-1.c: Ditto.
* gcc.target/i386/avx512dq-kortestb-1.c: Ditto.
* gcc.target/i386/avx512f-kortestw-1.c: Ditto.


--
WBR,
Andrew


avx512-kmask-intrin-part5.patch
Description: Binary data

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2017-01-19 13:39 GMT+03:00 Kirill Yukhin <kirill.yuk...@gmail.com>:
> Hi Andrew,
> On 18 Jan 15:45, Andrew Senkevich wrote:
>> 2017-01-17 16:51 GMT+03:00 Jakub Jelinek <ja...@redhat.com>:
>> > On Tue, Jan 17, 2017 at 04:03:08PM +0300, Andrew Senkevich wrote:
>> >> > I've played a bit w/ SDE. And looks like operands are not early clobber:
>> >> > TID0: INS 0x004003ee AVX512VEX kmovd k0, eax
>> >> > TID0:   k0 := _
>> >> > ...
>> >> > TID0: INS 0x004003f4 AVX512VEX kshiftlw k0, k0, 0x3
>> >> > TID0:   k0 := _fff8
>> >> >
>> >> > You can see that same dest and source works just fine.
>> >>
>> >> Hmm, I looked only on what ICC generates, and it was not correct way.
>> >
>> > I've just tried
>> > int
>> > main ()
>> > {
>> >   unsigned int a = 0x;
>> >   asm volatile ("kmovw %1, %%k6; kshiftlw $1, %%k6, %%k6; kmovw %%k6, %0" 
>> > : "=r" (a) : "r" (a) : "k6");
>> >   __builtin_printf ("%x\n", a);
>> >   return 0;
>> > }
>> > on KNL and got 0x.
>> > Are you going to report to the SDM authors so that they fix it up?
>> > E.g. using TEMP <- SRC1[0:...] before DEST[...] <- 0 and using TEMP
>> > instead of SRC1[0:...] would fix it, or filling up TEMP first and only
>> > at the end assigning DEST <- TEMP etc. would do.
>>
>> Yes, we will work on it.
>>
>> Attached patch refactored in part of builtints declarations and tests, is it 
>> Ok?
>
> Could you please add runtime tests for new intrinsics as well?

Attached with runtime tests.

gcc/
* config/i386/avx512bwintrin.h: Add k-mask registers shift intrinsics.
* config/i386/avx512dqintrin.h: Ditto.
* config/i386/avx512fintrin.h: Ditto.
* config/i386/i386-builtin-types.def: Add new types.
* gcc/config/i386/i386.c: Handle new types.
* config/i386/i386-builtin.def (__builtin_ia32_kshiftliqi,
__builtin_ia32_kshiftlihi, __builtin_ia32_kshiftlisi,
__builtin_ia32_kshiftlidi, __builtin_ia32_kshiftriqi,
__builtin_ia32_kshiftrihi, __builtin_ia32_kshiftrisi,
__builtin_ia32_kshiftridi): New.
* config/i386/sse.md (k): Rename *k.

gcc/testsuite/
* gcc.target/i386/avx512bw-kshiftld-1.c: New test.
* gcc.target/i386/avx512bw-kshiftlq-1.c: Ditto.
* gcc.target/i386/avx512dq-kshiftlb-1.c: Ditto.
* gcc.target/i386/avx512f-kshiftlw-1.c: Ditto.
* gcc.target/i386/avx512bw-kshiftrd-1.c: Ditto.
* gcc.target/i386/avx512bw-kshiftrq-1.c: Ditto.
* gcc.target/i386/avx512dq-kshiftrb-1.c: Ditto.
* gcc.target/i386/avx512f-kshiftrw-1.c: Ditto.
* gcc.target/i386/avx512bw-kshiftld-2.c: Ditto.
* gcc.target/i386/avx512bw-kshiftlq-2.c: Ditto.
* gcc.target/i386/avx512bw-kshiftrd-2.c: Ditto.
* gcc.target/i386/avx512bw-kshiftrq-2.c: Ditto.
* gcc.target/i386/avx512dq-kshiftlb-2.c: Ditto.
* gcc.target/i386/avx512dq-kshiftrb-2.c: Ditto.
* gcc.target/i386/avx512f-kshiftlw-2.c: Ditto.
* gcc.target/i386/avx512f-kshiftrw-2.c: Ditto.
* gcc.target/i386/avx-1.c: Test new intrinsics.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.


--
WBR,
Andrew


avx512-kmask-intrin-part4.patch
Description: Binary data

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2017-01-17 16:51 GMT+03:00 Jakub Jelinek <ja...@redhat.com>:
> On Tue, Jan 17, 2017 at 04:03:08PM +0300, Andrew Senkevich wrote:
>> > I've played a bit w/ SDE. And looks like operands are not early clobber:
>> > TID0: INS 0x004003ee AVX512VEX kmovd k0, eax
>> > TID0:   k0 := _
>> > ...
>> > TID0: INS 0x004003f4 AVX512VEX kshiftlw k0, k0, 0x3
>> > TID0:   k0 := _fff8
>> >
>> > You can see that same dest and source works just fine.
>>
>> Hmm, I looked only on what ICC generates, and it was not correct way.
>
> I've just tried
> int
> main ()
> {
>   unsigned int a = 0x;
>   asm volatile ("kmovw %1, %%k6; kshiftlw $1, %%k6, %%k6; kmovw %%k6, %0" : 
> "=r" (a) : "r" (a) : "k6");
>   __builtin_printf ("%x\n", a);
>   return 0;
> }
> on KNL and got 0x.
> Are you going to report to the SDM authors so that they fix it up?
> E.g. using TEMP <- SRC1[0:...] before DEST[...] <- 0 and using TEMP
> instead of SRC1[0:...] would fix it, or filling up TEMP first and only
> at the end assigning DEST <- TEMP etc. would do.

Yes, we will work on it.

Attached patch refactored in part of builtints declarations and tests, is it Ok?

gcc/
* config/i386/avx512bwintrin.h: Add k-mask registers shift intrinsics.
* config/i386/avx512dqintrin.h: Ditto.
* config/i386/avx512fintrin.h: Ditto.
* config/i386/i386-builtin-types.def: Add new types.
* gcc/config/i386/i386.c: Handle new types.
* config/i386/i386-builtin.def (__builtin_ia32_kshiftliqi,
__builtin_ia32_kshiftlihi, __builtin_ia32_kshiftlisi,
__builtin_ia32_kshiftlidi, __builtin_ia32_kshiftriqi,
__builtin_ia32_kshiftrihi, __builtin_ia32_kshiftrisi,
__builtin_ia32_kshiftridi): New.
* config/i386/sse.md (k): Rename *k.

gcc/testsuite/
* gcc.target/i386/avx512bw-kshiftld-1.c: New test.
* gcc.target/i386/avx512bw-kshiftlq-1.c: Ditto.
* gcc.target/i386/avx512dq-kshiftlb-1.c: Ditto.
* gcc.target/i386/avx512f-kshiftlw-1.c: Ditto.
* gcc.target/i386/avx512bw-kshiftrd-1.c: Ditto.
* gcc.target/i386/avx512bw-kshiftrq-1.c: Ditto.
* gcc.target/i386/avx512dq-kshiftrb-1.c: Ditto.
* gcc.target/i386/avx512f-kshiftrw-1.c: Ditto.
* gcc.target/i386/avx-1.c: Test new intrinsics.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.


--
WBR,
Andrew


avx512-kmask-intrin-part4.patch
Description: Binary data

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2017-01-17 15:30 GMT+03:00 Kirill Yukhin <kirill.yuk...@gmail.com>:
> Hi Anrey,
> On 17 Jan 14:04, Andrew Senkevich wrote:
>> 2017-01-17 1:55 GMT+03:00 Jakub Jelinek <ja...@redhat.com>:
>> > On Tue, Jan 17, 2017 at 01:30:11AM +0300, Andrew Senkevich wrote:
>> >> here is one more part of intrinsics for k-mask registers shifts:
>> >
>> > The software developer manuals describe KSHIFT{L,R}* like:
>> > KSHIFTLW
>> > COUNT <- imm8[7:0]
>> > DEST[MAX_KL-1:0] <- 0
>> > IF COUNT <=15
>> > THEN DEST[15:0] <- SRC1[15:0] << COUNT;
>> > FI;
>> >
>> > What is the behavior when src1 == dest, like:
>> >   kshiftld $3, %k3, %k3
>> > ?  Is it just a bug in the SDM and will it actually do the expected thing
>> > (set %k3 to %k3 << 3 and clear just the upper bits), or do we need
>> > an early-clobber on the destination to make sure GCC never emits these
>> > insns with the same register as both input and output?
>>
>> Indeed, it should be different registers, how to do it?
> Are you sure?
>
> I've played a bit w/ SDE. And looks like operands are not early clobber:
> TID0: INS 0x004003ee AVX512VEX kmovd k0, eax
> TID0:   k0 := _
> ...
> TID0: INS 0x004003f4 AVX512VEX kshiftlw k0, k0, 0x3
> TID0:   k0 := _fff8
>
> You can see that same dest and source works just fine.

Hmm, I looked only on what ICC generates, and it was not correct way.

Thanks Kirill!


--
WBR,
Andrew

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2017-01-17 1:55 GMT+03:00 Jakub Jelinek <ja...@redhat.com>:
> On Tue, Jan 17, 2017 at 01:30:11AM +0300, Andrew Senkevich wrote:
>> here is one more part of intrinsics for k-mask registers shifts:
>
> The software developer manuals describe KSHIFT{L,R}* like:
> KSHIFTLW
> COUNT <- imm8[7:0]
> DEST[MAX_KL-1:0] <- 0
> IF COUNT <=15
> THEN DEST[15:0] <- SRC1[15:0] << COUNT;
> FI;
>
> What is the behavior when src1 == dest, like:
>   kshiftld $3, %k3, %k3
> ?  Is it just a bug in the SDM and will it actually do the expected thing
> (set %k3 to %k3 << 3 and clear just the upper bits), or do we need
> an early-clobber on the destination to make sure GCC never emits these
> insns with the same register as both input and output?

Indeed, it should be different registers, how to do it?


--
WBR,
Andrew

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

Hi,

here is one more part of intrinsics for k-mask registers shifts:

gcc/
* config/i386/avx512bwintrin.h: Add k-mask registers shift intrinsics.
* config/i386/avx512dqintrin.h: Ditto.
* config/i386/avx512fintrin.h: Ditto.
* config/i386/i386-builtin-types.def: Add new types.
* gcc/config/i386/i386.c: Handle new types.
* config/i386/i386-builtin.def (__builtin_ia32_kshiftliqi,
__builtin_ia32_kshiftlihi, __builtin_ia32_kshiftlisi,
__builtin_ia32_kshiftlidi, __builtin_ia32_kshiftriqi,
__builtin_ia32_kshiftrihi, __builtin_ia32_kshiftrisi,
__builtin_ia32_kshiftridi): New.
* config/i386/sse.md (k2): Rename *k.

gcc/testsuite/
* gcc.target/i386/avx512bw-kshiftld-1.c: New test.
* gcc.target/i386/avx512bw-kshiftlq-1.c: Ditto.
* gcc.target/i386/avx512dq-kshiftlb-1.c: Ditto.
* gcc.target/i386/avx512f-kshiftlw-1.c: Ditto.
* gcc.target/i386/avx512bw-kshiftrd-1.c: Ditto.
* gcc.target/i386/avx512bw-kshiftrq-1.c: Ditto.
* gcc.target/i386/avx512dq-kshiftrb-1.c: Ditto.
* gcc.target/i386/avx512f-kshiftrw-1.c: Ditto.


Is it Ok for trunk?


--
WBR,
Andrew


avx512-kmask-intrin-part4.patch
Description: Binary data

Re: [PATCH] Enable SGX intrinsics

[Andrew Senkevich]

On Fri, Dec 30, 2016 at 03:37:14PM +0100, Uros Bizjak wrote:
>> As suggested in [1], you should write multi-line enums like:
>>
>> enum foo
>> {
>>   a = ...
>>   b = ...
>> }
>
> Sure.  Plus it depends on if users of the APIs should just write the operands 
> on their own as numbers, or as __SGX_E*, or as E*.
> In the first case the patch sans formatting is reasonable, in the second case 
> the enums should be moved to file scope, in the last case we have to live 
> with the namespace pollution.
> The pdf you've referenced in the thread doesn't list the _encls_u32 and
> _enclu_u32 intrinsics, so I think it depends on what ICC does (if it has been 
> shipped with such a support already, or on coordination with ICC if not).

Jakub, it is in accordance with ICC.
So the first case will be used.


--
WBR,
Andrew

Re: [PATCH][x86_64] Enable AVX512 VPOPCNTD/VPOPCNTQ instructions

[Andrew Senkevich]

2017-01-10 13:31 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
> On Tue, Jan 10, 2017 at 11:21 AM, Andrew Senkevich
> <andrew.n.senkev...@gmail.com> wrote:
>> 2017-01-10 13:04 GMT+03:00 Kirill Yukhin <kirill.yuk...@gmail.com>:
>>> Hi,
>>> In addition to Uroš's inputs:
>>>> diff --git a/gcc/config/i386/avx512vpopcntdqintrin.h
>>>> b/gcc/config/i386/avx512vpopcntdqintrin.h
>>>> new file mode 100644
>>>> index 000..28305f6
>>>> --- /dev/null
>>>> +++ b/gcc/config/i386/avx512vpopcntdqintrin.h
>>>> @@ -0,0 +1,90 @@
>>>> +/* Copyright (C) 2016 Free Software Foundation, Inc.
>>> Pls, fix year.
>>>
>>> Pattern should perfectly fit into subst infra.
>>
>> Indeed, patch attached.
>> Changelogs will be fixed accordingly.
>
> Patch is OK for mainline.

Thanks!

Attached with updated ChangeLogs.
Kirill, could you commit please?


--
WBR,
Andrew


avx512vpopcntdq_v3.patch
Description: Binary data

Re: [PATCH][x86_64] Enable AVX512 VPOPCNTD/VPOPCNTQ instructions

[Andrew Senkevich]

2017-01-10 13:04 GMT+03:00 Kirill Yukhin :
> Hi,
> In addition to Uroš's inputs:
>> diff --git a/gcc/config/i386/avx512vpopcntdqintrin.h
>> b/gcc/config/i386/avx512vpopcntdqintrin.h
>> new file mode 100644
>> index 000..28305f6
>> --- /dev/null
>> +++ b/gcc/config/i386/avx512vpopcntdqintrin.h
>> @@ -0,0 +1,90 @@
>> +/* Copyright (C) 2016 Free Software Foundation, Inc.
> Pls, fix year.
>
> Pattern should perfectly fit into subst infra.

Indeed, patch attached.
Changelogs will be fixed accordingly.


avx512vpopcntdq_v2.patch
Description: Binary data

Re: [PATCH][x86_64] Enable AVX512 VPOPCNTD/VPOPCNTQ instructions

[Andrew Senkevich]

2016-12-27 16:35 GMT+03:00 Uros Bizjak :
> Hello!
>
>> this patch enables AVX512 VPOPCNTD/VPOPCNTQ instructions recently
>> added in Instruction Set Extensions
>> (https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf).
>
> @@ -265,6 +268,9 @@
>  (define_mode_iterator VF_512
>[V16SF V8DF])
>
> +(define_mode_iterator VI_AVX512F
> +  [V16SI V8DI])
>
> Please name this iterator VI_512.

But there are already VI_512 :)

;; All 512bit vector integer modes
(define_mode_iterator VI_512
  [(V64QI "TARGET_AVX512BW")
   (V32HI "TARGET_AVX512BW")
   V16SI V8DI])


--
WBR,
Andrew

[PATCH][x86_64] Enable AVX512 VPOPCNTD/VPOPCNTQ instructions

[Andrew Senkevich]

Hi,

this patch enables AVX512 VPOPCNTD/VPOPCNTQ instructions recently
added in Instruction Set Extensions
(https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf).

gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET,
OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET): New.
* config.gcc: Add avx512vpopcntdqintrin.h.
* config/i386/avx512vpopcntdqintrin.h: New.
* config/i386/cpuid.h (bit_AVX512VPOPCNTDQ): New.
* config/i386/i386-builtin-types.def: Add new types.
* config/i386/i386-builtin.def (__builtin_ia32_vpopcountd_v16si,
__builtin_ia32_vpopcountd_v16si_mask,
__builtin_ia32_vpopcountd_v16si_maskz, __builtin_ia32_vpopcountq_v8di,
__builtin_ia32_vpopcountq_v8di_mask,
__builtin_ia32_vpopcountq_v8di_maskz): New.
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__AVX512VPOPCNTDQ__.
* config/i386/i386.c (ix86_target_string): Add -mavx512vpopcntdq.
(PTA_AVX512VPOPCNTDQ): Define.
* config/i386/i386.h (TARGET_AVX512VPOPCNTDQ,
TARGET_AVX512VPOPCNTDQ_P): Define.
* config/i386/i386.opt: Add mavx512vpopcntdq.
* config/i386/immintrin.h: Include avx512vpopcntdqintrin.h.
* config/i386/sse.md (unspec): Add UNSPEC_VPOPCNTDQ.
(define_insn "vpopcount"): New.
(define_insn "vpopcountv16si_mask"): Ditto.
(define_insn "vpopcountv16si_maskz"): Ditto.
(define_insn "vpopcountv8di_mask"): Ditto.
(define_insn "vpopcountv8di_maskz"): Ditto.
(define_mode_iterator VI_AVX512F): Ditto.

gcc/testsuite/
* g++.dg/other/i386-2.C: Add -mavx512vpopcntdq.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/sse-12.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/builtin_target.c: Handle new option.
* gcc.target/i386/funcspec-56.inc: Test new attributes.
* gcc.target/i386/avx512vpopcntdq-vpopcntd.c: New test.
* gcc.target/i386/avx512vpopcntdq-vpopcntq.c: Ditto.

libgcc/
* config/i386/cpuinfo.h (processor_features): Add
FEATURE_AVX512VPOPCNTDQ.
* config/i386/cpuinfo.c (get_available_features): Habdle new
feature.


diff --git a/gcc/common/config/i386/i386-common.c
b/gcc/common/config/i386/i386-common.c
index 98224f5..a425af5 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -78,6 +78,7 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
 #define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS
 #define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW
+#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET OPTION_MASK_ISA_AVX512VPOPCNTDQ
 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
@@ -183,6 +184,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
 #define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS
 #define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW
+#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
@@ -409,6 +411,8 @@ ix86_handle_option (struct gcc_options *opts,
   opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
   opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
   opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
+  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
+  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
  }
   return true;

@@ -481,6 +485,21 @@ ix86_handle_option (struct gcc_options *opts,
  }
   return true;

+case OPT_mavx512vpopcntdq:
+  if (value)
+ {
+  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
+  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
+  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
+  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
+ }
+  else
+ {
+  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
+  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
+ }
+  return true;
+
 case OPT_mavx512dq:
   if (value)
  {
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7afbc54..f9e9399 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -375,7 +375,8 @@ i[34567]86-*-*)
avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h
avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h
avx512vbmivlintrin.h avx5124fmapsintrin.h avx5124vnniwintrin.h
-   

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2016-12-15 19:51 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
> On Thu, Dec 15, 2016 at 2:31 PM, Andrew Senkevich
> <andrew.n.senkev...@gmail.com> wrote:
>> 2016-12-14 22:55 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>> On Wed, Dec 14, 2016 at 8:04 PM, Andrew Senkevich
>>> <andrew.n.senkev...@gmail.com> wrote:
>>>
>>>> here is the second part of k-mask intrinsics, is it Ok?
>>>
>>>> --- a/gcc/config/i386/sse.md
>>>> +++ b/gcc/config/i386/sse.md
>>>> @@ -1309,12 +1309,30 @@
>>>>  ;; Mask variant shift mnemonics
>>>>  (define_code_attr mshift [(ashift "shiftl") (lshiftrt "shiftr")])
>>>>
>>>> +(define_expand "kmovb"
>>>> +  [(set (match_operand:QI 0 "nonimmediate_operand")
>>>> + (match_operand:QI 1 "nonimmediate_operand"))]
>>>> +  "TARGET_AVX512DQ
>>>> +   && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
>>>> +
>>>>  (define_expand "kmovw"
>>>>[(set (match_operand:HI 0 "nonimmediate_operand")
>>>>   (match_operand:HI 1 "nonimmediate_operand"))]
>>>>"TARGET_AVX512F
>>>> && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
>>>>
>>>> +(define_expand "kmovd"
>>>> +  [(set (match_operand:SI 0 "nonimmediate_operand")
>>>> + (match_operand:SI 1 "nonimmediate_operand"))]
>>>> +  "TARGET_AVX512BW
>>>> +   && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
>>>> +
>>>> +(define_expand "kmovq"
>>>> +  [(set (match_operand:DI 0 "nonimmediate_operand")
>>>> + (match_operand:DI 1 "nonimmediate_operand"))]
>>>> +  "TARGET_AVX512BW
>>>> +   && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
>>>> +
>>>>  (define_insn "k"
>>>>[(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=k")
>>>>   (any_logic:SWI1248_AVX512BW
>>>
>>> All the above patterns can be macroized with the following patch:
>>>
>>> --cut here--
>>> Index: sse.md
>>> ===
>>> --- sse.md  (revision 243651)
>>> +++ sse.md  (working copy)
>>> @@ -1309,9 +1309,9 @@
>>>  ;; Mask variant shift mnemonics
>>>  (define_code_attr mshift [(ashift "shiftl") (lshiftrt "shiftr")])
>>>
>>> -(define_expand "kmovw"
>>> -  [(set (match_operand:HI 0 "nonimmediate_operand")
>>> -   (match_operand:HI 1 "nonimmediate_operand"))]
>>> +(define_expand "kmov"
>>> +  [(set (match_operand:SWI1248_AVX512BWDQ 0 "nonimmediate_operand")
>>> +   (match_operand:SWI1248_AVX512BWDQ 1 "nonimmediate_operand"))]
>>>"TARGET_AVX512F
>>> && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
>>>
>>> --cut here--
>>>
>>> Please also post ChangeLog entry.
>>
>> Thanks,
>>
>> here is with ChangeLogs and renamed internal __builtin_ia32_kmov* to
>> match instruction names.
>> For __builtin_ia32_kmov16 change I will follow up for update in branches.
>>
>> Regtested on x86_64-linux-gnu, Ok for trunk?
>
> OK.

Thanks,

here is one more part for kadd{b,w,d,q}, is it ok?

gcc/
* config/i386/avx512bwintrin.h: Add new k-mask intrinsics.
* config/i386/avx512dqintrin.h: Ditto.
* config/i386/avx512fintrin.h: Ditto.
* config/i386/i386-builtin.def (__builtin_ia32_kaddqi,
__builtin_ia32_kaddhi, __builtin_ia32_kaddsi,
__builtin_ia32_kadddi): New.
* config/i386/sse.md (kadd): New.

gcc/testsuite/
* gcc.target/i386/avx512bw-kaddd-1.c: New test.
* gcc.target/i386/avx512bw-kaddq-1.c: Ditto.
* gcc.target/i386/avx512dq-kaddb-1.c: Ditto.
* gcc.target/i386/avx512f-kaddw-1.c: Ditto.

diff --git a/gcc/config/i386/avx512bwintrin.h b/gcc/config/i386/avx512bwintrin.h
index b35ae2b..e38055c 100644
--- a/gcc/config/i386/avx512bwintrin.h
+++ b/gcc/config/i386/avx512bwintrin.h
@@ -40,6 +40,20 @@ typedef char __v64qi __attribute__ ((__vector_size__ (64)));

 typedef unsigned long long __mmask64;

+extern __inline __mmask32
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_kadd_mask32 (__mmask32 __A, __mmask32 __B)
+{
+  return (__mmask32) __builtin_ia32_kad

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2016-12-02 21:31 GMT+03:00 Uros Bizjak :
. . . . .
>>
>> I split this patch after last updates in md files, here is the first
>> part which doesn't change md files.
>> Regtested on x86_64-linux-gnu.  Is this part ok?
>
> There is no point to scan for kmovX insn in e.g.:
>
> +/* { dg-final { scan-assembler-times "kmovq" 2 } } */
> +
> +#include 
> +
> +void
> +avx512bw_test ()
> +{
> +  __mmask64 k1, k2, k3;
> +  volatile __m512i x = _mm512_setzero_si512 ();
> +
> +  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (1) );
> +  __asm__( "kmovq %1, %0" : "=k" (k2) : "r" (2) );
>
> since you emit it from inline asm.
>
> Please remove these pointles kmovX scan-asm-times directives from the
> testcases, and please also remove it  from avx512f-kandnw-1.c
> testcase.
>
> The patch is OK with this change.

Hi

here is the second part of k-mask intrinsics, is it Ok?

diff --git a/gcc/config/i386/avx512bwintrin.h b/gcc/config/i386/avx512bwintrin.h
index 9e6e0ce..7f40808 100644
--- a/gcc/config/i386/avx512bwintrin.h
+++ b/gcc/config/i386/avx512bwintrin.h
@@ -40,6 +40,62 @@ typedef char __v64qi __attribute__ ((__vector_size__ (64)));

 typedef unsigned long long __mmask64;

+extern __inline unsigned int
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_cvtmask32_u32 (__mmask32 __A)
+{
+  return (unsigned int) __builtin_ia32_kmov32 ((__mmask32) __A);
+}
+
+extern __inline unsigned long long
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_cvtmask64_u64 (__mmask64 __A)
+{
+  return (unsigned long long) __builtin_ia32_kmov64 ((__mmask64) __A);
+}
+
+extern __inline __mmask32
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_cvtu32_mask32 (unsigned int __A)
+{
+  return (__mmask32) __builtin_ia32_kmov32 ((__mmask32) __A);
+}
+
+extern __inline __mmask64
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_cvtu64_mask64 (unsigned long long __A)
+{
+  return (__mmask64) __builtin_ia32_kmov64 ((__mmask64) __A);
+}
+
+extern __inline __mmask32
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_load_mask32 (__mmask32 *__A)
+{
+  return (__mmask32) __builtin_ia32_kmov32 (*__A);
+}
+
+extern __inline __mmask64
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_load_mask64 (__mmask64 *__A)
+{
+  return (__mmask64) __builtin_ia32_kmov64 (*(__mmask64 *) __A);
+}
+
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_store_mask32 (__mmask32 *__A, __mmask32 __B)
+{
+  *(__mmask32 *) __A = __builtin_ia32_kmov32 (__B);
+}
+
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_store_mask64 (__mmask64 *__A, __mmask64 __B)
+{
+  *(__mmask64 *) __A = __builtin_ia32_kmov64 (__B);
+}
+
 extern __inline __mmask32
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _knot_mask32 (__mmask32 __A)
diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h
index d2405c3..d15d35d 100644
--- a/gcc/config/i386/avx512dqintrin.h
+++ b/gcc/config/i386/avx512dqintrin.h
@@ -34,6 +34,34 @@
 #define __DISABLE_AVX512DQ__
 #endif /* __AVX512DQ__ */

+extern __inline unsigned int
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_cvtmask8_u32 (__mmask8 __A)
+{
+  return (unsigned int) __builtin_ia32_kmov8 ((__mmask8 ) __A);
+}
+
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_cvtu32_mask8 (unsigned int __A)
+{
+  return (__mmask8) __builtin_ia32_kmov8 ((__mmask8) __A);
+}
+
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_load_mask8 (__mmask8 *__A)
+{
+  return (__mmask8) __builtin_ia32_kmov8 (*(__mmask8 *) __A);
+}
+
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_store_mask8 (__mmask8 *__A, __mmask8 __B)
+{
+  *(__mmask8 *) __A = __builtin_ia32_kmov8 (__B);
+}
+
 extern __inline __mmask8
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _knot_mask8 (__mmask8 __A)
diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h
index ab1704b..45e1949 100644
--- a/gcc/config/i386/avx512fintrin.h
+++ b/gcc/config/i386/avx512fintrin.h
@@ -9984,6 +9984,34 @@ _mm512_maskz_expandloadu_epi32 (__mmask16 __U,
void const *__P)
 #define _kxnor_mask16 _mm512_kxnor
 #define _kxor_mask16 _mm512_kxor

+extern __inline unsigned int
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_cvtmask16_u32 (__mmask16 __A)
+{
+  return (unsigned int) __builtin_ia32_kmov16 ((__mmask16 ) __A);
+}
+
+extern __inline __mmask16
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_cvtu32_mask16 (unsigned int __A)
+{
+  return (__mmask16) __builtin_ia32_kmov16 ((__mmask16 ) __A);
+}
+
+extern __inline __mmask16
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_load_mask16 (__mmask16 *__A)
+{
+  

Re: [PATCH] Remove x86 pcommit instruction

[Andrew Senkevich]

2016-12-07 15:34 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
> On Wed, Dec 7, 2016 at 1:25 PM, Andrew Senkevich
> <andrew.n.senkev...@gmail.com> wrote:
>
>> But how to update changes for upcoming GCC 6.3 (and future GCC 5.5)?
>
> There are corresponding documents at  [1] and [2], please add a "GCC
> 6.3" or "GCC 5.5" entry with "Target Specific Changes" at the end of
> the documents.
>
> [1] https://gcc.gnu.org/gcc-6/changes.html
> [2] https://gcc.gnu.org/gcc-5/changes.html

Attached patches, who will apply them?


--
WBR,
Andrew


gcc5.5_changes.patch
Description: Binary data


gcc6.3_changes.patch
Description: Binary data

Re: [PATCH] Remove x86 pcommit instruction

[Andrew Senkevich]

2016-10-14 12:23 GMT+03:00 Richard Biener <richard.guent...@gmail.com>:
> On Thu, Oct 13, 2016 at 11:39 PM, H.J. Lu <hjl.to...@gmail.com> wrote:
>> On Thu, Oct 13, 2016 at 5:09 AM, Andrew Senkevich
>> <andrew.n.senkev...@gmail.com> wrote:
>>> 2016-10-11 20:09 GMT+03:00 H.J. Lu <hjl.to...@gmail.com>:
>>>> On Tue, Oct 11, 2016 at 10:04 AM, Andrew Senkevich
>>>> <andrew.n.senkev...@gmail.com> wrote:
>>>>> 2016-10-06 1:07 GMT+03:00 H.J. Lu <hjl.to...@gmail.com>:
>>>>>> On Wed, Oct 5, 2016 at 1:42 PM, Andrew Senkevich
>>>>>> <andrew.n.senkev...@gmail.com> wrote:
>>>>>>> 2016-10-05 18:06 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>>>>>>> On Wed, Oct 5, 2016 at 3:47 PM, Andrew Senkevich
>>>>>>>> <andrew.n.senkev...@gmail.com> wrote:
>>>>>>>>>> -mpcommit
>>>>>>>>>> -Target Report Mask(ISA_PCOMMIT) Var(ix86_isa_flags) Save
>>>>>>>>>> -Support PCOMMIT instruction.
>>>>>>>>>> -
>>>>>>>>>>
>>>>>>>>>> You should not simply delete a option that was in the released
>>>>>>>>>> compiler, but a warning should be emitted instead. Please see how
>>>>>>>>>> msse5 is handled in i386.opt.
>>>>>>>>>
>>>>>>>>> Thank you, it is fixed in patch below. Ok for trunk?
>>>>>>>>
>>>>>>>> OK.
>>>>>>>>
>>>>>>>>> Is it subject for backport for 5.* and 6.* releases?
>>>>>>>>
>>>>>>>> Yes, but please wait a couple of days if any problem arises in trunk.
>>>>>>>>
>>>>>>>> (Please also provide an entry for Release Changes, since this is
>>>>>>>> user-facing change. Also for release branches.)
>>>>>>>
>>>>>>> Hi HJ,
>>>>>>>
>>>>>>> could you please commit this patch for trunk since I have no commit 
>>>>>>> rights.
>>>>>>> Attached in format for git am.
>>>>>>>
>>>>>>>
>>>>>>
>>>>>> Done.
>>>>>
>>>>> Thanks, HJ!
>>>>>
>>>>> Should I ask you or somebody else for backports for to 5.* and 6.* or
>>>>> may be I can somehow get commit after approval rights to don't disturb
>>>>> others with commits? I am preparing several patches.
>>>>>
>>>>
>>>> Please provide patches for GCC 5 and 6.
>>>
>>> Attached.
>>
>> I checked them into GCC 5 and GCC 6 branches.
>>
>>> Have you possibility to update according changes.html files?
>>>
>>
>> Here is the patch for GCC 7.  I am not sure what to do with GCC
>> 5 and 6.
>
> There are entries for each sub-release (if not for the next then add one).
>
> Richard.
>
>> --
>> H.J.
>> ---
>> Index: gcc-7/changes.html
>> ===
>> RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-7/changes.html,v
>> retrieving revision 1.18
>> diff -u -p -r1.18 changes.html
>> --- gcc-7/changes.html 12 Oct 2016 11:08:25 - 1.18
>> +++ gcc-7/changes.html 13 Oct 2016 21:37:18 -
>> @@ -318,7 +318,14 @@ const int* get_address (unsigned idx)
>>
>>  
>>
>> -
>> +IA-32/x86-64
>> +   
>> + 
>> +   Support for
>> +   > href="https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction;>deprecated
>> +   pcommit instruction has been removed.
>> + 
>> +   
>>
>>  

But how to update changes for upcoming GCC 6.3 (and future GCC 5.5)?


--
WBR,
Andrew

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2016-12-02 21:31 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
> On Fri, Dec 2, 2016 at 6:44 PM, Andrew Senkevich
> <andrew.n.senkev...@gmail.com> wrote:
>> 2016-11-11 22:14 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>> On Fri, Nov 11, 2016 at 7:23 PM, Andrew Senkevich
>>> <andrew.n.senkev...@gmail.com> wrote:
>>>> 2016-11-11 20:56 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>>>> On Fri, Nov 11, 2016 at 6:50 PM, Uros Bizjak <ubiz...@gmail.com> wrote:
>>>>>> On Fri, Nov 11, 2016 at 6:38 PM, Andrew Senkevich
>>>>>> <andrew.n.senkev...@gmail.com> wrote:
>>>>>>> 2016-11-11 17:34 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>>>>>>> Some quick remarks:
>>>>>>>>
>>>>>>>> +(define_insn "kmovb"
>>>>>>>> +  [(set (match_operand:QI 0 "nonimmediate_operand" "=k,k")
>>>>>>>> + (unspec:QI
>>>>>>>> +  [(match_operand:QI 1 "nonimmediate_operand" "r,km")]
>>>>>>>> +  UNSPEC_KMOV))]
>>>>>>>> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512DQ"
>>>>>>>> +  "@
>>>>>>>> +   kmovb\t{%k1, %0|%0, %k1}
>>>>>>>> +   kmovb\t{%1, %0|%0, %1}";
>>>>>>>> +  [(set_attr "mode" "QI")
>>>>>>>> +   (set_attr "type" "mskmov")
>>>>>>>> +   (set_attr "prefix" "vex")])
>>>>>>>> +
>>>>>>>> +(define_insn "kmovd"
>>>>>>>> +  [(set (match_operand:SI 0 "nonimmediate_operand" "=k,k")
>>>>>>>> + (unspec:SI
>>>>>>>> +  [(match_operand:SI 1 "nonimmediate_operand" "r,km")]
>>>>>>>> +  UNSPEC_KMOV))]
>>>>>>>> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512BW"
>>>>>>>> +  "@
>>>>>>>> +   kmovd\t{%k1, %0|%0, %k1}
>>>>>>>> +   kmovd\t{%1, %0|%0, %1}";
>>>>>>>> +  [(set_attr "mode" "SI")
>>>>>>>> +   (set_attr "type" "mskmov")
>>>>>>>> +   (set_attr "prefix" "vex")])
>>>>>>>> +
>>>>>>>> +(define_insn "kmovq"
>>>>>>>> +  [(set (match_operand:DI 0 "nonimmediate_operand" "=k,k,km")
>>>>>>>> + (unspec:DI
>>>>>>>> +  [(match_operand:DI 1 "nonimmediate_operand" "r,km,k")]
>>>>>>>> +  UNSPEC_KMOV))]
>>>>>>>> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512BW"
>>>>>>>> +  "@
>>>>>>>> +   kmovq\t{%k1, %0|%0, %k1}
>>>>>>>> +   kmovq\t{%1, %0|%0, %1}
>>>>>>>> +   kmovq\t{%1, %0|%0, %1}";
>>>>>>>> +  [(set_attr "mode" "DI")
>>>>>>>> +   (set_attr "type" "mskmov")
>>>>>>>> +   (set_attr "prefix" "vex")])
>>>>>>>>
>>>>>>>> - kmovd (and existing kmovw) should be using register_operand for
>>>>>>>> opreand 0. In this case, there is no need for MEM_P checks at all.
>>>>>>>> - In the insn constraint, pease check TARGET_AVX before checking MEM_P.
>>>>>>>> - please put these definitions above corresponding *mov??_internal 
>>>>>>>> patterns.
>>>>>>>
>>>>>>> Do you mean put below *mov??_internal patterns? Attached corrected such 
>>>>>>> way.
>>>>>>
>>>>>> No, please put kmovq near *movdi_internal, kmovd near *movsi_internal,
>>>>>> etc. It doesn't matter if they are above or below their respective
>>>>>> *mov??_internal patterns, as long as they are positioned in some
>>>>>> consistent way. IOW, new patterns shouldn't be grouped together, as is
>>>>>> the case with your patch.
>>>>>
>>>>> +(define_insn "kmovb"
>>

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2016-11-11 22:14 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
> On Fri, Nov 11, 2016 at 7:23 PM, Andrew Senkevich
> <andrew.n.senkev...@gmail.com> wrote:
>> 2016-11-11 20:56 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>> On Fri, Nov 11, 2016 at 6:50 PM, Uros Bizjak <ubiz...@gmail.com> wrote:
>>>> On Fri, Nov 11, 2016 at 6:38 PM, Andrew Senkevich
>>>> <andrew.n.senkev...@gmail.com> wrote:
>>>>> 2016-11-11 17:34 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>>>>> Some quick remarks:
>>>>>>
>>>>>> +(define_insn "kmovb"
>>>>>> +  [(set (match_operand:QI 0 "nonimmediate_operand" "=k,k")
>>>>>> + (unspec:QI
>>>>>> +  [(match_operand:QI 1 "nonimmediate_operand" "r,km")]
>>>>>> +  UNSPEC_KMOV))]
>>>>>> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512DQ"
>>>>>> +  "@
>>>>>> +   kmovb\t{%k1, %0|%0, %k1}
>>>>>> +   kmovb\t{%1, %0|%0, %1}";
>>>>>> +  [(set_attr "mode" "QI")
>>>>>> +   (set_attr "type" "mskmov")
>>>>>> +   (set_attr "prefix" "vex")])
>>>>>> +
>>>>>> +(define_insn "kmovd"
>>>>>> +  [(set (match_operand:SI 0 "nonimmediate_operand" "=k,k")
>>>>>> + (unspec:SI
>>>>>> +  [(match_operand:SI 1 "nonimmediate_operand" "r,km")]
>>>>>> +  UNSPEC_KMOV))]
>>>>>> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512BW"
>>>>>> +  "@
>>>>>> +   kmovd\t{%k1, %0|%0, %k1}
>>>>>> +   kmovd\t{%1, %0|%0, %1}";
>>>>>> +  [(set_attr "mode" "SI")
>>>>>> +   (set_attr "type" "mskmov")
>>>>>> +   (set_attr "prefix" "vex")])
>>>>>> +
>>>>>> +(define_insn "kmovq"
>>>>>> +  [(set (match_operand:DI 0 "nonimmediate_operand" "=k,k,km")
>>>>>> + (unspec:DI
>>>>>> +  [(match_operand:DI 1 "nonimmediate_operand" "r,km,k")]
>>>>>> +  UNSPEC_KMOV))]
>>>>>> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512BW"
>>>>>> +  "@
>>>>>> +   kmovq\t{%k1, %0|%0, %k1}
>>>>>> +   kmovq\t{%1, %0|%0, %1}
>>>>>> +   kmovq\t{%1, %0|%0, %1}";
>>>>>> +  [(set_attr "mode" "DI")
>>>>>> +   (set_attr "type" "mskmov")
>>>>>> +   (set_attr "prefix" "vex")])
>>>>>>
>>>>>> - kmovd (and existing kmovw) should be using register_operand for
>>>>>> opreand 0. In this case, there is no need for MEM_P checks at all.
>>>>>> - In the insn constraint, pease check TARGET_AVX before checking MEM_P.
>>>>>> - please put these definitions above corresponding *mov??_internal 
>>>>>> patterns.
>>>>>
>>>>> Do you mean put below *mov??_internal patterns? Attached corrected such 
>>>>> way.
>>>>
>>>> No, please put kmovq near *movdi_internal, kmovd near *movsi_internal,
>>>> etc. It doesn't matter if they are above or below their respective
>>>> *mov??_internal patterns, as long as they are positioned in some
>>>> consistent way. IOW, new patterns shouldn't be grouped together, as is
>>>> the case with your patch.
>>>
>>> +(define_insn "kmovb"
>>> +  [(set (match_operand:QI 0 "register_operand" "=k,k")
>>> +(unspec:QI
>>> +  [(match_operand:QI 1 "nonimmediate_operand" "r,km")]
>>> +  UNSPEC_KMOV))]
>>> +  "TARGET_AVX512DQ && !MEM_P (operands[1])"
>>>
>>> There is no need for !MEM_P, this will prevent memory operand, which
>>> is allowed by constraint "m".
>>>
>>> +(define_insn "kmovq"
>>> +  [(set (match_operand:DI 0 "register_operand" "=k,k,km")
>>> +(unspec:DI
>>> +  [(match_operand:DI 1 "nonimmediate_op

Re: [PATCH] Fix PR78306

[Andrew Senkevich]

2016-11-30 11:52 GMT+03:00 Richard Biener :
> On Tue, 29 Nov 2016, Jeff Law wrote:
>
>> On 11/29/2016 12:47 AM, Richard Biener wrote:
>> > > Balaji added this check explicitly. There should be tests in the 
>> > > testsuite
>> > > (spawnee_inline, spawner_inline) which exercise that code.
>> >
>> > Yes he did, but no, nothing in the testsuite.
>> I believe the tests are:
>>
>> c-c++-common/cilk-plus/CK/spawnee_inline.c
>> c-c++-common/cilk-plus/CK/spawner_inline.c
>>
>> But as I mentioned, they don't check for proper behaviour
>
> Actually they do -- and both show what the issue might be, cilk+
> uses setjmp but we already have code to disallow inlining of
> functions calling setjmp (but we happily inline into functions
> calling setjmp).  When mangling the testcases to try forcing
> inlining I still (the patch was already applied) get
>
> /space/rguenther/src/gcc-git/gcc/testsuite/c-c++-common/cilk-plus/CK/spawnee_inline.c:
> In function ‘fib’:
> /space/rguenther/src/gcc-git/gcc/testsuite/c-c++-common/cilk-plus/CK/spawnee_inline.c:9:50:
> error: function ‘fib’ can never be copied because it receives a non-local
> goto
>
> so the intent was probably to disallow inlining of functions calling
> cilk_spawn, not to disable inlining into functions calling cilk_spawn.
>
> But as seen above this is already handled by generic code handling
> setjmp.
>
>>
>> >
>> > There is _nowhere_ documented _why_ the checks were added.  Why is
>> > inlining a transform that can do anything bad to a function using
>> > cilk_spawn?
>> I know, it's disappointing.  Even the tests mentioned above don't shed any
>> real light on the issue.
>
> One issue is obvious (but already handled).  Why all inlining should
> be disabled is indeed still a mystery.

I can suppose inline should be disabled for the next function after
cilk_spawn because spawn should be done for function.
If no way to disable the next call inlining it looks it was disabled
for all function to fix Cilk Plus Conformance Suite test fail.


--
WBR,
Andrew

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

[Andrew Senkevich]

2016-11-21 20:12 GMT+03:00 Martin Sebor :
> On 11/20/2016 11:16 AM, Uros Bizjak wrote:
>>
>> On Sat, Nov 19, 2016 at 7:52 PM, Uros Bizjak  wrote:
>>>
>>> On Sat, Nov 19, 2016 at 6:24 PM, Jakub Jelinek  wrote:

 On Sat, Nov 19, 2016 at 12:28:22PM +0100, Jakub Jelinek wrote:
>
> On x86_64-linux with the 3 patches I'm not seeing any new FAILs
> compared to before r242569, on i686-linux there is still:
> +FAIL: gcc.target/i386/pr57756.c  (test for errors, line 6)
> +FAIL: gcc.target/i386/pr57756.c  (test for warnings, line 14)
> compared to pre-r242569 (so some further fix is needed).


 And finally here is yet another patch that fixes pr57756 on i686-linux.
 Ok for trunk together with the other 3 patches?
>>>
>>>
>>> OK for the whole patch series.
>>
>>
>> Hm, I still see (both, 32bit and 64bit targets):
>>
>> In file included from /ssd/uros/gcc-build/gcc/include/immintrin.h:45:0,^M
>>  from
>> /home/uros/gcc-svn/trunk/gcc/testsuite/gcc.target/i386/sse-22.c:223,^M
>>  from
>> /home/uros/gcc-svn/trunk/gcc/testsuite/gcc.target/i386/sse-22a.c:7:^M
>> /ssd/uros/gcc-build/gcc/include/avx5124fmapsintrin.h: In function
>> '_mm512_maskz_4fmadd_ps':^M
>> /ssd/uros/gcc-build/gcc/include/avx512fintrin.h:244:1: error: inlining
>> failed in call to always_inline '_mm512_setzero_ps': target specific
>> option mismatch^M
>> In file included from /ssd/uros/gcc-build/gcc/include/immintrin.h:71:0,^M
>>  from
>> /home/uros/gcc-svn/trunk/gcc/testsuite/gcc.target/i386/sse-22.c:223,^M
>>  from
>> /home/uros/gcc-svn/trunk/gcc/testsuite/gcc.target/i386/sse-22a.c:7:^M
>> /ssd/uros/gcc-build/gcc/include/avx5124fmapsintrin.h:77:17: note:
>> called from here^M
>> compiler exited with status 1
>> FAIL: gcc.target/i386/sse-22a.c (test for excess errors)
>> Excess errors:
>> /ssd/uros/gcc-build/gcc/include/avx512fintrin.h:244:1: error: inlining
>> failed in call to always_inline '_mm512_setzero_ps': target specific
>> option mismatch
>
>
> FWIW, I came across the same error in my own testing and raised
> bug 78451.

Can we fix it with the following patch? Regtesting in progress.

PR target/78451
* gcc/config/i386/avx5124fmapsintrin.h: Avoid call to
_mm512_setzero_ps.
* gcc/config/i386/avx5124vnniwintrin.h: Ditto.

diff --git a/gcc/config/i386/avx5124fmapsintrin.h
b/gcc/config/i386/avx5124fmapsintrin.h
index 6113ee9..dd9a322
--- a/gcc/config/i386/avx5124fmapsintrin.h
+++ b/gcc/config/i386/avx5124fmapsintrin.h
@@ -74,7 +74,9 @@ _mm512_maskz_4fmadd_ps (__mmask16 __U,
  (__v16sf) __E,
  (__v16sf) __A,
  (const __v4sf *) __F,
- (__v16sf) _mm512_setzero_ps (),
+ (__v16sf) {0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0},
  (__mmask16) __U);
 }

@@ -161,7 +163,9 @@ _mm512_maskz_4fnmadd_ps (__mmask16 __U,
  (__v16sf) __E,
  (__v16sf) __A,
  (const __v4sf *) __F,
- (__v16sf) _mm512_setzero_ps (),
+ (__v16sf) {0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0},
  (__mmask16) __U);
 }

diff --git a/gcc/config/i386/avx5124vnniwintrin.h
b/gcc/config/i386/avx5124vnniwintrin.h
index 392c6a5..a4faa24
--- a/gcc/config/i386/avx5124vnniwintrin.h
+++ b/gcc/config/i386/avx5124vnniwintrin.h
@@ -75,7 +75,9 @@ _mm512_maskz_4dpwssd_epi32 (__mmask16 __U, __m512i
__A, __m512i __B,
   (__v16si) __E,
   (__v16si) __A,
   (const __v4si *) __F,
-  (__v16si) _mm512_setzero_ps (),
+  (__v16si) {0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0},
   (__mmask16) __U);
 }

@@ -120,7 +122,9 @@ _mm512_maskz_4dpwssds_epi32 (__mmask16 __U,
__m512i __A, __m512i __B,
(__v16si) __E,
(__v16si) __A,
(const __v4si *) __F,
-   (__v16si) _mm512_setzero_ps (),
+   (__v16si) {0, 0, 0, 0,
+   0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0, 0, 0},
(__mmask16) __U);
 }


--
WBR,
Andrew


sse-22a-fix.patch
Description: Binary data

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

[Andrew Senkevich]

2016-11-19 13:17 GMT+03:00 Uros Bizjak :
> On Sat, Nov 19, 2016 at 9:05 AM, Jakub Jelinek  wrote:
>> On Fri, Nov 18, 2016 at 09:30:06PM +0100, Jakub Jelinek wrote:
>>> On Fri, Nov 18, 2016 at 08:41:01PM +0100, Jakub Jelinek wrote:
>>> > I'm seeing lots of ICEs with this.
>>>
>>> Here is untested fix for that, will bootstrap/regtest it soon (after my
>>> current set of bootstraps finishes).
>>>
>>> 2016-11-18  Jakub Jelinek  
>>>
>>>   * config/i386/i386.c (ix86_expand_builtin): Remove msk_mov variable,
>>>   don't initialize it, don't use it for the case where it isn't
>>>   provable %{z} nor using the same argument, instead move merge
>>>   argument into a new pseudo and use that as target.  Formatting fixes.
>>
>> Now successfully bootstrapped/regtested on x86_64-linux and i686-linux and
>> fixed a couple of FAILs, but not tons of others.
>>
>> Here is another patch I'm going to test which fixes many other FAILs, but
>> still some are left:
>> FAIL: gcc.target/i386/funcspec-3.c (internal compiler error)
>> FAIL: gcc.target/i386/funcspec-3.c (test for excess errors)
>> FAIL: gcc.target/i386/mvc1.c (internal compiler error)
>> FAIL: gcc.target/i386/mvc1.c (test for excess errors)
>> FAIL: gcc.target/i386/mvc6.c (internal compiler error)
>> FAIL: gcc.target/i386/mvc6.c (test for excess errors)
>> FAIL: gcc.target/i386/mvc6.c scan-assembler vpshufb
>> FAIL: gcc.target/i386/mvc6.c scan-assembler punpcklbw
>> FAIL: gcc.target/i386/mvc8.c (internal compiler error)
>> FAIL: gcc.target/i386/mvc8.c (test for excess errors)
>> FAIL: gcc.target/i386/pr67995-2.c (internal compiler error)
>> FAIL: gcc.target/i386/pr67995-2.c (test for excess errors)
>> FAIL: gcc.target/i386/pr71652-3.c (internal compiler error)
>> FAIL: gcc.target/i386/pr71652-3.c  (test for errors, line 5)
>> FAIL: gcc.target/i386/pr71652-3.c (test for excess errors)
>
> I wonder why patch submitter didn't get these failures during
> regtesting. There are plenty of tests (the above multi-vrsioning
> tests) that depend on correct handling of ISA variables. I assumed
> that these tests passed and consequently didn't went deep into the
> implementation, but rather requested a couple of additional tests that
> exercised added functionality.some more.

Completely my bad. Starting from addition last intrinsics testing gone wrong.
Will double check next time to avoid repeating in the future.

>> Will debug even those.

Thank you, Jakub.

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

[Andrew Senkevich]

2016-11-16 19:21 GMT+03:00 Bernd Schmidt <bschm...@redhat.com>:
> On 11/15/2016 05:31 PM, Andrew Senkevich wrote:
>>
>> 2016-11-15 17:56 GMT+03:00 Jeff Law <l...@redhat.com>:
>>>
>>> On 11/15/2016 05:55 AM, Andrew Senkevich wrote:
>>>>
>>>>
>>>> 2016-11-11 14:16 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>>>>
>>>>>
>>>>> --- a/gcc/genmodes.c
>>>>> +++ b/gcc/genmodes.c
>>>>> --- a/gcc/init-regs.c
>>>>> +++ b/gcc/init-regs.c
>>>>> --- a/gcc/machmode.h
>>>>> +++ b/gcc/machmode.h
>>>>>
>>>>> These are middle-end changes, you will need a separate review for
>>>>> these.
>>>>
>>>>
>>>>
>>>> Who could review these changes?
>>>
>>>
>>> I can.  I likely dropped the message because it looked x86 specific, so
>>> if
>>> you could resend it'd be appreciated.
>>
>>
>> Attached (diff with previous only in fixed comments typos).
>
>
> Next time please split middle-end changes out from target-related stuff and
> send them separately.

Ok.

> These ones are OK.
>
>
> Bernd

Thanks!

Who could commit it?


--
WBR,
Andrew

[PATCH] Follow-up patch on enabling new AVX512 instructions

[Andrew Senkevich]

Hi,

this is follow-up with tests for new __target__ attributes and
__builtin_cpu_supports update.

gcc/
* config/i386/i386.c (processor_features): Add
F_AVX5124VNNIW, F_AVX5124FMAPS.
(isa_names_table): Handle new features.
libgcc/
* config/i386/cpuinfo.c (processor_features): Add
FEATURE_AVX5124VNNIW, FEATURE_AVX5124FMAPS.
gcc/testsuite/
* gcc.target/i386/builtin_target.c: Handle new "avx5124vnniw",
"avx5124fmaps".
* gcc.target/i386/funcspec-56.inc: Test new attributes.

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 1da1abc..823930d
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -33205,6 +33205,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
 F_AVX512PF,
 F_AVX512VBMI,
 F_AVX512IFMA,
+F_AVX5124VNNIW,
+F_AVX5124FMAPS,
 F_MAX
   };

@@ -33317,6 +33319,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
   {"avx512pf",F_AVX512PF},
   {"avx512vbmi",F_AVX512VBMI},
   {"avx512ifma",F_AVX512IFMA},
+  {"avx5124vnniw",F_AVX5124VNNIW},
+  {"avx5124fmaps",F_AVX5124FMAPS},
 };

   tree __processor_model_type = build_processor_model_struct ();
diff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c
b/gcc/testsuite/gcc.target/i386/builtin_target.c
index 8d45d83..c620a74
--- a/gcc/testsuite/gcc.target/i386/builtin_target.c
+++ b/gcc/testsuite/gcc.target/i386/builtin_target.c
@@ -213,6 +213,10 @@ check_features (unsigned int ecx, unsigned int edx,
assert (__builtin_cpu_supports ("avx512ifma"));
   if (ecx & bit_AVX512VBMI)
assert (__builtin_cpu_supports ("avx512vbmi"));
+  if (edx & bit_AVX5124VNNIW)
+   assert (__builtin_cpu_supports ("avx5124vnniw"));
+  if (edx & bit_AVX5124FMAPS)
+   assert (__builtin_cpu_supports ("avx5124fmaps"));
 }
 }

@@ -311,6 +315,10 @@ quick_check ()

   assert (__builtin_cpu_supports ("avx512f") >= 0);

+  assert (__builtin_cpu_supports ("avx5124vnniw") >= 0);
+
+  assert (__builtin_cpu_supports ("avx5124fmaps") >= 0);
+
   /* Check CPU type.  */
   assert (__builtin_cpu_is ("amd") >= 0);

diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
index af203f2..4a0ad25
--- a/libgcc/config/i386/cpuinfo.c
+++ b/libgcc/config/i386/cpuinfo.c
@@ -115,7 +115,9 @@ enum processor_features
   FEATURE_AVX512ER,
   FEATURE_AVX512PF,
   FEATURE_AVX512VBMI,
-  FEATURE_AVX512IFMA
+  FEATURE_AVX512IFMA,
+  FEATURE_AVX5124VNNIW,
+  FEATURE_AVX5124FMAPS
 };

 struct __processor_model
@@ -359,6 +361,10 @@ get_available_features (unsigned int ecx, unsigned int edx,
features |= (1 << FEATURE_AVX512IFMA);
   if (ecx & bit_AVX512VBMI)
features |= (1 << FEATURE_AVX512VBMI);
+  if (edx & bit_AVX5124VNNIW)
+   features |= (1 << FEATURE_AVX5124VNNIW);
+  if (edx & bit_AVX5124FMAPS)
+   features |= (1 << FEATURE_AVX5124FMAPS);
 }

   unsigned int ext_level;
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 521ac8a..9334e9e 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -28,6 +28,8 @@ extern void test_avx512dq(void)
 __attribute__((__target__("avx512dq")));
 extern void test_avx512er(void)
__attribute__((__target__("avx512er")));
 extern void test_avx512pf(void)
__attribute__((__target__("avx512pf")));
 extern void test_avx512cd(void)
__attribute__((__target__("avx512cd")));
+extern void test_avx5124fmaps(void)
__attribute__((__target__("avx5124fmaps")));
+extern void test_avx5124vnniw(void)
__attribute__((__target__("avx5124vnniw")));
 extern void test_bmi (void)
__attribute__((__target__("bmi")));
 extern void test_bmi2 (void)
__attribute__((__target__("bmi2")));

@@ -59,6 +61,8 @@ extern void test_no_avx512dq(void)
__attribute__((__target__("no-avx512dq")));
 extern void test_no_avx512er(void)
__attribute__((__target__("no-avx512er")));
 extern void test_bo_avx512pf(void)
__attribute__((__target__("no-avx512pf")));
 extern void test_no_avx512cd(void)
__attribute__((__target__("no-avx512cd")));
+extern void test_no_avx5124fmaps(void)
__attribute__((__target__("no-avx5124fmaps")));
+extern void test_no_avx5124vnniw(void)
__attribute__((__target__("no-avx5124vnniw")));
 extern void test_no_bmi (void)
__attribute__((__target__("no-bmi")));
 extern void test_no_bmi2 (void)
__attribute__((__target__("no-bmi2")));


--
WBR,
Andrew


followup_tests.patch
Description: Binary data

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

[Andrew Senkevich]

2016-11-15 17:56 GMT+03:00 Jeff Law <l...@redhat.com>:
> On 11/15/2016 05:55 AM, Andrew Senkevich wrote:
>>
>> 2016-11-11 14:16 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>>
>>> --- a/gcc/genmodes.c
>>> +++ b/gcc/genmodes.c
>>> --- a/gcc/init-regs.c
>>> +++ b/gcc/init-regs.c
>>> --- a/gcc/machmode.h
>>> +++ b/gcc/machmode.h
>>>
>>> These are middle-end changes, you will need a separate review for these.
>>
>>
>> Who could review these changes?
>
> I can.  I likely dropped the message because it looked x86 specific, so if
> you could resend it'd be appreciated.

Attached (diff with previous only in fixed comments typos).


--
WBR,
Andrew


new_avx512_instructions_15.11.patch
Description: Binary data

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

[Andrew Senkevich]

2016-11-11 14:16 GMT+03:00 Uros Bizjak :
> --- a/gcc/genmodes.c
> +++ b/gcc/genmodes.c
> --- a/gcc/init-regs.c
> +++ b/gcc/init-regs.c
> --- a/gcc/machmode.h
> +++ b/gcc/machmode.h
>
> These are middle-end changes, you will need a separate review for these.

Who could review these changes?


--
WBR,
Andrew

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

[Andrew Senkevich]

2016-11-11 14:29 GMT+03:00 Jakub Jelinek <ja...@redhat.com>:
> Hi!
>
> I've noticed preexisting:
>
> On Thu, Nov 10, 2016 at 07:27:00PM +0300, Andrew Senkevich wrote:
>
>> --- a/gcc/config/i386/i386-modes.def
>> +++ b/gcc/config/i386/i386-modes.def
>> @@ -84,6 +84,7 @@ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
>>  VECTOR_MODES (FLOAT, 32); /*V16HF V8SF V4DF */
>>  VECTOR_MODES (FLOAT, 64); /*   V32HF V16SF V8DF */
>>  VECTOR_MODES (FLOAT, 128);/*  V64HF V32SF V16DF */
>
> The VECTOR_MODES (FLOAT, comments don't really match reality, shall we fix
> that?  None of them create V*HF mode, but they do create V*TF mode.

I have fixed it in new patch.


--
WBR,
Andrew

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

[Andrew Senkevich]

2016-11-11 14:16 GMT+03:00 Uros Bizjak :
> The x86 part of the patch is OK with the above changes and additional
> target attribute test for flags2 ISA features..

Fixed according your comments, I will followup with additional tests soon.


--
WBR,
Andrew


new_avx512_instructions_14.11.patch
Description: Binary data

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2016-11-11 18:26 GMT+03:00 Marc Glisse <marc.gli...@inria.fr>:
> On Fri, 11 Nov 2016, Andrew Senkevich wrote:
>
>> +extern __inline __mmask32
>> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
>> +_kand_mask32 (__mmask32 __A, __mmask32 __B)
>> +{
>> +  return (__mmask32) __builtin_ia32_kandsi ((__mmask32) __A, (__mmask32)
>> __B);
>> +}
>
>
> (picking one random example)
> Is a builtin really needed here? What would happen if you used
>
>   return __A & __B;
>
> ?

Good question. Looks like it also works (for this particular case).


--
WBR,
Andrew

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2016-11-11 20:56 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
> On Fri, Nov 11, 2016 at 6:50 PM, Uros Bizjak <ubiz...@gmail.com> wrote:
>> On Fri, Nov 11, 2016 at 6:38 PM, Andrew Senkevich
>> <andrew.n.senkev...@gmail.com> wrote:
>>> 2016-11-11 17:34 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>>> Some quick remarks:
>>>>
>>>> +(define_insn "kmovb"
>>>> +  [(set (match_operand:QI 0 "nonimmediate_operand" "=k,k")
>>>> + (unspec:QI
>>>> +  [(match_operand:QI 1 "nonimmediate_operand" "r,km")]
>>>> +  UNSPEC_KMOV))]
>>>> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512DQ"
>>>> +  "@
>>>> +   kmovb\t{%k1, %0|%0, %k1}
>>>> +   kmovb\t{%1, %0|%0, %1}";
>>>> +  [(set_attr "mode" "QI")
>>>> +   (set_attr "type" "mskmov")
>>>> +   (set_attr "prefix" "vex")])
>>>> +
>>>> +(define_insn "kmovd"
>>>> +  [(set (match_operand:SI 0 "nonimmediate_operand" "=k,k")
>>>> + (unspec:SI
>>>> +  [(match_operand:SI 1 "nonimmediate_operand" "r,km")]
>>>> +  UNSPEC_KMOV))]
>>>> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512BW"
>>>> +  "@
>>>> +   kmovd\t{%k1, %0|%0, %k1}
>>>> +   kmovd\t{%1, %0|%0, %1}";
>>>> +  [(set_attr "mode" "SI")
>>>> +   (set_attr "type" "mskmov")
>>>> +   (set_attr "prefix" "vex")])
>>>> +
>>>> +(define_insn "kmovq"
>>>> +  [(set (match_operand:DI 0 "nonimmediate_operand" "=k,k,km")
>>>> + (unspec:DI
>>>> +  [(match_operand:DI 1 "nonimmediate_operand" "r,km,k")]
>>>> +  UNSPEC_KMOV))]
>>>> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512BW"
>>>> +  "@
>>>> +   kmovq\t{%k1, %0|%0, %k1}
>>>> +   kmovq\t{%1, %0|%0, %1}
>>>> +   kmovq\t{%1, %0|%0, %1}";
>>>> +  [(set_attr "mode" "DI")
>>>> +   (set_attr "type" "mskmov")
>>>> +   (set_attr "prefix" "vex")])
>>>>
>>>> - kmovd (and existing kmovw) should be using register_operand for
>>>> opreand 0. In this case, there is no need for MEM_P checks at all.
>>>> - In the insn constraint, pease check TARGET_AVX before checking MEM_P.
>>>> - please put these definitions above corresponding *mov??_internal 
>>>> patterns.
>>>
>>> Do you mean put below *mov??_internal patterns? Attached corrected such way.
>>
>> No, please put kmovq near *movdi_internal, kmovd near *movsi_internal,
>> etc. It doesn't matter if they are above or below their respective
>> *mov??_internal patterns, as long as they are positioned in some
>> consistent way. IOW, new patterns shouldn't be grouped together, as is
>> the case with your patch.
>
> +(define_insn "kmovb"
> +  [(set (match_operand:QI 0 "register_operand" "=k,k")
> +(unspec:QI
> +  [(match_operand:QI 1 "nonimmediate_operand" "r,km")]
> +  UNSPEC_KMOV))]
> +  "TARGET_AVX512DQ && !MEM_P (operands[1])"
>
> There is no need for !MEM_P, this will prevent memory operand, which
> is allowed by constraint "m".
>
> +(define_insn "kmovq"
> +  [(set (match_operand:DI 0 "register_operand" "=k,k,km")
> +(unspec:DI
> +  [(match_operand:DI 1 "nonimmediate_operand" "r,km,k")]
> +  UNSPEC_KMOV))]
> +  "TARGET_AVX512BW && !MEM_P (operands[1])"
>
> Operand 0 should have "nonimmediate_operand" predicate. And here you
> need  && !(MEM_P (op0) && MEM_P (op1)) in insn constraint to prevent
> mem->mem moves.

Changed according your comments and attached.


--
WBR,
Andrew


add_k-mask_intrinsics_11.11_1.patch
Description: Binary data

Re: [PATCH] Add AVX512 k-mask intrinsics

[Andrew Senkevich]

2016-11-11 17:34 GMT+03:00 Uros Bizjak :
> Some quick remarks:
>
> +(define_insn "kmovb"
> +  [(set (match_operand:QI 0 "nonimmediate_operand" "=k,k")
> + (unspec:QI
> +  [(match_operand:QI 1 "nonimmediate_operand" "r,km")]
> +  UNSPEC_KMOV))]
> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512DQ"
> +  "@
> +   kmovb\t{%k1, %0|%0, %k1}
> +   kmovb\t{%1, %0|%0, %1}";
> +  [(set_attr "mode" "QI")
> +   (set_attr "type" "mskmov")
> +   (set_attr "prefix" "vex")])
> +
> +(define_insn "kmovd"
> +  [(set (match_operand:SI 0 "nonimmediate_operand" "=k,k")
> + (unspec:SI
> +  [(match_operand:SI 1 "nonimmediate_operand" "r,km")]
> +  UNSPEC_KMOV))]
> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512BW"
> +  "@
> +   kmovd\t{%k1, %0|%0, %k1}
> +   kmovd\t{%1, %0|%0, %1}";
> +  [(set_attr "mode" "SI")
> +   (set_attr "type" "mskmov")
> +   (set_attr "prefix" "vex")])
> +
> +(define_insn "kmovq"
> +  [(set (match_operand:DI 0 "nonimmediate_operand" "=k,k,km")
> + (unspec:DI
> +  [(match_operand:DI 1 "nonimmediate_operand" "r,km,k")]
> +  UNSPEC_KMOV))]
> +  "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512BW"
> +  "@
> +   kmovq\t{%k1, %0|%0, %k1}
> +   kmovq\t{%1, %0|%0, %1}
> +   kmovq\t{%1, %0|%0, %1}";
> +  [(set_attr "mode" "DI")
> +   (set_attr "type" "mskmov")
> +   (set_attr "prefix" "vex")])
>
> - kmovd (and existing kmovw) should be using register_operand for
> opreand 0. In this case, there is no need for MEM_P checks at all.
> - In the insn constraint, pease check TARGET_AVX before checking MEM_P.
> - please put these definitions above corresponding *mov??_internal patterns.

Do you mean put below *mov??_internal patterns? Attached corrected such way.


--
WBR,
Andrew


add_k-mask_intrinsics_11.11.patch
Description: Binary data

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

[Andrew Senkevich]

2016-11-10 20:14 GMT+03:00 Vladimir N Makarov <vmaka...@redhat.com>:
>
>
> On 11/10/2016 11:27 AM, Andrew Senkevich wrote:
>>
>> Hi,
>>
>> this patch enabled AVX512_4FMAPS and AVX512_4VNNIW instructions.
>>
>> It requires additional patch for register allocator from Vladimir
>> Makarov to be committed before.
>>
>>
> I've just committed the necessary patch.

Thanks, Vladimir.


--
WBR,
Andrew

Re: [PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

[Andrew Senkevich]

2016-11-10 19:36 GMT+03:00 Jakub Jelinek <ja...@redhat.com>:
> On Thu, Nov 10, 2016 at 07:27:00PM +0300, Andrew Senkevich wrote:
>> Hi,
>>
>> this patch enabled AVX512_4FMAPS and AVX512_4VNNIW instructions.
>>
>> It requires additional patch for register allocator from Vladimir
>> Makarov to be committed before.
>
> Your MUA ate tabs (and in the ChangeLog you're using spaces instead of
> tabs), can you repost as attachment or configure your MUA not to do this?
>
> Just a couple of random nits follow:
>
>> * gcc.target/i386/sse-12.c: Add -mavx5124fmaddps.
>
> This mentions an option that doesn't exist, is that s/dd// ?

Yes.
Attached fixed version.


--
WBR,
Andrew


new_avx512_instructions.patch
Description: Binary data

[PATCH] Enable Intel AVX512_4FMAPS and AVX512_4VNNIW instructions

[Andrew Senkevich]

Hi,

this patch enabled AVX512_4FMAPS and AVX512_4VNNIW instructions.

It requires additional patch for register allocator from Vladimir
Makarov to be committed before.

gcc/
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_AVX5124FMAPS_SET,
OPTION_MASK_ISA_AVX5124FMAPS_UNSET,
OPTION_MASK_ISA_AVX5124VNNIW_SET,
OPTION_MASK_ISA_AVX5124VNNIW_UNSET): New.
(ix86_handle_option): Handle OPT_mavx5124fmaps,
OPT_mavx5124vnniw.
* config.gcc: Add avx5124fmapsintrin.h, avx5124vnniwintrin.h.
* config/i386/avx5124fmapsintrin.h: New file.
* config/i386/avx5124vnniwintrin.h: Ditto.
* config/i386/constraints.md (h): New constraint.
* config/i386/cpuid.h: (bit_AVX5124VNNIW,
bit_AVX5124FMAPS): New.
* config/i386/driver-i386.c (host_detect_local_cpu):
Detect avx5124fmaps, avx5124vnniw.
* config/i386/i386-builtin-types.def: Add types
V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF_V16SF_UHI,
V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF,
V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF,
V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF_V4SF_UQI,
V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI,
V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI.
* config/i386/i386-builtin.def (__builtin_ia32_4fmaddps_mask,
__builtin_ia32_4fmaddps, __builtin_ia32_4fmaddss,
__builtin_ia32_4fmaddss_mask, __builtin_ia32_4fnmaddps_mask,
__builtin_ia32_4fnmaddps, __builtin_ia32_4fnmaddss,
__builtin_ia32_4fnmaddss_mask, __builtin_ia32_vp4dpwssd,
__builtin_ia32_vp4dpwssd_mask, __builtin_ia32_vp4dpwssds,
__builtin_ia32_vp4dpwssds_mask): New.
* config/i386/i386-c.c (ix86_target_macros_internal):
Define __AVX5124FMAPS__, __AVX5124VNNIW__.
* config/i386/i386-modes.def (VECTOR_MODES (FLOAT, 256),
VECTOR_MODE (INT, SI, 64)): New modes.
* config/i386/i386.c (ix86_target_string): Add -mavx5124fmaps,
-mavx5124vnniw.
(PTA_AVX5124FMAPS, PTA_AVX5124VNNIW): Define.
(ix86_option_override_internal): Handle new options.
(ix86_valid_target_attribute_inner_p): Add avx5124fmaps,
avx5124vnniw.
(ix86_expand_builtin): Handle new builtins.
(ix86_additional_allocno_class_p): New.
* config/i386/i386.h (TARGET_AVX5124FMAPS,
TARGET_AVX5124FMAPS_P,
TARGET_AVX5124VNNIW,
TARGET_AVX5124VNNIW_P): Define.
(reg_class): Add MOD4_SSE_REGS.
(MOD4_SSE_REG_P, MOD4_SSE_REGNO_P): New.
* config/i386/i386.opt: Add mavx5124fmaps, mavx5124vnniw.
* config/i386/immintrin.h: Include avx5124fmapsintrin.h,
avx5124vnniwintrin.h.
* config/i386/sse.md (unspec): Add UNSPEC_VP4FMADD,
UNSPEC_VP4FNMADD,
UNSPEC_VP4DPWSSD, UNSPEC_VP4DPWSSDS.
(define_mode_iterator IMOD4): New.
(define_mode_attr imod4_narrow): Ditto.
(define_insn "mov"): Ditto.
(define_insn "avx5124fmaddps_4fmaddps"): Ditto.
(define_insn "avx5124fmaddps_4fmaddps_mask"): Ditto.
(define_insn "avx5124fmaddps_4fmaddps_maskz"): Ditto.
(define_insn "avx5124fmaddps_4fmaddss"): Ditto.
(define_insn "avx5124fmaddps_4fmaddss_mask"): Ditto.
(define_insn "avx5124fmaddps_4fmaddss_maskz"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddps"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddps_mask"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddps_maskz"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddss"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddss_mask"): Ditto.
(define_insn "avx5124fmaddps_4fnmaddss_maskz"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssd"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssd_mask"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssd_maskz"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssds"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssds_mask"): Ditto.
(define_insn "avx5124vnniw_vp4dpwssds_maskz"): Ditto.
* init-regs.c (initialize_uninitialized_regs): Add emit_clobber call.
* genmodes.c (mode_size_inline): Extend return type.
* machmode.h (mode_size, mode_base_align): Extend type.
gcc/testsuite/
* gcc.target/i386/avx5124fmadd-v4fmaddps-1.c: New test.
* gcc.target/i386/avx5124fmadd-v4fmaddps-2.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fmaddss-1.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddps-1.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddps-2.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddss-1.c: Ditto.
* gcc.target/i386/avx5124fmaps-check.h: Ditto.
* gcc.target/i386/avx5124vnniw-check.h: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssd-1.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssd-2.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssds-1.c: Ditto.
   

Re: [PATCH] Remove x86 pcommit instruction

[Andrew Senkevich]

> That said - why do we need to remove pcommit support on the branches at all?

I think it is better to have old branches updated because pcommit will
not be implemented in hardware.


--
WBR,
Andrew

Re: [PATCH] Remove x86 pcommit instruction

[Andrew Senkevich]

2016-10-11 20:09 GMT+03:00 H.J. Lu <hjl.to...@gmail.com>:
> On Tue, Oct 11, 2016 at 10:04 AM, Andrew Senkevich
> <andrew.n.senkev...@gmail.com> wrote:
>> 2016-10-06 1:07 GMT+03:00 H.J. Lu <hjl.to...@gmail.com>:
>>> On Wed, Oct 5, 2016 at 1:42 PM, Andrew Senkevich
>>> <andrew.n.senkev...@gmail.com> wrote:
>>>> 2016-10-05 18:06 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>>>> On Wed, Oct 5, 2016 at 3:47 PM, Andrew Senkevich
>>>>> <andrew.n.senkev...@gmail.com> wrote:
>>>>>>> -mpcommit
>>>>>>> -Target Report Mask(ISA_PCOMMIT) Var(ix86_isa_flags) Save
>>>>>>> -Support PCOMMIT instruction.
>>>>>>> -
>>>>>>>
>>>>>>> You should not simply delete a option that was in the released
>>>>>>> compiler, but a warning should be emitted instead. Please see how
>>>>>>> msse5 is handled in i386.opt.
>>>>>>
>>>>>> Thank you, it is fixed in patch below. Ok for trunk?
>>>>>
>>>>> OK.
>>>>>
>>>>>> Is it subject for backport for 5.* and 6.* releases?
>>>>>
>>>>> Yes, but please wait a couple of days if any problem arises in trunk.
>>>>>
>>>>> (Please also provide an entry for Release Changes, since this is
>>>>> user-facing change. Also for release branches.)
>>>>
>>>> Hi HJ,
>>>>
>>>> could you please commit this patch for trunk since I have no commit rights.
>>>> Attached in format for git am.
>>>>
>>>>
>>>
>>> Done.
>>
>> Thanks, HJ!
>>
>> Should I ask you or somebody else for backports for to 5.* and 6.* or
>> may be I can somehow get commit after approval rights to don't disturb
>> others with commits? I am preparing several patches.
>>
>
> Please provide patches for GCC 5 and 6.

Attached.

Have you possibility to update according changes.html files?


--
WBR,
Andrew


remove_pcommit_gcc-5-branch.patch
Description: Binary data


remove_pcommit_gcc-6-branch.patch
Description: Binary data

Re: [PATCH] Remove x86 pcommit instruction

[Andrew Senkevich]

2016-10-06 1:07 GMT+03:00 H.J. Lu <hjl.to...@gmail.com>:
> On Wed, Oct 5, 2016 at 1:42 PM, Andrew Senkevich
> <andrew.n.senkev...@gmail.com> wrote:
>> 2016-10-05 18:06 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
>>> On Wed, Oct 5, 2016 at 3:47 PM, Andrew Senkevich
>>> <andrew.n.senkev...@gmail.com> wrote:
>>>>> -mpcommit
>>>>> -Target Report Mask(ISA_PCOMMIT) Var(ix86_isa_flags) Save
>>>>> -Support PCOMMIT instruction.
>>>>> -
>>>>>
>>>>> You should not simply delete a option that was in the released
>>>>> compiler, but a warning should be emitted instead. Please see how
>>>>> msse5 is handled in i386.opt.
>>>>
>>>> Thank you, it is fixed in patch below. Ok for trunk?
>>>
>>> OK.
>>>
>>>> Is it subject for backport for 5.* and 6.* releases?
>>>
>>> Yes, but please wait a couple of days if any problem arises in trunk.
>>>
>>> (Please also provide an entry for Release Changes, since this is
>>> user-facing change. Also for release branches.)
>>
>> Hi HJ,
>>
>> could you please commit this patch for trunk since I have no commit rights.
>> Attached in format for git am.
>>
>>
>
> Done.

Thanks, HJ!

Should I ask you or somebody else for backports for to 5.* and 6.* or
may be I can somehow get commit after approval rights to don't disturb
others with commits? I am preparing several patches.



--
WBR,
Andrew

Re: [PATCH] Remove x86 pcommit instruction

[Andrew Senkevich]

2016-10-05 18:06 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>:
> On Wed, Oct 5, 2016 at 3:47 PM, Andrew Senkevich
> <andrew.n.senkev...@gmail.com> wrote:
>>> -mpcommit
>>> -Target Report Mask(ISA_PCOMMIT) Var(ix86_isa_flags) Save
>>> -Support PCOMMIT instruction.
>>> -
>>>
>>> You should not simply delete a option that was in the released
>>> compiler, but a warning should be emitted instead. Please see how
>>> msse5 is handled in i386.opt.
>>
>> Thank you, it is fixed in patch below. Ok for trunk?
>
> OK.
>
>> Is it subject for backport for 5.* and 6.* releases?
>
> Yes, but please wait a couple of days if any problem arises in trunk.
>
> (Please also provide an entry for Release Changes, since this is
> user-facing change. Also for release branches.)

Hi HJ,

could you please commit this patch for trunk since I have no commit rights.
Attached in format for git am.


--
WBR,
Andrew


0001-Deleted-x86-pcommit-instruction-since-it-is-deprecat.patch
Description: Binary data

Re: [PATCH] Remove x86 pcommit instruction

[Andrew Senkevich]

> (Please also provide an entry for Release Changes, since this is
> user-facing change. Also for release branches.)

What is BKM for doing that for 7.1 release? File a PR and mention it
in ChangeLog?


--
WBR,
Andrew

Re: [PATCH] Remove x86 pcommit instruction

[Andrew Senkevich]

> -mpcommit
> -Target Report Mask(ISA_PCOMMIT) Var(ix86_isa_flags) Save
> -Support PCOMMIT instruction.
> -
>
> You should not simply delete a option that was in the released
> compiler, but a warning should be emitted instead. Please see how
> msse5 is handled in i386.opt.

Thank you, it is fixed in patch below. Ok for trunk?

Is it subject for backport for 5.* and 6.* releases?


2016-10-05  Andrew Senkevich  <andrew.senkev...@intel.com>

gcc/

* common/config/i386/i386-common.c (OPTION_MASK_ISA_PCOMMIT_UNSET,
OPTION_MASK_ISA_PCOMMIT_SET): Deleted definitions.
(ix86_handle_option): Deleted handle of OPT_mpcommit.
* config.gcc: Deleted pcommitintrin.h
* config/i386/pcommitintrin.h: Deleted file.
* config/i386/cpuid.h (bit_PCOMMIT): Deleted.
* config/i386/driver-i386.c (host_detect_local_cpu): Deleted pcommit
detection.
* config/i386/i386-c.c (ix86_target_macros_internal): Deleted define
__PCOMMIT__.
* config/i386/i386.c (ix86_target_string): Deleted -mpcommit.
(PTA_PCOMMIT): Deleted define.
(ix86_option_override_internal): Deleted handle of option.
(ix86_valid_target_attribute_inner_p): Deleted pcommit.
* config/i386/i386-builtin.def (IX86_BUILTIN_PCOMMIT,
__builtin_ia32_pcommit): Deleted.
* config/i386/i386.h (TARGET_PCOMMIT, TARGET_PCOMMIT_P): Deleted.
* config/i386/i386.md (unspecv): Deleted UNSPECV_PCOMMIT.
(pcommit): Deleted instruction.
* config/i386/i386.opt: Warning about mpcommit deprecation.
* config/i386/x86intrin.h: Deleted inclusion of pcommitintrin.h.

gcc/testsuite/

* gcc.target/i386/pcommit-1.c: Deleted.
* gcc.target/i386/sse-12.c: Deleted -mpcommit option.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.


diff --git a/gcc/common/config/i386/i386-common.c
b/gcc/common/config/i386/i386-common.c
index 4f0a55f..ce1b5f7 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -86,7 +86,6 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_XSAVEC_SET \
   (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE)
 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
-#define OPTION_MASK_ISA_PCOMMIT_SET OPTION_MASK_ISA_PCOMMIT

 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2.  */
@@ -187,7 +186,6 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
-#define OPTION_MASK_ISA_PCOMMIT_UNSET OPTION_MASK_ISA_PCOMMIT
 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
 #define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO
@@ -933,19 +931,6 @@ ix86_handle_option (struct gcc_options *opts,
}
   return true;

-case OPT_mpcommit:
-  if (value)
-   {
- opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCOMMIT_SET;
- opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCOMMIT_SET;
-   }
-  else
-   {
- opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCOMMIT_UNSET;
- opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCOMMIT_UNSET;
-   }
-  return true;
-
 case OPT_mclwb:
   if (value)
{
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7d24561..8fd07c5 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -373,8 +373,8 @@ i[34567]86-*-*)
   xsavesintrin.h avx512dqintrin.h avx512bwintrin.h
   avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h
   avx512ifmaintrin.h avx512ifmavlintrin.h
avx512vbmiintrin.h
-  avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h
-  mwaitxintrin.h clzerointrin.h pkuintrin.h"
+  avx512vbmivlintrin.h clwbintrin.h mwaitxintrin.h
+  clzerointrin.h pkuintrin.h"
;;
 x86_64-*-*)
cpu_type=i386
@@ -395,8 +395,8 @@ x86_64-*-*)
   xsavesintrin.h avx512dqintrin.h avx512bwintrin.h
   avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h
   avx512ifmaintrin.h avx512ifmavlintrin.h
avx512vbmiintrin.h
-  avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h
-  mwaitxintrin.h clzerointrin.h pkuintrin.h"
+  avx512vbmivlintrin.h clwbintrin.h mwaitxintrin.h
+  clzerointrin.h pkuintrin.h"
;;
 ia64-*-*)
extra_headers=i

[PATCH] Remove x86 pcommit instruction

[Andrew Senkevich]

Hi,

this patch removes PCOMMIT instruction since it was deprecated,

please visit 
https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction
for details.

Regtested on x86_64.  Is it Ok for trunk?

2016-10-03  Andrew Senkevich  <andrew.senkev...@intel.com>

gcc/

* common/config/i386/i386-common.c (OPTION_MASK_ISA_PCOMMIT_UNSET,
OPTION_MASK_ISA_PCOMMIT_SET): Deleted definitions.
(ix86_handle_option): Deleted handle of OPT_mpcommit.
* config.gcc: Deleted pcommitintrin.h
* config/i386/pcommitintrin.h: Deleted file.
* config/i386/cpuid.h (bit_PCOMMIT): Deleted.
* config/i386/driver-i386.c (host_detect_local_cpu): Deleted pcommit
detection.
* config/i386/i386-c.c (ix86_target_macros_internal): Deleted define
__PCOMMIT__.
* config/i386/i386.c (ix86_target_string): Deleted -mpcommit.
(PTA_PCOMMIT): Deleted define.
(ix86_option_override_internal): Deleted handle of option.
(ix86_valid_target_attribute_inner_p): Deleted pcommit.
* config/i386/i386-builtin.def (IX86_BUILTIN_PCOMMIT,
__builtin_ia32_pcommit): Deleted.
* config/i386/i386.h (TARGET_PCOMMIT, TARGET_PCOMMIT_P): Deleted.
* config/i386/i386.md (unspecv): Deleted UNSPECV_PCOMMIT.
(pcommit): Deleted instruction.
* config/i386/i386.opt: Deleted mpcommit.
* config/i386/x86intrin.h: Deleted inclusion of pcommitintrin.h.

gcc/testsuite/

* gcc.target/i386/pcommit-1.c: Deleted.
* gcc.target/i386/sse-12.c: Deleted -mpcommit option.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.


diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2b771d1..0728a9d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,35 @@
+2016-10-03  Andrew Senkevich  <andrew.senkev...@intel.com>
+
+   * common/config/i386/i386-common.c (OPTION_MASK_ISA_PCOMMIT_UNSET,
+   OPTION_MASK_ISA_PCOMMIT_SET): Deleted definitions.
+   (ix86_handle_option): Deleted handle of OPT_mpcommit.
+   * config.gcc: Deleted pcommitintrin.h
+   * config/i386/pcommitintrin.h: Deleted.
+   * config/i386/cpuid.h (bit_PCOMMIT): Deleted.
+   * config/i386/driver-i386.c (host_detect_local_cpu): Deleted pcommit
+   detection.
+   * config/i386/i386-c.c (ix86_target_macros_internal): Deleted define
+   __PCOMMIT__.
+   * config/i386/i386.c (ix86_target_string): Deleted -mpcommit.
+   (PTA_PCOMMIT): Deleted define.
+   (ix86_option_override_internal): Deleted handle of option.
+   (ix86_valid_target_attribute_inner_p): Deleted pcommit.
+   * config/i386/i386-builtin.def (IX86_BUILTIN_PCOMMIT,
+   __builtin_ia32_pcommit): Deleted.
+   * config/i386/i386.h (TARGET_PCOMMIT, TARGET_PCOMMIT_P): Deleted.
+   * config/i386/i386.md (unspecv): Deleted UNSPECV_PCOMMIT.
+   (pcommit): Deleted instruction.
+   * config/i386/i386.opt: Add mpcommit.
+   * config/i386/x86intrin.h: Delete inclusion of pcommitintrin.h.
+   * testsuite/gcc.target/i386/pcommit-1.c: Deleted.
+   * gcc/testsuite/gcc.target/i386/sse-12.c: Deleted -pcommit option.
+   * gcc/testsuite/gcc.target/i386/sse-13.c: Ditto.
+   * gcc/testsuite/gcc.target/i386/sse-14.c: Ditto.
+   * gcc/testsuite/gcc.target/i386/sse-22.c: Ditto.
+   * gcc/testsuite/gcc.target/i386/sse-23.c: Ditto.
+   * gcc/testsuite/g++.dg/other/i386-2.C: Ditto.
+   * gcc/testsuite/g++.dg/other/i386-3.C: Ditto.
+
 2016-10-03  Kyrylo Tkachov  <kyrylo.tkac...@arm.com>

Revert
diff --git a/gcc/common/config/i386/i386-common.c
b/gcc/common/config/i386/i386-common.c
index 4f0a55f..ce1b5f7 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -86,7 +86,6 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_XSAVEC_SET \
   (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE)
 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
-#define OPTION_MASK_ISA_PCOMMIT_SET OPTION_MASK_ISA_PCOMMIT

 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2.  */
@@ -187,7 +186,6 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
-#define OPTION_MASK_ISA_PCOMMIT_UNSET OPTION_MASK_ISA_PCOMMIT
 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
 #define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO
@@ -933,19 +931,6 @@ ix86_handle_option (struct gcc_options *opts,
}
   return true;

-case OPT_mpcommit