[gcc-wwwdocs PATCH] gcc-14: Mention -march=gracemont support in x86_64

[Haochen Jiang]

Hi all,

When I was backporting my doc patch in gcc trunk today, I found when adding
-march=gracemont in GCC14, the corresponding wwwdoc is missing. This patch
is adding that.

Ok for wwwdocs trunk?

Thx,
Haochen

---
 htdocs/gcc-14/changes.html | 4 
 1 file changed, 4 insertions(+)

diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index e0d856cc..ba9fc680 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -944,6 +944,10 @@ __asm (".global __flmap_lock"  "\n\t"
 Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16,
 PREFETCHI, SHA512, SM3, SM4 and USER_MSR ISA extensions.
   
+  GCC now supports the Intel CPU named Gracemont through
+-march=gracemont.
+Gracemont is based on Alder Lake.
+  
   GCC now supports the Intel CPU named Arrow Lake through
 -march=arrowlake.
 Based on Alder Lake, the switch further enables the AVX-IFMA,
-- 
2.31.1

[PATCH v2] i386: Enhance AVX10.2 convert tests

[Haochen Jiang]

Hi all,

For AVX10.2 convert tests, all of them are missing mask tests
previously, this patch will add them in the tests.

Tested on sde with assembler with corresponding insts. Ok for trunk?

Thx,
Haochen

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c: Enhance mask test.
* gcc.target/i386/avx10_2-512-vcvtbiasph2bf8-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtbiasph2hf8-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvthf82ph-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtne2ph2bf8-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtne2ph2bf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtne2ph2hf8-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtne2ph2hf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtneph2bf8-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtneph2bf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtneph2hf8-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtneph2hf8s-2.c: Ditto.
* gcc.target/i386/avx512f-helper.h: Fix a typo in macro define.
---
 .../i386/avx10_2-512-vcvt2ps2phx-2.c  | 35 ---
 .../i386/avx10_2-512-vcvtbiasph2bf8-2.c   | 25 ++---
 .../i386/avx10_2-512-vcvtbiasph2bf8s-2.c  | 28 ---
 .../i386/avx10_2-512-vcvtbiasph2hf8-2.c   | 25 ++---
 .../i386/avx10_2-512-vcvtbiasph2hf8s-2.c  | 25 ++---
 .../i386/avx10_2-512-vcvthf82ph-2.c   | 27 ++
 .../i386/avx10_2-512-vcvtne2ph2bf8-2.c| 25 ++---
 .../i386/avx10_2-512-vcvtne2ph2bf8s-2.c   | 25 ++---
 .../i386/avx10_2-512-vcvtne2ph2hf8-2.c| 25 ++---
 .../i386/avx10_2-512-vcvtne2ph2hf8s-2.c   | 25 ++---
 .../i386/avx10_2-512-vcvtneph2bf8-2.c | 29 ++-
 .../i386/avx10_2-512-vcvtneph2bf8s-2.c| 27 ++
 .../i386/avx10_2-512-vcvtneph2hf8-2.c | 27 ++
 .../i386/avx10_2-512-vcvtneph2hf8s-2.c| 27 ++
 .../gcc.target/i386/avx512f-helper.h  |  2 +-
 15 files changed, 295 insertions(+), 82 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c
index 40dbe18abbe..5e355ae53d4 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c
@@ -10,24 +10,25 @@
 #include "avx10-helper.h"
 #include 
 
-#define SIZE_RES (AVX512F_LEN / 16)
+#define SIZE (AVX512F_LEN / 16)
+#include "avx512f-mask-type.h"
 
 static void
 CALC (_Float16 *res_ref, float *src1, float *src2)
 {
   float fp32;
   int i;
-  for (i = 0; i < SIZE_RES / 2; i++)
+  for (i = 0; i < SIZE / 2; i++)
 {
   fp32 = (float) 2 * i + 7 + i * 0.5;
   res_ref[i] = fp32;
   src2[i] = fp32;
 }
-  for (i = SIZE_RES / 2; i < SIZE_RES; i++)
+  for (i = SIZE / 2; i < SIZE; i++)
 {
   fp32 = (float)2 * i + 7 + i * 0.5;
   res_ref[i] = fp32;
-  src1[i - (SIZE_RES / 2)] = fp32;
+  src1[i - (SIZE / 2)] = fp32;
 }
 }
 
@@ -35,17 +36,27 @@ void
 TEST (void)
 {
   int i;
-  UNION_TYPE (AVX512F_LEN, h) res1;
+  UNION_TYPE (AVX512F_LEN, h) res1, res2, res3;
   UNION_TYPE (AVX512F_LEN, ) src1, src2;
-  _Float16 res_ref[SIZE_RES];
-  float fp32;
-  
-  for (i = 0; i < SIZE_RES; i++)
-res1.a[i] = 5;
-  
+  MASK_TYPE mask = MASK_VALUE;
+  _Float16 res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+res2.a[i] = DEFAULT_VALUE;
+
   CALC (res_ref, src1.a, src2.a);
-  
+
   res1.x = INTRINSIC (_cvtx2ps_ph) (src1.x, src2.x);
   if (UNION_CHECK (AVX512F_LEN, h) (res1, res_ref))
 abort ();
+
+  res2.x = INTRINSIC (_mask_cvtx2ps_ph) (res2.x, mask, src1.x, src2.x);
+  MASK_MERGE (h) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, h) (res2, res_ref))
+abort ();
+
+  res3.x = INTRINSIC (_maskz_cvtx2ps_ph) (mask, src1.x, src2.x);
+  MASK_ZERO (h) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, h) (res3, res_ref))
+abort ();
 }
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8-2.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8-2.c
index 9ce3c9059f1..08450418dae 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvtbiasph2bf8-2.c
@@ -15,6 +15,9 @@
 #define SRC_F16 (AVX512F_LEN / 16)
 #define DST_F8_I8 (AVX512F_LEN_HALF / 8)
 #define DST_F16 (AVX512F_LEN_HALF / 16)
+#define SIZE SRC_F16 
+
+#include "avx512f-mask-type.h"
 
 void
 CALC (unsigned char *r, char *src1, _Float16 *src2)
@@ -39,9 +42,10 @@ void
 TEST (void)
 {
   int i,sign;
-  UNION_TYPE (AVX512F_LEN_HALF, i_b) res; 
+  UNION_TYPE (AVX512F_LEN_HALF, i_b) res1, res2, res3; 
   UNION_TYPE (AVX512F_LEN, i_b) src1;
   UNION_TYPE (AVX512F_LEN, h) src2;
+  MASK_TYPE mask = 

[PATCH] i386: Enhance AVX10.2 convert tests

[Haochen Jiang]

Hi all,

For AVX10.2 convert tests, all of them are missing mask tests
previously, this patch will add them in the tests.

Tested on sde with assembler with these insts. Ok for trunk?

Thx,
Haochen

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c: Enhance mask test.
* gcc.target/i386/avx10_2-512-vcvthf82ph-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtne2ph2bf8-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtne2ph2bf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtne2ph2hf8-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtne2ph2hf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtneph2bf8-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtneph2bf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtneph2hf8-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtneph2hf8s-2.c: Ditto.
* gcc.target/i386/avx512f-helper.h: Fix a typo in macro define.
---
 .../i386/avx10_2-512-vcvt2ps2phx-2.c  | 35 ---
 .../i386/avx10_2-512-vcvthf82ph-2.c   | 27 ++
 .../i386/avx10_2-512-vcvtne2ph2bf8-2.c| 25 ++---
 .../i386/avx10_2-512-vcvtne2ph2bf8s-2.c   | 25 ++---
 .../i386/avx10_2-512-vcvtne2ph2hf8-2.c| 25 ++---
 .../i386/avx10_2-512-vcvtne2ph2hf8s-2.c   | 25 ++---
 .../i386/avx10_2-512-vcvtneph2bf8-2.c | 29 ++-
 .../i386/avx10_2-512-vcvtneph2bf8s-2.c| 27 ++
 .../i386/avx10_2-512-vcvtneph2hf8-2.c | 27 ++
 .../i386/avx10_2-512-vcvtneph2hf8s-2.c| 27 ++
 .../gcc.target/i386/avx512f-helper.h  |  2 +-
 11 files changed, 209 insertions(+), 65 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c
index 40dbe18abbe..5e355ae53d4 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvt2ps2phx-2.c
@@ -10,24 +10,25 @@
 #include "avx10-helper.h"
 #include 
 
-#define SIZE_RES (AVX512F_LEN / 16)
+#define SIZE (AVX512F_LEN / 16)
+#include "avx512f-mask-type.h"
 
 static void
 CALC (_Float16 *res_ref, float *src1, float *src2)
 {
   float fp32;
   int i;
-  for (i = 0; i < SIZE_RES / 2; i++)
+  for (i = 0; i < SIZE / 2; i++)
 {
   fp32 = (float) 2 * i + 7 + i * 0.5;
   res_ref[i] = fp32;
   src2[i] = fp32;
 }
-  for (i = SIZE_RES / 2; i < SIZE_RES; i++)
+  for (i = SIZE / 2; i < SIZE; i++)
 {
   fp32 = (float)2 * i + 7 + i * 0.5;
   res_ref[i] = fp32;
-  src1[i - (SIZE_RES / 2)] = fp32;
+  src1[i - (SIZE / 2)] = fp32;
 }
 }
 
@@ -35,17 +36,27 @@ void
 TEST (void)
 {
   int i;
-  UNION_TYPE (AVX512F_LEN, h) res1;
+  UNION_TYPE (AVX512F_LEN, h) res1, res2, res3;
   UNION_TYPE (AVX512F_LEN, ) src1, src2;
-  _Float16 res_ref[SIZE_RES];
-  float fp32;
-  
-  for (i = 0; i < SIZE_RES; i++)
-res1.a[i] = 5;
-  
+  MASK_TYPE mask = MASK_VALUE;
+  _Float16 res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+res2.a[i] = DEFAULT_VALUE;
+
   CALC (res_ref, src1.a, src2.a);
-  
+
   res1.x = INTRINSIC (_cvtx2ps_ph) (src1.x, src2.x);
   if (UNION_CHECK (AVX512F_LEN, h) (res1, res_ref))
 abort ();
+
+  res2.x = INTRINSIC (_mask_cvtx2ps_ph) (res2.x, mask, src1.x, src2.x);
+  MASK_MERGE (h) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, h) (res2, res_ref))
+abort ();
+
+  res3.x = INTRINSIC (_maskz_cvtx2ps_ph) (mask, src1.x, src2.x);
+  MASK_ZERO (h) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, h) (res3, res_ref))
+abort ();
 }
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvthf82ph-2.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvthf82ph-2.c
index 6b9f07ff86a..1aa5daa6c58 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvthf82ph-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vcvthf82ph-2.c
@@ -12,13 +12,14 @@
 #include "fp8-helper.h"
 
 #define SIZE_SRC (AVX512F_LEN_HALF / 8)
-#define SIZE_RES (AVX512F_LEN / 16)
+#define SIZE (AVX512F_LEN / 16)
+#include "avx512f-mask-type.h"
 
 void
 CALC (_Float16 *r, unsigned char *s)
 {
   int i;
-  for (i = 0; i < SIZE_RES; i++)
+  for (i = 0; i < SIZE; i++)
 r[i] = convert_hf8_to_fp16(s[i]);
 }
 
@@ -26,9 +27,10 @@ void
 TEST (void)
 {
   int i,sign;
-  UNION_TYPE (AVX512F_LEN, h) res;
+  UNION_TYPE (AVX512F_LEN, h) res1, res2, res3;
   UNION_TYPE (AVX512F_LEN_HALF, i_b) src;
-  _Float16 res_ref[SIZE_RES];
+  MASK_TYPE mask = MASK_VALUE;
+  _Float16 res_ref[SIZE];
 
   sign = 1;
   for (i = 0; i < SIZE_SRC; i++)
@@ -37,9 +39,22 @@ TEST (void)
   sign = -sign;
 }
 
-  res.x = INTRINSIC (_cvthf8_ph) (src.x);
+  for (i = 0; i < SIZE; i++)
+res2.a[i] = DEFAULT_VALUE;
+
   CALC(res_ref, src.a);
 
-  if (UNION_ROUGH_CHECK (AVX512F_LEN, h) (res, res_ref, 0.0009765625))
+  res1.x = INTRINSIC (_cvthf8_ph) (src.x);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, h) (res1, res_ref, 0.000976562

[PATCH] i386: Add missing avx512f-mask-type.h include

[Haochen Jiang]

Hi all,

Since commit r15-3594, we fixed the bugs in MASK_TYPE for AVX10.2
testcases, but we missed the following four.

The tests are not FAIL since the binutils part haven't been merged
yet, which leads to UNSUPPORTED test. But the avx512f-mask-type.h
needs to be included, otherwise, it will be compile error.

Tested with asseblmer having those insts and sde. Ok for trunk?

Thx,
Haochen

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_2-512-vpdpbssd-2.c: Include
avx512f-mask-type.h.
* gcc.target/i386/avx10_2-vminmaxsd-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxsh-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxss-2.c: Ditto.
---
 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbssd-2.c | 2 ++
 gcc/testsuite/gcc.target/i386/avx10_2-vminmaxsd-2.c| 1 +
 gcc/testsuite/gcc.target/i386/avx10_2-vminmaxsh-2.c| 1 +
 gcc/testsuite/gcc.target/i386/avx10_2-vminmaxss-2.c| 1 +
 4 files changed, 5 insertions(+)

diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbssd-2.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbssd-2.c
index add9de89351..624a1a8e50e 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbssd-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbssd-2.c
@@ -13,6 +13,8 @@
 #define SRC_SIZE (AVX512F_LEN / 8)
 #define SIZE (AVX512F_LEN / 32)
 
+#include "avx512f-mask-type.h"
+
 static void
 CALC (int *r, int *dst, char *s1, char *s2)
 {
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxsd-2.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxsd-2.c
index 1e2d78c4068..f550e09be6c 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxsd-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxsd-2.c
@@ -8,6 +8,7 @@
 #include "avx10-helper.h"
 #include 
 #include "avx10-minmax-helper.h"
+#include "avx512f-mask-type.h"
 
 void static
 CALC (double *r, double *s1, double *s2, int R)
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxsh-2.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxsh-2.c
index e6a93c403b5..dbf1087d9c3 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxsh-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxsh-2.c
@@ -8,6 +8,7 @@
 #include "avx10-helper.h"
 #include 
 #include "avx10-minmax-helper.h"
+#include "avx512f-mask-type.h"
 
 void static
 CALC (_Float16 *r, _Float16 *s1, _Float16 *s2, int R)
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxss-2.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxss-2.c
index 47177e69640..7baa396a2d3 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxss-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-vminmaxss-2.c
@@ -8,6 +8,7 @@
 #include "avx10-helper.h"
 #include 
 #include "avx10-minmax-helper.h"
+#include "avx512f-mask-type.h"
 
 void static
 CALC (float *r, float *s1, float *s2, int R)
-- 
2.31.1

[PATCH] doc: Add more alias option and reorder Intel CPU -march documentation

[Haochen Jiang]

Hi all,

Since r15-3539, there are requests coming in to add other alias option
documentation. This patch will add all ot them, including corei7, corei7-avx,
core-avx-i, core-avx2, atom, slm, gracemont and emerarldrapids.

Also in the patch, I reordered that part of documentation, currently all
the CPUs/products are just all over the place. I regrouped them by
date-to-now products (since the very first CPU to latest Panther Lake), P-core
(since the clients become hybrid cores, starting from Sapphire Rapids) and
E-core (since Bonnell to latest Clearwater Forest).

And in the patch, I refined the product names in documentation.

Ok for trunk?

Thx,
Haochen

gcc/ChangeLog:

* doc/invoke.texi: Add corei7, corei7-avx, core-avx-i,
core-avx2, atom, slm, gracemont and emerarldrapids. Reorder
the -march documentation by splitting them into date-to-now
products, P-core and E-core. Refine the product names in
documentation.
---
 gcc/doc/invoke.texi | 234 +++-
 1 file changed, 121 insertions(+), 113 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a6cd5111d47..23e1d8577e7 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -34598,6 +34598,7 @@ Intel Core 2 CPU with 64-bit extensions, MMX, SSE, 
SSE2, SSE3, SSSE3, CX16,
 SAHF and FXSR instruction set support.
 
 @item nehalem
+@itemx corei7
 Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, CX16, SAHF and FXSR instruction set support.
 
@@ -34606,16 +34607,19 @@ Intel Westmere CPU with 64-bit extensions, MMX, SSE, 
SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR and PCLMUL instruction set support.
 
 @item sandybridge
+@itemx corei7-avx
 Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE and PCLMUL instruction set
 support.
 
 @item ivybridge
+@itemx core-avx-i
 Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND
 and F16C instruction set support.
 
 @item haswell
+@itemx core-avx2
 Intel Haswell CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,
 F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE and HLE instruction set support.
@@ -34632,61 +34636,6 @@ SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, 
PCLMUL, FSGSBASE, RDRND,
 F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES,
 CLFLUSHOPT, XSAVEC, XSAVES and SGX instruction set support.
 
-@item bonnell
-Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
-instruction set support.
-
-@item silvermont
-Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, 
SSSE3,
-SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, PCLMUL, PREFETCHW and RDRND
-instruction set support.
-
-@item goldmont
-Intel Goldmont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, PCLMUL, PREFETCHW, RDRND, AES, SHA,
-RDSEED, XSAVE, XSAVEC, XSAVES, XSAVEOPT, CLFLUSHOPT and FSGSBASE instruction
-set support.
-
-@item goldmont-plus
-Intel Goldmont Plus CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
-SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, PCLMUL, PREFETCHW, RDRND, AES,
-SHA, RDSEED, XSAVE, XSAVEC, XSAVES, XSAVEOPT, CLFLUSHOPT, FSGSBASE, PTWRITE,
-RDPID and SGX instruction set support.
-
-@item tremont
-Intel Tremont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, PCLMUL, PREFETCHW, RDRND, AES, SHA,
-RDSEED, XSAVE, XSAVEC, XSAVES, XSAVEOPT, CLFLUSHOPT, FSGSBASE, PTWRITE, RDPID,
-SGX, CLWB, GFNI-SSE, MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG instruction set
-support.
-
-@item sierraforest
-Intel Sierra Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
-SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
-XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
-MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
-PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
-AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD and UINTR instruction set
-support.
-
-@item grandridge
-Intel Grand Ridge CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
-SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
-XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
-MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
-PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
-AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD and UINTR instruction set
-support.
-
-@item clearwaterforest
-Intel Clearwater Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE

[PATCH] doc: Enhance Intel CPU documentation

[Haochen Jiang]

Hi all,

This patch will add those recent aliased CPU names into documentation
for clearness.

Ready to push for trunk and backport to GCC14 and part of the patch to
GCC13 as an obvious fix if no objection.

Thx,
Haochen

gcc/ChangeLog:

PR target/116617
* doc/invoke.texi: Add meteorlake, raptorlake and lunarlake.
---
 gcc/doc/invoke.texi | 25 ++---
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 019e0a5ca80..b9a86a9a181 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -34741,12 +34741,14 @@ UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, 
AVX512-FP16 and AVX512BF16
 instruction set support.
 
 @item alderlake
-Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES,
-XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B,
-CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU,
-VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL and AVX-VNNI instruction set
-support.
+@itemx raptorlake
+@itemx meteorlake
+Intel Alderlake/Raptorlake/Meteorlake CPU with 64-bit extensions, MOVBE, MMX,
+SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND,
+XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB,
+MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA,
+LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL and
+AVX-VNNI instruction set support.
 
 @item rocketlake
 Intel Rocketlake CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3
@@ -34788,11 +34790,12 @@ UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT and 
CMPCCXADD instruction set
 support.
 
 @item arrowlake-s
-Intel Arrow Lake S CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
-SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
-XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
-MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
-PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
+@itemx lunarlake
+Intel Arrow Lake S/Lunarlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
+SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE,
+XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB,
+MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA,
+LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
 UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512,
 SM3 and SM4 instruction set support.
 
-- 
2.31.1

[PATCH] i386: Fix incorrect avx512f-mask-type.h include

[Haochen Jiang]

Hi all,

In avx512f-mask-type.h, we need SIZE being defined to get
MASK_TYPE defined correctly. Fix those testcases where
SIZE are not defined before the include for avv512f-mask-type.h.

Note that for convert intrins in AVX10.2, they will need more
modifications due to the current tests did not include mask ones.
They will be in a seperate patch.

Tested on x86-64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10-helper.h: Do not include
avx512f-mask-type.h.
* gcc.target/i386/avx10_2-512-vaddnepbf16-2.c:
Define SIZE and include avx512f-mask-type.h.
* gcc.target/i386/avx10_2-512-vcmppbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtnebf162ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtnebf162iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtph2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtph2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtps2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtps2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttnebf162ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttnebf162iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttpd2dqs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttpd2qqs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttpd2udqs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttpd2uqqs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttph2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttps2dqs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttps2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttps2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttps2qqs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttps2udqs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttps2uqqs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vdivnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vdpphps-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vfmaddXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vfmsubXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vfnmaddXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vfnmsubXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vfpclasspbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vgetexppbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vgetmantpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vmaxpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vminmaxnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vminmaxpd-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vminmaxph-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vminmaxps-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vminpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vmpsadbw-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vmulnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbssd-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbssds-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbsud-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbsuds-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbuud-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbuuds-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwsud-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwsuds-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwusd-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwusds-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwuud-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwuuds-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vrcppbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vreducenepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vrndscalenepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vrsqrtpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vscalefpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vsqrtnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vsubnepbf16-2.c: Ditto.
* gcc.target/i386/avx512fp16-vfpclassph-1b.c: Ditto.
---
 gcc/testsuite/gcc.target/i386/avx10-helper.h  |  1 -
 .../i386/avx10_2-512-vaddnepbf16-2.c  | 11 +-
 .../gcc.target/i386/avx10_2-512-vcmppbf16-2.c |  5 +++--
 .../i386/avx10_2-512-vcvtnebf162ibs-2.c   | 16 +++---
 .../i386/avx10_2-512-vcvtnebf162iubs-2.c  | 16 +++---
 .../i386/avx10_2-512-vcvtph2ibs-2.c   | 16 +++---
 .../i386/avx10_2-512-vcvtph2iubs-2.c  | 16 +++---
 .../i386/avx10_2-512-vcvtps2ibs-2.c   | 16 +++---
 .../i386/avx10_2-512-vcvtps2iubs-2.c  | 16 +++---
 .../i386/avx10_2-512-vcvttnebf162ibs-2.c  | 16 +++---
 .../i386/avx10_2-512-vcvttnebf162iubs-2.c | 16 +++---
 .../i386/avx10_2-512-vcvttpd2dqs-2.c  | 

[PATCH] i386: Fix vfpclassph non-optimizied intrin

[Haochen Jiang]

Hi all,

The intrin for non-optimized got a typo in mask type, which will cause
the high bits of __mmask32 being unexpectedly zeroed.

The test does not fail under O0 with current 1b since the testcase is
wrong. We need to include avx512-mask-type.h after SIZE is defined, or
it will always be __mmask8. That problem also happened in AVX10.2 testcases.
I will write a seperate patch to fix that.

Bootstrapped and tested on x86-64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

gcc/ChangeLog:

* config/i386/avx512fp16intrin.h
(_mm512_mask_fpclass_ph_mask): Correct mask type to __mmask32.
(_mm512_fpclass_ph_mask): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512fp16-vfpclassph-1c.c: New test.
---
 gcc/config/i386/avx512fp16intrin.h|  4 +-
 .../i386/avx512fp16-vfpclassph-1c.c   | 77 +++
 2 files changed, 79 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vfpclassph-1c.c

diff --git a/gcc/config/i386/avx512fp16intrin.h 
b/gcc/config/i386/avx512fp16intrin.h
index 1869a920dd3..c3096b74ad2 100644
--- a/gcc/config/i386/avx512fp16intrin.h
+++ b/gcc/config/i386/avx512fp16intrin.h
@@ -3961,11 +3961,11 @@ _mm512_fpclass_ph_mask (__m512h __A, const int __imm)
 #else
 #define _mm512_mask_fpclass_ph_mask(u, x, c)   \
   ((__mmask32) __builtin_ia32_fpclassph512_mask ((__v32hf) (__m512h) (x), \
-(int) (c),(__mmask8)(u)))
+(int) (c),(__mmask32)(u)))
 
 #define _mm512_fpclass_ph_mask(x, c)\
   ((__mmask32) __builtin_ia32_fpclassph512_mask ((__v32hf) (__m512h) (x), \
-(int) (c),(__mmask8)-1))
+(int) (c),(__mmask32)-1))
 #endif /* __OPIMTIZE__ */
 
 /* Intrinsics vgetexpph.  */
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclassph-1c.c 
b/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclassph-1c.c
new file mode 100644
index 000..4739f1228e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfpclassph-1c.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-options "-O0 -mavx512fp16" } */
+/* { dg-require-effective-target avx512fp16 } */
+
+#define AVX512FP16
+#include "avx512f-helper.h"
+
+#include 
+#include 
+#include 
+#define SIZE (AVX512F_LEN / 16)
+#include "avx512f-mask-type.h"
+
+#ifndef __FPCLASSPH__
+#define __FPCLASSPH__
+int check_fp_class_hp (_Float16 src, int imm)
+{
+  int qNaN_res = isnan (src);
+  int sNaN_res = isnan (src);
+  int Pzero_res = (src == 0.0);
+  int Nzero_res = (src == -0.0);
+  int PInf_res = (isinf (src) == 1);
+  int NInf_res = (isinf (src) == -1);
+  int Denorm_res = (fpclassify (src) == FP_SUBNORMAL);
+  int FinNeg_res = __builtin_finite (src) && (src < 0);
+
+  int result = (((imm & 1) && qNaN_res)
+   || (((imm >> 1) & 1) && Pzero_res)
+   || (((imm >> 2) & 1) && Nzero_res)
+   || (((imm >> 3) & 1) && PInf_res)
+   || (((imm >> 4) & 1) && NInf_res)
+   || (((imm >> 5) & 1) && Denorm_res)
+   || (((imm >> 6) & 1) && FinNeg_res)
+   || (((imm >> 7) & 1) && sNaN_res));
+  return result;
+}
+#endif
+
+MASK_TYPE
+CALC (_Float16 *s1, int imm)
+{
+  int i;
+  MASK_TYPE res = 0;
+
+  for (i = 0; i < SIZE; i++)
+if (check_fp_class_hp(s1[i], imm))
+  res = res | (1 << i);
+
+  return res;
+}
+
+void
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, h) src;
+  MASK_TYPE res1, res2, res_ref = 0;
+  MASK_TYPE mask = MASK_VALUE;
+
+  src.a[SIZE - 1] = NAN;
+  src.a[SIZE - 2] = 1.0 / 0.0;
+  for (i = 0; i < SIZE - 2; i++)
+{
+  src.a[i] = -24.43 + 0.6 * i;
+}
+
+  res1 = INTRINSIC (_fpclass_ph_mask) (src.x, 0xFF);
+  res2 = INTRINSIC (_mask_fpclass_ph_mask) (mask, src.x, 0xFF);
+
+  res_ref = CALC (src.a, 0xFF);
+
+  if (res_ref != res1)
+abort ();
+
+  if ((mask & res_ref) != res2)
+abort ();
+}
-- 
2.31.1

[gcc-wwwdocs PATCH] gcc-15: Mention recent update for x86_64 backend

[Haochen Jiang]

Hi all,

Sorry for the disturb since I mis-typoed gcc-patches to gcc-patchs, resend
the patch.

This patch will add documentation for recent update in x86-64 backend.

Ok for wwwdocs trunk?

Thx,
Haochen

---

Mention AVX10.2 support and Xeon Phi removal in GCC 15.

---
 htdocs/gcc-15/changes.html | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index d0d6d147..4cb0fa90 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -132,7 +132,23 @@ a work-in-progress.
 code like 1 << offset is not fast enough.
 
 
-
+IA-32/x86-64
+
+
+  New ISA extension support for Intel AVX10.2 was added.
+  AVX10.2 intrinsics are available via the -mavx10.2 or
+  -mavx10.2-256 compiler switch with 256-bit vector size
+  support. 512-bit vector size support for AVX10.2 intrinsics are
+  available via the -mavx10.2-512 compiler switch.
+  
+  Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) were 
removed
+  in GCC 15. GCC will no longer accept -mavx5124fmaps,
+  -mavx5124vnniw, -mavx512er,
+  -mavx512pf, -mprefetchwt1,
+  -march=knl, -march=knm, -mtune=knl
+  or -mtune=knm compiler switches.
+  
+
 
 
 
-- 
2.31.1

[PATCH 4/8] i386: Support vectorized BF16 add/sub/mul/div with AVX10.2 instructions

[Haochen Jiang]

From: Levy Hsu 

AVX10.2 introduces several non-exception instructions for BF16 vector.
Enable vectorized BF add/sub/mul/div operation by supporting standard
optab for them.

gcc/ChangeLog:

* config/i386/sse.md (div3): New expander for BFmode div.
(VF_BHSD): New mode iterator with vector BFmodes.
(3): Change mode to VF_BHSD.
(mul3): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_2-512-bf-vector-operations-1.c: New test.
* gcc.target/i386/avx10_2-bf-vector-operations-1.c: Ditto.
---
 gcc/config/i386/sse.md| 49 ++--
 .../i386/avx10_2-512-bf-vector-operations-1.c | 42 ++
 .../i386/avx10_2-bf-vector-operations-1.c | 79 +++
 3 files changed, 162 insertions(+), 8 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-operations-1.c
 create mode 100644 
gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-operations-1.c

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 442ac93afa2..ebca462bae8 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -391,6 +391,19 @@
(V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX")
(V2DF "TARGET_SSE2")])
 
+(define_mode_iterator VF_BHSD
+  [(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")
+   (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
+   (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
+   (V16SF "TARGET_AVX512F && TARGET_EVEX512")
+   (V8SF "TARGET_AVX") V4SF
+   (V8DF "TARGET_AVX512F && TARGET_EVEX512")
+   (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")
+   (V32BF "TARGET_AVX10_2_512")
+   (V16BF "TARGET_AVX10_2_256")
+   (V8BF "TARGET_AVX10_2_256")
+  ])
+
 ;; 128-, 256- and 512-bit float vector modes for bitwise operations
 (define_mode_iterator VFB
   [(V32BF "TARGET_AVX512F && TARGET_EVEX512")
@@ -2527,10 +2540,10 @@
 })
 
 (define_expand "3"
-  [(set (match_operand:VFH 0 "register_operand")
-   (plusminus:VFH
- (match_operand:VFH 1 "")
- (match_operand:VFH 2 "")))]
+  [(set (match_operand:VF_BHSD 0 "register_operand")
+   (plusminus:VF_BHSD
+ (match_operand:VF_BHSD 1 "")
+ (match_operand:VF_BHSD 2 "")))]
   "TARGET_SSE &&  && "
   "ix86_fixup_binary_operands_no_copy (, mode, operands);")
 
@@ -2616,10 +2629,10 @@
 })
 
 (define_expand "mul3"
-  [(set (match_operand:VFH 0 "register_operand")
-   (mult:VFH
- (match_operand:VFH 1 "")
- (match_operand:VFH 2 "")))]
+  [(set (match_operand:VF_BHSD 0 "register_operand")
+   (mult:VF_BHSD
+ (match_operand:VF_BHSD 1 "")
+ (match_operand:VF_BHSD 2 "")))]
   "TARGET_SSE &&  && "
   "ix86_fixup_binary_operands_no_copy (MULT, mode, operands);")
 
@@ -2734,6 +2747,26 @@
 }
 })
 
+(define_expand "div3"
+  [(set (match_operand:VBF_AVX10_2 0 "register_operand")
+   (div:VBF_AVX10_2
+ (match_operand:VBF_AVX10_2 1 "register_operand")
+ (match_operand:VBF_AVX10_2 2 "vector_operand")))]
+  "TARGET_AVX10_2_256"
+{
+  if (TARGET_RECIP_VEC_DIV
+  && optimize_insn_for_speed_p ()
+  && flag_finite_math_only
+  && flag_unsafe_math_optimizations)
+{
+  rtx op = gen_reg_rtx (mode);
+  operands[2] = force_reg (mode, operands[2]);
+  emit_insn (gen_avx10_2_rcppbf16_ (op, operands[2]));
+  emit_insn (gen_avx10_2_mulnepbf16_ (operands[0], operands[1], op));
+  DONE;
+}
+})
+
 (define_expand "cond_div"
   [(set (match_operand:VFH 0 "register_operand")
(vec_merge:VFH
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-operations-1.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-operations-1.c
new file mode 100644
index 000..d6b0750c233
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-operations-1.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10.2-512 -O2" } */
+/* { dg-final { scan-assembler-times "vmulnepbf16\[ 
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vaddnepbf16\[ 
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vdivnepbf16\[ 
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vsubnepbf16\[ 
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrcppbf16\[ 
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include 
+
+typedef __bf16 v32bf __attribute__ ((__vector_size__ (64)));
+
+v32bf
+foo_mul (v32bf a, v32bf b)
+{
+  return a * b;
+}
+
+v32bf
+foo_add (v32bf a, v32bf b)
+{
+  return a + b;
+}
+
+v32bf
+foo_div (v32bf a, v32bf b)
+{
+  return a / b;
+}
+
+v32bf
+foo_sub (v32bf a, v32bf b)
+{
+  return a - b;
+}
+
+__attribute__((optimize("fast-math")))
+v32bf
+

[PATCH 8/8] i386: Support vec_cmp for V8BF/V16BF/V32BF in AVX10.2

[Haochen Jiang]

From: Levy Hsu 

gcc/ChangeLog:

* config/i386/i386-expand.cc (ix86_use_mask_cmp_p): Add BFmode
  for int mask cmp.
* config/i386/sse.md (vec_cmp): New
  vec_cmp expand for VBF modes.

gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_2-512-bf-vector-cmpp-1.c: New test.
* gcc.target/i386/avx10_2-bf-vector-cmpp-1.c: New test.
---
 gcc/config/i386/i386-expand.cc|  2 ++
 gcc/config/i386/sse.md| 13 +
 .../i386/avx10_2-512-bf-vector-cmpp-1.c   | 19 
 .../i386/avx10_2-bf-vector-cmpp-1.c   | 29 +++
 4 files changed, 63 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-cmpp-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-cmpp-1.c

diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 53327544620..124cb976ec8 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -4036,6 +4036,8 @@ ix86_use_mask_cmp_p (machine_mode mode, machine_mode 
cmp_mode,
 return true;
   else if (GET_MODE_INNER (cmp_mode) == HFmode)
 return true;
+  else if (GET_MODE_INNER (cmp_mode) == BFmode)
+return true;
 
   /* When op_true is NULL, op_false must be NULL, or vice versa.  */
   gcc_assert (!op_true == !op_false);
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 2de592a9c8f..3bf95f0b0e5 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -4797,6 +4797,19 @@
   DONE;
 })
 
+(define_expand "vec_cmp"
+  [(set (match_operand: 0 "register_operand")
+   (match_operator: 1 ""
+ [(match_operand:VBF_AVX10_2 2 "register_operand")
+  (match_operand:VBF_AVX10_2 3 "nonimmediate_operand")]))]
+  "TARGET_AVX10_2_256"
+{
+  bool ok = ix86_expand_mask_vec_cmp (operands[0], GET_CODE (operands[1]),
+ operands[2], operands[3]);
+  gcc_assert (ok);
+  DONE;
+})
+
 (define_expand "vec_cmp"
   [(set (match_operand: 0 "register_operand")
(match_operator: 1 ""
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-cmpp-1.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-cmpp-1.c
new file mode 100644
index 000..416fcaa3628
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-cmpp-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10.2-512 -O2 -mprefer-vector-width=512" } */
+/* { dg-final { scan-assembler-times "vcmppbf16" 5 } } */
+
+typedef __bf16 v32bf __attribute__ ((__vector_size__ (64)));
+
+#define VCMPMN(type, op, name) \
+type  \
+__attribute__ ((noinline, noclone)) \
+vec_cmp_##type##type##name (type a, type b) \
+{ \
+  return a op b;  \
+}
+
+VCMPMN (v32bf, <, lt)
+VCMPMN (v32bf, <=, le)
+VCMPMN (v32bf, >, gt)
+VCMPMN (v32bf, >=, ge)
+VCMPMN (v32bf, ==, eq)
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-cmpp-1.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-cmpp-1.c
new file mode 100644
index 000..6234116039f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-cmpp-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10.2 -O2" } */
+/* { dg-final { scan-assembler-times "vcmppbf16" 10 } } */
+
+typedef __bf16 v16bf __attribute__ ((__vector_size__ (32)));
+typedef __bf16 v8bf __attribute__ ((__vector_size__ (16)));
+
+#define VCMPMN(type, op, name) \
+type  \
+__attribute__ ((noinline, noclone)) \
+vec_cmp_##type##type##name (type a, type b) \
+{ \
+  return a op b;  \
+}
+
+VCMPMN (v16bf, <, lt)
+VCMPMN (v8bf, <, lt)
+
+VCMPMN (v16bf, <=, le)
+VCMPMN (v8bf, <=, le)
+
+VCMPMN (v16bf, >, gt)
+VCMPMN (v8bf, >, gt)
+
+VCMPMN (v16bf, >=, ge)
+VCMPMN (v8bf, >=, ge)
+
+VCMPMN (v16bf, ==, eq)
+VCMPMN (v8bf, ==, eq)
-- 
2.31.1

[PATCH 6/8] i386: Support vectorized BF16 smaxmin with AVX10.2 instructions

[Haochen Jiang]

From: Levy Hsu 

gcc/ChangeLog:

* config/i386/sse.md
(3): New define expand pattern for BF smaxmin.

gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_2-512-bf-vector-smaxmin-1.c: New test.
* gcc.target/i386/avx10_2-bf-vector-smaxmin-1.c: New test.
---
 gcc/config/i386/sse.md|  7 
 .../i386/avx10_2-512-bf-vector-smaxmin-1.c| 20 +++
 .../i386/avx10_2-bf-vector-smaxmin-1.c| 36 +++
 3 files changed, 63 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-smaxmin-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-smaxmin-1.c

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 85fbef331ea..b374783429c 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -31901,6 +31901,13 @@
"vscalefpbf16\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "prefix" "evex")])
 
+(define_expand "3"
+  [(set (match_operand:VBF_AVX10_2 0 "register_operand")
+ (smaxmin:VBF_AVX10_2
+   (match_operand:VBF_AVX10_2 1 "register_operand")
+   (match_operand:VBF_AVX10_2 2 "nonimmediate_operand")))]
+  "TARGET_AVX10_2_256")
+
 (define_insn "avx10_2_pbf16_"
[(set (match_operand:VBF_AVX10_2 0 "register_operand" "=v")
   (smaxmin:VBF_AVX10_2
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-smaxmin-1.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-smaxmin-1.c
new file mode 100644
index 000..e33c325e2da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-smaxmin-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10.2-512 -mprefer-vector-width=512 -Ofast" } */
+/* /* { dg-final { scan-assembler-times "vmaxpbf16" 1 } } */
+/* /* { dg-final { scan-assembler-times "vminpbf16" 1 } } */
+
+void
+maxpbf16_512 (__bf16* dest, __bf16* src1, __bf16* src2)
+{
+  int i;
+  for (i = 0; i < 32; i++)
+dest[i] = src1[i] > src2[i] ? src1[i] : src2[i];
+}
+
+void
+minpbf16_512 (__bf16* dest, __bf16* src1, __bf16* src2)
+{
+  int i;
+  for (i = 0; i < 32; i++)
+dest[i] = src1[i] < src2[i] ? src1[i] : src2[i];
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-smaxmin-1.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-smaxmin-1.c
new file mode 100644
index 000..9bae073c95a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-smaxmin-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10.2 -Ofast" } */
+/* /* { dg-final { scan-assembler-times "vmaxpbf16" 2 } } */
+/* /* { dg-final { scan-assembler-times "vminpbf16" 2 } } */
+
+void
+maxpbf16_256 (__bf16* dest, __bf16* src1, __bf16* src2)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+dest[i] = src1[i] > src2[i] ? src1[i] : src2[i];
+}
+
+void
+minpbf16_256 (__bf16* dest, __bf16* src1, __bf16* src2)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+dest[i] = src1[i] < src2[i] ? src1[i] : src2[i];
+}
+
+void
+maxpbf16_128 (__bf16* dest, __bf16* src1, __bf16* src2)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+dest[i] = src1[i] > src2[i] ? src1[i] : src2[i];
+}
+
+void
+minpbf16_128 (__bf16* dest, __bf16* src1, __bf16* src2)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+dest[i] = src1[i] < src2[i] ? src1[i] : src2[i];
+}
-- 
2.31.1

[PATCH 3/8] i386: Optimize generate insn for avx10.2 compare

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/i386-expand.cc (ix86_expand_fp_compare): Add UNSPEC to
support the optimization.
* config/i386/i386.cc (ix86_fp_compare_code_to_integer): Add NE/EQ.
* config/i386/i386.md (*cmpx): New define_insn.
(*cmpxhf): Ditto.
* config/i386/predicates.md (ix86_trivial_fp_comparison_operator):
Add ne/eq.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_2-compare-1b.c: New test.
---
 gcc/config/i386/i386-expand.cc|  5 +
 gcc/config/i386/i386.cc   |  5 +
 gcc/config/i386/i386.md   | 31 +-
 gcc/config/i386/predicates.md | 12 +++
 .../gcc.target/i386/avx10_2-compare-1b.c  | 96 +++
 5 files changed, 147 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-compare-1b.c

diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index d692008ffe7..53327544620 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -2916,6 +2916,11 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx 
op1)
   switch (ix86_fp_comparison_strategy (code))
 {
 case IX86_FPCMP_COMI:
+  tmp = gen_rtx_COMPARE (CCFPmode, op0, op1);
+  if (TARGET_AVX10_2_256 && (code == EQ || code == NE))
+   tmp = gen_rtx_UNSPEC (CCFPmode, gen_rtvec (1, tmp), UNSPEC_OPTCOMX);
+  if (unordered_compare)
+   tmp = gen_rtx_UNSPEC (CCFPmode, gen_rtvec (1, tmp), UNSPEC_NOTRAP);
   cmp_mode = CCFPmode;
   emit_insn (gen_rtx_SET (gen_rtx_REG (CCFPmode, FLAGS_REG), tmp));
   break;
diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 224a78cc832..a4454d393d5 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -16623,6 +16623,11 @@ ix86_fp_compare_code_to_integer (enum rtx_code code)
   return LEU;
 case LTGT:
   return NE;
+case EQ:
+case NE:
+  if (TARGET_AVX10_2_256)
+   return code;
+  /* FALLTHRU.  */
 default:
   return UNKNOWN;
 }
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index b56a51be09f..0fae3c1eb87 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -117,6 +117,7 @@
   UNSPEC_STC
   UNSPEC_PUSHFL
   UNSPEC_POPFL
+  UNSPEC_OPTCOMX
 
   ;; For SSE/MMX support:
   UNSPEC_FIX_NOTRUNC
@@ -1736,7 +1737,7 @@
(compare:CC (match_operand:XF 1 "nonmemory_operand")
(match_operand:XF 2 "nonmemory_operand")))
(set (pc) (if_then_else
-  (match_operator 0 "ix86_fp_comparison_operator"
+  (match_operator 0 "ix86_fp_comparison_operator_xf"
[(reg:CC FLAGS_REG)
 (const_int 0)])
   (label_ref (match_operand 3))
@@ -1753,7 +1754,7 @@
(compare:CC (match_operand:XF 2 "nonmemory_operand")
(match_operand:XF 3 "nonmemory_operand")))
(set (match_operand:QI 0 "register_operand")
-  (match_operator 1 "ix86_fp_comparison_operator"
+  (match_operator 1 "ix86_fp_comparison_operator_xf"
[(reg:CC FLAGS_REG)
 (const_int 0)]))]
   "TARGET_80387"
@@ -2017,6 +2018,32 @@
(set_attr "bdver1_decode" "double")
(set_attr "znver1_decode" "double")])
 
+(define_insn "*cmpx"
+  [(set (reg:CCFP FLAGS_REG)
+   (unspec:CCFP [
+ (compare:CCFP
+   (match_operand:MODEF 0 "register_operand" "v")
+   (match_operand:MODEF 1 "nonimmediate_operand" "vm"))]
+ UNSPEC_OPTCOMX))]
+  "TARGET_AVX10_2_256"
+  "%vcomx\t{%1, %0|%0, %1}"
+  [(set_attr "type" "ssecomi")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "")])
+
+(define_insn "*cmpxhf"
+  [(set (reg:CCFP FLAGS_REG)
+   (unspec:CCFP [
+ (compare:CCFP
+   (match_operand:HF 0 "register_operand" "v")
+   (match_operand:HF 1 "nonimmediate_operand" "vm"))]
+ UNSPEC_OPTCOMX))]
+  "TARGET_AVX10_2_256"
+  "vcomxsh\t{%1, %0|%0, %1}"
+  [(set_attr "type" "ssecomi")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "HF")])
+
 (define_insn "*cmpi"
   [(set (reg:CCFP FLAGS_REG)
(compare:CCFP
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index ab6a2e14d35..053312bbe27 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1633,7 +1633,13 @@
 })
 
 ;; Return true if this comparison only requires testing one flag bit.
+;; VCOMX/VUCOMX set ZF, SF, OF, differently from COMI/UCOMI.
 (define_predicate "ix86_trivial_fp_comparison_operator"
+  (if_then_else (match_test "TARGET_AVX10_2_256")
+   (match_code "gt,ge,unlt,unle,eq,uneq,ne,ltgt,ordered,unordered")
+   (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered")))
+
+(define_predicate "ix86_trivial_fp_comparison_operator_xf"
   (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
 
 ;; Return true if we know how to do this comp

[PATCH 7/8] i386: Support vectorized BF16 sqrt with AVX10.2 instruction

[Haochen Jiang]

From: Levy Hsu 

gcc/ChangeLog:

* config/i386/sse.md: Expand VF2H to VF2HB with VBF modes.
---
 gcc/config/i386/sse.md | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b374783429c..2de592a9c8f 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -447,9 +447,12 @@
 (define_mode_iterator VF2_AVX10_2
   [(V8DF "TARGET_AVX10_2_512") V4DF V2DF])
 
-;; All DFmode & HFmode vector float modes
-(define_mode_iterator VF2H
-  [(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")
+;; All DFmode & HFmode & BFmode vector float modes
+(define_mode_iterator VF2HB
+  [(V32BF "TARGET_AVX10_2_512")
+   (V16BF "TARGET_AVX10_2_256")
+   (V8BF "TARGET_AVX10_2_256")
+   (V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")
(V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
(V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
(V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") V2DF])
@@ -2933,8 +2936,8 @@
(set_attr "mode" "")])
 
 (define_expand "sqrt2"
-  [(set (match_operand:VF2H 0 "register_operand")
-   (sqrt:VF2H (match_operand:VF2H 1 "vector_operand")))]
+  [(set (match_operand:VF2HB 0 "register_operand")
+   (sqrt:VF2HB (match_operand:VF2HB 1 "vector_operand")))]
   "TARGET_SSE2")
 
 (define_expand "sqrt2"
-- 
2.31.1

[PATCH 5/8] i386: Support vectorized BF16 FMA with AVX10.2 instructions

[Haochen Jiang]

From: Levy Hsu 

gcc/ChangeLog:

* config/i386/sse.md: Add V8BF/V16BF/V32BF to mode iterator FMAMODEM.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_2-512-bf-vector-fma-1.c: New test.
* gcc.target/i386/avx10_2-bf-vector-fma-1.c: New test.
---
 gcc/config/i386/sse.md|  5 +-
 .../i386/avx10_2-512-bf-vector-fma-1.c| 34 ++
 .../gcc.target/i386/avx10_2-bf-vector-fma-1.c | 63 +++
 3 files changed, 101 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-fma-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-fma-1.c

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index ebca462bae8..85fbef331ea 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -5677,7 +5677,10 @@
(HF "TARGET_AVX512FP16")
(V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
(V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
-   (V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")])
+   (V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")
+   (V8BF "TARGET_AVX10_2_256")
+   (V16BF "TARGET_AVX10_2_256")
+   (V32BF "TARGET_AVX10_2_512")])
 
 (define_expand "fma4"
   [(set (match_operand:FMAMODEM 0 "register_operand")
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-fma-1.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-fma-1.c
new file mode 100644
index 000..a857f9b90db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-bf-vector-fma-1.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10.2-512 -O2" } */
+/* { dg-final { scan-assembler-times "vfmadd132nepbf16\[ 
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub132nepbf16\[ 
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132nepbf16\[ 
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132nepbf16\[ 
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+
+#include 
+
+typedef __bf16 v32bf __attribute__ ((__vector_size__ (64)));
+
+v32bf
+foo_madd (v32bf a, v32bf b, v32bf c)
+{
+  return a * b + c;
+}
+
+v32bf
+foo_msub (v32bf a, v32bf b, v32bf c)
+{
+  return a * b - c;
+}
+
+v32bf
+foo_nmadd (v32bf a, v32bf b, v32bf c)
+{
+  return -a * b + c;
+}
+
+v32bf
+foo_nmsub (v32bf a, v32bf b, v32bf c)
+{
+  return -a * b - c;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-fma-1.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-fma-1.c
new file mode 100644
index 000..0fd78efe049
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-bf-vector-fma-1.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10.2 -O2" } */
+/* { dg-final { scan-assembler-times "vfmadd132nepbf16\[ 
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub132nepbf16\[ 
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132nepbf16\[ 
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132nepbf16\[ 
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd132nepbf16\[ 
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub132nepbf16\[ 
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132nepbf16\[ 
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132nepbf16\[ 
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ 
\\t\]+#)" 1 } } */
+
+#include 
+
+typedef __bf16 v16bf __attribute__ ((__vector_size__ (32)));
+typedef __bf16 v8bf __attribute__ ((__vector_size__ (16)));
+
+v16bf
+foo_madd_256 (v16bf a, v16bf b, v16bf c)
+{
+  return a * b + c;
+}
+
+v16bf
+foo_msub_256 (v16bf a, v16bf b, v16bf c)
+{
+  return a * b - c;
+}
+
+v16bf
+foo_nmadd_256 (v16bf a, v16bf b, v16bf c)
+{
+  return -a * b + c;
+}
+
+v16bf
+foo_nmsub_256 (v16bf a, v16bf b, v16bf c)
+{
+  return -a * b - c;
+}
+
+v8bf
+foo_madd_128 (v8bf a, v8bf b, v8bf c)
+{
+  return a * b + c;
+}
+
+v8bf
+foo_msub_128 (v8bf a, v8bf b, v8bf c)
+{
+  return a * b - c;
+}
+
+v8bf
+foo_nmadd_128 (v8bf a, v8bf b, v8bf c)
+{
+  return -a * b + c;
+}
+
+v8bf
+foo_nmsub_128 (v8bf a, v8bf b, v8bf c)
+{
+  return -a * b - c;
+}
-- 
2.31.1

[PATCH 0/8] i386: Opmitize code with AVX10.2 new instructions

[Haochen Jiang]

Hi all,

I have just commited AVX10.2 new instructions patches into trunk hours
ago. The next and final part for AVX10.2 upstream is to optimize code
with AVX10.2 new instructions.

In this patch series, it will contain the following optimizations:

  - VNNI instruction auto vectorize (PATCH 1).
  - Codegen optimization with new scalar comparison instructions to
eliminate redundant code (PATCH 2-3).
  - BF16 instruction auto vectorize (PATCH 4-8).

This will finish the upstream for AVX10.2 series.

Afterwards, we may add V2BF/V4BF in another thread just like what we
have done for V2HF/V4HF when AVX512FP16 upstreamed.

Bootstrapped on x86-64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

[PATCH 2/8] i386: Optimize ordered and nonequal

[Haochen Jiang]

From: "Hu, Lin1" 

Currently, when we input !__builtin_isunordered (a, b) && (a != b), gcc
will emit
  ucomiss %xmm1, %xmm0
  movl $1, %ecx
  setp %dl
  setnp %al
  cmovne %ecx, %edx
  andl %edx, %eax
  movzbl %al, %eax

In fact,
  xorl %eax, %eax
  ucomiss %xmm1, %xmm0
  setne %al
is better.

gcc/ChangeLog:

* match.pd: Optimize (and ordered non-equal) to
(not (or unordered  equal))

gcc/testsuite/ChangeLog:

* gcc.target/i386/optimize_one.c: New test.
---
 gcc/match.pd | 3 +++
 gcc/testsuite/gcc.target/i386/optimize_one.c | 9 +
 2 files changed, 12 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/optimize_one.c

diff --git a/gcc/match.pd b/gcc/match.pd
index 78f1957e8c7..aaadd2e977c 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -6636,6 +6636,9 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
  (ltgt @0 @0)
  (if (!flag_trapping_math || !tree_expr_maybe_nan_p (@0))
   { constant_boolean_node (false, type); }))
+(simplify
+ (bit_and (ordered @0 @1) (ne @0 @1))
+ (bit_not (uneq @0 @1)))
 
 /* x == ~x -> false */
 /* x != ~x -> true */
diff --git a/gcc/testsuite/gcc.target/i386/optimize_one.c 
b/gcc/testsuite/gcc.target/i386/optimize_one.c
new file mode 100644
index 000..62728d3c5ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/optimize_one.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfpmath=sse" } */
+/* { dg-final { scan-assembler-times "comi" 1 } } */
+/* { dg-final { scan-assembler-times "set" 1 } } */
+
+int is_ordered_or_nonequal_sh (float a, float b)
+{
+  return !__builtin_isunordered (a, b) && (a != b);
+}
-- 
2.31.1

[PATCH 1/8] i386: Auto vectorize sdot_prod, usdot_prod, udot_prod with AVX10.2 instructions

[Haochen Jiang]

gcc/ChangeLog:

* config/i386/sse.md (VI1_AVX512VNNIBW): New.
(VI2_AVX10_2): Ditto.
(sdot_prod): Add AVX10.2
to auto vectorize and combine 512 bit part.
(udot_prod): Ditto.
(sdot_prodv64qi): Removed.
(udot_prodv64qi): Ditto.
(usdot_prod): Add AVX10.2 to auto vectorize.
(udot_prod): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/vnniint16-auto-vectorize-2.c: Only define
TEST when not defined.
* gcc.target/i386/vnniint8-auto-vectorize-2.c: Ditto.
* gcc.target/i386/vnniint16-auto-vectorize-3.c: New test.
* gcc.target/i386/vnniint16-auto-vectorize-4.c: Ditto.
* gcc.target/i386/vnniint8-auto-vectorize-3.c: Ditto.
* gcc.target/i386/vnniint8-auto-vectorize-4.c: Ditto.
---
 gcc/config/i386/sse.md| 93 +--
 .../i386/vnniint16-auto-vectorize-2.c | 11 ++-
 .../i386/vnniint16-auto-vectorize-3.c |  6 ++
 .../i386/vnniint16-auto-vectorize-4.c | 15 +++
 .../i386/vnniint8-auto-vectorize-2.c  | 12 ++-
 .../i386/vnniint8-auto-vectorize-3.c  |  6 ++
 .../i386/vnniint8-auto-vectorize-4.c  | 15 +++
 7 files changed, 80 insertions(+), 78 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/vnniint16-auto-vectorize-3.c
 create mode 100644 gcc/testsuite/gcc.target/i386/vnniint16-auto-vectorize-4.c
 create mode 100644 gcc/testsuite/gcc.target/i386/vnniint8-auto-vectorize-3.c
 create mode 100644 gcc/testsuite/gcc.target/i386/vnniint8-auto-vectorize-4.c

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index da91d39cf8e..442ac93afa2 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -610,6 +610,10 @@
 (define_mode_iterator VI1_AVX512VNNI
   [(V64QI "TARGET_AVX512VNNI && TARGET_EVEX512") (V32QI "TARGET_AVX2") V16QI])
 
+(define_mode_iterator VI1_AVX512VNNIBW
+  [(V64QI "(TARGET_AVX512BW || TARGET_AVX512VNNI) && TARGET_EVEX512")
+   (V32QI "TARGET_AVX2") V16QI])
+
 (define_mode_iterator VI12_256_512_AVX512VL
   [(V64QI "TARGET_EVEX512") (V32QI "TARGET_AVX512VL")
(V32HI "TARGET_EVEX512") (V16HI "TARGET_AVX512VL")])
@@ -627,6 +631,9 @@
   [(V32HI "(TARGET_AVX512BW || TARGET_AVX512VNNI) && TARGET_EVEX512")
(V16HI "TARGET_AVX2") V8HI])
 
+(define_mode_iterator VI2_AVX10_2
+  [(V32HI "TARGET_AVX10_2_512") V16HI V8HI])
+
 (define_mode_iterator VI4_AVX
   [(V8SI "TARGET_AVX") V4SI])
 
@@ -31232,12 +31239,13 @@
 
 (define_expand "sdot_prod"
   [(match_operand: 0 "register_operand")
-   (match_operand:VI1_AVX2 1 "register_operand")
-   (match_operand:VI1_AVX2 2 "register_operand")
+   (match_operand:VI1_AVX512VNNIBW 1 "register_operand")
+   (match_operand:VI1_AVX512VNNIBW 2 "register_operand")
(match_operand: 3 "register_operand")]
   "TARGET_SSE2"
 {
-  if (TARGET_AVXVNNIINT8)
+  if (( == 64 && TARGET_AVX10_2_512)
+  || ( < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2_256)))
 {
   operands[1] = lowpart_subreg (mode,
force_reg (mode, operands[1]),
@@ -31276,44 +31284,15 @@
   DONE;
 })
 
-(define_expand "sdot_prodv64qi"
-  [(match_operand:V16SI 0 "register_operand")
-   (match_operand:V64QI 1 "register_operand")
-   (match_operand:V64QI 2 "register_operand")
-   (match_operand:V16SI 3 "register_operand")]
-  "(TARGET_AVX512VNNI || TARGET_AVX512BW) && TARGET_EVEX512"
-{
-  /* Emulate with vpdpwssd.  */
-  rtx op1_lo = gen_reg_rtx (V32HImode);
-  rtx op1_hi = gen_reg_rtx (V32HImode);
-  rtx op2_lo = gen_reg_rtx (V32HImode);
-  rtx op2_hi = gen_reg_rtx (V32HImode);
-
-  emit_insn (gen_vec_unpacks_lo_v64qi (op1_lo, operands[1]));
-  emit_insn (gen_vec_unpacks_lo_v64qi (op2_lo, operands[2]));
-  emit_insn (gen_vec_unpacks_hi_v64qi (op1_hi, operands[1]));
-  emit_insn (gen_vec_unpacks_hi_v64qi (op2_hi, operands[2]));
-
-  rtx res1 = gen_reg_rtx (V16SImode);
-  rtx res2 = gen_reg_rtx (V16SImode);
-  rtx sum = gen_reg_rtx (V16SImode);
-
-  emit_move_insn (sum, CONST0_RTX (V16SImode));
-  emit_insn (gen_sdot_prodv32hi (res1, op1_lo, op2_lo, sum));
-  emit_insn (gen_sdot_prodv32hi (res2, op1_hi, op2_hi, operands[3]));
-
-  emit_insn (gen_addv16si3 (operands[0], res1, res2));
-  DONE;
-})
-
 (define_expand "udot_prod"
   [(match_operand: 0 "register_operand")
-   (match_operand:VI1_AVX2 1 "register_operand")
-   (match_operand:VI1_AVX2 2 "register_operand")
+   (match_operand:VI1_AVX512VNNIBW 1 "register_operand")
+   (match_operand:VI1_AVX512VNNIBW 2 "register_operand")
(match_operand: 3 "register_operand")]
   "TARGET_SSE2"
 {
-  if (TARGET_AVXVNNIINT8)
+  if (( == 64 && TARGET_AVX10_2_512)
+  || ( < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2_256)))
 {
   operands[1] = lowpart_subreg (mode,
force_reg (mode, operands[1]),
@@ -31352,36 +31331,6 @@
   DONE;
 })
 
-(define_expand "udot_prodv64qi"
-  [(match_operand:V16SI 0 "register_operand")
-   (match_operand:V64QI 1 "register_operand")
- 

[PATCH 11/12] AVX10.2: Support compare instructions

[Haochen Jiang]

From: "Zhang, Jun" 

gcc/ChangeLog:

* config/i386/i386-expand.cc
(ix86_ssecom_setcc): Mention behavior change on flags.
(ix86_expand_sse_comi): Handle AVX10.2 behavior.
(ix86_expand_sse_comi_round): Ditto.
(ix86_expand_round_builtin): Ditto.
(ix86_expand_builtin): Change function call.
* config/i386/i386.md (UNSPEC_COMX): New unspec.
* config/i386/sse.md
(avx10_2_vcomx): New.
(_comi): Add HFmode.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_2-compare-1.c: New test.

Co-authored-by: Haochen Jiang 
Co-authored-by: Hongtao Liu 
---
 gcc/config/i386/i386-expand.cc| 170 +++---
 gcc/config/i386/i386.md   |   1 +
 gcc/config/i386/sse.md|  18 +-
 .../gcc.target/i386/avx10_2-compare-1.c   |  21 +++
 4 files changed, 183 insertions(+), 27 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-compare-1.c

diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 0322ef003d1..cdeb8b14eb7 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -10664,7 +10664,9 @@ ix86_ssecom_setcc (const enum rtx_code comparison,
   rtx_code_label *label = NULL;
 
   /* NB: For ordered EQ or unordered NE, check ZF alone isn't sufficient
- with NAN operands.  */
+ with NAN operands.
+ Under TARGET_AVX10_2_256, VCOMX/VUCOMX are generated instead of
+ COMI/UCOMI.  VCOMX/VUCOMX will not set ZF for NAN operands.  */
   if (check_unordered)
 {
   gcc_assert (comparison == EQ || comparison == NE);
@@ -10703,7 +10705,7 @@ ix86_ssecom_setcc (const enum rtx_code comparison,
 
 static rtx
 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
- rtx target)
+ rtx target, bool comx_ok)
 {
   rtx pat, set_dst;
   tree arg0 = CALL_EXPR_ARG (exp, 0);
@@ -10736,11 +10738,13 @@ ix86_expand_sse_comi (const struct 
builtin_description *d, tree exp,
 case GE:
   break;
 case EQ:
-  check_unordered = true;
+  if (!TARGET_AVX10_2_256 || !comx_ok)
+   check_unordered = true;
   mode = CCZmode;
   break;
 case NE:
-  check_unordered = true;
+  if (!TARGET_AVX10_2_256 || !comx_ok)
+   check_unordered = true;
   mode = CCZmode;
   const_val = const1_rtx;
   break;
@@ -10759,6 +10763,28 @@ ix86_expand_sse_comi (const struct builtin_description 
*d, tree exp,
   || !insn_p->operand[1].predicate (op1, mode1))
 op1 = copy_to_mode_reg (mode1, op1);
 
+  if ((comparison == EQ || comparison == NE)
+  && TARGET_AVX10_2_256 && comx_ok)
+{
+  switch (icode)
+   {
+   case CODE_FOR_sse_comi:
+ icode = CODE_FOR_avx10_2_comxsf;
+ break;
+   case CODE_FOR_sse_ucomi:
+ icode = CODE_FOR_avx10_2_ucomxsf;
+ break;
+   case CODE_FOR_sse2_comi:
+ icode = CODE_FOR_avx10_2_comxdf;
+ break;
+   case CODE_FOR_sse2_ucomi:
+ icode = CODE_FOR_avx10_2_ucomxdf;
+ break;
+
+   default:
+ gcc_unreachable ();
+   }
+}
   pat = GEN_FCN (icode) (op0, op1);
   if (! pat)
 return 0;
@@ -12253,7 +12279,7 @@ ix86_erase_embedded_rounding (rtx pat)
with rounding.  */
 static rtx
 ix86_expand_sse_comi_round (const struct builtin_description *d,
-   tree exp, rtx target)
+   tree exp, rtx target, bool comx_ok)
 {
   rtx pat, set_dst;
   tree arg0 = CALL_EXPR_ARG (exp, 0);
@@ -12315,6 +12341,7 @@ ix86_expand_sse_comi_round (const struct 
builtin_description *d,
 op1 = safe_vector_operand (op1, mode1);
 
   enum rtx_code comparison = comparisons[INTVAL (op2)];
+  enum rtx_code orig_comp = comparison;
   bool ordered = ordereds[INTVAL (op2)];
   bool non_signaling = non_signalings[INTVAL (op2)];
   rtx const_val = const0_rtx;
@@ -12326,10 +12353,21 @@ ix86_expand_sse_comi_round (const struct 
builtin_description *d,
 case ORDERED:
   if (!ordered)
{
- /* NB: Use CCSmode/NE for _CMP_TRUE_UQ/_CMP_TRUE_US.  */
- if (!non_signaling)
-   ordered = true;
- mode = CCSmode;
+ if (TARGET_AVX10_2_256 && comx_ok)
+   {
+ /* Unlike VCOMI{SH,SS,SD}, VCOMX{SH,SS,SD} will set SF
+differently. So directly return true here.  */
+ target = gen_reg_rtx (SImode);
+ emit_move_insn (target, const1_rtx);
+ return target;
+   }
+ else
+   {
+ /* NB: Use CCSmode/NE for _CMP_TRUE_UQ/_CMP_TRUE_US.  */
+ if (!non_signaling)
+   ordered = true;
+ mode = CCSmode;
+   }
}
   else
{
@@ -12343,10 +12381,21 @@ ix86_expand_sse_comi_round (const struct 
builtin_description *d,
 case UNORDERED:
   if (ordered)
   

[PATCH 12/12] i386: Add bf8 -> fp16 intrin

[Haochen Jiang]

Since BF8 and FP16 have same bits for exponent, the type conversion
between them is just a cast for fraction part. We will use a sequence
of instrctions instead of new instructions to do that. For convenience,
intrins are also provided.

gcc/ChangeLog:

* config/i386/avx10_2-512convertintrin.h
(_mm512_cvtpbf8_ph): New.
(_mm512_mask_cvtpbf8_ph): Ditto.
(_mm512_maskz_cvtpbf8_ph): Ditto.
* config/i386/avx10_2convertintrin.h
(_mm_cvtpbf8_ph): Ditto.
(_mm_mask_cvtpbf8_ph): Ditto.
(_mm_maskz_cvtpbf8_ph): Ditto.
(_mm256_cvtpbf8_ph): Ditto.
(_mm256_mask_cvtpbf8_ph): Ditto.
(_mm256_maskz_cvtpbf8_ph): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_2-512-convert-1.c: Add tests for new
intrin.
* gcc.target/i386/avx10_2-convert-1.c: Ditto.
---
 gcc/config/i386/avx10_2-512convertintrin.h| 24 ++
 gcc/config/i386/avx10_2convertintrin.h| 48 +++
 .../gcc.target/i386/avx10_2-512-convert-1.c   | 16 ++-
 .../gcc.target/i386/avx10_2-convert-1.c   | 26 --
 4 files changed, 109 insertions(+), 5 deletions(-)

diff --git a/gcc/config/i386/avx10_2-512convertintrin.h 
b/gcc/config/i386/avx10_2-512convertintrin.h
index 4ad339bbbf9..dfbdfc3e51b 100644
--- a/gcc/config/i386/avx10_2-512convertintrin.h
+++ b/gcc/config/i386/avx10_2-512convertintrin.h
@@ -540,6 +540,30 @@ _mm512_maskz_cvtnesph_phf8 (__mmask32 __U, __m512h __A)
 (__mmask32) __U);
 }
 
+extern __inline __m512h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtpbf8_ph (__m256i __A)
+{
+  return (__m512h) _mm512_castsi512_ph ((__m512i) _mm512_slli_epi16 (
+(__m512i) _mm512_cvtepi8_epi16 (__A), 8));
+}
+
+extern __inline __m512h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvtpbf8_ph (__m512h __S, __mmask16 __U, __m256i __A)
+{
+  return (__m512h) _mm512_castsi512_ph ((__m512i) _mm512_mask_slli_epi16 (
+(__m512i) __S, __U, (__m512i) _mm512_cvtepi8_epi16 (__A), 8));
+}
+
+extern __inline __m512h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvtpbf8_ph (__mmask16 __U, __m256i __A)
+{
+  return (__m512h) _mm512_castsi512_ph ((__m512i) _mm512_slli_epi16 (
+(__m512i) _mm512_maskz_cvtepi8_epi16 (__U, __A), 8));
+}
+
 #ifdef __DISABLE_AVX10_2_512__
 #undef __DISABLE_AVX10_2_512__
 #pragma GCC pop_options
diff --git a/gcc/config/i386/avx10_2convertintrin.h 
b/gcc/config/i386/avx10_2convertintrin.h
index ac62d1290a5..8d2c1a54147 100644
--- a/gcc/config/i386/avx10_2convertintrin.h
+++ b/gcc/config/i386/avx10_2convertintrin.h
@@ -970,6 +970,54 @@ _mm256_maskz_cvtnesph_phf8 (__mmask16 __U, __m256h __A)
 (__mmask16) __U);
 }
 
+extern __inline __m128h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtpbf8_ph (__m128i __A)
+{
+  return (__m128h) _mm_castsi128_ph ((__m128i) _mm_slli_epi16 (
+(__m128i) _mm_cvtepi8_epi16 (__A), 8));
+}
+
+extern __inline __m128h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvtpbf8_ph (__m128h __S, __mmask8 __U, __m128i __A)
+{
+  return (__m128h) _mm_castsi128_ph ((__m128i) _mm_mask_slli_epi16 (
+(__m128i) __S, __U, (__m128i) _mm_cvtepi8_epi16 (__A), 8));
+}
+
+extern __inline __m128h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvtpbf8_ph (__mmask8 __U, __m128i __A)
+{
+  return (__m128h) _mm_castsi128_ph ((__m128i) _mm_slli_epi16 (
+(__m128i) _mm_maskz_cvtepi8_epi16 (__U, __A), 8));
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtpbf8_ph (__m128i __A)
+{
+  return (__m256h) _mm256_castsi256_ph ((__m256i) _mm256_slli_epi16 (
+(__m256i) _mm256_cvtepi8_epi16 (__A), 8));
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtpbf8_ph (__m256h __S, __mmask8 __U, __m128i __A)
+{
+  return (__m256h) _mm256_castsi256_ph ((__m256i) _mm256_mask_slli_epi16 (
+(__m256i) __S, __U, (__m256i) _mm256_cvtepi8_epi16 (__A), 8));
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtpbf8_ph (__mmask8 __U, __m128i __A)
+{
+  return (__m256h) _mm256_castsi256_ph ((__m256i) _mm256_slli_epi16 (
+(__m256i) _mm256_maskz_cvtepi8_epi16 (__U, __A), 8));
+}
+
 #ifdef __DISABLE_AVX10_2_256__
 #undef __DISABLE_AVX10_2_256__
 #pragma GCC pop_options
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c 
b/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c
index bbbff186d0a..f67138c237c 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-512-convert-1.c
@@ -45,13 +45,17 @@
 /* { dg-final { s

[PATCH 10/12] AVX10.2: Support vector copy instructions

[Haochen Jiang]

From: "Zhang, Jun" 

gcc/ChangeLog:

* config/config.gcc: Add avx10_2copyintrin.h.
* config/i386/i386.md (avx10_2): New isa attribute.
* config/i386/immintrin.h: Include avx10_2copyintrin.h.
* config/i386/sse.md
(sse_movss_): Add new constraints to handle AVX10.2.
(vec_set_0): Ditto.
(@vec_set_0): Ditto.
(vec_set_0): Ditto.
(avx512fp16_mov): Ditto.
(*vec_set_0_1): New split.
* config/i386/avx10_2copyintrin.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_2-vmovd-1.c: New test.
* gcc.target/i386/avx10_2-vmovd-2.c: Ditto.
* gcc.target/i386/avx10_2-vmovw-1.c: Ditto.
* gcc.target/i386/avx10_2-vmovw-2.c: Ditto.
---
 gcc/config.gcc|   3 +-
 gcc/config/i386/avx10_2copyintrin.h   |  38 +
 gcc/config/i386/i386.md   |   3 +-
 gcc/config/i386/immintrin.h   |   2 +
 gcc/config/i386/sse.md| 138 +++---
 .../gcc.target/i386/avx10_2-vmovd-1.c |  48 ++
 .../gcc.target/i386/avx10_2-vmovd-2.c |  44 ++
 .../gcc.target/i386/avx10_2-vmovw-1.c |  69 +
 .../gcc.target/i386/avx10_2-vmovw-2.c |  64 
 9 files changed, 356 insertions(+), 53 deletions(-)
 create mode 100644 gcc/config/i386/avx10_2copyintrin.h
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vmovd-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vmovd-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vmovw-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vmovw-2.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index cd8a34b292f..e887c9c7432 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -457,7 +457,8 @@ i[34567]86-*-* | x86_64-*-*)
   avx10_2convertintrin.h avx10_2-512convertintrin.h
   avx10_2bf16intrin.h avx10_2-512bf16intrin.h
   avx10_2satcvtintrin.h avx10_2-512satcvtintrin.h
-  avx10_2minmaxintrin.h avx10_2-512minmaxintrin.h"
+  avx10_2minmaxintrin.h avx10_2-512minmaxintrin.h
+  avx10_2copyintrin.h"
;;
 ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/avx10_2copyintrin.h 
b/gcc/config/i386/avx10_2copyintrin.h
new file mode 100644
index 000..f1150c71dbf
--- /dev/null
+++ b/gcc/config/i386/avx10_2copyintrin.h
@@ -0,0 +1,38 @@
+/* Copyright (C) 2024 Free Software Foundation, Inc.
+   This file is part of GCC.
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+#error "Never use  directly; include  
instead."
+#endif
+
+#ifndef _AVX10_2COPYINTRIN_H_INCLUDED
+#define _AVX10_2COPYINTRIN_H_INCLUDED
+
+extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
+_mm_move_epi32 (__m128i __A)
+{
+  return _mm_set_epi32 (0, 0, 0, ((__v4si) __A)[0]);
+}
+
+extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
+_mm_move_epi16 (__m128i __A)
+{
+  return _mm_set_epi16 (0, 0, 0, 0, 0, 0, 0, ((__v8hi) __A)[0]);
+}
+
+#endif /* _AVX10_2COPYINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 470ae5444db..e28f9bb5eae 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -582,7 +582,7 @@
noavx512dq,fma_or_avx512vl,avx512vl,noavx512vl,avxvnni,
avx512vnnivl,avx512fp16,avxifma,avx512ifmavl,avxneconvert,
avx512bf16vl,vpclmulqdqvl,avx_noavx512f,avx_noavx512vl,
-   vaes_avx512vl,noapx_nf,apx_cfcmov"
+   vaes_avx512vl,noapx_nf,apx_cfcmov,avx10_2"
   (const_string "base"))
 
 ;; The (bounding maximum) length of an instruction immediate.
@@ -979,6 +979,7 @@
   (symbol_ref "TARGET_APX_NDD && Pmode == DImode")
 (eq_attr "isa" "vaes_avx512vl")
   (symbol_ref "TARGET_VAES && TARGET_AVX512VL")
+(eq_attr "isa" "avx10_2") (symbol_ref "TARGET_AVX10_2_256

[PATCH 09/12] AVX10.2: Support minmax instructions

[Haochen Jiang]

From: "Mo, Zewei" 

gcc/ChangeLog:

* config.gcc: Add avx10_2-512minmaxintrin.h and
avx10_2minmaxintrin.h.
* config/i386/i386-builtin-types.def:
Add DEF_FUNCTION_TYPE (V8BF, V8BF, V8BF, INT, V8BF, UQI),
(V16BF, V16BF, V16BF, INT, V16BF, UHI),
(V32BF, V32BF, V32BF, INT, V32BF, USI),
(V8HF, V8HF, V8HF, INT, V8HF, UQI),
(V8DF, V8DF, V8DF, INT, V8DF, UQI, INT),
(V32HF, V32HF, V32HF, INT, V32HF, USI, INT),
(V16HF, V16HF, V16HF, INT, V16HF, UHI, INT),
(V16SF, V16SF, V16SF, INT, V16SF, UHI, INT).
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc
(ix86_expand_args_builtin): Handle V8BF_FTYPE_V8BF_V8BF_INT_V8BF_UQI,
V16BF_FTYPE_V16BF_V16BF_INT_V16BF_UHI,
V32BF_FTYPE_V32BF_V32BF_INT_V32BF_USI,
V8HF_FTYPE_V8HF_V8HF_INT_V8HF_UQI,
(ix86_expand_round_builtin): Handle 
V8DF_FTYPE_V8DF_V8DF_INT_V8DF_UQI_INT,
V32HF_FTYPE_V32HF_V32HF_INT_V32HF_USI_INT,
V16HF_FTYPE_V16HF_V16HF_INT_V16HF_UHI_INT.
V16SF_FTYPE_V16SF_V16SF_INT_V16SF_UHI_INT.
* config/i386/immtrin.h: Include avx10_2-512miscsintrin.h and
avx10_2miscsintrin.h.
* config/i386/sse.md (avx10_2_vminmaxnepbf16_): New.
(avx10_2_minmaxp): Ditto.
(avx10_2_minmaxs): 
Ditto.
* config/i386/avx10_2-512minmaxintrin.h: New file.
* config/i386/avx10_2minmaxintrin.h: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add macros.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10-minmax-helper.h: New helper file.
* gcc.target/i386/avx10_2-512-minmax-1.c: New test.
* gcc.target/i386/avx10_2-512-vminmaxnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vminmaxpd-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vminmaxph-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vminmaxps-2.c: Ditto.
* gcc.target/i386/avx10_2-mixmax-1.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxsd-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxsh-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxss-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxpd-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxph-2.c: Ditto.
* gcc.target/i386/avx10_2-vminmaxps-2.c: Ditto.

Co-authored-by: Lin Hu 
Co-authored-by: Haochen Jiang 
---
 gcc/config.gcc|3 +-
 gcc/config/i386/avx10_2-512minmaxintrin.h |  489 
 gcc/config/i386/avx10_2minmaxintrin.h | 1063 +
 gcc/config/i386/i386-builtin-types.def|8 +
 gcc/config/i386/i386-builtin.def  |   16 +-
 gcc/config/i386/i386-expand.cc|8 +
 gcc/config/i386/immintrin.h   |5 +
 gcc/config/i386/sse.md|   46 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   19 +
 .../gcc.target/i386/avx10-minmax-helper.h |  257 
 .../gcc.target/i386/avx10_2-512-minmax-1.c|   51 +
 .../i386/avx10_2-512-vminmaxnepbf16-2.c   |   35 +
 .../gcc.target/i386/avx10_2-512-vminmaxpd-2.c |   35 +
 .../gcc.target/i386/avx10_2-512-vminmaxph-2.c |   35 +
 .../gcc.target/i386/avx10_2-512-vminmaxps-2.c |   35 +
 .../gcc.target/i386/avx10_2-minmax-1.c|  122 ++
 .../i386/avx10_2-vminmaxnepbf16-2.c   |   13 +
 .../gcc.target/i386/avx10_2-vminmaxpd-2.c |   13 +
 .../gcc.target/i386/avx10_2-vminmaxph-2.c |   15 +
 .../gcc.target/i386/avx10_2-vminmaxps-2.c |   13 +
 .../gcc.target/i386/avx10_2-vminmaxsd-2.c |   34 +
 .../gcc.target/i386/avx10_2-vminmaxsh-2.c |   34 +
 .../gcc.target/i386/avx10_2-vminmaxss-2.c |   34 +
 .../gcc.target/i386/avx512f-helper.h  |2 +
 gcc/testsuite/gcc.target/i386/sse-13.c|   19 +
 gcc/testsuite/gcc.target/i386/sse-14.c|   67 ++
 gcc/testsuite/gcc.target/i386/sse-22.c|   67 ++
 gcc/testsuite/gcc.target/i386/sse-23.c|   19 +
 28 files changed, 2555 insertions(+), 2 deletions(-)
 create mode 100644 gcc/config/i386/avx10_2-512minmaxintrin.h
 create mode 100644 gcc/config/i386/avx10_2minmaxintrin.h
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10-minmax-helper.h
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-minmax-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxnepbf16-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxpd-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxph-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vminmaxps-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-minmax-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vminmaxnepbf16-2.c
 create m

[PATCH 06/12] [PATCH 2/2] AVX10.2: Support BF16 instructions

[Haochen Jiang]

From: konglin1 

gcc/ChangeLog:

* config/i386/avx10_2-512bf16intrin.h: Add new intrinsics.
* config/i386/avx10_2bf16intrin.h: Diito.
* config/i386/i386-builtin-types.def : Add new DEF_FUNCTION_TYPE
for new type.
* config/i386/i386-builtin.def (BDESC): Add new buildin.
* config/i386/i386-expand.cc (ix86_expand_args_builtin):
Handle new type.
* config/i386/sse.md (avx10_2_rsqrtpbf16_):
New define_insn.
(avx10_2_sqrtnepbf16_): Ditto.
(avx10_2_rcppbf16_): Ditto.
(avx10_2_getexppbf16_): Ditto.
(BF16IMMOP): New iterator.
(bf16immop): Ditto.
(avx10_2_pbf16_): New define_insn.
(avx10_2_fpclasspbf16_): Ditto.
(avx10_2_cmppbf16_): Ditto.
(avx10_2_comsbf16_v8bf): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10-helper.h: Add helper functions.
* gcc.target/i386/avx10_2-512-bf16-1.c: Add new tests.
* gcc.target/i386/avx10_2-bf16-1.c: Ditto.
* gcc.target/i386/avx-1.c: Add macros.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-512-vcmppbf16-2.c: New test.
* gcc.target/i386/avx10_2-512-vfpclasspbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vgetexppbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vgetmantpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vrcppbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vreducenepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vrndscalenepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vrsqrtpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vsqrtnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vcmppbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vcomsbf16-1.c: Ditto.
* gcc.target/i386/avx10_2-vcomsbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vfpclasspbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vgetexppbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vgetmantpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vrcppbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vreducenepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vrndscalenepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vrsqrtpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vsqrtnepbf16-2.c: Ditto.

Co-authored-by: Levy Hsu 
---
 gcc/config/i386/avx10_2-512bf16intrin.h   | 317 +
 gcc/config/i386/avx10_2bf16intrin.h   | 650 ++
 gcc/config/i386/i386-builtin-types.def|  10 +
 gcc/config/i386/i386-builtin.def  |  33 +
 gcc/config/i386/i386-expand.cc|  16 +
 gcc/config/i386/sse.md|  92 +++
 gcc/testsuite/gcc.target/i386/avx-1.c |  19 +
 gcc/testsuite/gcc.target/i386/avx10-check.h   |   4 +-
 gcc/testsuite/gcc.target/i386/avx10-helper.h  |  28 +
 .../gcc.target/i386/avx10_2-512-bf16-1.c  |  58 ++
 .../gcc.target/i386/avx10_2-512-vcmppbf16-2.c |  36 +
 .../i386/avx10_2-512-vfpclasspbf16-2.c|  44 ++
 .../i386/avx10_2-512-vgetexppbf16-2.c |  47 ++
 .../i386/avx10_2-512-vgetmantpbf16-2.c|  50 ++
 .../gcc.target/i386/avx10_2-512-vrcppbf16-2.c |  45 ++
 .../i386/avx10_2-512-vreducenepbf16-2.c   |  50 ++
 .../i386/avx10_2-512-vrndscalenepbf16-2.c |  46 ++
 .../i386/avx10_2-512-vrsqrtpbf16-2.c  |  47 ++
 .../i386/avx10_2-512-vscalefpbf16-2.c |   2 +-
 .../i386/avx10_2-512-vsqrtnepbf16-2.c |  47 ++
 .../gcc.target/i386/avx10_2-bf16-1.c  | 114 +++
 .../gcc.target/i386/avx10_2-vcmppbf16-2.c |  16 +
 .../gcc.target/i386/avx10_2-vcomsbf16-1.c |  19 +
 .../gcc.target/i386/avx10_2-vcomsbf16-2.c |  58 ++
 .../gcc.target/i386/avx10_2-vfpclasspbf16-2.c |  16 +
 .../gcc.target/i386/avx10_2-vgetexppbf16-2.c  |  16 +
 .../gcc.target/i386/avx10_2-vgetmantpbf16-2.c |  16 +
 .../gcc.target/i386/avx10_2-vrcppbf16-2.c |  16 +
 .../i386/avx10_2-vreducenepbf16-2.c   |  16 +
 .../i386/avx10_2-vrndscalenepbf16-2.c |  16 +
 .../gcc.target/i386/avx10_2-vrsqrtpbf16-2.c   |  16 +
 .../gcc.target/i386/avx10_2-vsqrtnepbf16-2.c  |  16 +
 gcc/testsuite/gcc.target/i386/sse-13.c|  19 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  43 ++
 gcc/testsuite/gcc.target/i386/sse-22.c|  43 ++
 gcc/testsuite/gcc.target/i386/sse-23.c|  19 +
 36 files changed, 2097 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vcmppbf16-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vfpclasspbf16-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vgetexppbf16-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vgetmantpbf16-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vrcppbf16-2.c
 create mode 100644 gcc/testsuite/gcc.target/i38

[PATCH 05/12] [PATCH 1/2] AVX10.2: Support BF16 instructions

[Haochen Jiang]

From: konglin1 

gcc/ChangeLog:

* config.gcc: Add avx10_2-512bf16intrin.h and avx10_2bf16intrin.h.
* config/i386/i386-builtin-types.def : Add new
DEF_FUNCTION_TYPE for V32BF_FTYPE_V32BF_V32BF,
V16BF_FTYPE_V16BF_V16BF, V8BF_FTYPE_V8BF_V8BF,
V8BF_FTYPE_V8BF_V8BF_UQI, V16BF_FTYPE_V16BF_V16BF_UHI,
V32BF_FTYPE_V32BF_V32BF_USI, V32BF_FTYPE_V32BF_V32BF_V32BF_USI,
V8BF_FTYPE_V8BF_V8BF_V8BF_UQI and V16BF_FTYPE_V16BF_V16BF_V16BF_UHI.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_args_builtin):
Handle new DEF_FUNCTION_TYPE.
* config/i386/immintrin.h: Include avx10_2-512bf16intrin.h and
avx10_2bf16intrin.h.
* config/i386/sse.md
(avx10_2_scalefpbf16_): New define_insn.
(avx10_2_nepbf16_): Ditto.
(avx10_2_nepbf16_): Ditto.
(avx10_2_pbf16__maskz): Ditto.
(avx10_2_pbf16_): Ditto.
(avx10_2_pbf16__mask3): Ditto.
* config/i386/avx10_2-512bf16intrin.h: New file.
* config/i386/avx10_2bf16intrin.h: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512f-helper.h: Add MAKE_MASK_MERGE and 
MAKE_MASK_ZERO
for bf16_uw.
* gcc.target/i386/m512-check.h: Add union512bf16_uw, union256bf16_uw,
union128bf16_uw and CHECK_EXP for them.
* gcc.target/i386/avx10-helper.h: New file.
* gcc.target/i386/avx10_2-512-bf16ne-1.c: New test.
* gcc.target/i386/avx10_2-512-vaddnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vdivnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vfmaddXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vfmsubXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vfnmaddXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vfnmsubXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vmaxpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vminpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vscalefpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vsubnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-bf16ne-1.c: Ditto.
* gcc.target/i386/avx10_2-vaddnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vdivnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vfmaddXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vfmsubXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vfnmaddXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vfnmsubXXXnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vmaxpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vminpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vmulnepbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vscalefpbf16-2.c: Ditto.
* gcc.target/i386/avx10_2-vsubnepbf16-2.c: Ditto.

Co-authored-by: Levy Hsu 
---
 gcc/config.gcc|   2 +-
 gcc/config/i386/avx10_2-512bf16intrin.h   | 364 ++
 gcc/config/i386/avx10_2bf16intrin.h   | 685 ++
 gcc/config/i386/i386-builtin-types.def|   9 +
 gcc/config/i386/i386-builtin.def  |  78 ++
 gcc/config/i386/i386-expand.cc|   9 +
 gcc/config/i386/immintrin.h   |   4 +
 gcc/config/i386/sse.md| 293 
 gcc/testsuite/gcc.target/i386/avx10-helper.h  |  48 +-
 .../gcc.target/i386/avx10_2-512-bf16-1.c  |  87 +++
 .../i386/avx10_2-512-vaddnepbf16-2.c  |  49 ++
 .../i386/avx10_2-512-vdivnepbf16-2.c  |  49 ++
 .../i386/avx10_2-512-vfmaddXXXnepbf16-2.c |  52 ++
 .../i386/avx10_2-512-vfmsubXXXnepbf16-2.c |  53 ++
 .../i386/avx10_2-512-vfnmaddXXXnepbf16-2.c|  53 ++
 .../i386/avx10_2-512-vfnmsubXXXnepbf16-2.c|  53 ++
 .../gcc.target/i386/avx10_2-512-vmaxpbf16-2.c |  51 ++
 .../gcc.target/i386/avx10_2-512-vminpbf16-2.c |  51 ++
 .../i386/avx10_2-512-vmulnepbf16-2.c  |  49 ++
 .../i386/avx10_2-512-vscalefpbf16-2.c |  51 ++
 .../i386/avx10_2-512-vsubnepbf16-2.c  |  49 ++
 .../gcc.target/i386/avx10_2-bf16-1.c  | 172 +
 .../gcc.target/i386/avx10_2-vaddnepbf16-2.c   |  16 +
 .../gcc.target/i386/avx10_2-vdivnepbf16-2.c   |  16 +
 .../i386/avx10_2-vfmaddXXXnepbf16-2.c |  16 +
 .../i386/avx10_2-vfmsubXXXnepbf16-2.c |  16 +
 .../i386/avx10_2-vfnmaddXXXnepbf16-2.c|  16 +
 .../i386/avx10_2-vfnmsubXXXnepbf16-2.c|  16 +
 .../gcc.target/i386/avx10_2-vmaxpbf16-2.c |  16 +
 .../gcc.target/i386/avx10_2-vminpbf16-2.c |  16 +
 .../gcc.target/i386/avx10_2-vmulnepbf16-2.c   |  16 +
 .../gcc.target/i386/avx10_2-vscalefpbf16-2.c  |  16 +
 .../gcc.target/i386/avx10_2-vsubnepbf16-2.c   |  16 +
 .../gcc.target/i386/avx512f-helper.h  |   2 +
 gcc/testsuite/gcc.target/i386/m512-check.h|  27 +
 35 files changed, 2514 insertions(+), 2 deletions(-)
 create mode 100644 gcc/config/i386/avx10_2-512bf16intrin.h
 create mode 100644 gcc/config/i386/a

[PATCH 07/12] [PATCH 1/2] AVX10.2: Support saturating convert instructions

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config.gcc: Add avx10_2satcvtintrin.h and
avx10_2-512satcvtintrin.h.
* config/i386/i386-builtin-types.def:
Add DEF_FUNCTION_TYPE (V8HI, V8BF, V8HI, UQI),
(V16HI, V16BF, V16HI, UHI), (V32HI, V32BF, V32HI, USI),
(V16SI, V16SF, V16SI, UHI, INT), (V16HI, V16BF, V16HI, UHI, INT),
(V32HI, V32BF, V32HI, USI, INT).
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle
V32HI_FTYPE_V32BF_V32HI_USI, V16HI_FTYPE_V16BF_V16HI_UHI,
V8HI_FTYPE_V8BF_V8HI_UQI.
(ix86_expand_round_builtin): Handle V32HI_FTYPE_V32BF_V32HI_USI_INT,
V16SI_FTYPE_V16SF_V16SI_UHI_INT, V16HI_FTYPE_V16BF_V16HI_UHI_INT.
* config/i386/immintrin.h: Include avx10_2satcvtintrin.h and
avx10_2-512savcvtintrin.h.
* config/i386/sse.md:

(avx10_2_cvtnebf162ibs):
New.

(avx10_2_cvtph2ibs):
Ditto.

(avx10_2_cvttph2ibs):
Ditto.

(avx10_2_cvtps2ibs):
Ditto.

(avx10_2_cvttps2ibs):
Ditto.
* config/i386/avx10_2-512satcvtintrin.h: New file.
* config/i386/avx10_2satcvtintrin.h: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add macros.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-512-satcvt-1.c: New test.
* gcc.target/i386/avx10_2-512-vcvtnebf162ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtnebf162iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtph2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtph2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtps2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtps2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttnebf162ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttnebf162iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttph2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttph2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttps2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvttps2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-1.c: Ditto.
* gcc.target/i386/avx10_2-vcvtnebf162ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtnebf162iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtph2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtph2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvtps2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttnebf162ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttnebf162iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttph2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttph2iubs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttps2ibs-2.c: Ditto.
* gcc.target/i386/avx10_2-vcvttps2iubs-2.c: Ditto.
---
 gcc/config.gcc|4 +-
 gcc/config/i386/avx10_2-512satcvtintrin.h |  624 ++
 gcc/config/i386/avx10_2satcvtintrin.h | 1022 +
 gcc/config/i386/i386-builtin-types.def|6 +
 gcc/config/i386/i386-builtin.def  |   36 +
 gcc/config/i386/i386-expand.cc|6 +
 gcc/config/i386/immintrin.h   |3 +
 gcc/config/i386/sse.md|  110 ++
 gcc/testsuite/gcc.target/i386/avx-1.c |   20 +
 .../gcc.target/i386/avx10_2-512-satcvt-1.c|  100 ++
 .../i386/avx10_2-512-vcvtnebf162ibs-2.c   |   69 ++
 .../i386/avx10_2-512-vcvtnebf162iubs-2.c  |   69 ++
 .../i386/avx10_2-512-vcvtph2ibs-2.c   |   74 ++
 .../i386/avx10_2-512-vcvtph2iubs-2.c  |   74 ++
 .../i386/avx10_2-512-vcvtps2ibs-2.c   |   75 ++
 .../i386/avx10_2-512-vcvtps2iubs-2.c  |   73 ++
 .../i386/avx10_2-512-vcvttnebf162ibs-2.c  |   69 ++
 .../i386/avx10_2-512-vcvttnebf162iubs-2.c |   69 ++
 .../i386/avx10_2-512-vcvttph2ibs-2.c  |   74 ++
 .../i386/avx10_2-512-vcvttph2iubs-2.c |   74 ++
 .../i386/avx10_2-512-vcvttps2ibs-2.c  |   75 ++
 .../i386/avx10_2-512-vcvttps2iubs-2.c |   73 ++
 .../gcc.target/i386/avx10_2-satcvt-1.c|  187 +++
 .../i386/avx10_2-vcvtnebf162ibs-2.c   |   16 +
 .../i386/avx10_2-vcvtnebf162iubs-2.c  |   16 +
 .../gcc.target/i386/avx10_2-vcvtph2ibs-2.c|   16 +
 .../gcc.target/i386/avx10_2-vcvtph2iubs-2.c   |   16 +
 .../gcc.target/i386/avx10_2-vcvtps2ibs-2.c|   16 +
 .../i386/avx10_2-vcvttnebf162ibs-2.c  |   16 +
 .../i386/avx10_2-vcvttnebf162iubs-2.c |   16 +
 .../gcc.target/i386/avx10_2-vcvttph2ibs-2.c   |   16 +
 .../gcc.target/i386/avx10_2-vcvttph2iubs-2.c  |   16 +
 .../gcc.target/i386/avx10_2-vcvttps2ibs-2.c   |   16 +
 .../gcc.target/i386/avx10_2-vcvttps2iubs-2.c  |   16 +
 .../gcc.ta

[PATCH 08/12] [PATCH 2/2] AVX10.2: Support saturating convert instructions

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md 
(avx10_2_vcvttpd2dqs):
New.

(avx10_2_vcvttpd2qqs):
Ditto.

(avx10_2_vcvttps2dqs):
Ditto.

(avx10_2_vcvttps2qqs):
Ditto.
(avx10_2_vcvttsd2sis):
Ditto.
(avx10_2_vcvttss2sis):
Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add macros.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-1.c: New test.
* gcc.target/i386/avx10_2-satcvt-512-1.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-512-vcvttpd2dqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-512-vcvttpd2qqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-512-vcvttpd2udqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-512-vcvttpd2uqqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-512-vcvttps2dqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-512-vcvttps2qqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-512-vcvttps2udqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-512-vcvttps2uqqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttpd2dqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttpd2qqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttpd2udqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttpd2uqqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttps2dqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttps2qqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttps2udqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttps2uqqs-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttsd2sis-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttsd2usis-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttss2sis-2.c: Ditto.
* gcc.target/i386/avx10_2-satcvt-vcvttss2usis-2.c: Ditto.
---
 gcc/config/i386/avx10_2-512satcvtintrin.h |  456 +++
 gcc/config/i386/avx10_2satcvtintrin.h | 1055 -
 gcc/config/i386/i386-builtin.def  |   33 +
 gcc/config/i386/sse.md|   83 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |   26 +
 .../gcc.target/i386/avx10_2-512-satcvt-1.c|   59 +
 .../i386/avx10_2-512-vcvttpd2dqs-2.c  |   72 ++
 .../i386/avx10_2-512-vcvttpd2qqs-2.c  |   72 ++
 .../i386/avx10_2-512-vcvttpd2udqs-2.c |   72 ++
 .../i386/avx10_2-512-vcvttpd2uqqs-2.c |   72 ++
 .../i386/avx10_2-512-vcvttps2dqs-2.c  |   72 ++
 .../i386/avx10_2-512-vcvttps2qqs-2.c  |   73 ++
 .../i386/avx10_2-512-vcvttps2udqs-2.c |   72 ++
 .../i386/avx10_2-512-vcvttps2uqqs-2.c |   72 ++
 .../gcc.target/i386/avx10_2-satcvt-1.c|  138 +++
 .../gcc.target/i386/avx10_2-vcvttpd2dqs-2.c   |   16 +
 .../gcc.target/i386/avx10_2-vcvttpd2qqs-2.c   |   16 +
 .../gcc.target/i386/avx10_2-vcvttpd2udqs-2.c  |   16 +
 .../gcc.target/i386/avx10_2-vcvttpd2uqqs-2.c  |   16 +
 .../gcc.target/i386/avx10_2-vcvttps2dqs-2.c   |   16 +
 .../gcc.target/i386/avx10_2-vcvttps2qqs-2.c   |   16 +
 .../gcc.target/i386/avx10_2-vcvttps2udqs-2.c  |   16 +
 .../gcc.target/i386/avx10_2-vcvttps2uqqs-2.c  |   16 +
 .../gcc.target/i386/avx10_2-vcvttsd2sis-2.c   |   47 +
 .../gcc.target/i386/avx10_2-vcvttsd2usis-2.c  |   47 +
 .../gcc.target/i386/avx10_2-vcvttss2sis-2.c   |   47 +
 .../gcc.target/i386/avx10_2-vcvttss2usis-2.c  |   46 +
 gcc/testsuite/gcc.target/i386/sse-13.c|   26 +
 gcc/testsuite/gcc.target/i386/sse-14.c|   58 +
 gcc/testsuite/gcc.target/i386/sse-22.c|   58 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   26 +
 31 files changed, 2870 insertions(+), 40 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2dqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2qqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2udqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttpd2uqqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2dqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2qqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2udqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vcvttps2uqqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2dqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2qqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2udqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vcvttpd2uqqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2dqs-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vcvttps2qqs-

[PATCH 02/12] [PATCH 1/2] AVX10.2: Support media instructions

[Haochen Jiang]

From: Hongyu Wang 

gcc/ChangeLog

* config.gcc: Add avx10_2mediaintrin.h and
avx10_2-512mediaintrin.h.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/i386-builtins.cc (def_builtin): Handle shared
builtins between AVXVNNIINT8 and AVX10.2.
* config/i386/i386-expand.cc (ix86_check_builtin_isa_match):
Ditto.
* config/i386/immintrin.h: Include avx10_2mediaintrin.h and
avx10_2-512mediaintrin.h
* config/i386/sse.md: (VI4_AVX10_2): New.
(vpdp_): Add AVX10_2_256.
(vpdp_v16si): New define_insn.
(vpdp__mask): Ditto.
(*vpdp__maskz): Ditto.
(vpdp__maskz): New expander.
* config/i386/avx10_2_512mediaintrin.h: New file.
* config/i386/avx10_2mediaintrin.h: Ditto.

gcc/testsuite/ChangeLog

* g++.dg/other/i386-2.C: Add -mavx10.2-512.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/avx512f-helper.h: Reuse AVX512F macros
for AVX10.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* lib/target-supports.exp
(check_effective_target_avx10_2): New.
(check_effective_target_avx10_2_512): Ditto.
* gcc.target/i386/avx10-check.h: New.
* gcc.target/i386/avx10-helper.h: New.
* gcc.target/i386/avx10_2-builtin-1.c: Ditto.
* gcc.target/i386/avx10_2-512-media-1.c: Ditto.
* gcc.target/i386/avx10_2-media-1.c: Ditto..
* gcc.target/i386/avxvnniint8-builtin.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbssd-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbssds-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbsud-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbsuds-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbuud-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpbuuds-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbssd-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbssds-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbsud-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbsuds-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbuud-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpbuuds-2.c: Ditto.

Co-authored-by: Haochen Jiang 
---
 gcc/config.gcc|   3 +-
 gcc/config/i386/avx10_2-512mediaintrin.h  | 234 +++
 gcc/config/i386/avx10_2mediaintrin.h  | 367 ++
 gcc/config/i386/i386-builtin.def  |  68 +++-
 gcc/config/i386/i386-builtins.cc  |  10 +-
 gcc/config/i386/i386-expand.cc|   3 +
 gcc/config/i386/immintrin.h   |   4 +
 gcc/config/i386/sse.md|  66 +++-
 gcc/testsuite/gcc.target/i386/avx10-check.h   |  61 +++
 gcc/testsuite/gcc.target/i386/avx10-helper.h  |  23 ++
 .../gcc.target/i386/avx10-os-support.h|  23 ++
 .../gcc.target/i386/avx10_2-512-media-1.c |  52 +++
 .../gcc.target/i386/avx10_2-512-vpdpbssd-2.c  |  71 
 .../gcc.target/i386/avx10_2-512-vpdpbssds-2.c |  74 
 .../gcc.target/i386/avx10_2-512-vpdpbsud-2.c  |  71 
 .../gcc.target/i386/avx10_2-512-vpdpbsuds-2.c |  74 
 .../gcc.target/i386/avx10_2-512-vpdpbuud-2.c  |  70 
 .../gcc.target/i386/avx10_2-512-vpdpbuuds-2.c |  73 
 .../gcc.target/i386/avx10_2-builtin-1.c   |   8 +
 .../gcc.target/i386/avx10_2-media-1.c |  96 +
 .../gcc.target/i386/avx10_2-vpdpbssd-2.c  |  16 +
 .../gcc.target/i386/avx10_2-vpdpbssds-2.c |  16 +
 .../gcc.target/i386/avx10_2-vpdpbsud-2.c  |  16 +
 .../gcc.target/i386/avx10_2-vpdpbsuds-2.c |  16 +
 .../gcc.target/i386/avx10_2-vpdpbuud-2.c  |  16 +
 .../gcc.target/i386/avx10_2-vpdpbuuds-2.c |  16 +
 .../gcc.target/i386/avx512f-helper.h  |   6 +-
 .../gcc.target/i386/avxvnniint8-builtin.c |   8 +
 gcc/testsuite/gcc.target/i386/funcspec-56.inc |   4 +
 gcc/testsuite/lib/target-supports.exp |  36 ++
 30 files changed, 1577 insertions(+), 24 deletions(-)
 create mode 100644 gcc/config/i386/avx10_2-512mediaintrin.h
 create mode 100644 gcc/config/i386/avx10_2mediaintrin.h
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10-check.h
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10-helper.h
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10-os-support.h
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-media-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbssd-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbssds-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbsud-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbsuds-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbuud-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpbuuds-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-builtin-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-media

[PATCH 03/12] [PATCH 2/2] AVX10.2: Support media instructions

[Haochen Jiang]

gcc/ChangeLog:

* config/i386/avx10_2-512mediaintrin.h: Add new intrins.
* config/i386/avx10_2mediaintrin.h: Ditto.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/i386-builtins.cc (def_builtin): Handle shared
builtins between AVXVNNIINT16 and AVX10.2.
* config/i386/i386-expand.cc (ix86_check_builtin_isa_match):
Ditto.
* config/i386/sse.md (unspec): Add UNSPEC_VDPPHPS.
(_mpsadbw): New define_insn.
(avx10_2_mpsadbw): Ditto.
(vpdp_): Add AVX10_2_256.
(vpdp_v16si): New defin_insn.
(vpdp__mask): Ditto.
(*vpdp__maskz): Ditto.
(vpdp__maskz): New expander.
(vdpphps_): New define_insn.
(vdpphps__mask): Ditto.
(*vdpphps__maskz): Ditto.
(vdpphps__maskz): New expander.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avxvnniint16-1.c: Add new macro test.
* gcc.target/i386/avx-1.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-512-media-1.c: Add test.
* gcc.target/i386/avx10_2-media-1.c: Ditto.
* gcc.target/i386/avxvnniint16-builtin.c: New test.
* gcc.target/i386/avx10_2-512-vdpphps-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vmpsadbw-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwsud-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwsuds-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwusd-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwusds-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwuud-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vpdpwuuds-2.c: Ditto.
* gcc.target/i386/avx10_2-builtin-2.c: Ditto.
* gcc.target/i386/avx10_2-vdpphps-2.c: Ditto.
* gcc.target/i386/avx10_2-vmpsadbw-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwsud-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwsuds-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwusd-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwusds-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwuud-2.c: Ditto.
* gcc.target/i386/avx10_2-vpdpwuuds-2.c: Ditto.

Co-authored-by: Hongyu Wang 
---
 gcc/config/i386/avx10_2-512mediaintrin.h  | 280 +++
 gcc/config/i386/avx10_2mediaintrin.h  | 472 ++
 gcc/config/i386/i386-builtin.def  |  76 ++-
 gcc/config/i386/i386-builtins.cc  |  11 +-
 gcc/config/i386/i386-expand.cc|   3 +
 gcc/config/i386/sse.md| 145 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |   8 +
 .../gcc.target/i386/avx10_2-512-media-1.c |  60 +++
 .../gcc.target/i386/avx10_2-512-vdpphps-2.c   |  71 +++
 .../gcc.target/i386/avx10_2-512-vmpsadbw-2.c  |  93 
 .../gcc.target/i386/avx10_2-512-vpdpwsud-2.c  |  71 +++
 .../gcc.target/i386/avx10_2-512-vpdpwsuds-2.c |  74 +++
 .../gcc.target/i386/avx10_2-512-vpdpwusd-2.c  |  71 +++
 .../gcc.target/i386/avx10_2-512-vpdpwusds-2.c |  74 +++
 .../gcc.target/i386/avx10_2-512-vpdpwuud-2.c  |  70 +++
 .../gcc.target/i386/avx10_2-512-vpdpwuuds-2.c |  73 +++
 .../gcc.target/i386/avx10_2-builtin-2.c   |   8 +
 .../gcc.target/i386/avx10_2-media-1.c | 112 +
 .../gcc.target/i386/avx10_2-vdpphps-2.c   |  16 +
 .../gcc.target/i386/avx10_2-vmpsadbw-2.c  |  16 +
 .../gcc.target/i386/avx10_2-vpdpwsud-2.c  |  16 +
 .../gcc.target/i386/avx10_2-vpdpwsuds-2.c |  16 +
 .../gcc.target/i386/avx10_2-vpdpwusd-2.c  |  16 +
 .../gcc.target/i386/avx10_2-vpdpwusds-2.c |  16 +
 .../gcc.target/i386/avx10_2-vpdpwuud-2.c  |  16 +
 .../gcc.target/i386/avx10_2-vpdpwuuds-2.c |  16 +
 .../gcc.target/i386/avxvnniint16-1.c  |  42 +-
 .../gcc.target/i386/avxvnniint16-builtin.c|   8 +
 gcc/testsuite/gcc.target/i386/sse-13.c|   8 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  11 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  11 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   8 +
 32 files changed, 1953 insertions(+), 35 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vdpphps-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vmpsadbw-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwsud-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwsuds-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwusd-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwusds-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwuud-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-512-vpdpwuuds-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-builtin-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vdpphps-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-vmpsadbw-2

[PATCH 00/12] AVX10.2: Support new instructions

[Haochen Jiang]

Hi all,

The AVX10.2 ymm rounding patches has been merged to trunk around
6 hours ago. As mentioned before, next step will be AVX10.2 new
instruction support.

This patch series could be divided into three part.

The first patch will refactor m512-check.h under testsuite to reuse
AVX-512 helper functions and unions and avoid ABI warnings when using
AVX10.

The following ten patches will support all AVX10.2 new instrctions,
including:

  - AI Datatypes, Conversions, and post-Convolution Instructions.
  - Media Acceleration.
  - IEEE-754-2019 Minimum and Maximum Support.
  - Saturating Conversions.
  - Zero-extending Partial Vector Copies.
  - FP Scalar Comparison.

For FP Scalar Comparison part (a.k.a comx instructions), we will only
provide pattern support but not intrin support since it is redundant
with comi ones for common usage. We will also add some optimizations
afterwards for common usage with comx instructions. If there are some
strong requests, we will add intrin support in the future.

The final patch will add bf8 -> fp16 intrin for convenience. Since the
conversion from bf8 to fp16 is only casting for fraction part due to
same bits for exponent part, we will use a sequence of instructions
instead of new instructions. It is just like the scenario for bf16 ->
fp32 conversion.

After all these patch merged, the next step would be optimizations based
on AVX10.2 new instructions, including vnni vectorization, bf16
vectorization, comx optmization, etc.

Bootstrapped on x86-64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

[PATCH 01/12] i386: Refactor m512-check.h

[Haochen Jiang]

After AVX10 introduction, we still want to use AVX512 helper functions
to avoid duplicate code. In order to reuse them, we need to do some refactor
to make sure each function define happen under correct ISA to avoid ABI
warnings.

gcc/testsuite/ChangeLog:

* gcc.target/i386/m512-check.h: Wrap the function define with
correct vector size.
---
 gcc/testsuite/gcc.target/i386/m512-check.h | 66 --
 1 file changed, 35 insertions(+), 31 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/m512-check.h 
b/gcc/testsuite/gcc.target/i386/m512-check.h
index 68e74fce68d..d5d18372947 100644
--- a/gcc/testsuite/gcc.target/i386/m512-check.h
+++ b/gcc/testsuite/gcc.target/i386/m512-check.h
@@ -61,6 +61,12 @@ typedef union
  unsigned long long a[8];
 } union512i_uq;
 
+typedef union
+{
+  __m512h x;
+  _Float16 a[32];
+} union512h;
+
 typedef union
 {
   __m128h x;
@@ -73,27 +79,6 @@ typedef union
   _Float16 a[16];
 } union256h;
 
-typedef union
-{
-  __m512h x;
-  _Float16 a[32];
-} union512h;
-
-CHECK_EXP (union512i_b, char, "%d")
-CHECK_EXP (union512i_w, short, "%d")
-CHECK_EXP (union512i_d, int, "0x%x")
-CHECK_EXP (union512i_q, long long, "0x%llx")
-CHECK_EXP (union512, float, "%f")
-CHECK_EXP (union512d, double, "%f")
-CHECK_EXP (union512i_ub, unsigned char, "%d")
-CHECK_EXP (union512i_uw, unsigned short, "%d")
-CHECK_EXP (union512i_ud, unsigned int, "0x%x")
-CHECK_EXP (union512i_uq, unsigned long long, "0x%llx")
- 
-
-CHECK_FP_EXP (union512, float, ESP_FLOAT, "%f")
-CHECK_FP_EXP (union512d, double, ESP_DOUBLE, "%f")
-
 #define CHECK_ROUGH_EXP(UNION_TYPE, VALUE_TYPE, FMT)   \
 static int \
 __attribute__((noinline, unused))  \
@@ -126,28 +111,47 @@ check_rough_##UNION_TYPE (UNION_TYPE u, const VALUE_TYPE 
*v,  \
   return err;  \
 }
 
-CHECK_ROUGH_EXP (union512, float, "%f")
-CHECK_ROUGH_EXP (union512d, double, "%f")
+#ifndef ESP_FLOAT16
+#define ESP_FLOAT16 0.27
+#endif
+
 CHECK_ROUGH_EXP (union256, float, "%f")
 CHECK_ROUGH_EXP (union256d, double, "%f")
 CHECK_ROUGH_EXP (union128, float, "%f")
 CHECK_ROUGH_EXP (union128d, double, "%f")
 
-#ifdef AVX512FP16
+#ifndef AVX512F_LEN
+CHECK_EXP (union512i_b, char, "%d")
+CHECK_EXP (union512i_w, short, "%d")
+CHECK_EXP (union512i_d, int, "0x%x")
+CHECK_EXP (union512i_q, long long, "0x%llx")
+CHECK_EXP (union512, float, "%f")
+CHECK_EXP (union512d, double, "%f")
+CHECK_EXP (union512i_ub, unsigned char, "%d")
+CHECK_EXP (union512i_uw, unsigned short, "%d")
+CHECK_EXP (union512i_ud, unsigned int, "0x%x")
+CHECK_EXP (union512i_uq, unsigned long long, "0x%llx")
+ 
+CHECK_FP_EXP (union512, float, ESP_FLOAT, "%f")
+CHECK_FP_EXP (union512d, double, ESP_DOUBLE, "%f")
 
-CHECK_EXP (union128h, _Float16, "%f")
-CHECK_EXP (union256h, _Float16, "%f")
-CHECK_EXP (union512h, _Float16, "%f")
+CHECK_ROUGH_EXP (union512, float, "%f")
+CHECK_ROUGH_EXP (union512d, double, "%f")
 
-#ifndef ESP_FLOAT16
-#define ESP_FLOAT16 0.27
+#if defined(AVX512FP16)
+CHECK_EXP (union512h, _Float16, "%f")
+CHECK_FP_EXP (union512h, _Float16, ESP_FLOAT16, "%f")
+CHECK_ROUGH_EXP (union512h, _Float16, "%f")
+#endif
 #endif
 
+#if defined(AVX512FP16)
+CHECK_EXP (union128h, _Float16, "%f")
+CHECK_EXP (union256h, _Float16, "%f")
+
 CHECK_FP_EXP (union128h, _Float16, ESP_FLOAT16, "%f")
 CHECK_FP_EXP (union256h, _Float16, ESP_FLOAT16, "%f")
-CHECK_FP_EXP (union512h, _Float16, ESP_FLOAT16, "%f")
 
 CHECK_ROUGH_EXP (union128h, _Float16, "%f")
 CHECK_ROUGH_EXP (union256h, _Float16, "%f")
-CHECK_ROUGH_EXP (union512h, _Float16, "%f")
 #endif
-- 
2.43.5

[PATCH 22/22] AVX10.2 ymm rounding: Support vsqrtp{s, d, h} and vsubp{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 339 ++
 gcc/config/i386/i386-builtin.def  |   6 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   6 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  50 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   7 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  18 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  15 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   6 +
 8 files changed, 447 insertions(+)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index f35f2337858..c7146e37ec9 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -3986,6 +3986,216 @@ _mm256_maskz_scalef_round_ps (__mmask8 __U, __m256 __A, 
__m256 __B,
 (__mmask8) __U,
 __R);
 }
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_sqrt_round_pd (__m256d __A, const int __R)
+{
+  return (__m256d) __builtin_ia32_sqrtpd256_mask_round ((__v4df) __A,
+   (__v4df)
+   _mm256_undefined_pd (),
+   (__mmask8) -1,
+   __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_sqrt_round_pd (__m256d __W, __mmask8 __U, __m256d __A,
+  const int __R)
+{
+  return (__m256d) __builtin_ia32_sqrtpd256_mask_round ((__v4df) __A,
+   (__v4df) __W,
+   (__mmask8) __U,
+   __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_sqrt_round_pd (__mmask8 __U, __m256d __A, const int __R)
+{
+  return (__m256d) __builtin_ia32_sqrtpd256_mask_round ((__v4df) __A,
+   (__v4df)
+   _mm256_setzero_pd (),
+   (__mmask8) __U,
+   __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_sqrt_round_ph (__m256h __A, const int __R)
+{
+  return (__m256h) __builtin_ia32_sqrtph256_mask_round ((__v16hf) __A,
+   (__v16hf)
+   _mm256_undefined_ph (),
+   (__mmask16) -1,
+   __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_sqrt_round_ph (__m256h __W, __mmask16 __U, __m256h __A,
+  const int __R)
+{
+  return (__m256h) __builtin_ia32_sqrtph256_mask_round ((__v16hf) __A,
+   (__v16hf) __W,
+   (__mmask16) __U,
+   __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_sqrt_round_ph (__mmask16 __U, __m256h __A, const int __R)
+{
+  return (__m256h) __builtin_ia32_sqrtph256_mask_round ((__v16hf) __A,
+   (__v16hf)
+   _mm256_setzero_ph (),
+   (__mmask16) __U,
+   __R);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_sqrt_round_ps (__m256 __A, const int __R)
+{
+  return (__m256) __builtin_ia32_sqrtps256_mask_round ((__v8sf) __A,
+  (__v8sf)
+  _mm256_undefined_ps (),
+  (__mmask8) -1,
+  __R);
+}
+
+extern __inline __m256
+

[PATCH 17/22] AVX10.2 ymm rounding: Support vgetexpp{s, d, h} and vgetmantp{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V8SF_FTYPE_V8SF_V8SF_UQI_INT, V4DF_FTYPE_V4DF_V4DF_UQI_INT,
V16HF_FTYPE_V16HF_V16HF_UHI_INT, V16HF_FTYPE_V16HF_INT_V16HF_UHI_INT,
V4DF_FTYPE_V4DF_INT_V4DF_UQI_INT, V8SF_FTYPE_V8SF_INT_V8SF_UQI_INT.
* config/i386/sse.md:
(_getexp):
Add condition check.
(_getmant):
Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 341 ++
 gcc/config/i386/i386-builtin-types.def|   6 +
 gcc/config/i386/i386-builtin.def  |   6 +
 gcc/config/i386/i386-expand.cc|   6 +
 gcc/config/i386/sse.md|   4 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |   6 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  59 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   6 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  18 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  18 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   6 +
 11 files changed, 474 insertions(+), 2 deletions(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index afc1220fea4..07729a6cc04 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -3021,6 +3021,217 @@ _mm256_maskz_fnmsub_round_ps (__mmask8 __U, __m256 __A, 
__m256 __B,
   (__mmask8) __U,
   __R);
 }
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_getexp_round_pd (__m256d __A, const int __R)
+{
+  return
+(__m256d) __builtin_ia32_getexppd256_mask_round ((__v4df) __A,
+(__v4df)
+_mm256_undefined_pd (),
+(__mmask8) -1,
+__R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_getexp_round_pd (__m256d __W, __mmask8 __U, __m256d __A,
+const int __R)
+{
+  return (__m256d) __builtin_ia32_getexppd256_mask_round ((__v4df) __A,
+ (__v4df) __W,
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_getexp_round_pd (__mmask8 __U, __m256d __A, const int __R)
+{
+  return (__m256d) __builtin_ia32_getexppd256_mask_round ((__v4df) __A,
+ (__v4df)
+ _mm256_setzero_pd (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_getexp_round_ph (__m256h __A, const int __R)
+{
+  return (__m256h) __builtin_ia32_getexpph256_mask_round ((__v16hf) __A,
+ (__v16hf)
+ _mm256_setzero_ph (),
+ (__mmask16) -1,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_getexp_round_ph (__m256h __W, __mmask16 __U, __m256h __A,
+const int __R)
+{
+  return (__m256h) __builtin_ia32_getexpph256_mask_round ((__v16hf) __A,
+ (__v16hf) __W,
+ (__mmask16) __U,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_getexp_round_ph (__mmask16 __U, __m256h __A, const int __R)
+{
+  return (__m256h) __builtin_ia32_getexpph256_mask_round ((__v16hf) __A,
+ (__v16hf)
+

[PATCH 20/22] AVX10.2 ymm rounding: Support vreducep{s, d, h} and vrndscalep{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md:
(reducep):
Add condition check.
(_rndscale): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 367 ++
 gcc/config/i386/i386-builtin.def  |   6 +
 gcc/config/i386/sse.md|   4 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |   6 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  50 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   6 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  18 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  18 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   6 +
 9 files changed, 479 insertions(+), 2 deletions(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index ac0914415c9..d6b8e2695de 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -3646,6 +3646,233 @@ _mm256_maskz_range_round_ps (__mmask8 __U, __m256 __A, 
__m256 __B,
(__mmask8) __U,
__R);
 }
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_reduce_round_pd (__m256d __A, const int __C, const int __R)
+{
+  return (__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) __A,
+ __C,
+ (__v4df)
+ _mm256_setzero_pd (),
+ (__mmask8) -1,
+ __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_reduce_round_pd (__m256d __W, __mmask8 __U, __m256d __A,
+const int __C, const int __R)
+{
+  return (__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) __A,
+ __C,
+ (__v4df) __W,
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_reduce_round_pd (__mmask8 __U, __m256d __A, const int __C,
+ const int __R)
+{
+  return (__m256d) __builtin_ia32_reducepd256_mask_round ((__v4df) __A,
+ __C,
+ (__v4df)
+ _mm256_setzero_pd (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_reduce_round_ph (__m256h __A, const int __C, const int __R)
+{
+  return (__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) __A,
+ __C,
+ (__v16hf)
+ _mm256_setzero_ph (),
+ (__mmask16) -1,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_reduce_round_ph (__m256h __W, __mmask16 __U, __m256h __A,
+const int __C, const int __R)
+{
+  return (__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) __A,
+ __C,
+ (__v16hf) __W,
+ (__mmask16) __U,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_reduce_round_ph (__mmask16 __U, __m256h __A, const int __C,
+ const int __R)
+{
+  return (__m256h) __builtin_ia32_reduceph256_mask_round ((__v16hf) __A,
+ __C,
+

[PATCH 21/22] AVX10.2 ymm rounding: Support vscalefp{s,d,h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/sse.md:
(_scalef): Add condition check.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 182 ++
 gcc/config/i386/i386-builtin.def  |   3 +
 gcc/config/i386/sse.md|   2 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |   3 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  25 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   3 +
 gcc/testsuite/gcc.target/i386/sse-14.c|   9 +
 gcc/testsuite/gcc.target/i386/sse-22.c|   9 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   3 +
 9 files changed, 238 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index d6b8e2695de..f35f2337858 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -3873,6 +3873,119 @@ _mm256_maskz_roundscale_round_ps (__mmask8 __U, __m256 
__A, const int __C,
   (__mmask8) __U,
   __R);
 }
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_scalef_round_pd (__m256d __A, __m256d __B, const int __R)
+{
+  return
+(__m256d) __builtin_ia32_scalefpd256_mask_round ((__v4df) __A,
+(__v4df) __B,
+(__v4df)
+_mm256_undefined_pd (),
+(__mmask8) -1,
+__R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_scalef_round_pd (__m256d __W, __mmask8 __U, __m256d __A,
+__m256d __B, const int __R)
+{
+  return (__m256d) __builtin_ia32_scalefpd256_mask_round ((__v4df) __A,
+ (__v4df) __B,
+ (__v4df) __W,
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_scalef_round_pd (__mmask8 __U, __m256d __A, __m256d __B,
+ const int __R)
+{
+  return (__m256d) __builtin_ia32_scalefpd256_mask_round ((__v4df) __A,
+ (__v4df) __B,
+ (__v4df)
+ _mm256_setzero_pd (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_scalef_round_ph (__m256h __A, __m256h __B, const int __R)
+{
+  return
+(__m256h) __builtin_ia32_scalefph256_mask_round ((__v16hf) __A,
+(__v16hf) __B,
+(__v16hf)
+_mm256_undefined_ph (),
+(__mmask16) -1,
+__R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_scalef_round_ph (__m256h __W, __mmask16 __U, __m256h __A,
+__m256h __B, const int __R)
+{
+  return (__m256h) __builtin_ia32_scalefph256_mask_round ((__v16hf) __A,
+ (__v16hf) __B,
+ (__v16hf) __W,
+ (__mmask16) __U,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_scalef_round_ph (__mmask16 __U, __m256h __A, __m256h __B,
+ const int __R)
+{
+  return (__m256h) __builtin_ia32_scalefph256_mask_round ((__v16hf) __A,
+ (__v16hf) __B,
+   

[PATCH 14/22] AVX10.2 ymm rounding: Support vfm{sub, subadd}{132, 231, 213}p{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md:
(_fmsub__mask): Add condition check.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 350 ++
 gcc/config/i386/i386-builtin.def  |  18 +
 gcc/config/i386/sse.md|   2 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |  18 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  62 
 gcc/testsuite/gcc.target/i386/sse-13.c|  18 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  24 ++
 gcc/testsuite/gcc.target/i386/sse-22.c|  24 ++
 gcc/testsuite/gcc.target/i386/sse-23.c|  18 +
 9 files changed, 533 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 95e42410a10..346a32c1a8a 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -2419,6 +2419,284 @@ _mm256_maskz_fmaddsub_round_ps (__mmask8 __U, __m256 
__A, __m256 __B,
 (__mmask8) __U,
 __R);
 }
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fmsub_round_pd (__m256d __A, __m256d __B, __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfmsubpd256_mask_round ((__v4df) __A,
+ (__v4df) __B,
+ (__v4df) __D,
+ (__mmask8) -1, __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fmsub_round_pd (__m256d __A, __mmask8 __U, __m256d __B,
+   __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfmsubpd256_mask_round ((__v4df) __A,
+ (__v4df) __B,
+ (__v4df) __D,
+ (__mmask8) __U, __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fmsub_round_pd (__m256d __A, __m256d __B, __m256d __D,
+__mmask8 __U, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfmsubpd256_mask3_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df) __D,
+  (__mmask8) __U, __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fmsub_round_pd (__mmask8 __U, __m256d __A, __m256d __B,
+__m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfmsubpd256_maskz_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df) __D,
+  (__mmask8) __U, __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fmsub_round_ph (__m256h __A, __m256h __B, __m256h __D, const int __R)
+{
+  return (__m256h)
+__builtin_ia32_vfmsubph256_mask_round ((__v16hf) __A,
+  (__v16hf) __B,
+  (__v16hf) __D,
+  (__mmask16) -1, __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fmsub_round_ph (__m256h __A, __mmask16 __U, __m256h __B,
+   __m256h __D, const int __R)
+{
+  return (__m256h)
+__builtin_ia32_vfmsubph256_mask_round ((__v16hf) __A,
+  (__v16hf) __B,
+  (__v16hf) __D,
+  (__mmask16) __U, __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fmsub_round_ph (__m256h __A, __m256h __B, __m256h __D,
+__mmask16 __U, const int __R)
+{
+  return (__m256h)
+__builtin_ia32_vfmsubph256_mask3_round ((__v16hf) __A,
+

[PATCH 01/22] AVX10.2 ymm rounding: Support vadd{s, d, h} and vcmp{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config.gcc: Add avx10_2roundingintrin.h.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT, V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT,
V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT, UQI_FTYPE_V4DF_V4DF_INT_UQI_INT,
UHI_FTYPE_V16HF_V16HF_INT_UHI_INT, UQI_FTYPE_V8SF_V8SF_INT_UQI_INT.
* config/i386/immintrin.h: Include avx10_2roundingintrin.h.
* config/i386/sse.md: Change subst_attr name due to renaming.
* config/i386/subst.md:
(): Add condition check for avx10.2
rounding control 256bit intrins and renamed to ...
(): ...this.
(round_saeonly_mode512bit_condition): Add condition check for
avx10.2 rounding control 256 bit intris and renamed to ...
(round_saeonly_mode_condition): ...this.
* config/i386/avx10_2roundingintrin.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add -mavx10.2 and new builtin test.
* gcc.target/i386/avx-2.c: Ditto.
* gcc.target/i386/sse-13.c: Add new tests.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/avx10_2-rounding-1.c: New test.
---
 gcc/config.gcc|   2 +-
 gcc/config/i386/avx10_2roundingintrin.h   | 337 ++
 gcc/config/i386/i386-builtin-types.def|   8 +
 gcc/config/i386/i386-builtin.def  |   8 +
 gcc/config/i386/i386-expand.cc|   6 +
 gcc/config/i386/immintrin.h   |   2 +
 gcc/config/i386/sse.md| 100 +++---
 gcc/config/i386/subst.md  |  32 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |  10 +-
 gcc/testsuite/gcc.target/i386/avx-2.c |   2 +-
 .../gcc.target/i386/avx10_2-rounding-1.c  |  64 
 gcc/testsuite/gcc.target/i386/sse-13.c|   8 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  17 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  17 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   8 +
 15 files changed, 558 insertions(+), 63 deletions(-)
 create mode 100644 gcc/config/i386/avx10_2roundingintrin.h
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-rounding-1.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index a36dd1bcbc6..2c0f4518638 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -452,7 +452,7 @@ i[34567]86-*-* | x86_64-*-*)
   cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h
   raointintrin.h amxcomplexintrin.h avxvnniint16intrin.h
   sm3intrin.h sha512intrin.h sm4intrin.h
-  usermsrintrin.h"
+  usermsrintrin.h avx10_2roundingintrin.h"
;;
 ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
new file mode 100644
index 000..5698ed05c1d
--- /dev/null
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -0,0 +1,337 @@
+/* Copyright (C) 2024 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#ifndef _IMMINTRIN_H_INCLUDED
+#error "Never use  directly; include  
instead."
+#endif
+
+#ifndef _AVX10_2ROUNDINGINTRIN_H_INCLUDED
+#define _AVX10_2ROUNDINGINTRIN_H_INCLUDED
+
+#ifndef __AVX10_2_256__
+#pragma GCC push_options
+#pragma GCC target("avx10.2-256")
+#define __DISABLE_AVX10_2_256__
+#endif /* __AVX10_2_256__ */
+
+#ifdef  __OPTIMIZE__
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_add_round_pd (__m256d __A, __m256d __B, const int __R)
+{
+  return (__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df

[PATCH 18/22] AVX10.2 ymm rounding: Support v{max, min}p{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 360 ++
 gcc/config/i386/i386-builtin.def  |   6 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   6 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  50 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   6 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  18 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  18 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   6 +
 8 files changed, 470 insertions(+)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 07729a6cc04..a5712f5230a 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -3232,6 +3232,228 @@ _mm256_maskz_getmant_round_ps (__mmask8 __U, __m256 __A,
  _mm256_setzero_ps (),
  __U, __R);
 }
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_max_round_pd (__m256d __A, __m256d __B, const int __R)
+{
+  return (__m256d) __builtin_ia32_maxpd256_mask_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df)
+  _mm256_undefined_pd (),
+  (__mmask8) -1,
+  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_max_round_pd (__m256d __W, __mmask8 __U, __m256d __A,
+ __m256d __B, const int __R)
+{
+  return (__m256d) __builtin_ia32_maxpd256_mask_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df) __W,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_max_round_pd (__mmask8 __U, __m256d __A, __m256d __B,
+  const int __R)
+{
+  return (__m256d) __builtin_ia32_maxpd256_mask_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df)
+  _mm256_setzero_pd (),
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_max_round_ph (__m256h __A, __m256h __B, const int __R)
+{
+  return (__m256h) __builtin_ia32_maxph256_mask_round ((__v16hf) __A,
+  (__v16hf) __B,
+  (__v16hf)
+  _mm256_undefined_ph (),
+  (__mmask16) -1,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_max_round_ph (__m256h __W, __mmask16 __U, __m256h __A,
+ __m256h __B, const int __R)
+{
+  return (__m256h) __builtin_ia32_maxph256_mask_round ((__v16hf) __A,
+  (__v16hf) __B,
+  (__v16hf) __W,
+  (__mmask16) __U,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_max_round_ph (__mmask16 __U, __m256h __A, __m256h __B,
+  const int __R)
+{
+  return (__m256h) __builtin_ia32_maxph256_mask_round ((__v16hf) __A,
+  (__v16hf) __B,
+  (__v16hf)
+  _mm256_setzero_ph (),
+  (__mmask16) __U,
+  __R);
+}
+
+exter

[PATCH 04/22] AVX10.2 ymm rounding: Support vcvtph2p{s, d, sx} and vcvtph2{, u}{dq, qq} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V8SF_FTYPE_V8HF_V8SF_UQI_INT, V8SI_FTYPE_V8HF_V8SI_UQI_INT,
V4DF_FTYPE_V8HF_V4DF_UQI_INT, V4DI_FTYPE_V8HF_V4DI_UQI_INT.
* config/i386/sse.md:
(avx512fp16_float_extend_ph2):
Add condition check.
(avx512fp16_vcvtph2_
 ):
Ditto.
(avx512fp16_float_extend_ph2): Extend round saeonly.
(vcvtph2ps256): Ditto.
* config/i386/subst.md
(round_saeonly_applied): New condition.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-1.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 384 ++
 gcc/config/i386/i386-builtin-types.def|   4 +
 gcc/config/i386/i386-builtin.def  |   7 +
 gcc/config/i386/i386-expand.cc|   4 +
 gcc/config/i386/sse.md|  19 +-
 gcc/config/i386/subst.md  |   1 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   7 +
 .../gcc.target/i386/avx10_2-rounding-1.c  |  57 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   7 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  20 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  21 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   7 +
 12 files changed, 529 insertions(+), 9 deletions(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 3e5e9f3ba0e..29966f5e1bf 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -486,6 +486,246 @@ _mm256_maskz_cvt_roundpd_epu64 (__mmask8 __U, __m256d 
__A, const int __R)
  (__mmask8) __U,
  __R);
 }
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundph_epi32 (__m128h __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvtph2dq256_mask_round ((__v8hf) __A,
+ (__v8si)
+ _mm256_setzero_si256 (),
+ (__mmask8) -1,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundph_epi32 (__m256i __W, __mmask8 __U, __m128h __A,
+  const int __R)
+{
+  return (__m256i) __builtin_ia32_vcvtph2dq256_mask_round ((__v8hf) __A,
+  (__v8si) __W,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundph_epi32 (__mmask8 __U, __m128h __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvtph2dq256_mask_round ((__v8hf) __A,
+ (__v8si)
+ _mm256_setzero_si256 (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundph_pd (__m128h __A, const int __R)
+{
+  return (__m256d) __builtin_ia32_vcvtph2pd256_mask_round ((__v8hf) __A,
+  (__v4df)
+  _mm256_setzero_pd (),
+  (__mmask8) -1,
+  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundph_pd (__m256d __W, __mmask8 __U, __m128h __A,
+   const int __R)
+{
+  return (__m256d) __builtin_ia32_vcvtph2pd256_mask_round ((__v8hf) __A,
+  (__v4df) __W,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundph_pd (__mmask8 __U, __m128h __A

[PATCH 19/22] AVX10.2 ymm rounding: Support vmulp{s, d, h} and vrangep{s, d} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin):
Handle V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI_INT,
V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI_INT.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 313 ++
 gcc/config/i386/i386-builtin-types.def|   2 +
 gcc/config/i386/i386-builtin.def  |   5 +
 gcc/config/i386/i386-expand.cc|   2 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   5 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  43 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   5 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  15 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  15 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   5 +
 10 files changed, 410 insertions(+)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index a5712f5230a..ac0914415c9 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -3454,6 +3454,198 @@ _mm256_maskz_min_round_ps (__mmask8 __U, __m256 __A, 
__m256 __B,
  (__mmask8) __U,
  __R);
 }
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mul_round_pd (__m256d __A, __m256d __B, const int __R)
+{
+  return (__m256d) __builtin_ia32_mulpd256_mask_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df)
+  _mm256_undefined_pd (),
+  (__mmask8) -1,
+  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_mul_round_pd (__m256d __W, __mmask8 __U, __m256d __A,
+ __m256d __B, const int __R)
+{
+  return (__m256d) __builtin_ia32_mulpd256_mask_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df) __W,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_mul_round_pd (__mmask8 __U, __m256d __A, __m256d __B,
+  const int __R)
+{
+  return (__m256d) __builtin_ia32_mulpd256_mask_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df)
+  _mm256_setzero_pd (),
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mul_round_ph (__m256h __A, __m256h __B, const int __R)
+{
+  return (__m256h) __builtin_ia32_mulph256_mask_round ((__v16hf) __A,
+  (__v16hf) __B,
+  (__v16hf)
+  _mm256_undefined_ph (),
+  (__mmask16) -1,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_mul_round_ph (__m256h __W, __mmask16 __U, __m256h __A,
+ __m256h __B, const int __R)
+{
+  return (__m256h) __builtin_ia32_mulph256_mask_round ((__v16hf) __A,
+  (__v16hf) __B,
+  (__v16hf) __W,
+  (__mmask16) __U,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_mul_round_ph (__mmask16 __U, __m256h __A, __m256h __B,
+  const int __R)
+{
+  return (__m256h) __builtin_ia32_mulph256_mask_round ((__v16hf) __A,
+  

[PATCH 15/22] AVX10.2 ymm rounding: Support vfmulcph and vfnmadd{132, 231, 213}p{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 241 ++
 gcc/config/i386/i386-builtin.def  |  11 +
 gcc/testsuite/gcc.target/i386/avx-1.c |  11 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  50 
 gcc/testsuite/gcc.target/i386/sse-13.c|  11 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  14 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  14 +
 gcc/testsuite/gcc.target/i386/sse-23.c|  11 +
 8 files changed, 363 insertions(+)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 346a32c1a8a..3f833bffa54 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -2697,6 +2697,185 @@ _mm256_maskz_fmsubadd_round_ps (__mmask8 __U, __m256 
__A, __m256 __B,
 (__mmask8) __U,
 __R);
 }
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fmul_round_pch (__m256h __B, __m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmulcph256_round ((__v16hf) __B,
+(__v16hf) __D,
+__R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fmul_round_pch (__m256h __A, __mmask8 __U, __m256h __B,
+   __m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmulcph256_mask_round ((__v16hf) __B,
+ (__v16hf) __D,
+ (__v16hf) __A,
+ (__mmask16) __U,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fmul_round_pch (__mmask8 __U, __m256h __B, __m256h __D,
+const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmulcph256_mask_round ((__v16hf) __B,
+ (__v16hf) __D,
+ (__v16hf)
+ _mm256_setzero_ph (),
+ (__mmask16) __U,
+ __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fnmadd_round_pd (__m256d __A, __m256d __B, __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmaddpd256_mask_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df) __D,
+  (__mmask8) -1,
+  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fnmadd_round_pd (__m256d __A, __mmask8 __U, __m256d __B,
+__m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmaddpd256_mask_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df) __D,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fnmadd_round_pd (__m256d __A, __m256d __B, __m256d __D,
+ __mmask8 __U, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmaddpd256_mask3_round ((__v4df) __A,
+   (__v4df) __B,
+   (__v4df) __D,
+   (__mmask8) __U,
+   __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fnmadd_round_pd (__mmask8 __U, __m256d __A, __m256d __B,
+ __m256d __D, const in

[PATCH 11/22] AVX10.2 ymm rounding: Support vfc{madd, mul}cph, vfixupimmp{s, d} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V16HF_FTYPE_V16HF_V16HF_INT, V16HF_FTYPE_V16HF_V16HF_V16HF_INT,
V16HF_FTYPE_V16HF_V16HF_V16HF_UQI_INT,
V4DF_FTYPE_V4DF_V4DF_V4DI_INT_UQI_INT,
V8SF_FTYPE_V8SF_V8SF_V8SI_INT_UQI_INT.
* config/i386/sse.md:
(_fixupimm):
Add condition check.
(_fixupimm_mask): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: New test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 247 ++
 gcc/config/i386/i386-builtin-types.def|   5 +
 gcc/config/i386/i386-builtin.def  |  10 +
 gcc/config/i386/i386-expand.cc|   5 +
 gcc/config/i386/sse.md|   4 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |  10 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  49 
 gcc/testsuite/gcc.target/i386/sse-13.c|  10 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  13 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  13 +
 gcc/testsuite/gcc.target/i386/sse-23.c|  10 +
 11 files changed, 374 insertions(+), 2 deletions(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 15ea46b5983..d5ea6bc57da 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -1934,6 +1934,164 @@ _mm256_maskz_div_round_ps (__mmask8 __U, __m256 __A, 
__m256 __B,
  (__mmask8) __U,
  __R);
 }
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fcmadd_round_pch (__m256h __A, __m256h __B, __m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfcmaddcph256_round ((__v16hf) __A,
+  (__v16hf) __B,
+  (__v16hf) __D,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fcmadd_round_pch (__m256h __A, __mmask8 __U, __m256h __B,
+ __m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfcmaddcph256_mask_round ((__v16hf) __A,
+   (__v16hf) __B,
+   (__v16hf) __D,
+   __U,
+   __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fcmadd_round_pch (__m256h __A, __m256h __B, __m256h __D,
+  __mmask8 __U, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfcmaddcph256_mask3_round ((__v16hf) __A,
+(__v16hf) __B,
+(__v16hf) __D,
+__U,
+__R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fcmadd_round_pch (__mmask8 __U, __m256h __A, __m256h __B,
+  __m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfcmaddcph256_maskz_round ((__v16hf) __A,
+(__v16hf) __B,
+(__v16hf) __D,
+__U,
+__R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fcmul_round_pch (__m256h __A, __m256h __B, const int __R)
+{
+  return
+(__m256h) __builtin_ia32_vfcmulcph256_round ((__v16hf) __A,
+(__v16hf) __B,
+__R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fcmul_round_pch (__m256h __W, __mmask8 __U, __m256h __A,
+__m256h __B, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfcmulcph256_mask_round ((__v16hf) __A,
+

[PATCH 16/22] AVX10.2 ymm rounding: Support vfnmsub{132, 231, 213}p{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md:
(_fnmsub__mask3): Add condition check.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 181 ++
 gcc/config/i386/i386-builtin.def  |   9 +
 gcc/config/i386/sse.md|   2 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |   9 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  31 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   9 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  12 ++
 gcc/testsuite/gcc.target/i386/sse-22.c|  12 ++
 gcc/testsuite/gcc.target/i386/sse-23.c|   9 +
 9 files changed, 273 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 3f833bffa54..afc1220fea4 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -2876,6 +2876,151 @@ _mm256_maskz_fnmadd_round_ps (__mmask8 __U, __m256 __A, 
__m256 __B,
   (__mmask8) __U,
   __R);
 }
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fnmsub_round_pd (__m256d __A, __m256d __B, __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmsubpd256_mask_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df) __D,
+  (__mmask8) -1,
+  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fnmsub_round_pd (__m256d __A, __mmask8 __U, __m256d __B,
+__m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmsubpd256_mask_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df) __D,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fnmsub_round_pd (__m256d __A, __m256d __B, __m256d __D,
+ __mmask8 __U, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmsubpd256_mask3_round ((__v4df) __A,
+   (__v4df) __B,
+   (__v4df) __D,
+   (__mmask8) __U,
+   __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fnmsub_round_pd (__mmask8 __U, __m256d __A, __m256d __B,
+ __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmsubpd256_maskz_round ((__v4df) __A,
+   (__v4df) __B,
+   (__v4df) __D,
+   (__mmask8) __U,
+   __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fnmsub_round_ph (__m256h __A, __m256h __B, __m256h __D, const int __R)
+{
+  return (__m256h)
+__builtin_ia32_vfnmsubph256_mask_round ((__v16hf) __A,
+   (__v16hf) __B,
+   (__v16hf) __D,
+   (__mmask16) -1,
+   __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fnmsub_round_ph (__m256h __A, __mmask16 __U, __m256h __B,
+__m256h __D, const int __R)
+{
+  return (__m256h)
+__builtin_ia32_vfnmsubph256_mask_round ((__v16hf) __A,
+   (__v16hf) __B,
+   (__v16hf) __D,
+   (__mmask16) __U,
+   __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_

[PATCH 09/22] AVX10.2 ymm rounding: Support vcvttps2{, u}{dq, qq} and vcvtu{dq, qq}2p{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md
(unspec_fix_truncv8sfv8si2): Extend rounding control.
(fixuns_trunc2):
Ditto.

(floatuns2):
Add condition check.

(fix_trunc2):
Remove round_saeonly_name.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-2.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 492 ++
 gcc/config/i386/i386-builtin.def  |   9 +
 gcc/config/i386/sse.md|  27 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |   9 +
 .../gcc.target/i386/avx10_2-rounding-2.c  |  75 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   9 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  26 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  27 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   9 +
 9 files changed, 670 insertions(+), 13 deletions(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 45a04e5a7a8..384facb424c 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -1451,6 +1451,312 @@ _mm256_maskz_cvtt_roundph_epi16 (__mmask16 __U, __m256h 
__A, const int __R)
  (__mmask16) __U,
  __R);
 }
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtt_roundps_epi32 (__m256 __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_cvttps2dq256_mask_round ((__v8sf) __A,
+ (__v8si)
+ _mm256_undefined_si256 (),
+ (__mmask8) -1,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtt_roundps_epi32 (__m256i __W, __mmask8 __U, __m256 __A,
+   const int __R)
+{
+  return (__m256i) __builtin_ia32_cvttps2dq256_mask_round ((__v8sf) __A,
+  (__v8si) __W,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtt_roundps_epi32 (__mmask8 __U, __m256 __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_cvttps2dq256_mask_round ((__v8sf) __A,
+ (__v8si)
+ _mm256_setzero_si256 (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtt_roundps_epi64 (__m128 __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_cvttps2qq256_mask_round ((__v4sf) __A,
+ (__v4di)
+ _mm256_setzero_si256 (),
+ (__mmask8) -1,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtt_roundps_epi64 (__m256i __W, __mmask8 __U, __m128 __A,
+   const int __R)
+{
+  return (__m256i) __builtin_ia32_cvttps2qq256_mask_round ((__v4sf) __A,
+  (__v4di) __W,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtt_roundps_epi64 (__mmask8 __U, __m128 __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_cvttps2qq256_mask_round ((__v4sf) __A,
+ (__v4di)
+ _mm256_setzero_si256 (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline_

[PATCH 07/22] AVX10.2 ymm rounding: Support vcvtqq2p{s, d, h} and vcvttpd2{, u}{dq, qq} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V4DF_FTYPE_V4DI_V4DF_UQI_INT, V4SF_FTYPE_V4DI_V4SF_UQI_INT,
V8HF_FTYPE_V4DI_V8HF_UQI_INT.
* config/i386/sse.md:
(avx512fp16_vcvtqq2ph_v4di_mask_round): New expand.
(*avx512fp16_vcvt2ph__mask):
Extend round control and add "_1" suffix.

(float2):
Add condition check.

(float2):
Ditto.
(float2):
Limit suffix output.
(unspec_fix_truncv4dfv4si2): Extend round control.
(unspec_fixuns_truncv4dfv4si2): Ditto.
* config/i386/subst.md (round_qq2pssuff): New iterator.
(round_saeonly_suff): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-2.c: New test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 390 ++
 gcc/config/i386/i386-builtin-types.def|   3 +
 gcc/config/i386/i386-builtin.def  |   7 +
 gcc/config/i386/i386-expand.cc|   3 +
 gcc/config/i386/sse.md|  43 +-
 gcc/config/i386/subst.md  |   2 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   7 +
 .../gcc.target/i386/avx10_2-rounding-2.c  |  72 
 gcc/testsuite/gcc.target/i386/sse-13.c|   7 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  21 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  21 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   7 +
 12 files changed, 569 insertions(+), 14 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-rounding-2.c

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index fca10a6b586..25efd9d7b96 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -1003,6 +1003,244 @@ _mm256_maskz_cvt_roundps_epu64 (__mmask8 __U, __m128 
__A, const int __R)
  (__mmask8) __U,
  __R);
 }
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundepi64_pd (__m256i __A, const int __R)
+{
+  return (__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) __A,
+ (__v4df)
+ _mm256_setzero_pd (),
+ (__mmask8) -1,
+ __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundepi64_pd (__m256d __W, __mmask8 __U, __m256i __A,
+  const int __R)
+{
+  return (__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) __A,
+ (__v4df) __W,
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundepi64_pd (__mmask8 __U, __m256i __A, const int __R)
+{
+  return (__m256d) __builtin_ia32_cvtqq2pd256_mask_round ((__v4di) __A,
+ (__v4df)
+ _mm256_setzero_pd (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m128h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundepi64_ph (__m256i __A, const int __R)
+{
+  return (__m128h) __builtin_ia32_vcvtqq2ph256_mask_round ((__v4di) __A,
+  (__v8hf)
+  _mm_setzero_ph (),
+  (__mmask8) -1,
+  __R);
+}
+
+extern __inline __m128h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundepi64_ph (__m128h __W, __mmask8 __U, __m256i __A,
+  const int __R)
+{
+  return (__m128h) __builtin_ia32_vcvtqq2ph256_mask_round ((__v4di) __A,
+  (__v8hf) __W,
+ 

[PATCH 03/22] AVX10.2 ymm rounding: Support vcvtpd2{, u}{dq, qq} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: Add new intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V4DI_FTYPE_V4DF_V4DI_UQI_INT, V4SI_FTYPE_V4DF_V4SI_UQI_INT.
* config/i386/sse.md:
(avx_cvtpd2dq256): Change name to
avx_cvtpd2dq256 and extend pattern to
generate 256bit insns.
(fixuns_notrunc2):
Add round_mode_condition.
* config/i386/subst.md (round_pd2udqsuff): New iterator.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-14.c: Add new macro test.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/avx10_2-rounding-1.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 218 ++
 gcc/config/i386/i386-builtin-types.def|   2 +
 gcc/config/i386/i386-builtin.def  |   4 +
 gcc/config/i386/i386-expand.cc|   2 +
 gcc/config/i386/sse.md|  13 +-
 gcc/config/i386/subst.md  |   1 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   4 +
 .../gcc.target/i386/avx10_2-rounding-1.c  |  33 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   4 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  12 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  12 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   4 +
 12 files changed, 303 insertions(+), 6 deletions(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 09285c1ffcd..3e5e9f3ba0e 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -348,6 +348,144 @@ _mm256_maskz_cvt_roundpd_ps (__mmask8 __U, __m256d __A, 
const int __R)
 (__mmask8) __U,
 __R);
 }
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundpd_epi32 (__m256d __A, const int __R)
+{
+  return
+(__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) __A,
+(__v4si)
+_mm_undefined_si128 (),
+(__mmask8) -1,
+__R);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundpd_epi32 (__m128i __W, __mmask8 __U, __m256d __A,
+  const int __R)
+{
+  return (__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) __A,
+ (__v4si) __W,
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundpd_epi32 (__mmask8 __U, __m256d __A, const int __R)
+{
+  return (__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) __A,
+ (__v4si)
+ _mm_setzero_si128 (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundpd_epi64 (__m256d __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) __A,
+(__v4di)
+_mm256_setzero_si256 (),
+(__mmask8) -1,
+__R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundpd_epi64 (__m256i __W, __mmask8 __U, __m256d __A,
+  const int __R)
+{
+  return (__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) __A,
+ (__v4di) __W,
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundpd_epi64 (__mmask8 __U, __m256d __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) __A,
+

[PATCH 00/22] Support AVX10.2 ymm rounding

[Haochen Jiang]

Hi all,

The initial patch for AVX10.2 has been merged this week.

For the upcoming patches, we will first upstream ymm rounding control part.

In ymm rounding part, ALL the instructions in AVX512 with 512-bit rounding
control will also have 256-bit rounding control in AVX10.2.

For clearness, the patch order is based on alphabetical order. Each patch
will include its intrin definition and related tests. Sometimes pattern is
not changed in the patch because the previous change in the patch series
has already enabled the 256 bit rounding in the pattern.

Bootstrapped on x86-64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

Ref: Intel Advanced Vector Extensions 10.2 Architecture Specification
https://cdrdv2.intel.com/v1/dl/getContent/828965

[PATCH 13/22] AVX10.2 ymm rounding: Support vfmaddcph and vfmaddsub{132, 231, 213}p{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md:
(_fmaddsub__mask): Add condition check.
(_fmaddsub__mask3): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 238 ++
 gcc/config/i386/i386-builtin.def  |  13 +
 gcc/config/i386/sse.md|   4 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |  13 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  43 
 gcc/testsuite/gcc.target/i386/sse-13.c|  13 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  16 ++
 gcc/testsuite/gcc.target/i386/sse-22.c|  15 ++
 gcc/testsuite/gcc.target/i386/sse-23.c|  13 +
 9 files changed, 366 insertions(+), 2 deletions(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 9015095144e..95e42410a10 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -2232,6 +2232,193 @@ _mm256_maskz_fmadd_round_ps (__mmask8 __U, __m256 __A, 
__m256 __B,
  (__mmask8) __U,
  __R);
 }
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fmadd_round_pch (__m256h __A, __m256h __B, __m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmaddcph256_round ((__v16hf) __A,
+ (__v16hf) __B,
+ (__v16hf) __D,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fmadd_round_pch (__m256h __A, __mmask16 __U, __m256h __B,
+__m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmaddcph256_mask_round ((__v16hf) __A,
+  (__v16hf) __B,
+  (__v16hf) __D,
+  __U,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fmadd_round_pch (__m256h __A, __m256h __B, __m256h __D,
+ __mmask16 __U, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmaddcph256_mask3_round ((__v16hf) __A,
+   (__v16hf) __B,
+   (__v16hf) __D,
+   __U,
+   __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fmadd_round_pch (__mmask16 __U, __m256h __A, __m256h __B,
+ __m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmaddcph256_maskz_round ((__v16hf) __A,
+   (__v16hf) __B,
+   (__v16hf) __D,
+   __U,
+   __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fmaddsub_round_pd (__m256d __A, __m256d __B, __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfmaddsubpd256_mask_round ((__v4df) __A,
+(__v4df) __B,
+(__v4df) __D,
+(__mmask8) -1,
+__R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fmaddsub_round_pd (__m256d __A, __mmask8 __U, __m256d __B,
+  __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfmaddsubpd256_mask_round ((__v4df) __A,
+(__v4df) __B,
+(__v4df) __D,
+(__mmask8) __

[PATCH 05/22] AVX10.2 ymm rounding: Support vcvtph2{, u}w and vcvtps2p{d, hx} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V16HI_FTYPE_V16HF_V16HI_UHI_INT, V4DF_FTYPE_V4SF_V4DF_UQI_INT
V8HF_FTYPE_V8SF_V8HF_UQI_INT.
* config/i386/sse.md
(avx512fp16_vcvt2ph_):
Add round condition check.
* config/i386/subst.md (round_mode_condition): Add V16HI check for
256bit.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-1.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 220 ++
 gcc/config/i386/i386-builtin-types.def|   3 +
 gcc/config/i386/i386-builtin.def  |   4 +
 gcc/config/i386/i386-expand.cc|   3 +
 gcc/config/i386/sse.md|   2 +-
 gcc/config/i386/subst.md  |   1 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   4 +
 .../gcc.target/i386/avx10_2-rounding-1.c  |  36 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   4 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  12 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  12 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   4 +
 12 files changed, 304 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 29966f5e1bf..bc3f92a7d1a 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -726,6 +726,143 @@ _mm256_maskz_cvt_roundph_epu64 (__mmask8 __U, __m128h 
__A, const int __R)
   (__mmask8) __U,
   __R);
 }
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundph_epu16 (__m256h __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) __A,
+ (__v16hi)
+ _mm256_undefined_si256 (),
+ (__mmask16) -1,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundph_epu16 (__m256i __W, __mmask16 __U, __m256h __A,
+  const int __R)
+{
+  return (__m256i) __builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) __A,
+  (__v16hi) __W,
+  (__mmask16) __U,
+  __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundph_epu16 (__mmask16 __U, __m256h __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvtph2uw256_mask_round ((__v16hf) __A,
+ (__v16hi)
+ _mm256_setzero_si256 (),
+ (__mmask16) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundph_epi16 (__m256h __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvtph2w256_mask_round ((__v16hf) __A,
+(__v16hi)
+_mm256_undefined_si256 (),
+(__mmask16) -1,
+__R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundph_epi16 (__m256i __W, __mmask16 __U, __m256h __A,
+  const int __R)
+{
+  return (__m256i) __builtin_ia32_vcvtph2w256_mask_round ((__v16hf) __A,
+ (__v16hi) __W,
+ (__mmask16) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundph_epi16 (__mmask16 __U, __m256h __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvtph2w256_mask_round ((__v16hf) __A,
+

[PATCH 08/22] AVX10.2 ymm rounding: Support vcvttph2{, u}{dq, qq, w} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md 
(avx512fp16_fix_trunc2):
Extend round control for 256bit.
(unspec_avx512fp16_fix_trunc2):
Ditto.

(avx512fp16_fix_trunc2):
Add condition check.
* config/i386/subst.md
(round_saeonly_mode_condition): Add V16HI check for 256bit.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-2.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 335 ++
 gcc/config/i386/i386-builtin.def  |   6 +
 gcc/config/i386/sse.md|  10 +-
 gcc/config/i386/subst.md  |   1 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   6 +
 .../gcc.target/i386/avx10_2-rounding-2.c  |  46 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   6 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  18 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  18 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   6 +
 10 files changed, 447 insertions(+), 5 deletions(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 25efd9d7b96..45a04e5a7a8 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -1241,6 +1241,216 @@ _mm256_maskz_cvtt_roundpd_epu64 (__mmask8 __U, __m256d 
__A, const int __R)
   (__mmask8) __U,
   __R);
 }
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtt_roundph_epi32 (__m128h __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvttph2dq256_mask_round ((__v8hf) __A,
+  (__v8si)
+  _mm256_setzero_si256 (),
+  (__mmask8) -1,
+  __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtt_roundph_epi32 (__m256i __W, __mmask8 __U, __m128h __A,
+   const int __R)
+{
+  return (__m256i) __builtin_ia32_vcvttph2dq256_mask_round ((__v8hf) __A,
+   (__v8si) __W,
+   (__mmask8) __U,
+   __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtt_roundph_epi32 (__mmask8 __U, __m128h __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvttph2dq256_mask_round ((__v8hf) __A,
+  (__v8si)
+  _mm256_setzero_si256 (),
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtt_roundph_epi64 (__m128h __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvttph2qq256_mask_round ((__v8hf) __A,
+  (__v4di)
+  _mm256_setzero_si256 (),
+  (__mmask8) -1,
+  __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtt_roundph_epi64 (__m256i __W, __mmask8 __U, __m128h __A,
+   const int __R)
+{
+  return (__m256i) __builtin_ia32_vcvttph2qq256_mask_round ((__v8hf) __A,
+   (__v4di) __W,
+   (__mmask8) __U,
+   __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtt_roundph_epi64 (__mmask8 __U, __m128h __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvttph2qq256_mask_round ((__v8hf) __A,
+  (__v4di)
+  _mm256_setzero_si256 (),
+  

[PATCH 10/22] AVX10.2 ymm rounding: Support vcvt{, u}w2ph and vdivp{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V16HF_FTYPE_V16HI_V16HF_UHI_INT.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: New test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 286 ++
 gcc/config/i386/i386-builtin-types.def|   1 +
 gcc/config/i386/i386-builtin.def  |   5 +
 gcc/config/i386/i386-expand.cc|   1 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   5 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  58 
 gcc/testsuite/gcc.target/i386/sse-13.c|   5 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  15 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  15 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   5 +
 10 files changed, 396 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 384facb424c..15ea46b5983 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -1757,6 +1757,183 @@ _mm256_maskz_cvt_roundepu64_ps (__mmask8 __U, __m256i 
__A, const int __R)
  (__mmask8) __U,
  __R);
 }
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundepu16_ph (__m256i __A, const int __R)
+{
+  return (__m256h) __builtin_ia32_vcvtuw2ph256_mask_round ((__v16hi) __A,
+  (__v16hf)
+  _mm256_setzero_ph (),
+  (__mmask16) -1,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundepu16_ph (__m256h __W, __mmask16 __U, __m256i __A,
+  const int __R)
+{
+  return (__m256h) __builtin_ia32_vcvtuw2ph256_mask_round ((__v16hi) __A,
+  (__v16hf) __W,
+  (__mmask16) __U,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundepu16_ph (__mmask16 __U, __m256i __A, const int __R)
+{
+  return (__m256h) __builtin_ia32_vcvtuw2ph256_mask_round ((__v16hi) __A,
+  (__v16hf)
+  _mm256_setzero_ph (),
+  (__mmask16) __U,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundepi16_ph (__m256i __A, const int __R)
+{
+  return (__m256h) __builtin_ia32_vcvtw2ph256_mask_round ((__v16hi) __A,
+ (__v16hf)
+ _mm256_setzero_ph (),
+ (__mmask16) -1,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundepi16_ph (__m256h __W, __mmask16 __U, __m256i __A,
+  const int __R)
+{
+  return (__m256h) __builtin_ia32_vcvtw2ph256_mask_round ((__v16hi) __A,
+ (__v16hf) __W,
+ (__mmask16) __U,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundepi16_ph (__mmask16 __U, __m256i __A, const int __R)
+{
+  return (__m256h) __builtin_ia32_vcvtw2ph256_mask_round ((__v16hi) __A,
+ (__v16hf)
+ _mm256_setzero_ph (),
+ (__mmask16) __U,
+ __R);
+}
+
+extern __inline __m256d
+__attri

[PATCH 02/22] AVX10.2 ymm rounding: Support vcvtdq2p{s, h} and vcvtpd2p{s, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: Add new intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V8SF_FTYPE_V8SI_V8SF_UQI_INT, V4SF_FTYPE_V4DF_V4SF_UQI_INT,
V8HF_FTYPE_V8SI_V8HF_UQI_INT, V8HF_FTYPE_V4DF_V8HF_UQI_INT.
* config/i386/sse.md:

(avx512fp16_vcvt2ph_):
Add condition check.
(avx512fp16_vcvtpd2ph_v4df_mask_round): New expand.
(*avx512fp16_vcvt2ph__mask): Change name to
avx512fp16_vcvt2ph__mask_1
and extend pattern to generate 256bit insns.
(avx_cvtpd2ps256): Change name to
avx_cvtpd2ps256 and extend pattern to
generate 256bit insns.
* config/i386/subst.md (round_applied): New condition.
(round_suff): New iterator.
(round_mode_condition): Add V32HI check for 512bit.
(round_saeonly_mode_condition): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-14.c: Add new macro test.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/avx10_2-rounding-1.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 210 ++
 gcc/config/i386/i386-builtin-types.def|   4 +
 gcc/config/i386/i386-builtin.def  |   4 +
 gcc/config/i386/i386-expand.cc|   4 +
 gcc/config/i386/sse.md|  32 ++-
 gcc/config/i386/subst.md  |   4 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   4 +
 .../gcc.target/i386/avx10_2-rounding-1.c  |  44 +++-
 gcc/testsuite/gcc.target/i386/sse-13.c|   4 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  12 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  12 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   4 +
 12 files changed, 322 insertions(+), 16 deletions(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index 5698ed05c1d..09285c1ffcd 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -216,6 +216,138 @@ _mm256_mask_cmp_round_ps_mask (__mmask8 __U, __m256 __A, 
__m256 __B,
(__mmask8) __U,
__R);
 }
+
+extern __inline __m128h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundepi32_ph (__m256i __A, const int __R)
+{
+  return (__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) __A,
+  (__v8hf)
+  _mm_setzero_ph (),
+  (__mmask8) -1,
+  __R);
+}
+
+extern __inline __m128h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundepi32_ph (__m128h __W, __mmask8 __U, __m256i __A,
+  const int __R)
+{
+  return (__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) __A,
+  (__v8hf) __W,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m128h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundepi32_ph (__mmask8 __U, __m256i __A, const int __R)
+{
+  return (__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) __A,
+  (__v8hf)
+  _mm_setzero_ph (),
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundepi32_ps (__m256i __A, const int __R)
+{
+  return (__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) __A,
+(__v8sf)
+_mm256_undefined_ps (),
+(__mmask8) -1,
+__R);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundepi32_ps (__m256 __W, __mmask8 __U, __m256i __A,
+  const int __R)
+{
+  return (__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) __A,
+   

[PATCH 12/22] AVX10.2 ymm rounding: Support vfmadd{132, 231, 213}p{s, d, h} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md:
(_fmadd__mask3): Add condition check.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-3.c: New test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 176 ++
 gcc/config/i386/i386-builtin.def  |   9 +
 gcc/config/i386/sse.md|   2 +-
 gcc/testsuite/gcc.target/i386/avx-1.c |   9 +
 .../gcc.target/i386/avx10_2-rounding-3.c  |  31 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   9 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  12 ++
 gcc/testsuite/gcc.target/i386/sse-22.c|  12 ++
 gcc/testsuite/gcc.target/i386/sse-23.c|   9 +
 9 files changed, 268 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index d5ea6bc57da..9015095144e 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -2092,6 +2092,146 @@ _mm256_maskz_fixupimm_round_ps (__mmask8 __U, __m256 
__A, __m256 __B,
(__mmask8) __U,
__R);
 }
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fmadd_round_pd (__m256d __A, __m256d __B, __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfmaddpd256_mask_round ((__v4df) __A,
+ (__v4df) __B,
+ (__v4df) __D,
+ (__mmask8) -1,
+ __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fmadd_round_pd (__m256d __A, __mmask8 __U, __m256d __B,
+   __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfmaddpd256_mask_round ((__v4df) __A,
+ (__v4df) __B,
+ (__v4df) __D,
+ (__mmask8) __U, __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fmadd_round_pd (__m256d __A, __m256d __B, __m256d __D,
+__mmask8 __U, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfmaddpd256_mask3_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df) __D,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fmadd_round_pd (__mmask8 __U, __m256d __A, __m256d __B,
+__m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfmaddpd256_maskz_round ((__v4df) __A,
+  (__v4df) __B,
+  (__v4df) __D,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fmadd_round_ph (__m256h __A, __m256h __B, __m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmaddph256_mask_round ((__v16hf) __A,
+ (__v16hf) __B,
+ (__v16hf) __D,
+ (__mmask16) -1,
+ __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fmadd_round_ph (__m256h __A, __mmask16 __U, __m256h __B,
+   __m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmaddph256_mask_round ((__v16hf) __A,
+ (__v16hf) __B,
+ (__v16hf) __D,
+ (__mmask16) __U,
+ __R);
+}
+
+extern __inline __m256h
+__attri

[PATCH 06/22] AVX10.2 ymm rounding: Support vcvtps2{, u}{dq, qq} intrins

[Haochen Jiang]

From: "Hu, Lin1" 

gcc/ChangeLog:

* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V8SI_FTYPE_V8SF_V8SI_UQI_INT, V4DI_FTYPE_V4SF_V4DI_UQI_INT.
* config/i386/sse.md
(_fix_notrunc):
Extend to round.

(_fixuns_notrunc):
Add round condition check.
* config/i386/subst.md (round_constraint4): New.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx-1.c: Add new builtin test.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add new macro test.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10_2-rounding-1.c: Add test.
---
 gcc/config/i386/avx10_2roundingintrin.h   | 226 ++
 gcc/config/i386/i386-builtin-types.def|   2 +
 gcc/config/i386/i386-builtin.def  |   4 +
 gcc/config/i386/i386-expand.cc|   2 +
 gcc/config/i386/sse.md|  10 +-
 gcc/config/i386/subst.md  |   1 +
 gcc/testsuite/gcc.target/i386/avx-1.c |   4 +
 .../gcc.target/i386/avx10_2-rounding-1.c  |  32 +++
 gcc/testsuite/gcc.target/i386/sse-13.c|   4 +
 gcc/testsuite/gcc.target/i386/sse-14.c|  12 +
 gcc/testsuite/gcc.target/i386/sse-22.c|  12 +
 gcc/testsuite/gcc.target/i386/sse-23.c|   4 +
 12 files changed, 308 insertions(+), 5 deletions(-)

diff --git a/gcc/config/i386/avx10_2roundingintrin.h 
b/gcc/config/i386/avx10_2roundingintrin.h
index bc3f92a7d1a..fca10a6b586 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -863,6 +863,146 @@ _mm256_maskz_cvtx_roundps_ph (__mmask8 __U, __m256 __A, 
const int __R)
(__mmask8) __U,
__R);
 }
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundps_epi32 (__m256 __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) __A,
+ (__v8si)
+ _mm256_undefined_si256 (),
+ (__mmask8) -1,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundps_epi32 (__m256i __W, __mmask8 __U, __m256 __A,
+  const int __R)
+{
+  return (__m256i) __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) __A,
+  (__v8si) __W,
+  (__mmask8) __U,
+  __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundps_epi32 (__mmask8 __U, __m256 __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_vcvtps2dq256_mask_round ((__v8sf) __A,
+ (__v8si)
+ _mm256_setzero_si256 (),
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvt_roundps_epi64 (__m128 __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) __A,
+(__v4di)
+_mm256_setzero_si256 (),
+(__mmask8) -1,
+__R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvt_roundps_epi64 (__m256i __W, __mmask8 __U, __m128 __A,
+  const int __R)
+{
+  return (__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) __A,
+ (__v4di) __W,
+ (__mmask8) __U,
+ __R);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvt_roundps_epi64 (__mmask8 __U, __m128 __A, const int __R)
+{
+  return
+(__m256i) __builtin_ia32_cvtps2qq256_mask_round ((__v4sf) __A,
+(__v4di)
+  

[PATCH 1/1] Initial support for AVX10.2

[Haochen Jiang]

gcc/ChangeLog:

* common/config/i386/cpuinfo.h (get_available_features): Handle
avx10.2.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10_2_256_SET): New.
(OPTION_MASK_ISA2_AVX10_2_512_SET): Ditto.
(OPTION_MASK_ISA2_AVX10_1_256_UNSET):
Add OPTION_MASK_ISA2_AVX10_2_256_UNSET.
(OPTION_MASK_ISA2_AVX10_1_512_UNSET):
Add OPTION_MASK_ISA2_AVX10_2_512_UNSET.
(OPTION_MASK_ISA2_AVX10_2_256_UNSET): New.
(OPTION_MASK_ISA2_AVX10_2_512_UNSET): Ditto.
(ix86_handle_option): Handle avx10.2-256 and avx10.2-512.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_AVX10_2_256 and FEATURE_AVX10_2_512.
* common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for
avx10.2-256 and avx10.2-512.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__AVX10_2_256__ and __AVX10_2_512__.
* config/i386/i386-isa.def (AVX10_2): Add DEF_PTA(AVX10_2_256)
and DEF_PTA(AVX10_2_512).
* config/i386/i386-options.cc (isa2_opts): Add -mavx10.2-256 and
-mavx10.2-512.
(ix86_valid_target_attribute_inner_p): Handle avx10.2-256 and
avx10.2-512.
* config/i386/i386.opt: Add option -mavx10.2, -mavx10.2-256 and
-mavx10.2-512.
* config/i386/i386.opt.urls: Regenerated.
* doc/extend.texi: Document avx10.2, avx10.2-256 and avx10.2-512.
* doc/invoke.texi: Document -mavx10.2, -mavx10.2-256 and
-mavx10.2-512.
* doc/sourcebuild.texi: Document target avx10.2, avx10.2-256,
avx10.2-512.

gcc/testsuite/ChangeLog:

* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/sse-12.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
---
 gcc/common/config/i386/cpuinfo.h   |  6 
 gcc/common/config/i386/i386-common.cc  | 43 --
 gcc/common/config/i386/i386-cpuinfo.h  |  2 ++
 gcc/common/config/i386/i386-isas.h |  3 ++
 gcc/config/i386/i386-c.cc  |  4 +++
 gcc/config/i386/i386-isa.def   |  2 ++
 gcc/config/i386/i386-options.cc|  7 -
 gcc/config/i386/i386.opt   | 15 +
 gcc/config/i386/i386.opt.urls  |  9 ++
 gcc/doc/extend.texi| 15 +
 gcc/doc/invoke.texi| 17 --
 gcc/doc/sourcebuild.texi   |  9 ++
 gcc/testsuite/g++.dg/other/i386-2.C|  9 +++---
 gcc/testsuite/g++.dg/other/i386-3.C|  9 +++---
 gcc/testsuite/gcc.target/i386/sse-12.c |  2 +-
 gcc/testsuite/gcc.target/i386/sse-13.c |  2 +-
 gcc/testsuite/gcc.target/i386/sse-14.c |  2 +-
 gcc/testsuite/gcc.target/i386/sse-22.c |  4 +--
 gcc/testsuite/gcc.target/i386/sse-23.c |  2 +-
 19 files changed, 140 insertions(+), 22 deletions(-)

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 2ae77d335d2..2ae383eb6ab 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -1006,6 +1006,9 @@ get_available_features (struct __processor_model 
*cpu_model,
   if (ebx & bit_AVX10_256)
switch (version)
  {
+ case 2:
+   set_feature (FEATURE_AVX10_2_256);
+   /* Fall through.  */
  case 1:
set_feature (FEATURE_AVX10_1_256);
break;
@@ -1016,6 +1019,9 @@ get_available_features (struct __processor_model 
*cpu_model,
   if (ebx & bit_AVX10_512)
switch (version)
  {
+ case 2:
+   set_feature (FEATURE_AVX10_2_512);
+   /* Fall through.  */
  case 1:
set_feature (FEATURE_AVX10_1_512);
break;
diff --git a/gcc/common/config/i386/i386-common.cc 
b/gcc/common/config/i386/i386-common.cc
index e38b1b22ffb..fb744319b05 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -122,6 +122,11 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256
 #define OPTION_MASK_ISA2_AVX10_1_512_SET \
   (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512)
+#define OPTION_MASK_ISA2_AVX10_2_256_SET \
+  (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_2_256)
+#define OPTION_MASK_ISA2_AVX10_2_512_SET \
+  (OPTION_MASK_ISA2_AVX10_1_512_SET | OPTION_MASK_ISA2_AVX10_2_256_SET \
+   | OPTION_MASK_ISA2_AVX10_2_512)
 
 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2.  */
@@ -307,8 +312,12 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
 #define OPTION_MASK_ISA2_AVX10_1_256_UNSET \
-  (OPTION_MASK_ISA2_AVX10_1_256 | OPTI

[PATCH 0/1] Initial support for AVX10.2

[Haochen Jiang]

Hi all,

AVX10.2 tech details has been just published on July 31st in the
following link:

https://cdrdv2.intel.com/v1/dl/getContent/828965

For new features and instructions, we could divide them into two parts.
One is ymm rounding control, the other is the new instructions.

In the following weeks, we plan to upstream ymm rounding part first,
following by new instructions. After all of them upstreamed, we will
also upstream several patches optimizing codegen with new AVX10.2
instructions.

The patch coming next is the initial support for AVX10.2. This patch
will be the foundation of all our patches. It adds the support for
cpuid, option, target attribute, etc.

Bootstrapped on x86-64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

[GCC12/13 PATCH] i386: Use _mm_setzero_ps/d instead of _mm_avx512_setzero_ps/d for GCC13/12

[Haochen Jiang]

Hi all,

In GCC13/12, there is no _mm_avx512_setzero_ps/d since it is introduced
in GCC14.

Fix the backport issue as obvious in:
https://gcc.gnu.org/pipermail/gcc-regression/2024-July/080385.html

Thx,
Haochen

gcc/ChangeLog:

* config/i386/avx512dqintrin.h (_mm_reduce_round_sd): Use
_mm_setzero_pd instead of _mm_avx512_setzero_pd.
(_mm_reduce_round_ss): Use _mm_setzero_ps instead of
_mm_avx512_setzero_ps.
---
 gcc/config/i386/avx512dqintrin.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h
index 4383ff14670..82f4acc7d2e 100644
--- a/gcc/config/i386/avx512dqintrin.h
+++ b/gcc/config/i386/avx512dqintrin.h
@@ -2840,7 +2840,7 @@ _mm512_fpclass_ps_mask (__m512 __A, const int __imm)
 
 #define _mm_reduce_round_sd(A, B, C, R)   \
   ((__m128d) __builtin_ia32_reducesd_mask_round ((__v2df)(__m128d)(A), \
-(__v2df)(__m128d)(B), (int)(C), (__v2df) _mm_avx512_setzero_pd (), \
+(__v2df)(__m128d)(B), (int)(C), (__v2df) _mm_setzero_pd (),   \
 (__mmask8)(-1), (int)(R)))
 
 #define _mm_mask_reduce_round_sd(W, U, A, B, C, R)\
@@ -2869,7 +2869,7 @@ _mm512_fpclass_ps_mask (__m512 __A, const int __imm)
 
 #define _mm_reduce_round_ss(A, B, C, R)   \
   ((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A),   \
-(__v4sf)(__m128)(B), (int)(C), (__v4sf) _mm_avx512_setzero_ps (),  \
+(__v4sf)(__m128)(B), (int)(C), (__v4sf) _mm_setzero_ps (),\
 (__mmask8)(-1), (int)(R)))
 
 #define _mm_mask_reduce_round_ss(W, U, A, B, C, R)\
-- 
2.31.1

[PATCH v2] i386: Add non-optimize prefetchi intrins

[Haochen Jiang]

Hi all,

I added related O0 testcase in this patch.

Ok for trunk and backport to GCC 14 and GCC 13?

Thx,
Haochen

---

Changes in v2: Add testcases.

---

Under -O0, with the "newly" introduced intrins, the variable will be
transformed as mem instead of the origin symbol_ref. The compiler will
then treat the operand as invalid and turn the operation into nop, which
is not expected. Use macro for non-optimize to keep the variable as
symbol_ref just as how prefetch intrin does.

gcc/ChangeLog:

* config/i386/prfchiintrin.h
(_m_prefetchit0): Add macro for non-optimized option.
(_m_prefetchit1): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/prefetchi-1b.c: New test.
---
 gcc/config/i386/prfchiintrin.h   |  9 +++
 gcc/testsuite/gcc.target/i386/prefetchi-1b.c | 26 
 2 files changed, 35 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/prefetchi-1b.c

diff --git a/gcc/config/i386/prfchiintrin.h b/gcc/config/i386/prfchiintrin.h
index dfca89c7d16..d6580e504c0 100644
--- a/gcc/config/i386/prfchiintrin.h
+++ b/gcc/config/i386/prfchiintrin.h
@@ -37,6 +37,7 @@
 #define __DISABLE_PREFETCHI__
 #endif /* __PREFETCHI__ */
 
+#ifdef __OPTIMIZE__
 extern __inline void
 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _m_prefetchit0 (void* __P)
@@ -50,6 +51,14 @@ _m_prefetchit1 (void* __P)
 {
   __builtin_ia32_prefetchi (__P, 2);
 }
+#else
+#define _m_prefetchit0(P)  \
+  __builtin_ia32_prefetchi(P, 3);
+
+#define _m_prefetchit1(P)  \
+  __builtin_ia32_prefetchi(P, 2);
+
+#endif
 
 #ifdef __DISABLE_PREFETCHI__
 #undef __DISABLE_PREFETCHI__
diff --git a/gcc/testsuite/gcc.target/i386/prefetchi-1b.c 
b/gcc/testsuite/gcc.target/i386/prefetchi-1b.c
new file mode 100644
index 000..93139554d3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/prefetchi-1b.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mprefetchi -O0" } */
+/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit0\[ 
\\t\]+bar\\(%rip\\)" 1 } } */
+/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit1\[ 
\\t\]+bar\\(%rip\\)" 1 } } */
+
+#include 
+
+int
+bar (int a)
+{
+  return a + 1;
+}
+
+int
+foo1 (int b)
+{
+  _m_prefetchit0 (bar);
+  return bar (b) + 1;
+}
+
+int
+foo2 (int b)
+{
+  _m_prefetchit1 (bar);
+  return bar (b) + 1;
+}
-- 
2.31.1

[PATCH v2] i386: Fix AVX512 intrin macro typo

[Haochen Jiang]

Hi all,

I have added related testcases into the patch.

Ok for trunk and backport to GCC 14, GCC 13 and GCC 12?


Thx,
Haochen

---

Changes in v2: Add related testcases

---

There are several typo in AVX512 intrins macro define. Correct them to solve
errors when compiled with -O0.

gcc/ChangeLog:

* config/i386/avx512dqintrin.h
(_mm_mask_fpclass_ss_mask): Correct operand order.
(_mm_mask_fpclass_sd_mask): Ditto.
(_mm_reduce_round_sd): Use -1 as mask since it is non-mask.
(_mm_reduce_round_ss): Ditto.
* config/i386/avx512vlbwintrin.h
(_mm256_mask_alignr_epi8): Correct operand usage.
(_mm_mask_alignr_epi8): Ditto.
* config/i386/avx512vlintrin.h (_mm_mask_alignr_epi64): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512bw-vpalignr-1b.c: New test.
* gcc.target/i386/avx512dq-vfpclasssd-1b.c: Ditto.
* gcc.target/i386/avx512dq-vfpcla-1b.c: Ditto.
* gcc.target/i386/avx512dq-vreducesd-1b.c: Ditto.
* gcc.target/i386/avx512dq-vreducess-1b.c: Ditto.
* gcc.target/i386/avx512vl-valignq-1b.c: Ditto.
---
 gcc/config/i386/avx512dqintrin.h   | 16 +---
 gcc/config/i386/avx512vlbwintrin.h |  4 ++--
 gcc/config/i386/avx512vlintrin.h   |  2 +-
 .../gcc.target/i386/avx512bw-vpalignr-1b.c | 18 ++
 .../gcc.target/i386/avx512dq-vfpclasssd-1b.c   | 14 ++
 .../gcc.target/i386/avx512dq-vfpcla-1b.c   | 14 ++
 .../gcc.target/i386/avx512dq-vreducesd-1b.c| 16 
 .../gcc.target/i386/avx512dq-vreducess-1b.c| 16 
 .../gcc.target/i386/avx512vl-valignq-1b.c  | 15 +++
 9 files changed, 105 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-1b.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1b.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx512dq-vfpcla-1b.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx512dq-vreducesd-1b.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx512dq-vreducess-1b.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-valignq-1b.c

diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h
index 3beed7e649a..d9890c6da1d 100644
--- a/gcc/config/i386/avx512dqintrin.h
+++ b/gcc/config/i386/avx512dqintrin.h
@@ -572,11 +572,11 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, 
const int __imm)
   ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X),   \
 (int) (C), (__mmask8) (-1))) \
 
-#define _mm_mask_fpclass_ss_mask(X, C, U)  \
+#define _mm_mask_fpclass_ss_mask(U, X, C)  \
   ((__mmask8) __builtin_ia32_fpcla_mask ((__v4sf) (__m128) (X),\
 (int) (C), (__mmask8) (U)))
 
-#define _mm_mask_fpclass_sd_mask(X, C, U)  \
+#define _mm_mask_fpclass_sd_mask(U, X, C)  \
   ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X),   \
 (int) (C), (__mmask8) (U)))
 #define _mm_reduce_sd(A, B, C) \
@@ -594,8 +594,9 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const 
int __imm)
 (__mmask8)(U)))
 
 #define _mm_reduce_round_sd(A, B, C, R)   \
-  ((__m128d) __builtin_ia32_reducesd_round ((__v2df)(__m128d)(A),  \
-(__v2df)(__m128d)(B), (int)(C), (__mmask8)(U), (int)(R)))
+  ((__m128d) __builtin_ia32_reducesd_mask_round ((__v2df)(__m128d)(A), \
+(__v2df)(__m128d)(B), (int)(C), (__v2df) _mm_avx512_setzero_pd (), \
+(__mmask8)(-1), (int)(R)))
 
 #define _mm_mask_reduce_round_sd(W, U, A, B, C, R)\
   ((__m128d) __builtin_ia32_reducesd_mask_round ((__v2df)(__m128d)(A), \
@@ -622,8 +623,9 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const 
int __imm)
 (__mmask8)(U)))
 
 #define _mm_reduce_round_ss(A, B, C, R)   \
-  ((__m128) __builtin_ia32_reducess_round ((__v4sf)(__m128)(A),   \
-(__v4sf)(__m128)(B), (int)(C), (__mmask8)(U), (int)(R)))
+  ((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A),   \
+(__v4sf)(__m128)(B), (int)(C), (__v4sf) _mm_avx512_setzero_ps (),  \
+(__mmask8)(-1), (int)(R)))
 
 #define _mm_mask_reduce_round_ss(W, U, A, B, C, R)\
   ((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A),   \
@@ -631,7 +633,7 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const 
int __imm)
 (__mmask8)(U), (int)(R)))
 
 #define _mm_maskz_reduce_round_ss(U, A, B, C, R)  \
-  ((__m128) __builtin_ia32_reducesd_mask_round ((__v4sf)(__m128)(A),   \
+  ((__m128) __builtin_ia32_reducess_mask_round ((__v4s

[PATCH] i386: Add non-optimize prefetchi intrins

[Haochen Jiang]

Hi all,

Under -O0, with the "newly" introduced intrins, the variable will be
transformed as mem instead of the origin symbol_ref. The compiler will
then treat the operand as invalid and turn the operation into nop, which
is not expected. Use macro for non-optimize to keep the variable as
symbol_ref just as how prefetch intrin does.

Bootstrapped and regtested on x86-64-pc-linux-gnu. Ok for trunk and backport
to GCC 14 and GCC 13?

Thx,
Haochen

---
 gcc/config/i386/prfchiintrin.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/gcc/config/i386/prfchiintrin.h b/gcc/config/i386/prfchiintrin.h
index dfca89c7d16..d6580e504c0 100644
--- a/gcc/config/i386/prfchiintrin.h
+++ b/gcc/config/i386/prfchiintrin.h
@@ -37,6 +37,7 @@
 #define __DISABLE_PREFETCHI__
 #endif /* __PREFETCHI__ */
 
+#ifdef __OPTIMIZE__
 extern __inline void
 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _m_prefetchit0 (void* __P)
@@ -50,6 +51,14 @@ _m_prefetchit1 (void* __P)
 {
   __builtin_ia32_prefetchi (__P, 2);
 }
+#else
+#define _m_prefetchit0(P)  \
+  __builtin_ia32_prefetchi(P, 3);
+
+#define _m_prefetchit1(P)  \
+  __builtin_ia32_prefetchi(P, 2);
+
+#endif
 
 #ifdef __DISABLE_PREFETCHI__
 #undef __DISABLE_PREFETCHI__
-- 
2.31.1

[PATCH] i386: Fix AVX512 intrin macro typo

[Haochen Jiang]

Hi all,

There are several typo in AVX512 intrins macro define. They will eventually
result in errors with -O0. This patch will fix that.

Bootstrapped on x86-64-pc-linux-gnu. Ok for trunk and backport to GCC14,
GCC 13 and GCC 12?

Thx,
Haochen

gcc/ChangeLog:

* config/i386/avx512dqintrin.h
(_mm_mask_fpclass_ss_mask): Correct operand order.
(_mm_mask_fpclass_sd_mask): Ditto.
(_mm_reduce_round_sd): Use -1 as mask since it is non-mask.
(_mm_reduce_round_ss): Ditto.
* config/i386/avx512vlbwintrin.h
(_mm256_mask_alignr_epi8): Correct operand usage.
(_mm_mask_alignr_epi8): Ditto.
* config/i386/avx512vlintrin.h (_mm_mask_alignr_epi64): Ditto.
---
 gcc/config/i386/avx512dqintrin.h   | 16 +---
 gcc/config/i386/avx512vlbwintrin.h |  4 ++--
 gcc/config/i386/avx512vlintrin.h   |  2 +-
 3 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h
index 3beed7e649a..d9890c6da1d 100644
--- a/gcc/config/i386/avx512dqintrin.h
+++ b/gcc/config/i386/avx512dqintrin.h
@@ -572,11 +572,11 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, 
const int __imm)
   ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X),   \
 (int) (C), (__mmask8) (-1))) \
 
-#define _mm_mask_fpclass_ss_mask(X, C, U)  \
+#define _mm_mask_fpclass_ss_mask(U, X, C)  \
   ((__mmask8) __builtin_ia32_fpcla_mask ((__v4sf) (__m128) (X),\
 (int) (C), (__mmask8) (U)))
 
-#define _mm_mask_fpclass_sd_mask(X, C, U)  \
+#define _mm_mask_fpclass_sd_mask(U, X, C)  \
   ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X),   \
 (int) (C), (__mmask8) (U)))
 #define _mm_reduce_sd(A, B, C) \
@@ -594,8 +594,9 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const 
int __imm)
 (__mmask8)(U)))
 
 #define _mm_reduce_round_sd(A, B, C, R)   \
-  ((__m128d) __builtin_ia32_reducesd_round ((__v2df)(__m128d)(A),  \
-(__v2df)(__m128d)(B), (int)(C), (__mmask8)(U), (int)(R)))
+  ((__m128d) __builtin_ia32_reducesd_mask_round ((__v2df)(__m128d)(A), \
+(__v2df)(__m128d)(B), (int)(C), (__v2df) _mm_avx512_setzero_pd (), \
+(__mmask8)(-1), (int)(R)))
 
 #define _mm_mask_reduce_round_sd(W, U, A, B, C, R)\
   ((__m128d) __builtin_ia32_reducesd_mask_round ((__v2df)(__m128d)(A), \
@@ -622,8 +623,9 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const 
int __imm)
 (__mmask8)(U)))
 
 #define _mm_reduce_round_ss(A, B, C, R)   \
-  ((__m128) __builtin_ia32_reducess_round ((__v4sf)(__m128)(A),   \
-(__v4sf)(__m128)(B), (int)(C), (__mmask8)(U), (int)(R)))
+  ((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A),   \
+(__v4sf)(__m128)(B), (int)(C), (__v4sf) _mm_avx512_setzero_ps (),  \
+(__mmask8)(-1), (int)(R)))
 
 #define _mm_mask_reduce_round_ss(W, U, A, B, C, R)\
   ((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A),   \
@@ -631,7 +633,7 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const 
int __imm)
 (__mmask8)(U), (int)(R)))
 
 #define _mm_maskz_reduce_round_ss(U, A, B, C, R)  \
-  ((__m128) __builtin_ia32_reducesd_mask_round ((__v4sf)(__m128)(A),   \
+  ((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A),   \
 (__v4sf)(__m128)(B), (int)(C), (__v4sf) _mm_avx512_setzero_ps (), \
 (__mmask8)(U), (int)(R)))
 
diff --git a/gcc/config/i386/avx512vlbwintrin.h 
b/gcc/config/i386/avx512vlbwintrin.h
index 56740054aa1..98b9099e343 100644
--- a/gcc/config/i386/avx512vlbwintrin.h
+++ b/gcc/config/i386/avx512vlbwintrin.h
@@ -2089,7 +2089,7 @@ _mm_maskz_slli_epi16 (__mmask8 __U, __m128i __A, unsigned 
int __B)
 #define _mm256_mask_alignr_epi8(W, U, X, Y, N) 
\
   ((__m256i) __builtin_ia32_palignr256_mask ((__v4di)(__m256i)(X), 
\
(__v4di)(__m256i)(Y), (int)((N) * 
8),   \
-   (__v4di)(__m256i)(X), 
(__mmask32)(U)))
+   (__v4di)(__m256i)(W), 
(__mmask32)(U)))
 
 #define _mm256_mask_srli_epi16(W, U, A, B)  \
   ((__m256i) __builtin_ia32_psrlwi256_mask ((__v16hi)(__m256i)(A),  \
@@ -2172,7 +2172,7 @@ _mm_maskz_slli_epi16 (__mmask8 __U, __m128i __A, unsigned 
int __B)
 #define _mm_mask_alignr_epi8(W, U, X, Y, N)
\
   ((__m128i) __builtin_ia32_palignr128_mask ((__v2di)(__m128i)(X), 
\

[PATCH v2] i386: Change prefetchi output template

[Haochen Jiang]

Hi all,

I tested with %a and it works. Therefore I suppose it is a better solution.

Bootstrapped and regtested on x86-64-pc-linux-gnu. Ok for trunk and backport
to GCC 13 and 14?

Thx,
Haochen

---

Changes in v2: Use %a in pattern

---

For prefetchi instructions, RIP-relative address is explicitly mentioned
for operand and assembler obeys that rule strictly. This makes
instruction like:

prefetchit0 bar

got illegal for assembler, which should be a broad usage for prefetchi.

Change to %a to explicitly add (%rip) after function label to make it
legal in assembler so that it could pass to linker to get the real address.

gcc/ChangeLog:

* config/i386/i386.md (prefetchi): Change to %a.

gcc/testsuite/ChangeLog:

* gcc.target/i386/prefetchi-1.c: Check (%rip).
---
 gcc/config/i386/i386.md | 2 +-
 gcc/testsuite/gcc.target/i386/prefetchi-1.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 90d3aa450f0..6207036a2a0 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -28004,7 +28004,7 @@
   "TARGET_PREFETCHI && TARGET_64BIT"
 {
   static const char * const patterns[2] = {
-"prefetchit1\t%0", "prefetchit0\t%0"
+"prefetchit1\t%a0", "prefetchit0\t%a0"
   };
 
   int locality = INTVAL (operands[1]);
diff --git a/gcc/testsuite/gcc.target/i386/prefetchi-1.c 
b/gcc/testsuite/gcc.target/i386/prefetchi-1.c
index 80f25e70e8e..03dfdc55e86 100644
--- a/gcc/testsuite/gcc.target/i386/prefetchi-1.c
+++ b/gcc/testsuite/gcc.target/i386/prefetchi-1.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { ! ia32 } } } */
 /* { dg-options "-mprefetchi -O2" } */
-/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit0\[ \\t\]+" 2 } } */
-/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit1\[ \\t\]+" 2 } } */
+/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit0\[ 
\\t\]+bar\\(%rip\\)" 2 } } */
+/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit1\[ 
\\t\]+bar\\(%rip\\)" 2 } } */
 
 #include 
 
-- 
2.31.1

[PATCH] i386: Change prefetchi output template

[Haochen Jiang]

Hi all,

For prefetchi instructions, RIP-relative address is explicitly mentioned
for operand and assembler obeys that rule strictly. This makes
instruction like:

prefetchit0 bar

got illegal for assembler, which should be a broad usage for prefetchi.

Explicitly add (%rip) after function label to make it legal in
assembler so that it could pass to linker to get the real address.

Ok for trunk and backport to GCC14 and GCC13 since prefetchi instructions
are introduced in GCC13?

Thx,
Haochen

gcc/ChangeLog:

* config/i386/i386.md (prefetchi): Add explicit (%rip) after
function label.

gcc/testsuite/ChangeLog:

* gcc.target/i386/prefetchi-1.c: Check (%rip).
---
 gcc/config/i386/i386.md | 2 +-
 gcc/testsuite/gcc.target/i386/prefetchi-1.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 90d3aa450f0..3ec51bad6fe 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -28004,7 +28004,7 @@
   "TARGET_PREFETCHI && TARGET_64BIT"
 {
   static const char * const patterns[2] = {
-"prefetchit1\t%0", "prefetchit0\t%0"
+"prefetchit1\t{%p0(%%rip)|%p0[rip]}", "prefetchit0\t{%p0(%%rip)|%p0[rip]}"
   };
 
   int locality = INTVAL (operands[1]);
diff --git a/gcc/testsuite/gcc.target/i386/prefetchi-1.c 
b/gcc/testsuite/gcc.target/i386/prefetchi-1.c
index 80f25e70e8e..03dfdc55e86 100644
--- a/gcc/testsuite/gcc.target/i386/prefetchi-1.c
+++ b/gcc/testsuite/gcc.target/i386/prefetchi-1.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { ! ia32 } } } */
 /* { dg-options "-mprefetchi -O2" } */
-/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit0\[ \\t\]+" 2 } } */
-/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit1\[ \\t\]+" 2 } } */
+/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit0\[ 
\\t\]+bar\\(%rip\\)" 2 } } */
+/* { dg-final { scan-assembler-times "\[ \\t\]+prefetchit1\[ 
\\t\]+bar\\(%rip\\)" 2 } } */
 
 #include 
 
-- 
2.31.1

[PATCH v2] i386: Fix testcases generating invalid asm

[Haochen Jiang]

Hi all,

I revised the patch according to the comment.

Ok for trunk?

Thx,
Haochen

---

Changes in v2: Add suffix for mov to make the test more robust.

---

For compile test, we should generate valid asm except for special purposes.
Fix the compile test that generates invalid asm.

gcc/testsuite/ChangeLog:

* gcc.target/i386/apx-egprs-names.c: Use ax for short and
al for char instead of eax.
* gcc.target/i386/avx512bw-kandnq-1.c: Do not run the test
under -m32 since kmovq with register is invalid. Use long
long to use 64 bit register instead of 32 bit register for
kmovq.
* gcc.target/i386/avx512bw-kandq-1.c: Ditto.
* gcc.target/i386/avx512bw-knotq-1.c: Ditto.
* gcc.target/i386/avx512bw-korq-1.c: Ditto.
* gcc.target/i386/avx512bw-kshiftlq-1.c: Ditto.
* gcc.target/i386/avx512bw-kshiftrq-1.c: Ditto.
* gcc.target/i386/avx512bw-kxnorq-1.c: Ditto.
* gcc.target/i386/avx512bw-kxorq-1.c: Ditto.
---
 gcc/testsuite/gcc.target/i386/apx-egprs-names.c | 8 
 gcc/testsuite/gcc.target/i386/avx512bw-kandnq-1.c   | 6 +++---
 gcc/testsuite/gcc.target/i386/avx512bw-kandq-1.c| 6 +++---
 gcc/testsuite/gcc.target/i386/avx512bw-knotq-1.c| 4 ++--
 gcc/testsuite/gcc.target/i386/avx512bw-korq-1.c | 6 +++---
 gcc/testsuite/gcc.target/i386/avx512bw-kshiftlq-1.c | 4 ++--
 gcc/testsuite/gcc.target/i386/avx512bw-kshiftrq-1.c | 4 ++--
 gcc/testsuite/gcc.target/i386/avx512bw-kxnorq-1.c   | 6 +++---
 gcc/testsuite/gcc.target/i386/avx512bw-kxorq-1.c| 6 +++---
 9 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/apx-egprs-names.c 
b/gcc/testsuite/gcc.target/i386/apx-egprs-names.c
index f0517e47c33..917ef505495 100644
--- a/gcc/testsuite/gcc.target/i386/apx-egprs-names.c
+++ b/gcc/testsuite/gcc.target/i386/apx-egprs-names.c
@@ -10,8 +10,8 @@ void foo ()
   register int b __asm ("r30");
   register short c __asm ("r29");
   register char d __asm ("r28");
-  __asm__ __volatile__ ("mov %0, %%rax" : : "r" (a) : "rax");
-  __asm__ __volatile__ ("mov %0, %%eax" : : "r" (b) : "eax");
-  __asm__ __volatile__ ("mov %0, %%eax" : : "r" (c) : "eax");
-  __asm__ __volatile__ ("mov %0, %%eax" : : "r" (d) : "eax");
+  __asm__ __volatile__ ("movq %0, %%rax" : : "r" (a) : "rax");
+  __asm__ __volatile__ ("movl %0, %%eax" : : "r" (b) : "eax");
+  __asm__ __volatile__ ("movw %0, %%ax" : : "r" (c) : "ax");
+  __asm__ __volatile__ ("movb %0, %%al" : : "r" (d) : "al");
 }
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-kandnq-1.c 
b/gcc/testsuite/gcc.target/i386/avx512bw-kandnq-1.c
index e8b7a5f9aa2..f9f03c90782 100644
--- a/gcc/testsuite/gcc.target/i386/avx512bw-kandnq-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-kandnq-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! ia32 } } } */
 /* { dg-options "-mavx512bw -O2" } */
 /* { dg-final { scan-assembler-times "kandnq\[ 
\\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
 
@@ -10,8 +10,8 @@ avx512bw_test ()
   __mmask64 k1, k2, k3;
   volatile __m512i x = _mm512_setzero_si512 ();
 
-  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (1) );
-  __asm__( "kmovq %1, %0" : "=k" (k2) : "r" (2) );
+  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (1ULL) );
+  __asm__( "kmovq %1, %0" : "=k" (k2) : "r" (2ULL) );
 
   k3 = _kandn_mask64 (k1, k2);
   x = _mm512_mask_add_epi8 (x, k3, x, x);
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-kandq-1.c 
b/gcc/testsuite/gcc.target/i386/avx512bw-kandq-1.c
index a1aaed67c66..6ad836087ad 100644
--- a/gcc/testsuite/gcc.target/i386/avx512bw-kandq-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-kandq-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! ia32 } } } */
 /* { dg-options "-mavx512bw -O2" } */
 /* { dg-final { scan-assembler-times "kandq\[ 
\\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
 
@@ -10,8 +10,8 @@ avx512bw_test ()
   __mmask64 k1, k2, k3;
   volatile __m512i x = _mm512_setzero_epi32();
 
-  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (1) );
-  __asm__( "kmovq %1, %0" : "=k" (k2) : "r" (2) );
+  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (1ULL) );
+  __asm__( "kmovq %1, %0" : "=k" (k2) : "r" (2ULL) );
 
   k3 = _kand_mask64 (k1, k2);
   x = _mm512_mask_add_epi8 (x, k3, x, x);
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-knotq-1.c 
b/gcc/testsuite/gcc.target/i386/avx512bw-knotq-1.c
index deb65795760..341bbc03847 100644
--- a/gcc/testsuite/gcc.target/i386/avx512bw-knotq-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-knotq-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! ia32 } } } */
 /* { dg-options "-mavx512bw -O2" } */
 /* { dg-final { scan-assembler-times "knotq\[ 
\\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
 
@@ -10,7 +10,7 @@ avx512bw_test ()
   __mmask64 k1, k2;
   volatile __m512i x = _mm512_setzero_si512 ();
 
-  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (45) );
+  __asm__( "kmovq %1, %

[PATCH] i386: Fix testcases generating invalid asm

[Haochen Jiang]

Hi all,

For compile test, we should generate valid asm except for special purposes.
Fix the compile test that generates invalid asm.

Regtested on x86-64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

gcc/testsuite/ChangeLog:

* gcc.target/i386/apx-egprs-names.c: Use ax for short and
al for char instead of eax.
* gcc.target/i386/avx512bw-kandnq-1.c: Do not run the test
under -m32 since kmovq with register is invalid. Use long
long to use 64 bit register instead of 32 bit register for
kmovq.
* gcc.target/i386/avx512bw-kandq-1.c: Ditto.
* gcc.target/i386/avx512bw-knotq-1.c: Ditto.
* gcc.target/i386/avx512bw-korq-1.c: Ditto.
* gcc.target/i386/avx512bw-kshiftlq-1.c: Ditto.
* gcc.target/i386/avx512bw-kshiftrq-1.c: Ditto.
* gcc.target/i386/avx512bw-kxnorq-1.c: Ditto.
* gcc.target/i386/avx512bw-kxorq-1.c: Ditto.
---
 gcc/testsuite/gcc.target/i386/apx-egprs-names.c | 4 ++--
 gcc/testsuite/gcc.target/i386/avx512bw-kandnq-1.c   | 6 +++---
 gcc/testsuite/gcc.target/i386/avx512bw-kandq-1.c| 6 +++---
 gcc/testsuite/gcc.target/i386/avx512bw-knotq-1.c| 4 ++--
 gcc/testsuite/gcc.target/i386/avx512bw-korq-1.c | 6 +++---
 gcc/testsuite/gcc.target/i386/avx512bw-kshiftlq-1.c | 4 ++--
 gcc/testsuite/gcc.target/i386/avx512bw-kshiftrq-1.c | 4 ++--
 gcc/testsuite/gcc.target/i386/avx512bw-kxnorq-1.c   | 6 +++---
 gcc/testsuite/gcc.target/i386/avx512bw-kxorq-1.c| 6 +++---
 9 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/apx-egprs-names.c 
b/gcc/testsuite/gcc.target/i386/apx-egprs-names.c
index f0517e47c33..5b342aa385b 100644
--- a/gcc/testsuite/gcc.target/i386/apx-egprs-names.c
+++ b/gcc/testsuite/gcc.target/i386/apx-egprs-names.c
@@ -12,6 +12,6 @@ void foo ()
   register char d __asm ("r28");
   __asm__ __volatile__ ("mov %0, %%rax" : : "r" (a) : "rax");
   __asm__ __volatile__ ("mov %0, %%eax" : : "r" (b) : "eax");
-  __asm__ __volatile__ ("mov %0, %%eax" : : "r" (c) : "eax");
-  __asm__ __volatile__ ("mov %0, %%eax" : : "r" (d) : "eax");
+  __asm__ __volatile__ ("mov %0, %%ax" : : "r" (c) : "ax");
+  __asm__ __volatile__ ("mov %0, %%al" : : "r" (d) : "al");
 }
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-kandnq-1.c 
b/gcc/testsuite/gcc.target/i386/avx512bw-kandnq-1.c
index e8b7a5f9aa2..f9f03c90782 100644
--- a/gcc/testsuite/gcc.target/i386/avx512bw-kandnq-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-kandnq-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! ia32 } } } */
 /* { dg-options "-mavx512bw -O2" } */
 /* { dg-final { scan-assembler-times "kandnq\[ 
\\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
 
@@ -10,8 +10,8 @@ avx512bw_test ()
   __mmask64 k1, k2, k3;
   volatile __m512i x = _mm512_setzero_si512 ();
 
-  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (1) );
-  __asm__( "kmovq %1, %0" : "=k" (k2) : "r" (2) );
+  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (1ULL) );
+  __asm__( "kmovq %1, %0" : "=k" (k2) : "r" (2ULL) );
 
   k3 = _kandn_mask64 (k1, k2);
   x = _mm512_mask_add_epi8 (x, k3, x, x);
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-kandq-1.c 
b/gcc/testsuite/gcc.target/i386/avx512bw-kandq-1.c
index a1aaed67c66..6ad836087ad 100644
--- a/gcc/testsuite/gcc.target/i386/avx512bw-kandq-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-kandq-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! ia32 } } } */
 /* { dg-options "-mavx512bw -O2" } */
 /* { dg-final { scan-assembler-times "kandq\[ 
\\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
 
@@ -10,8 +10,8 @@ avx512bw_test ()
   __mmask64 k1, k2, k3;
   volatile __m512i x = _mm512_setzero_epi32();
 
-  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (1) );
-  __asm__( "kmovq %1, %0" : "=k" (k2) : "r" (2) );
+  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (1ULL) );
+  __asm__( "kmovq %1, %0" : "=k" (k2) : "r" (2ULL) );
 
   k3 = _kand_mask64 (k1, k2);
   x = _mm512_mask_add_epi8 (x, k3, x, x);
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-knotq-1.c 
b/gcc/testsuite/gcc.target/i386/avx512bw-knotq-1.c
index deb65795760..341bbc03847 100644
--- a/gcc/testsuite/gcc.target/i386/avx512bw-knotq-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-knotq-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! ia32 } } } */
 /* { dg-options "-mavx512bw -O2" } */
 /* { dg-final { scan-assembler-times "knotq\[ 
\\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
 
@@ -10,7 +10,7 @@ avx512bw_test ()
   __mmask64 k1, k2;
   volatile __m512i x = _mm512_setzero_si512 ();
 
-  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (45) );
+  __asm__( "kmovq %1, %0" : "=k" (k1) : "r" (45ULL) );
 
   k2 = _knot_mask64 (k1);
   x = _mm512_mask_add_epi8 (x, k1, x, x);
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-korq-1.c 
b/gcc/testsuite/gcc.target/i386/avx512bw-korq-1.c
index 89753f02340..6e211491224 100644
--- a/gcc/testsuite/gcc.target/i386/

[PATCH] i386: Use BLKmode for {ld,st}tilecfg

[Haochen Jiang]

Hi all,

For AMX instructions related with memory, we will treat the memory
size as not specified since there won't be different size causing
confusion for memory.

This will change the output under Intel mode, which is broken for now when
using with assembler and aligns to current binutils behavior.

Bootstrapped and regtested on x86-64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

gcc/ChangeLog:

* config/i386/i386-expand.cc (ix86_expand_builtin): Change
from XImode to BLKmode.
* config/i386/i386.md (ldtilecfg): Change XI to BLK.
(sttilecfg): Ditto.
---
 gcc/config/i386/i386-expand.cc |  2 +-
 gcc/config/i386/i386.md| 12 +---
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 9a31e6df2aa..d9ad06264aa 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -14198,7 +14198,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx 
subtarget,
  op0 = convert_memory_address (Pmode, op0);
  op0 = copy_addr_to_reg (op0);
}
-  op0 = gen_rtx_MEM (XImode, op0);
+  op0 = gen_rtx_MEM (BLKmode, op0);
   if (fcode == IX86_BUILTIN_LDTILECFG)
icode = CODE_FOR_ldtilecfg;
   else
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index de9f4ba0496..86989d4875a 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -28975,24 +28975,22 @@
(set_attr "type" "other")])
 
 (define_insn "ldtilecfg"
-  [(unspec_volatile [(match_operand:XI 0 "memory_operand" "m")]
+  [(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")]
 UNSPECV_LDTILECFG)]
   "TARGET_AMX_TILE"
   "ldtilecfg\t%0"
   [(set_attr "type" "other")
(set_attr "prefix" "maybe_evex")
-   (set_attr "memory" "load")
-   (set_attr "mode" "XI")])
+   (set_attr "memory" "load")])
 
 (define_insn "sttilecfg"
-  [(set (match_operand:XI 0 "memory_operand" "=m")
-(unspec_volatile:XI [(const_int 0)] UNSPECV_STTILECFG))]
+  [(set (match_operand:BLK 0 "memory_operand" "=m")
+(unspec_volatile:BLK [(const_int 0)] UNSPECV_STTILECFG))]
   "TARGET_AMX_TILE"
   "sttilecfg\t%0"
   [(set_attr "type" "other")
(set_attr "prefix" "maybe_evex")
-   (set_attr "memory" "store")
-   (set_attr "mode" "XI")])
+   (set_attr "memory" "store")])
 
 (include "mmx.md")
 (include "sse.md")
-- 
2.31.1

[PATCH] i386: Correct AVX10 CPUID emulation

[Haochen Jiang]

Hi all,

AVX10 Documentaion has specified ecx value as 0 for AVX10 version and
vector size under 0x24 subleaf. Although for ecx=1, the bits are all
reserved for now, we still need to specify ecx as 0 to avoid dirty
value in ecx.

Bootstrapped on x86-64-pc-linux-gnu. Ok for trunk and backport to GCC14?

Reference:

Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification

https://cdrdv2.intel.com/v1/dl/getContent/784267

It describes the Intel Advanced Vector Extensions 10 Instruction Set 
Architecture.

Thx,
Haochen

gcc/ChangeLog:

* common/config/i386/cpuinfo.h (get_available_features): Correct
AVX10 CPUID emulation to specify ecx value.
---
 gcc/common/config/i386/cpuinfo.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 936039725ab..2ae77d335d2 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -998,10 +998,10 @@ get_available_features (struct __processor_model 
*cpu_model,
}
 }
 
-  /* Get Advanced Features at level 0x24 (eax = 0x24).  */
+  /* Get Advanced Features at level 0x24 (eax = 0x24, ecx = 0).  */
   if (avx10_set && max_cpuid_level >= 0x24)
 {
-  __cpuid (0x24, eax, ebx, ecx, edx);
+  __cpuid_count (0x24, 0, eax, ebx, ecx, edx);
   version = ebx & 0xff;
   if (ebx & bit_AVX10_256)
switch (version)
-- 
2.31.1

[PATCH] Add AVX10.1 target_clones support

[Haochen Jiang]

Hi all,

Since AVX10 is the first major ISA introduced after AVX-512, we propose
to add target_clones support for it.

Although AVX10.1-256 won't cover 512-bit part of AVX512F, but since
it is only for priority but not for implication, it won't be an issue.

Bootstrapped and regtested on x86_64-pc-linux-gnu. Ok for trunk and backport
to GCC14?

Thx,
hAOCHEN

gcc/ChangeLog:

* common/config/i386/i386-common.cc: Change Granite Rapids
series CPU type to P_PROC_AVX10_1_512.
* common/config/i386/i386-cpuinfo.h (enum feature_priority):
Revise comment part. Add P_AVX10_1_256, P_AVX10_1_512,
P_PROC_AVX10_1_512.
* common/config/i386/i386-isas.h: Link to avx10.1-256, avx10.1-512.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_1-25.c: New test.
* gcc.target/i386/avx10_1-26.c: Ditto.
---
 gcc/common/config/i386/i386-common.cc  | 4 ++--
 gcc/common/config/i386/i386-cpuinfo.h  | 5 -
 gcc/common/config/i386/i386-isas.h | 4 ++--
 gcc/testsuite/gcc.target/i386/avx10_1-25.c | 9 +
 gcc/testsuite/gcc.target/i386/avx10_1-26.c | 9 +
 5 files changed, 26 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-25.c
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-26.c

diff --git a/gcc/common/config/i386/i386-common.cc 
b/gcc/common/config/i386/i386-common.cc
index 77b154663bc..d578918dfb7 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -2273,10 +2273,10 @@ const pta processor_alias_table[] =
   {"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
   {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS,
-M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX512F},
+M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX10_1_512},
   {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D, CPU_HASWELL,
 PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D),
-P_PROC_AVX512F},
+P_PROC_AVX10_1_512},
   {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE,
 M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2},
   {"arrowlake-s", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
diff --git a/gcc/common/config/i386/i386-cpuinfo.h 
b/gcc/common/config/i386/i386-cpuinfo.h
index 73131657eab..be52ad2c60d 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -112,7 +112,7 @@ enum processor_subtypes
 /* Priority of i386 features, greater value is higher priority.   This is
used to decide the order in which function dispatch must happen.  For
instance, a version specialized for SSE4.2 should be checked for dispatch
-   before a version for SSE3, as SSE4.2 implies SSE3.  */
+   before a version for SSE3.  */
 enum feature_priority
 {
   P_NONE = 0,
@@ -148,6 +148,9 @@ enum feature_priority
   P_AVX512F,
   P_PROC_AVX512F,
   P_X86_64_V4,
+  P_AVX10_1_256,
+  P_AVX10_1_512,
+  P_PROC_AVX10_1_512,
   P_PROC_DYNAMIC
 };
 
diff --git a/gcc/common/config/i386/i386-isas.h 
b/gcc/common/config/i386/i386-isas.h
index d6deb9a1522..9c2179a3dd8 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -194,6 +194,6 @@ ISA_NAMES_TABLE_START
   ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf")
   ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr")
   ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1")
-  ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_NONE, 
"-mavx10.1-256")
-  ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_NONE, 
"-mavx10.1-512")
+  ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256, 
"-mavx10.1-256")
+  ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_AVX10_1_512, 
"-mavx10.1-512")
 ISA_NAMES_TABLE_END
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-25.c 
b/gcc/testsuite/gcc.target/i386/avx10_1-25.c
new file mode 100644
index 000..73f1b724560
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-25.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+
+#include 
+__attribute__((target_clones ("default","avx10.1-256")))
+__m256d foo(__m256d a, __m256d b)
+{
+  return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-26.c 
b/gcc/testsuite/gcc.target/i386/avx10_1-26.c
new file mode 100644
index 000..514ab57a406
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-26.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+
+#include 
+__attribute__((target_clones ("default","avx10.1-512")))
+__m512d foo(__m512d a, __m512d b)
+{
+  return a + b;
+}
-- 
2.31.1

[PATCH v3] i386: Disable ix86_expand_vecop_qihi2 when !TARGET_AVX512BW

[Haochen Jiang]

Hi all,

This is the v3 patch to fix PR115069. The new testcase has passed.

Changes in v3:
  - Simplify the testcase.

Changes in v2:
  - Add a testcase.
  - Change the comment for the early exit.

Thx,
Haochen

Since vpermq is really slow, we should avoid using it for permutation
when vpmovwb is not available (needs AVX512BW) for ix86_expand_vecop_qihi2
and fall back to ix86_expand_vecop_qihi.

gcc/ChangeLog:

PR target/115069
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
Do not enable the optimization when AVX512BW is not enabled.

gcc/testsuite/ChangeLog:

PR target/115069
* gcc.target/i386/pr115069.c: New.
---
 gcc/config/i386/i386-expand.cc   |  7 +++
 gcc/testsuite/gcc.target/i386/pr115069.c | 10 ++
 2 files changed, 17 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr115069.c

diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index a6132911e6a..f7939761879 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -24323,6 +24323,13 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, 
rtx op1, rtx op2)
   bool op2vec = GET_MODE_CLASS (GET_MODE (op2)) == MODE_VECTOR_INT;
   bool uns_p = code != ASHIFTRT;
 
+  /* Without VPMOVWB (provided by AVX512BW ISA), the expansion uses the
+ generic permutation to merge the data back into the right place.  This
+ permutation results in VPERMQ, which is slow, so better fall back to
+ ix86_expand_vecop_qihi.  */
+  if (!TARGET_AVX512BW)
+return false;
+
   if ((qimode == V16QImode && !TARGET_AVX2)
   || (qimode == V32QImode && (!TARGET_AVX512BW || !TARGET_EVEX512))
   /* There are no V64HImode instructions.  */
diff --git a/gcc/testsuite/gcc.target/i386/pr115069.c 
b/gcc/testsuite/gcc.target/i386/pr115069.c
new file mode 100644
index 000..7f1ff209f26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr115069.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx2" } */
+/* { dg-final { scan-assembler-not "vpermq" } } */
+
+typedef char v16qi __attribute__((vector_size(16)));
+
+v16qi foo (v16qi a, v16qi b) {
+return a * b;
+}
+
-- 
2.31.1

[PATCH v2] i386: Disable ix86_expand_vecop_qihi2 when !TARGET_AVX512BW

[Haochen Jiang]

Hi all,

This is the v2 patch to fix PR115069. The new testcase has passed.

Changes in v2:
  - Added a testcase.
  - Change the comment for the early exit.

Thx,
Haochen

Since vpermq is really slow, we should avoid using it for permutation
when vpmovwb is not available (needs AVX512BW) for ix86_expand_vecop_qihi2
and fall back to ix86_expand_vecop_qihi.

gcc/ChangeLog:

PR target/115069
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
Do not enable the optimization when AVX512BW is not enabled.

gcc/testsuite/ChangeLog:

PR target/115069
* gcc.target/i386/pr115069.c: New.
---
 gcc/config/i386/i386-expand.cc   |  7 +++
 gcc/testsuite/gcc.target/i386/pr115069.c | 78 
 2 files changed, 85 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr115069.c

diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index a6132911e6a..f7939761879 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -24323,6 +24323,13 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, 
rtx op1, rtx op2)
   bool op2vec = GET_MODE_CLASS (GET_MODE (op2)) == MODE_VECTOR_INT;
   bool uns_p = code != ASHIFTRT;
 
+  /* Without VPMOVWB (provided by AVX512BW ISA), the expansion uses the
+ generic permutation to merge the data back into the right place.  This
+ permutation results in VPERMQ, which is slow, so better fall back to
+ ix86_expand_vecop_qihi.  */
+  if (!TARGET_AVX512BW)
+return false;
+
   if ((qimode == V16QImode && !TARGET_AVX2)
   || (qimode == V32QImode && (!TARGET_AVX512BW || !TARGET_EVEX512))
   /* There are no V64HImode instructions.  */
diff --git a/gcc/testsuite/gcc.target/i386/pr115069.c 
b/gcc/testsuite/gcc.target/i386/pr115069.c
new file mode 100644
index 000..c4b48b602ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr115069.c
@@ -0,0 +1,78 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx2" } */
+/* { dg-final { scan-assembler-not "vpermq" } } */
+
+#include 
+#include 
+#include 
+#include 
+
+typedef int8_t  stress_vint8_t  __attribute__ ((vector_size (16)));
+
+#define OPS(a, b, c, s, v23, v3) \
+do {   \
+   a += b; \
+   a |= b; \
+   a -= b; \
+   a &= ~b;\
+   a *= c; \
+   a = ~a; \
+   a *= s; \
+   a ^= c; \
+   a <<= 1;\
+   b >>= 1;\
+   b += c; \
+   a %= v23;   \
+   c /= v3;\
+   b = b ^ c;  \
+   c = b ^ c;  \
+   b = b ^ c;  \
+} while (0)
+
+volatile uint8_t csum8_put;
+
+void stress_vecmath(void)
+{
+   const stress_vint8_t v23_8 = { 
+   0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 
+   0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17 
+   };
+   const stress_vint8_t v3_8 = {
+   0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+   0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03
+   };
+   stress_vint8_t a8 = {
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+   };
+   stress_vint8_t b8 = {
+   0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
+   0x0f, 0x1e, 0x2d, 0x3c, 0x4b, 0x5a, 0x69, 0x78
+   };
+   stress_vint8_t c8 = {
+   0x01, 0x02, 0x03, 0x02, 0x01, 0x02, 0x03, 0x02,
+   0x03, 0x02, 0x01, 0x02, 0x03, 0x02, 0x01, 0x02
+   };
+   stress_vint8_t s8 = {
+   0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02,
+   0x01, 0x01, 0x02, 0x02, 0x01, 0x01, 0x02, 0x02,
+   };
+   const uint8_t csum8_val =  (uint8_t)0x1b;
+   int i;
+   uint8_t csum8;
+
+   for (i = 1000; i; i--) {
+   OPS(a8, b8, c8, s8, v23_8, v3_8);
+   OPS(a8, b8, c8, s8, v23_8, v3_8);
+   OPS(a8, b8, c8, s8, v23_8, v3_8);
+   OPS(a8, b8, c8, s8, v23_8, v3_8);
+   OPS(a8, b8, c8, s8, v23_8, v3_8);
+   OPS(a8, b8, c8, s8, v23_8, v3_8);
+   }
+
+   csum8 = a8[0]  ^ a8[1]  ^ a8[2]  ^ a8[3]  ^
+   a8[4]  ^ a8[5]  ^ a8[6]  ^ a8[7]  ^
+   a8[8]  ^ a8[9]  ^ a8[10] ^ a8[11] ^
+   a8[12] ^ a8[13] ^ a8[14] ^ a8[15];
+   csum8_put = csum8;
+}
-- 
2.31.1

[PATCH] i386: Disable ix86_expand_vecop_qihi2 when !TARGET_AVX512BW

[Haochen Jiang]

Hi all,

Since vpermq is really slow, we should avoid using it when it is
the only instruction could be used for ix86_expand_vecop_qihi2.

Bootstrapped and regtested on x86_64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

gcc/ChangeLog:

PR target/115069
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
Do not enable the optimization when AVX512BW is not enabled.
---
 gcc/config/i386/i386-expand.cc | 5 +
 1 file changed, 5 insertions(+)

diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index a6132911e6a..f24c800bb4f 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -24323,6 +24323,11 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, 
rtx op1, rtx op2)
   bool op2vec = GET_MODE_CLASS (GET_MODE (op2)) == MODE_VECTOR_INT;
   bool uns_p = code != ASHIFTRT;
 
+  /* vpermq is slow and we should not fall into the optimization when
+ it is the only instruction to be selected.  */
+  if (!TARGET_AVX512BW)
+return false;
+
   if ((qimode == V16QImode && !TARGET_AVX2)
   || (qimode == V32QImode && (!TARGET_AVX512BW || !TARGET_EVEX512))
   /* There are no V64HImode instructions.  */
-- 
2.31.1

[PATCH 2/2] Align tight&hot loop without considering max skipping bytes.

[Haochen Jiang]

From: liuhongt 

When hot loop is small enough to fix into one cacheline, we should align
the loop with ceil_log2 (loop_size) without considering maximum
skipp bytes. It will help code prefetch.

gcc/ChangeLog:

* config/i386/i386.cc (ix86_avoid_jump_mispredicts): Change
gen_pad to gen_max_skip_align.
(ix86_align_loops): New function.
(ix86_reorg): Call ix86_align_loops.
* config/i386/i386.md (pad): Rename to ..
(max_skip_align): .. this, and accept 2 operands for align and
skip.
---
 gcc/config/i386/i386.cc | 148 +++-
 gcc/config/i386/i386.md |  10 +--
 2 files changed, 153 insertions(+), 5 deletions(-)

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index e67e5f62533..c617091c8e1 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -23137,7 +23137,7 @@ ix86_avoid_jump_mispredicts (void)
  if (dump_file)
fprintf (dump_file, "Padding insn %i by %i bytes!\n",
 INSN_UID (insn), padsize);
-  emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
+ emit_insn_before (gen_max_skip_align (GEN_INT (4), GEN_INT 
(padsize)), insn);
}
 }
 }
@@ -23410,6 +23410,150 @@ ix86_split_stlf_stall_load ()
 }
 }
 
+/* When a hot loop can be fit into one cacheline,
+   force align the loop without considering the max skip.  */
+static void
+ix86_align_loops ()
+{
+  basic_block bb;
+
+  /* Don't do this when we don't know cache line size.  */
+  if (ix86_cost->prefetch_block == 0)
+return;
+
+  loop_optimizer_init (AVOID_CFG_MODIFICATIONS);
+  profile_count count_threshold = cfun->cfg->count_max / param_align_threshold;
+  FOR_EACH_BB_FN (bb, cfun)
+{
+  rtx_insn *label = BB_HEAD (bb);
+  bool has_fallthru = 0;
+  edge e;
+  edge_iterator ei;
+
+  if (!LABEL_P (label))
+   continue;
+
+  profile_count fallthru_count = profile_count::zero ();
+  profile_count branch_count = profile_count::zero ();
+
+  FOR_EACH_EDGE (e, ei, bb->preds)
+   {
+ if (e->flags & EDGE_FALLTHRU)
+   has_fallthru = 1, fallthru_count += e->count ();
+ else
+   branch_count += e->count ();
+   }
+
+  if (!fallthru_count.initialized_p () || !branch_count.initialized_p ())
+   continue;
+
+  if (bb->loop_father
+ && bb->loop_father->latch != EXIT_BLOCK_PTR_FOR_FN (cfun)
+ && (has_fallthru
+ ? (!(single_succ_p (bb)
+  && single_succ (bb) == EXIT_BLOCK_PTR_FOR_FN (cfun))
+&& optimize_bb_for_speed_p (bb)
+&& branch_count + fallthru_count > count_threshold
+&& (branch_count > fallthru_count * 
param_align_loop_iterations))
+ /* In case there'no fallthru for the loop.
+Nops inserted won't be executed.  */
+ : (branch_count > count_threshold
+|| (bb->count > bb->prev_bb->count * 10
+&& (bb->prev_bb->count
+<= ENTRY_BLOCK_PTR_FOR_FN (cfun)->count / 2)
+   {
+ rtx_insn* insn, *end_insn;
+ HOST_WIDE_INT size = 0;
+ bool padding_p = true;
+ basic_block tbb = bb;
+ unsigned cond_branch_num = 0;
+ bool detect_tight_loop_p = false;
+
+ for (unsigned int i = 0; i != bb->loop_father->num_nodes;
+  i++, tbb = tbb->next_bb)
+   {
+ /* Only handle continuous cfg layout. */
+ if (bb->loop_father != tbb->loop_father)
+   {
+ padding_p = false;
+ break;
+   }
+
+ FOR_BB_INSNS (tbb, insn)
+   {
+ if (!NONDEBUG_INSN_P (insn))
+   continue;
+ size += ix86_min_insn_size (insn);
+
+ /* We don't know size of inline asm.
+Don't align loop for call.  */
+ if (asm_noperands (PATTERN (insn)) >= 0
+ || CALL_P (insn))
+   {
+ size = -1;
+ break;
+   }
+   }
+
+ if (size == -1 || size > ix86_cost->prefetch_block)
+   {
+ padding_p = false;
+ break;
+   }
+
+ FOR_EACH_EDGE (e, ei, tbb->succs)
+   {
+ /* It could be part of the loop.  */
+ if (e->dest == bb)
+   {
+ detect_tight_loop_p = true;
+ break;
+   }
+   }
+
+ if (detect_tight_loop_p)
+   break;
+
+ end_insn = BB_END (tbb);
+ if (JUMP_P (end_insn))
+   {
+ /* For decoded icache:
+1. Up to two branches are allowed per Way.
+2. A non-conditional branch is the l

[PATCH 1/2] Adjust generic loop alignment from 16:11:8 to 16 for Intel processors

[Haochen Jiang]

Previously, we use 16:11:8 in generic tune for Intel processors, which
lead to cross cache line issue and result in some random performance
penalty in benchmarks with small loops commit to commit.

After changing to always aligning to 16 bytes, it will somehow solve
the issue.

gcc/ChangeLog:

* config/i386/x86-tune-costs.h (generic_cost): Change from
16:11:8 to 16.
---
 gcc/config/i386/x86-tune-costs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h
index 65d7d1f7e42..d34b5cc 100644
--- a/gcc/config/i386/x86-tune-costs.h
+++ b/gcc/config/i386/x86-tune-costs.h
@@ -3758,7 +3758,7 @@ struct processor_costs generic_cost = {
   generic_memset,
   COSTS_N_INSNS (4),   /* cond_taken_branch_cost.  */
   COSTS_N_INSNS (2),   /* cond_not_taken_branch_cost.  */
-  "16:11:8",   /* Loop alignment.  */
+  "16",/* Loop alignment.  */
   "16:11:8",   /* Jump alignment.  */
   "0:0:8", /* Label alignment.  */
   "16",/* Func alignment.  */
-- 
2.31.1

[PATCH 0/2] Align tight loops to solve cross cacheline issue

[Haochen Jiang]

Hi all,

Recently, we have encountered several random performance regressions in
benchmarks commit to commit. It is caused by cross cacheline issue for
tight loops.

We are trying to solve the issue by two patches. One is adjusting the
loop alignment for generic tune, the other is aligning tight and hot
loops more aggressively.

For SPECINT, we get a 0.85% improvement overall in rates, under option
-O2 -march=x86-64-v3 -mtune=generic on Emerald Rapids.

BenchMarks  EMR Rates
500.perlbench_r -1.21%
502.gcc_r   0.78%
505.mcf_r   0.00%
520.omnetpp_r   0.41%
523.xalancbmk_r 1.33%
525.x264_r  2.83%
531.deepsjeng_r 1.11%
541.leela_r 0.00%
548.exchange2_r 2.36%
557.xz_r0.98%
Geomean-int 0.85%

Side effect is that we get a 1.40% increase in codesize.

BenchMarks  EMR Codesize
500.perlbench_r 0.70%
502.gcc_r   0.67%
505.mcf_r   3.26%
520.omnetpp_r   0.31%
523.xalancbmk_r 1.15%
525.x264_r  1.11%
531.deepsjeng_r 1.40%
541.leela_r 1.31%
548.exchange2_r 3.06%
557.xz_r1.04%
Geomean-int 1.40%

Bootstrapped and regtested on x86_64-pc-linux-gnu.

After we committed into trunk for a month, if there isn't any unexpected
happen. We planned to backport it to GCC14.2.

Thx,
Haochen

Haochen Jiang (1):
  Adjust generic loop alignment from 16:11:8 to 16 for Intel processors

liuhongt (1):
  Align tight&hot loop without considering max skipping bytes.

 gcc/config/i386/i386.cc  | 148 ++-
 gcc/config/i386/i386.md  |  10 ++-
 gcc/config/i386/x86-tune-costs.h |   2 +-
 3 files changed, 154 insertions(+), 6 deletions(-)

-- 
2.31.1

[PATCH] i386: Fix array index overflow in pr105354-2.c

[Haochen Jiang]

Hi all,

The array index should not be over 8 for v8hi, or it will fail
under -O0 or using -fstack-protector.

This patch aims to fix that, which is mentioned in PR110621.

Commit as obvious and backport to GCC13.

Thx,
Haochen

gcc/testsuite/ChangeLog:

PR target/110621
* gcc.target/i386/pr105354-2.c: As mentioned.
---
 gcc/testsuite/gcc.target/i386/pr105354-2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/i386/pr105354-2.c 
b/gcc/testsuite/gcc.target/i386/pr105354-2.c
index b78b62e1e7e..1c592e84860 100644
--- a/gcc/testsuite/gcc.target/i386/pr105354-2.c
+++ b/gcc/testsuite/gcc.target/i386/pr105354-2.c
@@ -17,7 +17,7 @@ sse2_test (void)
   b.a[i] = i + 16;
   res_ab.a[i] = 0;
   exp_ab.a[i] = -1;
-  if (i <= 8)
+  if (i < 8)
{
  c.a[i] = i;
  d.a[i] = i + 8;
-- 
2.31.1

[PATCH] i386: Fix behavior for both using AVX10.1-256 in options and function attribute

[Haochen Jiang]

Hi all,

When we are using -mavx10.1-256 in command line and avx10.1-256 in
target attribute together, zmm should never be generated. But current
GCC will generate zmm since it wrongly enables EVEX512 for non-explicitly
set AVX512. This patch will fix that issue.

Regtested on x86_64-pc-linux-gnu. Ok for trunk?

gcc/ChangeLog:

* config/i386/i386-options.cc (ix86_valid_target_attribute_tree):
Check whether AVX512F is explicitly enabled.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_1-24.c: New test.
---
 gcc/config/i386/i386-options.cc| 1 +
 gcc/testsuite/gcc.target/i386/avx10_1-24.c | 7 +++
 2 files changed, 8 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-24.c

diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 68a2e1c6910..ac48b5c61c4 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -1431,6 +1431,7 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args,
  scenario.  */
   if ((def->x_ix86_isa_flags2 & OPTION_MASK_ISA2_AVX10_1_256)
   && (opts->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512F)
+  && (opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F)
   && !(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)
   && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))
 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-24.c 
b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
new file mode 100644
index 000..2e93f041760
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-final { scan-assembler-not "%zmm" } } */
+
+typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__));
+
+void __attribute__((target("avx10.1-256"))) callee256(__m512 *a, __m512 *b) { 
*a = *b; }
-- 
2.31.1

[PATCH] i386: Fix Sierra Forest auto dispatch

[Haochen Jiang]

Hi all,

This patch fixes an bug in mapping which caused auto dispatch failed.
Sierra Forest is in processor_types enum, but not processor_subtypes.

Committed as obvious and backport to GCC13.

Thx,
Haochen

gcc/ChangeLog:

* common/config/i386/i386-common.cc (processor_alias_table):
Let Sierra Forest map to CPU_TYPE enum.
---
 gcc/common/config/i386/i386-common.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/common/config/i386/i386-common.cc 
b/gcc/common/config/i386/i386-common.cc
index f814df8385b..77b154663bc 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -2302,7 +2302,7 @@ const pta processor_alias_table[] =
   {"gracemont", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
   {"sierraforest", PROCESSOR_SIERRAFOREST, CPU_HASWELL, PTA_SIERRAFOREST,
-M_CPU_SUBTYPE (INTEL_SIERRAFOREST), P_PROC_AVX2},
+M_CPU_TYPE (INTEL_SIERRAFOREST), P_PROC_AVX2},
   {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE,
 M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2},
   {"clearwaterforest", PROCESSOR_CLEARWATERFOREST, CPU_HASWELL,
-- 
2.31.1

[gcc-wwwdocs PATCH] Uncomment MCore part title

[Haochen Jiang]

Hi all,

When I am checking GCC14 documentation, I found that MCore forgot to uncomment
the title for their part, which caused the documentation is mixed with x86.

Uncomment that and commit as obvious.

Thx,
Haochen

---
 htdocs/gcc-14/changes.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 14301157..8ac08e9a 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -828,7 +828,7 @@ __asm (".global __flmap_lock"  "\n\t"
   
 
 
-
+MCore
 
   Bitfields are now signed by default per GCC policy.  If you need 
bitfields
 to be unsigned, use -funsigned-bitfields.
-- 
2.31.1

[PATCH] i386: Modify testcases failed under -DDEBUG

[Haochen Jiang]

Hi all,

Recently, I happened to run i386.exp under -DDEBUG and found some fail.

This patch aims to fix that. Ok for trunk?

Thx,
Haochen

gcc/testsuite/ChangeLog:

* gcc.target/i386/adx-check.h: Include stdio.h when DEBUG
is defined.
* gcc.target/i386/avx512fp16-vscalefph-1b.c: Do not define
DEBUG.
* gcc.target/i386/avx512fp16vl-vaddph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vcmpph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vdivph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vfpclassph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vgetexpph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vgetmantph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vmaxph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vminph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vmulph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vrcpph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vreduceph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vrsqrtph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vscalefph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vsqrtph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vsubph-1b.c: Ditto.
* gcc.target/i386/readeflags-1.c: Include stdio.h when DEBUG
is defined.
* gcc.target/i386/rtm-check.h: Ditto.
* gcc.target/i386/sha-check.h: Ditto.
* gcc.target/i386/writeeflags-1.c: Ditto.
---
 gcc/testsuite/gcc.target/i386/adx-check.h   | 3 +++
 gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1b.c | 3 ---
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vaddph-1b.c  | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vcmpph-1b.c  | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vdivph-1b.c  | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vfpclassph-1b.c  | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetexpph-1b.c   | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vgetmantph-1b.c  | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vmaxph-1b.c  | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vminph-1b.c  | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vmulph-1b.c  | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1b.c  | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1b.c   | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vrsqrtph-1b.c| 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1b.c   | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vsqrtph-1b.c | 1 -
 gcc/testsuite/gcc.target/i386/avx512fp16vl-vsubph-1b.c  | 1 -
 gcc/testsuite/gcc.target/i386/readeflags-1.c| 3 +++
 gcc/testsuite/gcc.target/i386/rtm-check.h   | 3 +++
 gcc/testsuite/gcc.target/i386/sha-check.h   | 3 +++
 gcc/testsuite/gcc.target/i386/writeeflags-1.c   | 3 +++
 22 files changed, 15 insertions(+), 19 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/adx-check.h 
b/gcc/testsuite/gcc.target/i386/adx-check.h
index cfed1a38483..45435b91d0e 100644
--- a/gcc/testsuite/gcc.target/i386/adx-check.h
+++ b/gcc/testsuite/gcc.target/i386/adx-check.h
@@ -1,5 +1,8 @@
 #include 
 #include "cpuid.h"
+#ifdef DEBUG
+#include 
+#endif
 
 static void adx_test (void);
 
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1b.c 
b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1b.c
index 7c7288d6eb3..0ba9ec57f37 100644
--- a/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1b.c
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1b.c
@@ -1,9 +1,6 @@
 /* { dg-do run { target avx512fp16 } } */
 /* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
 
-
-#define DEBUG
-
 #define AVX512FP16
 #include "avx512fp16-helper.h"
 
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vaddph-1b.c 
b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vaddph-1b.c
index fcf6a9058f5..1db7c565262 100644
--- a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vaddph-1b.c
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vaddph-1b.c
@@ -1,7 +1,6 @@
 /* { dg-do run { target avx512fp16 } } */
 /* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
 
-#define DEBUG
 #define AVX512VL
 #define AVX512F_LEN 256  
 #define AVX512F_LEN_HALF 128 
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcmpph-1b.c 
b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcmpph-1b.c
index c201a9258bf..bbd366a5d29 100644
--- a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcmpph-1b.c
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcmpph-1b.c
@@ -1,7 +1,6 @@
 /* { dg-do run { target avx512fp16 } } */
 /* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
 
-#define DEBUG
 #define AVX512VL
 #define AVX512F_LEN 256  
 #define AVX512F_LEN_HALF 128 
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vdivph-1b.c 
b/gcc/testsuite/gc

[PATCH] i386: Remove redundant move in vnni pattern

[Haochen Jiang]

Hi all,

This patch removes all redundant set in vnni patterns.

Ok for trunk?

Thx,
Haochen

gcc/ChangeLog:

* config/i386/sse.md (sdot_prod): Remove redundant SET.
(usdot_prod): Ditto.
(sdot_prod): Ditto.
(udot_prod): Ditto.
---
 gcc/config/i386/sse.md | 4 
 1 file changed, 4 deletions(-)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 532738dcf94..acd10908d76 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16174,7 +16174,6 @@
   operands[2] = lowpart_subreg (mode,
force_reg (mode, operands[2]),
mode);
-  emit_insn (gen_rtx_SET (operands[0], operands[3]));
   emit_insn (gen_vpdpwssd_ (operands[0], operands[3],
   operands[1], operands[2]));
 }
@@ -29963,7 +29962,6 @@
   operands[2] = lowpart_subreg (mode,
force_reg (mode, operands[2]),
mode);
-  emit_insn (gen_rtx_SET (operands[0], operands[3]));
   emit_insn (gen_vpdpbusd_ (operands[0], operands[3],
  operands[1], operands[2]));
   DONE;
@@ -30780,7 +30778,6 @@
   operands[2] = lowpart_subreg (mode,
force_reg (mode, operands[2]),
mode);
-  emit_insn (gen_rtx_SET (operands[0], operands[3]));
   emit_insn (gen_vpdpbssd_ (operands[0], operands[3],
  operands[1], operands[2]));
 }
@@ -30857,7 +30854,6 @@
   operands[2] = lowpart_subreg (mode,
force_reg (mode, operands[2]),
mode);
-  emit_insn (gen_rtx_SET (operands[0], operands[3]));
   emit_insn (gen_vpdpbuud_ (operands[0], operands[3],
  operands[1], operands[2]));
}
-- 
2.31.1

[PATCH] i386: Add AVX10.1 related macros

[Haochen Jiang]

Hi all,

This patch aims to add AVX10.1 related macros for libgomp's request. The
request comes following:

https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642025.html

Ok for trunk?

Thx,
Haochen

gcc/ChangeLog:

PR target/113288
* config/i386/i386-c.cc (ix86_target_macros_internal):
Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
---
 gcc/config/i386/i386-c.cc | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index c3ae984670b..366b560158a 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -735,6 +735,13 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
 def_or_undef (parse_in, "__EVEX512__");
   if (isa_flag2 & OPTION_MASK_ISA2_USER_MSR)
 def_or_undef (parse_in, "__USER_MSR__");
+  if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1_256)
+{
+  def_or_undef (parse_in, "__AVX10_1_256__");
+  def_or_undef (parse_in, "__AVX10_1__");
+}
+  if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1_512)
+def_or_undef (parse_in, "__AVX10_1_512__");
   if (TARGET_IAMCU)
 {
   def_or_undef (parse_in, "__iamcu");
-- 
2.31.1

[PATCH] Add -mevex512 into invoke.texi

[Haochen Jiang]

Hi Richard,

It seems that I send out a not updated patch. This patch should what
I want to send.

Thx,
Haochen

gcc/ChangeLog:

* doc/invoke.texi: Add -mevex512.
---
 gcc/doc/invoke.texi | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 68d1f364ac0..6d4f92f1101 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1463,7 +1463,7 @@ See RS/6000 and PowerPC Options.
 -mamx-tile  -mamx-int8  -mamx-bf16 -muintr -mhreset -mavxvnni
 -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
--musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512
+-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512
 -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg}
 -mkl -mwidekl
@@ -35272,6 +35272,11 @@ r8-r15 registers so that the call and jmp instruction 
length is 6 bytes
 to allow them to be replaced with @samp{lfence; call *%r8-r15} or
 @samp{lfence; jmp *%r8-r15} at run-time.
 
+@opindex mevex512
+@item -mevex512
+@itemx -mno-evex512
+Enables/disables 512-bit vector. It will be default on if AVX512F is enabled.
+
 @end table
 
 These @samp{-m} switches are supported in addition to the above
-- 
2.31.1

[PATCH] Add -mevex512 into invoke.texi

[Haochen Jiang]

Hi all,

In invoke.texi, -mevex512 is missing. This patch adds that.

Ok for trunk?

Thx,
Haochen

gcc/ChangeLog:

* doc/invoke.texi: Add -mevex512.
---
 gcc/doc/invoke.texi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 68d1f364ac0..1a92dcdc1ef 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1463,7 +1463,7 @@ See RS/6000 and PowerPC Options.
 -mamx-tile  -mamx-int8  -mamx-bf16 -muintr -mhreset -mavxvnni
 -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
--musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512
+-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512
 -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg}
 -mkl -mwidekl
-- 
2.31.1

[PATCH] i386: Fix recent testcase fail

[Haochen Jiang]

After commit 01f4251b8775c832a92d55e2df57c9ac72eaceef, early break
vectorization is supported. The two testcases need to be fixed.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx512fp16-xorsign-1.c: Fix testcase.
* gcc.target/i386/part-vect-absneghf.c: Ditto.
---
 gcc/testsuite/gcc.target/i386/avx512fp16-xorsign-1.c | 2 +-
 gcc/testsuite/gcc.target/i386/part-vect-absneghf.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-xorsign-1.c 
b/gcc/testsuite/gcc.target/i386/avx512fp16-xorsign-1.c
index a22a6ceabff..f5dd457c9eb 100644
--- a/gcc/testsuite/gcc.target/i386/avx512fp16-xorsign-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-xorsign-1.c
@@ -35,7 +35,7 @@ do_test (void)
   abort ();
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
 /* { dg-final { scan-assembler "\[ \t\]xor" } } */
 /* { dg-final { scan-assembler "\[ \t\]and" } } */
 /* { dg-final { scan-assembler-not "copysign" } } */
diff --git a/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c 
b/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c
index 48aed14d604..713f0bff4dd 100644
--- a/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c
+++ b/gcc/testsuite/gcc.target/i386/part-vect-absneghf.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target avx512fp16 } } */
-/* { dg-options "-O1 -mavx512fp16 -mavx512vl -ftree-vectorize 
-fdump-tree-slp-details -fdump-tree-optimized" } */
+/* { dg-options "-O1 -mavx512fp16 -mavx512vl -fdump-tree-slp-details 
-fdump-tree-optimized" } */
 
 extern void abort ();
 
-- 
2.31.1

[gcc-wwwdocs PATCH v2] gcc-13/14: Mention recent update for x86_64 backend

[Haochen Jiang]

Hi all,

This is the v2 patch for the wwwdocs change regarding to review.

If there is no objection, I will push this change next Tuesday.

Changes is v2:

  - Remove RAO-INT from Grand Ridge
  - Remove the mask register restriction for -mno-evex512
  - Arrange the options alphabetically
  - Other minor text change

Thx,
Haochen

Messages in v1:

This patch will mention the following changes in wwwdocs for x86_64 backend:

  - AVX10.1 support
  - APX EGPR, PUSH2POP2, PPX and NDD support
  - Xeon Phi ISAs deprecated

Also I adjust the words in x86_64 part for GCC 13.

---
Mention AVX10.1 support, APX support and Xeon Phi deprecate in GCC 14.
Also adjust documentation in GCC 13.
---
 htdocs/gcc-13/changes.html | 38 --
 htdocs/gcc-14/changes.html | 27 ++-
 2 files changed, 42 insertions(+), 23 deletions(-)

diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index d3bacc16..b4b1a39a 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -543,24 +543,28 @@ You may also want to check out our
   __bf16 type to x86 psABI. Users need to adjust their
   AVX512BF16-related source code when upgrading GCC12 to GCC13.
   
-  New ISA extension support for Intel AVX-IFMA was added.
-  AVX-IFMA intrinsics are available via the -mavxifma
+  New ISA extension support for Intel AMX-COMPLEX was added.
+  AMX-COMPLEX intrinsics are available via the -mamx-complex
   compiler switch.
   
-  New ISA extension support for Intel AVX-VNNI-INT8 was added.
-  AVX-VNNI-INT8 intrinsics are available via the -mavxvnniint8
+  New ISA extension support for Intel AMX-FP16 was added.
+  AMX-FP16 intrinsics are available via the -mamx-fp16
+  compiler switch.
+  
+  New ISA extension support for Intel AVX-IFMA was added.
+  AVX-IFMA intrinsics are available via the -mavxifma
   compiler switch.
   
   New ISA extension support for Intel AVX-NE-CONVERT was added.
   AVX-NE-CONVERT intrinsics are available via the
   -mavxneconvert compiler switch.
   
-  New ISA extension support for Intel CMPccXADD was added.
-  CMPccXADD intrinsics are available via the -mcmpccxadd
+  New ISA extension support for Intel AVX-VNNI-INT8 was added.
+  AVX-VNNI-INT8 intrinsics are available via the -mavxvnniint8
   compiler switch.
   
-  New ISA extension support for Intel AMX-FP16 was added.
-  AMX-FP16 intrinsics are available via the -mamx-fp16
+  New ISA extension support for Intel CMPccXADD was added.
+  CMPccXADD intrinsics are available via the -mcmpccxadd
   compiler switch.
   
   New ISA extension support for Intel PREFETCHI was added.
@@ -571,10 +575,6 @@ You may also want to check out our
   RAO-INT intrinsics are available via the -mraoint
   compiler switch.
   
-  New ISA extension support for Intel AMX-COMPLEX was added.
-  AMX-COMPLEX intrinsics are available via the -mamx-complex
-  compiler switch.
-  
   GCC now supports the Intel CPU named Raptor Lake through
 -march=raptorlake.
 Raptor Lake is based on Alder Lake.
@@ -585,13 +585,13 @@ You may also want to check out our
   
   GCC now supports the Intel CPU named Sierra Forest through
 -march=sierraforest.
-The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
-ENQCMD and UINTR ISA extensions.
+Based on ISA extensions enabled on Alder Lake, the switch further enables
+the AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, CMPccXADD, ENQCMD and UINTR
+ISA extensions.
   
   GCC now supports the Intel CPU named Grand Ridge through
 -march=grandridge.
-The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
-ENQCMD, UINTR and RAO-INT ISA extensions.
+Grand Ridge is based on Sierra Forest.
   
   GCC now supports the Intel CPU named Emerald Rapids through
 -march=emeraldrapids.
@@ -599,11 +599,13 @@ You may also want to check out our
   
   GCC now supports the Intel CPU named Granite Rapids through
 -march=graniterapids.
-The switch enables the AMX-FP16 and PREFETCHI ISA extensions.
+Based on Sapphire Rapids, the switch further enables the AMX-FP16 and
+PREFETCHI ISA extensions.
   
   GCC now supports the Intel CPU named Granite Rapids D through
 -march=graniterapids-d.
-The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions.
+Based on Granite Rapids, the switch further enables the AMX-COMPLEX ISA
+extensions.
   
   GCC now supports AMD CPUs based on the znver4 core
 via -march=znver4.  The switch makes GCC consider
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 24e6409a..4b83037a 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -320,8 +320,18 @@ a work-in-progress.
 IA-32/x86-64
 
   New compiler option -m[no-]evex512 was added.
-  The compiler switch enables/disables 512 bit vector and 64 bit mask
-  register. It will

[PATCH] i386: Allow 64 bit mask register for -mno-evex512

[Haochen Jiang]

Hi all,

There is a recent change in AVX10 documentation which allows 64 bit mask
register instructions in AVX10-256, the documentation comes following:

Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification
https://cdrdv2.intel.com/v1/dl/getContent/784267
The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical Paper
https://cdrdv2.intel.com/v1/dl/getContent/784343

As a result, we will need to allow 64 bit mask register for -mno-evex512. The
patch aims to add them.

Regtested on x86_64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

gcc/ChangeLog:

* config/i386/avx512bwintrin.h: Allow 64 bit mask intrin usage
for -mno-evex512.
* config/i386/i386-builtin.def: Remove OPTION_MASK_ISA2_EVEX512
for 64 bit mask builtins.
* config/i386/i386.cc (ix86_hard_regno_mode_ok): Allow 64 bit
mask register for -mno-evex512.
* config/i386/i386.md (SWI1248_AVX512BWDQ_64): Remove
TARGET_EVEX512.
(*zero_extendsidi2): Change isa attribute to avx512bw.
(kmov_isa): Ditto.
(*anddi_1): Ditto.
(*andn_1): Remove TARGET_EVEX512.
(*one_cmplsi2_1_zext): Change isa attribute to avx512bw.
(*ashl3_1): Ditto.
(*lshr3_1): Ditto.
* config/i386/sse.md (SWI1248_AVX512BWDQ): Remove TARGET_EVEX512.
(SWI1248_AVX512BW): Ditto.
(SWI1248_AVX512BWDQ2): Ditto.
(*knotsi_1_zext): Ditto.
(kunpckdi): Ditto.
(SWI24_MASK): Removed.
(vec_pack_trunc_): Change iterator from SWI24_MASK to SWI24.
(vec_unpacks_lo_di): Remove TARGET_EVEX512.
(SWI48x_MASK): Removed.
(vec_unpacks_hi_): Change iterator from SWI48x_MASK to SWI48x.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_1-6.c: Remove check for errors.
* gcc.target/i386/noevex512-2.c: Diito.
---
 gcc/config/i386/avx512bwintrin.h| 42 ++---
 gcc/config/i386/i386-builtin.def| 28 +++---
 gcc/config/i386/i386.cc |  3 +-
 gcc/config/i386/i386.md | 20 +-
 gcc/config/i386/sse.md  | 30 ++-
 gcc/testsuite/gcc.target/i386/avx10_1-6.c   |  2 +-
 gcc/testsuite/gcc.target/i386/noevex512-2.c |  2 +-
 7 files changed, 59 insertions(+), 68 deletions(-)

diff --git a/gcc/config/i386/avx512bwintrin.h b/gcc/config/i386/avx512bwintrin.h
index d5ce79fd073..37fd7c68976 100644
--- a/gcc/config/i386/avx512bwintrin.h
+++ b/gcc/config/i386/avx512bwintrin.h
@@ -34,6 +34,8 @@
 #define __DISABLE_AVX512BW__
 #endif /* __AVX512BW__ */
 
+typedef unsigned long long __mmask64;
+
 extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
 _mm_avx512_set_epi32 (int __q3, int __q2, int __q1, int __q0)
 {
@@ -223,27 +225,6 @@ _kshiftri_mask32 (__mmask32 __A, unsigned int __B)
 
 #endif
 
-#ifdef __DISABLE_AVX512BW__
-#undef __DISABLE_AVX512BW__
-#pragma GCC pop_options
-#endif /* __DISABLE_AVX512BW__ */
-
-#if !defined (__AVX512BW__) || !defined (__EVEX512__)
-#pragma GCC push_options
-#pragma GCC target("avx512bw,evex512")
-#define __DISABLE_AVX512BW_512__
-#endif /* __AVX512BW_512__ */
-
-/* Internal data types for implementing the intrinsics.  */
-typedef short __v32hi __attribute__ ((__vector_size__ (64)));
-typedef short __v32hi_u __attribute__ ((__vector_size__ (64),  \
-   __may_alias__, __aligned__ (1)));
-typedef char __v64qi __attribute__ ((__vector_size__ (64)));
-typedef char __v64qi_u __attribute__ ((__vector_size__ (64),   \
-  __may_alias__, __aligned__ (1)));
-
-typedef unsigned long long __mmask64;
-
 extern __inline unsigned char
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _ktest_mask64_u8  (__mmask64 __A,  __mmask64 __B, unsigned char *__CF)
@@ -365,6 +346,25 @@ _kandn_mask64 (__mmask64 __A, __mmask64 __B)
   return (__mmask64) __builtin_ia32_kandndi ((__mmask64) __A, (__mmask64) __B);
 }
 
+#ifdef __DISABLE_AVX512BW__
+#undef __DISABLE_AVX512BW__
+#pragma GCC pop_options
+#endif /* __DISABLE_AVX512BW__ */
+
+#if !defined (__AVX512BW__) || !defined (__EVEX512__)
+#pragma GCC push_options
+#pragma GCC target("avx512bw,evex512")
+#define __DISABLE_AVX512BW_512__
+#endif /* __AVX512BW_512__ */
+
+/* Internal data types for implementing the intrinsics.  */
+typedef short __v32hi __attribute__ ((__vector_size__ (64)));
+typedef short __v32hi_u __attribute__ ((__vector_size__ (64),  \
+   __may_alias__, __aligned__ (1)));
+typedef char __v64qi __attribute__ ((__vector_size__ (64)));
+typedef char __v64qi_u __attribute__ ((__vector_size__ (64),   \
+  __may_alias__, __aligned__ (1)));
+
 extern __inline __m512i
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm512_mask_mov_epi16 (__m512i __W, __mmask32 __U, __m512i __A)
diff --git a/gcc/co

[PATCH] i386: Remove RAO-INT from Grand Ridge

[Haochen Jiang]

Hi all,

According to ISE050 published at the end of September, RAO-INT will not
be in Grand Ridge anymore. This patch aims to remove it.

The documentation comes following:

https://cdrdv2.intel.com/v1/dl/getContent/671368

Regtested on x86_64-pc-linux-gnu. Ok for trunk and backport to GCC13?

Thx,
Haochen

gcc/ChangeLog:

* config/i386/driver-i386.cc (host_detect_local_cpu): Do not
set Grand Ridge depending on RAO-INT.
* config/i386/i386.h: Remove PTA_RAOINT from PTA_GRANDRIDGE.
* doc/invoke.texi: Adjust documentation.
---
 gcc/config/i386/driver-i386.cc | 3 ---
 gcc/config/i386/i386.h | 2 +-
 gcc/doc/invoke.texi| 4 ++--
 3 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc
index 0cfb2884d65..3342e550f2a 100644
--- a/gcc/config/i386/driver-i386.cc
+++ b/gcc/config/i386/driver-i386.cc
@@ -665,9 +665,6 @@ const char *host_detect_local_cpu (int argc, const char 
**argv)
  /* Assume Arrow Lake S.  */
  else if (has_feature (FEATURE_SM3))
cpu = "arrowlake-s";
- /* Assume Grand Ridge.  */
- else if (has_feature (FEATURE_RAOINT))
-   cpu = "grandridge";
  /* Assume Sierra Forest.  */
  else if (has_feature (FEATURE_AVXVNNIINT8))
cpu = "sierraforest";
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 47340c6a4ad..303baf8c921 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2416,7 +2416,7 @@ constexpr wide_int_bitmask PTA_GRANITERAPIDS = 
PTA_SAPPHIRERAPIDS | PTA_AMX_FP16
   | PTA_PREFETCHI;
 constexpr wide_int_bitmask PTA_GRANITERAPIDS_D = PTA_GRANITERAPIDS
   | PTA_AMX_COMPLEX;
-constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT;
+constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST;
 constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_ALDERLAKE | PTA_AVXIFMA
   | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_UINTR;
 constexpr wide_int_bitmask PTA_ARROWLAKE_S = PTA_ARROWLAKE | PTA_AVXVNNIINT16
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1f26f80d26c..82dd9cdf907 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -33451,8 +33451,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, 
RDRND, XSAVE, XSAVEC,
 XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
 MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
 PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI,
-AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD, UINTR and RAOINT
-instruction set support.
+AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, ENQCMD and UINTR instruction set
+support.
 
 @item clearwaterforest
 Intel Clearwater Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
-- 
2.31.1

[PATCH] i386: Fix PR110790 testcase

[Haochen Jiang]

Hi all,

This patch will fix the testcase fail previously introduced.

Approved by another thread:

https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640288.html

Pushed to trunk.

Thx,
Haochen

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr110790-2.c: Change scan-assembler from shrq
to shr\[qx\].
---
 gcc/testsuite/gcc.target/i386/pr110790-2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/i386/pr110790-2.c 
b/gcc/testsuite/gcc.target/i386/pr110790-2.c
index 16c73cb7465..dbb526308e6 100644
--- a/gcc/testsuite/gcc.target/i386/pr110790-2.c
+++ b/gcc/testsuite/gcc.target/i386/pr110790-2.c
@@ -21,5 +21,5 @@ refmpn_tstbit_bad (mp_srcptr ptr, unsigned long bit)
 shrq%cl, %rax
 andl   $1, %eax
  */
-/* { dg-final { scan-assembler-times "shrq" 2 { target { lp64 } } } } */
+/* { dg-final { scan-assembler-times "shr\[qx\]" 2 { target { lp64 } } } } */
 /* { dg-final { scan-assembler-times "andl" 2 { target { lp64 } } } } */
-- 
2.31.1

[gcc-wwwdocs PATCH] gcc-13/14: Mention recent update for x86_64 backend

[Haochen Jiang]

Hi all,

This patch will mention the following changes in wwwdocs for x86_64 backend:

  - AVX10.1 support
  - APX EGPR, PUSH2POP2, PPX and NDD support
  - Xeon Phi ISAs deprecated

Also I adjust the words in x86_64 part for GCC 13. Ok for gcc-wwwdocs?

Thx,
Haochen

Mention AVX10.1 support, APX support and Xeon Phi deprecate in GCC 14.
Also adjust documentation in GCC 13.
---
 htdocs/gcc-13/changes.html | 14 --
 htdocs/gcc-14/changes.html | 18 ++
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 8ef3d639..e29ca72e 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -579,13 +579,13 @@ You may also want to check out our
   
   GCC now supports the Intel CPU named Sierra Forest through
 -march=sierraforest.
-The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
-ENQCMD and UINTR ISA extensions.
+Based on ISA extensions enabled on Alder Lake, the switch further enables
+the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, ENQCMD and UINTR
+ISA extensions.
   
   GCC now supports the Intel CPU named Grand Ridge through
 -march=grandridge.
-The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
-ENQCMD, UINTR and RAO-INT ISA extensions.
+Based on Sierra Forest, the switch further enables RAO-INT ISA extensions.
   
   GCC now supports the Intel CPU named Emerald Rapids through
 -march=emeraldrapids.
@@ -593,11 +593,13 @@ You may also want to check out our
   
   GCC now supports the Intel CPU named Granite Rapids through
 -march=graniterapids.
-The switch enables the AMX-FP16, PREFETCHI ISA extensions.
+Based on Sapphire Rapids, the switch further enables the AMX-FP16 and
+PREFETCHI ISA extensions.
   
   GCC now supports the Intel CPU named Granite Rapids D through
 -march=graniterapids-d.
-The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions.
+Based on Granite Rapids, the switch further enables the AMX-COMPLEX ISA
+extensions.
   
   GCC now supports AMD CPUs based on the znver4 core
 via -march=znver4.  The switch makes GCC consider
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 6d7138f8..8590f735 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -296,6 +296,16 @@ a work-in-progress.
   USER_MSR intrinsics are available via the -muser_msr
   compiler switch.
   
+  New ISA extension support for Intel AVX10.1 was added.
+  AVX10.1 intrinsics are available via the -mavx10.1 or
+  -mavx10.1-256 compiler switch with 256 bit vector size
+  support. 512 bit vector size support for AVX10.1 intrinsics are
+  available via the -mavx10.1-512 compiler switch.
+  
+  Part of new feature support for Intel APX was added, including EGPR,
+  PUSH2POP2, PPX and NDD. APX features are available via the
+  -mapxf compiler switch.
+  
   GCC now supports the Intel CPU named Clearwater Forest through
 -march=clearwaterforest.
 Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16,
@@ -321,6 +331,14 @@ a work-in-progress.
 Based on Arrow Lake S, the switch further enables the PREFETCHI ISA
 extensions.
   
+  Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are marked
+as deprecated. GCC will emit a warning when using the
+-mavx5124fmaps, -mavx5124vnniw,
+-mavx512er, -mavx512pf,
+-mprefetchwt1, -march=knl,
+-march=knm, -mtune=knl and 
-mtune=knm
+compiler switch. The support will be removed in GCC 15.
+  
 
 
 
-- 
2.31.1

[PATCH] i386: Mark Xeon Phi ISAs as deprecated

[Haochen Jiang]

Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in GCC 15. In GCC 14, we will first
emit a warning for the usage.

gcc/ChangeLog:

* config/i386/driver-i386.cc (host_detect_local_cpu):
Do not append "-mno-" for Xeon Phi ISAs.
* config/i386/i386-options.cc (ix86_option_override_internal):
Emit a warning for KNL/KNM targets.
* config/i386/i386.opt: Emit a warning for Xeon Phi ISAs.

gcc/testsuite/ChangeLog:

* g++.dg/other/i386-2.C: Adjust testcases.
* g++.dg/other/i386-3.C: Ditto.
* g++.dg/pr80481.C: Ditto.
* gcc.dg/pr71279.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fmaddps-1.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fmaddps-2.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fmaddss-1.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddps-1.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddps-2.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddss-1.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssd-1.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssd-2.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssds-1.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssds-2.c: Ditto.
* gcc.target/i386/avx512er-vexp2pd-1.c: Ditto.
* gcc.target/i386/avx512er-vexp2pd-2.c: Ditto.
* gcc.target/i386/avx512er-vexp2ps-1.c: Ditto.
* gcc.target/i386/avx512er-vexp2ps-2.c: Ditto.
* gcc.target/i386/avx512er-vrcp28pd-1.c: Ditto.
* gcc.target/i386/avx512er-vrcp28pd-2.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ps-1.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ps-2.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ps-3.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ps-4.c: Ditto.
* gcc.target/i386/avx512er-vrcp28sd-1.c: Ditto.
* gcc.target/i386/avx512er-vrcp28sd-2.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ss-1.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ss-2.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28pd-1.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28pd-2.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-1.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-2.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-3.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-4.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-5.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-6.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28sd-1.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28sd-2.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ss-1.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ss-2.c: Ditto.
* gcc.target/i386/avx512f-gather-1.c: Ditto.
* gcc.target/i386/avx512f-gather-2.c: Ditto.
* gcc.target/i386/avx512f-gather-3.c: Ditto.
* gcc.target/i386/avx512f-gather-4.c: Ditto.
* gcc.target/i386/avx512f-gather-5.c: Ditto.
* gcc.target/i386/avx512f-i32gatherd512-1.c: Ditto.
* gcc.target/i386/avx512f-i32gatherd512-2.c: Ditto.
* gcc.target/i386/avx512f-i32gatherpd512-1.c: Ditto.
* gcc.target/i386/avx512f-i32gatherpd512-2.c: Ditto.
* gcc.target/i386/avx512f-i32gatherps512-1.c: Ditto.
* gcc.target/i386/avx512f-vect-perm-1.c: Ditto.
* gcc.target/i386/avx512f-vect-perm-2.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf0dpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf0dps-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf0qpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf0qps-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf1dpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf1dps-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf1qpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf1qps-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf0dpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf0dps-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf0qpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf0qps-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf1dpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf1dps-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf1qpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf1qps-1.c: Ditto.
* gcc.target/i386/funcspec-56.inc: Ditto.
* gcc.target/i386/pr101395-2.c: Ditto.
* gcc.target/i386/pr101395-3.c: Ditto.
* gcc.target/i386/pr103404.c: Ditto.
* gcc.target/i386/pr104448.c: Ditto.
* gcc.target/i386/pr107934.c: Ditto.
* gcc.target/i386/pr57275.c: Ditto.
* gcc.target/i386/pr64387.c: Ditto.
* gcc.target/i386/pr70728.c: Ditto.
* gcc.target/i386/pr71346.c: Ditto.
* gcc.target/i386/pr82941-2.c: Ditto.
* gcc.target/i386/pr82942-1.c: Ditto.
* gcc.target/i386/pr82942

[RFC] i386: Remove Xeon Phi ISA support

[Haochen Jiang]

Hi all,

Since Knight Landing and Knight Mill microarchitectures were EOL in 2019
and previously ICC and ICX has removed the support and emitted errors, we
would also like to remove the support in GCC to reduce maintainence effort.
The deprecated Xeon Phi ISAs are AVX512PF, AVX512ER, AVX5124VNNIW,
AVX5124FMAPS, PREFETCHWT1.

Our plan is to first emit a warning in GCC 14 to indicate that we will remove
them in GCC 15. And in GCC 15, we will remove the support if there is no
objection.

The patch following is the GCC 14 patch which mark them as deprecated.

Regtested on x86_64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

[PATCH] i386: Fix AVX512 and AVX10 option issues

[Haochen Jiang]

Hi all,

This patch should be able to fix the current issue mentioned in PR112643.

Also, I fixed some legacy issues in code related to AVX512/AVX10.

Ok for trunk?

Thx,
Haochen

gcc/ChangeLog:

PR target/112643
* config/i386/driver-i386.cc (check_avx10_avx512_features):
Renamed to ...
(check_avx512_features): this and remove avx10 check.
(host_detect_local_cpu): Never append -mno-avx10.1-{256,512} to
avoid emitting warnings when building GCC with native arch.
* config/i386/i386-builtin.def (BDESC): Add missing AVX512VL for
128/256 bit builtin for AVX512VP2INTERSECT.
* config/i386/i386-options.cc (ix86_option_override_internal):
Also check whether the AVX512 flags is set when trying to reset.
* config/i386/i386.h
(PTA_SKYLAKE_AVX512): Add missing PTA_EVEX512.
(PTA_ZNVER4): Ditto.
---
 gcc/config/i386/driver-i386.cc   | 19 +--
 gcc/config/i386/i386-builtin.def |  8 
 gcc/config/i386/i386-options.cc  |  8 +---
 gcc/config/i386/i386.h   |  4 ++--
 4 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc
index ae67efc49c3..204600e128a 100644
--- a/gcc/config/i386/driver-i386.cc
+++ b/gcc/config/i386/driver-i386.cc
@@ -377,15 +377,10 @@ detect_caches_intel (bool xeon_mp, unsigned max_level,
enabled and the other disabled.  Add this function to avoid push "-mno-"
options under this scenario for -march=native.  */
 
-bool check_avx10_avx512_features (__processor_model &cpu_model,
- unsigned int 
(&cpu_features2)[SIZE_OF_CPU_FEATURES],
- const enum processor_features feature)
+bool check_avx512_features (__processor_model &cpu_model,
+   unsigned int (&cpu_features2)[SIZE_OF_CPU_FEATURES],
+   const enum processor_features feature)
 {
-  if (has_feature (FEATURE_AVX512F)
-  && ((feature == FEATURE_AVX10_1_256)
- || (feature == FEATURE_AVX10_1_512)))
-return false;
-
   if (has_feature (FEATURE_AVX10_1_256)
   && ((feature == FEATURE_AVX512F)
  || (feature == FEATURE_AVX512CD)
@@ -900,8 +895,12 @@ const char *host_detect_local_cpu (int argc, const char 
**argv)
  options = concat (options, " ",
isa_names_table[i].option, NULL);
  }
-   else if (check_avx10_avx512_features (cpu_model, cpu_features2,
- isa_names_table[i].feature))
+   /* Never push -mno-avx10.1-{256,512} under -march=native to
+  avoid unnecessary warnings when building librarys.  */
+   else if ((isa_names_table[i].feature != FEATURE_AVX10_1_256)
+&& (isa_names_table[i].feature != FEATURE_AVX10_1_512)
+&& check_avx512_features (cpu_model, cpu_features2,
+  isa_names_table[i].feature))
  options = concat (options, neg_option,
isa_names_table[i].option + 2, NULL);
  }
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 19fa5c107c7..7a5f2676999 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -301,10 +301,10 @@ BDESC (OPTION_MASK_ISA_AVX512BW, 
OPTION_MASK_ISA2_EVEX512, CODE_FOR_avx512bw_sto
 /* AVX512VP2INTERSECT */
 BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT | OPTION_MASK_ISA2_EVEX512, 
CODE_FOR_nothing, "__builtin_ia32_2intersectd512", IX86_BUILTIN_2INTERSECTD512, 
UNKNOWN, (int) VOID_FTYPE_PUHI_PUHI_V16SI_V16SI)
 BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT | OPTION_MASK_ISA2_EVEX512, 
CODE_FOR_nothing, "__builtin_ia32_2intersectq512", IX86_BUILTIN_2INTERSECTQ512, 
UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V8DI_V8DI)
-BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, 
"__builtin_ia32_2intersectd256", IX86_BUILTIN_2INTERSECTD256, UNKNOWN, (int) 
VOID_FTYPE_PUQI_PUQI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, 
"__builtin_ia32_2intersectq256", IX86_BUILTIN_2INTERSECTQ256, UNKNOWN, (int) 
VOID_FTYPE_PUQI_PUQI_V4DI_V4DI)
-BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, 
"__builtin_ia32_2intersectd128", IX86_BUILTIN_2INTERSECTD128, UNKNOWN, (int) 
VOID_FTYPE_PUQI_PUQI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, 
"__builtin_ia32_2intersectq128", IX86_BUILTIN_2INTERSECTQ128, UNKNOWN, (int) 
VOID_FTYPE_PUQI_PUQI_V2DI_V2DI)
+BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512VP2INTERSECT, 
CODE_FOR_nothing, "__builtin_ia32_2intersectd256", IX86_BUILTIN_2INTERSECTD256, 
UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V8SI_V8SI)
+BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512VP2INTERSECT, 
CODE_FOR_nothing, "__builtin_ia32_2intersectq256", IX86_BUILTIN_2INT

[PATCH] Initial support for AVX10.1

[Haochen Jiang]

gcc/ChangeLog:

* common/config/i386/cpuinfo.h (get_available_features):
Add avx10_set and version and detect avx10.1.
(cpu_indicator_init): Handle avx10.1-512.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10_1_256_SET): New.
(OPTION_MASK_ISA2_AVX10_1_256_SET): Ditto.
(OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10.1.
(ix86_handle_option): Handle -mavx10.1-256 and -mavx10.1-512.
Add indicator for explicit no-avx512 and no-avx10.1 options.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_AVX10_1_256 and FEATURE_AVX10_1_512.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
AVX10_1_256 and AVX10_1_512.
* config/i386/cpuid.h (bit_AVX10): New.
(bit_AVX10_256): Ditto.
(bit_AVX10_512): Ditto.
* config/i386/driver-i386.cc (check_avx10_avx512_features): New.
(host_detect_local_cpu): Do not append "-mno-" options under
specific scenarios to avoid emitting a warning.
* config/i386/i386-isa.def
(EVEX512): Add DEF_PTA(EVEX512).
(AVX10_1_256): Add DEF_PTA(AVX10_1_256).
(AVX10_1_512): Add DEF_PTA(AVX10_1_512).
* config/i386/i386-options.cc (isa2_opts): Add -mavx10.1-256 and
-mavx10.1-512.
(ix86_function_specific_save): Save explicit no indicator.
(ix86_function_specific_restore): Restore explicit no indicator.
(ix86_valid_target_attribute_inner_p): Handle avx10.1, avx10.1-256 and
avx10.1-512.
(ix86_valid_target_attribute_tree): Handle avx512 function
attributes with avx10.1 command line option.
(ix86_option_override_internal): Handle AVX10.1 options.
* config/i386/i386.h: Add PTA_EVEX512 for AVX512 target
machines.
* config/i386/i386.opt: Add variable ix86_no_avx512_explicit and
ix86_no_avx10_1_explicit, option -mavx10.1, -mavx10.1-256 and
-mavx10.1-512.
* doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512.
* doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512.
* doc/sourcebuild.texi: Document target avx10.1, avx10.1-256
and avx10.1-512.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_1-1.c: New test.
* gcc.target/i386/avx10_1-10.c: Ditto.
* gcc.target/i386/avx10_1-11.c: Ditto.
* gcc.target/i386/avx10_1-12.c: Ditto.
* gcc.target/i386/avx10_1-13.c: Ditto.
* gcc.target/i386/avx10_1-14.c: Ditto.
* gcc.target/i386/avx10_1-15.c: Ditto.
* gcc.target/i386/avx10_1-16.c: Ditto.
* gcc.target/i386/avx10_1-17.c: Ditto.
* gcc.target/i386/avx10_1-18.c: Ditto.
* gcc.target/i386/avx10_1-19.c: Ditto.
* gcc.target/i386/avx10_1-2.c: Ditto.
* gcc.target/i386/avx10_1-20.c: Ditto.
* gcc.target/i386/avx10_1-21.c: Ditto.
* gcc.target/i386/avx10_1-22.c: Ditto.
* gcc.target/i386/avx10_1-23.c: Ditto.
* gcc.target/i386/avx10_1-3.c: Ditto.
* gcc.target/i386/avx10_1-4.c: Ditto.
* gcc.target/i386/avx10_1-5.c: Ditto.
* gcc.target/i386/avx10_1-6.c: Ditto.
* gcc.target/i386/avx10_1-7.c: Ditto.
* gcc.target/i386/avx10_1-8.c: Ditto.
* gcc.target/i386/avx10_1-9.c: Ditto.
---
 gcc/common/config/i386/cpuinfo.h   |  33 ++
 gcc/common/config/i386/i386-common.cc  |  55 -
 gcc/common/config/i386/i386-cpuinfo.h  |   2 +
 gcc/common/config/i386/i386-isas.h |   3 +
 gcc/config/i386/cpuid.h|   5 +
 gcc/config/i386/driver-i386.cc |  43 ++-
 gcc/config/i386/i386-isa.def   |   3 +
 gcc/config/i386/i386-options.cc| 132 +++--
 gcc/config/i386/i386.h |   2 +-
 gcc/config/i386/i386.opt   |  30 +
 gcc/doc/extend.texi|  15 +++
 gcc/doc/invoke.texi|  17 ++-
 gcc/doc/sourcebuild.texi   |   9 ++
 gcc/testsuite/gcc.target/i386/avx10_1-1.c  |  22 
 gcc/testsuite/gcc.target/i386/avx10_1-10.c |   6 +
 gcc/testsuite/gcc.target/i386/avx10_1-11.c |   6 +
 gcc/testsuite/gcc.target/i386/avx10_1-12.c |   6 +
 gcc/testsuite/gcc.target/i386/avx10_1-13.c |  13 ++
 gcc/testsuite/gcc.target/i386/avx10_1-14.c |  13 ++
 gcc/testsuite/gcc.target/i386/avx10_1-15.c |  13 ++
 gcc/testsuite/gcc.target/i386/avx10_1-16.c |  13 ++
 gcc/testsuite/gcc.target/i386/avx10_1-17.c |  13 ++
 gcc/testsuite/gcc.target/i386/avx10_1-18.c |  13 ++
 gcc/testsuite/gcc.target/i386/avx10_1-19.c |  13 ++
 gcc/testsuite/gcc.target/i386/avx10_1-2.c  |  13 ++
 gcc/testsuite/gcc.target/i386/avx10_1-20.c |  13 ++
 gcc/testsuite/gcc.target/i386/avx10_1-21.c |   6 +
 gcc/testsuite/gcc.target/i386/avx10_1-22.c |  13 ++
 gcc/

[RFC] Intel AVX10.1 Compiler Design and Support

[Haochen Jiang]

Hi all,

This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex512
support, it makes a lot easier to add them comparing to the August version.
Detail for AVX10 is shown below:

Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification 
It describes the Intel Advanced Vector Extensions 10 Instruction Set
Architecture.
https://cdrdv2.intel.com/v1/dl/getContent/784267

The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical Paper
It provides introductory information regarding the converged vector ISA: Intel
Advanced Vector Extensions 10.
https://cdrdv2.intel.com/v1/dl/getContent/784343

Our proposal is to take AVX10.1-256 and AVX10.1-512 as two "virtual" ISAs in
the compiler. AVX10.1-512 will imply AVX10.1-256. They will not enable
anything at first. At the end of the option handling, we will check whether
the two bits are set. If AVX10.1-256 is set, we will set the AVX512 related
ISA bits. AVX10.1-512 will further set EVEX512 ISA bit.

It means that AVX10 options will be separated from the existing AVX512 and the
newly added -m[no-]evex512 options. AVX10 and AVX512 options will control
(enable/disable/set vector size) the AVX512 features underneath independently.
If there’s potential overlap or conflict between AVX10 and AVX512 options,
some rules are provided to define the behavior, which will be described below.

avx10.1 option will be provided as an alias of avx10.1-256.

In the future, the AVX10 options will imply like this:

AVX10.1-256 < AVX10.1-512
 ^ ^
 | |

AVX10.2-256 < AVX10.2-512
 ^ ^
 | |

AVX10.3-256 < AVX10.3-512
 ^ ^
 | |

Each of them will have its own option to enable/disabled corresponding
features. The alias avx10.x will also be provided.

As mentioned in August version RFC, since we lean towards the adoption of
AVX10 instead of AVX512 from now on, we don’t recommend users to combine the
AVX10 and legacy AVX512 options. However, we would like to introduce some
simple rules for user when it comes to combination. 

1. Enabling AVX10 and AVX512 at the same command line with different vector
size will lead to a warning message. The behavior of the compiler will be
enabling AVX10 with longer, i.e., 512 bit vector size.

If the vector sizes are the same (e.g. -mavx10.1-256 -mavx512f -mno-evex512,
-mavx10.1-512 -mavx512f), it will be valid with the corresponding vector size.

2. -mno-avx10.1 option can’t disable any features enabled by AVX512 options or
impact the vector size, and vice versa. The compiler will emit warnings if
necessary.

For the auto dispatch support including function multi versioning, function
attribute usage, the behavior will be identical to compiler options.

If you have any questions, feel free to ask in this thread.

Thx,
Haochen

[PATCH] i386: Fix isa attribute for TI/TF andnot mode

[Haochen Jiang]

Hi all,

This patch aims fo fix the wrong isa attribute which caused regression
on PR111907.

Regtested on x86_64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

gcc/ChangeLog:

PR target/111907
* config/i386/i386.md (avx_noavx512vl): Add missing definition.
* config/i386/sse.md (*andnot3): Change isa attribute from
avx_noavx512f to avx_noavx512vl.

gcc/testsuite/ChangeLog:

PR target/111907
* gcc.target/i386/pr111907.c: New test.
---
 gcc/config/i386/i386.md  | 2 ++
 gcc/config/i386/sse.md   | 2 +-
 gcc/testsuite/gcc.target/i386/pr111907.c | 8 
 3 files changed, 11 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr111907.c

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index ecc74e9994e..8f2f6e5d908 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -919,6 +919,8 @@
 (eq_attr "isa" "avx") (symbol_ref "TARGET_AVX")
 (eq_attr "isa" "avx_noavx512f")
   (symbol_ref "TARGET_AVX && !TARGET_AVX512F")
+(eq_attr "isa" "avx_noavx512vl")
+  (symbol_ref "TARGET_AVX && !TARGET_AVX512VL")
 (eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
 (eq_attr "isa" "avx2") (symbol_ref "TARGET_AVX2")
 (eq_attr "isa" "noavx2") (symbol_ref "!TARGET_AVX2")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e6a5c7911d5..33198756bb0 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -5169,7 +5169,7 @@
   output_asm_insn (buf, operands);
   return "";
 }
-  [(set_attr "isa" "noavx,avx_noavx512f,avx512vl,avx512f_512")
+  [(set_attr "isa" "noavx,avx_noavx512vl,avx512vl,avx512f_512")
(set_attr "addr" "*,gpr16,*,*")
(set_attr "type" "sselog")
(set (attr "prefix_data16")
diff --git a/gcc/testsuite/gcc.target/i386/pr111907.c 
b/gcc/testsuite/gcc.target/i386/pr111907.c
new file mode 100644
index 000..5275e9400ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr111907.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -mno-evex512" } */
+
+_Float128
+foo (_Float128 d, _Float128 e)
+{
+  return __builtin_copysignf128 (d, e);
+}
-- 
2.31.1

[PATCH 3/4] [PATCH 3/3] Change internal intrin call for AVX512 intrins

[Haochen Jiang]

gcc/ChangeLog:

* config/i386/avx512bf16vlintrin.h
(_mm_avx512_castsi128_ps): New.
(_mm256_avx512_castsi256_ps): Ditto.
(_mm_avx512_slli_epi32): Ditto.
(_mm256_avx512_slli_epi32): Ditto.
(_mm_avx512_cvtepi16_epi32): Ditto.
(_mm256_avx512_cvtepi16_epi32): Ditto.
(__attribute__): Change intrin call.
* config/i386/avx512bwintrin.h
(_mm_avx512_set_epi32): New.
(_mm_avx512_set_epi16): Ditto.
(_mm_avx512_set_epi8): Ditto.
(__attribute__): Change intrin call.
* config/i386/avx512fp16intrin.h: Ditto.
* config/i386/avx512fp16vlintrin.h
(_mm_avx512_set1_ps): New.
(_mm256_avx512_set1_ps): Ditto.
(_mm_avx512_and_si128): Ditto.
(_mm256_avx512_and_si256): Ditto.
(__attribute__): Change intrin call.
* config/i386/avx512vlbwintrin.h
(_mm_avx512_set1_epi32): New.
(_mm_avx512_set1_epi16): Ditto.
(_mm_avx512_set1_epi8): Ditto.
(_mm256_avx512_set_epi16): Ditto.
(_mm256_avx512_set_epi8): Ditto.
(_mm256_avx512_set1_epi16): Ditto.
(_mm256_avx512_set1_epi32): Ditto.
(_mm256_avx512_set1_epi8): Ditto.
(_mm_avx512_max_epi16): Ditto.
(_mm_avx512_min_epi16): Ditto.
(_mm_avx512_max_epu16): Ditto.
(_mm_avx512_min_epu16): Ditto.
(_mm_avx512_max_epi8): Ditto.
(_mm_avx512_min_epi8): Ditto.
(_mm_avx512_max_epu8): Ditto.
(_mm_avx512_min_epu8): Ditto.
(_mm256_avx512_max_epi16): Ditto.
(_mm256_avx512_min_epi16): Ditto.
(_mm256_avx512_max_epu16): Ditto.
(_mm256_avx512_min_epu16): Ditto.
(_mm256_avx512_insertf128_ps): Ditto.
(_mm256_avx512_extractf128_pd): Ditto.
(_mm256_avx512_extracti128_si256): Ditto.
(_MM256_AVX512_REDUCE_OPERATOR_BASIC_EPI16): Ditto.
(_MM256_AVX512_REDUCE_OPERATOR_MAX_MIN_EP16): Ditto.
(_MM256_AVX512_REDUCE_OPERATOR_BASIC_EPI8): Ditto.
(_MM256_AVX512_REDUCE_OPERATOR_MAX_MIN_EP8): Ditto.
(__attribute__): Change intrin call.
---
 gcc/config/i386/avx512bf16vlintrin.h |  58 -
 gcc/config/i386/avx512bwintrin.h |  26 +++
 gcc/config/i386/avx512fp16intrin.h   |   2 +-
 gcc/config/i386/avx512fp16vlintrin.h |  54 +++--
 gcc/config/i386/avx512vlbwintrin.h   | 338 +++
 5 files changed, 409 insertions(+), 69 deletions(-)

diff --git a/gcc/config/i386/avx512bf16vlintrin.h 
b/gcc/config/i386/avx512bf16vlintrin.h
index 517544c5b89..78c001f55ad 100644
--- a/gcc/config/i386/avx512bf16vlintrin.h
+++ b/gcc/config/i386/avx512bf16vlintrin.h
@@ -45,6 +45,44 @@ typedef __bf16 __m128bh __attribute__ ((__vector_size__ 
(16), __may_alias__));
 
 typedef __bf16 __bfloat16;
 
+extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
+_mm_avx512_castsi128_ps(__m128i __A)
+{
+  return (__m128) __A;
+}
+
+extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
+_mm256_avx512_castsi256_ps (__m256i __A)
+{
+  return (__m256) __A;
+}
+
+extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
+_mm_avx512_slli_epi32 (__m128i __A, int __B)
+{
+  return (__m128i)__builtin_ia32_pslldi128 ((__v4si)__A, __B);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_avx512_slli_epi32 (__m256i __A, int __B)
+{
+  return (__m256i)__builtin_ia32_pslldi256 ((__v8si)__A, __B);
+}
+
+extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
+_mm_avx512_cvtepi16_epi32 (__m128i __X)
+{
+  return (__m128i) __builtin_ia32_pmovsxwd128 ((__v8hi)__X);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_avx512_cvtepi16_epi32 (__m128i __X)
+{
+  return (__m256i) __builtin_ia32_pmovsxwd256 ((__v8hi)__X);
+}
+
 #define _mm256_cvtneps_pbh(A) \
   (__m128bh) __builtin_ia32_cvtneps2bf16_v8sf (A)
 #define _mm_cvtneps_pbh(A) \
@@ -182,23 +220,23 @@ extern __inline __m128
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_cvtpbh_ps (__m128bh __A)
 {
-  return (__m128)_mm_castsi128_ps ((__m128i)_mm_slli_epi32 (
-(__m128i)_mm_cvtepi16_epi32 ((__m128i)__A), 16));
+  return (__m128)_mm_avx512_castsi128_ps ((__m128i)_mm_avx512_slli_epi32 (
+(__m128i)_mm_avx512_cvtepi16_epi32 ((__m128i)__A), 16));
 }
 
 extern __inline __m256
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm256_cvtpbh_ps (__m128bh __A)
 {
-  return (__m256)_mm256_castsi256_ps ((__m256i)_mm256_slli_epi32 (
-(__m256i)_mm256_cvtepi16_epi32 ((__m128i)__A), 16));
+  return (__m256)_mm256_avx512_castsi256_ps ((__m256i)_mm256_avx512_slli_epi32 
(
+(__m256i)_mm256_avx512_cvtepi16_epi32 ((__m128i)__A), 16));
 }
 
 extern __inline __m128
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)

[PATCH 2/4] [PATCH 2/3] Change internal intrin call for AVX512 intrins

[Haochen Jiang]

gcc/ChangeLog:

* config/i386/avx512bf16vlintrin.h: Change intrin call.
* config/i386/avx512fintrin.h
(_mm_avx512_undefined_ps): New.
(_mm_avx512_undefined_pd): Ditto.
(__attribute__): Change intrin call.
* config/i386/avx512vbmivlintrin.h: Ditto.
* config/i386/avx512vlbwintrin.h: Ditto.
* config/i386/avx512vldqintrin.h: Ditto.
* config/i386/avx512vlintrin.h
(_mm_avx512_undefined_si128): New.
(_mm256_avx512_undefined_ps): Ditto.
(_mm256_avx512_undefined_pd): Ditto.
(_mm256_avx512_undefined_si256): Ditto.
(__attribute__): Change intrin call.
---
 gcc/config/i386/avx512bf16vlintrin.h |   2 +-
 gcc/config/i386/avx512fintrin.h  |  24 +-
 gcc/config/i386/avx512vbmivlintrin.h |   8 +-
 gcc/config/i386/avx512vlbwintrin.h   |  12 +--
 gcc/config/i386/avx512vldqintrin.h   |  10 +--
 gcc/config/i386/avx512vlintrin.h | 110 ++-
 6 files changed, 113 insertions(+), 53 deletions(-)

diff --git a/gcc/config/i386/avx512bf16vlintrin.h 
b/gcc/config/i386/avx512bf16vlintrin.h
index 6e8a6a09511..517544c5b89 100644
--- a/gcc/config/i386/avx512bf16vlintrin.h
+++ b/gcc/config/i386/avx512bf16vlintrin.h
@@ -174,7 +174,7 @@ _mm_cvtness_sbh (float __A)
 {
   __v4sf __V = {__A, 0, 0, 0};
   __v8bf __R = __builtin_ia32_cvtneps2bf16_v4sf_mask ((__v4sf)__V,
-  (__v8bf)_mm_undefined_si128 (), (__mmask8)-1);
+  (__v8bf)_mm_avx512_undefined_si128 (), (__mmask8)-1);
   return __R[0];
 }
 
diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h
index 530be29eefa..90a00bec09a 100644
--- a/gcc/config/i386/avx512fintrin.h
+++ b/gcc/config/i386/avx512fintrin.h
@@ -59,6 +59,26 @@ typedef enum
when calling AVX512 intrins implemented with these intrins under no-evex512
function attribute.  All AVX512 intrins calling those AVX2 intrins or
before will change their calls to these AVX512 version.  */
+extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
+_mm_avx512_undefined_ps (void)
+{
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Winit-self"
+  __m128 __Y = __Y;
+#pragma GCC diagnostic pop
+  return __Y;
+}
+
+extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
+_mm_avx512_undefined_pd (void)
+{
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Winit-self"
+  __m128d __Y = __Y;
+#pragma GCC diagnostic pop
+  return __Y;
+}
+
 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
 _mm_avx512_setzero_ps (void)
 {
@@ -674,13 +694,13 @@ _mm_maskz_scalef_round_ss (__mmask8 __U, __m128 __A, 
__m128 __B, const int __R)
 #define _mm_scalef_round_sd(A, B, C)   \
   ((__m128d)   \
__builtin_ia32_scalefsd_mask_round ((A), (B),   \
-  (__v2df) _mm_undefined_pd (),\
+  (__v2df) _mm_avx512_undefined_pd (), 
\
   -1, (C)))
 
 #define _mm_scalef_round_ss(A, B, C)   \
   ((__m128)\
__builtin_ia32_scalefss_mask_round ((A), (B),   \
-  (__v4sf) _mm_undefined_ps (),\
+  (__v4sf) _mm_avx512_undefined_ps (), 
\
   -1, (C)))
 
 #define _mm_mask_scalef_round_sd(W, U, A, B, C)
\
diff --git a/gcc/config/i386/avx512vbmivlintrin.h 
b/gcc/config/i386/avx512vbmivlintrin.h
index 270e9406db5..acec23b742f 100644
--- a/gcc/config/i386/avx512vbmivlintrin.h
+++ b/gcc/config/i386/avx512vbmivlintrin.h
@@ -62,7 +62,7 @@ _mm256_multishift_epi64_epi8 (__m256i __X, __m256i __Y)
   return (__m256i) __builtin_ia32_vpmultishiftqb256_mask ((__v32qi) __X,
  (__v32qi) __Y,
  (__v32qi)
- 
_mm256_undefined_si256 (),
+ 
_mm256_avx512_undefined_si256 (),
  (__mmask32) -1);
 }
 
@@ -94,7 +94,7 @@ _mm_multishift_epi64_epi8 (__m128i __X, __m128i __Y)
   return (__m128i) __builtin_ia32_vpmultishiftqb128_mask ((__v16qi) __X,
  (__v16qi) __Y,
  (__v16qi)
- _mm_undefined_si128 
(),
+ 
_mm_avx512_undefined_si128 (),
  (__mmask16) -

[PATCH 4/4] Push no-evex512 target for 128/256 bit intrins

[Haochen Jiang]

gcc/ChangeLog:

PR target/111889
* config/i386/avx512bf16intrin.h: Push no-evex512 target.
* config/i386/avx512bf16vlintrin.h: Ditto.
* config/i386/avx512bitalgvlintrin.h: Ditto.
* config/i386/avx512bwintrin.h: Ditto.
* config/i386/avx512dqintrin.h: Ditto.
* config/i386/avx512fintrin.h: Ditto.
* config/i386/avx512fp16intrin.h: Ditto.
* config/i386/avx512fp16vlintrin.h: Ditto.
* config/i386/avx512ifmavlintrin.h: Ditto.
* config/i386/avx512vbmi2vlintrin.h: Ditto.
* config/i386/avx512vbmivlintrin.h: Ditto.
* config/i386/avx512vlbwintrin.h: Ditto.
* config/i386/avx512vldqintrin.h: Ditto.
* config/i386/avx512vlintrin.h: Ditto.
* config/i386/avx512vnnivlintrin.h: Ditto.
* config/i386/avx512vp2intersectvlintrin.h: Ditto.
* config/i386/avx512vpopcntdqvlintrin.h: Ditto.

gcc/testsuite/ChangeLog:

PR target/111889
* gcc.target/i386/pr111889.c: New test.
---
 gcc/config/i386/avx512bf16intrin.h   |  4 ++--
 gcc/config/i386/avx512bf16vlintrin.h |  4 ++--
 gcc/config/i386/avx512bitalgvlintrin.h   |  4 ++--
 gcc/config/i386/avx512bwintrin.h |  4 ++--
 gcc/config/i386/avx512dqintrin.h |  4 ++--
 gcc/config/i386/avx512fintrin.h  |  4 ++--
 gcc/config/i386/avx512fp16intrin.h   |  4 ++--
 gcc/config/i386/avx512fp16vlintrin.h |  4 ++--
 gcc/config/i386/avx512ifmavlintrin.h |  4 ++--
 gcc/config/i386/avx512vbmi2vlintrin.h|  4 ++--
 gcc/config/i386/avx512vbmivlintrin.h |  4 ++--
 gcc/config/i386/avx512vlbwintrin.h   |  4 ++--
 gcc/config/i386/avx512vldqintrin.h   |  4 ++--
 gcc/config/i386/avx512vlintrin.h |  6 +++---
 gcc/config/i386/avx512vnnivlintrin.h |  4 ++--
 gcc/config/i386/avx512vp2intersectvlintrin.h |  5 +++--
 gcc/config/i386/avx512vpopcntdqvlintrin.h|  5 +++--
 gcc/testsuite/gcc.target/i386/pr111889.c | 10 ++
 18 files changed, 47 insertions(+), 35 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr111889.c

diff --git a/gcc/config/i386/avx512bf16intrin.h 
b/gcc/config/i386/avx512bf16intrin.h
index 94ccbf6389f..5084a8c23ed 100644
--- a/gcc/config/i386/avx512bf16intrin.h
+++ b/gcc/config/i386/avx512bf16intrin.h
@@ -28,9 +28,9 @@
 #ifndef _AVX512BF16INTRIN_H_INCLUDED
 #define _AVX512BF16INTRIN_H_INCLUDED
 
-#ifndef __AVX512BF16__
+#if !defined (__AVX512BF16__) || defined (__EVEX512__)
 #pragma GCC push_options
-#pragma GCC target("avx512bf16")
+#pragma GCC target("avx512bf16,no-evex512")
 #define __DISABLE_AVX512BF16__
 #endif /* __AVX512BF16__ */
 
diff --git a/gcc/config/i386/avx512bf16vlintrin.h 
b/gcc/config/i386/avx512bf16vlintrin.h
index 78c001f55ad..a389bfe7cec 100644
--- a/gcc/config/i386/avx512bf16vlintrin.h
+++ b/gcc/config/i386/avx512bf16vlintrin.h
@@ -28,9 +28,9 @@
 #ifndef _AVX512BF16VLINTRIN_H_INCLUDED
 #define _AVX512BF16VLINTRIN_H_INCLUDED
 
-#if !defined(__AVX512VL__) || !defined(__AVX512BF16__)
+#if !defined(__AVX512VL__) || !defined(__AVX512BF16__) || defined (__EVEX512__)
 #pragma GCC push_options
-#pragma GCC target("avx512bf16,avx512vl")
+#pragma GCC target("avx512bf16,avx512vl,no-evex512")
 #define __DISABLE_AVX512BF16VL__
 #endif /* __AVX512BF16__ */
 
diff --git a/gcc/config/i386/avx512bitalgvlintrin.h 
b/gcc/config/i386/avx512bitalgvlintrin.h
index 39301625601..327425ef0cb 100644
--- a/gcc/config/i386/avx512bitalgvlintrin.h
+++ b/gcc/config/i386/avx512bitalgvlintrin.h
@@ -28,9 +28,9 @@
 #ifndef _AVX512BITALGVLINTRIN_H_INCLUDED
 #define _AVX512BITALGVLINTRIN_H_INCLUDED
 
-#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__)
+#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) || defined 
(__EVEX512__)
 #pragma GCC push_options
-#pragma GCC target("avx512bitalg,avx512vl")
+#pragma GCC target("avx512bitalg,avx512vl,no-evex512")
 #define __DISABLE_AVX512BITALGVL__
 #endif /* __AVX512BITALGVL__ */
 
diff --git a/gcc/config/i386/avx512bwintrin.h b/gcc/config/i386/avx512bwintrin.h
index 45a46936aef..d5ce79fd073 100644
--- a/gcc/config/i386/avx512bwintrin.h
+++ b/gcc/config/i386/avx512bwintrin.h
@@ -28,9 +28,9 @@
 #ifndef _AVX512BWINTRIN_H_INCLUDED
 #define _AVX512BWINTRIN_H_INCLUDED
 
-#ifndef __AVX512BW__
+#if !defined (__AVX512BW__) || defined (__EVEX512__)
 #pragma GCC push_options
-#pragma GCC target("avx512bw")
+#pragma GCC target("avx512bw,no-evex512")
 #define __DISABLE_AVX512BW__
 #endif /* __AVX512BW__ */
 
diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h
index fb0aea70280..55a5d9fee9c 100644
--- a/gcc/config/i386/avx512dqintrin.h
+++ b/gcc/config/i386/avx512dqintrin.h
@@ -28,9 +28,9 @@
 #ifndef _AVX512DQINTRIN_H_INCLUDED
 #define _AVX512DQINTRIN_H_INCLUDED
 
-#ifndef __AVX512DQ__
+#if !defined (__AVX512DQ__) || defined (__EVEX512__)
 #pragma GCC push_options
-#pragma GCC target("avx512dq")
+#pragma GCC target("avx512dq,no-evex512")

[PATCH 0/4] Fix no-evex512 function attribute

[Haochen Jiang]

Hi all,

These four patches are going to fix no-evex512 function attribute. The detail
of the issue comes following:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111889

My proposal for this problem is to also push "no-evex512" when defining
128/256 intrins in AVX512.

Besides, I added some new intrins to support the current AVX512 intrins.
The newly added  _mm{,256}_avx512* intrins are duplicated from their
_mm{,256}_* forms from AVX2 or before. We need to add them to prevent target
option mismatch when calling AVX512 intrins implemented with these intrins
under no-evex512 function attribute. All AVX512 intrins calling those AVX2
intrins or before will change their calls to these newly added AVX512 version.

This will solve the problem when we are using no-evex512 attribute with
AVX512 related intrins. But it will not solve target option mismatch when we
are calling AVX2 intrins or before with no-evex512 function attribute since as
mentioned in PR111889, it actually comes from a legacy issue. Therefore, we
are not expecting that usage.

Regtested on x86_64-pc-linux-gnu. Ok for trunk?

Thx,
Haochen

[PATCH] Fix incorrect option mask and avx512cd target push

[Haochen Jiang]

Hi all,

This patch fixed two obvious bug in current evex512 implementation.

Also, I moved AVX512CD+AVX512VL part out of the AVX512VL to avoid
accidental handle miss in avx512cd in the future.

Ok for trunk?

BRs,
Haochen

gcc/ChangeLog:

* config/i386/avx512cdintrin.h (target): Push evex512 for
avx512cd.
* config/i386/avx512vlintrin.h (target): Split avx512cdvl part
out from avx512vl.
* config/i386/i386-builtin.def (BDESC): Do not check evex512
for builtins not needed.
---
 gcc/config/i386/avx512cdintrin.h |2 +-
 gcc/config/i386/avx512vlintrin.h | 1792 +++---
 gcc/config/i386/i386-builtin.def |4 +-
 3 files changed, 899 insertions(+), 899 deletions(-)

diff --git a/gcc/config/i386/avx512cdintrin.h b/gcc/config/i386/avx512cdintrin.h
index a5f5eabb68d..56a786aa9a3 100644
--- a/gcc/config/i386/avx512cdintrin.h
+++ b/gcc/config/i386/avx512cdintrin.h
@@ -30,7 +30,7 @@
 
 #ifndef __AVX512CD__
 #pragma GCC push_options
-#pragma GCC target("avx512cd")
+#pragma GCC target("avx512cd,evex512")
 #define __DISABLE_AVX512CD__
 #endif /* __AVX512CD__ */
 
diff --git a/gcc/config/i386/avx512vlintrin.h b/gcc/config/i386/avx512vlintrin.h
index 08e49e8d8ab..a40aa91b948 100644
--- a/gcc/config/i386/avx512vlintrin.h
+++ b/gcc/config/i386/avx512vlintrin.h
@@ -8396,1281 +8396,1003 @@ _mm_mask_min_epu32 (__m128i __W, __mmask8 __M, 
__m128i __A,
  (__v4si) __W, __M);
 }
 
-#ifndef __AVX512CD__
-#pragma GCC push_options
-#pragma GCC target("avx512vl,avx512cd")
-#define __DISABLE_AVX512VLCD__
-#endif
-
-extern __inline __m128i
+extern __inline __m256d
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_broadcastmb_epi64 (__mmask8 __A)
+_mm256_mask_unpacklo_pd (__m256d __W, __mmask8 __U, __m256d __A,
+__m256d __B)
 {
-  return (__m128i) __builtin_ia32_broadcastmb128 (__A);
+  return (__m256d) __builtin_ia32_unpcklpd256_mask ((__v4df) __A,
+   (__v4df) __B,
+   (__v4df) __W,
+   (__mmask8) __U);
 }
 
-extern __inline __m256i
+extern __inline __m256d
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm256_broadcastmb_epi64 (__mmask8 __A)
+_mm256_maskz_unpacklo_pd (__mmask8 __U, __m256d __A, __m256d __B)
 {
-  return (__m256i) __builtin_ia32_broadcastmb256 (__A);
+  return (__m256d) __builtin_ia32_unpcklpd256_mask ((__v4df) __A,
+   (__v4df) __B,
+   (__v4df)
+   _mm256_setzero_pd (),
+   (__mmask8) __U);
 }
 
-extern __inline __m128i
+extern __inline __m128d
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm_broadcastmw_epi32 (__mmask16 __A)
+_mm_mask_unpacklo_pd (__m128d __W, __mmask8 __U, __m128d __A,
+ __m128d __B)
 {
-  return (__m128i) __builtin_ia32_broadcastmw128 (__A);
+  return (__m128d) __builtin_ia32_unpcklpd128_mask ((__v2df) __A,
+   (__v2df) __B,
+   (__v2df) __W,
+   (__mmask8) __U);
 }
 
-extern __inline __m256i
+extern __inline __m128d
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm256_broadcastmw_epi32 (__mmask16 __A)
+_mm_maskz_unpacklo_pd (__mmask8 __U, __m128d __A, __m128d __B)
 {
-  return (__m256i) __builtin_ia32_broadcastmw256 (__A);
+  return (__m128d) __builtin_ia32_unpcklpd128_mask ((__v2df) __A,
+   (__v2df) __B,
+   (__v2df)
+   _mm_setzero_pd (),
+   (__mmask8) __U);
 }
 
-extern __inline __m256i
+extern __inline __m256
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm256_lzcnt_epi32 (__m256i __A)
+_mm256_mask_unpacklo_ps (__m256 __W, __mmask8 __U, __m256 __A,
+__m256 __B)
 {
-  return (__m256i) __builtin_ia32_vplzcntd_256_mask ((__v8si) __A,
-(__v8si)
-_mm256_setzero_si256 (),
-(__mmask8) -1);
+  return (__m256) __builtin_ia32_unpcklps256_mask ((__v8sf) __A,
+  (__v8sf) __B,
+  (__v8sf) __W,
+  (__mmask8) __U);
 }
 
-extern __inline __m256i
+extern __inline __m256d
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
-_mm256_mas

[gccwwwdocs PATCH] gcc-13/14: Mention Intel new ISA and march support

[Haochen Jiang]

Hi all,

This patch mentions recent update for x86-64 backend, including ISAs enabled
update on previous introduced CPU and newly introduced options/ISAs/CPUs.

Ok for wwwdocs?

Thx,
Haochen

---
 htdocs/gcc-13/changes.html |  8 
 htdocs/gcc-14/changes.html | 19 +++
 2 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 10c54689..8ef3d639 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -579,13 +579,13 @@ You may also want to check out our
   
   GCC now supports the Intel CPU named Sierra Forest through
 -march=sierraforest.
-The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT and
-CMPccXADD ISA extensions.
+The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
+ENQCMD and UINTR ISA extensions.
   
   GCC now supports the Intel CPU named Grand Ridge through
 -march=grandridge.
-The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD
-and RAO-INT ISA extensions.
+The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
+ENQCMD, UINTR and RAO-INT ISA extensions.
   
   GCC now supports the Intel CPU named Emerald Rapids through
 -march=emeraldrapids.
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index c817dde4..4f71061f 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -186,6 +186,10 @@ a work-in-progress.
 
 IA-32/x86-64
 
+  New compiler option -m[no-]evex512 was added.
+  The compiler switch enables/disables 512 bit vector and 64 bit mask
+  register. It will be default on if AVX512F is enabled.
+  
   New ISA extension support for Intel AVX-VNNI-INT16 was added.
   AVX-VNNI-INT16 intrinsics are available via the 
-mavxvnniint16
   compiler switch.
@@ -202,6 +206,16 @@ a work-in-progress.
   SM4 intrinsics are available via the -msm4
   compiler switch.
   
+  New ISA extension support for Intel USER_MSR was added.
+  USER_MSR intrinsics are available via the -muser_msr
+  compiler switch.
+  
+  GCC now supports the Intel CPU named Clearwater Forest through
+-march=clearwaterforest.
+Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16,
+SHA512, SM3, SM4, USER_MSR and PREFETCHI ISA extensions.
+extensions.
+  
   GCC now supports the Intel CPU named Arrow Lake through
 -march=arrowlake.
 Based on Alder Lake, the switch further enables the AVX-IFMA,
@@ -216,6 +230,11 @@ a work-in-progress.
 -march=lunarlake.
 Lunar Lake is based on Arrow Lake S.
   
+  GCC now supports the Intel CPU named Panther Lake through
+-march=pantherlake.
+Based on Arrow Lake S, the switch further enables the PREFETCHI ISA
+extensions.
+  
 
 
 
-- 
2.31.1