[PATCH, i386] Add native detection for VIA C7 and Eden CPUs

[J. Mayer]

The following patch adds native detection for C7, Eden "Esther" and
Eden "Nehemiah" VIA CPUs.

Please CC me to any comment / review / change request.

---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 14b8030..55afd8b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-06-21  Jocelyn Mayer  
+
+   * config/i386/driver-i386.c (host_detect_local_cpu): Set
+   PROCESSOR_PENTIUMPRO for signature_CENTAUR_ebx family >= 9.
+   : Pass c7 or nehemiah for
+   signature_CENTAUR_ebx.
+
 2016-06-21  Jakub Jelinek  
 
PR tree-optimization/71588
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-
i386.c
index 9f44ee8..22a8f28 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -653,10 +653,7 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
case 6:
  if (has_longmode)
processor = PROCESSOR_K8;
- else if (model > 9)
-   /* Use the default detection procedure.  */
-   ;
- else if (model == 9)
+ else if (model >= 9)
processor = PROCESSOR_PENTIUMPRO;
  else if (model >= 6)
processor = PROCESSOR_I486;
@@ -818,15 +815,27 @@ const char *host_detect_local_cpu (int argc,
const char **argv)
   as all the CPUs below are 32-bit only.  */
cpu = "x86-64";
  else if (has_sse3)
-   /* It is Core Duo.  */
-   cpu = "pentium-m";
+   {
+ if (vendor == signature_CENTAUR_ebx)
+   /* C7 / Eden "Esther" */
+   cpu = "c7";
+ else
+   /* It is Core Duo.  */
+   cpu = "pentium-m";
+   }
  else if (has_sse2)
/* It is Pentium M.  */
cpu = "pentium-m";
  else if (has_sse)
{
  if (vendor == signature_CENTAUR_ebx)
-   cpu = "c3-2";
+   {
+ if (model >= 9)
+   /* Eden "Nehemiah" */
+   cpu = "nehemiah";
+ else
+   cpu = "c3-2";
+   }
  else
/* It is Pentium III.  */
cpu = "pentium3";

[PATCH, i386][Updated] Add native support for VIA C7, Eden and Nano CPUs

[J. Mayer]

The following patch adds support and native detection for C7, Eden
"Samuel2", Eden "Nehemiah", Eden "Esther", Eden x2, Eden x4, Nano 1xxx,
Nano 2xxx, Nano 3xxx, Nano x2 and Nano x4 VIA CPUs.

This patch has been updated against current repository.
It contains documentation and Changelog updates.

Please CC me to any comment / review / change request.

---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2650405..05b450a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2016-06-16  Jocelyn Mayer 
+
+   * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Set
+   PROCESSOR_K8 for signature_CENTAUR_ebx with has_longmode.
+   : Pass nano-3000, nano, eden-x2 or k8 for
+   signature_CENTAUR_ebx.
+   : Pass c7, nehemiah or samuel-2 for
signature_CENTAUR_ebx.
+   * gcc/config/i386/i386.c (ix86_option_override_internal): Add
+   definitions for VIA c7, samuel-2, nehemiah, esther, eden-x2,
eden-x4,
+   nano, nano-1000, nano-2000, nano-3000, nano-x2 and nano-x4.
+   * gcc/doc/invoke.texi: Document new VIA -march entries.
+
 2016-06-15  Michael Meissner  
 
* config/rs6000/vsx.md (VSINT_84): Add DImode to enable loading
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-
i386.c
index a9d5135..d2c4c4c 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -651,7 +651,9 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
  break;
 
case 6:
- if (model > 9 || has_longmode)
+ if (has_longmode)
+   processor = PROCESSOR_K8;
+ else if (model > 9)
/* Use the default detection procedure.  */
;
  else if (model == 9)
@@ -869,9 +871,30 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
cpu = "athlon";
   break;
 case PROCESSOR_K8:
-  if (arch && has_sse3)
-   cpu = "k8-sse3";
+  if (arch)
+   {
+ if (vendor == signature_CENTAUR_ebx)
+   {
+ if (has_sse4_1)
+   /* Nano 3000 | Nano dual / quad core | Eden X4 */
+   cpu = "nano-3000";
+ else if (has_ssse3)
+   /* Nano 1000 | Nano 2000 */
+   cpu = "nano";
+ else if (has_sse3)
+   /* Eden X2 */
+   cpu = "eden-x2";
+ else
+   /* Default to k8 */
+   cpu = "k8";
+   }
+ else if (has_sse3)
+   cpu = "k8-sse3";
+ else
+   cpu = "k8";
+   }
   else
+   /* For -mtune, we default to -mtune=k8 */
cpu = "k8";
   break;
 case PROCESSOR_AMDFAM10:
@@ -903,7 +926,22 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
   /* Use something reasonable.  */
   if (arch)
{
- if (has_ssse3)
+ if (vendor == signature_CENTAUR_ebx)
+   {
+ if (has_sse3) {
+   /* C7 / Eden "Esther" */
+   cpu = "c7";
+ } else if (has_sse) {
+   /* Eden "Nehemiah" */
+   cpu = "nehemiah";
+ } else if (has_3dnow) {
+   /* Eden "Samuel2" */
+   cpu = "samuel-2";
+ } else {
+   /* We have no idea: default to generic i386 */
+ }
+   }
+ else if (has_ssse3)
cpu = "core2";
  else if (has_sse3)
{
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index c5e5e12..3c88912 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -4783,8 +4783,15 @@ ix86_option_override_internal (bool main_args_p,
   {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
   {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
   {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
+  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
   {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
   {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
   {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
   {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX |
PTA_FXSR},
@@ -4915,6 +4922,30 @@ ix86_option_override_internal (bool main_args_p,
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+  {"eden-x2", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_FXSR},
+  

[PATCH, i386][resend] Add native support for VIA C7, Eden and Nano CPUs

[J. Mayer]

The following patch adds support and native detection for C7, Eden
"Samuel2", Eden "Nehemiah", Eden "Esther", Eden x2, Eden x4, Nano 1xxx,
Nano 2xxx, Nano 3xxx, Nano x2 and Nano x4 VIA CPUs.

Sorry for the bogus character encoding of my previous mail.

Please CC me to any comment / review / change request.

---

diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-
i386.c
index a9d5135..d2c4c4c 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -651,7 +651,9 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
  break;
 
case 6:
- if (model > 9 || has_longmode)
+ if (has_longmode)
+   processor = PROCESSOR_K8;
+ else if (model > 9)
/* Use the default detection procedure.  */
;
  else if (model == 9)
@@ -869,9 +871,30 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
cpu = "athlon";
   break;
 case PROCESSOR_K8:
-  if (arch && has_sse3)
-   cpu = "k8-sse3";
+  if (arch)
+   {
+ if (vendor == signature_CENTAUR_ebx)
+   {
+ if (has_sse4_1)
+   /* Nano 3000 | Nano dual / quad core | Eden X4 */
+   cpu = "nano-3000";
+ else if (has_ssse3)
+   /* Nano 1000 | Nano 2000 */
+   cpu = "nano";
+ else if (has_sse3)
+   /* Eden X2 */
+   cpu = "eden-x2";
+ else
+   /* Default to k8 */
+   cpu = "k8";
+   }
+ else if (has_sse3)
+   cpu = "k8-sse3";
+ else
+   cpu = "k8";
+   }
   else
+   /* For -mtune, we default to -mtune=k8 */
cpu = "k8";
   break;
 case PROCESSOR_AMDFAM10:
@@ -903,7 +926,22 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
   /* Use something reasonable.  */
   if (arch)
{
- if (has_ssse3)
+ if (vendor == signature_CENTAUR_ebx)
+   {
+ if (has_sse3) {
+   /* C7 / Eden "Esther" */
+   cpu = "c7";
+ } else if (has_sse) {
+   /* Eden "Nehemiah" */
+   cpu = "nehemiah";
+ } else if (has_3dnow) {
+   /* Eden "Samuel2" */
+   cpu = "samuel-2";
+ } else {
+   /* We have no idea: default to generic i386 */
+ }
+   }
+ else if (has_ssse3)
cpu = "core2";
  else if (has_sse3)
{
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index c5e5e12..3c88912 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -4783,8 +4783,15 @@ ix86_option_override_internal (bool main_args_p,
   {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
   {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
   {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
+  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
   {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
   {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
   {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
   {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX |
PTA_FXSR},
@@ -4915,6 +4922,30 @@ ix86_option_override_internal (bool main_args_p,
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+  {"eden-x2", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_FXSR},
+  {"eden-x4", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-1000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-2000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-3000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x2", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x4", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | 

[PATCH, i386][updated] Add native support for VIA C7, Eden and Nano CPUs

[J. Mayer]

The following patch adds support and native detection for C7, Eden
"Samuel2", Eden "Nehemiah", Eden "Esther", Eden x2, Eden x4, Nano 1xxx,
Nano 2xxx, Nano 3xxx, Nano x2 and Nano x4 VIA CPUs.

Please CC me to any comment / review / change request.

---

diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-
i386.c
index a9d5135..d2c4c4c 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -651,7 +651,9 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
  break;
 
case 6:
- if (model > 9 || has_longmode)
+ if (has_longmode)
+   processor = PROCESSOR_K8;
+ else if (model > 9)
/* Use the default detection procedure.  */
;
  else if (model == 9)
@@ -869,9 +871,30 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
cpu = "athlon";
   break;
 case PROCESSOR_K8:
-  if (arch && has_sse3)
-   cpu = "k8-sse3";
+  if (arch)
+   {
+ if (vendor == signature_CENTAUR_ebx)
+   {
+ if (has_sse4_1)
+   /* Nano 3000 | Nano dual / quad core | Eden X4 */
+   cpu = "nano-3000";
+ else if (has_ssse3)
+   /* Nano 1000 | Nano 2000 */
+   cpu = "nano";
+ else if (has_sse3)
+   /* Eden X2 */
+   cpu = "eden-x2";
+ else
+   /* Default to k8 */
+   cpu = "k8";
+   }
+ else if (has_sse3)
+   cpu = "k8-sse3";
+ else
+   cpu = "k8";
+   }
   else
+   /* For -mtune, we default to -mtune=k8 */
cpu = "k8";
   break;
 case PROCESSOR_AMDFAM10:
@@ -903,7 +926,22 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
   /* Use something reasonable.  */
   if (arch)
{
- if (has_ssse3)
+ if (vendor == signature_CENTAUR_ebx)
+   {
+ if (has_sse3) {
+   /* C7 / Eden "Esther" */
+   cpu = "c7";
+ } else if (has_sse) {
+   /* Eden "Nehemiah" */
+   cpu = "nehemiah";
+ } else if (has_3dnow) {
+   /* Eden "Samuel2" */
+   cpu = "samuel-2";
+ } else {
+   /* We have no idea: default to generic i386 */
+ }
+   }
+ else if (has_ssse3)
cpu = "core2";
  else if (has_sse3)
{
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index c5e5e12..3c88912 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -4783,8 +4783,15 @@ ix86_option_override_internal (bool main_args_p,
   {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
   {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
   {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
+  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
   {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
   {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
   {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
   {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX |
PTA_FXSR},
@@ -4915,6 +4922,30 @@ ix86_option_override_internal (bool main_args_p,
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+  {"eden-x2", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_FXSR},
+  {"eden-x4", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-1000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-2000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-3000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x2", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x4", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | 

Re: [PATCH, i386] Add native support for VIA C7, Eden and Nano CPUs

[J. Mayer]

On Mon, 2016-06-06 at 17:27 +, Joseph Myers wrote:
> This patch is missing the invoke.texi changes to document all the new
> CPU 
> names.

Hi,
correct, please consider adding the following patch to fix this.
Regards.

---

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ce162a0..ac7f8a8 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -23261,6 +23261,54 @@ VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE
instruction set support.
 (No scheduling is
 implemented for this chip.)
 
+@item c7
+VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3 instruction set
support.
+(No scheduling is implemented for this chip.)
+
+@item samuel-2
+VIA Eden Samuel 2 CPU with MMX and 3DNow!@: instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nehemiah
+VIA Eden Nehemiah CPU with MMX and SSE instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item esther
+VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3 instruction set
support.
+(No scheduling is implemented for this chip.)
+
+@item eden-x2
+VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3 instruction set
support.
+(No scheduling is implemented for this chip.)
+
+@item eden-x4
+VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
SSE4.2, AVX and AVX2 instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano
+Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano-1000
+VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano-2000
+VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano-3000
+VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1
instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano-x2
+VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and
SSE4.1 instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano-x4
+VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and
SSE4.1 instruction set support.
+(No scheduling is implemented for this chip.)
+
 @item geode
 AMD Geode embedded processor with MMX and 3DNow!@: instruction set
support.
 @end table

[PATCH, i386] Add native support for VIA C7, Eden and Nano CPUs

[J. Mayer]

The following patch adds support and native detection for C7, Eden
"Samuel2", Eden "Nehemiah", Eden "Esther", Eden x2, Eden x4, Nano 1xxx,
Nano 2xxx, Nano 3xxx, Nano x2 and Nano x4 VIA CPUs.

Please CC me to any comment / review / change request.

---

diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-
i386.c
index a9d5135..d2c4c4c 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -651,7 +651,9 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
  break;
 
case 6:
- if (model > 9 || has_longmode)
+ if (has_longmode)
+   processor = PROCESSOR_K8;
+ else if (model > 9)
/* Use the default detection procedure.  */
;
  else if (model == 9)
@@ -869,9 +871,30 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
cpu = "athlon";
   break;
 case PROCESSOR_K8:
-  if (arch && has_sse3)
-   cpu = "k8-sse3";
+  if (arch)
+   {
+ if (vendor == signature_CENTAUR_ebx)
+   {
+ if (has_sse4_1)
+   /* Nano 3000 | Nano dual / quad core | Eden X4 */
+   cpu = "nano-3000";
+ else if (has_ssse3)
+   /* Nano 1000 | Nano 2000 */
+   cpu = "nano";
+ else if (has_sse3)
+   /* Eden X2 */
+   cpu = "eden-x2";
+ else
+   /* Default to k8 */
+   cpu = "k8";
+   }
+ else if (has_sse3)
+   cpu = "k8-sse3";
+ else
+   cpu = "k8";
+   }
   else
+   /* For -mtune, we default to -mtune=k8 */
cpu = "k8";
   break;
 case PROCESSOR_AMDFAM10:
@@ -903,7 +926,22 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
   /* Use something reasonable.  */
   if (arch)
{
- if (has_ssse3)
+ if (vendor == signature_CENTAUR_ebx)
+   {
+ if (has_sse3) {
+   /* C7 / Eden "Esther" */
+   cpu = "c7";
+ } else if (has_sse) {
+   /* Eden "Nehemiah" */
+   cpu = "nehemiah";
+ } else if (has_3dnow) {
+   /* Eden "Samuel2" */
+   cpu = "samuel-2";
+ } else {
+   /* We have no idea: default to generic i386 */
+ }
+   }
+ else if (has_ssse3)
cpu = "core2";
  else if (has_sse3)
{
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 7e9f511..c9bd25e 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -4783,8 +4783,15 @@ ix86_option_override_internal (bool main_args_p,
   {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
   {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
   {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
+  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
   {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
   {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
   {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
   {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX |
PTA_FXSR},
@@ -4915,6 +4922,30 @@ ix86_option_override_internal (bool main_args_p,
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+  {"eden-x2", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_FXSR},
+  {"eden-x4", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-1000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-2000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-3000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x2", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x4", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | 

Re: [PATCH][i386] Add -march=native support for VIA nano CPUs

[J. Mayer]

On Tue, 2016-05-31 at 13:38 +0200, Uros Bizjak wrote:
> On Mon, May 30, 2016 at 12:09 AM, J. Mayer <l_ind...@magic.fr> wrote:
> > 
> > Hello,
> > 
> > On Sun, 2016-05-29 at 21:12 +0200, Uros Bizjak wrote:
> > > 
> > > Hello!
> > > 
> > > > 
> > > > 
> > > > When trying to compile using -march=native on a VIA nano CPU,
> > > > gcc
> > > > selects "-march=core2" "-mtune=i386" then is unable to compile,
> > > > as
> > > > this
> > > > creates a conflicts between 32 bits and 64 bits compilation
> > > > modes,
> > > > as
> > > > show by the following test:
> > > [...]
> > > 
> > > > 
> > > > 
> > > > --- gcc/config/i386/driver-i386.c.origÂÂ2015-02-02
> > > > 05:20:49.0
> > > > +0100
> > > > +++ gcc/config/i386/driver-i386.cÂÂÂ2015-08-23
> > > > 01:11:03.0
> > > > +0200
> > > > @@ -601,15 +601,20 @@
> > > > ÂÂswitch (family)
> > > > {
> > > > case 6:
> > > > -Âif (model > 9)
> > > The patch was corrupted by your mailer. But - can you please open
> > > a
> > > bugreport, and refer reposted patch to this bugreport? This way,
> > > the
> > > problem (and the patch) won't get forgotten.
> > > 
> > > Uros.
> > > 
> > Sorry for that, might be because of UTF-8 encoding.
> > I already opened a bug many monthes ago, ID 67310:
> > <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67310>
> > I just updated the patch against current git repository, the only
> > difference between previous versions are diff offsets.
> Can you please test the patch that is attached to the bugreport?
> 
> Thanks,
> Uros.

Yes, I've seen your patch and downloaded it, I'm now recompiling gcc
from patched git repository; I'll be busy in the hours to come, but
I'll make the test as soon as I can.

Jocelyn

Re: [PATCH][i386] Add -march=native support for VIA nano CPUs

[J. Mayer]

Hello,

On Sun, 2016-05-29 at 21:12 +0200, Uros Bizjak wrote:
> Hello!
> 
> > 
> > When trying to compile using -march=native on a VIA nano CPU, gcc
> > selects "-march=core2" "-mtune=i386" then is unable to compile, as
> > this
> > creates a conflicts between 32 bits and 64 bits compilation modes,
> > as
> > show by the following test:
> [...]
> 
> > 
> > --- gcc/config/i386/driver-i386.c.origÂÂ2015-02-02
> > 05:20:49.0
> > +0100
> > +++ gcc/config/i386/driver-i386.cÂÂÂ2015-08-23
> > 01:11:03.0
> > +0200
> > @@ -601,15 +601,20 @@
> > ÂÂswitch (family)
> > {
> > case 6:
> > -Âif (model > 9)
> The patch was corrupted by your mailer. But - can you please open a
> bugreport, and refer reposted patch to this bugreport? This way, the
> problem (and the patch) won't get forgotten.
> 
> Uros.
> 

Sorry for that, might be because of UTF-8 encoding.
I already opened a bug many monthes ago, ID 67310:

I just updated the patch against current git repository, the only
difference between previous versions are diff offsets.

Jocelyn

---

diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-
i386.c
index b121466..662709e 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -642,15 +642,20 @@ const char *host_detect_local_cpu (int argc,
const char **argv)
  switch (family)
{
case 6:
- if (model > 9)
-   /* Use the default detection procedure.  */
+ if (has_longmode)
processor = PROCESSOR_GENERIC;
- else if (model == 9)
-   cpu = "c3-2";
- else if (model >= 6)
-   cpu = "c3";
  else
-   processor = PROCESSOR_GENERIC;
+   {
+ if (model > 9)
+   /* Use the default detection procedure.  */
+   processor = PROCESSOR_GENERIC;
+ else if (model == 9)
+   cpu = "c3-2";
+ else if (model >= 6)
+   cpu = "c3";
+ else
+   processor = PROCESSOR_GENERIC;
+   }
  break;
case 5:
  if (has_3dnow)
@@ -664,6 +669,8 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
  /* We have no idea.  */
  processor = PROCESSOR_GENERIC;
}
+   } else {
+ processor = PROCESSOR_GENERIC;
}
 }
   else
@@ -894,7 +901,12 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
   if (arch)
{
  if (has_ssse3)
-   cpu = "core2";
+   {
+ if (vendor == signature_CENTAUR_ebx)
+   cpu = "x86-64";
+ else
+   cpu = "core2";
+   }
  else if (has_sse3)
{
  if (has_longmode)

[PATCH][i386] Add -march=native support for VIA nano CPUs

[J. Mayer]

When trying to compile using -march=native on a VIA nano CPU, gcc
selects "-march=core2" "-mtune=i386" then is unable to compile, as this
creates a conflicts between 32 bits and 64 bits compilation modes, as
show by the following test:

# echo 'int main(){return 0;}' > test.c && gcc -march=native -O2
-pipe  test.c -o test && rm test.c test
Compilation fails with the following error message and informations:
[...]
test.c:1:0: error: CPU you selected does not support x86-64 instruction
set
 int main(){return 0;}
 ^

Using "-v -Q" option shows the detection problem:
gnu/gcc/../lib/gcc/x86_64-unknown-linux-gnu/4.8.4/
 test.c -march=core2 -mcx16 -msahf -mno-movbe -mno-aes -mno-pclmul
 -mno-popcnt -mno-abm -mno-lwp -mno-fma -mno-fma4 -mno-xop -mno-bmi
 -mno-bmi2 -mno-tbm -mno-avx -mno-avx2 -mno-sse4.2 -mno-sse4.1 -mno-
lzcnt
 -mno-rtm -mno-hle -mno-rdrnd -mno-f16c -mno-fsgsbase -mno-rdseed
 -mno-prfchw -mno-adx -mfxsr -mno-xsave -mno-xsaveopt
 --param l1-cache-size=64 --param l1-cache-line-size=64
 --param l2-cache-size=1024 -mtune=i386 -O2 -fno-use-linker-plugin


The following patch allows gcc to select correct compilation options,
which can be checked using "-v -Q" gcc options. GCC output becomes:
gnu/gcc/../lib/gcc/x86_64-unknown-linux-gnu/4.8.4/
 test.c -march=x86-64 -mcx16 -msahf -mno-movbe -mno-aes -mno-pclmul
 -mno-popcnt -mno-abm -mno-lwp -mno-fma -mno-fma4 -mno-xop -mno-bmi
 -mno-bmi2 -mno-tbm -mno-avx -mno-avx2 -msse3 -mssse3 -mno-sse4.2
 -mno-sse4.1 -mno-lzcnt -mno-rtm -mno-hle -mno-rdrnd -mno-f16c
 -mno-fsgsbase -mno-rdseed -mno-prfchw -mno-adx -mfxsr -mno-xsave
 -mno-xsaveopt --param l1-cache-size=64 --param l1-cache-line-size=64
 --param l2-cache-size=1024 -mtune=generic -O2 -fno-use-linker-plugin

which seems OK.
The same problem appears with gcc 4.9.3 and 5.2, and likely with
current git version.

The following patch applies to gcc >= 4.9; it has been tested by
recompiling the whole system from scratch on a Gentoo distribution
using gcc version 4.9.3 (the current stable gcc version on Gentoo
x86_64) with no issue.

Please consider applying this patch to future releases.

Jocelyn Mayer 

PS: please CC me to any answer to this mail, as I didn't subscribe to
the mailing list.

---

--- gcc/config/i386/driver-i386.c.orig  2015-02-02 05:20:49.0
+0100
+++ gcc/config/i386/driver-i386.c   2015-08-23 01:11:03.0
+0200
@@ -601,15 +601,20 @@
  switch (family)
{
case 6:
- if (model > 9)
-   /* Use the default detection procedure.  */
+ if (has_longmode)
processor = PROCESSOR_GENERIC;
- else if (model == 9)
-   cpu = "c3-2";
- else if (model >= 6)
-   cpu = "c3";
  else
-   processor = PROCESSOR_GENERIC;
+   {
+ if (model > 9)
+   /* Use the default detection procedure.  */
+   processor = PROCESSOR_GENERIC;
+ else if (model == 9)
+   cpu = "c3-2";
+ else if (model >= 6)
+   cpu = "c3";
+ else
+   processor = PROCESSOR_GENERIC;
+   }
  break;
case 5:
  if (has_3dnow)
@@ -623,6 +628,8 @@
  /* We have no idea.  */
  processor = PROCESSOR_GENERIC;
}
+   } else {
+ processor = PROCESSOR_GENERIC;
}
 }
   else
@@ -840,7 +847,12 @@
   if (arch)
{ 
  if (has_ssse3)
-   cpu = "core2";
+   {
+ if (vendor == signature_CENTAUR_ebx)
+   cpu = "x86-64";
+ else
+   cpu = "core2";
+   }
  else if (has_sse3)
{ 
  if (has_longmode)