RE: Add support for use_hazard_barrier_return function attribute
Please find the updated patch below. I hope I've covered everything.
I've added the test for inline restriction, could you check if I got all the
options correct?
Changelog:
2017-06-23 Prachi Godbole
gcc/
* config/mips/mips.h (machine_function): New variable
use_hazard_barrier_return_p.
* config/mips/mips.md (UNSPEC_JRHB): New unspec.
(mips_hb_return_internal): New insn pattern.
* config/mips/mips.c (mips_attribute_table): Add attribute
use_hazard_barrier_return.
(mips_use_hazard_barrier_return_p): New static function.
(mips_function_attr_inlinable_p): Likewise.
(mips_compute_frame_info): Set use_hazard_barrier_return_p. Emit error
for unsupported architecture choice.
(mips_function_ok_for_sibcall, mips_can_use_return_insn): Return false
for use_hazard_barrier_return.
(mips_expand_epilogue): Emit hazard barrier return.
* doc/extend.texi: Document use_hazard_barrier_return.
gcc/testsuite/
* gcc.target/mips/hazard-barrier-return-attribute.c: New tests.
Index: gcc/doc/extend.texi
===
--- gcc/doc/extend.texi (revision 246899)
+++ gcc/doc/extend.texi (working copy)
@@ -4496,6 +4496,12 @@ On MIPS targets, you can use the @code{nocompressi
to locally turn off MIPS16 and microMIPS code generation. This attribute
overrides the @option{-mips16} and @option{-mmicromips} options on the
command line (@pxref{MIPS Options}).
+
+@item use_hazard_barrier_return
+@cindex @code{use_hazard_barrier_return} function attribute, MIPS
+This function attribute instructs the compiler to generate a hazard
+barrier return that clears all execution and instruction hazards while
+returning, instead of generating a normal return instruction.
@end table
@node MSP430 Function Attributes
Index: gcc/config/mips/mips.md
===
--- gcc/config/mips/mips.md (revision 246899)
+++ gcc/config/mips/mips.md (working copy)
@@ -156,6 +156,9 @@
;; The `.insn' pseudo-op.
UNSPEC_INSN_PSEUDO
+
+ ;; Hazard barrier return.
+ UNSPEC_JRHB
])
(define_constants
@@ -6578,6 +6581,20 @@
[(set_attr "type""jump")
(set_attr "mode""none")])
+;; Insn to clear execution and instruction hazards while returning.
+;; However, it doesn't clear hazards created by the insn in its delay slot.
+;; Thus, explicitly place a nop in its delay slot.
+
+(define_insn "mips_hb_return_internal"
+ [(return)
+ (unspec_volatile [(match_operand 0 "pmode_register_operand" "")]
+ UNSPEC_JRHB)]
+ ""
+ {
+return "%(jr.hb\t$31%/%)";
+ }
+ [(set_attr "insn_count" "2")])
+
;; Normal return.
(define_insn "_internal"
Index: gcc/config/mips/mips.c
===
--- gcc/config/mips/mips.c (revision 246899)
+++ gcc/config/mips/mips.c (working copy)
@@ -615,6 +615,7 @@ static const struct attribute_spec mips_attribute_
mips_handle_use_shadow_register_set_attr, false },
{ "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
{ "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
+ { "use_hazard_barrier_return", 0, 0, true, false, false, NULL, false },
{ NULL, 0, 0, false, false, false, NULL, false }
};
@@ -1275,6 +1276,16 @@ mips_use_debug_exception_return_p (tree type)
TYPE_ATTRIBUTES (type)) != NULL;
}
+/* Check if the attribute to use hazard barrier return is set for
+ the function declaration DECL. */
+
+static bool
+mips_use_hazard_barrier_return_p (const_tree decl)
+{
+ return lookup_attribute ("use_hazard_barrier_return",
+ DECL_ATTRIBUTES (decl)) != NULL;
+}
+
/* Return the set of compression modes that are explicitly required
by the attributes in ATTRIBUTES. */
@@ -1460,6 +1471,21 @@ mips_can_inline_p (tree caller, tree callee)
return default_target_can_inline_p (caller, callee);
}
+/* Implement TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P.
+
+ A function reqeuesting clearing of all instruction and execution hazards
+ before returning cannot be inlined - thereby not clearing any hazards.
+ All our other function attributes are related to how out-of-line copies
+ should be compiled or called. They don't in themselves prevent inlining.
*/
+
+static bool
+mips_function_attr_inlinable_p (const_tree decl)
+{
+ if (mips_use_hazard_barrier_return_p (decl))
+return false;
+ return true;
+}
+
/* Handle an "interrupt" attribute with an optional argument. */
static tree
@@ -7863,6 +7889,17 @@ mips_function_ok_for_sibcall (tree decl, tree exp
&& !targetm.binds
Add support for use_hazard_barrier_return function attribute
This patch adds support for function attribute __attribute__
((use_hazard_barrier_return)). The attribute will generate hazard barrier
return (jr.hb) instead of a normal return instruction.
Changelog:
2017-04-25 Prachi Godbole
gcc/
* config/mips/mips.h (machine_function): New variable
use_hazard_barrier_return_p.
* config/mips/mips.md (UNSPEC_JRHB): New unspec.
(mips_hb_return_internal): New insn pattern.
* config/mips/mips.c (mips_attribute_table): Add attribute
use_hazard_barrier_return.
(mips_use_hazard_barrier_return_p): New static function.
(mips_function_attr_inlinable_p): Likewise.
(mips_compute_frame_info): Set use_hazard_barrier_return_p. Emit error
for unsupported architecture choice.
(mips_function_ok_for_sibcall, mips_can_use_return_insn): Return false
for use_hazard_barrier_return.
(mips_expand_epilogue): Emit hazard barrier return.
* doc/extend.texi: Document use_hazard_barrier_return.
gcc/testsuite/
* gcc.target/mips/hazard-barrier-return-attribute.c: New test.
Ok for stage1?
Regards,
Prachi
Index: gcc/doc/extend.texi
===
--- gcc/doc/extend.texi (revision 246899)
+++ gcc/doc/extend.texi (working copy)
@@ -4496,6 +4496,12 @@ On MIPS targets, you can use the @code{nocompressi
to locally turn off MIPS16 and microMIPS code generation. This attribute
overrides the @option{-mips16} and @option{-mmicromips} options on the
command line (@pxref{MIPS Options}).
+
+@item use_hazard_barrier_return
+@cindex @code{use_hazard_barrier_return} function attribute, MIPS
+This function attribute instructs the compiler to generate hazard barrier
return
+that clears all execution and instruction hazards while returning, instead of
+generating a normal return instruction.
@end table
@node MSP430 Function Attributes
Index: gcc/config/mips/mips.md
===
--- gcc/config/mips/mips.md (revision 246899)
+++ gcc/config/mips/mips.md (working copy)
@@ -156,6 +156,7 @@
;; The `.insn' pseudo-op.
UNSPEC_INSN_PSEUDO
+ UNSPEC_JRHB
])
(define_constants
@@ -6578,6 +6579,20 @@
[(set_attr "type""jump")
(set_attr "mode""none")])
+;; Insn to clear execution and instruction hazards while returning.
+;; However, it doesn't clear hazards created by the insn in its delay slot.
+;; Thus, explicitly place a nop in its delay slot.
+
+(define_insn "mips_hb_return_internal"
+ [(return)
+ (unspec_volatile [(match_operand 0 "pmode_register_operand" "")]
+ UNSPEC_JRHB)]
+ ""
+ {
+return "%(jr.hb\t$31%/%)";
+ }
+ [(set_attr "insn_count" "2")])
+
;; Normal return.
(define_insn "_internal"
Index: gcc/config/mips/mips.c
===
--- gcc/config/mips/mips.c (revision 246899)
+++ gcc/config/mips/mips.c (working copy)
@@ -615,6 +615,7 @@ static const struct attribute_spec mips_attribute_
mips_handle_use_shadow_register_set_attr, false },
{ "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
{ "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
+ { "use_hazard_barrier_return", 0, 0, true, false, false, NULL, false },
{ NULL, 0, 0, false, false, false, NULL, false }
};
@@ -1275,6 +1276,16 @@ mips_use_debug_exception_return_p (tree type)
TYPE_ATTRIBUTES (type)) != NULL;
}
+/* Check if the attribute to use hazard barrier return is set for
+ the function declaration DECL. */
+
+static bool
+mips_use_hazard_barrier_return_p (tree decl)
+{
+ return lookup_attribute ("use_hazard_barrier_return",
+ DECL_ATTRIBUTES (decl)) != NULL;
+}
+
/* Return the set of compression modes that are explicitly required
by the attributes in ATTRIBUTES. */
@@ -1460,6 +1471,21 @@ mips_can_inline_p (tree caller, tree callee)
return default_target_can_inline_p (caller, callee);
}
+/* Implement TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P.
+
+ A function reqeuesting clearing of all instruction and execution hazards
+ before returning cannot be inlined - thereby not clearing any hazards.
+ All our other function attributes are related to how out-of-line copies
+ should be compiled or called. They don't in themselves prevent inlining.
*/
+
+static bool
+mips_function_attr_inlinable_p (const_tree decl)
+{
+ if (mips_use_hazard_barrier_return_p (const_cast(decl)))
+return false;
+ return hook_bool_const_tree_true (decl);
+}
+
/* Handle an "interrupt" attribute with an optional argument. */
static tree
@@ -7863,6 +7889,11 @@ mips_function_ok_for_sibcall (
RE: [PATCH][MIPS]MSA AND.d optimization to generate BCLRI.d
Committed as r245995 with dg-skip-if comment change.
Prachi
-Original Message-
From: Matthew Fortune
Sent: Thursday, March 9, 2017 2:59 PM
To: Prachi Godbole; gcc-patches@gcc.gnu.org
Cc: Moore, Catherine
Subject: RE: [PATCH][MIPS]MSA AND.d optimization to generate BCLRI.d
Prachi Godbole writes:
> 2017-03-09 Prachi Godbole
>
> gcc/testsuite/
> * gcc.target/mips/msa-bclri.c: Skip the test for -O0.
>
>
> Index: testsuite/gcc.target/mips/msa-bclri.c
> ===
> --- testsuite/gcc.target/mips/msa-bclri.c (revision 245912)
> +++ testsuite/gcc.target/mips/msa-bclri.c (working copy)
> @@ -1,5 +1,6 @@
> /* { dg-do compile } */
> /* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
>
> typedef long long v2i64 __attribute__ ((vector_size(16)));
I guess this is effectively a code quality test as well as a regression test
for the bug so can you state "code quality test"
in the dg-skip-if string.
Otherwise OK for trunk,
Matthew
RE: [PATCH][MIPS]MSA AND.d optimization to generate BCLRI.d
Hi,
Here's a patch to disable the test for BCLRI.d optimization for level -O0.
OK for trunk?
Changelog:
2017-03-09 Prachi Godbole
gcc/testsuite/
* gcc.target/mips/msa-bclri.c: Skip the test for -O0.
Index: testsuite/gcc.target/mips/msa-bclri.c
===
--- testsuite/gcc.target/mips/msa-bclri.c (revision 245912)
+++ testsuite/gcc.target/mips/msa-bclri.c (working copy)
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
typedef long long v2i64 __attribute__ ((vector_size(16)));
-Original Message-
From: Matthew Fortune
Sent: Monday, March 6, 2017 2:58 PM
To: Prachi Godbole; gcc-patches@gcc.gnu.org
Cc: Moore, Catherine
Subject: RE: [PATCH][MIPS]MSA AND.d optimization to generate BCLRI.d
Prachi Godbole writes:
> 2017-03-06 Prachi Godbole
>
> gcc/
> * config/mips/mips.c (mips_gen_const_int_vector): Change type of last
> argument.
> * config/mips/mips-protos.h (mips_gen_const_int_vector): Likewise.
>
> gcc/testsuite/
> * gcc.target/mips/msa-bclri.c: New test.
OK, Thanks.
Matthew
[PATCH][MIPS]MSA min,max insn family RTL fixes
Hi,
Here are a couple of bugs for MSA min/max instructions along with proposed
fixes. Patch for the same is also included below:
1. mini_s and maxi_s: Assembler error: invalid operand :-
Fix: Change print operand code so as to print signed immediate instead of an
unsigned one.
2. max_a, min_a, fmax_a, fmin_a: RTL operand is missing mode; it was discovered
while forward propagating the result.
Fix: Introduce mode iterator in if_then_else construct.
OK?
Changelog:
2017-03-06 Prachi Godbole
gcc/
* config/mips/mips-msa.md (msa_fmax_a_, msa_fmin_a_,
msa_max_a_, msa_min_a_): Introduce mode interator for
if_then_else.
(smin3, smax3): Change operand print code from 'B' to 'E'.
gcc/testsuite/
* gcc.target/mips/msa-minmax.c: New tests.
Index: config/mips/mips-msa.md
===
--- config/mips/mips-msa.md (revision 245205)
+++ config/mips/mips-msa.md (working copy)
@@ -1688,7 +1688,7 @@
(define_insn "msa_fmax_a_"
[(set (match_operand:FMSA 0 "register_operand" "=f")
- (if_then_else
+ (if_then_else:FMSA
(gt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f"))
(abs:FMSA (match_operand:FMSA 2 "register_operand" "f")))
(match_dup 1)
@@ -1709,7 +1709,7 @@
(define_insn "msa_fmin_a_"
[(set (match_operand:FMSA 0 "register_operand" "=f")
- (if_then_else
+ (if_then_else:FMSA
(lt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f"))
(abs:FMSA (match_operand:FMSA 2 "register_operand" "f")))
(match_dup 1)
@@ -2174,7 +2174,7 @@
(define_insn "msa_max_a_"
[(set (match_operand:IMSA 0 "register_operand" "=f")
- (if_then_else
+ (if_then_else:IMSA
(gt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
(abs:IMSA (match_operand:IMSA 2 "register_operand" "f")))
(match_dup 1)
@@ -2191,7 +2191,7 @@
"ISA_HAS_MSA"
"@
max_s.\t%w0,%w1,%w2
- maxi_s.\t%w0,%w1,%B2"
+ maxi_s.\t%w0,%w1,%E2"
[(set_attr "type" "simd_int_arith")
(set_attr "mode" "")])
@@ -2208,7 +2208,7 @@
(define_insn "msa_min_a_"
[(set (match_operand:IMSA 0 "register_operand" "=f")
- (if_then_else
+ (if_then_else:IMSA
(lt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
(abs:IMSA (match_operand:IMSA 2 "register_operand" "f")))
(match_dup 1)
@@ -2225,7 +2225,7 @@
"ISA_HAS_MSA"
"@
min_s.\t%w0,%w1,%w2
- mini_s.\t%w0,%w1,%B2"
+ mini_s.\t%w0,%w1,%E2"
[(set_attr "type" "simd_int_arith")
(set_attr "mode" "")])
Index: testsuite/gcc.target/mips/msa-minmax.c
===
--- testsuite/gcc.target/mips/msa-minmax.c (revision 0)
+++ testsuite/gcc.target/mips/msa-minmax.c (revision 0)
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */
+
+typedef int v4i32 __attribute__ ((vector_size(16)));
+typedef float v4f32 __attribute__ ((vector_size(16)));
+
+/* Test MSA signed min/max immediate for correct assembly output. */
+
+void
+min_s_msa (v4i32 *vx, v4i32 *vy)
+{
+ *vy = __builtin_msa_mini_s_w (*vx, -15);
+}
+/* { dg-final { scan-assembler "-15" } } */
+
+void
+max_s_msa (v4i32 *vx, v4i32 *vy)
+{
+ *vy = __builtin_msa_maxi_s_w (*vx, -15);
+}
+/* { dg-final { scan-assembler "-15" } } */
+
+/* Test MSA min_a/max_a instructions for forward propagation optimization. */
+
+#define FUNC(NAME, TYPE, RETTYPE) RETTYPE NAME##_a_msa (TYPE *vx, TYPE *vy) \
+{ \
+ TYPE dest = __builtin_msa_##NAME##_a_w (*vx, *vy); \
+ return dest[0]; \
+}
+
+FUNC(fmin, v4f32, float)
+/* { dg-final { scan-assembler "fmin_a.w" } } */
+FUNC(fmax, v4f32, float)
+/* { dg-final { scan-assembler "fmax_a.w" } } */
+FUNC(min, v4i32, int)
+/* { dg-final { scan-assembler "min_a.w" } } */
+FUNC(max, v4i32, int)
+/* { dg-final { scan-assembler "max_a.w" } } */
[PATCH][MIPS]MSA dotp.d, dpadd.d, dpsub.d insn RTL - fix MODE
Hi,
A bug was discovered in MSA dotp__d, dpadd__d and dpsub__d RTL
patterns while CSE'ing the result:
Wrong MODE for vec_select in the second mult operand.
The patch below fixes the same.
OK for trunk?
Changelog:
2017-03-06 Prachi Godbole
gcc/
* config/mips/mips-msa.md (msa_dotp__d, msa_dpadd__d,
msa_dpsub__d): Fix MODE for vec_select.
gcc/testsuite/
* gcc.target/mips/msa-dotp.c: New tests.
Index: config/mips/mips-msa.md
===
--- config/mips/mips-msa.md (revision 245205)
+++ config/mips/mips-msa.md (working copy)
@@ -1230,10 +1230,10 @@
(parallel [(const_int 0) (const_int 2)]
(mult:V2DI
(any_extend:V2DI
- (vec_select:V4SI (match_dup 1)
+ (vec_select:V2SI (match_dup 1)
(parallel [(const_int 1) (const_int 3)])))
(any_extend:V2DI
- (vec_select:V4SI (match_dup 2)
+ (vec_select:V2SI (match_dup 2)
(parallel [(const_int 1) (const_int 3)]))]
"ISA_HAS_MSA"
"dotp_.d\t%w0,%w1,%w2"
@@ -1319,10 +1319,10 @@
(parallel [(const_int 0) (const_int 2)]
(mult:V2DI
(any_extend:V2DI
- (vec_select:V4SI (match_dup 2)
+ (vec_select:V2SI (match_dup 2)
(parallel [(const_int 1) (const_int 3)])))
(any_extend:V2DI
- (vec_select:V4SI (match_dup 3)
+ (vec_select:V2SI (match_dup 3)
(parallel [(const_int 1) (const_int 3)])
(match_operand:V2DI 1 "register_operand" "0")))]
"ISA_HAS_MSA"
@@ -1414,10 +1414,10 @@
(parallel [(const_int 0) (const_int 2)]
(mult:V2DI
(any_extend:V2DI
- (vec_select:V4SI (match_dup 2)
+ (vec_select:V2SI (match_dup 2)
(parallel [(const_int 1) (const_int 3)])))
(any_extend:V2DI
- (vec_select:V4SI (match_dup 3)
+ (vec_select:V2SI (match_dup 3)
(parallel [(const_int 1) (const_int 3)])))]
"ISA_HAS_MSA"
"dpsub_.d\t%w0,%w2,%w3"
Index: testsuite/gcc.target/mips/msa-dotp.c
===
--- testsuite/gcc.target/mips/msa-dotp.c(revision 0)
+++ testsuite/gcc.target/mips/msa-dotp.c(revision 0)
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */
+
+typedef int v4i32 __attribute__ ((vector_size(16)));
+typedef long long v2i64 __attribute__ ((vector_size(16)));
+
+/* Test MSA dot product family for CSE optimization. */
+
+static v4i32 g = {0, 92, 93, 94};
+static v4i32 h = {12, 24, 36, 48};
+static v2i64 l = {84, 98};
+
+void
+dotp_d_msa (v2i64 *c)
+{
+ *c = __builtin_msa_dotp_s_d (g, h);
+}
+/* { dg-final { scan-assembler "dotp_s.d" } } */
+
+void
+dpadd_d_msa (v2i64 *c)
+{
+ *c = __builtin_msa_dpadd_s_d (l, g, h);
+}
+/* { dg-final { scan-assembler "dpadd_s.d" } } */
+
+void
+dpsub_d_msa (v2i64 *c)
+{
+ *c = __builtin_msa_dpsub_s_d (l, g, h);
+}
+/* { dg-final { scan-assembler "dpsub_s.d" } } */
[PATCH][MIPS]MSA AND.d optimization to generate BCLRI.d
Hi,
Below is the patch to fix ICE: output_operand: invalid use of '%V'
when generating BCLRI.d instruction from AND.d pattern.
Proposed fix:
mips_gen_const_int_vector (machine_mode mode, int val): Change type for
argument VAL from int to HOST_WIDE_INT to allow const vector of type doubleword.
It is used by BCLRI.d alternative in AND.d pattern for immediate const vector
operand with only one bit clear.
OK?
Changelog:
2017-03-06 Prachi Godbole
gcc/
* config/mips/mips.c (mips_gen_const_int_vector): Change type of last
argument.
* config/mips/mips-protos.h (mips_gen_const_int_vector): Likewise.
gcc/testsuite/
* gcc.target/mips/msa-bclri.c: New test.
Index: config/mips/mips.c
===
--- config/mips/mips.c (revision 245205)
+++ config/mips/mips.c (working copy)
@@ -21608,7 +21608,7 @@
/* Return a const_int vector of VAL with mode MODE. */
rtx
-mips_gen_const_int_vector (machine_mode mode, int val)
+mips_gen_const_int_vector (machine_mode mode, HOST_WIDE_INT val)
{
int nunits = GET_MODE_NUNITS (mode);
rtvec v = rtvec_alloc (nunits);
Index: config/mips/mips-protos.h
===
--- config/mips/mips-protos.h (revision 245205)
+++ config/mips/mips-protos.h (working copy)
@@ -294,7 +294,7 @@
extern bool mips_const_vector_bitimm_set_p (rtx, machine_mode);
extern bool mips_const_vector_bitimm_clr_p (rtx, machine_mode);
extern rtx mips_msa_vec_parallel_const_half (machine_mode, bool);
-extern rtx mips_gen_const_int_vector (machine_mode, int);
+extern rtx mips_gen_const_int_vector (machine_mode, HOST_WIDE_INT);
extern bool mips_secondary_memory_needed (enum reg_class, enum reg_class,
machine_mode);
extern bool mips_cannot_change_mode_class (machine_mode,
Index: testsuite/gcc.target/mips/msa-bclri.c
===
--- testsuite/gcc.target/mips/msa-bclri.c (revision 0)
+++ testsuite/gcc.target/mips/msa-bclri.c (revision 0)
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */
+
+typedef long long v2i64 __attribute__ ((vector_size(16)));
+
+/* Test MSA AND.d optimization: generate BCLRI.d instead, for immediate const
+ vector operand with only one bit clear. */
+
+void
+and_d_msa (v2i64 *vx, v2i64 *vy)
+{
+ v2i64 and_vec = {0x7FFF, 0x7FFF};
+ *vy = (*vx) & and_vec;
+}
+/* { dg-final { scan-assembler "bclri.d" } } */
[PATCH][MIPS] MSA machine description fixes
Hi,
The patch fixes some bugs as mentioned below.
1. mips_gen_const_int_vector(): Change type for argument VAL from int to
HOST_WIDE_INT to allow const vector of type doubleword. It in turn enables
generation of BCLRI.d instead of AND.d for immediate const vector operand with
only one bit clear.
2. MSA dot product family instruction for .d format: Fix wrong MODE for
vec_select in the second mult operand. It enables some optimizations like CSE
fwprop etc.
3. signed min/max immediate: Fix print operand code so as to print signed
immediate instead of an unsigned one.
4. MSA max/min absolute instruction family: Introduce mode iterator in
if_then_else construct. It enables some optimizations like CSE fwprop etc.
Tests for all of them are also included in the patch.
Ok for trunk?
Regards,
Prachi
Changelog:
2017-02-07 Prachi Godbole
gcc/
* config/mips/mips-msa.md (msa_dotp__d, msa_dpadd__d,
msa_dpsub__d): Fix MODE for vec_select.
(msa_fmax_a_, msa_fmin_a_, msa_max_a_,
msa_min_a_): Introduce mode interator for if_then_else.
(smin3, smax3): Change operand print code from 'B' to 'E'.
* config/mips/mips.c (mips_gen_const_int_vector): Change type of last
argument.
* config/mips/mips-protos.h (mips_gen_const_int_vector): Likewise.
gcc/testsuite/
* gcc.target/mips/msa-1.c: New tests.
Index: gcc/config/mips/mips.c
===
--- gcc/config/mips/mips.c (revision 245205)
+++ gcc/config/mips/mips.c (working copy)
@@ -21608,7 +21608,7 @@
/* Return a const_int vector of VAL with mode MODE. */
rtx
-mips_gen_const_int_vector (machine_mode mode, int val)
+mips_gen_const_int_vector (machine_mode mode, HOST_WIDE_INT val)
{
int nunits = GET_MODE_NUNITS (mode);
rtvec v = rtvec_alloc (nunits);
Index: gcc/config/mips/mips-protos.h
===
--- gcc/config/mips/mips-protos.h (revision 245205)
+++ gcc/config/mips/mips-protos.h (working copy)
@@ -294,7 +294,7 @@
extern bool mips_const_vector_bitimm_set_p (rtx, machine_mode);
extern bool mips_const_vector_bitimm_clr_p (rtx, machine_mode);
extern rtx mips_msa_vec_parallel_const_half (machine_mode, bool);
-extern rtx mips_gen_const_int_vector (machine_mode, int);
+extern rtx mips_gen_const_int_vector (machine_mode, HOST_WIDE_INT);
extern bool mips_secondary_memory_needed (enum reg_class, enum reg_class,
machine_mode);
extern bool mips_cannot_change_mode_class (machine_mode,
Index: gcc/config/mips/mips-msa.md
===
--- gcc/config/mips/mips-msa.md (revision 245205)
+++ gcc/config/mips/mips-msa.md (working copy)
@@ -1230,10 +1230,10 @@
(parallel [(const_int 0) (const_int 2)]
(mult:V2DI
(any_extend:V2DI
- (vec_select:V4SI (match_dup 1)
+ (vec_select:V2SI (match_dup 1)
(parallel [(const_int 1) (const_int 3)])))
(any_extend:V2DI
- (vec_select:V4SI (match_dup 2)
+ (vec_select:V2SI (match_dup 2)
(parallel [(const_int 1) (const_int 3)]))]
"ISA_HAS_MSA"
"dotp_.d\t%w0,%w1,%w2"
@@ -1319,10 +1319,10 @@
(parallel [(const_int 0) (const_int 2)]
(mult:V2DI
(any_extend:V2DI
- (vec_select:V4SI (match_dup 2)
+ (vec_select:V2SI (match_dup 2)
(parallel [(const_int 1) (const_int 3)])))
(any_extend:V2DI
- (vec_select:V4SI (match_dup 3)
+ (vec_select:V2SI (match_dup 3)
(parallel [(const_int 1) (const_int 3)])
(match_operand:V2DI 1 "register_operand" "0")))]
"ISA_HAS_MSA"
@@ -1414,10 +1414,10 @@
(parallel [(const_int 0) (const_int 2)]
(mult:V2DI
(any_extend:V2DI
- (vec_select:V4SI (match_dup 2)
+ (vec_select:V2SI (match_dup 2)
(parallel [(const_int 1) (const_int 3)])))
(any_extend:V2DI
- (vec_select:V4SI (match_dup 3)
+ (vec_select:V2SI (match_dup 3)
(parallel [(const_int 1) (const_int 3)])))]
"ISA_HAS_MSA"
"dpsub_.d\t%w0,%w2,%w3"
@@ -1688,7 +1688,7 @@
(define_insn "msa_fmax_a_"
[(set (match_operand:FMSA 0 "register_operand" "=f")
- (if_then_else
+ (if_then_else:FMSA
(gt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f"))
(abs:FMSA (match_operand:FMSA 2 "register_operand" "f")))
(match_dup 1)
@@ -1709,7 +1709,7 @@
(define_insn "msa_fmin_a_"
RE: [PATCH][MIPS] Fix P5600 memory cost
Sorry for all the trouble. I messed up with the Changelog by mistake. I'll be careful now onwards. Prachi -Original Message- From: Jeff Law [mailto:l...@redhat.com] Sent: Wednesday, December 10, 2014 4:05 AM To: Matthew Fortune; Prachi Godbole Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH][MIPS] Fix P5600 memory cost On 12/09/14 15:33, Matthew Fortune wrote: > Hi Prachi, > > I'm afraid you updated the wrong Changelog with this commit. GCC > changes are recorded in gcc/ChangeLog. > > I'm not sure what the correct procedure is for fixing this. > > Jeff: Should a mistake like this be fixed by removing the entry from > the top level and adding one at the appropriate location in the > gcc/ChangeLog one? Yes, just move it to the appropriate place. These kinds of things happen from time to time, standard practice is to just fix them, no review required :-0 jeff
RE: [PATCH][MIPS] P5600 pipeline description fixes
Committed. Prachi -Original Message- From: Matthew Fortune Sent: Wednesday, December 3, 2014 4:18 PM To: Prachi Godbole; gcc-patches@gcc.gnu.org Subject: RE: [PATCH][MIPS] P5600 pipeline description fixes > Changelog: > > 2014-12-03 Prachi Godbole > > * config/mips/p5600.md (define_automaton, define_cpu_unit): Replace > p5600_agen_pipe and p5600_alu_pipe with p5600_agen_alq_pipe. > > (p5600_int_arith_1, p5600_int_arith_2, p5600_int_arith_4): Change > reservation order. OK. (No newline required in the middle of the ChangeLog entry.) Thanks, Matthew
[PATCH][MIPS] P5600 pipeline description fixes
Hi, This patch merges automata p5600_agen_pipe and p5600_alu_pipe into one to enable blocking of the cpu units in either-or reservations. It also changes the order of the units in such reservations to benefit from multi-issue scenarios. Changelog: 2014-12-03 Prachi Godbole * config/mips/p5600.md (define_automaton, define_cpu_unit): Replace p5600_agen_pipe and p5600_alu_pipe with p5600_agen_alq_pipe. (p5600_int_arith_1, p5600_int_arith_2, p5600_int_arith_4): Change reservation order. diff --git a/gcc/config/mips/p5600.md b/gcc/config/mips/p5600.md index d0b1424..c1bde2a 100644 --- a/gcc/config/mips/p5600.md +++ b/gcc/config/mips/p5600.md @@ -18,14 +18,14 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. -(define_automaton "p5600_agen_pipe, p5600_alu_pipe, p5600_fpu_pipe") +(define_automaton "p5600_agen_alq_pipe, p5600_fpu_pipe") ;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes (define_cpu_unit "p5600_agq, p5600_al2, p5600_ctistd, p5600_ldsta, - p5600_gpdiv" "p5600_agen_pipe") + p5600_gpdiv" "p5600_agen_alq_pipe") ;; The arithmetic-logic-unit queue (ALQ) has ALU pipe -(define_cpu_unit "p5600_alq, p5600_alu" "p5600_alu_pipe") +(define_cpu_unit "p5600_alq, p5600_alu" "p5600_agen_alq_pipe") ;; The floating-point-unit queue (FPQ) has short and long pipes (define_cpu_unit "p5600_fpu_short, p5600_fpu_long" "p5600_fpu_pipe") @@ -141,13 +141,13 @@ (define_insn_reservation "p5600_int_arith_1" 1 (and (eq_attr "cpu" "p5600") (eq_attr "move_type" "andi,sll0,signext")) - "p5600_agq_al2 | p5600_alq_alu") + "p5600_alq_alu | p5600_agq_al2") ;; addi, addiu, ori, xori, add, addu (define_insn_reservation "p5600_int_arith_2" 1 (and (eq_attr "cpu" "p5600") (eq_attr "alu_type" "add,or,xor")) - "p5600_agq_al2 | p5600_alq_alu") + "p5600_alq_alu | p5600_agq_al2") ;; nor, sub (define_insn_reservation "p5600_int_arith_3" 1 @@ -159,7 +159,7 @@ (define_insn_reservation "p5600_int_arith_4" 1 (and (eq_attr "cpu" "p5600") (eq_attr "type" "shift,slt,move")) - "p5600_agq_al2 | p5600_alq_alu") + "p5600_alq_alu | p5600_agq_al2") ;; nop (define_insn_reservation "p5600_int_nop" 0 Ok? Prachi
RE: [PATCH][MIPS] Fix P5600 memory cost
Committed with ChangeLog entry fixes. Prachi -Original Message- From: Matthew Fortune Sent: Wednesday, November 5, 2014 4:07 PM To: Prachi Godbole; gcc-patches@gcc.gnu.org Subject: RE: [PATCH][MIPS] Fix P5600 memory cost > The patch below fixes the memory cost for P5600. > > ChangeLog: > 2014-11-05 Prachi Godbole > > * config/mips/mips.c (mips_rtx_cost_data): Fix memory_letency cost for > p5600. Please follow these instructions to add yourself to MAINTAINERS in the write-after-approval section now that you have write access to GCC: https://gcc.gnu.org/svnwrite.html#authenticated OK with fixes to the changelog entry: latency not latency. Remember to tab in the changelog entry and split the line as it will exceed 80 chars. Also two spaces between the date/name and name/email. E.g. 2014-11-05 Prachi Godbole * config/mips/mips.c (mips_rtx_cost_data): Fix memory_latency cost for p5600. Thanks, Matthew > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index > af6a913..558ba2f 100644 > --- a/gcc/config/mips/mips.c > +++ b/gcc/config/mips/mips.c > @@ -1193,7 +1193,7 @@ static const struct mips_rtx_cost_data > COSTS_N_INSNS (8),/* int_div_si */ > COSTS_N_INSNS (8),/* int_div_di */ > 2,/* branch_cost */ > - 10 /* memory_latency */ > + 4 /* memory_latency */ >} > }; > ^L
RE: [PATCH][MIPS] Fix P5600 memory cost
Hi Matthew, Sorry for the delay. I was running out of memory to build and test the patch. So was in the process of acquiring more memory. I'll commit the patch in a day or two. Regards, Prachi -Original Message- From: Matthew Fortune Sent: Tuesday, November 25, 2014 8:15 PM To: Prachi Godbole; gcc-patches@gcc.gnu.org Subject: RE: [PATCH][MIPS] Fix P5600 memory cost Hi Prachi, > OK with fixes to the changelog entry: > > latency not latency. Remember to tab in the changelog entry and split > the line as it will exceed 80 chars. Also two spaces between the > date/name and name/email. E.g. > > 2014-11-05 Prachi Godbole > > * config/mips/mips.c (mips_rtx_cost_data): Fix memory_latency cost > for > p5600. I can't see this committed in svn trunk, did you find a problem with the patch? Thanks, Matthew
[committed] MAINTAINERS (Write After Approval): Add myself
2014-11-06 Prachi Godbole * MAINTAINERS (Write After Approval): Add myself. Index: MAINTAINERS === --- MAINTAINERS (revision 217171) +++ MAINTAINERS (working copy) @@ -395,6 +395,7 @@ Tristan Gingold Jan-Benedict Glaw Marc Glisse +Prachi Godbole Anthony Green James Greenhalgh Doug Gregor
[PATCH][MIPS] Fix P5600 memory cost
Hi, The patch below fixes the memory cost for P5600. ChangeLog: 2014-11-05 Prachi Godbole * config/mips/mips.c (mips_rtx_cost_data): Fix memory_letency cost for p5600. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index af6a913..558ba2f 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -1193,7 +1193,7 @@ static const struct mips_rtx_cost_data COSTS_N_INSNS (8),/* int_div_si */ COSTS_N_INSNS (8),/* int_div_di */ 2,/* branch_cost */ - 10 /* memory_latency */ + 4 /* memory_latency */ } }; ^L
