[PATCH V1] RISC-V: Add mininal support for zabha extension.

[shiyulong]

From: yulong 

This patch add the mininal support for zabha extension.
The doc url as follow: 
https://github.com/riscv/riscv-zabha/blob/v1.0-rc1/zabha.adoc
There are have no amocas.[b|h] instructions, because the zacas extension is not 
merged.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add zabha extension name.
* config/riscv/riscv.md (amo_addqi3): New mode.
(amo_addhi3): Ditto.
(amo_minqi3): Ditto.
(amo_minuqi3): Ditto.
(amo_minhi3): Ditto.
(amo_minuhi3): Ditto.
(amo_maxqi3): Ditto.
(amo_maxuqi3): Ditto.
(amo_maxhi3): Ditto.
(amo_maxuhi3): Ditto.
(amo_andqi3): Ditto.
(amo_andhi3): Ditto.
(amo_orqi3): Ditto.
(amo_orhi3): Ditto.
(amo_xorqi3): Ditto.
(amo_xorhi3): Ditto.
(amo_swapqi3): Ditto.
(amo_swaphi3): Ditto.
* config/riscv/riscv.opt: Add zabha extension.

---
 gcc/common/config/riscv/riscv-common.cc |   2 +
 gcc/config/riscv/riscv.md   | 167 
 gcc/config/riscv/riscv.opt  |   2 +
 3 files changed, 171 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 631ce8309a0..9c3be0d7651 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -250,6 +250,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zabha", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1504,6 +1505,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"za64rs", _options::x_riscv_za_subext, MASK_ZA64RS},
   {"za128rs", _options::x_riscv_za_subext, MASK_ZA128RS},
   {"zawrs", _options::x_riscv_za_subext, MASK_ZAWRS},
+  {"zabha", _options::x_riscv_za_subext, MASK_ZABHA},
 
   {"zba",_options::x_riscv_zb_subext, MASK_ZBA},
   {"zbb",_options::x_riscv_zb_subext, MASK_ZBB},
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 39b29795cd6..058b63ac7f0 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -134,6 +134,9 @@
   ;; XTheadInt unspec
   UNSPECV_XTHEADINT_PUSH
   UNSPECV_XTHEADINT_POP
+
+  ;; Zabha instructions.
+  UNSPEC_AMO_SWAP
 ])
 
 (define_constants
@@ -849,6 +852,24 @@
   [(set_attr "type" "arith")
(set_attr "mode" "SI")])
 
+(define_insn "amo_addqi3"
+  [(set (match_operand:QI  0 "register_operand" "=r,r")
+   (plus:QI (match_operand:QI 1 "register_operand" " r,r")
+(match_operand:QI 2 "arith_operand"" r,r")))]
+  "TARGET_ZABHA"
+  "amoadd.b\t%0,%1,%2"
+  [(set_attr "type" "atomic")
+   (set_attr "mode" "QI")])
+
+(define_insn "amo_addhi3"
+  [(set (match_operand:HI  0 "register_operand" "=r,r")
+   (plus:HI (match_operand:HI 1 "register_operand" " r,r")
+(match_operand:HI 2 "arith_operand"" r,r")))]
+  "TARGET_ZABHA"
+  "amoadd.h\t%0,%1,%2"
+  [(set_attr "type" "atomic")
+   (set_attr "mode" "HI")])
+
 ;;
 ;;  
 ;;
@@ -1645,6 +1666,78 @@
   [(set_attr "type" "fmove")
(set_attr "mode" "")])
 
+(define_insn "amo_minqi3"
+  [(set (match_operand:QI0 "register_operand" "=r")
+   (smin:QI (match_operand:QI 1 "register_operand" " r")
+  (match_operand:QI 2 "register_operand" " r")))]
+  "TARGET_ZABHA"
+  "amomin.b\t%0,%1,%2"
+  [(set_attr "type" "atomic")
+   (set_attr "mode" "QI")])
+
+(define_insn "amo_minuqi3"
+  [(set (match_operand:QI0 "register_operand" "=r")
+   (umin:QI (match_operand:QI 1 "register_operand" " r")
+  (match_operand:QI 2 "register_operand" " r")))]
+  "TARGET_ZABHA"
+  "amominu.b\t%0,%1,%2"
+  [(set_attr "type" "atomic")
+   (set_attr "mode" "QI")])
+
+(define_insn "amo_minhi3"
+  [(set (match_operand:HI0 "register_operand" "=r")
+   (smin:HI (match_operand:HI 1 "register_operand" " r")
+  (match_operand:HI 2 "register_operand" " r")))]
+  "TARGET_ZABHA"
+  "amomin.h\t%0,%1,%2"
+  [(set_attr "type" "atomic")
+   (set_attr "mode" "HI")])
+
+(define_insn "amo_minuhi3"
+  [(set (match_operand:HI0 "register_operand" "=r")
+   (umin:HI (match_operand:HI 1 "register_operand" " r")
+  (match_operand:HI 2 "register_operand" " r")))]
+  "TARGET_ZABHA"
+  "amominu.h\t%0,%1,%2"
+  [(set_attr "type" "atomic")
+   (set_attr "mode" "HI")])
+
+(define_insn "amo_maxqi3"
+  [(set (match_operand:QI0 "register_operand" "=r")
+   (smax:QI (match_operand:QI 1 "register_operand" " r")
+  (match_operand:QI 2 "register_operand" " r")))]
+  "TARGET_ZABHA"
+  "amomax.b\t%0,%1,%2"
+  [(set_attr "type" "atomic")
+   (set_attr "mode" "QI")])
+
+(define_insn "amo_maxuqi3"
+  [(set 

[PATCH V1] RISC-V: Fix a bug that causes an error insn.

[shiyulong]

From: yulong 

I test the following rvv intrinsics.
vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t 
value, size_t vl) {
  return __riscv_vslide1up_vx_i64m1_m(mask, src, value, vl);}
And I got an error info,that is error: unrecognizable insn:(insn 17 16 18 2 
(set (reg:RVVMIDI 134 [ _1 ])(if_then_else:RVVMIDI (unspec:RVVMF64BI [(reg/v:SI 
142 [ vl ])(const_int 2 [x2])(const_int ??? [o])(reg:SI 66 vl)(reg:SI 67 
vtype)] UNSPEC_VPREDICATE(vec_merge:RVVMIDI (reg:RVVMIDI 134 [ _1 
])(unspec:RVVMIDI [(reg:sI ??? zero)] UNSPEC_VUNDEF)
(reg/v:RVVMF64BI 137 [ mask ]))
(unspec:RVVM1DI[(reg:sI ??? zero)] UNSPEC_VUNDEF)))

This patch fix it.

gcc/ChangeLog:

* config/riscv/riscv-v.cc (slide1_sew64_helper): Modify.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vslide1down-1.c: New test.
* gcc.target/riscv/rvv/base/vslide1down-2.c: New test.
* gcc.target/riscv/rvv/base/vslide1down-3.c: New test.
* gcc.target/riscv/rvv/base/vslide1up-1.c: New test.
* gcc.target/riscv/rvv/base/vslide1up-2.c: New test.
* gcc.target/riscv/rvv/base/vslide1up-3.c: New test.

---
 gcc/config/riscv/riscv-v.cc   |  5 ++---
 .../gcc.target/riscv/rvv/base/vslide1down-1.c | 22 +++
 .../gcc.target/riscv/rvv/base/vslide1down-2.c | 22 +++
 .../gcc.target/riscv/rvv/base/vslide1down-3.c | 22 +++
 .../gcc.target/riscv/rvv/base/vslide1up-1.c   | 22 +++
 .../gcc.target/riscv/rvv/base/vslide1up-2.c   | 22 +++
 .../gcc.target/riscv/rvv/base/vslide1up-3.c   | 22 +++
 7 files changed, 134 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 278452b9e05..f73ec8c6474 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2103,9 +2103,8 @@ slide1_sew64_helper (int unspec, machine_mode mode, 
machine_mode demote_mode,
 CONSTM1_RTX (demote_mask_mode), merge, temp,
 demote_scalar_op2, vl_x2, ta, ma, ops[8]));
 
-  if (rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1]
-return true;
-  else
+  if (!rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1])))
+  && !rtx_equal_p (ops[2], RVV_VUNDEF (GET_MODE (ops[2]
 emit_insn (gen_pred_merge (mode, ops[0], ops[2], ops[2], ops[0], ops[1],
   force_vector_length_operand (ops[5]), ops[6],
   ops[8]));
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
new file mode 100644
index 000..541745be2a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 
-fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t 
value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t 
value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m2_m(mask, src, value, vl);
+}
+
+vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t src, int64_t 
value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m4_m(mask, src, value, vl);
+}
+
+vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t src, int64_t 
value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m8_m(mask, src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times 
{vseti?vli\s+[a-z0-9]+,\s*[a-z0-9]+,\s*e[0-9]+,\s*mf?[1248],\s*t[au],\s*m[au]\s+vslide1down\.[ivxfswum.]+\s+}
 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
new file mode 100644
index 000..9b5a240a9e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 
-fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t src, int64_t 
value, size_t vl) {
+  return __riscv_vslide1down_vx_i64m1_m(mask, src, value, vl);
+}
+
+vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t src, int64_t 
value, size_t vl) {
+  return 

[PATCH V1] RISC-V:Add float16 tuple type abi

[shiyulong]

From: yulong 

 gcc/ChangeLog:

* config/riscv/vector.md: Add float16 attr at sew、vlmul and ratio.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/abi-10.c: Add float16 tuple type case.
* gcc.target/riscv/rvv/base/abi-11.c: Ditto.
* gcc.target/riscv/rvv/base/abi-12.c: Ditto.
* gcc.target/riscv/rvv/base/abi-15.c: Ditto.
* gcc.target/riscv/rvv/base/abi-8.c: Ditto.
* gcc.target/riscv/rvv/base/abi-9.c: Ditto.
* gcc.target/riscv/rvv/base/abi-17.c: New test.
* gcc.target/riscv/rvv/base/abi-18.c: New test.

---
 gcc/config/riscv/vector.md|  31 ++-
 .../gcc.target/riscv/rvv/base/abi-10.c|  25 ++
 .../gcc.target/riscv/rvv/base/abi-11.c|  27 ++-
 .../gcc.target/riscv/rvv/base/abi-12.c|  27 ++-
 .../gcc.target/riscv/rvv/base/abi-15.c|  27 ++-
 .../gcc.target/riscv/rvv/base/abi-17.c| 229 ++
 .../gcc.target/riscv/rvv/base/abi-18.c| 229 ++
 .../gcc.target/riscv/rvv/base/abi-8.c |  27 ++-
 .../gcc.target/riscv/rvv/base/abi-9.c |  25 ++
 9 files changed, 630 insertions(+), 17 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-17.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-18.c

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 884e7435cc2..cd87989b536 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -98,7 +98,12 @@
  
VNx2x8HI,VNx3x8HI,VNx4x8HI,VNx5x8HI,VNx6x8HI,VNx7x8HI,VNx8x8HI,\
  
VNx2x4HI,VNx3x4HI,VNx4x4HI,VNx5x4HI,VNx6x4HI,VNx7x4HI,VNx8x4HI,\
  
VNx2x2HI,VNx3x2HI,VNx4x2HI,VNx5x2HI,VNx6x2HI,VNx7x2HI,VNx8x2HI,\
- 
VNx2x1HI,VNx3x1HI,VNx4x1HI,VNx5x1HI,VNx6x1HI,VNx7x1HI,VNx8x1HI")
+ 
VNx2x1HI,VNx3x1HI,VNx4x1HI,VNx5x1HI,VNx6x1HI,VNx7x1HI,VNx8x1HI,\
+   VNx2x32HF,VNx2x16HF,VNx3x16HF,VNx4x16HF,\
+ 
VNx2x8HF,VNx3x8HF,VNx4x8HF,VNx5x8HF,VNx6x8HF,VNx7x8HF,VNx8x8HF,\
+ 
VNx2x4HF,VNx3x4HF,VNx4x4HF,VNx5x4HF,VNx6x4HF,VNx7x4HF,VNx8x4HF,\
+ 
VNx2x2HF,VNx3x2HF,VNx4x2HF,VNx5x2HF,VNx6x2HF,VNx7x2HF,VNx8x2HF,\
+ 
VNx2x1HF,VNx3x1HF,VNx4x1HF,VNx5x1HF,VNx6x1HF,VNx7x1HF,VNx8x1HF")
 (const_int 16)
 (eq_attr "mode" "VNx1SI,VNx2SI,VNx4SI,VNx8SI,VNx16SI,VNx32SI,\
  VNx1SF,VNx2SF,VNx4SF,VNx8SF,VNx16SF,VNx32SF,\
@@ -156,17 +161,17 @@
   (symbol_ref "riscv_vector::get_vlmul(E_VNx64HImode)")
 
 ; Half float point
-(eq_attr "mode" "VNx1HF")
+(eq_attr "mode" 
"VNx1HF,VNx2x1HF,VNx3x1HF,VNx4x1HF,VNx5x1HF,VNx6x1HF,VNx7x1HF,VNx8x1HF")
   (symbol_ref "riscv_vector::get_vlmul(E_VNx1HFmode)")
-(eq_attr "mode" "VNx2HF")
+(eq_attr "mode" 
"VNx2HF,VNx2x2HF,VNx3x2HF,VNx4x2HF,VNx5x2HF,VNx6x2HF,VNx7x2HF,VNx8x2HF")
   (symbol_ref "riscv_vector::get_vlmul(E_VNx2HFmode)")
-(eq_attr "mode" "VNx4HF")
+(eq_attr "mode" 
"VNx4HF,VNx2x4HF,VNx3x4HF,VNx4x4HF,VNx5x4HF,VNx6x4HF,VNx7x4HF,VNx8x4HF")
   (symbol_ref "riscv_vector::get_vlmul(E_VNx4HFmode)")
-(eq_attr "mode" "VNx8HF")
+(eq_attr "mode" 
"VNx8HF,VNx2x8HF,VNx3x8HF,VNx4x8HF,VNx5x8HF,VNx6x8HF,VNx7x8HF,VNx8x8HF")
   (symbol_ref "riscv_vector::get_vlmul(E_VNx8HFmode)")
-(eq_attr "mode" "VNx16HF")
+(eq_attr "mode" "VNx16HF,VNx2x16HF,VNx3x16HF,VNx4x16HF")
   (symbol_ref "riscv_vector::get_vlmul(E_VNx16HFmode)")
-(eq_attr "mode" "VNx32HF")
+(eq_attr "mode" "VNx32HF,VNx2x32HF")
   (symbol_ref "riscv_vector::get_vlmul(E_VNx32HFmode)")
 (eq_attr "mode" "VNx64HF")
   (symbol_ref "riscv_vector::get_vlmul(E_VNx64HFmode)")
@@ -249,17 +254,17 @@
   (symbol_ref "riscv_vector::get_ratio(E_VNx64HImode)")
 
 ; Half float point.
-(eq_attr "mode" "VNx1HF")
+(eq_attr "mode" 
"VNx1HF,VNx2x1HF,VNx3x1HF,VNx4x1HF,VNx5x1HF,VNx6x1HF,VNx7x1HF,VNx8x1HF")
   (symbol_ref "riscv_vector::get_ratio(E_VNx1HFmode)")
-(eq_attr "mode" "VNx2HF")
+(eq_attr "mode" 
"VNx2HF,VNx2x2HF,VNx3x2HF,VNx4x2HF,VNx5x2HF,VNx6x2HF,VNx7x2HF,VNx8x2HF")
   (symbol_ref "riscv_vector::get_ratio(E_VNx2HFmode)")
-(eq_attr "mode" "VNx4HF")
+(eq_attr "mode" 
"VNx4HF,VNx2x4HF,VNx3x4HF,VNx4x4HF,VNx5x4HF,VNx6x4HF,VNx7x4HF,VNx8x4HF")
   (symbol_ref "riscv_vector::get_ratio(E_VNx4HFmode)")
-(eq_attr "mode" "VNx8HF")
+(eq_attr "mode" 
"VNx8HF,VNx2x8HF,VNx3x8HF,VNx4x8HF,VNx5x8HF,VNx6x8HF,VNx7x8HF,VNx8x8HF")
   (symbol_ref "riscv_vector::get_ratio(E_VNx8HFmode)")
-(eq_attr "mode" "VNx16HF")
+(eq_attr "mode" "VNx16HF,VNx2x16HF,VNx3x16HF,VNx4x16HF")
   (symbol_ref "riscv_vector::get_ratio(E_VNx16HFmode)")
-

[PATCH V1] RISC-V:Add float16 tuple type support

[shiyulong]

From: yulong 

This patch adds support for the float16 tuple type.

gcc/ChangeLog:

* config/riscv/genrvv-type-indexer.cc (valid_type): Enable FP16 tuple.
* config/riscv/riscv-modes.def (RVV_TUPLE_MODES): New macro.
(ADJUST_ALIGNMENT): Ditto.
(RVV_TUPLE_PARTIAL_MODES): Ditto.
(ADJUST_NUNITS): Ditto.
* config/riscv/riscv-vector-builtins-types.def (vfloat16mf4x2_t): New 
types.
(vfloat16mf4x3_t): Ditto.
(vfloat16mf4x4_t): Ditto.
(vfloat16mf4x5_t): Ditto.
(vfloat16mf4x6_t): Ditto.
(vfloat16mf4x7_t): Ditto.
(vfloat16mf4x8_t): Ditto.
(vfloat16mf2x2_t): Ditto.
(vfloat16mf2x3_t): Ditto.
(vfloat16mf2x4_t): Ditto.
(vfloat16mf2x5_t): Ditto.
(vfloat16mf2x6_t): Ditto.
(vfloat16mf2x7_t): Ditto.
(vfloat16mf2x8_t): Ditto.
(vfloat16m1x2_t): Ditto.
(vfloat16m1x3_t): Ditto.
(vfloat16m1x4_t): Ditto.
(vfloat16m1x5_t): Ditto.
(vfloat16m1x6_t): Ditto.
(vfloat16m1x7_t): Ditto.
(vfloat16m1x8_t): Ditto.
(vfloat16m2x2_t): Ditto.
(vfloat16m2x3_t): Ditto.
(vfloat16m2x4_t): Ditto.
(vfloat16m4x2_t): Ditto.
* config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): New macro.
(vfloat16mf4x3_t): Ditto.
(vfloat16mf4x4_t): Ditto.
(vfloat16mf4x5_t): Ditto.
(vfloat16mf4x6_t): Ditto.
(vfloat16mf4x7_t): Ditto.
(vfloat16mf4x8_t): Ditto.
(vfloat16mf2x2_t): Ditto.
(vfloat16mf2x3_t): Ditto.
(vfloat16mf2x4_t): Ditto.
(vfloat16mf2x5_t): Ditto.
(vfloat16mf2x6_t): Ditto.
(vfloat16mf2x7_t): Ditto.
(vfloat16mf2x8_t): Ditto.
(vfloat16m1x2_t): Ditto.
(vfloat16m1x3_t): Ditto.
(vfloat16m1x4_t): Ditto.
(vfloat16m1x5_t): Ditto.
(vfloat16m1x6_t): Ditto.
(vfloat16m1x7_t): Ditto.
(vfloat16m1x8_t): Ditto.
(vfloat16m2x2_t): Ditto.
(vfloat16m2x3_t): Ditto.
(vfloat16m2x4_t): Ditto.
(vfloat16m4x2_t): Ditto.
* config/riscv/riscv-vector-switch.def (TUPLE_ENTRY): New.
* config/riscv/riscv.md: New.
* config/riscv/vector-iterators.md: New.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/tuple-28.c: New test.
* gcc.target/riscv/rvv/base/tuple-29.c: New test.
* gcc.target/riscv/rvv/base/tuple-30.c: New test.
* gcc.target/riscv/rvv/base/tuple-31.c: New test.
* gcc.target/riscv/rvv/base/tuple-32.c: New test.

---
 gcc/config/riscv/genrvv-type-indexer.cc   |  3 -
 gcc/config/riscv/riscv-modes.def  | 15 +
 .../riscv/riscv-vector-builtins-types.def | 25 
 gcc/config/riscv/riscv-vector-builtins.def| 30 ++
 gcc/config/riscv/riscv-vector-switch.def  | 32 ++
 gcc/config/riscv/riscv.md |  5 ++
 gcc/config/riscv/vector-iterators.md  | 37 
 .../gcc.target/riscv/rvv/base/tuple-28.c  | 59 +++
 .../gcc.target/riscv/rvv/base/tuple-29.c  | 59 +++
 .../gcc.target/riscv/rvv/base/tuple-30.c  | 58 ++
 .../gcc.target/riscv/rvv/base/tuple-31.c  | 30 ++
 .../gcc.target/riscv/rvv/base/tuple-32.c  | 16 +
 12 files changed, 366 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple-28.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple-29.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple-30.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple-31.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple-32.c

diff --git a/gcc/config/riscv/genrvv-type-indexer.cc 
b/gcc/config/riscv/genrvv-type-indexer.cc
index 8fc93ceaab4..a332a6a3334 100644
--- a/gcc/config/riscv/genrvv-type-indexer.cc
+++ b/gcc/config/riscv/genrvv-type-indexer.cc
@@ -73,9 +73,6 @@ valid_type (unsigned sew, int lmul_log2, unsigned nf, bool 
float_p)
   if (nf > 8 || nf < 1)
 return false;
 
-  if (sew == 16 && nf != 1 && float_p) // Disable FP16 tuple in temporarily.
-return false;
-
   switch (lmul_log2)
 {
 case 1:
diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
index 19a4f9fb3db..1d152709ddc 100644
--- a/gcc/config/riscv/riscv-modes.def
+++ b/gcc/config/riscv/riscv-modes.def
@@ -220,6 +220,7 @@ ADJUST_ALIGNMENT (VNx1QI, 1);
 #define RVV_TUPLE_MODES(NBYTES, NSUBPARTS, VB, VH, VS, VD) 
\
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, NBYTES, 1); 
\
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, NBYTES / 2, 1); 
\
+  VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, HF, NBYTES / 2, 1);   
\
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, SI, NBYTES / 4, 1); 
\
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, SF, NBYTES / 4, 1);   

[PATCH V2] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c

[shiyulong]

From: yulong 

I find fail of the xtheadcondmov-indirect-rv64.c test case and provide a way to 
solve it.
In this patch, I take Kito's advice that I modify the form of the function 
bodies.It likes
*[a-x0-9].

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadcondmov-indirect-rv32.c:Modify
* gcc.target/riscv/xtheadcondmov-indirect-rv64.c:Modify

---
 .../riscv/xtheadcondmov-indirect-rv32.c   | 50 +--
 .../riscv/xtheadcondmov-indirect-rv64.c   | 50 +--
 2 files changed, 50 insertions(+), 50 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c 
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
index e2b135f3d00..d0df59c5e1c 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
@@ -5,9 +5,9 @@
 
 /*
 **ConEmv_imm_imm_reg:
-** addia5,a0,-1000
-** li  a0,10
-** th.mvneza0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
 ** ret
 */
 int ConEmv_imm_imm_reg(int x, int y){
@@ -17,9 +17,9 @@ int ConEmv_imm_imm_reg(int x, int y){
 
 /*
 **ConEmv_imm_reg_reg:
-** addia5,a0,-1000
-** th.mveqza2,a1,a5
-** mv  a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
 ** ret
 */
 int ConEmv_imm_reg_reg(int x, int y, int z){
@@ -29,9 +29,9 @@ int ConEmv_imm_reg_reg(int x, int y, int z){
 
 /*
 **ConEmv_reg_imm_reg:
-** sub a1,a0,a1
-** li  a0,10
-** th.mvneza0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
 ** ret
 */
 int ConEmv_reg_imm_reg(int x, int y, int z){
@@ -41,9 +41,9 @@ int ConEmv_reg_imm_reg(int x, int y, int z){
 
 /*
 **ConEmv_reg_reg_reg:
-** sub a1,a0,a1
-** th.mveqza3,a2,a1
-** mv  a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
 ** ret
 */
 int ConEmv_reg_reg_reg(int x, int y, int z, int n){
@@ -53,10 +53,10 @@ int ConEmv_reg_reg_reg(int x, int y, int z, int n){
 
 /*
 **ConNmv_imm_imm_reg:
-** addia5,a0,-1000
-** li  a0,9998336
-** addia0,a0,1664
-** th.mveqza0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,9998336+
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,1664+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
 ** ret
 */
 int ConNmv_imm_imm_reg(int x, int y){
@@ -66,9 +66,9 @@ int ConNmv_imm_imm_reg(int x, int y){
 
 /*
 **ConNmv_imm_reg_reg:
-** addia0,a0,-1000
-** th.mvneza2,a1,a0
-** mv  a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
 ** ret
 */
 int ConNmv_imm_reg_reg(int x, int y, int z){
@@ -78,9 +78,9 @@ int ConNmv_imm_reg_reg(int x, int y, int z){
 
 /*
 **ConNmv_reg_imm_reg:
-** sub a1,a0,a1
-** li  a0,10
-** th.mveqza0,a2,a1
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** li\t\s*[a-x0-9]+,10+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
 ** ret
 */
 int ConNmv_reg_imm_reg(int x, int y, int z){
@@ -90,9 +90,9 @@ int ConNmv_reg_imm_reg(int x, int y, int z){
 
 /*
 **ConNmv_reg_reg_reg:
-** sub a0,a0,a1
-** th.mvneza3,a2,a0
-** mv  a0,a3
+** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
 ** ret
 */
 int ConNmv_reg_reg_reg(int x, int y, int z, int n){
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c 
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
index 99956f8496c..cc971a75ace 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
@@ -5,9 +5,9 @@
 
 /*
 **ConEmv_imm_imm_reg:
-** addia5,a0,-1000
-** li  a0,10
-** th.mvneza0,a1,a5
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** li\t\s*[a-x0-9]+,10+
+** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
 ** ret
 */
 int ConEmv_imm_imm_reg(int x, int y){
@@ -17,9 +17,9 @@ int ConEmv_imm_imm_reg(int x, int y){
 
 /*
 **ConEmv_imm_reg_reg:
-** addia0,a0,-1000
-** th.mveqza2,a1,a5
-** mv  a0,a2
+** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
+** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
+** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
 ** ret
 */
 int ConEmv_imm_reg_reg(int x, int y, int z){
@@ -29,9 +29,9 @@ int ConEmv_imm_reg_reg(int x, int y, int z){
 
 /*
 

[PATCH V1] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c

[shiyulong]

From: yulong 

I find fail of the xtheadcondmov-indirect-rv64.c test case and provide the way 
to solve it.
In this patch, I modify the check information of the 
function(ConEmv_imm_imm_reg and ConNmv_imm_imm_reg) body.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadcondmov-indirect-rv64.c:Modify

---
 gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c 
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
index 99956f8496c..dda0f902c32 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
@@ -17,7 +17,7 @@ int ConEmv_imm_imm_reg(int x, int y){
 
 /*
 **ConEmv_imm_reg_reg:
-** addia0,a0,-1000
+** addia5,a0,-1000
 ** th.mveqza2,a1,a5
 ** mv  a0,a2
 ** ret
@@ -66,7 +66,7 @@ int ConNmv_imm_imm_reg(int x, int y){
 
 /*
 **ConNmv_imm_reg_reg:
-** addia5,a0,-1000
+** addia0,a0,-1000
 ** th.mvneza2,a1,a0
 ** mv  a0,a2
 ** ret
-- 
2.25.1

[PATCH V5] Testsuite: Fix a redefinition bug for the fd-4.c

[shiyulong]

From: yulong 

This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the 
definition in types.h that be included by stdio.h.
Thanks to Jeff Law for reviewing the previous version.

gcc/testsuite/ChangeLog:

* gcc.dg/analyzer/fd-4.c: delete the definition of mode_t.

---
 gcc/testsuite/gcc.dg/analyzer/fd-4.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-4.c 
b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
index 994bad84342..9ec015679e9 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-4.c
+++ b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
@@ -13,11 +13,6 @@ int read (int fd, void *buf, int nbytes);
 #define O_WRONLY 1
 #define O_RDWR 2
 
-typedef enum {
-  S_IRWXU
-  // etc
-} mode_t;
-
 int creat (const char *, mode_t mode);
 
 void
-- 
2.25.1

[PATCH V2] RISC-V: Modified validation information for contracts-tmpl-spec2.C

[shiyulong]

From: yulong 

This patch fixes the problem of the contracts-tmpl-spec2.c running failure.
When run the dejagnu test, I find that the output is inconsistent with that 
verified
in the testcase. So I try to modify it, and then it can be passed.

gcc/testsuite/ChangeLog:

* g++.dg/contracts/contracts-tmpl-spec2.C:delete some output information

---
 gcc/testsuite/g++.dg/contracts/contracts-tmpl-spec2.C | 6 --
 1 file changed, 6 deletions(-)

diff --git a/gcc/testsuite/g++.dg/contracts/contracts-tmpl-spec2.C 
b/gcc/testsuite/g++.dg/contracts/contracts-tmpl-spec2.C
index 82117671b2d..17048584ac9 100644
--- a/gcc/testsuite/g++.dg/contracts/contracts-tmpl-spec2.C
+++ b/gcc/testsuite/g++.dg/contracts/contracts-tmpl-spec2.C
@@ -369,15 +369,9 @@ int main(int, char**)
 // { dg-output {contract violation in function G3::f at .*:148: s 
> 2(\n|\r\n|\r)} }
 // { dg-output {\[continue:on\](\n|\r\n|\r)} }
 // { dg-output {G3 full int double(\n|\r\n|\r)} }
-// { dg-output {contract violation in function G3::f at .*:124: t 
> 0(\n|\r\n|\r)} }
-// { dg-output {\[continue:on\](\n|\r\n|\r)} }
-// { dg-output {contract violation in function G3::f at .*:125: s 
> 0(\n|\r\n|\r)} }
-// { dg-output {\[continue:on\](\n|\r\n|\r)} }
 // { dg-output {G3 general T S(\n|\r\n|\r)} }
 // { dg-output {contract violation in function G3::f at .*:139: t > 
1(\n|\r\n|\r)} }
 // { dg-output {\[continue:on\](\n|\r\n|\r)} }
-// { dg-output {contract violation in function G3::f at .*:140: s > 
1(\n|\r\n|\r)} }
-// { dg-output {\[continue:on\](\n|\r\n|\r)} }
 // { dg-output {G3 partial int S(\n|\r\n|\r)} }
 // { dg-output {G3 full int C(\n|\r\n|\r)} }
 // { dg-output {G3 full int C(\n|\r\n|\r)} }
-- 
2.25.1

[PATCH V4] RISC-V: Fix a redefinition bug for the fd-4.c

[shiyulong]

From: yulong 

This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the 
definition in types.h that be included by stdio.h.

gcc/testsuite/ChangeLog:

* gcc.dg/analyzer/fd-4.c: delete the definition of mode_t.

---
 gcc/testsuite/gcc.dg/analyzer/fd-4.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-4.c 
b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
index 994bad84342..9ec015679e9 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-4.c
+++ b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
@@ -13,11 +13,6 @@ int read (int fd, void *buf, int nbytes);
 #define O_WRONLY 1
 #define O_RDWR 2
 
-typedef enum {
-  S_IRWXU
-  // etc
-} mode_t;
-
 int creat (const char *, mode_t mode);
 
 void
-- 
2.25.1

[PATCH V1] RISCV: Modified validation information for contracts-tmpl-spec2.C

[shiyulong]

From: yulong 

This patch fixes the problem of the contracts-tmpl-spec2.c running failure.

When run the dejagnu test, I find that the output is inconsistent with that 
verified
in the testcase. So I try to modify it, and then it can be passed.

gcc/testsuite/ChangeLog:

* g++.dg/contracts/contracts-tmpl-spec2.C:delete some output information

---
 gcc/testsuite/g++.dg/contracts/contracts-tmpl-spec2.C | 6 --
 1 file changed, 6 deletions(-)

diff --git a/gcc/testsuite/g++.dg/contracts/contracts-tmpl-spec2.C 
b/gcc/testsuite/g++.dg/contracts/contracts-tmpl-spec2.C
index 82117671b2d..17048584ac9 100644
--- a/gcc/testsuite/g++.dg/contracts/contracts-tmpl-spec2.C
+++ b/gcc/testsuite/g++.dg/contracts/contracts-tmpl-spec2.C
@@ -369,15 +369,9 @@ int main(int, char**)
 // { dg-output {contract violation in function G3::f at .*:148: s 
> 2(\n|\r\n|\r)} }
 // { dg-output {\[continue:on\](\n|\r\n|\r)} }
 // { dg-output {G3 full int double(\n|\r\n|\r)} }
-// { dg-output {contract violation in function G3::f at .*:124: t 
> 0(\n|\r\n|\r)} }
-// { dg-output {\[continue:on\](\n|\r\n|\r)} }
-// { dg-output {contract violation in function G3::f at .*:125: s 
> 0(\n|\r\n|\r)} }
-// { dg-output {\[continue:on\](\n|\r\n|\r)} }
 // { dg-output {G3 general T S(\n|\r\n|\r)} }
 // { dg-output {contract violation in function G3::f at .*:139: t > 
1(\n|\r\n|\r)} }
 // { dg-output {\[continue:on\](\n|\r\n|\r)} }
-// { dg-output {contract violation in function G3::f at .*:140: s > 
1(\n|\r\n|\r)} }
-// { dg-output {\[continue:on\](\n|\r\n|\r)} }
 // { dg-output {G3 partial int S(\n|\r\n|\r)} }
 // { dg-output {G3 full int C(\n|\r\n|\r)} }
 // { dg-output {G3 full int C(\n|\r\n|\r)} }
-- 
2.25.1

[PATCH V3] RISC-V: Fix a redefinition bug for the fd-4.c

[shiyulong]

From: yulong 

This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the 
definition in stdio.h.

gcc/testsuite/ChangeLog:

* gcc.dg/analyzer/fd-4.c: delete the definition of mode_t.

---
 gcc/testsuite/gcc.dg/analyzer/fd-4.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-4.c 
b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
index 994bad84342..9ec015679e9 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-4.c
+++ b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
@@ -13,11 +13,6 @@ int read (int fd, void *buf, int nbytes);
 #define O_WRONLY 1
 #define O_RDWR 2
 
-typedef enum {
-  S_IRWXU
-  // etc
-} mode_t;
-
 int creat (const char *, mode_t mode);
 
 void
-- 
2.25.1

[PATCH V1 1/1] UNRATIFIED RISC-V: Add 'ZiCond' extension

[shiyulong]

From: yulong 

[DO NOT MERGE]
Until 'ZiCond' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream.  This commit uses
version 1.0 as in the documentation.

This commit adds support for the latest draft of RISC-V Integer Conditional
(ZiCond) extension consisting of 2 new instructions.

This is based on the early draft of ZiCond on GitHub:


gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add zicond ext.
* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New.
(AVAIL): New.
(RISCV_FTYPE_ATYPES2): New.
* config/riscv/riscv-ftypes.def (2): New.
* config/riscv/riscv-opts.h (MASK_ZICOND): New.
(TARGET_ZICOND): New.
* config/riscv/riscv.md (riscv_eqz_): Add new mode.
(riscv_nez_): Add new mode.
* config/riscv/riscv.opt: New.
* config/riscv/riscv-zicond.def: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zicond-1.c: New test.
* gcc.target/riscv/zicond-2.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |  4 
 gcc/config/riscv/riscv-builtins.cc|  8 
 gcc/config/riscv/riscv-ftypes.def |  2 ++
 gcc/config/riscv/riscv-opts.h |  3 +++
 gcc/config/riscv/riscv-zicond.def |  5 +
 gcc/config/riscv/riscv.md | 22 ++
 gcc/config/riscv/riscv.opt|  3 +++
 gcc/testsuite/gcc.target/riscv/zicond-1.c | 15 +++
 gcc/testsuite/gcc.target/riscv/zicond-2.c | 15 +++
 9 files changed, 77 insertions(+)
 create mode 100644 gcc/config/riscv/riscv-zicond.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 787674003cb..5a8b1278ac8 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -190,6 +190,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zicond",ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zk",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zkn",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zks",   ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1209,6 +1211,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
   {"zicbop", _options::x_riscv_zicmo_subext, MASK_ZICBOP},
 
+  {"zicond", _options::x_riscv_zicond_subext, MASK_ZICOND},
+
   {"zve32x",   _options::x_target_flags, MASK_VECTOR},
   {"zve32f",   _options::x_target_flags, MASK_VECTOR},
   {"zve64x",   _options::x_target_flags, MASK_VECTOR},
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 25ca407f9a9..66a8126b2b4 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -42,6 +42,7 @@ along with GCC; see the file COPYING3.  If not see
 /* Macros to create an enumeration identifier for a function prototype.  */
 #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
 #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
+#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
 
 /* Classifies the prototype of a built-in function.  */
 enum riscv_function_type {
@@ -99,6 +100,10 @@ AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
 AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
 AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
 AVAIL (always, (!0))
+AVAIL (nez32, TARGET_ZICOND && !TARGET_64BIT)
+AVAIL (nez64, TARGET_ZICOND && TARGET_64BIT)
+AVAIL (eqz32, TARGET_ZICOND && !TARGET_64BIT)
+AVAIL (eqz64, TARGET_ZICOND && TARGET_64BIT)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -142,9 +147,12 @@ AVAIL (always, (!0))
   RISCV_ATYPE_##A
 #define RISCV_FTYPE_ATYPES1(A, B) \
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
+#define RISCV_FTYPE_ATYPES2(A, B, C) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
 
 static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-cmo.def"
+  #include "riscv-zicond.def"
 
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 3a40c33e7c2..d305282d811 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -32,3 +32,5 @@ DEF_RISCV_FTYPE (1, (VOID, USI))
 DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
 DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
+DEF_RISCV_FTYPE (2, (SI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, DI))
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index ff398c0a2ae..0baf6553913 100644
--- 

[PATCH V1 0/1] UNRATIFIED RISC-V:Add 'ZiCond' extension

[shiyulong]

From: yulong 

*** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and not frozen RISC-V extension
and not intended to be merged for now.
The intent to submit this patchset is to synchronize with the implementation
of binutils about the ZiCond extension.

This patchset adds following unratified extension to GNU gcc:

- 'ZiCond'(Integer Conditional Operations) version 1.0 development which
adds 2 instructions ('czero.eqz' and 'czero.nez').

This extension makes conditional arithmetic feature much simpler (fewer
instructions when no branches are allowed).  Note that constant timing
guarantee (data-independence / certain side-channel resistance) for this
extension is being discussed and may not be guaranteed.


This is based on the commit 394e24376939 of the specification document:


*** BLURB HERE ***

yulong (1):
  UNRATIFIED RISC-V: Add 'ZiCond' extension

 gcc/common/config/riscv/riscv-common.cc   |  4 
 gcc/config/riscv/riscv-builtins.cc|  8 
 gcc/config/riscv/riscv-ftypes.def |  2 ++
 gcc/config/riscv/riscv-opts.h |  3 +++
 gcc/config/riscv/riscv-zicond.def |  5 +
 gcc/config/riscv/riscv.md | 22 ++
 gcc/config/riscv/riscv.opt|  3 +++
 gcc/testsuite/gcc.target/riscv/zicond-1.c | 15 +++
 gcc/testsuite/gcc.target/riscv/zicond-2.c | 15 +++
 9 files changed, 77 insertions(+)
 create mode 100644 gcc/config/riscv/riscv-zicond.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-2.c

-- 
2.25.1

[PATCH V1] RISC-V: Fix a redefinition bug for the fd-4.c

[shiyulong]

From: yulong 

This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the 
definition in stdio.h.There are have a definition about mode_t in the fd-4.c, 
but it duplicates the definition in stdio.h.

gcc/testsuite/ChangeLog:

* gcc.dg/analyzer/fd-4.c: delete the definition of mode_t.

---
 gcc/testsuite/gcc.dg/analyzer/fd-4.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-4.c 
b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
index 842a26b4364..db342feb6ee 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-4.c
+++ b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
@@ -12,11 +12,6 @@ int read (int fd, void *buf, int nbytes);
 #define O_WRONLY 1
 #define O_RDWR 2
 
-typedef enum {
-  S_IRWXU
-  // etc
-} mode_t;
-
 int creat (const char *, mode_t mode);
 
 void
-- 
2.17.1

[PATCH V0] RISC-V: Fix a redefinition bug for the fd-4.c

[shiyulong]

From: yulong 

This patch fix a redefinition bug.
There are have a definition about mode_t in the fd-4.c, but it duplicates the 
definition in stdio.h.

gcc/testsuite/ChangeLog:

* gcc.dg/analyzer/fd-4.c: delete the definition of mode_t.

---
 gcc/testsuite/gcc.dg/analyzer/fd-4.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/analyzer/fd-4.c 
b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
index 842a26b4364..db342feb6ee 100644
--- a/gcc/testsuite/gcc.dg/analyzer/fd-4.c
+++ b/gcc/testsuite/gcc.dg/analyzer/fd-4.c
@@ -12,11 +12,6 @@ int read (int fd, void *buf, int nbytes);
 #define O_WRONLY 1
 #define O_RDWR 2
 
-typedef enum {
-  S_IRWXU
-  // etc
-} mode_t;
-
 int creat (const char *, mode_t mode);
 
 void
-- 
2.17.1

[PATCH V3] RISC-V:Fix a bug that is the CMO builtins are missing parameter

[shiyulong]

From: yulong 

We changed builtins format about zicbom and zicboz subextensions and modified 
test cases.
diff with the previous version:
1.We modified the FUNCTION_TYPE from RISCV_VOID_FTYPE_SI/DI to 
RISCV_VOID_FTYPE_VOID_PTR.
2.We added a new RISCV_ATYPE_VOID_PTR in riscv-builtins.cc and a new 
DEF_RISCV_FTYPE (1, (VOID, VOID_PTR)) in riscv-ftypes.def.
3.We deleted DEF_RISCV_FTYPE (1, (VOID, SI/DI)).
4.We modified the input parameters of the test cases.

Thanks, Simon and Kito.

gcc/ChangeLog:

* config/riscv/riscv-builtins.cc (RISCV_ATYPE_VOID_PTR): New.
* config/riscv/riscv-cmo.def (RISCV_BUILTIN): changed the FUNCTION_TYPE 
of RISCV_BUILTIN.
* config/riscv/riscv-ftypes.def (0): New.
(1):

gcc/testsuite/ChangeLog:

* gcc.target/riscv/cmo-zicbom-1.c: modified the input parameters.
* gcc.target/riscv/cmo-zicbom-2.c: modified the input parameters.
* gcc.target/riscv/cmo-zicboz-1.c: modified the input parameters.
* gcc.target/riscv/cmo-zicboz-2.c: modified the input parameters.

---
 gcc/config/riscv/riscv-builtins.cc|  1 +
 gcc/config/riscv/riscv-cmo.def| 16 ++--
 gcc/config/riscv/riscv-ftypes.def |  3 +--
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 26 ---
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 26 ---
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 10 ---
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 10 ---
 7 files changed, 58 insertions(+), 34 deletions(-)

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 795132a0c16..1218fdfc67d 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -133,6 +133,7 @@ AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
 #define RISCV_ATYPE_SI intSI_type_node
 #define RISCV_ATYPE_DI intDI_type_node
+#define RISCV_ATYPE_VOID_PTR ptr_type_node
 
 /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs.  */
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index b30ecf96ec1..9fe5094ce1a 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -1,16 +1,16 @@
 // zicbom
-RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, clean32),
-RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, clean64),
+RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_VOID_PTR, clean32),
+RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_VOID_PTR, clean64),
 
-RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, flush32),
-RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, flush64),
+RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_VOID_PTR, flush32),
+RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_VOID_PTR, flush64),
 
-RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, inval32),
-RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, inval64),
+RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_VOID_PTR, inval32),
+RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_VOID_PTR, inval64),
 
 // zicboz
-RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, zero32),
-RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, zero64),
+RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_VOID_PTR, zero32),
+RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_VOID_PTR, zero64),
 
 // zicbop
 RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, prefetchi32),
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 62421292ce7..c2b45c63ea1 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -28,7 +28,6 @@ along with GCC; see the file COPYING3.  If not see
 
 DEF_RISCV_FTYPE (0, (USI))
 DEF_RISCV_FTYPE (1, (VOID, USI))
-DEF_RISCV_FTYPE (0, (SI))
-DEF_RISCV_FTYPE (0, (DI))
+DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
 DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
index e2ba2183511..6341f7874d3 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
@@ -1,21 +1,29 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gc_zicbom -mabi=lp64" } */
 
-int 

[PATCH V2] RISC-V:Fix a bug that is the CMO builtins are missing parameter

[shiyulong]

From: yulong 

We changed builtins format about zicbom and zicboz subextensions and added test 
cases.
diff with the previous version:
1.We deleted the RLT mode's second input operand.
2.We modified the type of builtins from RISCV_BUILTIN_DIRECT to 
RISCV_BUILTIN_DIRECT_NO_TARGET.
3.We modified the test cases and added more parameter tests.

Thanks, Simon and Kito.

gcc/ChangeLog:

* config/riscv/riscv-cmo.def (RISCV_BUILTIN): changed BUILTIN_TYPE and 
FUNCTION_TYPE
* config/riscv/riscv-ftypes.def (0): changed "DEF_RISCV_FTYPE (0, 
(SI/DI))" to "DEF_RISCV_FTYPE (1, (VOID, SI/DI))"
(1):

gcc/testsuite/ChangeLog:

* gcc.target/riscv/cmo-zicbom-1.c: added parameter and modified the 
fun's type
* gcc.target/riscv/cmo-zicbom-2.c: added parameter and modified the 
fun's type
* gcc.target/riscv/cmo-zicboz-1.c: added parameter and modified the 
fun's type
* gcc.target/riscv/cmo-zicboz-2.c: added parameter and modified the 
fun's type

---
 gcc/config/riscv/riscv-cmo.def| 16 ++--
 gcc/config/riscv/riscv-ftypes.def |  4 +--
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 25 ---
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 25 ---
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c |  9 ---
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c |  9 ---
 6 files changed, 54 insertions(+), 34 deletions(-)

diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index b30ecf96ec1..7b3da7c24ef 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -1,16 +1,16 @@
 // zicbom
-RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, clean32),
-RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, clean64),
+RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_SI, clean32),
+RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_DI, clean64),
 
-RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, flush32),
-RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, flush64),
+RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_SI, flush32),
+RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_DI, flush64),
 
-RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, inval32),
-RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, inval64),
+RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_SI, inval32),
+RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_DI, inval64),
 
 // zicboz
-RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, zero32),
-RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, zero64),
+RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_SI, zero32),
+RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_DI, zero64),
 
 // zicbop
 RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, prefetchi32),
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 62421292ce7..77ac6ea3f66 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -28,7 +28,7 @@ along with GCC; see the file COPYING3.  If not see
 
 DEF_RISCV_FTYPE (0, (USI))
 DEF_RISCV_FTYPE (1, (VOID, USI))
-DEF_RISCV_FTYPE (0, (SI))
-DEF_RISCV_FTYPE (0, (DI))
+DEF_RISCV_FTYPE (1, (VOID, SI))
+DEF_RISCV_FTYPE (1, (VOID, DI))
 DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
index e2ba2183511..2bf5b77380e 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
@@ -1,21 +1,28 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gc_zicbom -mabi=lp64" } */
+int var;
 
-int foo1()
+void foo1()
 {
-return __builtin_riscv_zicbom_cbo_clean();
+__builtin_riscv_zicbom_cbo_clean(0);
+__builtin_riscv_zicbom_cbo_clean(var);
+__builtin_riscv_zicbom_cbo_clean(0x111);
 }
 
-int foo2()
+void foo2()
 {
-return __builtin_riscv_zicbom_cbo_flush();
+__builtin_riscv_zicbom_cbo_flush(0);
+__builtin_riscv_zicbom_cbo_flush(var);
+__builtin_riscv_zicbom_cbo_flush(0x111);
 }
 
-int foo3()
+void foo3()
 {
-return __builtin_riscv_zicbom_cbo_inval();
+__builtin_riscv_zicbom_cbo_inval(0);
+__builtin_riscv_zicbom_cbo_inval(var);
+__builtin_riscv_zicbom_cbo_inval(0x111);
 }
 
-/* { dg-final { scan-assembler-times "cbo.clean" 1 } } 

[PATCH] RISC-V:Fix a bug that is the CMO builtins are missing parameter

[shiyulong]

From: yulong 

We changed the RTL mode and builtins format about zicbom and zicboz 
subextensions.

gcc/ChangeLog:

* config/riscv/riscv-cmo.def (RISCV_BUILTIN): changed 
"RISCV_SI(DI)_FTYPE" to "RISCV_SI(DI)_FTPYE_SI(DI)"
* config/riscv/riscv-ftypes.def (0): deleted DEF_RISCV_FTYPE (0,(SI)) 
and DEF_RISCV_FTYPE (0,(DI))
* config/riscv/riscv.md: added a immediate_operand about cbo.clean, 
cbo.flush, cbo.inval and cbo.zero instructions

gcc/testsuite/ChangeLog:

* gcc.target/riscv/cmo-zicbom-1.c: added a parameter
* gcc.target/riscv/cmo-zicbom-2.c: added a parameter
* gcc.target/riscv/cmo-zicboz-1.c: added a parameter
* gcc.target/riscv/cmo-zicboz-2.c: added a parameter

---
 gcc/config/riscv/riscv-cmo.def| 16 
 gcc/config/riscv/riscv-ftypes.def |  2 --
 gcc/config/riscv/riscv.md | 12 
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c |  6 +++---
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c |  6 +++---
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c |  2 +-
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c |  2 +-
 7 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index b30ecf96ec1..d43cbf62954 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -1,16 +1,16 @@
 // zicbom
-RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, clean32),
-RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, clean64),
+RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, clean32),
+RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI, clean64),
 
-RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, flush32),
-RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, flush64),
+RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, flush32),
+RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI, flush64),
 
-RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, inval32),
-RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, inval64),
+RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, inval32),
+RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI, inval64),
 
 // zicboz
-RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, zero32),
-RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, zero64),
+RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, zero32),
+RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI, zero64),
 
 // zicbop
 RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, prefetchi32),
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 62421292ce7..445eb8ee05d 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -28,7 +28,5 @@ along with GCC; see the file COPYING3.  If not see
 
 DEF_RISCV_FTYPE (0, (USI))
 DEF_RISCV_FTYPE (1, (VOID, USI))
-DEF_RISCV_FTYPE (0, (SI))
-DEF_RISCV_FTYPE (0, (DI))
 DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b8ab0cf169a..2d7d94eebd3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2893,28 +2893,32 @@
   [(set_attr "length" "12")])
 
 (define_insn "riscv_clean_"
-  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+   (match_operand:X 1 "immediate_operand" "i")]
 UNSPECV_CLEAN)]
   "TARGET_ZICBOM"
   "cbo.clean\t%a0"
 )
 
 (define_insn "riscv_flush_"
-  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+   (match_operand:X 1 "immediate_operand" "i")]
 UNSPECV_FLUSH)]
   "TARGET_ZICBOM"
   "cbo.flush\t%a0"
 )
 
 (define_insn "riscv_inval_"
-  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+   (match_operand:X 1 "immediate_operand" "i")]
 UNSPECV_INVAL)]
   "TARGET_ZICBOM"
   "cbo.inval\t%a0"
 )
 
 (define_insn "riscv_zero_"
-  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+   (match_operand:X 1 "immediate_operand" "i")]
 UNSPECV_ZERO)]
   "TARGET_ZICBOZ"
   "cbo.zero\t%a0"
diff --git 

[PATCH V4 3/3] RISC-V:Cache Management Operation instructions testcases

[shiyulong]

From: yulong 

This commit adds testcases about CMO instructions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/cmo-zicbom-1.c: New test.
* gcc.target/riscv/cmo-zicbom-2.c: New test.
* gcc.target/riscv/cmo-zicbop-1.c: New test.
* gcc.target/riscv/cmo-zicbop-2.c: New test.
* gcc.target/riscv/cmo-zicboz-1.c: New test.
* gcc.target/riscv/cmo-zicboz-2.c: New test.
---
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 +
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 +
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 +++
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 +++
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c |  9 
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c |  9 
 6 files changed, 106 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c

diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
new file mode 100644
index 000..e2ba2183511
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicbom -mabi=lp64" } */
+
+int foo1()
+{
+return __builtin_riscv_zicbom_cbo_clean();
+}
+
+int foo2()
+{
+return __builtin_riscv_zicbom_cbo_flush();
+}
+
+int foo3()
+{
+return __builtin_riscv_zicbom_cbo_inval();
+}
+
+/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
new file mode 100644
index 000..a605e8b1bdc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zicbom -mabi=ilp32" } */
+
+int foo1()
+{
+return __builtin_riscv_zicbom_cbo_clean();
+}
+
+int foo2()
+{
+return __builtin_riscv_zicbom_cbo_flush();
+}
+
+int foo3()
+{
+return __builtin_riscv_zicbom_cbo_inval();
+}
+
+/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
new file mode 100644
index 000..c5d78c1763d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile target { { rv64-*-*}}} */
+/* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */
+
+void foo (char *p)
+{
+  __builtin_prefetch (p, 0, 0);
+  __builtin_prefetch (p, 0, 1);
+  __builtin_prefetch (p, 0, 2);
+  __builtin_prefetch (p, 0, 3);
+  __builtin_prefetch (p, 1, 0);
+  __builtin_prefetch (p, 1, 1);
+  __builtin_prefetch (p, 1, 2);
+  __builtin_prefetch (p, 1, 3);
+}
+
+int foo1()
+{
+  return __builtin_riscv_zicbop_cbo_prefetchi(1);
+}
+
+/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
+/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
new file mode 100644
index 000..6576365b39c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile target { { rv32-*-*}}} */
+/* { dg-options "-march=rv32gc_zicbop -mabi=ilp32" } */
+
+void foo (char *p)
+{
+  __builtin_prefetch (p, 0, 0);
+  __builtin_prefetch (p, 0, 1);
+  __builtin_prefetch (p, 0, 2);
+  __builtin_prefetch (p, 0, 3);
+  __builtin_prefetch (p, 1, 0);
+  __builtin_prefetch (p, 1, 1);
+  __builtin_prefetch (p, 1, 2);
+  __builtin_prefetch (p, 1, 3);
+}
+
+int foo1()
+{
+  return __builtin_riscv_zicbop_cbo_prefetchi(1);
+}
+
+/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
+/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ 
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
new file mode 100644
index 000..96c1674ef2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicboz -mabi=lp64" } */
+
+int foo1()
+{
+return __builtin_riscv_zicboz_cbo_zero();
+}
+
+/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */ 
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c 

[PATCH V4 2/3] RISC-V:Cache Management Operation instructions

[shiyulong]

From: yulong 

This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r 
and prefetch.w instructions.
diff with the previous version:
We use unspec_volatile instead of unspec for those cache operations. We use 
UNSPECV instead of UNSPEC and move them to unspecv.

gcc/ChangeLog:

* config/riscv/predicates.md (imm5_operand): Add a new operand type for 
prefetch instructions.
* config/riscv/riscv-builtins.cc (AVAIL): Add new AVAILs for CMO ISA 
Extensions.
(RISCV_ATYPE_SI): New.
(RISCV_ATYPE_DI): New.
* config/riscv/riscv-ftypes.def (0): New.
(1): New.
* config/riscv/riscv.md (riscv_clean_): New.
(riscv_flush_): New.
(riscv_inval_): New.
(riscv_zero_): New.
(prefetch): New.
(riscv_prefetchi_): New.
* config/riscv/riscv-cmo.def: New file.
---
 gcc/config/riscv/predicates.md |  4 +++
 gcc/config/riscv/riscv-builtins.cc | 16 ++
 gcc/config/riscv/riscv-cmo.def | 17 ++
 gcc/config/riscv/riscv-ftypes.def  |  4 +++
 gcc/config/riscv/riscv.md  | 51 ++
 5 files changed, 92 insertions(+)
 create mode 100644 gcc/config/riscv/riscv-cmo.def

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 97cdbdf053b..3fb4d95ab08 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -239,3 +239,7 @@
 (define_predicate "const63_operand"
   (and (match_code "const_int")
(match_test "INTVAL (op) == 63")))
+
+(define_predicate "imm5_operand"
+  (and (match_code "const_int")
+   (match_test "INTVAL (op) < 5")))
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 0658f8d3047..795132a0c16 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -87,6 +87,18 @@ struct riscv_builtin_description {
 
 AVAIL (hard_float, TARGET_HARD_FLOAT)
 
+
+AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (clean64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (flush32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (flush64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (zero32,  TARGET_ZICBOZ && !TARGET_64BIT)
+AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
+AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
+AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+
 /* Construct a riscv_builtin_description from the given arguments.
 
INSN is the name of the associated instruction pattern, without the
@@ -119,6 +131,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
+#define RISCV_ATYPE_SI intSI_type_node
+#define RISCV_ATYPE_DI intDI_type_node
 
 /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs.  */
@@ -128,6 +142,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
 
 static const struct riscv_builtin_description riscv_builtins[] = {
+  #include "riscv-cmo.def"
+
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
 };
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
new file mode 100644
index 000..01cbf6ad64f
--- /dev/null
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -0,0 +1,17 @@
+// zicbom
+RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, clean32),
+RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, clean64),
+
+RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, flush32),
+RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, flush64),
+
+RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, inval32),
+RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, inval64),
+
+// zicboz
+RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, zero32),
+RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, zero64),
+
+// zicbop
+RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, prefetchi32),
+RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI, prefetchi64),
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 2214c496f9b..62421292ce7 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -28,3 +28,7 @@ along with GCC; see the file COPYING3.  If not see
 
 DEF_RISCV_FTYPE (0, (USI))
 DEF_RISCV_FTYPE (1, (VOID, USI))
+DEF_RISCV_FTYPE (0, (SI))
+DEF_RISCV_FTYPE (0, (DI))
+DEF_RISCV_FTYPE (1, (SI, SI))
+DEF_RISCV_FTYPE 

[PATCH V4 1/3] RISC-V: Add mininal support for Zicbo[mzp]

[shiyulong]

From: yulong 

This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop 
extensions.
* config/riscv/riscv-opts.h (MASK_ZICBOZ): New.
(MASK_ZICBOM): New.
(MASK_ZICBOP): New.
(TARGET_ZICBOZ): New.
(TARGET_ZICBOM): New.
(TARGET_ZICBOP): New.
* config/riscv/riscv.opt: New.

---
 gcc/common/config/riscv/riscv-common.cc | 8 
 gcc/config/riscv/riscv-opts.h   | 8 
 gcc/config/riscv/riscv.opt  | 3 +++
 3 files changed, 19 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 1501242e296..bf7a7caabef 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -165,6 +165,10 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zksh",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zk",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zkn",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zks",   ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1110,6 +1114,10 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zksh",   _options::x_riscv_zk_subext, MASK_ZKSH},
   {"zkt",_options::x_riscv_zk_subext, MASK_ZKT},
 
+  {"zicboz", _options::x_riscv_zicmo_subext, MASK_ZICBOZ},
+  {"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
+  {"zicbop", _options::x_riscv_zicmo_subext, MASK_ZICBOP},
+
   {"zve32x",   _options::x_target_flags, MASK_VECTOR},
   {"zve32f",   _options::x_target_flags, MASK_VECTOR},
   {"zve64x",   _options::x_target_flags, MASK_VECTOR},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 15bb5e76854..1e153b3a6e7 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -145,6 +145,14 @@ enum stack_protector_guard {
 #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
 #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
 
+#define MASK_ZICBOZ   (1 << 0)
+#define MASK_ZICBOM   (1 << 1)
+#define MASK_ZICBOP   (1 << 2)
+
+#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
+#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
+#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
+
 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
popcount to caclulate the minimal VLEN.  */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 492aad12324..d1b3c1840a6 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -209,6 +209,9 @@ int riscv_vector_elen_flags
 TargetVariable
 int riscv_zvl_flags
 
+TargetVariable
+int riscv_zicmo_subext
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
-- 
2.17.1

[PATCH V4 0/3] RISC-V:Add mininal support for Zicbo[mzp]

[shiyulong]

From: yulong 

This patchset adds support for three recently ratified RISC-V extensions:

-   Zicbom (Cache-Block Management Instructions)
-   Zicbop (Cache-Block Prefetch hint instructions)
-   Zicboz (Cache-Block Zero Instructions)

Patch 1: Add Zicbom/z/p mininal support
Patch 2: Add Zicbom/z/p instructions arch support
Patch 3: Add Zicbom/z/p instructions testcases

diff with the previous version:
We use unspec_volatile instead of unspec for those cache operations, and move 
those UNSPEC from unspec to unspecv.
 19
 20 cf. 
;

yulong (3):
  RISC-V: Add mininal support for Zicbo[mzp]
  RISC-V:Cache Management Operation instructions
  RISC-V:Cache Management Operation instructions testcases

 gcc/common/config/riscv/riscv-common.cc   |  8 +++
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv-builtins.cc| 16 ++
 gcc/config/riscv/riscv-cmo.def| 17 +++
 gcc/config/riscv/riscv-ftypes.def |  4 ++
 gcc/config/riscv/riscv-opts.h |  8 +++
 gcc/config/riscv/riscv.md | 51 +++
 gcc/config/riscv/riscv.opt|  3 ++
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 +
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 +
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c |  9 
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c |  9 
 14 files changed, 217 insertions(+)
 create mode 100644 gcc/config/riscv/riscv-cmo.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c

-- 
2.17.1

[PATCH V3 3/3] RISC-V:Cache Management Operation instructions testcases

[shiyulong]

From: yulong 

This commit adds testcases about CMO instructions.
diff with the previous two versions:
We change the names of builtin about cbo.clean, cbo.flush, cbo.inval, cbo.zero 
and prefetch.i instructions in the testcases.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/cmo-zicbom-1.c: New test.
* gcc.target/riscv/cmo-zicbom-2.c: New test.
* gcc.target/riscv/cmo-zicbop-1.c: New test.
* gcc.target/riscv/cmo-zicbop-2.c: New test.
* gcc.target/riscv/cmo-zicboz-1.c: New test.
* gcc.target/riscv/cmo-zicboz-2.c: New test.

---
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 +
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 +
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 +++
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 +++
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c |  9 
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c |  9 
 6 files changed, 106 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c

diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
new file mode 100644
index 000..e2ba2183511
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicbom -mabi=lp64" } */
+
+int foo1()
+{
+return __builtin_riscv_zicbom_cbo_clean();
+}
+
+int foo2()
+{
+return __builtin_riscv_zicbom_cbo_flush();
+}
+
+int foo3()
+{
+return __builtin_riscv_zicbom_cbo_inval();
+}
+
+/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
new file mode 100644
index 000..a605e8b1bdc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zicbom -mabi=ilp32" } */
+
+int foo1()
+{
+return __builtin_riscv_zicbom_cbo_clean();
+}
+
+int foo2()
+{
+return __builtin_riscv_zicbom_cbo_flush();
+}
+
+int foo3()
+{
+return __builtin_riscv_zicbom_cbo_inval();
+}
+
+/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */
+/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
new file mode 100644
index 000..c5d78c1763d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile target { { rv64-*-*}}} */
+/* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */
+
+void foo (char *p)
+{
+  __builtin_prefetch (p, 0, 0);
+  __builtin_prefetch (p, 0, 1);
+  __builtin_prefetch (p, 0, 2);
+  __builtin_prefetch (p, 0, 3);
+  __builtin_prefetch (p, 1, 0);
+  __builtin_prefetch (p, 1, 1);
+  __builtin_prefetch (p, 1, 2);
+  __builtin_prefetch (p, 1, 3);
+}
+
+int foo1()
+{
+  return __builtin_riscv_zicbop_cbo_prefetchi(1);
+}
+
+/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
+/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
new file mode 100644
index 000..6576365b39c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile target { { rv32-*-*}}} */
+/* { dg-options "-march=rv32gc_zicbop -mabi=ilp32" } */
+
+void foo (char *p)
+{
+  __builtin_prefetch (p, 0, 0);
+  __builtin_prefetch (p, 0, 1);
+  __builtin_prefetch (p, 0, 2);
+  __builtin_prefetch (p, 0, 3);
+  __builtin_prefetch (p, 1, 0);
+  __builtin_prefetch (p, 1, 1);
+  __builtin_prefetch (p, 1, 2);
+  __builtin_prefetch (p, 1, 3);
+}
+
+int foo1()
+{
+  return __builtin_riscv_zicbop_cbo_prefetchi(1);
+}
+
+/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
+/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ 
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
new file mode 100644
index 000..96c1674ef2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicboz -mabi=lp64" } */
+
+int foo1()
+{
+return 

[PATCH V3 2/3] RISC-V:Cache Management Operation instructions

[shiyulong]

From: yulong 

This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r 
and prefetch.w instructions.
diff with the previous two versions:
1.We change the instruction format from "prefetch.i\t%0" to "prefetch.i\t%a0" 
about the prefetch.i, cbo.clean, cbo.flush, cbo.inval, cbo.zero modes in 
riscv.md.
2.We change the the names of builtin about cbo.clean, cbo.flush, cbo.inval, 
cbo.zero and prefetch.i instructions in the riscv-cmo.def.

gcc/ChangeLog:
* config/riscv/predicates.md (imm5_operand): Add a new operand type for 
prefetch instructions.
* config/riscv/riscv-builtins.cc (AVAIL): Add new AVAILs for CMO ISA 
Extensions.
(RISCV_ATYPE_SI): New.
(RISCV_ATYPE_DI): New.
* config/riscv/riscv-ftypes.def (0): New.
(1): New.
* config/riscv/riscv.md (riscv_clean_): New.
(riscv_flush_): New.
(riscv_inval_): New.
(riscv_zero_): New.
(prefetch): New.
(riscv_prefetchi_): New.
* config/riscv/riscv-cmo.def: New file.

---
 gcc/config/riscv/predicates.md |  4 +++
 gcc/config/riscv/riscv-builtins.cc | 16 +
 gcc/config/riscv/riscv-cmo.def | 17 ++
 gcc/config/riscv/riscv-ftypes.def  |  4 +++
 gcc/config/riscv/riscv.md  | 52 ++
 5 files changed, 93 insertions(+)
 create mode 100644 gcc/config/riscv/riscv-cmo.def

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 97cdbdf053b..3fb4d95ab08 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -239,3 +239,7 @@
 (define_predicate "const63_operand"
   (and (match_code "const_int")
(match_test "INTVAL (op) == 63")))
+
+(define_predicate "imm5_operand"
+  (and (match_code "const_int")
+   (match_test "INTVAL (op) < 5")))
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 0658f8d3047..795132a0c16 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -87,6 +87,18 @@ struct riscv_builtin_description {
 
 AVAIL (hard_float, TARGET_HARD_FLOAT)
 
+
+AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (clean64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (flush32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (flush64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT)
+AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT)
+AVAIL (zero32,  TARGET_ZICBOZ && !TARGET_64BIT)
+AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
+AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
+AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+
 /* Construct a riscv_builtin_description from the given arguments.
 
INSN is the name of the associated instruction pattern, without the
@@ -119,6 +131,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
+#define RISCV_ATYPE_SI intSI_type_node
+#define RISCV_ATYPE_DI intDI_type_node
 
 /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs.  */
@@ -128,6 +142,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
 
 static const struct riscv_builtin_description riscv_builtins[] = {
+  #include "riscv-cmo.def"
+
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
 };
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
new file mode 100644
index 000..01cbf6ad64f
--- /dev/null
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -0,0 +1,17 @@
+// zicbom
+RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, clean32),
+RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, clean64),
+
+RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, flush32),
+RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, flush64),
+
+RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, inval32),
+RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, inval64),
+
+// zicboz
+RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE, zero32),
+RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE, zero64),
+
+// zicbop
+RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, prefetchi32),
+RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI, prefetchi64),
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 2214c496f9b..62421292ce7 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -28,3 +28,7 @@ along with GCC; see the file COPYING3.  If 

[PATCH V3 1/3] RISC-V: Add mininal support for Zicbo[mzp]

[shiyulong]

From: yulong 

This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop 
extensions.
* config/riscv/riscv-opts.h (MASK_ZICBOZ): New.
(MASK_ZICBOM): New.
(MASK_ZICBOP): New.
(TARGET_ZICBOZ): New.
(TARGET_ZICBOM): New.
(TARGET_ZICBOP): New.
* config/riscv/riscv.opt: New.

---
 gcc/common/config/riscv/riscv-common.cc | 8 
 gcc/config/riscv/riscv-opts.h   | 8 
 gcc/config/riscv/riscv.opt  | 3 +++
 3 files changed, 19 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 1501242e296..bf7a7caabef 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -165,6 +165,10 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zksh",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zk",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zkn",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zks",   ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1110,6 +1114,10 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zksh",   _options::x_riscv_zk_subext, MASK_ZKSH},
   {"zkt",_options::x_riscv_zk_subext, MASK_ZKT},
 
+  {"zicboz", _options::x_riscv_zicmo_subext, MASK_ZICBOZ},
+  {"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
+  {"zicbop", _options::x_riscv_zicmo_subext, MASK_ZICBOP},
+
   {"zve32x",   _options::x_target_flags, MASK_VECTOR},
   {"zve32f",   _options::x_target_flags, MASK_VECTOR},
   {"zve64x",   _options::x_target_flags, MASK_VECTOR},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 15bb5e76854..1e153b3a6e7 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -145,6 +145,14 @@ enum stack_protector_guard {
 #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
 #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
 
+#define MASK_ZICBOZ   (1 << 0)
+#define MASK_ZICBOM   (1 << 1)
+#define MASK_ZICBOP   (1 << 2)
+
+#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
+#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
+#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
+
 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
popcount to caclulate the minimal VLEN.  */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 492aad12324..d1b3c1840a6 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -209,6 +209,9 @@ int riscv_vector_elen_flags
 TargetVariable
 int riscv_zvl_flags
 
+TargetVariable
+int riscv_zicmo_subext
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
-- 
2.17.1

[PATCH V3 0/3] RISC-V:Add mininal support for Zicbo[mzp]

[shiyulong]

From: yulong 

This patchset adds support for three recently ratified RISC-V extensions:

-   Zicbom (Cache-Block Management Instructions)
-   Zicbom (Cache-Block Management Instructions)
-   Zicboz (Cache-Block Zero Instructions)

Patch 1: Add Zicbom/z/p mininal support
Patch 2: Add Zicbom/z/p instructions arch support
Patch 3: Add Zicbom/z/p instructions testcases

diff with the previous two versions:
1.The naming of builtin caused oddities, so we have changed the names of 
builtin.
2.According to spec, we have changed the format of the prefetch.i instruction.

cf. 
;

yulong (3):
  RISC-V: Add mininal support for Zicbo[mzp]
  RISC-V:Cache Management Operation instructions
  RISC-V:Cache Management Operation instructions testcases

 gcc/common/config/riscv/riscv-common.cc   |  8 +++
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv-builtins.cc| 16 ++
 gcc/config/riscv/riscv-cmo.def| 17 ++
 gcc/config/riscv/riscv-ftypes.def |  4 ++
 gcc/config/riscv/riscv-opts.h |  8 +++
 gcc/config/riscv/riscv.md | 52 +++
 gcc/config/riscv/riscv.opt|  3 ++
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 
 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c |  9 
 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c |  9 
 14 files changed, 218 insertions(+)
 create mode 100644 gcc/config/riscv/riscv-cmo.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c

-- 
2.17.1