Re: [PATCH, i386] Add native support for VIA C7, Eden and Nano CPUs

2016-06-06 Thread J. Mayer 
On Mon, 2016-06-06 at 17:27 +, Joseph Myers wrote:
> This patch is missing the invoke.texi changes to document all the new
> CPU 
> names.

Hi,
correct, please consider adding the following patch to fix this.
Regards.

---

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ce162a0..ac7f8a8 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -23261,6 +23261,54 @@ VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE
instruction set support.
 (No scheduling is
 implemented for this chip.)
 
+@item c7
+VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3 instruction set
support.
+(No scheduling is implemented for this chip.)
+
+@item samuel-2
+VIA Eden Samuel 2 CPU with MMX and 3DNow!@: instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nehemiah
+VIA Eden Nehemiah CPU with MMX and SSE instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item esther
+VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3 instruction set
support.
+(No scheduling is implemented for this chip.)
+
+@item eden-x2
+VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3 instruction set
support.
+(No scheduling is implemented for this chip.)
+
+@item eden-x4
+VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
SSE4.2, AVX and AVX2 instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano
+Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano-1000
+VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano-2000
+VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano-3000
+VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1
instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano-x2
+VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and
SSE4.1 instruction set support.
+(No scheduling is implemented for this chip.)
+
+@item nano-x4
+VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and
SSE4.1 instruction set support.
+(No scheduling is implemented for this chip.)
+
 @item geode
 AMD Geode embedded processor with MMX and 3DNow!@: instruction set
support.
 @end table

Re: [PATCH, i386] Add native support for VIA C7, Eden and Nano CPUs

2016-06-06 Thread Joseph Myers 
This patch is missing the invoke.texi changes to document all the new CPU 
names.

-- 
Joseph S. Myers
jos...@codesourcery.com

[PATCH, i386] Add native support for VIA C7, Eden and Nano CPUs

2016-06-01 Thread J. Mayer 
The following patch adds support and native detection for C7, Eden
"Samuel2", Eden "Nehemiah", Eden "Esther", Eden x2, Eden x4, Nano 1xxx,
Nano 2xxx, Nano 3xxx, Nano x2 and Nano x4 VIA CPUs.

Please CC me to any comment / review / change request.

---

diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-
i386.c
index a9d5135..d2c4c4c 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -651,7 +651,9 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
  break;
 
case 6:
- if (model > 9 || has_longmode)
+ if (has_longmode)
+   processor = PROCESSOR_K8;
+ else if (model > 9)
/* Use the default detection procedure.  */
;
  else if (model == 9)
@@ -869,9 +871,30 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
cpu = "athlon";
   break;
 case PROCESSOR_K8:
-  if (arch && has_sse3)
-   cpu = "k8-sse3";
+  if (arch)
+   {
+ if (vendor == signature_CENTAUR_ebx)
+   {
+ if (has_sse4_1)
+   /* Nano 3000 | Nano dual / quad core | Eden X4 */
+   cpu = "nano-3000";
+ else if (has_ssse3)
+   /* Nano 1000 | Nano 2000 */
+   cpu = "nano";
+ else if (has_sse3)
+   /* Eden X2 */
+   cpu = "eden-x2";
+ else
+   /* Default to k8 */
+   cpu = "k8";
+   }
+ else if (has_sse3)
+   cpu = "k8-sse3";
+ else
+   cpu = "k8";
+   }
   else
+   /* For -mtune, we default to -mtune=k8 */
cpu = "k8";
   break;
 case PROCESSOR_AMDFAM10:
@@ -903,7 +926,22 @@ const char *host_detect_local_cpu (int argc, const
char **argv)
   /* Use something reasonable.  */
   if (arch)
{
- if (has_ssse3)
+ if (vendor == signature_CENTAUR_ebx)
+   {
+ if (has_sse3) {
+   /* C7 / Eden "Esther" */
+   cpu = "c7";
+ } else if (has_sse) {
+   /* Eden "Nehemiah" */
+   cpu = "nehemiah";
+ } else if (has_3dnow) {
+   /* Eden "Samuel2" */
+   cpu = "samuel-2";
+ } else {
+   /* We have no idea: default to generic i386 */
+ }
+   }
+ else if (has_ssse3)
cpu = "core2";
  else if (has_sse3)
{
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 7e9f511..c9bd25e 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -4783,8 +4783,15 @@ ix86_option_override_internal (bool main_args_p,
   {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
   {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
   {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
+  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
PTA_PRFCHW},
   {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+   PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
   {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
   {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
   {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX |
PTA_FXSR},
@@ -4915,6 +4922,30 @@ ix86_option_override_internal (bool main_args_p,
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+  {"eden-x2", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_FXSR},
+  {"eden-x4", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-1000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-2000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_FXSR},
+  {"nano-3000", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x2", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x4", PROCESSOR_K8, CPU_K8,
+   PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},