Re: [PATCH][AArch64] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16
Dennis Zhang writes: > Hi Richard, > > On 06/12/2019 10:22, Richard Sandiford wrote: >> Dennis Zhang writes: >>> 2019-12-04 Dennis Zhang >>> >>> * config/aarch64/aarch64-arches.def (armv8.6-a): New. >>> * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define >>> __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC and >>> __ARM_FEATURE_BF16_SCALAR_ARITHMETIC when enabled. >>> * config/aarch64/aarch64-option-extensions.def (i8mm, bf16): New. >>> (fp): Disabling fp also disables i8mm and bf16. >>> (simd): Disabling simd also disables i8mm. >>> * config/aarch64/aarch64.h (AARCH64_FL_V8_6): New macro. >>> (AARCH64_FL_I8MM, AARCH64_FL_BF16, AARCH64_FL_FOR_ARCH8_6): Likewise. >>> (AARCH64_ISA_V8_6, AARCH64_ISA_I8MM, AARCH64_ISA_BF16): Likewise. >>> (TARGET_I8MM, TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise. >>> * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options. Add >>> a new table to list permissible values for ARCH. >>> >>> gcc/testsuite/ChangeLog: >>> >>> 2019-12-04 Dennis Zhang >>> >>> * gcc.target/aarch64/pragma_cpp_predefs_2.c: Add tests for i8mm >>> and bf16 features. >> >> Thanks for the update, looks great. A couple of comments below. >> >>> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi >>> index d165f31a865..1192e8f4b06 100644 >>> --- a/gcc/doc/invoke.texi >>> +++ b/gcc/doc/invoke.texi >>> @@ -16050,25 +16050,22 @@ Specify the name of the target architecture and, >>> optionally, one or >>> more feature modifiers. This option has the form >>> @option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}. >>> >>> -The permissible values for @var{arch} are @samp{armv8-a}, >>> -@samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a}, @samp{armv8.4-a}, >>> -@samp{armv8.5-a} or @var{native}. >>> - >>> -The value @samp{armv8.5-a} implies @samp{armv8.4-a} and enables compiler >>> -support for the ARMv8.5-A architecture extensions. >>> - >>> -The value @samp{armv8.4-a} implies @samp{armv8.3-a} and enables compiler >>> -support for the ARMv8.4-A architecture extensions. >>> - >>> -The value @samp{armv8.3-a} implies @samp{armv8.2-a} and enables compiler >>> -support for the ARMv8.3-A architecture extensions. >>> - >>> -The value @samp{armv8.2-a} implies @samp{armv8.1-a} and enables compiler >>> -support for the ARMv8.2-A architecture extensions. >>> - >>> -The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler >>> -support for the ARMv8.1-A architecture extension. In particular, it >>> -enables the @samp{+crc}, @samp{+lse}, and @samp{+rdma} features. >>> +The table below summarizes the permissible values for @var{arch} >>> +and the features that they enable by default: >>> + >>> +@multitable @columnfractions 0.20 0.20 0.60 >>> +@headitem @var{arch} value @tab Architecture @tab Includes by default >> >> We should have an armv8-a entry here, something like: >> >> @item @samp{armv8-a} @tab Armv8-A @tab @samp{+fp}, @samp{+simd} >> > > The armv8-a entry is added. > >>> +@item @samp{armv8.1-a} @tab Armv8.1-A >>> +@tab @samp{armv8-a}, @samp{+crc}, @samp{+lse}, @samp{+rdma} >>> +@item @samp{armv8.2-a} @tab Armv8.2-A @tab @samp{armv8.1-a} >>> +@item @samp{armv8.3-a} @tab Armv8.3-A @tab @samp{armv8.2-a} >>> +@item @samp{armv8.4-a} @tab Armv8.4-A >>> +@tab @samp{armv8.3-a}, @samp{+fp16fml}, @samp{+dotprod} >>> +@item @samp{armv8.5-a} @tab Armv8.5-A >>> +@tab @samp{armv8.4-a}, @samp{+sb}, @samp{+ssbs}, @samp{+predres} >>> +@item @samp{armv8.6-a} @tab Armv8.6-A >>> +@tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm} >>> +@end multitable >> >> I should have tried a proof of concept of this before suggesting it, sorry. >> Trying the patch locally I get: >> >> gcc.pod around line 18643: You can't have =items (as at line 18649) unless >> the first thing after the =over is an =item >> POD document had syntax errors at /usr/bin/pod2man line 71. >> Makefile:3363: recipe for target 'doc/gcc.1' failed >> make: [doc/gcc.1] Error 1 (ignored) >> >> (Odd that this is an ignored error, since we end up with an empty man page.) >> >> I've posted a texi2pod.pl patch for that: >> >> https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00407.html >> >> However, even with that patch, the script needs the full table row to be >> on a single line, so I think we need to do that and live with the long lines. >> > > The items are kept in a single line for each. > >>> [...] >>> diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c >>> b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c >>> index 608b89d19ce..5ae39bc6cf0 100644 >>> --- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c >>> +++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c >>> @@ -13,6 +13,92 @@ >>> #error "__ARM_FEATURE_TME is defined but should not be!" >>> #endif >>> >>> +/* Test Armv8.6-a features. */ >>> + >>> +#pragma GCC push_options >>> +#pragma GCC target ("arch=armv8-a") >> >> Thes
Re: [PATCH][AArch64] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16
Hi Richard, On 06/12/2019 10:22, Richard Sandiford wrote: > Dennis Zhang writes: >> 2019-12-04 Dennis Zhang >> >> * config/aarch64/aarch64-arches.def (armv8.6-a): New. >> * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define >> __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC and >> __ARM_FEATURE_BF16_SCALAR_ARITHMETIC when enabled. >> * config/aarch64/aarch64-option-extensions.def (i8mm, bf16): New. >> (fp): Disabling fp also disables i8mm and bf16. >> (simd): Disabling simd also disables i8mm. >> * config/aarch64/aarch64.h (AARCH64_FL_V8_6): New macro. >> (AARCH64_FL_I8MM, AARCH64_FL_BF16, AARCH64_FL_FOR_ARCH8_6): Likewise. >> (AARCH64_ISA_V8_6, AARCH64_ISA_I8MM, AARCH64_ISA_BF16): Likewise. >> (TARGET_I8MM, TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise. >> * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options. Add >> a new table to list permissible values for ARCH. >> >> gcc/testsuite/ChangeLog: >> >> 2019-12-04 Dennis Zhang >> >> * gcc.target/aarch64/pragma_cpp_predefs_2.c: Add tests for i8mm >> and bf16 features. > > Thanks for the update, looks great. A couple of comments below. > >> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi >> index d165f31a865..1192e8f4b06 100644 >> --- a/gcc/doc/invoke.texi >> +++ b/gcc/doc/invoke.texi >> @@ -16050,25 +16050,22 @@ Specify the name of the target architecture and, >> optionally, one or >> more feature modifiers. This option has the form >> @option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}. >> >> -The permissible values for @var{arch} are @samp{armv8-a}, >> -@samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a}, @samp{armv8.4-a}, >> -@samp{armv8.5-a} or @var{native}. >> - >> -The value @samp{armv8.5-a} implies @samp{armv8.4-a} and enables compiler >> -support for the ARMv8.5-A architecture extensions. >> - >> -The value @samp{armv8.4-a} implies @samp{armv8.3-a} and enables compiler >> -support for the ARMv8.4-A architecture extensions. >> - >> -The value @samp{armv8.3-a} implies @samp{armv8.2-a} and enables compiler >> -support for the ARMv8.3-A architecture extensions. >> - >> -The value @samp{armv8.2-a} implies @samp{armv8.1-a} and enables compiler >> -support for the ARMv8.2-A architecture extensions. >> - >> -The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler >> -support for the ARMv8.1-A architecture extension. In particular, it >> -enables the @samp{+crc}, @samp{+lse}, and @samp{+rdma} features. >> +The table below summarizes the permissible values for @var{arch} >> +and the features that they enable by default: >> + >> +@multitable @columnfractions 0.20 0.20 0.60 >> +@headitem @var{arch} value @tab Architecture @tab Includes by default > > We should have an armv8-a entry here, something like: > > @item @samp{armv8-a} @tab Armv8-A @tab @samp{+fp}, @samp{+simd} > The armv8-a entry is added. >> +@item @samp{armv8.1-a} @tab Armv8.1-A >> +@tab @samp{armv8-a}, @samp{+crc}, @samp{+lse}, @samp{+rdma} >> +@item @samp{armv8.2-a} @tab Armv8.2-A @tab @samp{armv8.1-a} >> +@item @samp{armv8.3-a} @tab Armv8.3-A @tab @samp{armv8.2-a} >> +@item @samp{armv8.4-a} @tab Armv8.4-A >> +@tab @samp{armv8.3-a}, @samp{+fp16fml}, @samp{+dotprod} >> +@item @samp{armv8.5-a} @tab Armv8.5-A >> +@tab @samp{armv8.4-a}, @samp{+sb}, @samp{+ssbs}, @samp{+predres} >> +@item @samp{armv8.6-a} @tab Armv8.6-A >> +@tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm} >> +@end multitable > > I should have tried a proof of concept of this before suggesting it, sorry. > Trying the patch locally I get: > > gcc.pod around line 18643: You can't have =items (as at line 18649) unless > the first thing after the =over is an =item > POD document had syntax errors at /usr/bin/pod2man line 71. > Makefile:3363: recipe for target 'doc/gcc.1' failed > make: [doc/gcc.1] Error 1 (ignored) > > (Odd that this is an ignored error, since we end up with an empty man page.) > > I've posted a texi2pod.pl patch for that: > > https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00407.html > > However, even with that patch, the script needs the full table row to be > on a single line, so I think we need to do that and live with the long lines. > The items are kept in a single line for each. >> [...] >> diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c >> b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c >> index 608b89d19ce..5ae39bc6cf0 100644 >> --- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c >> +++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c >> @@ -13,6 +13,92 @@ >> #error "__ARM_FEATURE_TME is defined but should not be!" >> #endif >> >> +/* Test Armv8.6-a features. */ >> + >> +#pragma GCC push_options >> +#pragma GCC target ("arch=armv8-a") > > These two pragmas should be at the beginning of the file, so that we > start with base armv8-a for all the tests. The pragmas are mov
Re: [PATCH][AArch64] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16
Dennis Zhang writes: > 2019-12-04 Dennis Zhang > > * config/aarch64/aarch64-arches.def (armv8.6-a): New. > * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define > __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC and > __ARM_FEATURE_BF16_SCALAR_ARITHMETIC when enabled. > * config/aarch64/aarch64-option-extensions.def (i8mm, bf16): New. > (fp): Disabling fp also disables i8mm and bf16. > (simd): Disabling simd also disables i8mm. > * config/aarch64/aarch64.h (AARCH64_FL_V8_6): New macro. > (AARCH64_FL_I8MM, AARCH64_FL_BF16, AARCH64_FL_FOR_ARCH8_6): Likewise. > (AARCH64_ISA_V8_6, AARCH64_ISA_I8MM, AARCH64_ISA_BF16): Likewise. > (TARGET_I8MM, TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise. > * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options. Add > a new table to list permissible values for ARCH. > > gcc/testsuite/ChangeLog: > > 2019-12-04 Dennis Zhang > > * gcc.target/aarch64/pragma_cpp_predefs_2.c: Add tests for i8mm > and bf16 features. Thanks for the update, looks great. A couple of comments below. > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index d165f31a865..1192e8f4b06 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -16050,25 +16050,22 @@ Specify the name of the target architecture and, > optionally, one or > more feature modifiers. This option has the form > @option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}. > > -The permissible values for @var{arch} are @samp{armv8-a}, > -@samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a}, @samp{armv8.4-a}, > -@samp{armv8.5-a} or @var{native}. > - > -The value @samp{armv8.5-a} implies @samp{armv8.4-a} and enables compiler > -support for the ARMv8.5-A architecture extensions. > - > -The value @samp{armv8.4-a} implies @samp{armv8.3-a} and enables compiler > -support for the ARMv8.4-A architecture extensions. > - > -The value @samp{armv8.3-a} implies @samp{armv8.2-a} and enables compiler > -support for the ARMv8.3-A architecture extensions. > - > -The value @samp{armv8.2-a} implies @samp{armv8.1-a} and enables compiler > -support for the ARMv8.2-A architecture extensions. > - > -The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler > -support for the ARMv8.1-A architecture extension. In particular, it > -enables the @samp{+crc}, @samp{+lse}, and @samp{+rdma} features. > +The table below summarizes the permissible values for @var{arch} > +and the features that they enable by default: > + > +@multitable @columnfractions 0.20 0.20 0.60 > +@headitem @var{arch} value @tab Architecture @tab Includes by default We should have an armv8-a entry here, something like: @item @samp{armv8-a} @tab Armv8-A @tab @samp{+fp}, @samp{+simd} > +@item @samp{armv8.1-a} @tab Armv8.1-A > +@tab @samp{armv8-a}, @samp{+crc}, @samp{+lse}, @samp{+rdma} > +@item @samp{armv8.2-a} @tab Armv8.2-A @tab @samp{armv8.1-a} > +@item @samp{armv8.3-a} @tab Armv8.3-A @tab @samp{armv8.2-a} > +@item @samp{armv8.4-a} @tab Armv8.4-A > +@tab @samp{armv8.3-a}, @samp{+fp16fml}, @samp{+dotprod} > +@item @samp{armv8.5-a} @tab Armv8.5-A > +@tab @samp{armv8.4-a}, @samp{+sb}, @samp{+ssbs}, @samp{+predres} > +@item @samp{armv8.6-a} @tab Armv8.6-A > +@tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm} > +@end multitable I should have tried a proof of concept of this before suggesting it, sorry. Trying the patch locally I get: gcc.pod around line 18643: You can't have =items (as at line 18649) unless the first thing after the =over is an =item POD document had syntax errors at /usr/bin/pod2man line 71. Makefile:3363: recipe for target 'doc/gcc.1' failed make: [doc/gcc.1] Error 1 (ignored) (Odd that this is an ignored error, since we end up with an empty man page.) I've posted a texi2pod.pl patch for that: https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00407.html However, even with that patch, the script needs the full table row to be on a single line, so I think we need to do that and live with the long lines. > [...] > diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c > b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c > index 608b89d19ce..5ae39bc6cf0 100644 > --- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c > +++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c > @@ -13,6 +13,92 @@ > #error "__ARM_FEATURE_TME is defined but should not be!" > #endif > > +/* Test Armv8.6-a features. */ > + > +#pragma GCC push_options > +#pragma GCC target ("arch=armv8-a") These two pragmas should be at the beginning of the file, so that we start with base armv8-a for all the tests. Thanks, Richard
Re: [PATCH][AArch64] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16
Hi Richard, On 29/11/2019 13:00, Richard Sandiford wrote: > Hi Dennis, > > Sorry for the slow response. > > Dennis Zhang writes: >> Hi all, >> >> This patch is part of a series adding support for Armv8.6-A features. >> It enables options including -march=armv8.6-a, +i8mm and +bf16. >> The +i8mm and +bf16 features are mandatory for Armv8.6-a and optional >> for Armv8.2-a and onward. >> Documents are at https://developer.arm.com/docs/ddi0596/latest >> >> Regtested for aarch64-none-linux-gnu. >> >> Please help to check if it's ready for trunk. >> >> Many thanks! >> Dennis >> >> gcc/ChangeLog: >> >> 2019-11-26 Dennis Zhang >> >> * config/aarch64/aarch64-arches.def (armv8.6-a): New. >> * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define >> __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC and >> __ARM_FEATURE_BF16_SCALAR_ARITHMETIC when enabled. >> * config/aarch64/aarch64-option-extensions.def (i8mm, bf16): New. >> * config/aarch64/aarch64.h (AARCH64_FL_V8_6): New macro. >> (AARCH64_FL_I8MM, AARCH64_FL_BF16, AARCH64_FL_FOR_ARCH8_6): Likewise. >> (AARCH64_ISA_V8_6, AARCH64_ISA_I8MM, AARCH64_ISA_BF16): Likewise. >> (TARGET_I8MM, TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise. >> * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options. >> >> gcc/testsuite/ChangeLog: >> >> 2019-11-26 Dennis Zhang >> >> * gcc.target/aarch64/pragma_cpp_predefs_2.c: Add tests for i8mm >> and bf16 features. >> >> diff --git a/gcc/config/aarch64/aarch64-arches.def >> b/gcc/config/aarch64/aarch64-arches.def >> index d258bd49244..e464d329c1a 100644 >> --- a/gcc/config/aarch64/aarch64-arches.def >> +++ b/gcc/config/aarch64/aarch64-arches.def >> @@ -36,5 +36,6 @@ AARCH64_ARCH("armv8.2-a", generic, 8_2A, >> 8, AARCH64_FL_FOR_ARCH8_2) >> AARCH64_ARCH("armv8.3-a", generic, 8_3A, 8, >> AARCH64_FL_FOR_ARCH8_3) >> AARCH64_ARCH("armv8.4-a", generic, 8_4A, 8, >> AARCH64_FL_FOR_ARCH8_4) >> AARCH64_ARCH("armv8.5-a", generic, 8_5A, 8, >> AARCH64_FL_FOR_ARCH8_5) >> +AARCH64_ARCH("armv8.6-a", generic, 8_6A, 8, >> AARCH64_FL_FOR_ARCH8_6) >> >> #undef AARCH64_ARCH >> diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c >> index f3da07fd28a..20d1e00552b 100644 >> --- a/gcc/config/aarch64/aarch64-c.c >> +++ b/gcc/config/aarch64/aarch64-c.c >> @@ -165,6 +165,12 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) >> aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile); >> aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", >> pfile); >> >> + aarch64_def_or_undef (TARGET_I8MM, "__ARM_FEATURE_MATMUL_INT8", pfile); >> + aarch64_def_or_undef (TARGET_BF16_SIMD, >> +"__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile); >> + aarch64_def_or_undef (TARGET_BF16_FP, >> +"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile); >> + >> /* Not for ACLE, but required to keep "float.h" correct if we switch >>target between implementations that do or do not support ARMv8.2-A >>16-bit floating-point extensions. */ >> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def >> b/gcc/config/aarch64/aarch64-option-extensions.def >> index d3ae1b2431b..5b7c3b8a213 100644 >> --- a/gcc/config/aarch64/aarch64-option-extensions.def >> +++ b/gcc/config/aarch64/aarch64-option-extensions.def >> @@ -198,4 +198,14 @@ AARCH64_OPT_EXTENSION("sve2-bitperm", >> AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD | >> /* Enabling or disabling "tme" only changes "tme". */ >> AARCH64_OPT_EXTENSION("tme", AARCH64_FL_TME, 0, 0, false, "") >> >> +/* Enabling "i8mm" also enables "simd". >> + Disabling "i8mm" only disables "i8mm". */ >> +AARCH64_OPT_EXTENSION("i8mm", AARCH64_FL_I8MM, AARCH64_FL_SIMD, \ >> + 0, false, "i8mm") > > We have to maintain the transitive closure of features by hand, > so anything that enables AARCH64_FL_SIMD also needs to enable > AARCH64_FL_FP. > > We should also add i8mm to the list of things that +nosimd and +nofp > disable. > > (It would be better to do this automatically, but that's future work.) > >> +/* Enabling "bf16" also enables "simd" and "fp". >> + Disabling "bf16" only disables "bf16". */ >> +AARCH64_OPT_EXTENSION("bf16", AARCH64_FL_BF16, AARCH64_FL_SIMD | >> AARCH64_FL_FP, >> + 0, false, "bf16") > > Similarly here we should add bf16 to the list of things that +nofp disables. > >> @@ -308,6 +323,13 @@ extern unsigned aarch64_architecture_version; >> /* Memory Tagging instructions optional to Armv8.5 enabled through >> +memtag. */ >> #define TARGET_MEMTAG (AARCH64_ISA_V8_5 && AARCH64_ISA_MEMTAG) >> >> +/* I8MM instructions are enabled through +i8mm. */ >> +#define TARGET_I8MM (TARGET_SIMD && AARCH64_ISA_I8MM) > > This should then just be AARCH64_ISA_I8MM (i.e. no need to test > TARG
Re: [PATCH][AArch64] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16
Hi Dennis, Sorry for the slow response. Dennis Zhang writes: > Hi all, > > This patch is part of a series adding support for Armv8.6-A features. > It enables options including -march=armv8.6-a, +i8mm and +bf16. > The +i8mm and +bf16 features are mandatory for Armv8.6-a and optional > for Armv8.2-a and onward. > Documents are at https://developer.arm.com/docs/ddi0596/latest > > Regtested for aarch64-none-linux-gnu. > > Please help to check if it's ready for trunk. > > Many thanks! > Dennis > > gcc/ChangeLog: > > 2019-11-26 Dennis Zhang > > * config/aarch64/aarch64-arches.def (armv8.6-a): New. > * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define > __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC and > __ARM_FEATURE_BF16_SCALAR_ARITHMETIC when enabled. > * config/aarch64/aarch64-option-extensions.def (i8mm, bf16): New. > * config/aarch64/aarch64.h (AARCH64_FL_V8_6): New macro. > (AARCH64_FL_I8MM, AARCH64_FL_BF16, AARCH64_FL_FOR_ARCH8_6): Likewise. > (AARCH64_ISA_V8_6, AARCH64_ISA_I8MM, AARCH64_ISA_BF16): Likewise. > (TARGET_I8MM, TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise. > * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options. > > gcc/testsuite/ChangeLog: > > 2019-11-26 Dennis Zhang > > * gcc.target/aarch64/pragma_cpp_predefs_2.c: Add tests for i8mm > and bf16 features. > > diff --git a/gcc/config/aarch64/aarch64-arches.def > b/gcc/config/aarch64/aarch64-arches.def > index d258bd49244..e464d329c1a 100644 > --- a/gcc/config/aarch64/aarch64-arches.def > +++ b/gcc/config/aarch64/aarch64-arches.def > @@ -36,5 +36,6 @@ AARCH64_ARCH("armv8.2-a", generic, 8_2A, > 8, AARCH64_FL_FOR_ARCH8_2) > AARCH64_ARCH("armv8.3-a", generic,8_3A, 8, > AARCH64_FL_FOR_ARCH8_3) > AARCH64_ARCH("armv8.4-a", generic,8_4A, 8, > AARCH64_FL_FOR_ARCH8_4) > AARCH64_ARCH("armv8.5-a", generic,8_5A, 8, > AARCH64_FL_FOR_ARCH8_5) > +AARCH64_ARCH("armv8.6-a", generic,8_6A, 8, > AARCH64_FL_FOR_ARCH8_6) > > #undef AARCH64_ARCH > diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c > index f3da07fd28a..20d1e00552b 100644 > --- a/gcc/config/aarch64/aarch64-c.c > +++ b/gcc/config/aarch64/aarch64-c.c > @@ -165,6 +165,12 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) >aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile); >aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", > pfile); > > + aarch64_def_or_undef (TARGET_I8MM, "__ARM_FEATURE_MATMUL_INT8", pfile); > + aarch64_def_or_undef (TARGET_BF16_SIMD, > + "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile); > + aarch64_def_or_undef (TARGET_BF16_FP, > + "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile); > + >/* Not for ACLE, but required to keep "float.h" correct if we switch > target between implementations that do or do not support ARMv8.2-A > 16-bit floating-point extensions. */ > diff --git a/gcc/config/aarch64/aarch64-option-extensions.def > b/gcc/config/aarch64/aarch64-option-extensions.def > index d3ae1b2431b..5b7c3b8a213 100644 > --- a/gcc/config/aarch64/aarch64-option-extensions.def > +++ b/gcc/config/aarch64/aarch64-option-extensions.def > @@ -198,4 +198,14 @@ AARCH64_OPT_EXTENSION("sve2-bitperm", > AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD | > /* Enabling or disabling "tme" only changes "tme". */ > AARCH64_OPT_EXTENSION("tme", AARCH64_FL_TME, 0, 0, false, "") > > +/* Enabling "i8mm" also enables "simd". > + Disabling "i8mm" only disables "i8mm". */ > +AARCH64_OPT_EXTENSION("i8mm", AARCH64_FL_I8MM, AARCH64_FL_SIMD, \ > + 0, false, "i8mm") We have to maintain the transitive closure of features by hand, so anything that enables AARCH64_FL_SIMD also needs to enable AARCH64_FL_FP. We should also add i8mm to the list of things that +nosimd and +nofp disable. (It would be better to do this automatically, but that's future work.) > +/* Enabling "bf16" also enables "simd" and "fp". > + Disabling "bf16" only disables "bf16". */ > +AARCH64_OPT_EXTENSION("bf16", AARCH64_FL_BF16, AARCH64_FL_SIMD | > AARCH64_FL_FP, > + 0, false, "bf16") Similarly here we should add bf16 to the list of things that +nofp disables. > @@ -308,6 +323,13 @@ extern unsigned aarch64_architecture_version; > /* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. > */ > #define TARGET_MEMTAG (AARCH64_ISA_V8_5 && AARCH64_ISA_MEMTAG) > > +/* I8MM instructions are enabled through +i8mm. */ > +#define TARGET_I8MM (TARGET_SIMD && AARCH64_ISA_I8MM) This should then just be AARCH64_ISA_I8MM (i.e. no need to test TARGET_SIMD). > + > +/* BF16 instructions are enabled through +bf16. */ > +#define TARGET_BF16_FP (AARCH64_ISA_BF16 && TARGET_FLOAT) Similarly here we don't need a test for TARGET_FLOAT. > +#
[PATCH][AArch64] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16
Hi all, This patch is part of a series adding support for Armv8.6-A features. It enables options including -march=armv8.6-a, +i8mm and +bf16. The +i8mm and +bf16 features are mandatory for Armv8.6-a and optional for Armv8.2-a and onward. Documents are at https://developer.arm.com/docs/ddi0596/latest Regtested for aarch64-none-linux-gnu. Please help to check if it's ready for trunk. Many thanks! Dennis gcc/ChangeLog: 2019-11-26 Dennis Zhang * config/aarch64/aarch64-arches.def (armv8.6-a): New. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC and __ARM_FEATURE_BF16_SCALAR_ARITHMETIC when enabled. * config/aarch64/aarch64-option-extensions.def (i8mm, bf16): New. * config/aarch64/aarch64.h (AARCH64_FL_V8_6): New macro. (AARCH64_FL_I8MM, AARCH64_FL_BF16, AARCH64_FL_FOR_ARCH8_6): Likewise. (AARCH64_ISA_V8_6, AARCH64_ISA_I8MM, AARCH64_ISA_BF16): Likewise. (TARGET_I8MM, TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise. * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options. gcc/testsuite/ChangeLog: 2019-11-26 Dennis Zhang * gcc.target/aarch64/pragma_cpp_predefs_2.c: Add tests for i8mm and bf16 features. diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def index d258bd49244..e464d329c1a 100644 --- a/gcc/config/aarch64/aarch64-arches.def +++ b/gcc/config/aarch64/aarch64-arches.def @@ -36,5 +36,6 @@ AARCH64_ARCH("armv8.2-a", generic, 8_2A, 8, AARCH64_FL_FOR_ARCH8_2) AARCH64_ARCH("armv8.3-a", generic, 8_3A, 8, AARCH64_FL_FOR_ARCH8_3) AARCH64_ARCH("armv8.4-a", generic, 8_4A, 8, AARCH64_FL_FOR_ARCH8_4) AARCH64_ARCH("armv8.5-a", generic, 8_5A, 8, AARCH64_FL_FOR_ARCH8_5) +AARCH64_ARCH("armv8.6-a", generic, 8_6A, 8, AARCH64_FL_FOR_ARCH8_6) #undef AARCH64_ARCH diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c index f3da07fd28a..20d1e00552b 100644 --- a/gcc/config/aarch64/aarch64-c.c +++ b/gcc/config/aarch64/aarch64-c.c @@ -165,6 +165,12 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile); aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile); + aarch64_def_or_undef (TARGET_I8MM, "__ARM_FEATURE_MATMUL_INT8", pfile); + aarch64_def_or_undef (TARGET_BF16_SIMD, + "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile); + aarch64_def_or_undef (TARGET_BF16_FP, + "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile); + /* Not for ACLE, but required to keep "float.h" correct if we switch target between implementations that do or do not support ARMv8.2-A 16-bit floating-point extensions. */ diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index d3ae1b2431b..5b7c3b8a213 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -198,4 +198,14 @@ AARCH64_OPT_EXTENSION("sve2-bitperm", AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD | /* Enabling or disabling "tme" only changes "tme". */ AARCH64_OPT_EXTENSION("tme", AARCH64_FL_TME, 0, 0, false, "") +/* Enabling "i8mm" also enables "simd". + Disabling "i8mm" only disables "i8mm". */ +AARCH64_OPT_EXTENSION("i8mm", AARCH64_FL_I8MM, AARCH64_FL_SIMD, \ + 0, false, "i8mm") + +/* Enabling "bf16" also enables "simd" and "fp". + Disabling "bf16" only disables "bf16". */ +AARCH64_OPT_EXTENSION("bf16", AARCH64_FL_BF16, AARCH64_FL_SIMD | AARCH64_FL_FP, + 0, false, "bf16") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index ee01909abb9..7de99285e8a 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -202,6 +202,15 @@ extern unsigned aarch64_architecture_version; /* Transactional Memory Extension. */ #define AARCH64_FL_TME (1ULL << 33) /* Has TME instructions. */ +/* Armv8.6-A architecture extensions. */ +#define AARCH64_FL_V8_6 (1ULL << 34) + +/* 8-bit Integer Matrix Multiply (I8MM) extensions. */ +#define AARCH64_FL_I8MM (1ULL << 35) + +/* Brain half-precision floating-point (BFloat16) Extension. */ +#define AARCH64_FL_BF16 (1ULL << 36) + /* Has FP and SIMD. */ #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) @@ -223,6 +232,9 @@ extern unsigned aarch64_architecture_version; #define AARCH64_FL_FOR_ARCH8_5 \ (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5 \ | AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES) +#define AARCH64_FL_FOR_ARCH8_6 \ + (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_V8_6 | AARCH64_FL_FPSIMD \ + | AARCH64_FL_I8MM | AARCH64_FL_BF16) /* Macros to test ISA flags. */ @@ -249,6 +261,9 @@ extern unsigned aarch64_architecture_version; #define AARCH64_ISA_V8_5 (aarch64_isa_flags & AARC