Re: [PATCH][AArch64 array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md
On Tue, Sep 15, 2015 at 10:14:38AM +0100, Alan Lawrence wrote:
> The V_THREE_ELEM attribute used BLKmode for most sizes, but occasionally
> EImode. This patch changes to BLKmode in all cases, explicitly setting
> memory size (thus, preserving size for the cases that were EImode, and
> setting size for the first time for cases that were already BLKmode).
>
> The patterns affected are only for intrinsics: the aarch64_ld3r
> expanders and aarch64_simd_ld3r insns, and the
> aarch64_vec_{load,store}_lanesci_lane insns used by the
> aarch64_{ld,st}3_lane expanders.
>
> bootstrapped and check-gcc on aarch64-none-linux-gnu
OK (some comments on your ChangeLog below).
Thanks,
James
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd.md (aarch64_simd_ld3r,
> aarch64_vec_load_lanesci_lane,
> aarch64_vec_store_lanesci_lane): Change operand mode
> from to BLK.
I see this style used by a few people in the ChangeLog, personally I prefer
the form where each named entity is in its own set of (), such that I can
search for "(aarch64_foo)" and not match partial strings like
", aarch64_foo_bar" as I would searching "aarch64_foo" with your format.
>
No newline here.
> (aarch64_ld3r, aarch64_ld3_lane,
> aarch64_st3_lane): Generate MEM rtx with BLKmode, call
> set_mem_size.
>
Likewise.
> * config/aarch64/iterators.md (V_THREE_ELEM): Remove.
[PATCH][AArch64 array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md
The V_THREE_ELEM attribute used BLKmode for most sizes, but occasionally
EImode. This patch changes to BLKmode in all cases, explicitly setting
memory size (thus, preserving size for the cases that were EImode, and
setting size for the first time for cases that were already BLKmode).
The patterns affected are only for intrinsics: the aarch64_ld3r
expanders and aarch64_simd_ld3r insns, and the
aarch64_vec_{load,store}_lanesci_lane insns used by the
aarch64_{ld,st}3_lane expanders.
bootstrapped and check-gcc on aarch64-none-linux-gnu
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_simd_ld3r,
aarch64_vec_load_lanesci_lane,
aarch64_vec_store_lanesci_lane): Change operand mode
from to BLK.
(aarch64_ld3r, aarch64_ld3_lane,
aarch64_st3_lane): Generate MEM rtx with BLKmode, call
set_mem_size.
* config/aarch64/iterators.md (V_THREE_ELEM): Remove.
---
gcc/config/aarch64/aarch64-simd.md | 26 +-
gcc/config/aarch64/iterators.md| 9 -
2 files changed, 13 insertions(+), 22 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 20b9be9..c1048d3 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4026,7 +4026,7 @@
(define_insn "aarch64_simd_ld3r"
[(set (match_operand:CI 0 "register_operand" "=w")
- (unspec:CI [(match_operand: 1
"aarch64_simd_struct_operand" "Utv")
+ (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
UNSPEC_LD3_DUP))]
"TARGET_SIMD"
@@ -4036,7 +4036,7 @@
(define_insn "aarch64_vec_load_lanesci_lane"
[(set (match_operand:CI 0 "register_operand" "=w")
- (unspec:CI [(match_operand: 1
"aarch64_simd_struct_operand" "Utv")
+ (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")
(match_operand:CI 2 "register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
@@ -4080,11 +4080,11 @@
;; RTL uses GCC vector extension indices, so flip only for assembly.
(define_insn "aarch64_vec_store_lanesci_lane"
- [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv")
- (unspec: [(match_operand:CI 1 "register_operand" "w")
- (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
- (match_operand:SI 2 "immediate_operand" "i")]
- UNSPEC_ST3_LANE))]
+ [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
+ (unspec:BLK [(match_operand:CI 1 "register_operand" "w")
+(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
+(match_operand:SI 2 "immediate_operand" "i")]
+ UNSPEC_ST3_LANE))]
"TARGET_SIMD"
{
operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2])));
@@ -4400,8 +4400,8 @@
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
- machine_mode mode = mode;
- rtx mem = gen_rtx_MEM (mode, operands[1]);
+ rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+ set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3);
emit_insn (gen_aarch64_simd_ld3r (operands[0], mem));
DONE;
@@ -4625,8 +4625,8 @@
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
- machine_mode mode = mode;
- rtx mem = gen_rtx_MEM (mode, operands[1]);
+ rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+ set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3);
emit_insn (gen_aarch64_vec_load_lanesci_lane (operands[0],
mem,
@@ -4905,8 +4905,8 @@
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
{
- machine_mode mode = mode;
- rtx mem = gen_rtx_MEM (mode, operands[0]);
+ rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
+ set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3);
emit_insn (gen_aarch64_vec_store_lanesci_lane (mem,
operands[1],
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 298bee6..65ca0fd 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -601,15 +601,6 @@
(V4HF "SF") (V8HF "SF")
(DF "V2DI") (V2DF "V2DI")])
-;; Similar, for three elements.
-(define_mode_attr V_THREE_ELEM [(V8QI "BLK") (V16QI "BLK")
-(V4HI "BLK") (V8HI "BLK")
-(V2SI "BLK") (V4SI "BLK")
-(DI "EI")(V2DI "EI")
-(V2SF "BLK") (V4SF "BLK")
-(V4HF "BLK") (V8HF "BLK")
-(DF "EI")(V2DF "EI")])
-
;; Similar,
[PATCH][AArch64 array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md
The V_THREE_ELEM attribute used BLKmode for most sizes, but occasionally
EImode. This patch changes to BLKmode in all cases, explicitly setting
memory size (thus, preserving size for the cases that were EImode, and
setting size for the first time for cases that were already BLKmode).
The patterns affected are only for intrinsics: the aarch64_ld3r
expanders and aarch64_simd_ld3r insns, and the
aarch64_vec_{load,store}_lanesci_lane insns used by the
aarch64_{ld,st}3_lane expanders.
bootstrapped and check-gcc on aarch64-none-linux-gnu
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_simd_ld3rmode,
aarch64_vec_load_lanesci_lanemode,
aarch64_vec_store_lanesci_lanemode): Change operand mode
from V_THREE_ELEM to BLK.
(aarch64_ld3rmode, aarch64_ld3_lanemode,
aarch64_st3_laneVQ:mode): Generate MEM rtx with BLKmode, call
set_mem_size.
* config/aarch64/iterators.md (V_THREE_ELEM): Remove.
---
gcc/config/aarch64/aarch64-simd.md | 27 ++-
gcc/config/aarch64/iterators.md| 8
2 files changed, 14 insertions(+), 21 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 7b7a1b8..156fc4f 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4001,7 +4001,7 @@
(define_insn aarch64_simd_ld3rmode
[(set (match_operand:CI 0 register_operand =w)
- (unspec:CI [(match_operand:V_THREE_ELEM 1
aarch64_simd_struct_operand Utv)
+ (unspec:CI [(match_operand:BLK 1 aarch64_simd_struct_operand Utv)
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
UNSPEC_LD3_DUP))]
TARGET_SIMD
@@ -4011,7 +4011,7 @@
(define_insn aarch64_vec_load_lanesci_lanemode
[(set (match_operand:CI 0 register_operand =w)
- (unspec:CI [(match_operand:V_THREE_ELEM 1
aarch64_simd_struct_operand Utv)
+ (unspec:CI [(match_operand:BLK 1 aarch64_simd_struct_operand Utv)
(match_operand:CI 2 register_operand 0)
(match_operand:SI 3 immediate_operand i)
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
@@ -4052,11 +4052,11 @@
;; RTL uses GCC vector extension indices, so flip only for assembly.
(define_insn aarch64_vec_store_lanesci_lanemode
- [(set (match_operand:V_THREE_ELEM 0 aarch64_simd_struct_operand =Utv)
- (unspec:V_THREE_ELEM [(match_operand:CI 1 register_operand w)
-(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
- (match_operand:SI 2 immediate_operand i)]
- UNSPEC_ST3_LANE))]
+ [(set (match_operand:BLK 0 aarch64_simd_struct_operand =Utv)
+ (unspec:BLK [(match_operand:CI 1 register_operand w)
+(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
+(match_operand:SI 2 immediate_operand i)]
+ UNSPEC_ST3_LANE))]
TARGET_SIMD
{
operands[2] = GEN_INT (ENDIAN_LANE_N (MODEmode, INTVAL (operands[2])));
@@ -4368,8 +4368,8 @@
(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
TARGET_SIMD
{
- machine_mode mode = V_THREE_ELEMmode;
- rtx mem = gen_rtx_MEM (mode, operands[1]);
+ rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+ set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (MODEmode)) * 3);
emit_insn (gen_aarch64_simd_ld3rmode (operands[0], mem));
DONE;
@@ -4589,8 +4589,8 @@
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
TARGET_SIMD
{
- machine_mode mode = V_THREE_ELEMmode;
- rtx mem = gen_rtx_MEM (mode, operands[1]);
+ rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+ set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (MODEmode)) * 3);
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (VCONQmode),
NULL);
@@ -4874,8 +4874,9 @@
(match_operand:SI 2 immediate_operand)]
TARGET_SIMD
{
- machine_mode mode = V_THREE_ELEMmode;
- rtx mem = gen_rtx_MEM (mode, operands[0]);
+ rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
+ set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (MODEmode)) * 3);
+
operands[2] = GEN_INT (ENDIAN_LANE_N (MODEmode, INTVAL (operands[2])));
emit_insn (gen_aarch64_vec_store_lanesci_laneVQ:mode (mem,
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 98b6714..ae0be0b 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -568,14 +568,6 @@
(V2SF V2SF) (V4SF V2SF)
(DF V2DI) (V2DF V2DI)])
-;; Similar, for three elements.
-(define_mode_attr V_THREE_ELEM [(V8QI BLK) (V16QI BLK)
-(V4HI BLK) (V8HI BLK)
-(V2SI BLK) (V4SI BLK)
-(DI EI)(V2DI EI)
-(V2SF BLK) (V4SF BLK)
-(DF EI)(V2DF EI)])
-
;; Similar, for four elements.
