Re: [PATCH] [Refactor] [AVX512] Combine VI12_AVX512VL with VI48_AVX512VL into VI_AVX512VLBW
On Wed, Dec 2, 2020 at 9:57 AM Hongtao Liu wrote:
>
> On Wed, Dec 2, 2020 at 8:28 AM Jeff Law wrote:
> >
> >
> >
> > On 11/30/20 10:17 PM, Hongtao Liu via Gcc-patches wrote:
> > > Hi:
> > > There're many pairs of define_insn/define_expand that are very similar
> > > to each other except mode iterator and condition. For these patterns
> > > VI12_AVX512VL are used under condition TARGET_AVX512BW, and
> > > VI48_AVX512VL are used under condition TARGET_AVX512F.
> > >
> > > This patch is about to introduce a new iterator VI_AVX512VLBW to
> > > combine a pair of those patterns into one.
> > >
> > > There are no functional changes, just code refactoring.
> > >
> > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
> > >
> > > gcc/ChangeLog
> > >
> > > * config/i386/sse.md (VI_AVX512VLBW): New mode iterator.
> > > (_ucmp3): Combine
> > > two patterns with mode iterator VI12_AVX512VL and VI48_AVX512VL
> > > into one pattern with mode iterator VI_AVX512VLBW.
> > > (vec_cmpu): Ditto.
> > > (_cvt2mask): Ditto.
> > > (_cvtmask2): Ditto.
> > > (*_cvtmask2): Ditto.
> > > (3_mask): Ditto.
> > > (*3_mask): Ditto.
> > > (_eq3): Ditto.
> > > (_eq3_1): Ditto.
> > > (_gt3): Ditto.
> > > (_andnot3_mask): Ditto.
> > > (abs2_mask): Ditto.
> > > (*_3): Combine from ...
> > > (*avx512f_3)
> > > and (3).
> > I'd suggest deferring to gcc-12 unless there is a strong need for this
> > cleanup to make fixing a bug easier.
> >
> > jeff
> >
>
> Sure, I'll wait for GCC-12.
>
Rebased patch.
> --
> BR,
> Hongtao
--
BR,
Hongtao
From 51a2fba947b5de779cda4f464cd25b13a21ff99c Mon Sep 17 00:00:00 2001
From: liuhongt
Date: Fri, 23 Apr 2021 16:24:14 +0800
Subject: [PATCH] [PATCH] [i386] Combine same patterns with different iterators
of VI12_AVX512VL and VI48_AVX512VL into VI1248_AVX512VLBW.
gcc/ChangeLog
* config/i386/sse.md
(_ucmp3): Merge two same
patterns with different iterators of VI12_AVX512VL and
VI48_AVX512VL into VI1248_AVX512VLBW.
(vec_cmpu): Ditto.
(_cvt2mask): Ditto.
(_cvtmask2): Ditto.
(*_cvtmask2): Ditto.
(3_mask): Ditto.
(*3_mask): Ditto.
(_eq3): Ditto.
(_eq3_1): Ditto.
(_gt3): Ditto.
(_andnot3_mask): Ditto.
(abs2_mask): Ditto.
(*avx512f_3, 3_mask):
Merged to ..
(3): .. this.
---
gcc/config/i386/sse.md | 298 ++---
1 file changed, 73 insertions(+), 225 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 9d3728d1cb0..fe8cb9c6d13 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -250,6 +250,14 @@ (define_mode_iterator VI12_AVX512VLBW
(V32QI "TARGET_AVX512VL && TARGET_AVX512BW") (V32HI "TARGET_AVX512BW")
(V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")])
+(define_mode_iterator VI1248_AVX512VLBW
+ [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL && TARGET_AVX512BW")
+ (V16QI "TARGET_AVX512VL && TARGET_AVX512BW")
+ (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512VL && TARGET_AVX512BW")
+ (V8HI "TARGET_AVX512VL && TARGET_AVX512BW")
+ V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")
+ V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
+
(define_mode_iterator VI1_AVX512VL
[V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")])
@@ -3222,22 +3230,8 @@ (define_insn_and_split "*_cmp3"
(define_insn "_ucmp3"
[(set (match_operand: 0 "register_operand" "=k")
(unspec:
- [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
- (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")
- (match_operand:SI 3 "const_0_to_7_operand" "n")]
- UNSPEC_UNSIGNED_PCMP))]
- "TARGET_AVX512BW"
- "vpcmpu\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssecmp")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "evex")
- (set_attr "mode" "")])
-
-(define_insn "_ucmp3"
- [(set (match_operand: 0 "register_operand" "=k")
- (unspec:
- [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
- (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")
+ [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
+ (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")
(match_operand:SI 3 "const_0_to_7_operand" "n")]
UNSPEC_UNSIGNED_PCMP))]
"TARGET_AVX512F"
@@ -3444,8 +3438,8 @@ (define_expand "vec_cmp"
(define_expand "vec_cmpu"
[(set (match_operand: 0 "register_operand")
(match_operator: 1 ""
- [(match_operand:VI48_AVX512VL 2 "register_operand")
- (match_operand:VI48_AVX512VL 3 "nonimmediate_operand")]))]
+ [(match_operand:VI1248_AVX512VLBW 2 "register_operand")
+ (match_operand:VI1248_AVX512VLBW 3 "nonimmediate_operand")]))]
"TARGET_AVX512F"
{
bool ok = ix86_expand_mask_vec_cmp (operands[0], GET_CODE (operands[1]),
@@ -3454,19 +3448,6 @@ (define_expand "vec_cmpu"
DONE;
})
-(define_expand "vec_cmpu"
- [(set (match_operand: 0 "register_operand")
- (mat
Re: [PATCH] [Refactor] [AVX512] Combine VI12_AVX512VL with VI48_AVX512VL into VI_AVX512VLBW
On Wed, Dec 2, 2020 at 8:28 AM Jeff Law wrote: > > > > On 11/30/20 10:17 PM, Hongtao Liu via Gcc-patches wrote: > > Hi: > > There're many pairs of define_insn/define_expand that are very similar > > to each other except mode iterator and condition. For these patterns > > VI12_AVX512VL are used under condition TARGET_AVX512BW, and > > VI48_AVX512VL are used under condition TARGET_AVX512F. > > > > This patch is about to introduce a new iterator VI_AVX512VLBW to > > combine a pair of those patterns into one. > > > > There are no functional changes, just code refactoring. > > > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? > > > > gcc/ChangeLog > > > > * config/i386/sse.md (VI_AVX512VLBW): New mode iterator. > > (_ucmp3): Combine > > two patterns with mode iterator VI12_AVX512VL and VI48_AVX512VL > > into one pattern with mode iterator VI_AVX512VLBW. > > (vec_cmpu): Ditto. > > (_cvt2mask): Ditto. > > (_cvtmask2): Ditto. > > (*_cvtmask2): Ditto. > > (3_mask): Ditto. > > (*3_mask): Ditto. > > (_eq3): Ditto. > > (_eq3_1): Ditto. > > (_gt3): Ditto. > > (_andnot3_mask): Ditto. > > (abs2_mask): Ditto. > > (*_3): Combine from ... > > (*avx512f_3) > > and (3). > I'd suggest deferring to gcc-12 unless there is a strong need for this > cleanup to make fixing a bug easier. > > jeff > Sure, I'll wait for GCC-12. -- BR, Hongtao
Re: [PATCH] [Refactor] [AVX512] Combine VI12_AVX512VL with VI48_AVX512VL into VI_AVX512VLBW
On 11/30/20 10:17 PM, Hongtao Liu via Gcc-patches wrote: > Hi: > There're many pairs of define_insn/define_expand that are very similar > to each other except mode iterator and condition. For these patterns > VI12_AVX512VL are used under condition TARGET_AVX512BW, and > VI48_AVX512VL are used under condition TARGET_AVX512F. > > This patch is about to introduce a new iterator VI_AVX512VLBW to > combine a pair of those patterns into one. > > There are no functional changes, just code refactoring. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? > > gcc/ChangeLog > > * config/i386/sse.md (VI_AVX512VLBW): New mode iterator. > (_ucmp3): Combine > two patterns with mode iterator VI12_AVX512VL and VI48_AVX512VL > into one pattern with mode iterator VI_AVX512VLBW. > (vec_cmpu): Ditto. > (_cvt2mask): Ditto. > (_cvtmask2): Ditto. > (*_cvtmask2): Ditto. > (3_mask): Ditto. > (*3_mask): Ditto. > (_eq3): Ditto. > (_eq3_1): Ditto. > (_gt3): Ditto. > (_andnot3_mask): Ditto. > (abs2_mask): Ditto. > (*_3): Combine from ... > (*avx512f_3) > and (3). I'd suggest deferring to gcc-12 unless there is a strong need for this cleanup to make fixing a bug easier. jeff
[PATCH] [Refactor] [AVX512] Combine VI12_AVX512VL with VI48_AVX512VL into VI_AVX512VLBW
Hi:
There're many pairs of define_insn/define_expand that are very similar
to each other except mode iterator and condition. For these patterns
VI12_AVX512VL are used under condition TARGET_AVX512BW, and
VI48_AVX512VL are used under condition TARGET_AVX512F.
This patch is about to introduce a new iterator VI_AVX512VLBW to
combine a pair of those patterns into one.
There are no functional changes, just code refactoring.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
gcc/ChangeLog
* config/i386/sse.md (VI_AVX512VLBW): New mode iterator.
(_ucmp3): Combine
two patterns with mode iterator VI12_AVX512VL and VI48_AVX512VL
into one pattern with mode iterator VI_AVX512VLBW.
(vec_cmpu): Ditto.
(_cvt2mask): Ditto.
(_cvtmask2): Ditto.
(*_cvtmask2): Ditto.
(3_mask): Ditto.
(*3_mask): Ditto.
(_eq3): Ditto.
(_eq3_1): Ditto.
(_gt3): Ditto.
(_andnot3_mask): Ditto.
(abs2_mask): Ditto.
(*_3): Combine from ...
(*avx512f_3)
and (3).
--
BR,
Hongtao
From e55528fb9a0346365327e7b1cdebadec7c71be15 Mon Sep 17 00:00:00 2001
From: liuhongt
Date: Mon, 30 Nov 2020 13:24:45 +0800
Subject: [PATCH] Combine VI12_AVX512VL with VI48_AVX512VL into VI_AVX512VLBW.
There're many pairs of define_insn/define_expand that are very similar
to each other except mode iterator and condition. For these patterns
VI12_AVX512VL are used under condition TARGET_AVX512BW, and
VI48_AVX512VL are used under condition TARGET_AVX512F.
This patch is about to introduce a new iterator VI_AVX512VLBW to
combine a pair of those patterns into one.
There're no functional changed, just code refactoring.
gcc/ChangeLog
* config/i386/sse.md (VI_AVX512VLBW): New mode iterator.
(_ucmp3): Combine
two patterns with mode iterator VI12_AVX512VL and VI48_AVX512VL
into one pattern with mode iterator VI_AVX512VLBW.
(vec_cmpu): Ditto.
(_cvt2mask): Ditto.
(_cvtmask2): Ditto.
(*_cvtmask2): Ditto.
(3_mask): Ditto.
(*3_mask): Ditto.
(_eq3): Ditto.
(_eq3_1): Ditto.
(_gt3): Ditto.
(_andnot3_mask): Ditto.
(abs2_mask): Ditto.
(*_3): Combine from ...
(*avx512f_3)
and (3).
---
gcc/config/i386/sse.md | 312 -
1 file changed, 89 insertions(+), 223 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 4aad462f882..c761a018e86 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -335,6 +335,14 @@ (define_mode_iterator VI48_AVX512VL
[V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")
V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
+(define_mode_iterator VI_AVX512VLBW
+ [(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")
+ (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")
+ (V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL && TARGET_AVX512BW")
+ (V16QI "TARGET_AVX512BW && TARGET_AVX512VL")
+ (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512VL && TARGET_AVX512BW")
+ (V8HI "TARGET_AVX512VL && TARGET_AVX512BW")])
+
(define_mode_iterator VF_AVX512VL
[V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")
V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
@@ -2981,25 +2989,11 @@ (define_insn "_cmp3"
(define_insn "_ucmp3"
[(set (match_operand: 0 "register_operand" "=k")
(unspec:
- [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
- (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")
+ [(match_operand:VI_AVX512VLBW 1 "register_operand" "v")
+ (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand" "vm")
(match_operand:SI 3 "const_0_to_7_operand" "n")]
UNSPEC_UNSIGNED_PCMP))]
- "TARGET_AVX512BW"
- "vpcmpu\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssecmp")
- (set_attr "length_immediate" "1")
- (set_attr "prefix" "evex")
- (set_attr "mode" "")])
-
-(define_insn "_ucmp3"
- [(set (match_operand: 0 "register_operand" "=k")
- (unspec:
- [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
- (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")
- (match_operand:SI 3 "const_0_to_7_operand" "n")]
- UNSPEC_UNSIGNED_PCMP))]
- "TARGET_AVX512F"
+ ""
"vpcmpu\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssecmp")
(set_attr "length_immediate" "1")
@@ -3149,22 +3143,9 @@ (define_expand "vec_cmp"
(define_expand "vec_cmpu"
[(set (match_operand: 0 "register_operand")
(match_operator: 1 ""
- [(match_operand:VI48_AVX512VL 2 "register_operand")
- (match_operand:VI48_AVX512VL 3 "nonimmediate_operand")]))]
- "TARGET_AVX512F"
-{
- bool ok = ix86_expand_mask_vec_cmp (operands[0], GET_CODE (operands[1]),
- operands[2], operands[3]);
- gcc_assert (ok);
- DONE;
-})
-
-(define_expand "vec_cmpu"
- [(set (match_operand: 0 "register_operand")
- (match_operator: 1 ""
- [(match_operand:VI12_AVX512VL 2 "register_operand")
- (match_operand:VI12_
