Re: [PATCH 1/2] [ARC] Improve code gen when compiling for size
Committed with your feedback taken into account. Thank you for your review, Claudiu On Sat, Jun 8, 2019 at 12:57 AM Jeff Law wrote: > > On 6/6/19 1:42 AM, Claudiu Zissulescu wrote: > > When optimizing for size, try to avoid using long immediate by > > employing alternative (short) instructions. > > > > Ok to apply? > > Claudiu > > > > gcc/ > > -xx-xx Claudiu Zissulescu > > > > * config/arc/arc-protos.h (arc_check_ior_const): Declare. > > (arc_split_ior): Likewise. > > (arc_check_mov_const): Likewise. > > (arc_split_mov_const): Likewise. > > * config/arc/arc.c (arc_print_operand): Fix 'z' letter. > > (arc_rtx_costs): Replace check Crr with Cax constraint. > > (prepare_move_operands): Cleanup, remove unused code. > > (arc_split_ior): New function. > > (arc_check_ior_const): Likewise. > > (arc_split_mov_const): Likewise. > > (arc_check_mov_const): Likewise. > > * config/arc/arc.md (movsi_insn): Restructure it, and convert it > > in define_insn_and_split pattern. > > (iorsi3): Likewise. > > (mulsi3_v2): Add new matching variant. > > (andsi3_i): Cleanup pattern. > > (rotrsi3_cnt1): Update pattern. > > (rotrsi3_cnt8): New pattern. > > (ashlsi2_cnt8): Likewise. > > (ashlsi2_cnt16): Likewise. > > * config/arc/constraints.md (C0p): Update constraint. > > (Crr): Remove it. > > (C0x): New pattern. > > (Cax): New pattern. > > > > testsuite/ > > -xx-xx Claudiu Zissulescu > > > > * gcc.target/arc/and-cnst-size.c: New test. > > * gcc.target/arc/mov-cnst-size.c: Likewise. > > * gcc.target/arc/or-cnst-size.c: Likewise. > > * gcc.target/arc/store-merge-1.c: Update test. > > * gcc.target/arc/arc700-stld-hazard.c: Likewise. > > * gcc.target/arc/cmem-1.c: Likewise. > > * gcc.target/arc/cmem-2.c: Likewise. > > * gcc.target/arc/cmem-3.c: Likewise. > > * gcc.target/arc/cmem-4.c: Likewise. > > * gcc.target/arc/cmem-5.c: Likewise. > > * gcc.target/arc/cmem-6.c: Likewise. > > * gcc.target/arc/loop-4.c: Likewise. > > * gcc.target/arc/movh_cl-1.c: Likewise. > > * gcc.target/arc/sdata-3.c: Likewise. > > --- > > > > diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c > > index b49f2539408..f398c4a0086 100644 > > --- a/gcc/config/arc/arc.c > > +++ b/gcc/config/arc/arc.c > > @@ -11457,6 +11429,198 @@ arc_memory_move_cost (machine_mode mode, > >return (2 * GET_MODE_SIZE (mode)); > > } > > > > +/* Split an OR instruction into multiple BSET/OR instructions in a > > + tentative to avoid long immediate constants. The next strategies > > + are employed when destination is 'q' reg. > s/tentative/attempt/ ? > > > + > > + 1. if there are up to three bits set in the mask, a succesion of > s/succesion/succession/ > > OK with the nits fixed. > > jeff
Re: [PATCH 1/2] [ARC] Improve code gen when compiling for size
On 6/6/19 1:42 AM, Claudiu Zissulescu wrote: > When optimizing for size, try to avoid using long immediate by > employing alternative (short) instructions. > > Ok to apply? > Claudiu > > gcc/ > -xx-xx Claudiu Zissulescu > > * config/arc/arc-protos.h (arc_check_ior_const): Declare. > (arc_split_ior): Likewise. > (arc_check_mov_const): Likewise. > (arc_split_mov_const): Likewise. > * config/arc/arc.c (arc_print_operand): Fix 'z' letter. > (arc_rtx_costs): Replace check Crr with Cax constraint. > (prepare_move_operands): Cleanup, remove unused code. > (arc_split_ior): New function. > (arc_check_ior_const): Likewise. > (arc_split_mov_const): Likewise. > (arc_check_mov_const): Likewise. > * config/arc/arc.md (movsi_insn): Restructure it, and convert it > in define_insn_and_split pattern. > (iorsi3): Likewise. > (mulsi3_v2): Add new matching variant. > (andsi3_i): Cleanup pattern. > (rotrsi3_cnt1): Update pattern. > (rotrsi3_cnt8): New pattern. > (ashlsi2_cnt8): Likewise. > (ashlsi2_cnt16): Likewise. > * config/arc/constraints.md (C0p): Update constraint. > (Crr): Remove it. > (C0x): New pattern. > (Cax): New pattern. > > testsuite/ > -xx-xx Claudiu Zissulescu > > * gcc.target/arc/and-cnst-size.c: New test. > * gcc.target/arc/mov-cnst-size.c: Likewise. > * gcc.target/arc/or-cnst-size.c: Likewise. > * gcc.target/arc/store-merge-1.c: Update test. > * gcc.target/arc/arc700-stld-hazard.c: Likewise. > * gcc.target/arc/cmem-1.c: Likewise. > * gcc.target/arc/cmem-2.c: Likewise. > * gcc.target/arc/cmem-3.c: Likewise. > * gcc.target/arc/cmem-4.c: Likewise. > * gcc.target/arc/cmem-5.c: Likewise. > * gcc.target/arc/cmem-6.c: Likewise. > * gcc.target/arc/loop-4.c: Likewise. > * gcc.target/arc/movh_cl-1.c: Likewise. > * gcc.target/arc/sdata-3.c: Likewise. > --- > > diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c > index b49f2539408..f398c4a0086 100644 > --- a/gcc/config/arc/arc.c > +++ b/gcc/config/arc/arc.c > @@ -11457,6 +11429,198 @@ arc_memory_move_cost (machine_mode mode, >return (2 * GET_MODE_SIZE (mode)); > } > > +/* Split an OR instruction into multiple BSET/OR instructions in a > + tentative to avoid long immediate constants. The next strategies > + are employed when destination is 'q' reg. s/tentative/attempt/ ? > + > + 1. if there are up to three bits set in the mask, a succesion of s/succesion/succession/ OK with the nits fixed. jeff
[PATCH 1/2] [ARC] Improve code gen when compiling for size
When optimizing for size, try to avoid using long immediate by
employing alternative (short) instructions.
Ok to apply?
Claudiu
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc-protos.h (arc_check_ior_const): Declare.
(arc_split_ior): Likewise.
(arc_check_mov_const): Likewise.
(arc_split_mov_const): Likewise.
* config/arc/arc.c (arc_print_operand): Fix 'z' letter.
(arc_rtx_costs): Replace check Crr with Cax constraint.
(prepare_move_operands): Cleanup, remove unused code.
(arc_split_ior): New function.
(arc_check_ior_const): Likewise.
(arc_split_mov_const): Likewise.
(arc_check_mov_const): Likewise.
* config/arc/arc.md (movsi_insn): Restructure it, and convert it
in define_insn_and_split pattern.
(iorsi3): Likewise.
(mulsi3_v2): Add new matching variant.
(andsi3_i): Cleanup pattern.
(rotrsi3_cnt1): Update pattern.
(rotrsi3_cnt8): New pattern.
(ashlsi2_cnt8): Likewise.
(ashlsi2_cnt16): Likewise.
* config/arc/constraints.md (C0p): Update constraint.
(Crr): Remove it.
(C0x): New pattern.
(Cax): New pattern.
testsuite/
-xx-xx Claudiu Zissulescu
* gcc.target/arc/and-cnst-size.c: New test.
* gcc.target/arc/mov-cnst-size.c: Likewise.
* gcc.target/arc/or-cnst-size.c: Likewise.
* gcc.target/arc/store-merge-1.c: Update test.
* gcc.target/arc/arc700-stld-hazard.c: Likewise.
* gcc.target/arc/cmem-1.c: Likewise.
* gcc.target/arc/cmem-2.c: Likewise.
* gcc.target/arc/cmem-3.c: Likewise.
* gcc.target/arc/cmem-4.c: Likewise.
* gcc.target/arc/cmem-5.c: Likewise.
* gcc.target/arc/cmem-6.c: Likewise.
* gcc.target/arc/loop-4.c: Likewise.
* gcc.target/arc/movh_cl-1.c: Likewise.
* gcc.target/arc/sdata-3.c: Likewise.
---
gcc/config/arc/arc-protos.h | 4 +
gcc/config/arc/arc.c | 222 +++---
gcc/config/arc/arc.md | 215 ++---
gcc/config/arc/constraints.md | 22 +-
gcc/testsuite/gcc.target/arc/and-cnst-size.c | 16 ++
.../gcc.target/arc/arc700-stld-hazard.c | 4 +-
gcc/testsuite/gcc.target/arc/cmem-1.c | 6 +-
gcc/testsuite/gcc.target/arc/cmem-2.c | 6 +-
gcc/testsuite/gcc.target/arc/cmem-3.c | 6 +-
gcc/testsuite/gcc.target/arc/cmem-4.c | 6 +-
gcc/testsuite/gcc.target/arc/cmem-5.c | 6 +-
gcc/testsuite/gcc.target/arc/cmem-6.c | 6 +-
gcc/testsuite/gcc.target/arc/loop-4.c | 3 +-
gcc/testsuite/gcc.target/arc/mov-cnst-size.c | 42
gcc/testsuite/gcc.target/arc/movh_cl-1.c | 2 +-
gcc/testsuite/gcc.target/arc/or-cnst-size.c | 16 ++
gcc/testsuite/gcc.target/arc/sdata-3.c| 18 +-
gcc/testsuite/gcc.target/arc/store-merge-1.c | 2 +-
18 files changed, 449 insertions(+), 153 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arc/and-cnst-size.c
create mode 100644 gcc/testsuite/gcc.target/arc/mov-cnst-size.c
create mode 100644 gcc/testsuite/gcc.target/arc/or-cnst-size.c
diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
index ac0de6b2874..f501bc30ee7 100644
--- a/gcc/config/arc/arc-protos.h
+++ b/gcc/config/arc/arc-protos.h
@@ -48,6 +48,10 @@ extern bool arc_is_uncached_mem_p (rtx);
extern bool gen_operands_ldd_std (rtx *operands, bool load, bool commute);
extern bool arc_check_multi (rtx, bool);
extern void arc_adjust_reg_alloc_order (void);
+extern bool arc_check_ior_const (HOST_WIDE_INT );
+extern void arc_split_ior (rtx *);
+extern bool arc_check_mov_const (HOST_WIDE_INT );
+extern bool arc_split_mov_const (rtx *);
#endif /* RTX_CODE */
extern unsigned int arc_compute_frame_size (int);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index b49f2539408..f398c4a0086 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -4232,7 +4232,7 @@ arc_print_operand (FILE *file, rtx x, int code)
case 'z':
if (GET_CODE (x) == CONST_INT)
- fprintf (file, "%d",exact_log2(INTVAL (x)) );
+ fprintf (file, "%d",exact_log2 (INTVAL (x) & 0x));
else
output_operand_lossage ("invalid operand to %%z code");
@@ -5597,9 +5597,6 @@ arc_rtx_costs (rtx x, machine_mode mode, int outer_code,
if (satisfies_constraint_C0p (x)) /* bxor */
nolimm = fast = condexec = true;
break;
- case SET:
- if (satisfies_constraint_Crr (x)) /* ror b,u6 */
- nolimm = true;
default:
break;
}
@@ -9088,31 +9085,6 @@ prepare_move_operands (rtx *operands, machine_mode mode)
MEM_COPY_ATTRIBUTES (pat, operands[0]);
operands[0] = pat;
}
- if (!cse_not_expected)
- {
- rtx pat =
