subject:"\[PATCH v1\] RISC\-V\: Support rounding mode for VFNMADD\/VFNMACC autovec"

Re: [PATCH v1] RISC-V: Support rounding mode for VFNMADD/VFNMACC autovec

2023-08-24 Thread Kito Cheng via Gcc-patches

lgtm

On Fri, Aug 25, 2023 at 9:49 AM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> There will be a case like below for intrinsic and autovec combination.
>
> vfadd RTZ   <- intrinisc static rounding
> vfnmadd <- autovec/autovec-opt
>
> The autovec generated vfnmadd should take DYN mode, and the
> frm must be restored before the vfnmadd insn. This patch
> would like to fix this issue by:
>
> * Add the frm operand to the autovec/autovec-opt pattern.
> * Set the frm_mode attr to DYN.
>
> Thus, the frm flow when combine autovec and intrinsic should be.
>
> +
> | frrm  a5
> | ...
> | fsrmi 4
> | vfadd   <- intrinsic static rounding.
> | ...
> | fsrm  a5
> | vfnmadd <- autovec/autovec-opt
> | ...
> +
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmadd/vfnmacc.
> * config/riscv/autovec.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: New test.
> ---
>  gcc/config/riscv/autovec-opt.md   | 38 
>  gcc/config/riscv/autovec.md   | 34 ---
>  .../rvv/base/float-point-frm-autovec-4.c  | 88 +++
>  3 files changed, 130 insertions(+), 30 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 54ca6df721c..2922f370a17 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -655,14 +655,16 @@ (define_insn_and_split "*single_widen_fms"
>  ;; vect__13.182_33 = .FNMS (vect__11.180_35, vect__8.176_40, vect__4.172_45);
>  (define_insn_and_split "*double_widen_fnms"
>[(set (match_operand:VWEXTF 0 "register_operand")
> -   (fma:VWEXTF
> - (neg:VWEXTF
> +   (unspec:VWEXTF
> + [(fma:VWEXTF
> +   (neg:VWEXTF
> + (float_extend:VWEXTF
> +   (match_operand: 2 "register_operand")))
> (float_extend:VWEXTF
> - (match_operand: 2 "register_operand")))
> - (float_extend:VWEXTF
> -   (match_operand: 3 "register_operand"))
> - (neg:VWEXTF
> -   (match_operand:VWEXTF 1 "register_operand"]
> + (match_operand: 3 "register_operand"))
> +   (neg:VWEXTF
> + (match_operand:VWEXTF 1 "register_operand")))
> +  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -673,18 +675,21 @@ (define_insn_and_split "*double_widen_fnms"
>  DONE;
>}
>[(set_attr "type" "vfwmuladd")
> -   (set_attr "mode" "")])
> +   (set_attr "mode" "")
> +   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
>  ;; This helps to match ext + fnms.
>  (define_insn_and_split "*single_widen_fnms"
>[(set (match_operand:VWEXTF 0 "register_operand")
> -   (fma:VWEXTF
> - (neg:VWEXTF
> -   (float_extend:VWEXTF
> - (match_operand: 2 "register_operand")))
> - (match_operand:VWEXTF 3 "register_operand")
> - (neg:VWEXTF
> -   (match_operand:VWEXTF 1 "register_operand"]
> +   (unspec:VWEXTF
> + [(fma:VWEXTF
> +   (neg:VWEXTF
> + (float_extend:VWEXTF
> +   (match_operand: 2 "register_operand")))
> +   (match_operand:VWEXTF 3 "register_operand")
> +   (neg:VWEXTF
> + (match_operand:VWEXTF 1 "register_operand")))
> +  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -701,4 +706,5 @@ (define_insn_and_split "*single_widen_fnms"
>  DONE;
>}
>[(set_attr "type" "vfwmuladd")
> -   (set_attr "mode" "")])
> +   (set_attr "mode" "")
> +   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 28396c6175d..5f16ac53712 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1274,26 +1274,31 @@ (define_insn_and_split "*fms"
>  (define_expand "fnms4"
>[(parallel
>  [(set (match_operand:VF 0 "register_operand")
> - (fma:VF
> -   (neg:VF
> - (match_operand:VF 1 "register_operand"))
> -   (match_operand:VF 2 "register_operand")
> -   (neg:VF
> - (match_operand:VF 3 "register_operand"
> + (unspec:VF
> +   [(fma:VF
> + (neg:VF
> +   (match_operand:VF 1 "register_operand"))
> + (match_operand:VF 2 "register_operand")
> + (neg:VF
> +   (match_operand:VF 3 "register_operand")))
> +(reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
>   (clobber (match_dup 4))])]
>"TARGET_VECTOR"
>{
>  operands[4] = gen_reg_rtx (Pmode);
> -  })
> +  }
> +  [(set (attr "frm_mode") (symbol_ref

[PATCH v1] RISC-V: Support rounding mode for VFNMADD/VFNMACC autovec

2023-08-24 Thread Pan Li via Gcc-patches

From: Pan Li 

There will be a case like below for intrinsic and autovec combination.

vfadd RTZ   <- intrinisc static rounding
vfnmadd <- autovec/autovec-opt

The autovec generated vfnmadd should take DYN mode, and the
frm must be restored before the vfnmadd insn. This patch
would like to fix this issue by:

* Add the frm operand to the autovec/autovec-opt pattern.
* Set the frm_mode attr to DYN.

Thus, the frm flow when combine autovec and intrinsic should be.

+
| frrm  a5
| ...
| fsrmi 4
| vfadd   <- intrinsic static rounding.
| ...
| fsrm  a5
| vfnmadd <- autovec/autovec-opt
| ...
+

Signed-off-by: Pan Li 

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmadd/vfnmacc.
* config/riscv/autovec.md: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: New test.
---
 gcc/config/riscv/autovec-opt.md   | 38 
 gcc/config/riscv/autovec.md   | 34 ---
 .../rvv/base/float-point-frm-autovec-4.c  | 88 +++
 3 files changed, 130 insertions(+), 30 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 54ca6df721c..2922f370a17 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -655,14 +655,16 @@ (define_insn_and_split "*single_widen_fms"
 ;; vect__13.182_33 = .FNMS (vect__11.180_35, vect__8.176_40, vect__4.172_45);
 (define_insn_and_split "*double_widen_fnms"
   [(set (match_operand:VWEXTF 0 "register_operand")
-   (fma:VWEXTF
- (neg:VWEXTF
+   (unspec:VWEXTF
+ [(fma:VWEXTF
+   (neg:VWEXTF
+ (float_extend:VWEXTF
+   (match_operand: 2 "register_operand")))
(float_extend:VWEXTF
- (match_operand: 2 "register_operand")))
- (float_extend:VWEXTF
-   (match_operand: 3 "register_operand"))
- (neg:VWEXTF
-   (match_operand:VWEXTF 1 "register_operand"]
+ (match_operand: 3 "register_operand"))
+   (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand")))
+  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
@@ -673,18 +675,21 @@ (define_insn_and_split "*double_widen_fnms"
 DONE;
   }
   [(set_attr "type" "vfwmuladd")
-   (set_attr "mode" "")])
+   (set_attr "mode" "")
+   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
 
 ;; This helps to match ext + fnms.
 (define_insn_and_split "*single_widen_fnms"
   [(set (match_operand:VWEXTF 0 "register_operand")
-   (fma:VWEXTF
- (neg:VWEXTF
-   (float_extend:VWEXTF
- (match_operand: 2 "register_operand")))
- (match_operand:VWEXTF 3 "register_operand")
- (neg:VWEXTF
-   (match_operand:VWEXTF 1 "register_operand"]
+   (unspec:VWEXTF
+ [(fma:VWEXTF
+   (neg:VWEXTF
+ (float_extend:VWEXTF
+   (match_operand: 2 "register_operand")))
+   (match_operand:VWEXTF 3 "register_operand")
+   (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand")))
+  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
@@ -701,4 +706,5 @@ (define_insn_and_split "*single_widen_fnms"
 DONE;
   }
   [(set_attr "type" "vfwmuladd")
-   (set_attr "mode" "")])
+   (set_attr "mode" "")
+   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 28396c6175d..5f16ac53712 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1274,26 +1274,31 @@ (define_insn_and_split "*fms"
 (define_expand "fnms4"
   [(parallel
 [(set (match_operand:VF 0 "register_operand")
- (fma:VF
-   (neg:VF
- (match_operand:VF 1 "register_operand"))
-   (match_operand:VF 2 "register_operand")
-   (neg:VF
- (match_operand:VF 3 "register_operand"
+ (unspec:VF
+   [(fma:VF
+ (neg:VF
+   (match_operand:VF 1 "register_operand"))
+ (match_operand:VF 2 "register_operand")
+ (neg:VF
+   (match_operand:VF 3 "register_operand")))
+(reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
  (clobber (match_dup 4))])]
   "TARGET_VECTOR"
   {
 operands[4] = gen_reg_rtx (Pmode);
-  })
+  }
+  [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
 
 (define_insn_and_split "*fnms"
   [(set (match_operand:VF 0 "register_operand" "=vr, vr, ?")
-   (fma:VF
- (neg:VF
-   (match_operand:VF 1 "register_operand" " %0, vr,   vr"))
- (match_operand:VF 2 "register_operand"   " vr, vr,   vr")
- (neg:VF
-   (match_operand:VF 3

Re: [PATCH v1] RISC-V: Support rounding mode for VFNMADD/VFNMACC autovec

[PATCH v1] RISC-V: Support rounding mode for VFNMADD/VFNMACC autovec

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