Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Jeff Law via Gcc-patches]

On 6/15/23 03:52, Jin Ma wrote:

  


There are also some problems here, which cannot be simply handled like HF.
Many instructions support HF but do not support BF. For example, fadd.h
can be used for HF but cannot be used for BF.

I guess it may need to be converted to SF first, then fadd.s, and finally
converted to BF.  I'm not so sure.

Right.  This is relatively common.

jeff

Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Jin Ma via Gcc-patches]

> diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
> index 5b70ab20758..6349f032bc8 100644
> --- a/gcc/config/riscv/iterators.md
> +++ b/gcc/config/riscv/iterators.md
> @@ -61,10 +61,15 @@
>  ;; Iterator for hardware-supported floating-point modes.
>  (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
> (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
> -   (HF "TARGET_ZFH || TARGET_ZHINX")])
> +   (HF "TARGET_ZFH || TARGET_ZHINX") 
> +(BF "TARGET_ZFBFMIN")])
> +
> +;; Iterator for HImode constant generation.
> +(define_mode_iterator BFHF [BF HF])
>  
>  ;; Iterator for floating-point modes that can be loaded into X registers.
> -(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
> +(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")
> +(BF "TARGET_ZFBFMIN")])
>  
>  
>  ;; ---
> @@ -76,27 +81,27 @@
>  (define_mode_attr size [(QI "b") (HI "h")])
>  
>  ;; Mode attributes for loads.
> -(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (HF "flh") 
> (SF "flw") (DF "fld")])
> +(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (BF "flh") 
> (HF "flh") (SF "flw") (DF "fld")])
>  
>  ;; Instruction names for integer loads that aren't explicitly sign or zero
>  ;; extended.  See riscv_output_move and LOAD_EXTEND_OP.
>  (define_mode_attr default_load [(QI "lbu") (HI "lhu") (SI "lw") (DI "ld")])
>  
>  ;; Mode attribute for FP loads into integer registers.
> -(define_mode_attr softload [(HF "lh") (SF "lw") (DF "ld")])
> +(define_mode_attr softload [(BF "lh") (HF "lh") (SF "lw") (DF "ld")])
>  
>  ;; Instruction names for stores.
> -(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (HF "fsh") 
> (SF "fsw") (DF "fsd")])
> +(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (BF "fsh") 
> (HF "fsh") (SF "fsw") (DF "fsd")])
>  
>  ;; Instruction names for FP stores from integer registers.
> -(define_mode_attr softstore [(HF "sh") (SF "sw") (DF "sd")])
> +(define_mode_attr softstore [(BF "sh") (HF "sh") (SF "sw") (DF "sd")])
>  
>  ;; This attribute gives the best constraint to use for registers of
>  ;; a given mode.
>  (define_mode_attr reg [(SI "d") (DI "d") (CC "d")])
>  
>  ;; This attribute gives the format suffix for floating-point operations.
> -(define_mode_attr fmt [(HF "h") (SF "s") (DF "d")])
> +(define_mode_attr fmt [(BF "h") (HF "h") (SF "s") (DF "d")])
>  
>  ;; This attribute gives the integer suffix for floating-point conversions.
>  (define_mode_attr ifmt [(SI "w") (DI "l")])
> @@ -106,7 +111,7 @@
>  
>  ;; This attribute gives the upper-case mode name for one unit of a
>  ;; floating-point mode.
> -(define_mode_attr UNITMODE [(HF "HF") (SF "SF") (DF "DF")])
> +(define_mode_attr UNITMODE [(BF "BF") (HF "HF") (SF "SF") (DF "DF")])
>  

There are also some problems here, which cannot be simply handled like HF. 
Many instructions support HF but do not support BF. For example, fadd.h
can be used for HF but cannot be used for BF. 

I guess it may need to be converted to SF first, then fadd.s, and finally
converted to BF.  I'm not so sure.

Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Jin Ma via Gcc-patches]

> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index ebc1ed7d7e4..2b3ff1f5b8e 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -102,6 +102,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
> {"zvl32768b", "zvl16384b"},
> {"zvl65536b", "zvl32768b"},
> 
> + {"zfbfmin", "zfhmin"},
> +
> {"zfh", "zfhmin"},
> {"zfhmin", "f"},
> 
> @@ -1239,6 +1241,8 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
> {"zvl16384b", _options::x_riscv_zvl_flags, MASK_ZVL16384B},
> {"zvl32768b", _options::x_riscv_zvl_flags, MASK_ZVL32768B},
> {"zvl65536b", _options::x_riscv_zvl_flags, MASK_ZVL65536B},
> + 
> + {"zfbfmin", _options::x_riscv_zf_subext, MASK_ZFBFMIN},
> 
> {"zfhmin", _options::x_riscv_zf_subext, MASK_ZFHMIN},
> {"zfh", _options::x_riscv_zf_subext, MASK_ZFH},
As kito says, there is no version information for the extension.
> diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
> index 5b70ab20758..6349f032bc8 100644
> --- a/gcc/config/riscv/iterators.md
> +++ b/gcc/config/riscv/iterators.md
> @@ -61,10 +61,15 @@
> ;; Iterator for hardware-supported floating-point modes.
> (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
> (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
> - (HF "TARGET_ZFH || TARGET_ZHINX")])
> + (HF "TARGET_ZFH || TARGET_ZHINX") 
> + (BF "TARGET_ZFBFMIN")])
> +
> +;; Iterator for HImode constant generation.
> +(define_mode_iterator BFHF [BF HF])
> 
> ;; Iterator for floating-point modes that can be loaded into X registers.
> -(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
> +(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")
> + (BF "TARGET_ZFBFMIN")])
> 
> 
> ;; ---
> @@ -76,27 +81,27 @@
> (define_mode_attr size [(QI "b") (HI "h")])
> 
> ;; Mode attributes for loads.
> -(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (HF "flh") 
> (SF "flw") (DF "fld")])
> +(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (BF "flh") 
> (HF "flh") (SF "flw") (DF "fld")])
> 
> ;; Instruction names for integer loads that aren't explicitly sign or zero
> ;; extended. See riscv_output_move and LOAD_EXTEND_OP.
> (define_mode_attr default_load [(QI "lbu") (HI "lhu") (SI "lw") (DI "ld")])
> 
> ;; Mode attribute for FP loads into integer registers.
> -(define_mode_attr softload [(HF "lh") (SF "lw") (DF "ld")])
> +(define_mode_attr softload [(BF "lh") (HF "lh") (SF "lw") (DF "ld")])
> 
> ;; Instruction names for stores.
> -(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (HF "fsh") 
> (SF "fsw") (DF "fsd")])
> +(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd") (BF "fsh") 
> (HF "fsh") (SF "fsw") (DF "fsd")])
> 
> ;; Instruction names for FP stores from integer registers.
> -(define_mode_attr softstore [(HF "sh") (SF "sw") (DF "sd")])
> +(define_mode_attr softstore [(BF "sh") (HF "sh") (SF "sw") (DF "sd")])
> 
> ;; This attribute gives the best constraint to use for registers of
> ;; a given mode.
> (define_mode_attr reg [(SI "d") (DI "d") (CC "d")])
> 
> ;; This attribute gives the format suffix for floating-point operations.
> -(define_mode_attr fmt [(HF "h") (SF "s") (DF "d")])
> +(define_mode_attr fmt [(BF "h") (HF "h") (SF "s") (DF "d")])
> 
> ;; This attribute gives the integer suffix for floating-point conversions.
> (define_mode_attr ifmt [(SI "w") (DI "l")])
> @@ -106,7 +111,7 @@
> 
> ;; This attribute gives the upper-case mode name for one unit of a
> ;; floating-point mode.
> -(define_mode_attr UNITMODE [(HF "HF") (SF "SF") (DF "DF")])
> +(define_mode_attr UNITMODE [(BF "BF") (HF "HF") (SF "SF") (DF "DF")])
> 
> ;; This attribute gives the integer mode that has half the size of
> ;; the controlling mode.
> diff --git a/gcc/config/riscv/riscv-builtins.cc 
> b/gcc/config/riscv/riscv-builtins.cc
> index 25ca407f9a9..e0c6f6834a5 100644
> --- a/gcc/config/riscv/riscv-builtins.cc
> +++ b/gcc/config/riscv/riscv-builtins.cc
> @@ -163,6 +163,7 @@ static GTY(()) int 
> riscv_builtin_decl_index[NUM_INSN_CODES];
> riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]]
> 
> tree riscv_float16_type_node = NULL_TREE;
> +tree riscv_bfloat16_type_node = NULL_TREE;
> 
> /* Return the function type associated with function prototype TYPE. */
> 
> @@ -190,7 +191,7 @@ riscv_build_function_type (enum riscv_function_type type)
> }
> 
> static void
> -riscv_init_builtin_types (void)
> +riscv_fp16_builtin_type (void)
> {
> /* Provide the _Float16 type and float16_type_node if needed. */
> if (!float16_type_node)
> @@ -208,6 +209,32 @@ riscv_init_builtin_types (void)
> "_Float16");
> }
> 
> +static void
> +riscv_bf16_builtin_type (void)
> +{
> + /* Provide the _bf16 type and bfloat16_type_node if needed. */
> + if (!bfloat16_type_node)
> + {
> + riscv_bfloat16_type_node = make_node (REAL_TYPE);

Re: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Jeff Law via Gcc-patches]

On 6/1/23 10:56, Palmer Dabbelt wrote:

On Thu, 01 Jun 2023 09:48:47 PDT (-0700), jeffreya...@gmail.com wrote:



On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote:

I plan to implement BF16 vector in GCC but still waiting for ISA
ratified since GCC policy doesn't allow un-ratified ISA.

Right.  So those specs need to move along further before we can start
integrating code.



Currently, we are working on INT8,INT16,INT32,INT64,FP16,FP32,FP64
auto-vectorizaiton.
It should very simple BF16 in current vector framework in GCC.

In prior architectures I've worked on the bulk of BF16 work was just
adding additional entries to existing iterators.  So I agree, it should
be very simple :-)


We should also have someone who's a bit more plugged in to floating 
point check to make sure the RISC-V bfloat16 semantics match IEEE.  I 
don't see any issues, but I'm not really a FP person so I'm not sure. 
There were certainly a lot of subtlies for the other FP bits, so even if 
the implementation just plumbs straight through IMO it's worth checking.


We have one FP person at Rivos, I can try and rope him in if you want? 
Happy to have someone else do it, though, as he's usually pretty busy ;)
I don't really have an FP expert here.  I can't honestly pretend to be 
one myself.


jeff

Re: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Philipp Tomsich]

On Thu, 1 Jun 2023 at 18:49, Jeff Law via Gcc-patches
 wrote:
>
>
>
> On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote:
> > I plan to implement BF16 vector in GCC but still waiting for ISA
> > ratified since GCC policy doesn't allow un-ratified ISA.
> Right.  So those specs need to move along further before we can start
> integrating code.

Doesn't our policy require specs to only pass the FREEZE milestone
(i.e., the requirement for public review) before we can start
integrating them?
This should give us at least a 6 week (minimum 30 days public-review
plus 2 weeks for the TSC vote to send this up for ratification)
headstart on ratification (with the small risk of minor changes
required due to review comments) to start integrating support for new
extensions.

Best,
Philipp.

p.s.: Just for reference, the RISC-V Lifecycle Guide (defining these
milestones in specification development) is linked from
https://wiki.riscv.org/ for details.


> >
> > Currently, we are working on INT8,INT16,INT32,INT64,FP16,FP32,FP64
> > auto-vectorizaiton.
> > It should very simple BF16 in current vector framework in GCC.
> In prior architectures I've worked on the bulk of BF16 work was just
> adding additional entries to existing iterators.  So I agree, it should
> be very simple :-)
>
> Jeff
>

Re: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Palmer Dabbelt]

On Thu, 01 Jun 2023 09:48:47 PDT (-0700), jeffreya...@gmail.com wrote:



On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote:

I plan to implement BF16 vector in GCC but still waiting for ISA
ratified since GCC policy doesn't allow un-ratified ISA.

Right.  So those specs need to move along further before we can start
integrating code.



Currently, we are working on INT8,INT16,INT32,INT64,FP16,FP32,FP64
auto-vectorizaiton.
It should very simple BF16 in current vector framework in GCC.

In prior architectures I've worked on the bulk of BF16 work was just
adding additional entries to existing iterators.  So I agree, it should
be very simple :-)


We should also have someone who's a bit more plugged in to floating 
point check to make sure the RISC-V bfloat16 semantics match IEEE.  I 
don't see any issues, but I'm not really a FP person so I'm not sure.  
There were certainly a lot of subtlies for the other FP bits, so even if 
the implementation just plumbs straight through IMO it's worth checking.


We have one FP person at Rivos, I can try and rope him in if you want?  
Happy to have someone else do it, though, as he's usually pretty busy ;)

Re: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Jeff Law via Gcc-patches]

On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote:
I plan to implement BF16 vector in GCC but still waiting for ISA 
ratified since GCC policy doesn't allow un-ratified ISA.
Right.  So those specs need to move along further before we can start 
integrating code.




Currently, we are working on INT8,INT16,INT32,INT64,FP16,FP32,FP64 
auto-vectorizaiton.

It should very simple BF16 in current vector framework in GCC.
In prior architectures I've worked on the bulk of BF16 work was just 
adding additional entries to existing iterators.  So I agree, it should 
be very simple :-)


Jeff

Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Liao Shihua]

Hi, Ma Jin

    1. There are few developments since May in GCC because the spec of 
Zfbf  is constantly changing.


    2. We (PLCT lab) will implement Zvfbfmin and Zvfbfwma after Zvfh 
has been merged in GCC.


    3. I will send a patch to support bfloat16_t in RISC-V port, but 
Zfbf extension's patch will be sent after it released.


Liao Shihua

在 2023/6/1 14:51, Jin Ma 写道:

hi,

Are there any new developments about Zfb? Are there any plans to implement
the Zvfbfmin and Zvfbfwma expansion? I see that Zfb is being reviewed in
llvm, maybe we should do the same on gcc.

Ref:https://reviews.llvm.org/D151313
  https://reviews.llvm.org/D150929

Re: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[juzhe.zh...@rivai.ai]

I plan to implement BF16 vector in GCC but still waiting for ISA ratified since 
GCC policy doesn't allow un-ratified ISA.

Currently, we are working on INT8,INT16,INT32,INT64,FP16,FP32,FP64 
auto-vectorizaiton.
It should very simple BF16 in current vector framework in GCC.

Thanks.


juzhe.zh...@rivai.ai
 
From: Li, Pan2
Date: 2023-06-01 14:57
To: juzhe.zh...@rivai.ai
Subject: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 
in riscv like x86_64 and arm.
FYI.
 
-Original Message-
From: Gcc-patches  On Behalf 
Of Jin Ma via Gcc-patches
Sent: Thursday, June 1, 2023 2:51 PM
To: gcc-patches@gcc.gnu.org
Cc: shi...@iscas.ac.cn; kito.ch...@gmail.com; Jin Ma 
Subject: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in 
riscv like x86_64 and arm.
 
hi, 
 
Are there any new developments about Zfb? Are there any plans to implement the 
Zvfbfmin and Zvfbfwma expansion? I see that Zfb is being reviewed in llvm, 
maybe we should do the same on gcc.
 
Ref: https://reviews.llvm.org/D151313
 https://reviews.llvm.org/D150929
 

[RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Jin Ma via Gcc-patches]

hi, 

Are there any new developments about Zfb? Are there any plans to implement
the Zvfbfmin and Zvfbfwma expansion? I see that Zfb is being reviewed in
llvm, maybe we should do the same on gcc.

Ref: https://reviews.llvm.org/D151313
 https://reviews.llvm.org/D150929

Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Kito Cheng via Gcc-patches]

Hi ShiHua:

Thanks for your contribution to the zfbfmin extension :)

General comments:
- Add zfbfmin to riscv_ext_version_table
- Add test case to verify the -march is accepted.
- Add testcase to test argument passing.
- Add testcase for operations.
- Add testcase for compares.

> +(define_insn "*movbf_softfloat"
> +  [(set (match_operand:BF 0 "nonimmediate_operand" "=f, r,r,m,*f,*r")
> +   (match_operand:BF 1 "move_operand" " f,Gr,m,r,*r,*f"))]
> +  "!TARGET_ZFHMIN

Should be TARGET_ZFBFMIN?

> @@ -3192,7 +3192,11 @@ riscv_emit_float_compare (enum rtx_code *code, rtx 
> *op0, rtx *op1)
>else if (GET_MODE (cmp_op0) == HFmode && TARGET_64BIT)   \
> emit_insn (gen_f##CMP##_quiethfdi4 (*op0, cmp_op0, cmp_op1));   \
>else if (GET_MODE (cmp_op0) == HFmode)   \
> -   emit_insn (gen_f##CMP##_quiethfsi4 (*op0, cmp_op0, cmp_op1));   \
> +   emit_insn (gen_f##CMP##_quietbfsi4 (*op0, cmp_op0, cmp_op1));   \
> +  else if (GET_MODE (cmp_op0) == BFmode && TARGET_64BIT)   \
> +   emit_insn (gen_f##CMP##_quietbfdi4 (*op0, cmp_op0, cmp_op1));   \
> +  else if (GET_MODE (cmp_op0) == BFmode)   \
> +   emit_insn (gen_f##CMP##_quietbfsi4 (*op0, cmp_op0, cmp_op1));   \
>else \
> gcc_unreachable (); \
>*op1 = const0_rtx;   \

Do we really need this? I thought we'll always promote to SF before
they compare?

[RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

[Liao Shihua]

   According to https://github.com/riscv/riscv-bfloat16 , zfbfmin extension 
depends on zfh/zfhmin extension.

   According to the discussion 
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367, this use __bf16 
and use DF16b in riscv_mangle_type like x86.


gcc\ChangeLog:

* common/config/riscv/riscv-common.cc: Add ZFBFMIN extension.
* config/riscv/iterators.md (TARGET_ZFHMIN):Add iterator BF.
(fld):Likewise.
(ld):Likewise
(fsd):Likewise
(sd):Likewise
(d):Likewise
(DF):Likewise
* config/riscv/riscv-builtins.cc (riscv_init_builtin_types): Add 
bfloat16 type in riscv .
(riscv_fp16_builtin_type):Likewise
(riscv_bf16_builtin_type):Likewise
* config/riscv/riscv-modes.def (FLOAT_MODE):Likewise
(ADJUST_FLOAT_FORMAT):Likewise
* config/riscv/riscv-opts.h (MASK_ZFBFMIN):Add ZFBFMIN extension.
(TARGET_ZFBFMIN):
* config/riscv/riscv-vector-switch.def (ENTRY):
* config/riscv/riscv.cc (riscv_emit_float_compare):Add bfloat16 type in 
riscv .
(riscv_mangle_type):
(riscv_scalar_mode_supported_p):
(riscv_libgcc_floating_mode_supported_p):
(riscv_init_libfuncs):
* config/riscv/riscv.md (mode" ):Add bfloat16 type in riscv .
(truncdfhf2):
(truncsfbf2):
(truncdf2):
(extendbfsf2):
(extendhfdf2):
(extenddf2):
(movbf):
(*movbf_hardfloat):
(*movbf_softfloat):

libgcc\ChangeLog:

* config/riscv/sfp-machine.h (_FP_NANFRAC_B):Add bfloat16 type in riscv 
.
(_FP_NANSIGN_B):
* config/riscv/t-softfp32:

---
 gcc/common/config/riscv/riscv-common.cc  |  4 ++
 gcc/config/riscv/iterators.md| 21 +---
 gcc/config/riscv/riscv-builtins.cc   | 29 +-
 gcc/config/riscv/riscv-modes.def |  2 +
 gcc/config/riscv/riscv-opts.h|  2 +
 gcc/config/riscv/riscv-vector-switch.def |  4 +-
 gcc/config/riscv/riscv.cc| 37 +++--
 gcc/config/riscv/riscv.md| 69 
 libgcc/config/riscv/sfp-machine.h|  3 ++
 libgcc/config/riscv/t-softfp32   |  8 +--
 10 files changed, 150 insertions(+), 29 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index ebc1ed7d7e4..2b3ff1f5b8e 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -102,6 +102,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zvl32768b", "zvl16384b"},
   {"zvl65536b", "zvl32768b"},
 
+  {"zfbfmin", "zfhmin"},
+
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
   
@@ -1239,6 +1241,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl16384b", _options::x_riscv_zvl_flags, MASK_ZVL16384B},
   {"zvl32768b", _options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", _options::x_riscv_zvl_flags, MASK_ZVL65536B},
+  
+  {"zfbfmin",_options::x_riscv_zf_subext, MASK_ZFBFMIN},
 
   {"zfhmin",_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   _options::x_riscv_zf_subext, MASK_ZFH},
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 5b70ab20758..6349f032bc8 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -61,10 +61,15 @@
 ;; Iterator for hardware-supported floating-point modes.
 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
(DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
-   (HF "TARGET_ZFH || TARGET_ZHINX")])
+   (HF "TARGET_ZFH || TARGET_ZHINX") 
+   (BF "TARGET_ZFBFMIN")])
+
+;; Iterator for HImode constant generation.
+(define_mode_iterator BFHF [BF HF])
 
 ;; Iterator for floating-point modes that can be loaded into X registers.
-(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
+(define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")
+   (BF "TARGET_ZFBFMIN")])
 
 
 ;; ---
@@ -76,27 +81,27 @@
 (define_mode_attr size [(QI "b") (HI "h")])
 
 ;; Mode attributes for loads.
-(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (HF "flh") (SF 
"flw") (DF "fld")])
+(define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (BF "flh") (HF 
"flh") (SF "flw") (DF "fld")])
 
 ;; Instruction names for integer loads that aren't explicitly sign or zero
 ;; extended.  See riscv_output_move and LOAD_EXTEND_OP.
 (define_mode_attr default_load [(QI "lbu") (HI "lhu") (SI "lw") (DI "ld")])
 
 ;; Mode attribute for FP loads into integer registers.
-(define_mode_attr softload [(HF "lh") (SF "lw") (DF "ld")])
+(define_mode_attr softload [(BF "lh") (HF "lh") (SF "lw") (DF "ld")])
 
 ;; Instruction names for stores.
-(define_mode_attr store [(QI "sb")