On Mon, Mar 26, 2012 at 7:47 AM, H.J. Lu hjl.to...@gmail.com wrote:
On Mon, Mar 26, 2012 at 4:53 AM, Joseph S. Myers
jos...@codesourcery.com wrote:
On Sun, 25 Mar 2012, H.J. Lu wrote:
Hi Joseph,
I need to support InverseMask(XXX) in options without the corresponding
Mask(XXX) since XXX is never set directly via a command line option. This
patch adds a MaskNeeded property which turns InverseMask(XXX) into
the inverse version of Mask(XXX), which allocates a unique bit and defines
the same set of macros as Mask(XXX). Does it look OK?
I'd have thought that either Mask or InverseMask with a given mask name
(or a standalone target mask record) should cause allocation (only once,
no matter how many options use the same mask name), and MaskExists should
be removed, rather than adding MaskNeeded - if I understood correctly the
purpose for which you are adding MaskNeeded.
That is correct. I will work on a patch to remove MaskExists.
Here is a patch to remove MaskExists. The difference between the old
options.h and the new options.h on Linux/x86-64 are
--- /tmp/options.h 2012-03-26 09:49:09.590137047 -0700
+++ ./options.h 2012-03-26 10:07:56.940168938 -0700
@@ -3677,55 +3677,55 @@ extern void cl_target_option_print (FILE
#endif
#define MASK_128BIT_LONG_DOUBLE (1 0)
-#define OPTION_MASK_ISA_3DNOW (HOST_WIDE_INT_1 0)
-#define OPTION_MASK_ISA_3DNOW_A (HOST_WIDE_INT_1 1)
-#define OPTION_MASK_ISA_64BIT (HOST_WIDE_INT_1 2)
+#define OPTION_MASK_ISA_64BIT (HOST_WIDE_INT_1 0)
+#define OPTION_MASK_ISA_3DNOW (HOST_WIDE_INT_1 1)
+#define OPTION_MASK_ISA_3DNOW_A (HOST_WIDE_INT_1 2)
#define MASK_80387 (1 1)
#define MASK_USE_8BIT_IDIV (1 2)
#define OPTION_MASK_ISA_ABM (HOST_WIDE_INT_1 3)
#define MASK_ACCUMULATE_OUTGOING_ARGS (1 3)
#define OPTION_MASK_ISA_AES (HOST_WIDE_INT_1 4)
#define MASK_ALIGN_DOUBLE (1 4)
+#define MASK_NO_ALIGN_STRINGOPS (1 5)
#define OPTION_MASK_ANDROID (1 0)
#define OPTION_MASK_ISA_AVX (HOST_WIDE_INT_1 5)
#define OPTION_MASK_ISA_AVX2 (HOST_WIDE_INT_1 6)
-#define MASK_AVX256_SPLIT_UNALIGNED_LOAD (1 5)
-#define MASK_AVX256_SPLIT_UNALIGNED_STORE (1 6)
+#define MASK_AVX256_SPLIT_UNALIGNED_LOAD (1 6)
+#define MASK_AVX256_SPLIT_UNALIGNED_STORE (1 7)
#define OPTION_MASK_ISA_BMI (HOST_WIDE_INT_1 7)
#define OPTION_MASK_ISA_BMI2 (HOST_WIDE_INT_1 8)
-#define MASK_CLD (1 7)
+#define MASK_CLD (1 8)
#define OPTION_MASK_ISA_CRC32 (HOST_WIDE_INT_1 9)
#define OPTION_MASK_ISA_CX16 (HOST_WIDE_INT_1 10)
#define OPTION_MASK_ISA_F16C (HOST_WIDE_INT_1 11)
+#define MASK_NO_FANCY_MATH_387 (1 9)
#define OPTION_MASK_ISA_FMA (HOST_WIDE_INT_1 12)
#define OPTION_MASK_ISA_FMA4 (HOST_WIDE_INT_1 13)
-#define MASK_FLOAT_RETURNS (1 8)
+#define MASK_FLOAT_RETURNS (1 10)
#define OPTION_MASK_ISA_FSGSBASE (HOST_WIDE_INT_1 14)
-#define MASK_IEEE_FP (1 9)
-#define MASK_INLINE_ALL_STRINGOPS (1 10)
-#define MASK_INLINE_STRINGOPS_DYNAMICALLY (1 11)
+#define MASK_IEEE_FP (1 11)
+#define MASK_INLINE_ALL_STRINGOPS (1 12)
+#define MASK_INLINE_STRINGOPS_DYNAMICALLY (1 13)
#define OPTION_MASK_ISA_LWP (HOST_WIDE_INT_1 15)
#define OPTION_MASK_ISA_LZCNT (HOST_WIDE_INT_1 16)
#define OPTION_MASK_ISA_MMX (HOST_WIDE_INT_1 17)
#define OPTION_MASK_ISA_MOVBE (HOST_WIDE_INT_1 18)
-#define MASK_MS_BITFIELD_LAYOUT (1 12)
-#define MASK_NO_ALIGN_STRINGOPS (1 13)
-#define MASK_NO_FANCY_MATH_387 (1 14)
+#define MASK_MS_BITFIELD_LAYOUT (1 14)
#define MASK_NO_PUSH_ARGS (1 15)
#define MASK_NO_RED_ZONE (1 16)
+#define OPTION_MASK_ISA_SSE4_1 (HOST_WIDE_INT_1 19)
#define MASK_OMIT_LEAF_FRAME_POINTER (1 17)
-#define OPTION_MASK_ISA_PCLMUL (HOST_WIDE_INT_1 19)
-#define OPTION_MASK_ISA_POPCNT (HOST_WIDE_INT_1 20)
+#define OPTION_MASK_ISA_PCLMUL (HOST_WIDE_INT_1 20)
+#define OPTION_MASK_ISA_POPCNT (HOST_WIDE_INT_1 21)
#define MASK_PREFER_AVX128 (1 18)
-#define OPTION_MASK_ISA_RDRND (HOST_WIDE_INT_1 21)
+#define OPTION_MASK_ISA_RDRND (HOST_WIDE_INT_1 22)
#define MASK_RECIP (1 19)
#define MASK_RTD (1 20)
-#define OPTION_MASK_ISA_RTM (HOST_WIDE_INT_1 22)
-#define OPTION_MASK_ISA_SAHF (HOST_WIDE_INT_1 23)
-#define OPTION_MASK_ISA_SSE (HOST_WIDE_INT_1 24)
-#define OPTION_MASK_ISA_SSE2 (HOST_WIDE_INT_1 25)
-#define OPTION_MASK_ISA_SSE3 (HOST_WIDE_INT_1 26)
-#define OPTION_MASK_ISA_SSE4_1 (HOST_WIDE_INT_1 27)
+#define OPTION_MASK_ISA_RTM (HOST_WIDE_INT_1 23)
+#define OPTION_MASK_ISA_SAHF (HOST_WIDE_INT_1 24)
+#define OPTION_MASK_ISA_SSE (HOST_WIDE_INT_1 25)
+#define OPTION_MASK_ISA_SSE2 (HOST_WIDE_INT_1 26)
+#define OPTION_MASK_ISA_SSE3 (HOST_WIDE_INT_1 27)
#define OPTION_MASK_ISA_SSE4_2 (HOST_WIDE_INT_1 28)
#define OPTION_MASK_ISA_SSE4A (HOST_WIDE_INT_1 29)
#define MASK_SSEREGPARM (1 21)
@@ -3742,15 +3742,16 @@ extern void cl_target_option_print (FILE
#endif
#define TARGET_128BIT_LONG_DOUBLE ((target_flags
MASK_128BIT_LONG_DOUBLE) != 0)
+#define OPTION_ISA_64BIT ((ix86_isa_flags OPTION_MASK_ISA_64BIT) != 0)
#define OPTION_ISA_3DNOW
