On Mon, 2021-04-26 at 09:35 -0700, Carl Love wrote:
> Will, Segher:
>
> This patch fixes the order of the argument in the vec_rlmi and
> vec_rlnm builtins. The patch also adds a new test cases to verify
> the fix.
>
> The patch has been tested on
> powerpc64-linux instead (Power 8 BE)
> powerpc64-linux instead (Power 9 LE)
> powerpc64-linux instead (Power 10 LE)
>
> Please let me know if the patch is acceptable for mainline.
>
>Carl Love
Hi,
Is there an existing PR for this one?
The subject line does not reflect this patch.
subject: Re: [PATCH 1/5 ver4] RS6000: Add 128-bit Integer Operations
>
>
>
> 2021-04-26 Carl Love
>
> gcc/
> * config/rs6000/altivec.md (altivec_vrlmi): Fix
> bug in argument generation.
>
> gcc/testsuite/
> gcc.target/powerpc/check-builtin-vec_rlnm-runnable.c:
> New runnable test case.
> gcc.target/powerpc/vec-rlmi-rlnm.c: Update scan assembler times
> for xxlor instruction.
Need leading "*" on the file names above.
> ---
> gcc/config/rs6000/altivec.md | 6 +-
> .../powerpc/check-builtin-vec_rlnm-runnable.c | 231 ++
> .../gcc.target/powerpc/vec-rlmi-rlnm.c| 2 +-
> 3 files changed, 235 insertions(+), 4 deletions(-)
> create mode 100644
> gcc/testsuite/gcc.target/powerpc/check-builtin-vec_rlnm-runnable.c
>
> diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
> index 1351dafbc41..97dc9d2bda9 100644
> --- a/gcc/config/rs6000/altivec.md
> +++ b/gcc/config/rs6000/altivec.md
> @@ -1987,12 +1987,12 @@
>
> (define_insn "altivec_vrlmi"
>[(set (match_operand:VIlong 0 "register_operand" "=v")
> -(unspec:VIlong [(match_operand:VIlong 1 "register_operand" "0")
> - (match_operand:VIlong 2 "register_operand" "v")
> +(unspec:VIlong [(match_operand:VIlong 1 "register_operand" "v")
> + (match_operand:VIlong 2 "register_operand" "0")
> (match_operand:VIlong 3 "register_operand" "v")]
> UNSPEC_VRLMI))]
>"TARGET_P9_VECTOR"
> - "vrlmi %0,%2,%3"
> + "vrlmi %0,%1,%3"
>[(set_attr "type" "veclogical")])
ok
>
> (define_insn "altivec_vrlnm"
> diff --git
> a/gcc/testsuite/gcc.target/powerpc/check-builtin-vec_rlnm-runnable.c
> b/gcc/testsuite/gcc.target/powerpc/check-builtin-vec_rlnm-runnable.c
> new file mode 100644
> index 000..be8f82d8a06
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/check-builtin-vec_rlnm-runnable.c
> @@ -0,0 +1,231 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-options "-O2 -mdejagnu-cpu=power9 -save-temps" } */
> +
> +/* Verify the vec_rlm and vec_rlmi builtins works correctly. */
> +/* { dg-final { scan-assembler-times {\mvrldmi\M} 1 } } */
> +
> +#include
> +
> +#ifdef DEBUG
> +#include
> +#include
> +#endif
> +
> +void abort (void);
> +
> +int main ()
> +{
> + int i;
> +
> + vector unsigned int vec_arg1_int, vec_arg2_int, vec_arg3_int;
> + vector unsigned int vec_result_int, vec_expected_result_int;
> +
> + vector unsigned long long int vec_arg1_di, vec_arg2_di, vec_arg3_di;
> + vector unsigned long long int vec_result_di, vec_expected_result_di;
> +
> + unsigned int mask_begin, mask_end, shift;
> + unsigned long long int mask;
> +
> +/* Check vec int version of vec_rlmi builtin */
> + mask = 0;
> + mask_begin = 0;
> + mask_end = 4;
> + shift = 16;
> +
> + for (i = 0; i < 31; i++)
> +if ((i >= mask_begin) && (i <= mask_end))
> + mask |= 0x8000ULL >> i;
> +
> + for (i = 0; i < 4; i++) {
> +vec_arg1_int[i] = 0x12345678 + i*0x;
> +vec_arg2_int[i] = 0xA1B1CDEF;
> +vec_arg3_int[i] = mask_begin << 16 | mask_end << 8 | shift;
> +
> +/* do rotate */
> +vec_expected_result_int[i] = ( vec_arg2_int[i] & ~mask)
> + | ((vec_arg1_int[i] << shift) | (vec_arg1_int[i] >> (32-shift))) &
> mask;
> +
> + }
> +
> + /* vec_rlmi(arg1, arg2, arg3)
> + result - rotate each element of arg2 left and inserting it into arg1
> + element based on the mask specified in arg3. The shift, mask
> + start and end is specified in arg3. */
> + vec_result_int = vec_rlmi (vec_arg1_int, vec_arg2_int, vec_arg3
